From c4f583e39fda30851908905ba4f2451fc42bab4f Mon Sep 17 00:00:00 2001
From: Kirill Mikhailov <konnor1980@yandex.ru>
Date: Thu, 14 Nov 2024 08:20:06 +0100
Subject: [PATCH] get rid of `get_` prefix

---
 esp-hal/src/interrupt/riscv.rs       | 8 ++++----
 esp-hal/src/soc/esp32p4/efuse/mod.rs | 4 ++--
 esp-hal/src/soc/esp32p4/gpio.rs      | 4 ++--
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/esp-hal/src/interrupt/riscv.rs b/esp-hal/src/interrupt/riscv.rs
index 84e539e6dc7..fd5fdbda81a 100644
--- a/esp-hal/src/interrupt/riscv.rs
+++ b/esp-hal/src/interrupt/riscv.rs
@@ -831,7 +831,7 @@ mod clic {
     /// Get pointer to interrupt control register for the given core and CPU
     /// interrupt number
     fn intr_cntrl(core: Cpu, cpu_interrupt_number: usize) -> *mut u32 {
-        let offset = if core == crate::get_core() {
+        let offset = if core == crate::core() {
             0
         } else {
             DUALCORE_CLIC_CTRL_OFF
@@ -850,7 +850,7 @@ mod clic {
     /// Make sure there is an interrupt handler registered.
     pub unsafe fn enable_cpu_interrupt(which: CpuInterrupt) {
         let cpu_interrupt_number = which as usize;
-        let intr_cntrl = intr_cntrl(crate::get_core(), cpu_interrupt_number);
+        let intr_cntrl = intr_cntrl(crate::core(), cpu_interrupt_number);
 
         unsafe {
             let mut val = InterruptControl(intr_cntrl.read_volatile());
@@ -910,7 +910,7 @@ mod clic {
 
     /// Get interrupt priority
     #[inline]
-    pub(super) fn get_priority_by_core(core: Cpu, cpu_interrupt: CpuInterrupt) -> Priority {
+    pub(super) fn priority_by_core(core: Cpu, cpu_interrupt: CpuInterrupt) -> Priority {
         let cpu_interrupt_number = cpu_interrupt as usize;
 
         unsafe {
@@ -923,7 +923,7 @@ mod clic {
 
     /// Get interrupt priority - called by assembly code
     #[inline]
-    pub(super) unsafe extern "C" fn get_priority(cpu_interrupt: CpuInterrupt) -> Priority {
+    pub(super) unsafe extern "C" fn priority(cpu_interrupt: CpuInterrupt) -> Priority {
         let clic = &*crate::peripherals::CLIC::PTR;
         let prio = clic
             .int_ctrl(cpu_interrupt as usize)
diff --git a/esp-hal/src/soc/esp32p4/efuse/mod.rs b/esp-hal/src/soc/esp32p4/efuse/mod.rs
index 84688fea2ab..fcc49670ae0 100644
--- a/esp-hal/src/soc/esp32p4/efuse/mod.rs
+++ b/esp-hal/src/soc/esp32p4/efuse/mod.rs
@@ -57,12 +57,12 @@ impl Efuse {
     }
 
     /// Get status of SPI boot encryption.
-    pub fn get_flash_encryption() -> bool {
+    pub fn flash_encryption() -> bool {
         todo!()
     }
 
     /// Get the multiplier for the timeout value of the RWDT STAGE 0 register.
-    pub fn get_rwdt_multiplier() -> u8 {
+    pub fn rwdt_multiplier() -> u8 {
         todo!()
     }
 }
diff --git a/esp-hal/src/soc/esp32p4/gpio.rs b/esp-hal/src/soc/esp32p4/gpio.rs
index 7b70027a084..86e6cd55bce 100644
--- a/esp-hal/src/soc/esp32p4/gpio.rs
+++ b/esp-hal/src/soc/esp32p4/gpio.rs
@@ -8,7 +8,7 @@
 //!
 //! Let's get through the functionality and configurations provided by this GPIO
 //! module:
-//!   - `get_io_mux_reg(gpio_num: u8) -> &'static
+//!   - `io_mux_reg(gpio_num: u8) -> &'static
 //!     crate::peripherals::io_mux::GPIO0:`:
 //!       * Returns the IO_MUX register for the specified GPIO pin number.
 //!   - `gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8`:
@@ -57,7 +57,7 @@ pub(crate) const ZERO_INPUT: u8 = 0x3e;
 
 pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function1;
 
-pub(crate) const fn get_io_mux_reg(gpio_num: u8) -> &'static crate::peripherals::io_mux::GPIO {
+pub(crate) const fn io_mux_reg(gpio_num: u8) -> &'static crate::peripherals::io_mux::GPIO {
     unsafe { (*crate::peripherals::IO_MUX::PTR).gpio(gpio_num as usize) }
 }