From f4e745dd502ef47bb0e367017f9a9a069e9a6da4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1niel=20Buga?= Date: Wed, 2 Oct 2024 15:11:27 +0200 Subject: [PATCH] Erase DMA type params --- esp-hal/src/aes/mod.rs | 53 ++-------- esp-hal/src/dma/gdma.rs | 87 +++++++++------- esp-hal/src/dma/pdma.rs | 2 +- esp-hal/src/i2s.rs | 155 ++++++++++++---------------- esp-hal/src/lcd_cam/cam.rs | 49 +++------ esp-hal/src/lcd_cam/lcd/i8080.rs | 33 +++--- esp-hal/src/parl_io.rs | 172 +++++++++++-------------------- esp-hal/src/spi/master.rs | 117 +++++++++------------ esp-hal/src/spi/slave.rs | 67 ++++++------ 9 files changed, 299 insertions(+), 436 deletions(-) diff --git a/esp-hal/src/aes/mod.rs b/esp-hal/src/aes/mod.rs index 8c56bb80353..d523f974621 100644 --- a/esp-hal/src/aes/mod.rs +++ b/esp-hal/src/aes/mod.rs @@ -241,7 +241,6 @@ pub mod dma { ChannelRx, ChannelTx, DescriptorChain, - DmaChannel, DmaDescriptor, DmaPeripheral, DmaTransferRxTx, @@ -272,14 +271,11 @@ pub mod dma { } /// A DMA capable AES instance. - pub struct AesDma<'d, C = AnyDmaChannel> - where - C: DmaChannel, - { + pub struct AesDma<'d> { /// The underlying [`Aes`](super::Aes) driver pub aes: super::Aes<'d>, - pub(crate) channel: Channel<'d, C, crate::Blocking>, + channel: Channel<'d, AnyDmaChannel, crate::Blocking>, rx_chain: DescriptorChain, tx_chain: DescriptorChain, } @@ -296,43 +292,23 @@ pub mod dma { Self: Sized, C: PeripheralDmaChannel, C::P: AesPeripheral, - { - self.with_dma_typed(channel.degrade(), rx_descriptors, tx_descriptors) - } - - /// Enable DMA for the current instance of the AES driver - pub fn with_dma_typed( - self, - channel: Channel<'d, C, crate::Blocking>, - rx_descriptors: &'static mut [DmaDescriptor], - tx_descriptors: &'static mut [DmaDescriptor], - ) -> AesDma<'d, C> - where - C: PeripheralDmaChannel, - C::P: AesPeripheral, { AesDma { aes: self, - channel, + channel: channel.degrade(), rx_chain: DescriptorChain::new(rx_descriptors), tx_chain: DescriptorChain::new(tx_descriptors), } } } - impl<'d, C> core::fmt::Debug for AesDma<'d, C> - where - C: DmaChannel, - { + impl<'d> core::fmt::Debug for AesDma<'d> { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { f.debug_struct("AesDma").finish() } } - impl<'d, C> DmaSupport for AesDma<'d, C> - where - C: DmaChannel, - { + impl<'d> DmaSupport for AesDma<'d> { fn peripheral_wait_dma(&mut self, _is_rx: bool, _is_tx: bool) { while self.aes.aes.state().read().state().bits() != 2 // DMA status DONE == 2 && !self.channel.tx.is_done() @@ -348,11 +324,8 @@ pub mod dma { } } - impl<'d, C> DmaSupportTx for AesDma<'d, C> - where - C: DmaChannel, - { - type TX = ChannelTx<'d, C>; + impl<'d> DmaSupportTx for AesDma<'d> { + type TX = ChannelTx<'d, AnyDmaChannel>; fn tx(&mut self) -> &mut Self::TX { &mut self.channel.tx @@ -363,11 +336,8 @@ pub mod dma { } } - impl<'d, C> DmaSupportRx for AesDma<'d, C> - where - C: DmaChannel, - { - type RX = ChannelRx<'d, C>; + impl<'d> DmaSupportRx for AesDma<'d> { + type RX = ChannelRx<'d, AnyDmaChannel>; fn rx(&mut self) -> &mut Self::RX { &mut self.channel.rx @@ -378,10 +348,7 @@ pub mod dma { } } - impl<'d, C> AesDma<'d, C> - where - C: DmaChannel, - { + impl<'d> AesDma<'d> { /// Writes the encryption key to the AES hardware, checking that its /// length matches expected constraints. pub fn write_key(&mut self, key: K) diff --git a/esp-hal/src/dma/gdma.rs b/esp-hal/src/dma/gdma.rs index 9eee9332388..869dbdb2bd4 100644 --- a/esp-hal/src/dma/gdma.rs +++ b/esp-hal/src/dma/gdma.rs @@ -709,21 +709,25 @@ pub use m2m::*; mod m2m { #[cfg(esp32s3)] use crate::dma::DmaExtMemBKSize; - use crate::dma::{ - dma_private::{DmaSupport, DmaSupportRx}, - Channel, - ChannelRx, - DescriptorChain, - DmaChannel, - DmaDescriptor, - DmaEligible, - DmaError, - DmaPeripheral, - DmaTransferRx, - ReadBuffer, - Rx, - Tx, - WriteBuffer, + use crate::{ + dma::{ + dma_private::{DmaSupport, DmaSupportRx}, + AnyDmaChannel, + Channel, + ChannelRx, + DescriptorChain, + DmaChannel, + DmaDescriptor, + DmaEligible, + DmaError, + DmaPeripheral, + DmaTransferRx, + ReadBuffer, + Rx, + Tx, + WriteBuffer, + }, + Mode, }; /// DMA Memory to Memory pseudo-Peripheral @@ -731,29 +735,30 @@ mod m2m { /// This is a pseudo-peripheral that allows for memory to memory transfers. /// It is not a real peripheral, but a way to use the DMA engine for memory /// to memory transfers. - pub struct Mem2Mem<'d, C, MODE> + pub struct Mem2Mem<'d, M> where - C: DmaChannel, - MODE: crate::Mode, + M: Mode, { - channel: Channel<'d, C, MODE>, + channel: Channel<'d, AnyDmaChannel, M>, rx_chain: DescriptorChain, tx_chain: DescriptorChain, peripheral: DmaPeripheral, } - impl<'d, C, MODE> Mem2Mem<'d, C, MODE> + impl<'d, M> Mem2Mem<'d, M> where - C: DmaChannel, - MODE: crate::Mode, + M: Mode, { /// Create a new Mem2Mem instance. - pub fn new( - channel: Channel<'d, C, MODE>, + pub fn new( + channel: Channel<'d, CH, M>, peripheral: impl DmaEligible, rx_descriptors: &'static mut [DmaDescriptor], tx_descriptors: &'static mut [DmaDescriptor], - ) -> Result { + ) -> Result + where + CH: DmaChannel, + { unsafe { Self::new_unsafe( channel, @@ -766,13 +771,16 @@ mod m2m { } /// Create a new Mem2Mem instance with specific chunk size. - pub fn new_with_chunk_size( - channel: Channel<'d, C, MODE>, + pub fn new_with_chunk_size( + channel: Channel<'d, CH, M>, peripheral: impl DmaEligible, rx_descriptors: &'static mut [DmaDescriptor], tx_descriptors: &'static mut [DmaDescriptor], chunk_size: usize, - ) -> Result { + ) -> Result + where + CH: DmaChannel, + { unsafe { Self::new_unsafe( channel, @@ -790,13 +798,16 @@ mod m2m { /// /// You must ensure that your not using DMA for the same peripheral and /// that your the only one using the DmaPeripheral. - pub unsafe fn new_unsafe( - channel: Channel<'d, C, MODE>, + pub unsafe fn new_unsafe( + channel: Channel<'d, CH, M>, peripheral: DmaPeripheral, rx_descriptors: &'static mut [DmaDescriptor], tx_descriptors: &'static mut [DmaDescriptor], chunk_size: usize, - ) -> Result { + ) -> Result + where + CH: DmaChannel, + { if !(1..=4092).contains(&chunk_size) { return Err(DmaError::InvalidChunkSize); } @@ -804,7 +815,7 @@ mod m2m { return Err(DmaError::OutOfDescriptors); } Ok(Mem2Mem { - channel, + channel: channel.degrade(), peripheral, rx_chain: DescriptorChain::new_with_chunk_size(rx_descriptors, chunk_size), tx_chain: DescriptorChain::new_with_chunk_size(tx_descriptors, chunk_size), @@ -855,10 +866,9 @@ mod m2m { } } - impl<'d, C, MODE> DmaSupport for Mem2Mem<'d, C, MODE> + impl<'d, MODE> DmaSupport for Mem2Mem<'d, MODE> where - C: DmaChannel, - MODE: crate::Mode, + MODE: Mode, { fn peripheral_wait_dma(&mut self, _is_rx: bool, _is_tx: bool) { while !self.channel.rx.is_done() {} @@ -869,12 +879,11 @@ mod m2m { } } - impl<'d, C, MODE> DmaSupportRx for Mem2Mem<'d, C, MODE> + impl<'d, MODE> DmaSupportRx for Mem2Mem<'d, MODE> where - C: DmaChannel, - MODE: crate::Mode, + MODE: Mode, { - type RX = ChannelRx<'d, C>; + type RX = ChannelRx<'d, AnyDmaChannel>; fn rx(&mut self) -> &mut Self::RX { &mut self.channel.rx diff --git a/esp-hal/src/dma/pdma.rs b/esp-hal/src/dma/pdma.rs index e362537787e..ed8654bd716 100644 --- a/esp-hal/src/dma/pdma.rs +++ b/esp-hal/src/dma/pdma.rs @@ -915,7 +915,7 @@ macro_rules! ImplI2sChannel { } fn set_isr(handler: InterruptHandler) { - let interrupt = $crate::peripherals::Interrupt::[< I2S $num >]; + let interrupt = $crate::peripherals::Interrupt::[< I2S $num >]; unsafe { crate::interrupt::bind_interrupt(interrupt, handler.handler()); } diff --git a/esp-hal/src/i2s.rs b/esp-hal/src/i2s.rs index 209d3e7689e..3e4cf7f90f9 100644 --- a/esp-hal/src/i2s.rs +++ b/esp-hal/src/i2s.rs @@ -89,6 +89,7 @@ use crate::dma::I2s1Peripheral; use crate::{ dma::{ dma_private::{DmaSupport, DmaSupportRx, DmaSupportTx}, + AnyDmaChannel, Channel, ChannelRx, ChannelTx, @@ -263,10 +264,9 @@ pub trait I2sWrite { } /// Initiate a DMA tx transfer -pub trait I2sWriteDma<'d, T, CH, TXBUF, DmaMode> +pub trait I2sWriteDma<'d, T, TXBUF, DmaMode> where T: RegisterAccess, - CH: DmaChannel, DmaMode: Mode, Self: DmaSupportTx + Sized, { @@ -295,10 +295,9 @@ pub trait I2sRead { } /// Initiate a DMA rx transfer -pub trait I2sReadDma<'d, T, CH, RXBUF, DmaMode> +pub trait I2sReadDma<'d, T, RXBUF, DmaMode> where T: RegisterAccess, - CH: DmaChannel, DmaMode: Mode, Self: DmaSupportRx + Sized, { @@ -321,27 +320,25 @@ where } /// Instance of the I2S peripheral driver -pub struct I2s<'d, I, CH, DmaMode> +pub struct I2s<'d, I, DmaMode> where I: RegisterAccess, - CH: DmaChannel, DmaMode: Mode, { /// Handles the reception (RX) side of the I2S peripheral. - pub i2s_rx: RxCreator<'d, I, CH, DmaMode>, + pub i2s_rx: RxCreator<'d, I, DmaMode>, /// Handles the transmission (TX) side of the I2S peripheral. - pub i2s_tx: TxCreator<'d, I, CH, DmaMode>, + pub i2s_tx: TxCreator<'d, I, DmaMode>, phantom: PhantomData, } -impl<'d, I, CH, DmaMode> I2s<'d, I, CH, DmaMode> +impl<'d, I, DmaMode> I2s<'d, I, DmaMode> where I: RegisterAccess, - CH: DmaChannel, DmaMode: Mode, { #[allow(clippy::too_many_arguments)] - fn new_internal( + fn new_internal( _i2s: impl Peripheral

+ 'd, standard: Standard, data_format: DataFormat, @@ -361,6 +358,7 @@ where I::set_master(); I::update(); + let channel = channel.degrade(); Self { i2s_rx: RxCreator { register_access: PhantomData, @@ -379,10 +377,9 @@ where } } -impl<'d, I, CH, DmaMode> I2s<'d, I, CH, DmaMode> +impl<'d, I, DmaMode> I2s<'d, I, DmaMode> where I: RegisterAccess, - CH: DmaChannel, DmaMode: Mode, { /// Sets the interrupt handler @@ -413,18 +410,16 @@ where } } -impl<'d, I, CH, DmaMode> crate::private::Sealed for I2s<'d, I, CH, DmaMode> +impl<'d, I, DmaMode> crate::private::Sealed for I2s<'d, I, DmaMode> where I: RegisterAccess, - CH: DmaChannel, DmaMode: Mode, { } -impl<'d, I, CH, DmaMode> InterruptConfigurable for I2s<'d, I, CH, DmaMode> +impl<'d, I, DmaMode> InterruptConfigurable for I2s<'d, I, DmaMode> where I: RegisterAccess, - CH: DmaChannel, DmaMode: Mode, { fn set_interrupt_handler(&mut self, handler: crate::interrupt::InterruptHandler) { @@ -432,16 +427,15 @@ where } } -impl<'d, I, CH, DmaMode> I2s<'d, I, CH, DmaMode> +impl<'d, I, DmaMode> I2s<'d, I, DmaMode> where I: RegisterAccess, - CH: DmaChannel, DmaMode: Mode, { /// Construct a new I2S peripheral driver instance for the first I2S /// peripheral #[allow(clippy::too_many_arguments)] - pub fn new( + pub fn new( i2s: impl Peripheral

+ 'd, standard: Standard, data_format: DataFormat, @@ -471,7 +465,7 @@ where /// peripheral #[allow(clippy::too_many_arguments)] #[cfg(i2s1)] - pub fn new_i2s1( + pub fn new_i2s1( i2s: impl Peripheral

+ 'd, standard: Standard, data_format: DataFormat, @@ -507,21 +501,19 @@ where } /// I2S TX channel -pub struct I2sTx<'d, T, CH, DmaMode> +pub struct I2sTx<'d, T, DmaMode> where T: RegisterAccess, - CH: DmaChannel, { register_access: PhantomData, - tx_channel: ChannelTx<'d, CH>, + tx_channel: ChannelTx<'d, AnyDmaChannel>, tx_chain: DescriptorChain, phantom: PhantomData, } -impl<'d, T, CH, DmaMode> core::fmt::Debug for I2sTx<'d, T, CH, DmaMode> +impl<'d, T, DmaMode> core::fmt::Debug for I2sTx<'d, T, DmaMode> where T: RegisterAccess, - CH: DmaChannel, DmaMode: Mode, { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { @@ -529,10 +521,9 @@ where } } -impl<'d, T, CH, DmaMode> DmaSupport for I2sTx<'d, T, CH, DmaMode> +impl<'d, T, DmaMode> DmaSupport for I2sTx<'d, T, DmaMode> where T: RegisterAccess, - CH: DmaChannel, DmaMode: Mode, { fn peripheral_wait_dma(&mut self, _is_rx: bool, _is_tx: bool) { @@ -544,13 +535,12 @@ where } } -impl<'d, T, CH, DmaMode> DmaSupportTx for I2sTx<'d, T, CH, DmaMode> +impl<'d, T, DmaMode> DmaSupportTx for I2sTx<'d, T, DmaMode> where T: RegisterAccess, - CH: DmaChannel, DmaMode: Mode, { - type TX = ChannelTx<'d, CH>; + type TX = ChannelTx<'d, AnyDmaChannel>; fn tx(&mut self) -> &mut Self::TX { &mut self.tx_channel @@ -561,13 +551,15 @@ where } } -impl<'d, T, CH, DmaMode> I2sTx<'d, T, CH, DmaMode> +impl<'d, T, DmaMode> I2sTx<'d, T, DmaMode> where T: RegisterAccess, - CH: DmaChannel, DmaMode: Mode, { - fn new(tx_channel: ChannelTx<'d, CH>, descriptors: &'static mut [DmaDescriptor]) -> Self { + fn new( + tx_channel: ChannelTx<'d, AnyDmaChannel>, + descriptors: &'static mut [DmaDescriptor], + ) -> Self { Self { register_access: PhantomData, tx_channel, @@ -636,10 +628,9 @@ where } } -impl<'d, T, W, CH, DmaMode> I2sWrite for I2sTx<'d, T, CH, DmaMode> +impl<'d, T, W, DmaMode> I2sWrite for I2sTx<'d, T, DmaMode> where T: RegisterAccess, - CH: DmaChannel, W: AcceptedWord, DmaMode: Mode, { @@ -650,10 +641,9 @@ where } } -impl<'d, T, CH, TXBUF, DmaMode> I2sWriteDma<'d, T, CH, TXBUF, DmaMode> for I2sTx<'d, T, CH, DmaMode> +impl<'d, T, TXBUF, DmaMode> I2sWriteDma<'d, T, TXBUF, DmaMode> for I2sTx<'d, T, DmaMode> where T: RegisterAccess, - CH: DmaChannel, DmaMode: Mode, { fn write_dma<'t>(&'t mut self, words: &'t TXBUF) -> Result, Error> @@ -677,22 +667,20 @@ where } /// I2S RX channel -pub struct I2sRx<'d, T, CH, DmaMode> +pub struct I2sRx<'d, T, DmaMode> where T: RegisterAccess, - CH: DmaChannel, DmaMode: Mode, { register_access: PhantomData, - rx_channel: ChannelRx<'d, CH>, + rx_channel: ChannelRx<'d, AnyDmaChannel>, rx_chain: DescriptorChain, phantom: PhantomData, } -impl<'d, T, CH, DmaMode> core::fmt::Debug for I2sRx<'d, T, CH, DmaMode> +impl<'d, T, DmaMode> core::fmt::Debug for I2sRx<'d, T, DmaMode> where T: RegisterAccess, - CH: DmaChannel, DmaMode: Mode, { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { @@ -700,10 +688,9 @@ where } } -impl<'d, T, CH, DmaMode> DmaSupport for I2sRx<'d, T, CH, DmaMode> +impl<'d, T, DmaMode> DmaSupport for I2sRx<'d, T, DmaMode> where T: RegisterAccess, - CH: DmaChannel, DmaMode: Mode, { fn peripheral_wait_dma(&mut self, _is_rx: bool, _is_tx: bool) { @@ -715,13 +702,12 @@ where } } -impl<'d, T, CH, DmaMode> DmaSupportRx for I2sRx<'d, T, CH, DmaMode> +impl<'d, T, DmaMode> DmaSupportRx for I2sRx<'d, T, DmaMode> where T: RegisterAccess, - CH: DmaChannel, DmaMode: Mode, { - type RX = ChannelRx<'d, CH>; + type RX = ChannelRx<'d, AnyDmaChannel>; fn rx(&mut self) -> &mut Self::RX { &mut self.rx_channel @@ -732,13 +718,15 @@ where } } -impl<'d, T, CH, DmaMode> I2sRx<'d, T, CH, DmaMode> +impl<'d, T, DmaMode> I2sRx<'d, T, DmaMode> where T: RegisterAccess, - CH: DmaChannel, DmaMode: Mode, { - fn new(rx_channel: ChannelRx<'d, CH>, descriptors: &'static mut [DmaDescriptor]) -> Self { + fn new( + rx_channel: ChannelRx<'d, AnyDmaChannel>, + descriptors: &'static mut [DmaDescriptor], + ) -> Self { Self { register_access: PhantomData, rx_channel, @@ -805,10 +793,9 @@ where } } -impl<'d, W, T, CH, DmaMode> I2sRead for I2sRx<'d, T, CH, DmaMode> +impl<'d, W, T, DmaMode> I2sRead for I2sRx<'d, T, DmaMode> where T: RegisterAccess, - CH: DmaChannel, W: AcceptedWord, DmaMode: Mode, { @@ -826,10 +813,9 @@ where } } -impl<'d, T, CH, RXBUF, DmaMode> I2sReadDma<'d, T, CH, RXBUF, DmaMode> for I2sRx<'d, T, CH, DmaMode> +impl<'d, T, RXBUF, DmaMode> I2sReadDma<'d, T, RXBUF, DmaMode> for I2sRx<'d, T, DmaMode> where T: RegisterAccess, - CH: DmaChannel, DmaMode: Mode, Self: DmaSupportRx + Sized, { @@ -878,7 +864,7 @@ mod private { #[cfg(any(esp32, esp32s3))] use crate::peripherals::{i2s1::RegisterBlock, I2S1}; use crate::{ - dma::{ChannelRx, ChannelTx, DmaChannel, DmaDescriptor, DmaPeripheral}, + dma::{AnyDmaChannel, ChannelRx, ChannelTx, DmaDescriptor, DmaPeripheral}, gpio::{InputSignal, OutputSignal, PeripheralInput, PeripheralOutput}, interrupt::InterruptHandler, into_ref, @@ -888,25 +874,23 @@ mod private { Mode, }; - pub struct TxCreator<'d, T, CH, DmaMode> + pub struct TxCreator<'d, T, DmaMode> where T: RegisterAccess, - CH: DmaChannel, DmaMode: Mode, { pub register_access: PhantomData, - pub tx_channel: ChannelTx<'d, CH>, + pub tx_channel: ChannelTx<'d, AnyDmaChannel>, pub descriptors: &'static mut [DmaDescriptor], pub(crate) phantom: PhantomData, } - impl<'d, T, CH, DmaMode> TxCreator<'d, T, CH, DmaMode> + impl<'d, T, DmaMode> TxCreator<'d, T, DmaMode> where T: RegisterAccess, - CH: DmaChannel, DmaMode: Mode, { - pub fn build(self) -> I2sTx<'d, T, CH, DmaMode> { + pub fn build(self) -> I2sTx<'d, T, DmaMode> { I2sTx::new(self.tx_channel, self.descriptors) } @@ -944,25 +928,23 @@ mod private { } } - pub struct RxCreator<'d, T, CH, DmaMode> + pub struct RxCreator<'d, T, DmaMode> where T: RegisterAccess, - CH: DmaChannel, DmaMode: Mode, { pub register_access: PhantomData, - pub rx_channel: ChannelRx<'d, CH>, + pub rx_channel: ChannelRx<'d, AnyDmaChannel>, pub descriptors: &'static mut [DmaDescriptor], pub(crate) phantom: PhantomData, } - impl<'d, T, CH, DmaMode> RxCreator<'d, T, CH, DmaMode> + impl<'d, T, DmaMode> RxCreator<'d, T, DmaMode> where T: RegisterAccess, - CH: DmaChannel, DmaMode: Mode, { - pub fn build(self) -> I2sRx<'d, T, CH, DmaMode> { + pub fn build(self) -> I2sRx<'d, T, DmaMode> { I2sRx::new(self.rx_channel, self.descriptors) } @@ -2100,7 +2082,6 @@ pub mod asynch { use crate::{ dma::{ asynch::{DmaRxDoneChFuture, DmaRxFuture, DmaTxDoneChFuture, DmaTxFuture}, - DmaChannel, ReadBuffer, Rx, RxCircularState, @@ -2112,10 +2093,9 @@ pub mod asynch { }; /// Initiate an async DMA tx transfer - pub trait I2sWriteDmaAsync<'d, T, CH> + pub trait I2sWriteDmaAsync<'d, T> where T: RegisterAccess, - CH: DmaChannel, { /// One-shot write I2S. async fn write_dma_async(&mut self, words: &mut [u8]) -> Result<(), Error>; @@ -2124,15 +2104,14 @@ pub mod asynch { fn write_dma_circular_async( self, words: TXBUF, - ) -> Result, Error> + ) -> Result, Error> where TXBUF: ReadBuffer; } - impl<'d, T, CH> I2sWriteDmaAsync<'d, T, CH> for super::I2sTx<'d, T, CH, Async> + impl<'d, T> I2sWriteDmaAsync<'d, T> for super::I2sTx<'d, T, Async> where T: RegisterAccess, - CH: DmaChannel, { async fn write_dma_async(&mut self, words: &mut [u8]) -> Result<(), Error> { let (ptr, len) = (words.as_ptr(), words.len()); @@ -2158,7 +2137,7 @@ pub mod asynch { fn write_dma_circular_async( mut self, words: TXBUF, - ) -> Result, Error> + ) -> Result, Error> where TXBUF: ReadBuffer, { @@ -2192,20 +2171,18 @@ pub mod asynch { } /// An in-progress async circular DMA write transfer. - pub struct I2sWriteDmaTransferAsync<'d, T, CH, BUFFER> + pub struct I2sWriteDmaTransferAsync<'d, T, BUFFER> where T: RegisterAccess, - CH: DmaChannel, { - i2s_tx: I2sTx<'d, T, CH, Async>, + i2s_tx: I2sTx<'d, T, Async>, state: TxCircularState, _buffer: BUFFER, } - impl<'d, T, CH, BUFFER> I2sWriteDmaTransferAsync<'d, T, CH, BUFFER> + impl<'d, T, BUFFER> I2sWriteDmaTransferAsync<'d, T, BUFFER> where T: RegisterAccess, - CH: DmaChannel, { /// How many bytes can be pushed into the DMA transaction. /// Will wait for more than 0 bytes available. @@ -2244,10 +2221,9 @@ pub mod asynch { } /// Initiate an async DMA rx transfer - pub trait I2sReadDmaAsync<'d, T, CH> + pub trait I2sReadDmaAsync<'d, T> where T: RegisterAccess, - CH: DmaChannel, { /// One-shot read I2S. async fn read_dma_async(&mut self, words: &mut [u8]) -> Result<(), Error>; @@ -2256,15 +2232,14 @@ pub mod asynch { fn read_dma_circular_async( self, words: RXBUF, - ) -> Result, Error> + ) -> Result, Error> where RXBUF: WriteBuffer; } - impl<'d, T, CH> I2sReadDmaAsync<'d, T, CH> for super::I2sRx<'d, T, CH, Async> + impl<'d, T> I2sReadDmaAsync<'d, T> for super::I2sRx<'d, T, Async> where T: RegisterAccess, - CH: DmaChannel, { async fn read_dma_async(&mut self, words: &mut [u8]) -> Result<(), Error> { let (ptr, len) = (words.as_mut_ptr(), words.len()); @@ -2298,7 +2273,7 @@ pub mod asynch { fn read_dma_circular_async( mut self, mut words: RXBUF, - ) -> Result, Error> + ) -> Result, Error> where RXBUF: WriteBuffer, { @@ -2334,20 +2309,18 @@ pub mod asynch { } /// An in-progress async circular DMA read transfer. - pub struct I2sReadDmaTransferAsync<'d, T, CH, BUFFER> + pub struct I2sReadDmaTransferAsync<'d, T, BUFFER> where T: RegisterAccess, - CH: DmaChannel, { - i2s_rx: I2sRx<'d, T, CH, Async>, + i2s_rx: I2sRx<'d, T, Async>, state: RxCircularState, _buffer: BUFFER, } - impl<'d, T, CH, BUFFER> I2sReadDmaTransferAsync<'d, T, CH, BUFFER> + impl<'d, T, BUFFER> I2sReadDmaTransferAsync<'d, T, BUFFER> where T: RegisterAccess, - CH: DmaChannel, { /// How many bytes can be popped from the DMA transaction. /// Will wait for more than 0 bytes available. diff --git a/esp-hal/src/lcd_cam/cam.rs b/esp-hal/src/lcd_cam/cam.rs index fce7aa05666..17cd84e22c0 100644 --- a/esp-hal/src/lcd_cam/cam.rs +++ b/esp-hal/src/lcd_cam/cam.rs @@ -77,7 +77,6 @@ use crate::{ dma::{ AnyDmaChannel, ChannelRx, - DmaChannel, DmaError, DmaPeripheral, DmaRxBuffer, @@ -130,31 +129,14 @@ pub struct Cam<'d> { } /// Represents the camera interface with DMA support. -pub struct Camera<'d, CH: DmaChannel = AnyDmaChannel> { +pub struct Camera<'d> { lcd_cam: PeripheralRef<'d, LCD_CAM>, - rx_channel: ChannelRx<'d, CH>, + rx_channel: ChannelRx<'d, AnyDmaChannel>, } impl<'d> Camera<'d> { /// Creates a new `Camera` instance with DMA support. - pub fn new( - cam: Cam<'d>, - channel: ChannelRx<'d, CH>, - descriptors: &'static mut [DmaDescriptor], - pins: P, - frequency: HertzU32, - ) -> Self - where - CH: PeripheralDmaChannel, - CH::P: LcdCamPeripheral, - { - Self::new_typed(cam, channel.degrade(), descriptors, pins, frequency) - } -} - -impl<'d, CH: DmaChannel> Camera<'d, CH> { - /// Creates a new `Camera` instance with DMA support. - pub fn new_typed( + pub fn new( cam: Cam<'d>, channel: ChannelRx<'d, CH>, _pins: P, @@ -163,6 +145,7 @@ impl<'d, CH: DmaChannel> Camera<'d, CH> { where CH: PeripheralDmaChannel, CH::P: LcdCamPeripheral, + P: RxPins, { let lcd_cam = cam.lcd_cam; @@ -209,12 +192,12 @@ impl<'d, CH: DmaChannel> Camera<'d, CH> { Self { lcd_cam, - rx_channel: channel, + rx_channel: channel.degrade(), } } } -impl<'d, CH: DmaChannel> Camera<'d, CH> { +impl<'d> Camera<'d> { /// Configures the byte order for the camera data. pub fn set_byte_order(&mut self, byte_order: ByteOrder) -> &mut Self { self.lcd_cam @@ -329,7 +312,7 @@ impl<'d, CH: DmaChannel> Camera<'d, CH> { pub fn receive( mut self, mut buf: BUF, - ) -> Result, (DmaError, Self, BUF)> { + ) -> Result, (DmaError, Self, BUF)> { // Reset Camera control unit and Async Rx FIFO self.lcd_cam .cam_ctrl1() @@ -375,12 +358,12 @@ impl<'d, CH: DmaChannel> Camera<'d, CH> { /// Represents an ongoing (or potentially stopped) transfer from the Camera to a /// DMA buffer. -pub struct CameraTransfer<'d, BUF: DmaRxBuffer, CH: DmaChannel = AnyDmaChannel> { - camera: ManuallyDrop>, +pub struct CameraTransfer<'d, BUF: DmaRxBuffer> { + camera: ManuallyDrop>, buffer_view: ManuallyDrop, } -impl<'d, BUF: DmaRxBuffer, CH: DmaChannel> CameraTransfer<'d, BUF, CH> { +impl<'d, BUF: DmaRxBuffer> CameraTransfer<'d, BUF> { /// Returns true when [Self::wait] will not block. pub fn is_done(&self) -> bool { // This peripheral doesn't really "complete". As long the camera (or anything @@ -408,7 +391,7 @@ impl<'d, BUF: DmaRxBuffer, CH: DmaChannel> CameraTransfer<'d, BUF, CH> { } /// Stops this transfer on the spot and returns the peripheral and buffer. - pub fn stop(mut self) -> (Camera<'d, CH>, BUF) { + pub fn stop(mut self) -> (Camera<'d>, BUF) { self.stop_peripherals(); let (camera, view) = self.release(); (camera, BUF::from_view(view)) @@ -419,7 +402,7 @@ impl<'d, BUF: DmaRxBuffer, CH: DmaChannel> CameraTransfer<'d, BUF, CH> { /// Note: The camera doesn't really "finish" its transfer, so what you're /// really waiting for here is a DMA Error. You typically just want to /// call [Self::stop] once you have the data you need. - pub fn wait(mut self) -> (Result<(), DmaError>, Camera<'d, CH>, BUF) { + pub fn wait(mut self) -> (Result<(), DmaError>, Camera<'d>, BUF) { while !self.is_done() {} // Stop the DMA as it doesn't know that the camera has stopped. @@ -438,7 +421,7 @@ impl<'d, BUF: DmaRxBuffer, CH: DmaChannel> CameraTransfer<'d, BUF, CH> { (result, camera, BUF::from_view(view)) } - fn release(mut self) -> (Camera<'d, CH>, BUF::View) { + fn release(mut self) -> (Camera<'d>, BUF::View) { // SAFETY: Since forget is called on self, we know that self.camera and // self.buffer_view won't be touched again. let result = unsafe { @@ -462,7 +445,7 @@ impl<'d, BUF: DmaRxBuffer, CH: DmaChannel> CameraTransfer<'d, BUF, CH> { } } -impl<'d, BUF: DmaRxBuffer, CH: DmaChannel> Deref for CameraTransfer<'d, BUF, CH> { +impl<'d, BUF: DmaRxBuffer> Deref for CameraTransfer<'d, BUF> { type Target = BUF::View; fn deref(&self) -> &Self::Target { @@ -470,13 +453,13 @@ impl<'d, BUF: DmaRxBuffer, CH: DmaChannel> Deref for CameraTransfer<'d, BUF, CH> } } -impl<'d, BUF: DmaRxBuffer, CH: DmaChannel> DerefMut for CameraTransfer<'d, BUF, CH> { +impl<'d, BUF: DmaRxBuffer> DerefMut for CameraTransfer<'d, BUF> { fn deref_mut(&mut self) -> &mut Self::Target { &mut self.buffer_view } } -impl<'d, BUF: DmaRxBuffer, CH: DmaChannel> Drop for CameraTransfer<'d, BUF, CH> { +impl<'d, BUF: DmaRxBuffer> Drop for CameraTransfer<'d, BUF> { fn drop(&mut self) { self.stop_peripherals(); diff --git a/esp-hal/src/lcd_cam/lcd/i8080.rs b/esp-hal/src/lcd_cam/lcd/i8080.rs index bc9a81b8298..f02009d9199 100644 --- a/esp-hal/src/lcd_cam/lcd/i8080.rs +++ b/esp-hal/src/lcd_cam/lcd/i8080.rs @@ -69,8 +69,8 @@ use fugit::HertzU32; use crate::{ clock::Clocks, dma::{ + AnyDmaChannel, ChannelTx, - DmaChannel, DmaError, DmaPeripheral, DmaTxBuffer, @@ -93,15 +93,15 @@ use crate::{ }; /// Represents the I8080 LCD interface. -pub struct I8080<'d, CH: DmaChannel, DM: Mode> { +pub struct I8080<'d, DM: Mode> { lcd_cam: PeripheralRef<'d, LCD_CAM>, - tx_channel: ChannelTx<'d, CH>, + tx_channel: ChannelTx<'d, AnyDmaChannel>, _phantom: PhantomData, } -impl<'d, CH: DmaChannel, DM: Mode> I8080<'d, CH, DM> { +impl<'d, DM: Mode> I8080<'d, DM> { /// Creates a new instance of the I8080 LCD interface. - pub fn new( + pub fn new( lcd: Lcd<'d, DM>, channel: ChannelTx<'d, CH>, mut pins: P, @@ -111,6 +111,7 @@ impl<'d, CH: DmaChannel, DM: Mode> I8080<'d, CH, DM> { where CH: PeripheralDmaChannel, CH::P: LcdCamPeripheral, + P: TxPins, { let lcd_cam = lcd.lcd_cam; @@ -214,13 +215,13 @@ impl<'d, CH: DmaChannel, DM: Mode> I8080<'d, CH, DM> { Self { lcd_cam, - tx_channel: channel, + tx_channel: channel.degrade(), _phantom: PhantomData, } } } -impl<'d, CH: DmaChannel, DM: Mode> I8080<'d, CH, DM> { +impl<'d, DM: Mode> I8080<'d, DM> { /// Configures the byte order for data transmission. pub fn set_byte_order(&mut self, byte_order: ByteOrder) -> &mut Self { let is_inverted = byte_order != ByteOrder::default(); @@ -279,7 +280,7 @@ impl<'d, CH: DmaChannel, DM: Mode> I8080<'d, CH, DM> { cmd: impl Into>, dummy: u8, mut data: BUF, - ) -> Result, (DmaError, Self, BUF)> { + ) -> Result, (DmaError, Self, BUF)> { let cmd = cmd.into(); // Reset LCD control unit and Async Tx FIFO @@ -375,7 +376,7 @@ impl<'d, CH: DmaChannel, DM: Mode> I8080<'d, CH, DM> { } } -impl<'d, CH: DmaChannel, DM: Mode> core::fmt::Debug for I8080<'d, CH, DM> { +impl<'d, DM: Mode> core::fmt::Debug for I8080<'d, DM> { fn fmt(&self, f: &mut Formatter<'_>) -> core::fmt::Result { f.debug_struct("I8080").finish() } @@ -383,12 +384,12 @@ impl<'d, CH: DmaChannel, DM: Mode> core::fmt::Debug for I8080<'d, CH, DM> { /// Represents an ongoing (or potentially finished) transfer using the I8080 LCD /// interface -pub struct I8080Transfer<'d, BUF, CH: DmaChannel, DM: Mode> { - i8080: ManuallyDrop>, +pub struct I8080Transfer<'d, BUF, DM: Mode> { + i8080: ManuallyDrop>, tx_buf: ManuallyDrop, } -impl<'d, BUF, CH: DmaChannel, DM: Mode> I8080Transfer<'d, BUF, CH, DM> { +impl<'d, BUF, DM: Mode> I8080Transfer<'d, BUF, DM> { /// Returns true when [Self::wait] will not block. pub fn is_done(&self) -> bool { self.i8080 @@ -400,7 +401,7 @@ impl<'d, BUF, CH: DmaChannel, DM: Mode> I8080Transfer<'d, BUF, CH, DM> { } /// Stops this transfer on the spot and returns the peripheral and buffer. - pub fn cancel(mut self) -> (I8080<'d, CH, DM>, BUF) { + pub fn cancel(mut self) -> (I8080<'d, DM>, BUF) { self.stop_peripherals(); let (_, i8080, buf) = self.wait(); (i8080, buf) @@ -410,7 +411,7 @@ impl<'d, BUF, CH: DmaChannel, DM: Mode> I8080Transfer<'d, BUF, CH, DM> { /// /// Note: This also clears the transfer interrupt so it can be used in /// interrupt handlers to "handle" the interrupt. - pub fn wait(mut self) -> (Result<(), DmaError>, I8080<'d, CH, DM>, BUF) { + pub fn wait(mut self) -> (Result<(), DmaError>, I8080<'d, DM>, BUF) { while !self.is_done() {} // Clear "done" interrupt. @@ -449,7 +450,7 @@ impl<'d, BUF, CH: DmaChannel, DM: Mode> I8080Transfer<'d, BUF, CH, DM> { } } -impl<'d, BUF, CH: DmaChannel> I8080Transfer<'d, BUF, CH, crate::Async> { +impl<'d, BUF> I8080Transfer<'d, BUF, crate::Async> { /// Waits for [Self::is_done] to return true. pub async fn wait_for_done(&mut self) { use core::{ @@ -488,7 +489,7 @@ impl<'d, BUF, CH: DmaChannel> I8080Transfer<'d, BUF, CH, crate::Async> { } } -impl<'d, BUF, CH: DmaChannel, DM: Mode> Drop for I8080Transfer<'d, BUF, CH, DM> { +impl<'d, BUF, DM: Mode> Drop for I8080Transfer<'d, BUF, DM> { fn drop(&mut self) { self.stop_peripherals(); diff --git a/esp-hal/src/parl_io.rs b/esp-hal/src/parl_io.rs index 7e350359cdb..dad3f5eaf05 100644 --- a/esp-hal/src/parl_io.rs +++ b/esp-hal/src/parl_io.rs @@ -33,11 +33,11 @@ use private::*; use crate::{ dma::{ dma_private::{DmaSupport, DmaSupportRx, DmaSupportTx}, + AnyDmaChannel, Channel, ChannelRx, ChannelTx, DescriptorChain, - DmaChannel, DmaDescriptor, DmaError, DmaPeripheral, @@ -836,9 +836,8 @@ impl<'d, P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15> { } -impl<'d, CH, DM> TxCreatorFullDuplex<'d, CH, DM> +impl<'d, DM> TxCreatorFullDuplex<'d, DM> where - CH: DmaChannel, DM: Mode, { /// Configure TX to use the given pins and settings @@ -849,7 +848,7 @@ where idle_value: u16, sample_edge: SampleEdge, bit_order: BitPackOrder, - ) -> Result, Error> + ) -> Result, Error> where P: FullDuplex + TxPins + ConfigurePins, CP: TxClkPin, @@ -869,9 +868,8 @@ where } } -impl<'d, CH, DM> TxCreator<'d, CH, DM> +impl<'d, DM> TxCreator<'d, DM> where - CH: DmaChannel, DM: Mode, { /// Configure TX to use the given pins and settings @@ -882,7 +880,7 @@ where idle_value: u16, sample_edge: SampleEdge, bit_order: BitPackOrder, - ) -> Result, Error> + ) -> Result, Error> where P: TxPins + ConfigurePins, CP: TxClkPin, @@ -903,19 +901,17 @@ where } /// Parallel IO TX channel -pub struct ParlIoTx<'d, CH, DM> +pub struct ParlIoTx<'d, DM> where - CH: DmaChannel, DM: Mode, { - tx_channel: ChannelTx<'d, CH>, + tx_channel: ChannelTx<'d, AnyDmaChannel>, tx_chain: DescriptorChain, phantom: PhantomData, } -impl<'d, CH, DM> core::fmt::Debug for ParlIoTx<'d, CH, DM> +impl<'d, DM> core::fmt::Debug for ParlIoTx<'d, DM> where - CH: DmaChannel, DM: Mode, { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { @@ -923,9 +919,8 @@ where } } -impl<'d, CH, DM> RxCreatorFullDuplex<'d, CH, DM> +impl<'d, DM> RxCreatorFullDuplex<'d, DM> where - CH: DmaChannel, DM: Mode, { /// Configure RX to use the given pins and settings @@ -935,7 +930,7 @@ where clk_pin: &'d mut CP, bit_order: BitPackOrder, timeout_ticks: Option, - ) -> Result, Error> + ) -> Result, Error> where P: FullDuplex + RxPins + ConfigurePins, CP: RxClkPin, @@ -954,9 +949,8 @@ where } } -impl<'d, CH, DM> RxCreator<'d, CH, DM> +impl<'d, DM> RxCreator<'d, DM> where - CH: DmaChannel, DM: Mode, { /// Configure RX to use the given pins and settings @@ -966,7 +960,7 @@ where clk_pin: &'d mut CP, bit_order: BitPackOrder, timeout_ticks: Option, - ) -> Result, Error> + ) -> Result, Error> where P: RxPins + ConfigurePins, CP: RxClkPin, @@ -986,19 +980,17 @@ where } /// Parallel IO RX channel -pub struct ParlIoRx<'d, CH, DM> +pub struct ParlIoRx<'d, DM> where - CH: DmaChannel, DM: Mode, { - rx_channel: ChannelRx<'d, CH>, + rx_channel: ChannelRx<'d, AnyDmaChannel>, rx_chain: DescriptorChain, phantom: PhantomData, } -impl<'d, CH, DM> core::fmt::Debug for ParlIoRx<'d, CH, DM> +impl<'d, DM> core::fmt::Debug for ParlIoRx<'d, DM> where - CH: DmaChannel, DM: Mode, { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { @@ -1099,26 +1091,24 @@ fn internal_clear_interrupts(interrupts: EnumSet) { /// Parallel IO in full duplex mode /// /// Full duplex mode might limit the maximum possible bit width. -pub struct ParlIoFullDuplex<'d, CH, DM> +pub struct ParlIoFullDuplex<'d, DM> where - CH: DmaChannel, DM: Mode, { /// The transmitter (TX) channel responsible for handling DMA transfers in /// the parallel I/O full-duplex operation. - pub tx: TxCreatorFullDuplex<'d, CH, DM>, + pub tx: TxCreatorFullDuplex<'d, DM>, /// The receiver (RX) channel responsible for handling DMA transfers in the /// parallel I/O full-duplex operation. - pub rx: RxCreatorFullDuplex<'d, CH, DM>, + pub rx: RxCreatorFullDuplex<'d, DM>, } -impl<'d, CH, DM> ParlIoFullDuplex<'d, CH, DM> +impl<'d, DM> ParlIoFullDuplex<'d, DM> where - CH: DmaChannel, DM: Mode, { /// Create a new instance of [ParlIoFullDuplex] - pub fn new( + pub fn new( _parl_io: impl Peripheral

+ 'd, dma_channel: Channel<'d, CH, DM>, tx_descriptors: &'static mut [DmaDescriptor], @@ -1133,12 +1123,12 @@ where Ok(Self { tx: TxCreatorFullDuplex { - tx_channel: dma_channel.tx, + tx_channel: dma_channel.tx.degrade(), descriptors: tx_descriptors, phantom: PhantomData, }, rx: RxCreatorFullDuplex { - rx_channel: dma_channel.rx, + rx_channel: dma_channel.rx.degrade(), descriptors: rx_descriptors, phantom: PhantomData, }, @@ -1146,10 +1136,7 @@ where } } -impl<'d, CH> ParlIoFullDuplex<'d, CH, Blocking> -where - CH: DmaChannel, -{ +impl<'d> ParlIoFullDuplex<'d, Blocking> { /// Sets the interrupt handler, enables it with /// [crate::interrupt::Priority::min()] /// @@ -1179,35 +1166,31 @@ where } } -impl<'d, CH> crate::private::Sealed for ParlIoFullDuplex<'d, CH, Blocking> where CH: DmaChannel {} +impl<'d> crate::private::Sealed for ParlIoFullDuplex<'d, Blocking> {} -impl<'d, CH> InterruptConfigurable for ParlIoFullDuplex<'d, CH, Blocking> -where - CH: DmaChannel, -{ +impl<'d> InterruptConfigurable for ParlIoFullDuplex<'d, Blocking> { fn set_interrupt_handler(&mut self, handler: crate::interrupt::InterruptHandler) { ParlIoFullDuplex::set_interrupt_handler(self, handler); } } /// Parallel IO in half duplex / TX only mode -pub struct ParlIoTxOnly<'d, CH, DM> +pub struct ParlIoTxOnly<'d, DM> where - CH: DmaChannel, DM: Mode, { /// The transmitter (TX) channel responsible for handling DMA transfers in /// the parallel I/O operation. - pub tx: TxCreator<'d, CH, DM>, + pub tx: TxCreator<'d, DM>, } -impl<'d, CH, DM> ParlIoTxOnly<'d, CH, DM> +impl<'d, DM> ParlIoTxOnly<'d, DM> where - CH: DmaChannel, DM: Mode, { /// Create a new [ParlIoTxOnly] - pub fn new( + // TODO: only take a TX DMA channel? + pub fn new( _parl_io: impl Peripheral

+ 'd, dma_channel: Channel<'d, CH, DM>, descriptors: &'static mut [DmaDescriptor], @@ -1221,7 +1204,7 @@ where Ok(Self { tx: TxCreator { - tx_channel: dma_channel.tx, + tx_channel: dma_channel.tx.degrade(), descriptors, phantom: PhantomData, }, @@ -1229,10 +1212,7 @@ where } } -impl<'d, CH> ParlIoTxOnly<'d, CH, Blocking> -where - CH: DmaChannel, -{ +impl<'d> ParlIoTxOnly<'d, Blocking> { /// Sets the interrupt handler, enables it with /// [crate::interrupt::Priority::min()] /// @@ -1262,35 +1242,31 @@ where } } -impl<'d, CH> crate::private::Sealed for ParlIoTxOnly<'d, CH, Blocking> where CH: DmaChannel {} +impl<'d> crate::private::Sealed for ParlIoTxOnly<'d, Blocking> {} -impl<'d, CH> InterruptConfigurable for ParlIoTxOnly<'d, CH, Blocking> -where - CH: DmaChannel, -{ +impl<'d> InterruptConfigurable for ParlIoTxOnly<'d, Blocking> { fn set_interrupt_handler(&mut self, handler: crate::interrupt::InterruptHandler) { ParlIoTxOnly::set_interrupt_handler(self, handler); } } /// Parallel IO in half duplex / RX only mode -pub struct ParlIoRxOnly<'d, CH, DM> +pub struct ParlIoRxOnly<'d, DM> where - CH: DmaChannel, DM: Mode, { /// The receiver (RX) channel responsible for handling DMA transfers in the /// parallel I/O operation. - pub rx: RxCreator<'d, CH, DM>, + pub rx: RxCreator<'d, DM>, } -impl<'d, CH, DM> ParlIoRxOnly<'d, CH, DM> +impl<'d, DM> ParlIoRxOnly<'d, DM> where - CH: DmaChannel, DM: Mode, { /// Create a new [ParlIoRxOnly] instance - pub fn new( + // TODO: only take a RX DMA channel? + pub fn new( _parl_io: impl Peripheral

+ 'd, dma_channel: Channel<'d, CH, DM>, descriptors: &'static mut [DmaDescriptor], @@ -1304,7 +1280,7 @@ where Ok(Self { rx: RxCreator { - rx_channel: dma_channel.rx, + rx_channel: dma_channel.rx.degrade(), descriptors, phantom: PhantomData, }, @@ -1312,10 +1288,7 @@ where } } -impl<'d, CH> ParlIoRxOnly<'d, CH, Blocking> -where - CH: DmaChannel, -{ +impl<'d> ParlIoRxOnly<'d, Blocking> { /// Sets the interrupt handler, enables it with /// [crate::interrupt::Priority::min()] /// @@ -1345,12 +1318,9 @@ where } } -impl<'d, CH> crate::private::Sealed for ParlIoRxOnly<'d, CH, Blocking> where CH: DmaChannel {} +impl<'d> crate::private::Sealed for ParlIoRxOnly<'d, Blocking> {} -impl<'d, CH> InterruptConfigurable for ParlIoRxOnly<'d, CH, Blocking> -where - CH: DmaChannel, -{ +impl<'d> InterruptConfigurable for ParlIoRxOnly<'d, Blocking> { fn set_interrupt_handler(&mut self, handler: crate::interrupt::InterruptHandler) { ParlIoRxOnly::set_interrupt_handler(self, handler); } @@ -1389,9 +1359,8 @@ fn internal_init(frequency: HertzU32) -> Result<(), Error> { Ok(()) } -impl<'d, CH, DM> ParlIoTx<'d, CH, DM> +impl<'d, DM> ParlIoTx<'d, DM> where - CH: DmaChannel, DM: Mode, { /// Perform a DMA write. @@ -1449,9 +1418,8 @@ where } } -impl<'d, CH, DM> DmaSupport for ParlIoTx<'d, CH, DM> +impl<'d, DM> DmaSupport for ParlIoTx<'d, DM> where - CH: DmaChannel, DM: Mode, { fn peripheral_wait_dma(&mut self, _is_rx: bool, _is_tx: bool) { @@ -1465,12 +1433,11 @@ where } } -impl<'d, CH, DM> DmaSupportTx for ParlIoTx<'d, CH, DM> +impl<'d, DM> DmaSupportTx for ParlIoTx<'d, DM> where - CH: DmaChannel, DM: Mode, { - type TX = ChannelTx<'d, CH>; + type TX = ChannelTx<'d, AnyDmaChannel>; fn tx(&mut self) -> &mut Self::TX { &mut self.tx_channel @@ -1481,9 +1448,8 @@ where } } -impl<'d, CH, DM> ParlIoRx<'d, CH, DM> +impl<'d, DM> ParlIoRx<'d, DM> where - CH: DmaChannel, DM: Mode, { /// Perform a DMA read. @@ -1513,7 +1479,7 @@ where } fn start_receive_bytes_dma( - rx_channel: &mut ChannelRx<'d, CH>, + rx_channel: &mut ChannelRx<'d, AnyDmaChannel>, rx_chain: &mut DescriptorChain, ptr: *mut u8, len: usize, @@ -1541,9 +1507,8 @@ where } } -impl<'d, CH, DM> DmaSupport for ParlIoRx<'d, CH, DM> +impl<'d, DM> DmaSupport for ParlIoRx<'d, DM> where - CH: DmaChannel, DM: Mode, { fn peripheral_wait_dma(&mut self, _is_rx: bool, _is_tx: bool) { @@ -1564,12 +1529,11 @@ where } } -impl<'d, CH, DM> DmaSupportRx for ParlIoRx<'d, CH, DM> +impl<'d, DM> DmaSupportRx for ParlIoRx<'d, DM> where - CH: DmaChannel, DM: Mode, { - type RX = ChannelRx<'d, CH>; + type RX = ChannelRx<'d, AnyDmaChannel>; fn rx(&mut self) -> &mut Self::RX { &mut self.rx_channel @@ -1581,45 +1545,41 @@ where } /// Creates a TX channel -pub struct TxCreator<'d, CH, DM> +pub struct TxCreator<'d, DM> where - CH: DmaChannel, DM: Mode, { - tx_channel: ChannelTx<'d, CH>, + tx_channel: ChannelTx<'d, AnyDmaChannel>, descriptors: &'static mut [DmaDescriptor], phantom: PhantomData, } /// Creates a RX channel -pub struct RxCreator<'d, CH, DM> +pub struct RxCreator<'d, DM> where - CH: DmaChannel, DM: Mode, { - rx_channel: ChannelRx<'d, CH>, + rx_channel: ChannelRx<'d, AnyDmaChannel>, descriptors: &'static mut [DmaDescriptor], phantom: PhantomData, } /// Creates a TX channel -pub struct TxCreatorFullDuplex<'d, CH, DM> +pub struct TxCreatorFullDuplex<'d, DM> where - CH: DmaChannel, DM: Mode, { - tx_channel: ChannelTx<'d, CH>, + tx_channel: ChannelTx<'d, AnyDmaChannel>, descriptors: &'static mut [DmaDescriptor], phantom: PhantomData, } /// Creates a RX channel -pub struct RxCreatorFullDuplex<'d, CH, DM> +pub struct RxCreatorFullDuplex<'d, DM> where - CH: DmaChannel, DM: Mode, { - rx_channel: ChannelRx<'d, CH>, + rx_channel: ChannelRx<'d, AnyDmaChannel>, descriptors: &'static mut [DmaDescriptor], phantom: PhantomData, } @@ -1633,7 +1593,7 @@ pub mod asynch { use super::{private::Instance, Error, ParlIoRx, ParlIoTx, MAX_DMA_SIZE}; use crate::{ - dma::{asynch::DmaRxFuture, DmaChannel, ReadBuffer, WriteBuffer}, + dma::{asynch::DmaRxFuture, ReadBuffer, WriteBuffer}, peripherals::Interrupt, }; @@ -1688,10 +1648,7 @@ pub mod asynch { } } - impl<'d, CH> ParlIoTx<'d, CH, crate::Async> - where - CH: DmaChannel, - { + impl<'d> ParlIoTx<'d, crate::Async> { /// Perform a DMA write. /// /// The maximum amount of data to be sent is 32736 bytes. @@ -1713,10 +1670,7 @@ pub mod asynch { } } - impl<'d, CH> ParlIoRx<'d, CH, crate::Async> - where - CH: DmaChannel, - { + impl<'d> ParlIoRx<'d, crate::Async> { /// Perform a DMA write. /// /// The maximum amount of data to be sent is 32736 bytes. diff --git a/esp-hal/src/spi/master.rs b/esp-hal/src/spi/master.rs index 0ef6b2d0109..1a909db8b3a 100644 --- a/esp-hal/src/spi/master.rs +++ b/esp-hal/src/spi/master.rs @@ -918,8 +918,8 @@ mod dma { use crate::{ dma::{ asynch::{DmaRxFuture, DmaTxFuture}, + AnyDmaChannel, Channel, - DmaChannel, DmaRxBuf, DmaRxBuffer, DmaTxBuf, @@ -946,7 +946,7 @@ mod dma { pub fn with_dma( self, channel: Channel<'d, C, DmaMode>, - ) -> SpiDma<'d, crate::peripherals::SPI2, C, M, DmaMode> + ) -> SpiDma<'d, crate::peripherals::SPI2, M, DmaMode> where C: PeripheralDmaChannel, C::P: SpiPeripheral + Spi2Peripheral, @@ -969,7 +969,7 @@ mod dma { pub fn with_dma( self, channel: Channel<'d, C, DmaMode>, - ) -> SpiDma<'d, crate::peripherals::SPI3, C, M, DmaMode> + ) -> SpiDma<'d, crate::peripherals::SPI3, M, DmaMode> where C: PeripheralDmaChannel, C::P: SpiPeripheral + Spi3Peripheral, @@ -986,14 +986,13 @@ mod dma { /// [`SpiDmaBus`] via `with_buffers` to get access /// to a DMA capable SPI bus that implements the /// embedded-hal traits. - pub struct SpiDma<'d, T, C, D, M> + pub struct SpiDma<'d, T, D, M> where - C: DmaChannel, D: DuplexMode, M: Mode, { pub(crate) spi: PeripheralRef<'d, T>, - pub(crate) channel: Channel<'d, C, M>, + pub(crate) channel: Channel<'d, AnyDmaChannel, M>, tx_transfer_in_progress: bool, rx_transfer_in_progress: bool, #[cfg(all(esp32, spi_address_workaround))] @@ -1002,17 +1001,15 @@ mod dma { } #[cfg(all(esp32, spi_address_workaround))] - unsafe impl<'d, T, C, D, M> Send for SpiDma<'d, T, C, D, M> + unsafe impl<'d, T, D, M> Send for SpiDma<'d, T, D, M> where - C: DmaChannel, D: DuplexMode, M: Mode, { } - impl<'d, T, C, D, M> core::fmt::Debug for SpiDma<'d, T, C, D, M> + impl<'d, T, D, M> core::fmt::Debug for SpiDma<'d, T, D, M> where - C: DmaChannel, D: DuplexMode, M: Mode, { @@ -1025,17 +1022,16 @@ mod dma { } } - impl<'d, T, C, D, M> SpiDma<'d, T, C, D, M> + impl<'d, T, D, M> SpiDma<'d, T, D, M> where T: InstanceDma, - C: DmaChannel, D: DuplexMode, M: Mode, { - fn new(spi: PeripheralRef<'d, T>, channel: Channel<'d, C, M>) -> Self + fn new(spi: PeripheralRef<'d, T>, channel: Channel<'d, CH, M>) -> Self where - C: PeripheralDmaChannel, - C::P: SpiPeripheral, + CH: PeripheralDmaChannel, + CH::P: SpiPeripheral, { #[cfg(all(esp32, spi_address_workaround))] let address_buffer = { @@ -1055,7 +1051,7 @@ mod dma { Self { spi, - channel, + channel: channel.degrade(), #[cfg(all(esp32, spi_address_workaround))] address_buffer, tx_transfer_in_progress: false, @@ -1307,19 +1303,17 @@ mod dma { } } - impl<'d, T, C, D, M> crate::private::Sealed for SpiDma<'d, T, C, D, M> + impl<'d, T, D, M> crate::private::Sealed for SpiDma<'d, T, D, M> where T: InstanceDma, - C: DmaChannel, D: DuplexMode, M: Mode, { } - impl<'d, T, C, D, M> InterruptConfigurable for SpiDma<'d, T, C, D, M> + impl<'d, T, D, M> InterruptConfigurable for SpiDma<'d, T, D, M> where T: InstanceDma, - C: DmaChannel, D: DuplexMode, M: Mode, { @@ -1329,10 +1323,9 @@ mod dma { } } - impl<'d, T, C, D, M> SpiDma<'d, T, C, D, M> + impl<'d, T, D, M> SpiDma<'d, T, D, M> where T: InstanceDma, - C: DmaChannel, D: DuplexMode, M: Mode, { @@ -1350,7 +1343,7 @@ mod dma { self, dma_rx_buf: DmaRxBuf, dma_tx_buf: DmaTxBuf, - ) -> SpiDmaBus<'d, T, C, D, M> { + ) -> SpiDmaBus<'d, T, D, M> { SpiDmaBus::new(self, dma_rx_buf, dma_tx_buf) } } @@ -1359,25 +1352,23 @@ mod dma { /// /// This structure holds references to the SPI instance, DMA buffers, and /// transfer status. - pub struct SpiDmaTransfer<'d, T, C, D, M, Buf> + pub struct SpiDmaTransfer<'d, T, D, M, Buf> where T: InstanceDma, - C: DmaChannel, D: DuplexMode, M: Mode, { - spi_dma: ManuallyDrop>, + spi_dma: ManuallyDrop>, dma_buf: ManuallyDrop, } - impl<'d, T, C, D, M, Buf> SpiDmaTransfer<'d, T, C, D, M, Buf> + impl<'d, T, D, M, Buf> SpiDmaTransfer<'d, T, D, M, Buf> where T: InstanceDma, - C: DmaChannel, D: DuplexMode, M: Mode, { - fn new(spi_dma: SpiDma<'d, T, C, D, M>, dma_buf: Buf) -> Self { + fn new(spi_dma: SpiDma<'d, T, D, M>, dma_buf: Buf) -> Self { Self { spi_dma: ManuallyDrop::new(spi_dma), dma_buf: ManuallyDrop::new(dma_buf), @@ -1396,7 +1387,7 @@ mod dma { /// /// This method blocks until the transfer is finished and returns the /// `SpiDma` instance and the associated buffer. - pub fn wait(mut self) -> (SpiDma<'d, T, C, D, M>, Buf) { + pub fn wait(mut self) -> (SpiDma<'d, T, D, M>, Buf) { self.spi_dma.wait_for_idle(); let retval = unsafe { ( @@ -1416,10 +1407,9 @@ mod dma { } } - impl<'d, T, C, D, M, Buf> Drop for SpiDmaTransfer<'d, T, C, D, M, Buf> + impl<'d, T, D, M, Buf> Drop for SpiDmaTransfer<'d, T, D, M, Buf> where T: InstanceDma, - C: DmaChannel, D: DuplexMode, M: Mode, { @@ -1436,10 +1426,9 @@ mod dma { } } - impl<'d, T, C, D, Buf> SpiDmaTransfer<'d, T, C, D, crate::Async, Buf> + impl<'d, T, D, Buf> SpiDmaTransfer<'d, T, D, crate::Async, Buf> where T: InstanceDma, - C: DmaChannel, D: DuplexMode, { /// Waits for the DMA transfer to complete asynchronously. @@ -1450,10 +1439,9 @@ mod dma { } } - impl<'d, T, C, M> SpiDma<'d, T, C, FullDuplexMode, M> + impl<'d, T, M> SpiDma<'d, T, FullDuplexMode, M> where T: InstanceDma, - C: DmaChannel, M: Mode, { /// # Safety: @@ -1480,7 +1468,7 @@ mod dma { pub fn dma_write( mut self, mut buffer: TX, - ) -> Result, (Error, Self, TX)> { + ) -> Result, (Error, Self, TX)> { self.wait_for_idle(); match unsafe { self.start_dma_write(&mut buffer) } { @@ -1513,7 +1501,7 @@ mod dma { pub fn dma_read( mut self, mut buffer: RX, - ) -> Result, (Error, Self, RX)> { + ) -> Result, (Error, Self, RX)> { self.wait_for_idle(); match unsafe { self.start_dma_read(&mut buffer) } { Ok(_) => Ok(SpiDmaTransfer::new(self, buffer)), @@ -1552,7 +1540,7 @@ mod dma { mut self, mut rx_buffer: RX, mut tx_buffer: TX, - ) -> Result, (Error, Self, RX, TX)> + ) -> Result, (Error, Self, RX, TX)> { self.wait_for_idle(); match unsafe { self.start_dma_transfer(&mut rx_buffer, &mut tx_buffer) } { @@ -1562,10 +1550,9 @@ mod dma { } } - impl<'d, T, C, M> SpiDma<'d, T, C, HalfDuplexMode, M> + impl<'d, T, M> SpiDma<'d, T, HalfDuplexMode, M> where T: InstanceDma, - C: DmaChannel, M: Mode, { /// # Safety: @@ -1609,7 +1596,7 @@ mod dma { address: Address, dummy: u8, mut buffer: RX, - ) -> Result, (Error, Self, RX)> { + ) -> Result, (Error, Self, RX)> { self.wait_for_idle(); match unsafe { @@ -1670,7 +1657,7 @@ mod dma { address: Address, dummy: u8, mut buffer: TX, - ) -> Result, (Error, Self, TX)> { + ) -> Result, (Error, Self, TX)> { self.wait_for_idle(); match unsafe { @@ -1686,28 +1673,26 @@ mod dma { /// /// This structure is responsible for managing SPI transfers using DMA /// buffers. - pub struct SpiDmaBus<'d, T, C, D, M> + pub struct SpiDmaBus<'d, T, D, M> where T: InstanceDma, - C: DmaChannel, D: DuplexMode, M: Mode, { - spi_dma: SpiDma<'d, T, C, D, M>, + spi_dma: SpiDma<'d, T, D, M>, rx_buf: DmaRxBuf, tx_buf: DmaTxBuf, } - impl<'d, T, C, D, M> SpiDmaBus<'d, T, C, D, M> + impl<'d, T, D, M> SpiDmaBus<'d, T, D, M> where T: InstanceDma, - C: DmaChannel, D: DuplexMode, M: Mode, { /// Creates a new `SpiDmaBus` with the specified SPI instance and DMA /// buffers. - pub fn new(spi_dma: SpiDma<'d, T, C, D, M>, rx_buf: DmaRxBuf, tx_buf: DmaTxBuf) -> Self { + pub fn new(spi_dma: SpiDma<'d, T, D, M>, rx_buf: DmaRxBuf, tx_buf: DmaTxBuf) -> Self { Self { spi_dma, rx_buf, @@ -1756,10 +1741,9 @@ mod dma { } } - impl<'d, T, C, D, M> InterruptConfigurable for SpiDmaBus<'d, T, C, D, M> + impl<'d, T, D, M> InterruptConfigurable for SpiDmaBus<'d, T, D, M> where T: InstanceDma, - C: DmaChannel, D: DuplexMode, M: Mode, { @@ -1769,19 +1753,17 @@ mod dma { } } - impl<'d, T, C, D, M> crate::private::Sealed for SpiDmaBus<'d, T, C, D, M> + impl<'d, T, D, M> crate::private::Sealed for SpiDmaBus<'d, T, D, M> where T: InstanceDma, - C: DmaChannel, D: DuplexMode, M: Mode, { } - impl<'d, T, C, M> SpiDmaBus<'d, T, C, FullDuplexMode, M> + impl<'d, T, M> SpiDmaBus<'d, T, FullDuplexMode, M> where T: InstanceDma, - C: DmaChannel, M: Mode, { /// Reads data from the SPI bus using DMA. @@ -1873,10 +1855,9 @@ mod dma { } } - impl<'d, T, C, M> HalfDuplexReadWrite for SpiDmaBus<'d, T, C, HalfDuplexMode, M> + impl<'d, T, M> HalfDuplexReadWrite for SpiDmaBus<'d, T, HalfDuplexMode, M> where T: InstanceDma, - C: DmaChannel, M: Mode, { type Error = Error; @@ -1945,11 +1926,10 @@ mod dma { } } - impl<'d, T, C> embedded_hal_02::blocking::spi::Transfer - for SpiDmaBus<'d, T, C, FullDuplexMode, crate::Blocking> + impl<'d, T> embedded_hal_02::blocking::spi::Transfer + for SpiDmaBus<'d, T, FullDuplexMode, crate::Blocking> where T: InstanceDma, - C: DmaChannel, { type Error = Error; @@ -1959,11 +1939,10 @@ mod dma { } } - impl<'d, T, C> embedded_hal_02::blocking::spi::Write - for SpiDmaBus<'d, T, C, FullDuplexMode, crate::Blocking> + impl<'d, T> embedded_hal_02::blocking::spi::Write + for SpiDmaBus<'d, T, FullDuplexMode, crate::Blocking> where T: InstanceDma, - C: DmaChannel, { type Error = Error; @@ -2020,10 +1999,9 @@ mod dma { } } - impl<'d, T, C> SpiDmaBus<'d, T, C, FullDuplexMode, crate::Async> + impl<'d, T> SpiDmaBus<'d, T, FullDuplexMode, crate::Async> where T: InstanceDma, - C: DmaChannel, { /// Fill the given buffer with data from the bus. pub async fn read_async(&mut self, words: &mut [u8]) -> Result<(), Error> { @@ -2137,10 +2115,9 @@ mod dma { } } - impl<'d, T, C> embedded_hal_async::spi::SpiBus for SpiDmaBus<'d, T, C, FullDuplexMode, crate::Async> + impl<'d, T> embedded_hal_async::spi::SpiBus for SpiDmaBus<'d, T, FullDuplexMode, crate::Async> where T: InstanceDma, - C: DmaChannel, { async fn read(&mut self, words: &mut [u8]) -> Result<(), Self::Error> { self.read_async(words).await @@ -2170,19 +2147,17 @@ mod dma { use super::*; - impl<'d, T, C, M> ErrorType for SpiDmaBus<'d, T, C, FullDuplexMode, M> + impl<'d, T, M> ErrorType for SpiDmaBus<'d, T, FullDuplexMode, M> where T: InstanceDma, - C: DmaChannel, M: Mode, { type Error = Error; } - impl<'d, T, C, M> SpiBus for SpiDmaBus<'d, T, C, FullDuplexMode, M> + impl<'d, T, M> SpiBus for SpiDmaBus<'d, T, FullDuplexMode, M> where T: InstanceDma, - C: DmaChannel, M: Mode, { fn read(&mut self, words: &mut [u8]) -> Result<(), Self::Error> { diff --git a/esp-hal/src/spi/slave.rs b/esp-hal/src/spi/slave.rs index 59760e5c6a8..37fb04827fb 100644 --- a/esp-hal/src/spi/slave.rs +++ b/esp-hal/src/spi/slave.rs @@ -151,6 +151,7 @@ pub mod dma { use crate::{ dma::{ dma_private::{DmaSupport, DmaSupportRx, DmaSupportTx}, + AnyDmaChannel, Channel, ChannelRx, ChannelTx, @@ -179,18 +180,13 @@ pub mod dma { channel: Channel<'d, C, DmaMode>, rx_descriptors: &'static mut [DmaDescriptor], tx_descriptors: &'static mut [DmaDescriptor], - ) -> SpiDma<'d, crate::peripherals::SPI2, C, DmaMode> + ) -> SpiDma<'d, crate::peripherals::SPI2, DmaMode> where C: PeripheralDmaChannel, C::P: SpiPeripheral + Spi2Peripheral, DmaMode: Mode, { - SpiDma { - spi: self.spi, - channel, - rx_chain: DescriptorChain::new(rx_descriptors), - tx_chain: DescriptorChain::new(tx_descriptors), - } + SpiDma::new(self.spi, channel, rx_descriptors, tx_descriptors) } } @@ -203,36 +199,29 @@ pub mod dma { channel: Channel<'d, C, DmaMode>, rx_descriptors: &'static mut [DmaDescriptor], tx_descriptors: &'static mut [DmaDescriptor], - ) -> SpiDma<'d, crate::peripherals::SPI3, C, DmaMode> + ) -> SpiDma<'d, crate::peripherals::SPI3, DmaMode> where C: PeripheralDmaChannel, C::P: SpiPeripheral + Spi3Peripheral, DmaMode: Mode, { - SpiDma { - spi: self.spi, - channel, - rx_chain: DescriptorChain::new(rx_descriptors), - tx_chain: DescriptorChain::new(tx_descriptors), - } + SpiDma::new(self.spi, channel, rx_descriptors, tx_descriptors) } } /// A DMA capable SPI instance. - pub struct SpiDma<'d, T, C, DmaMode> + pub struct SpiDma<'d, T, DmaMode> where - C: DmaChannel, DmaMode: Mode, { pub(crate) spi: PeripheralRef<'d, T>, - pub(crate) channel: Channel<'d, C, DmaMode>, + pub(crate) channel: Channel<'d, AnyDmaChannel, DmaMode>, rx_chain: DescriptorChain, tx_chain: DescriptorChain, } - impl<'d, T, C, DmaMode> core::fmt::Debug for SpiDma<'d, T, C, DmaMode> + impl<'d, T, DmaMode> core::fmt::Debug for SpiDma<'d, T, DmaMode> where - C: DmaChannel, DmaMode: Mode, { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { @@ -240,10 +229,9 @@ pub mod dma { } } - impl<'d, T, C, DmaMode> DmaSupport for SpiDma<'d, T, C, DmaMode> + impl<'d, T, DmaMode> DmaSupport for SpiDma<'d, T, DmaMode> where - T: InstanceDma, ChannelTx<'d, C>>, - C: DmaChannel, + T: InstanceDma, ChannelTx<'d, AnyDmaChannel>>, DmaMode: Mode, { fn peripheral_wait_dma(&mut self, is_rx: bool, is_tx: bool) { @@ -260,13 +248,12 @@ pub mod dma { } } - impl<'d, T, C, DmaMode> DmaSupportTx for SpiDma<'d, T, C, DmaMode> + impl<'d, T, DmaMode> DmaSupportTx for SpiDma<'d, T, DmaMode> where - T: InstanceDma, ChannelTx<'d, C>>, - C: DmaChannel, + T: InstanceDma, ChannelTx<'d, AnyDmaChannel>>, DmaMode: Mode, { - type TX = ChannelTx<'d, C>; + type TX = ChannelTx<'d, AnyDmaChannel>; fn tx(&mut self) -> &mut Self::TX { &mut self.channel.tx @@ -277,13 +264,12 @@ pub mod dma { } } - impl<'d, T, C, DmaMode> DmaSupportRx for SpiDma<'d, T, C, DmaMode> + impl<'d, T, DmaMode> DmaSupportRx for SpiDma<'d, T, DmaMode> where - T: InstanceDma, ChannelTx<'d, C>>, - C: DmaChannel, + T: InstanceDma, ChannelTx<'d, AnyDmaChannel>>, DmaMode: Mode, { - type RX = ChannelRx<'d, C>; + type RX = ChannelRx<'d, AnyDmaChannel>; fn rx(&mut self) -> &mut Self::RX { &mut self.channel.rx @@ -294,12 +280,27 @@ pub mod dma { } } - impl<'d, T, C, DmaMode> SpiDma<'d, T, C, DmaMode> + impl<'d, T, DmaMode> SpiDma<'d, T, DmaMode> where - T: InstanceDma, ChannelTx<'d, C>>, - C: DmaChannel, + T: InstanceDma, ChannelTx<'d, AnyDmaChannel>>, DmaMode: Mode, { + fn new( + spi: PeripheralRef<'d, T>, + channel: Channel<'d, CH, DmaMode>, + rx_descriptors: &'static mut [DmaDescriptor], + tx_descriptors: &'static mut [DmaDescriptor], + ) -> Self + where + CH: DmaChannel, + { + Self { + spi, + channel: channel.degrade(), + rx_chain: DescriptorChain::new(rx_descriptors), + tx_chain: DescriptorChain::new(tx_descriptors), + } + } /// Register a buffer for a DMA write. /// /// This will return a [DmaTransferTx]. The maximum amount of data to be