From fdc1dbfa1defeda1b9d72261a8fccce0fa29b1e5 Mon Sep 17 00:00:00 2001
From: Kirill Mikhailov <62840029+playfulFence@users.noreply.github.com>
Date: Mon, 8 Jan 2024 15:00:26 +0100
Subject: [PATCH] Unify the low-power peripheral names (`RTC_CNTL` and
`LP_CLKRST` to `LPWR`) (#1064)
* WIP
* Adjusting to changes in driver
* Adding CHANGELOG entry
---
CHANGELOG.md | 3 +
esp-hal-common/src/gpio.rs | 2 +-
esp-hal-common/src/otg_fs.rs | 2 +-
esp-hal-common/src/peripheral.rs | 2 +-
esp-hal-common/src/rtc_cntl/mod.rs | 57 ++++++++-----------
esp-hal-common/src/rtc_cntl/rtc/esp32h2.rs | 10 ++--
esp-hal-common/src/soc/esp32/mod.rs | 4 +-
esp-hal-common/src/soc/esp32/peripherals.rs | 2 +-
esp-hal-common/src/soc/esp32c2/mod.rs | 4 +-
esp-hal-common/src/soc/esp32c2/peripherals.rs | 2 +-
esp-hal-common/src/soc/esp32c3/mod.rs | 4 +-
esp-hal-common/src/soc/esp32c3/peripherals.rs | 2 +-
esp-hal-common/src/soc/esp32c6/mod.rs | 4 +-
esp-hal-common/src/soc/esp32c6/peripherals.rs | 2 +-
esp-hal-common/src/soc/esp32h2/mod.rs | 4 +-
esp-hal-common/src/soc/esp32h2/peripherals.rs | 2 +-
esp-hal-common/src/soc/esp32s2/mod.rs | 4 +-
esp-hal-common/src/soc/esp32s2/peripherals.rs | 2 +-
esp-hal-common/src/soc/esp32s3/mod.rs | 4 +-
esp-hal-common/src/soc/esp32s3/peripherals.rs | 2 +-
esp-hal-common/src/timer.rs | 2 +-
esp32-hal/examples/clock_monitor.rs | 2 +-
esp32-hal/examples/ram.rs | 2 +-
esp32-hal/examples/rtc_time.rs | 2 +-
esp32-hal/examples/rtc_watchdog.rs | 2 +-
esp32-hal/examples/sleep_timer.rs | 2 +-
esp32-hal/examples/sleep_timer_ext0.rs | 2 +-
esp32-hal/examples/sleep_timer_ext1.rs | 2 +-
esp32c2-hal/examples/clock_monitor.rs | 2 +-
esp32c2-hal/examples/rtc_time.rs | 2 +-
esp32c2-hal/examples/rtc_watchdog.rs | 2 +-
esp32c3-hal/examples/clock_monitor.rs | 2 +-
esp32c3-hal/examples/ram.rs | 2 +-
esp32c3-hal/examples/rtc_time.rs | 2 +-
esp32c3-hal/examples/rtc_watchdog.rs | 2 +-
esp32c3-hal/examples/sleep_timer.rs | 2 +-
esp32c3-hal/examples/sleep_timer_rtcio.rs | 2 +-
esp32c6-hal/examples/ram.rs | 2 +-
esp32c6-hal/examples/rtc_time.rs | 2 +-
esp32c6-hal/examples/rtc_watchdog.rs | 2 +-
esp32c6-hal/examples/sleep_lpio.rs | 2 +-
esp32h2-hal/examples/ram.rs | 2 +-
esp32h2-hal/examples/rtc_time.rs | 2 +-
esp32h2-hal/examples/rtc_watchdog.rs | 2 +-
esp32s2-hal/examples/clock_monitor.rs | 2 +-
esp32s2-hal/examples/ram.rs | 2 +-
esp32s2-hal/examples/rtc_time.rs | 2 +-
esp32s2-hal/examples/rtc_watchdog.rs | 2 +-
esp32s3-hal/examples/clock_monitor.rs | 2 +-
esp32s3-hal/examples/ram.rs | 2 +-
esp32s3-hal/examples/rtc_time.rs | 2 +-
esp32s3-hal/examples/rtc_watchdog.rs | 2 +-
esp32s3-hal/examples/sleep_timer.rs | 2 +-
esp32s3-hal/examples/sleep_timer_ext0.rs | 2 +-
esp32s3-hal/examples/sleep_timer_ext1.rs | 2 +-
esp32s3-hal/examples/sleep_timer_rtcio.rs | 2 +-
56 files changed, 92 insertions(+), 98 deletions(-)
diff --git a/CHANGELOG.md b/CHANGELOG.md
index 037c5da5251..f892e8b5672 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -24,6 +24,9 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
### Removed
+### Breaking
+- Unify the low-power peripheral names (`RTC_CNTL` and `LP_CLKRST` to `LPWR`) (#1064)
+
## [0.14.1] - 2023-12-13
### Fixed
diff --git a/esp-hal-common/src/gpio.rs b/esp-hal-common/src/gpio.rs
index cd767162c30..ec2a90da4fa 100644
--- a/esp-hal-common/src/gpio.rs
+++ b/esp-hal-common/src/gpio.rs
@@ -1691,7 +1691,7 @@ macro_rules! rtc_pins {
}
fn rtcio_pad_hold(&mut self, enable: bool) {
- let rtc_ctrl = unsafe { &*crate::peripherals::RTC_CNTL::PTR };
+ let rtc_ctrl = unsafe { &*crate::peripherals::LPWR::PTR };
#[cfg(esp32)]
rtc_ctrl.hold_force().modify(|_, w| w.$hold().bit(enable));
diff --git a/esp-hal-common/src/otg_fs.rs b/esp-hal-common/src/otg_fs.rs
index 2323d1b3a5c..16e1a76361b 100644
--- a/esp-hal-common/src/otg_fs.rs
+++ b/esp-hal-common/src/otg_fs.rs
@@ -110,7 +110,7 @@ where
#[cfg(esp32s3)]
{
- let rtc = &*peripherals::RTC_CNTL::PTR;
+ let rtc = &*peripherals::LPWR::PTR;
rtc.usb_conf()
.modify(|_, w| w.sw_hw_usb_phy_sel().set_bit().sw_usb_phy_sel().set_bit());
}
diff --git a/esp-hal-common/src/peripheral.rs b/esp-hal-common/src/peripheral.rs
index 4f0d566cc8f..53e85c38575 100644
--- a/esp-hal-common/src/peripheral.rs
+++ b/esp-hal-common/src/peripheral.rs
@@ -29,7 +29,7 @@
//! ```
//! ### Accessing peripherals
//! ```no_run
-//! let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+//! let mut rtc = Rtc::new(peripherals.LPWR);
//! ```
//! ```no_run
//! let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
diff --git a/esp-hal-common/src/rtc_cntl/mod.rs b/esp-hal-common/src/rtc_cntl/mod.rs
index a29b23d47a8..d2411b01da6 100644
--- a/esp-hal-common/src/rtc_cntl/mod.rs
+++ b/esp-hal-common/src/rtc_cntl/mod.rs
@@ -79,10 +79,10 @@ pub use self::rtc::SocResetReason;
use crate::clock::XtalClock;
#[cfg(not(esp32))]
use crate::efuse::Efuse;
+#[cfg(not(any(esp32c6, esp32h2)))]
+use crate::peripherals::{LPWR, TIMG0};
#[cfg(any(esp32c6, esp32h2))]
use crate::peripherals::{LP_TIMER, LP_WDT};
-#[cfg(not(any(esp32c6, esp32h2)))]
-use crate::peripherals::{RTC_CNTL, TIMG0};
#[cfg(any(esp32, esp32s3, esp32c3, esp32c6))]
use crate::rtc_cntl::sleep::{RtcSleepConfig, WakeSource, WakeTriggers};
use crate::{
@@ -95,11 +95,6 @@ use crate::{
#[cfg(any(esp32, esp32s3, esp32c3, esp32c6))]
pub mod sleep;
-#[cfg(any(esp32c6, esp32h2))]
-type RtcCntl = crate::peripherals::LP_CLKRST;
-#[cfg(not(any(esp32c6, esp32h2)))]
-type RtcCntl = crate::peripherals::RTC_CNTL;
-
#[cfg_attr(esp32, path = "rtc/esp32.rs")]
#[cfg_attr(esp32c2, path = "rtc/esp32c2.rs")]
#[cfg_attr(esp32c3, path = "rtc/esp32c3.rs")]
@@ -194,14 +189,14 @@ pub(crate) enum RtcCalSel {
/// Low-power Management
pub struct Rtc<'d> {
- _inner: PeripheralRef<'d, RtcCntl>,
+ _inner: PeripheralRef<'d, crate::peripherals::LPWR>,
pub rwdt: Rwdt,
#[cfg(any(esp32c2, esp32c3, esp32c6, esp32h2, esp32s3))]
pub swd: Swd,
}
impl<'d> Rtc<'d> {
- pub fn new(rtc_cntl: impl Peripheral + 'd) -> Self {
+ pub fn new(rtc_cntl: impl Peripheral
+ 'd) -> Self {
rtc::init();
rtc::configure_clock();
@@ -227,7 +222,7 @@ impl<'d> Rtc<'d> {
/// read the current value of the rtc time registers.
pub fn get_time_raw(&self) -> u64 {
#[cfg(not(any(esp32c6, esp32h2)))]
- let rtc_cntl = unsafe { &*RTC_CNTL::ptr() };
+ let rtc_cntl = unsafe { &*LPWR::ptr() };
#[cfg(any(esp32c6, esp32h2))]
let rtc_cntl = unsafe { &*LP_TIMER::ptr() };
@@ -346,7 +341,7 @@ impl RtcClock {
/// disabled to reduce power consumption.
#[cfg(not(any(esp32c6, esp32h2)))]
fn enable_8m(clk_8m_en: bool, d256_en: bool) {
- let rtc_cntl = unsafe { &*RTC_CNTL::PTR };
+ let rtc_cntl = unsafe { &*LPWR::PTR };
if clk_8m_en {
rtc_cntl.clk_conf().modify(|_, w| w.enb_ck8m().clear_bit());
@@ -376,7 +371,7 @@ impl RtcClock {
/// This is the value stored in RTC register RTC_XTAL_FREQ_REG by the
/// bootloader, as passed to rtc_clk_init function.
pub fn get_xtal_freq() -> XtalClock {
- let xtal_freq_reg = unsafe { &*RTC_CNTL::PTR }.store4().read().bits();
+ let xtal_freq_reg = unsafe { &*LPWR::PTR }.store4().read().bits();
// Values of RTC_XTAL_FREQ_REG and RTC_APB_FREQ_REG are stored as two copies in
// lower and upper 16-bit halves. These are the routines to work with such a
@@ -405,7 +400,7 @@ impl RtcClock {
/// Get the RTC_SLOW_CLK source
#[cfg(not(any(esp32c6, esp32h2)))]
pub fn get_slow_freq() -> RtcSlowClock {
- let rtc_cntl = unsafe { &*RTC_CNTL::PTR };
+ let rtc_cntl = unsafe { &*LPWR::PTR };
let slow_freq = rtc_cntl.clk_conf().read().ana_clk_rtc_sel().bits();
match slow_freq {
0 => RtcSlowClock::RtcSlowClockRtc,
@@ -419,7 +414,7 @@ impl RtcClock {
#[cfg(not(any(esp32c6, esp32h2)))]
fn set_slow_freq(slow_freq: RtcSlowClock) {
unsafe {
- let rtc_cntl = &*RTC_CNTL::PTR;
+ let rtc_cntl = &*LPWR::PTR;
rtc_cntl.clk_conf().modify(|_, w| {
w.ana_clk_rtc_sel()
.bits(slow_freq as u8)
@@ -448,7 +443,7 @@ impl RtcClock {
#[cfg(not(any(esp32c6, esp32h2)))]
fn set_fast_freq(fast_freq: RtcFastClock) {
unsafe {
- let rtc_cntl = &*RTC_CNTL::PTR;
+ let rtc_cntl = &*LPWR::PTR;
rtc_cntl.clk_conf().modify(|_, w| {
w.fast_clk_rtc_sel().bit(match fast_freq {
RtcFastClock::RtcFastClock8m => true,
@@ -479,7 +474,7 @@ impl RtcClock {
RtcCalSel::RtcCalInternalOsc => RtcCalSel::RtcCalRtcMux,
_ => cal_clk,
};
- let rtc_cntl = unsafe { &*RTC_CNTL::PTR };
+ let rtc_cntl = unsafe { &*LPWR::PTR };
let timg0 = unsafe { &*TIMG0::PTR };
// Enable requested clock (150k clock is always on)
@@ -656,7 +651,7 @@ impl RtcClock {
// Number of 8M/256 clock cycles to use for XTAL frequency estimation.
const XTAL_FREQ_EST_CYCLES: u32 = 10;
- let rtc_cntl = unsafe { &*RTC_CNTL::PTR };
+ let rtc_cntl = unsafe { &*LPWR::PTR };
let clk_8m_enabled = rtc_cntl.clk_conf().read().enb_ck8m().bit_is_clear();
let clk_8md256_enabled = rtc_cntl.clk_conf().read().enb_ck8m_div().bit_is_clear();
@@ -719,7 +714,7 @@ impl Rwdt {
pub fn listen(&mut self) {
#[cfg(not(any(esp32c6, esp32h2)))]
- let rtc_cntl = unsafe { &*RTC_CNTL::PTR };
+ let rtc_cntl = unsafe { &*LPWR::PTR };
#[cfg(any(esp32c6, esp32h2))]
let rtc_cntl = unsafe { &*LP_WDT::PTR };
@@ -744,7 +739,7 @@ impl Rwdt {
pub fn unlisten(&mut self) {
#[cfg(not(any(esp32c6, esp32h2)))]
- let rtc_cntl = unsafe { &*RTC_CNTL::PTR };
+ let rtc_cntl = unsafe { &*LPWR::PTR };
#[cfg(any(esp32c6, esp32h2))]
let rtc_cntl = unsafe { &*LP_WDT::PTR };
@@ -771,7 +766,7 @@ impl Rwdt {
pub fn clear_interrupt(&mut self) {
#[cfg(not(any(esp32c6, esp32h2)))]
- let rtc_cntl = unsafe { &*RTC_CNTL::PTR };
+ let rtc_cntl = unsafe { &*LPWR::PTR };
#[cfg(any(esp32c6, esp32h2))]
let rtc_cntl = unsafe { &*LP_WDT::PTR };
@@ -787,7 +782,7 @@ impl Rwdt {
pub fn is_interrupt_set(&self) -> bool {
#[cfg(not(any(esp32c6, esp32h2)))]
- let rtc_cntl = unsafe { &*RTC_CNTL::PTR };
+ let rtc_cntl = unsafe { &*LPWR::PTR };
#[cfg(any(esp32c6, esp32h2))]
let rtc_cntl = unsafe { &*LP_WDT::PTR };
@@ -802,7 +797,7 @@ impl Rwdt {
pub fn feed(&mut self) {
#[cfg(not(any(esp32c6, esp32h2)))]
- let rtc_cntl = unsafe { &*RTC_CNTL::PTR };
+ let rtc_cntl = unsafe { &*LPWR::PTR };
#[cfg(any(esp32c6, esp32h2))]
let rtc_cntl = unsafe { &*LP_WDT::PTR };
@@ -813,7 +808,7 @@ impl Rwdt {
fn set_write_protection(&mut self, enable: bool) {
#[cfg(not(any(esp32c6, esp32h2)))]
- let rtc_cntl = unsafe { &*RTC_CNTL::PTR };
+ let rtc_cntl = unsafe { &*LPWR::PTR };
#[cfg(any(esp32c6, esp32h2))]
let rtc_cntl = unsafe { &*LP_WDT::PTR };
@@ -824,7 +819,7 @@ impl Rwdt {
fn set_enabled(&mut self, enable: bool) {
#[cfg(not(any(esp32c6, esp32h2)))]
- let rtc_cntl = unsafe { &*RTC_CNTL::PTR };
+ let rtc_cntl = unsafe { &*LPWR::PTR };
#[cfg(any(esp32c6, esp32h2))]
let rtc_cntl = unsafe { &*LP_WDT::PTR };
@@ -839,7 +834,7 @@ impl Rwdt {
fn set_timeout(&mut self, timeout: MicrosDurationU64) {
#[cfg(not(any(esp32c6, esp32h2)))]
- let rtc_cntl = unsafe { &*RTC_CNTL::PTR };
+ let rtc_cntl = unsafe { &*LPWR::PTR };
#[cfg(any(esp32c6, esp32h2))]
let rtc_cntl = unsafe { &*LP_WDT::PTR };
@@ -929,7 +924,7 @@ impl Swd {
/// Enable/disable write protection for WDT registers
fn set_write_protection(&mut self, enable: bool) {
#[cfg(not(any(esp32c6, esp32h2)))]
- let rtc_cntl = unsafe { &*RTC_CNTL::PTR };
+ let rtc_cntl = unsafe { &*LPWR::PTR };
#[cfg(any(esp32c6, esp32h2))]
let rtc_cntl = unsafe { &*LP_WDT::PTR };
@@ -945,7 +940,7 @@ impl Swd {
fn set_enabled(&mut self, enable: bool) {
#[cfg(not(any(esp32c6, esp32h2)))]
- let rtc_cntl = unsafe { &*RTC_CNTL::PTR };
+ let rtc_cntl = unsafe { &*LPWR::PTR };
#[cfg(any(esp32c6, esp32h2))]
let rtc_cntl = unsafe { &*LP_WDT::PTR };
@@ -986,7 +981,7 @@ pub fn get_wakeup_cause() -> SleepSource {
});
#[cfg(not(any(esp32, esp32c6, esp32h2)))]
let wakeup_cause = WakeupReason::from_bits_retain(unsafe {
- (&*RTC_CNTL::PTR)
+ (&*LPWR::PTR)
.slp_wakeup_cause()
.read()
.wakeup_cause()
@@ -994,11 +989,7 @@ pub fn get_wakeup_cause() -> SleepSource {
});
#[cfg(esp32)]
let wakeup_cause = WakeupReason::from_bits_retain(unsafe {
- (&*RTC_CNTL::PTR)
- .wakeup_state()
- .read()
- .wakeup_cause()
- .bits() as u32
+ (&*LPWR::PTR).wakeup_state().read().wakeup_cause().bits() as u32
});
if wakeup_cause.contains(WakeupReason::TimerTrigEn) {
diff --git a/esp-hal-common/src/rtc_cntl/rtc/esp32h2.rs b/esp-hal-common/src/rtc_cntl/rtc/esp32h2.rs
index cf0dcf7a170..8cee82c1aa2 100644
--- a/esp-hal-common/src/rtc_cntl/rtc/esp32h2.rs
+++ b/esp-hal-common/src/rtc_cntl/rtc/esp32h2.rs
@@ -3,7 +3,7 @@ use strum::FromRepr;
use crate::{
clock::{clocks_ll::regi2c_write_mask, Clock, XtalClock},
- peripherals::{LP_AON, LP_CLKRST, PCR, PMU, TIMG0},
+ peripherals::{LPWR, LP_AON, PCR, PMU, TIMG0},
};
const I2C_PMU: u8 = 0x6d;
@@ -306,7 +306,7 @@ impl RtcClock {
fn set_fast_freq(fast_freq: RtcFastClock) {
// components/hal/esp32s2/include/hal/clk_tree_ll.h
unsafe {
- let lp_clkrst = &*LP_CLKRST::PTR;
+ let lp_clkrst = &*LPWR::PTR;
lp_clkrst.lp_clk_conf().modify(|_, w| {
w.fast_clk_sel().bits(match fast_freq {
RtcFastClock::RtcFastClockRcFast => 0b00,
@@ -319,7 +319,7 @@ impl RtcClock {
fn set_slow_freq(slow_freq: RtcSlowClock) {
unsafe {
- let lp_clkrst = &*LP_CLKRST::PTR;
+ let lp_clkrst = &*LPWR::PTR;
lp_clkrst
.lp_clk_conf()
@@ -341,7 +341,7 @@ impl RtcClock {
/// Get the RTC_SLOW_CLK source
pub(crate) fn get_slow_freq() -> RtcSlowClock {
- let lp_clrst = unsafe { &*LP_CLKRST::ptr() };
+ let lp_clrst = unsafe { &*LPWR::ptr() };
let slow_freq = lp_clrst.lp_clk_conf().read().slow_clk_sel().bits();
match slow_freq {
@@ -382,7 +382,7 @@ impl RtcClock {
};
}
- let lp_clkrst = unsafe { &*LP_CLKRST::ptr() };
+ let lp_clkrst = unsafe { &*LPWR::ptr() };
let pcr = unsafe { &*PCR::ptr() };
let pmu = unsafe { &*PMU::ptr() };
diff --git a/esp-hal-common/src/soc/esp32/mod.rs b/esp-hal-common/src/soc/esp32/mod.rs
index bb31a02bcb8..697a4bc5d37 100644
--- a/esp-hal-common/src/soc/esp32/mod.rs
+++ b/esp-hal-common/src/soc/esp32/mod.rs
@@ -5,7 +5,7 @@
//! The `SOC` module provides access, functions and structures that are useful
//! for interacting with various system-related peripherals on `ESP32` chip.
-use self::peripherals::{RTC_CNTL, TIMG0, TIMG1};
+use self::peripherals::{LPWR, TIMG0, TIMG1};
use crate::{timer::Wdt, Rtc};
pub mod cpu_control;
@@ -74,7 +74,7 @@ pub extern "Rust" fn __init_data() -> bool {
#[export_name = "__post_init"]
unsafe fn post_init() {
// RTC domain must be enabled before we try to disable
- let mut rtc = Rtc::new(RTC_CNTL::steal());
+ let mut rtc = Rtc::new(LPWR::steal());
rtc.rwdt.disable();
Wdt::::set_wdt_enabled(false);
diff --git a/esp-hal-common/src/soc/esp32/peripherals.rs b/esp-hal-common/src/soc/esp32/peripherals.rs
index 5f334ce5afa..5b8d2eda3b3 100644
--- a/esp-hal-common/src/soc/esp32/peripherals.rs
+++ b/esp-hal-common/src/soc/esp32/peripherals.rs
@@ -51,7 +51,7 @@ crate::peripherals! {
RMT <= RMT,
RNG <= RNG,
RSA <= RSA,
- RTC_CNTL <= RTC_CNTL,
+ LPWR <= RTC_CNTL,
RTC_IO <= RTC_IO,
RTC_I2C <= RTC_I2C,
SDHOST <= SDHOST,
diff --git a/esp-hal-common/src/soc/esp32c2/mod.rs b/esp-hal-common/src/soc/esp32c2/mod.rs
index 2cb4ea54dbf..da9c81e7491 100644
--- a/esp-hal-common/src/soc/esp32c2/mod.rs
+++ b/esp-hal-common/src/soc/esp32c2/mod.rs
@@ -5,7 +5,7 @@
//! The `SOC` module provides access, functions and structures that are useful
//! for interacting with various system-related peripherals on `ESP32-C2` chip.
-use self::peripherals::{RTC_CNTL, TIMG0};
+use self::peripherals::{LPWR, TIMG0};
use crate::{timer::Wdt, Rtc};
pub mod efuse;
@@ -25,7 +25,7 @@ pub(crate) mod constants {
#[export_name = "__post_init"]
unsafe fn post_init() {
// RTC domain must be enabled before we try to disable
- let mut rtc = Rtc::new(RTC_CNTL::steal());
+ let mut rtc = Rtc::new(LPWR::steal());
rtc.swd.disable();
rtc.rwdt.disable();
diff --git a/esp-hal-common/src/soc/esp32c2/peripherals.rs b/esp-hal-common/src/soc/esp32c2/peripherals.rs
index 72da6e943a0..5f07a5afefd 100644
--- a/esp-hal-common/src/soc/esp32c2/peripherals.rs
+++ b/esp-hal-common/src/soc/esp32c2/peripherals.rs
@@ -40,8 +40,8 @@ crate::peripherals! {
INTERRUPT_CORE0 <= INTERRUPT_CORE0,
IO_MUX <= IO_MUX,
LEDC <= LEDC,
+ LPWR <= RTC_CNTL,
RNG <= RNG,
- RTC_CNTL <= RTC_CNTL,
SENSITIVE <= SENSITIVE,
SHA <= SHA,
SPI0 <= SPI0,
diff --git a/esp-hal-common/src/soc/esp32c3/mod.rs b/esp-hal-common/src/soc/esp32c3/mod.rs
index 3f0a89a79f1..a84c0c94ba6 100644
--- a/esp-hal-common/src/soc/esp32c3/mod.rs
+++ b/esp-hal-common/src/soc/esp32c3/mod.rs
@@ -9,7 +9,7 @@
//! * I2S_SCLK: 160_000_000 - I2S clock frequency
//! * I2S_DEFAULT_CLK_SRC: 2 - I2S clock source
-use self::peripherals::{RTC_CNTL, TIMG0, TIMG1};
+use self::peripherals::{LPWR, TIMG0, TIMG1};
use crate::{timer::Wdt, Rtc};
pub mod efuse;
@@ -37,7 +37,7 @@ pub(crate) mod constants {
#[export_name = "__post_init"]
unsafe fn post_init() {
// RTC domain must be enabled before we try to disable
- let mut rtc = Rtc::new(RTC_CNTL::steal());
+ let mut rtc = Rtc::new(LPWR::steal());
rtc.swd.disable();
rtc.rwdt.disable();
diff --git a/esp-hal-common/src/soc/esp32c3/peripherals.rs b/esp-hal-common/src/soc/esp32c3/peripherals.rs
index 88649eb18a9..63d554dc97e 100644
--- a/esp-hal-common/src/soc/esp32c3/peripherals.rs
+++ b/esp-hal-common/src/soc/esp32c3/peripherals.rs
@@ -44,10 +44,10 @@ crate::peripherals! {
INTERRUPT_CORE0 <= INTERRUPT_CORE0,
IO_MUX <= IO_MUX,
LEDC <= LEDC,
+ LPWR <= RTC_CNTL,
RMT <= RMT,
RNG <= RNG,
RSA <= RSA,
- RTC_CNTL <= RTC_CNTL,
SENSITIVE <= SENSITIVE,
SHA <= SHA,
SPI0 <= SPI0,
diff --git a/esp-hal-common/src/soc/esp32c6/mod.rs b/esp-hal-common/src/soc/esp32c6/mod.rs
index b0eb6b248f9..28a757cea61 100644
--- a/esp-hal-common/src/soc/esp32c6/mod.rs
+++ b/esp-hal-common/src/soc/esp32c6/mod.rs
@@ -10,7 +10,7 @@
//! * I2S_DEFAULT_CLK_SRC: 2 - I2S clock source
//! * I2S_SCLK: 160_000_000 - I2S clock frequency
-use self::peripherals::{LP_CLKRST, TIMG0, TIMG1};
+use self::peripherals::{LPWR, TIMG0, TIMG1};
use crate::{timer::Wdt, Rtc};
pub mod efuse;
@@ -43,7 +43,7 @@ pub(crate) mod constants {
#[export_name = "__post_init"]
unsafe fn post_init() {
// RTC domain must be enabled before we try to disable
- let mut rtc = Rtc::new(LP_CLKRST::steal());
+ let mut rtc = Rtc::new(LPWR::steal());
rtc.swd.disable();
rtc.rwdt.disable();
diff --git a/esp-hal-common/src/soc/esp32c6/peripherals.rs b/esp-hal-common/src/soc/esp32c6/peripherals.rs
index 898b72446f2..ed256dcfce0 100644
--- a/esp-hal-common/src/soc/esp32c6/peripherals.rs
+++ b/esp-hal-common/src/soc/esp32c6/peripherals.rs
@@ -50,12 +50,12 @@ crate::peripherals! {
INTPRI <= INTPRI,
IO_MUX <= IO_MUX,
LEDC <= LEDC,
+ LPWR <= LP_CLKRST,
LP_PERI <= LP_PERI,
LP_ANA <= LP_ANA,
LP_AON <= LP_AON,
LP_APM <= LP_APM,
LP_APM0 <= LP_APM0,
- LP_CLKRST <= LP_CLKRST,
LP_I2C0 <= LP_I2C0,
LP_I2C_ANA_MST <= LP_I2C_ANA_MST,
LP_IO <= LP_IO,
diff --git a/esp-hal-common/src/soc/esp32h2/mod.rs b/esp-hal-common/src/soc/esp32h2/mod.rs
index 04be9c9d79f..b367042d63d 100644
--- a/esp-hal-common/src/soc/esp32h2/mod.rs
+++ b/esp-hal-common/src/soc/esp32h2/mod.rs
@@ -10,7 +10,7 @@
//! * I2S_DEFAULT_CLK_SRC: 1 - I2S clock source
//! * I2S_SCLK: 96_000_000 - I2S clock frequency
-use self::peripherals::{LP_CLKRST, TIMG0, TIMG1};
+use self::peripherals::{LPWR, TIMG0, TIMG1};
use crate::{timer::Wdt, Rtc};
pub mod efuse;
@@ -42,7 +42,7 @@ pub(crate) mod constants {
#[export_name = "__post_init"]
unsafe fn post_init() {
// RTC domain must be enabled before we try to disable
- let mut rtc = Rtc::new(LP_CLKRST::steal());
+ let mut rtc = Rtc::new(LPWR::steal());
rtc.swd.disable();
rtc.rwdt.disable();
diff --git a/esp-hal-common/src/soc/esp32h2/peripherals.rs b/esp-hal-common/src/soc/esp32h2/peripherals.rs
index 714958914f5..89166af5c81 100644
--- a/esp-hal-common/src/soc/esp32h2/peripherals.rs
+++ b/esp-hal-common/src/soc/esp32h2/peripherals.rs
@@ -47,10 +47,10 @@ crate::peripherals! {
INTPRI <= INTPRI,
IO_MUX <= IO_MUX,
LEDC <= LEDC,
+ LPWR <= LP_CLKRST,
LP_ANA <= LP_ANA,
LP_AON <= LP_AON,
LP_APM <= LP_APM,
- LP_CLKRST <= LP_CLKRST,
LP_PERI <= LP_PERI,
LP_TIMER <= LP_TIMER,
LP_WDT <= LP_WDT,
diff --git a/esp-hal-common/src/soc/esp32s2/mod.rs b/esp-hal-common/src/soc/esp32s2/mod.rs
index a1b35e99041..656ef673a1e 100644
--- a/esp-hal-common/src/soc/esp32s2/mod.rs
+++ b/esp-hal-common/src/soc/esp32s2/mod.rs
@@ -9,7 +9,7 @@
//! * I2S_SCLK: 160_000_000 - I2S clock frequency
//! * I2S_DEFAULT_CLK_SRC: 2 - I2S clock source
-use self::peripherals::{RTC_CNTL, TIMG0, TIMG1};
+use self::peripherals::{LPWR, TIMG0, TIMG1};
use crate::{timer::Wdt, Rtc};
pub mod efuse;
@@ -78,7 +78,7 @@ pub extern "Rust" fn __init_data() -> bool {
#[export_name = "__post_init"]
unsafe fn post_init() {
// RTC domain must be enabled before we try to disable
- let mut rtc = Rtc::new(RTC_CNTL::steal());
+ let mut rtc = Rtc::new(LPWR::steal());
rtc.rwdt.disable();
Wdt::::set_wdt_enabled(false);
diff --git a/esp-hal-common/src/soc/esp32s2/peripherals.rs b/esp-hal-common/src/soc/esp32s2/peripherals.rs
index 76443d034c0..7d114c5caae 100644
--- a/esp-hal-common/src/soc/esp32s2/peripherals.rs
+++ b/esp-hal-common/src/soc/esp32s2/peripherals.rs
@@ -44,13 +44,13 @@ crate::peripherals! {
INTERRUPT_CORE0 <= INTERRUPT_CORE0,
IO_MUX <= IO_MUX,
LEDC <= LEDC,
+ LPWR <= RTC_CNTL,
PCNT <= PCNT,
PMS <= PMS,
RMT <= RMT,
RNG <= RNG,
RSA <= RSA,
RTC_IO <= RTC_IO,
- RTC_CNTL <= RTC_CNTL,
RTC_I2C <= RTC_I2C,
SENS <= SENS,
SHA <= SHA,
diff --git a/esp-hal-common/src/soc/esp32s3/mod.rs b/esp-hal-common/src/soc/esp32s3/mod.rs
index 1ff65941861..9c3c52fe79a 100644
--- a/esp-hal-common/src/soc/esp32s3/mod.rs
+++ b/esp-hal-common/src/soc/esp32s3/mod.rs
@@ -9,7 +9,7 @@
//! * I2S_SCLK: 160_000_000 - I2S clock frequency
//! * I2S_DEFAULT_CLK_SRC: 2 - I2S clock source
-use self::peripherals::{RTC_CNTL, TIMG0, TIMG1};
+use self::peripherals::{LPWR, TIMG0, TIMG1};
use crate::{timer::Wdt, Rtc};
pub mod cpu_control;
@@ -113,7 +113,7 @@ pub extern "Rust" fn __init_data() -> bool {
#[export_name = "__post_init"]
unsafe fn post_init() {
// RTC domain must be enabled before we try to disable
- let mut rtc = Rtc::new(RTC_CNTL::steal());
+ let mut rtc = Rtc::new(LPWR::steal());
rtc.rwdt.disable();
Wdt::::set_wdt_enabled(false);
diff --git a/esp-hal-common/src/soc/esp32s3/peripherals.rs b/esp-hal-common/src/soc/esp32s3/peripherals.rs
index 846bef689b0..8eaa7ef038d 100644
--- a/esp-hal-common/src/soc/esp32s3/peripherals.rs
+++ b/esp-hal-common/src/soc/esp32s3/peripherals.rs
@@ -49,6 +49,7 @@ crate::peripherals! {
IO_MUX <= IO_MUX,
LCD_CAM <= LCD_CAM,
LEDC <= LEDC,
+ LPWR <= RTC_CNTL,
PCNT <= PCNT,
PERI_BACKUP <= PERI_BACKUP,
MCPWM0 <= MCPWM0,
@@ -56,7 +57,6 @@ crate::peripherals! {
RMT <= RMT,
RNG <= RNG,
RSA <= RSA,
- RTC_CNTL <= RTC_CNTL,
RTC_I2C <= RTC_I2C,
RTC_IO <= RTC_IO,
SENS <= SENS,
diff --git a/esp-hal-common/src/timer.rs b/esp-hal-common/src/timer.rs
index 10483f2e64b..e46250019ac 100644
--- a/esp-hal-common/src/timer.rs
+++ b/esp-hal-common/src/timer.rs
@@ -18,7 +18,7 @@
//! ## Example
//!
//! ```no_run
-//! let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+//! let mut rtc = Rtc::new(peripherals.LPWR);
//!
//! // Create timer groups
//! let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
diff --git a/esp32-hal/examples/clock_monitor.rs b/esp32-hal/examples/clock_monitor.rs
index 56aa2190fdd..931cfa31ea7 100644
--- a/esp32-hal/examples/clock_monitor.rs
+++ b/esp32-hal/examples/clock_monitor.rs
@@ -25,7 +25,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+ let mut rtc = Rtc::new(peripherals.LPWR);
rtc.rwdt.start(2000u64.millis());
rtc.rwdt.listen();
diff --git a/esp32-hal/examples/ram.rs b/esp32-hal/examples/ram.rs
index 332d8823d5d..a76d8107fde 100644
--- a/esp32-hal/examples/ram.rs
+++ b/esp32-hal/examples/ram.rs
@@ -40,7 +40,7 @@ fn main() -> ! {
// The RWDT flash boot protection must be enabled, as it is triggered as part of
// the example.
- let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+ let mut rtc = Rtc::new(peripherals.LPWR);
rtc.rwdt.enable();
timer0.start(1u64.secs());
diff --git a/esp32-hal/examples/rtc_time.rs b/esp32-hal/examples/rtc_time.rs
index 627a81e9cf7..e0ff2da49f8 100644
--- a/esp32-hal/examples/rtc_time.rs
+++ b/esp32-hal/examples/rtc_time.rs
@@ -12,7 +12,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let rtc = Rtc::new(peripherals.RTC_CNTL);
+ let rtc = Rtc::new(peripherals.LPWR);
let mut delay = Delay::new(&clocks);
diff --git a/esp32-hal/examples/rtc_watchdog.rs b/esp32-hal/examples/rtc_watchdog.rs
index 422a92a5dab..e531b6a02e7 100644
--- a/esp32-hal/examples/rtc_watchdog.rs
+++ b/esp32-hal/examples/rtc_watchdog.rs
@@ -27,7 +27,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let _clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+ let mut rtc = Rtc::new(peripherals.LPWR);
rtc.rwdt.start(2000u64.millis());
rtc.rwdt.listen();
diff --git a/esp32-hal/examples/sleep_timer.rs b/esp32-hal/examples/sleep_timer.rs
index f0332093c27..691b442cdad 100644
--- a/esp32-hal/examples/sleep_timer.rs
+++ b/esp32-hal/examples/sleep_timer.rs
@@ -24,7 +24,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+ let mut rtc = Rtc::new(peripherals.LPWR);
println!("up and runnning!");
let reason = get_reset_reason(Cpu::ProCpu).unwrap_or(SocResetReason::ChipPowerOn);
diff --git a/esp32-hal/examples/sleep_timer_ext0.rs b/esp32-hal/examples/sleep_timer_ext0.rs
index b1b2ced121f..72a6399984c 100644
--- a/esp32-hal/examples/sleep_timer_ext0.rs
+++ b/esp32-hal/examples/sleep_timer_ext0.rs
@@ -30,7 +30,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+ let mut rtc = Rtc::new(peripherals.LPWR);
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
let mut ext0_pin = io.pins.gpio27;
diff --git a/esp32-hal/examples/sleep_timer_ext1.rs b/esp32-hal/examples/sleep_timer_ext1.rs
index 594e7d70f92..aa9559bb699 100644
--- a/esp32-hal/examples/sleep_timer_ext1.rs
+++ b/esp32-hal/examples/sleep_timer_ext1.rs
@@ -30,7 +30,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+ let mut rtc = Rtc::new(peripherals.LPWR);
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
let mut pin27 = io.pins.gpio27;
diff --git a/esp32c2-hal/examples/clock_monitor.rs b/esp32c2-hal/examples/clock_monitor.rs
index 084e89ecee6..cb7589c21a0 100644
--- a/esp32c2-hal/examples/clock_monitor.rs
+++ b/esp32c2-hal/examples/clock_monitor.rs
@@ -25,7 +25,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+ let mut rtc = Rtc::new(peripherals.LPWR);
rtc.rwdt.start(2000u64.millis());
rtc.rwdt.listen();
diff --git a/esp32c2-hal/examples/rtc_time.rs b/esp32c2-hal/examples/rtc_time.rs
index f45eb287cbe..400abbf3b8f 100644
--- a/esp32c2-hal/examples/rtc_time.rs
+++ b/esp32c2-hal/examples/rtc_time.rs
@@ -12,7 +12,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let rtc = Rtc::new(peripherals.RTC_CNTL);
+ let rtc = Rtc::new(peripherals.LPWR);
let mut delay = Delay::new(&clocks);
loop {
diff --git a/esp32c2-hal/examples/rtc_watchdog.rs b/esp32c2-hal/examples/rtc_watchdog.rs
index b25f00639f9..aeb2df90317 100644
--- a/esp32c2-hal/examples/rtc_watchdog.rs
+++ b/esp32c2-hal/examples/rtc_watchdog.rs
@@ -27,7 +27,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let _clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+ let mut rtc = Rtc::new(peripherals.LPWR);
rtc.rwdt.start(2000u64.millis());
rtc.rwdt.listen();
diff --git a/esp32c3-hal/examples/clock_monitor.rs b/esp32c3-hal/examples/clock_monitor.rs
index 6c793ca380f..2069e5ac4b0 100644
--- a/esp32c3-hal/examples/clock_monitor.rs
+++ b/esp32c3-hal/examples/clock_monitor.rs
@@ -25,7 +25,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+ let mut rtc = Rtc::new(peripherals.LPWR);
rtc.rwdt.start(2000u64.millis());
rtc.rwdt.listen();
diff --git a/esp32c3-hal/examples/ram.rs b/esp32c3-hal/examples/ram.rs
index a0abf052984..571f6efb45e 100644
--- a/esp32c3-hal/examples/ram.rs
+++ b/esp32c3-hal/examples/ram.rs
@@ -40,7 +40,7 @@ fn main() -> ! {
// The RWDT flash boot protection must be enabled, as it is triggered as part of
// the example.
- let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+ let mut rtc = Rtc::new(peripherals.LPWR);
rtc.rwdt.enable();
timer0.start(1u64.secs());
diff --git a/esp32c3-hal/examples/rtc_time.rs b/esp32c3-hal/examples/rtc_time.rs
index 1bf8195c8c5..93b71bcfefb 100644
--- a/esp32c3-hal/examples/rtc_time.rs
+++ b/esp32c3-hal/examples/rtc_time.rs
@@ -12,7 +12,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let rtc = Rtc::new(peripherals.RTC_CNTL);
+ let rtc = Rtc::new(peripherals.LPWR);
let mut delay = Delay::new(&clocks);
loop {
diff --git a/esp32c3-hal/examples/rtc_watchdog.rs b/esp32c3-hal/examples/rtc_watchdog.rs
index e15d212f2f6..194f65f4f39 100644
--- a/esp32c3-hal/examples/rtc_watchdog.rs
+++ b/esp32c3-hal/examples/rtc_watchdog.rs
@@ -27,7 +27,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let _clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+ let mut rtc = Rtc::new(peripherals.LPWR);
rtc.rwdt.start(2000u64.millis());
rtc.rwdt.listen();
diff --git a/esp32c3-hal/examples/sleep_timer.rs b/esp32c3-hal/examples/sleep_timer.rs
index ed2c13a1042..760ddd8e429 100644
--- a/esp32c3-hal/examples/sleep_timer.rs
+++ b/esp32c3-hal/examples/sleep_timer.rs
@@ -24,7 +24,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+ let mut rtc = Rtc::new(peripherals.LPWR);
println!("up and runnning!");
let reason = get_reset_reason(Cpu::ProCpu).unwrap_or(SocResetReason::ChipPowerOn);
diff --git a/esp32c3-hal/examples/sleep_timer_rtcio.rs b/esp32c3-hal/examples/sleep_timer_rtcio.rs
index 130e8a045a5..b181936ba9f 100644
--- a/esp32c3-hal/examples/sleep_timer_rtcio.rs
+++ b/esp32c3-hal/examples/sleep_timer_rtcio.rs
@@ -32,7 +32,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+ let mut rtc = Rtc::new(peripherals.LPWR);
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
let mut pin2 = io.pins.gpio2;
diff --git a/esp32c6-hal/examples/ram.rs b/esp32c6-hal/examples/ram.rs
index f583deb9a87..5f42c5bb611 100644
--- a/esp32c6-hal/examples/ram.rs
+++ b/esp32c6-hal/examples/ram.rs
@@ -40,7 +40,7 @@ fn main() -> ! {
// The RWDT flash boot protection must be enabled, as it is triggered as part of
// the example.
- let mut rtc = Rtc::new(peripherals.LP_CLKRST);
+ let mut rtc = Rtc::new(peripherals.LPWR);
rtc.rwdt.enable();
timer0.start(1u64.secs());
diff --git a/esp32c6-hal/examples/rtc_time.rs b/esp32c6-hal/examples/rtc_time.rs
index 906a9897b5b..9cf66a9016e 100644
--- a/esp32c6-hal/examples/rtc_time.rs
+++ b/esp32c6-hal/examples/rtc_time.rs
@@ -12,7 +12,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let rtc = Rtc::new(peripherals.LP_CLKRST);
+ let rtc = Rtc::new(peripherals.LPWR);
let mut delay = Delay::new(&clocks);
loop {
diff --git a/esp32c6-hal/examples/rtc_watchdog.rs b/esp32c6-hal/examples/rtc_watchdog.rs
index 7c9447305c7..96686482932 100644
--- a/esp32c6-hal/examples/rtc_watchdog.rs
+++ b/esp32c6-hal/examples/rtc_watchdog.rs
@@ -27,7 +27,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let _clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let mut rtc = Rtc::new(peripherals.LP_CLKRST);
+ let mut rtc = Rtc::new(peripherals.LPWR);
rtc.rwdt.start(2000u64.millis());
rtc.rwdt.listen();
diff --git a/esp32c6-hal/examples/sleep_lpio.rs b/esp32c6-hal/examples/sleep_lpio.rs
index e1fe4238757..164d460e440 100644
--- a/esp32c6-hal/examples/sleep_lpio.rs
+++ b/esp32c6-hal/examples/sleep_lpio.rs
@@ -29,7 +29,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let mut rtc = Rtc::new(peripherals.LP_CLKRST);
+ let mut rtc = Rtc::new(peripherals.LPWR);
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
let mut pin2 = io.pins.gpio2;
diff --git a/esp32h2-hal/examples/ram.rs b/esp32h2-hal/examples/ram.rs
index f92b090df67..97ad9f380d1 100644
--- a/esp32h2-hal/examples/ram.rs
+++ b/esp32h2-hal/examples/ram.rs
@@ -40,7 +40,7 @@ fn main() -> ! {
// The RWDT flash boot protection must be enabled, as it is triggered as part of
// the example.
- let mut rtc = Rtc::new(peripherals.LP_CLKRST);
+ let mut rtc = Rtc::new(peripherals.LPWR);
rtc.rwdt.enable();
timer0.start(1u64.secs());
diff --git a/esp32h2-hal/examples/rtc_time.rs b/esp32h2-hal/examples/rtc_time.rs
index f79a7b5510b..1597025f048 100644
--- a/esp32h2-hal/examples/rtc_time.rs
+++ b/esp32h2-hal/examples/rtc_time.rs
@@ -12,7 +12,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let rtc = Rtc::new(peripherals.LP_CLKRST);
+ let rtc = Rtc::new(peripherals.LPWR);
let mut delay = Delay::new(&clocks);
loop {
diff --git a/esp32h2-hal/examples/rtc_watchdog.rs b/esp32h2-hal/examples/rtc_watchdog.rs
index 39cc5ebbc01..ac737cf1dd6 100644
--- a/esp32h2-hal/examples/rtc_watchdog.rs
+++ b/esp32h2-hal/examples/rtc_watchdog.rs
@@ -27,7 +27,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let _clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let mut rtc = Rtc::new(peripherals.LP_CLKRST);
+ let mut rtc = Rtc::new(peripherals.LPWR);
rtc.rwdt.start(2000u64.millis());
rtc.rwdt.listen();
diff --git a/esp32s2-hal/examples/clock_monitor.rs b/esp32s2-hal/examples/clock_monitor.rs
index e2135d4dc56..8ddfbda1605 100644
--- a/esp32s2-hal/examples/clock_monitor.rs
+++ b/esp32s2-hal/examples/clock_monitor.rs
@@ -26,7 +26,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+ let mut rtc = Rtc::new(peripherals.LPWR);
rtc.rwdt.start(2000u64.millis());
rtc.rwdt.listen();
diff --git a/esp32s2-hal/examples/ram.rs b/esp32s2-hal/examples/ram.rs
index e8c538e9839..98ce1e5f555 100644
--- a/esp32s2-hal/examples/ram.rs
+++ b/esp32s2-hal/examples/ram.rs
@@ -40,7 +40,7 @@ fn main() -> ! {
// The RWDT flash boot protection must be enabled, as it is triggered as part of
// the example.
- let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+ let mut rtc = Rtc::new(peripherals.LPWR);
rtc.rwdt.enable();
timer0.start(1u64.secs());
diff --git a/esp32s2-hal/examples/rtc_time.rs b/esp32s2-hal/examples/rtc_time.rs
index 6f16358391f..da4b8072a26 100644
--- a/esp32s2-hal/examples/rtc_time.rs
+++ b/esp32s2-hal/examples/rtc_time.rs
@@ -12,7 +12,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let rtc = Rtc::new(peripherals.RTC_CNTL);
+ let rtc = Rtc::new(peripherals.LPWR);
let mut delay = Delay::new(&clocks);
loop {
diff --git a/esp32s2-hal/examples/rtc_watchdog.rs b/esp32s2-hal/examples/rtc_watchdog.rs
index c04f1d9b612..9138be8ce4d 100644
--- a/esp32s2-hal/examples/rtc_watchdog.rs
+++ b/esp32s2-hal/examples/rtc_watchdog.rs
@@ -27,7 +27,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let _clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+ let mut rtc = Rtc::new(peripherals.LPWR);
rtc.rwdt.start(2000u64.millis());
rtc.rwdt.listen();
diff --git a/esp32s3-hal/examples/clock_monitor.rs b/esp32s3-hal/examples/clock_monitor.rs
index b8838b51e20..0fb79083a9d 100644
--- a/esp32s3-hal/examples/clock_monitor.rs
+++ b/esp32s3-hal/examples/clock_monitor.rs
@@ -26,7 +26,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+ let mut rtc = Rtc::new(peripherals.LPWR);
rtc.rwdt.start(2000u64.millis());
rtc.rwdt.listen();
diff --git a/esp32s3-hal/examples/ram.rs b/esp32s3-hal/examples/ram.rs
index 7e021ec3178..a8927ca4ef9 100644
--- a/esp32s3-hal/examples/ram.rs
+++ b/esp32s3-hal/examples/ram.rs
@@ -40,7 +40,7 @@ fn main() -> ! {
// The RWDT flash boot protection must be enabled, as it is triggered as part of
// the example.
- let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+ let mut rtc = Rtc::new(peripherals.LPWR);
rtc.rwdt.enable();
timer0.start(1u64.secs());
diff --git a/esp32s3-hal/examples/rtc_time.rs b/esp32s3-hal/examples/rtc_time.rs
index b698b7d0398..db3bfecf017 100644
--- a/esp32s3-hal/examples/rtc_time.rs
+++ b/esp32s3-hal/examples/rtc_time.rs
@@ -12,7 +12,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let rtc = Rtc::new(peripherals.RTC_CNTL);
+ let rtc = Rtc::new(peripherals.LPWR);
let mut delay = Delay::new(&clocks);
loop {
diff --git a/esp32s3-hal/examples/rtc_watchdog.rs b/esp32s3-hal/examples/rtc_watchdog.rs
index 409a9c60fbe..a1655546f03 100644
--- a/esp32s3-hal/examples/rtc_watchdog.rs
+++ b/esp32s3-hal/examples/rtc_watchdog.rs
@@ -27,7 +27,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let _clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+ let mut rtc = Rtc::new(peripherals.LPWR);
rtc.rwdt.start(2000u64.millis());
rtc.rwdt.listen();
diff --git a/esp32s3-hal/examples/sleep_timer.rs b/esp32s3-hal/examples/sleep_timer.rs
index 46c1c9ecdb7..2aeec442289 100644
--- a/esp32s3-hal/examples/sleep_timer.rs
+++ b/esp32s3-hal/examples/sleep_timer.rs
@@ -24,7 +24,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+ let mut rtc = Rtc::new(peripherals.LPWR);
println!("up and runnning!");
let reason = get_reset_reason(Cpu::ProCpu).unwrap_or(SocResetReason::ChipPowerOn);
diff --git a/esp32s3-hal/examples/sleep_timer_ext0.rs b/esp32s3-hal/examples/sleep_timer_ext0.rs
index 5ec0758f586..9210a6a2617 100644
--- a/esp32s3-hal/examples/sleep_timer_ext0.rs
+++ b/esp32s3-hal/examples/sleep_timer_ext0.rs
@@ -30,7 +30,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+ let mut rtc = Rtc::new(peripherals.LPWR);
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
let mut ext0_pin = io.pins.gpio18;
diff --git a/esp32s3-hal/examples/sleep_timer_ext1.rs b/esp32s3-hal/examples/sleep_timer_ext1.rs
index 191eb6ed4aa..61cf56e7575 100644
--- a/esp32s3-hal/examples/sleep_timer_ext1.rs
+++ b/esp32s3-hal/examples/sleep_timer_ext1.rs
@@ -30,7 +30,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+ let mut rtc = Rtc::new(peripherals.LPWR);
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
let mut pin18 = io.pins.gpio18;
diff --git a/esp32s3-hal/examples/sleep_timer_rtcio.rs b/esp32s3-hal/examples/sleep_timer_rtcio.rs
index 82173917c84..d6d44e25f59 100644
--- a/esp32s3-hal/examples/sleep_timer_rtcio.rs
+++ b/esp32s3-hal/examples/sleep_timer_rtcio.rs
@@ -31,7 +31,7 @@ fn main() -> ! {
let system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
- let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+ let mut rtc = Rtc::new(peripherals.LPWR);
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
let mut rtcio_pin18 = io.pins.gpio18;