SPI CS-to-clock delays ?

[yanshay]

I'm trying to get a PN532 to work using SPI. It seems to respond but the data I receive seems to not be correct.

In my searches, I stumbled upon the topic of 'CS-to-clock delays' in embedded-hal documentation at https://rtic.rs/dev/api/embedded_hal/spi/index.html (relevant part quoted below), from which I understand there should be a way when configuring the SPI to configure CS-to-clock delay on the SpiDevice instance or in hardware. I can't find a way to configure a hardware managed delay in esp-hal. Is there such in esp32?

The SpiDevice I use is from embedded-hal-bus and I don't see there support for such delay either (actually found it is missing: rust-embedded/embedded-hal#605)

CS-to-clock delays

Many chips require a minimum delay between asserting CS and the first SCK edge, and the last SCK edge and deasserting CS. Drivers should NOT use Operation::DelayNs for this, they should instead document that the user should configure the delays when creating the SpiDevice instance, same as they have to configure the SPI frequency and mode. This has a few advantages:
Allows implementations that use hardware-managed CS to program the delay in hardware
Allows the end user more flexibility. For example, they can choose to not configure any delay if their MCU is slow enough to “naturally” do the delay (very common if the delay is in the order of nanoseconds).

[Dominaezzz]

The hardware supports it, it just needs to be exposed in the API.

Each chip has varying amount of support. You're looking for SPI_CS_SETUP in the TRMs.

[yanshay]

Do you happen to have some example code for using it?

[Dominaezzz]

No sadly, I haven't actually used it myself.