From 41f846f318c3f535351c1ef046e3d41e053cba6a Mon Sep 17 00:00:00 2001 From: Jesse Braham Date: Fri, 22 Dec 2023 09:59:13 -0800 Subject: [PATCH 1/2] Move initialization functions into `esp-hal-common` package's `soc` module --- esp-hal-common/src/soc/esp32/mod.rs | 57 +++++++++++++++++ esp-hal-common/src/soc/esp32c2/mod.rs | 13 ++++ esp-hal-common/src/soc/esp32c3/mod.rs | 14 +++++ esp-hal-common/src/soc/esp32c6/mod.rs | 14 +++++ esp-hal-common/src/soc/esp32h2/mod.rs | 14 +++++ esp-hal-common/src/soc/esp32s2/mod.rs | 58 +++++++++++++++++ esp-hal-common/src/soc/esp32s3/mod.rs | 90 ++++++++++++++++++++++++++ esp32-hal/src/lib.rs | 59 ----------------- esp32c2-hal/src/lib.rs | 15 ----- esp32c3-hal/src/lib.rs | 16 ----- esp32c6-hal/src/lib.rs | 16 ----- esp32h2-hal/src/lib.rs | 16 ----- esp32s2-hal/src/lib.rs | 59 ----------------- esp32s3-hal/src/lib.rs | 91 --------------------------- 14 files changed, 260 insertions(+), 272 deletions(-) diff --git a/esp-hal-common/src/soc/esp32/mod.rs b/esp-hal-common/src/soc/esp32/mod.rs index 9d5c1078d46..b70edda1616 100644 --- a/esp-hal-common/src/soc/esp32/mod.rs +++ b/esp-hal-common/src/soc/esp32/mod.rs @@ -5,6 +5,9 @@ //! The `SOC` module provides access, functions and structures that are useful //! for interacting with various system-related peripherals on `ESP32` chip. +use self::peripherals::{RTC_CNTL, TIMG0, TIMG1}; +use crate::{timer::Wdt, Rtc}; + pub mod cpu_control; pub mod efuse; pub mod gpio; @@ -23,3 +26,57 @@ pub(crate) mod constants { pub const SOC_DRAM_LOW: u32 = 0x3FFA_E000; pub const SOC_DRAM_HIGH: u32 = 0x4000_0000; } + +/// Function initializes ESP32 specific memories (RTC slow and fast) and +/// then calls original Reset function +/// +/// ENTRY point is defined in memory.x +/// *Note: the pre_init function is called in the original reset handler +/// after the initializations done in this function* +#[cfg(feature = "rt-xtensa")] +#[doc(hidden)] +#[no_mangle] +pub unsafe extern "C" fn ESP32Reset() -> ! { + // These symbols come from `memory.x` + extern "C" { + static mut _rtc_fast_bss_start: u32; + static mut _rtc_fast_bss_end: u32; + + static mut _rtc_slow_bss_start: u32; + static mut _rtc_slow_bss_end: u32; + + static mut _stack_start_cpu0: u32; + } + + // set stack pointer to end of memory: no need to retain stack up to this point + esp_hal_common::xtensa_lx::set_stack_pointer(&mut _stack_start_cpu0); + + // copying data from flash to various data segments is done by the bootloader + // initialization to zero needs to be done by the application + + // Initialize RTC RAM + esp_hal_common::xtensa_lx_rt::zero_bss(&mut _rtc_fast_bss_start, &mut _rtc_fast_bss_end); + esp_hal_common::xtensa_lx_rt::zero_bss(&mut _rtc_slow_bss_start, &mut _rtc_slow_bss_end); + + // continue with default reset handler + esp_hal_common::xtensa_lx_rt::Reset(); +} + +/// The ESP32 has a first stage bootloader that handles loading program data +/// into the right place therefore we skip loading it again. +#[doc(hidden)] +#[no_mangle] +#[rustfmt::skip] +pub extern "Rust" fn __init_data() -> bool { + false +} + +#[export_name = "__post_init"] +unsafe fn post_init() { + // RTC domain must be enabled before we try to disable + let mut rtc = Rtc::new(RTC_CNTL::steal()); + rtc.rwdt.disable(); + + Wdt::::set_wdt_enabled(false); + Wdt::::set_wdt_enabled(false); +} diff --git a/esp-hal-common/src/soc/esp32c2/mod.rs b/esp-hal-common/src/soc/esp32c2/mod.rs index bec36080aa1..2cb4ea54dbf 100644 --- a/esp-hal-common/src/soc/esp32c2/mod.rs +++ b/esp-hal-common/src/soc/esp32c2/mod.rs @@ -5,6 +5,9 @@ //! The `SOC` module provides access, functions and structures that are useful //! for interacting with various system-related peripherals on `ESP32-C2` chip. +use self::peripherals::{RTC_CNTL, TIMG0}; +use crate::{timer::Wdt, Rtc}; + pub mod efuse; pub mod gpio; pub mod peripherals; @@ -18,3 +21,13 @@ pub(crate) mod constants { pub const SOC_DRAM_LOW: u32 = 0x3FCA_0000; pub const SOC_DRAM_HIGH: u32 = 0x3FCE_0000; } + +#[export_name = "__post_init"] +unsafe fn post_init() { + // RTC domain must be enabled before we try to disable + let mut rtc = Rtc::new(RTC_CNTL::steal()); + rtc.swd.disable(); + rtc.rwdt.disable(); + + Wdt::::set_wdt_enabled(false); +} diff --git a/esp-hal-common/src/soc/esp32c3/mod.rs b/esp-hal-common/src/soc/esp32c3/mod.rs index 89da41c7ff0..3f0a89a79f1 100644 --- a/esp-hal-common/src/soc/esp32c3/mod.rs +++ b/esp-hal-common/src/soc/esp32c3/mod.rs @@ -9,6 +9,9 @@ //! * I2S_SCLK: 160_000_000 - I2S clock frequency //! * I2S_DEFAULT_CLK_SRC: 2 - I2S clock source +use self::peripherals::{RTC_CNTL, TIMG0, TIMG1}; +use crate::{timer::Wdt, Rtc}; + pub mod efuse; pub mod gpio; pub mod peripherals; @@ -30,3 +33,14 @@ pub(crate) mod constants { pub const SOC_DRAM_LOW: u32 = 0x3FC8_0000; pub const SOC_DRAM_HIGH: u32 = 0x3FCE_0000; } + +#[export_name = "__post_init"] +unsafe fn post_init() { + // RTC domain must be enabled before we try to disable + let mut rtc = Rtc::new(RTC_CNTL::steal()); + rtc.swd.disable(); + rtc.rwdt.disable(); + + Wdt::::set_wdt_enabled(false); + Wdt::::set_wdt_enabled(false); +} diff --git a/esp-hal-common/src/soc/esp32c6/mod.rs b/esp-hal-common/src/soc/esp32c6/mod.rs index 8ad33831e14..b0eb6b248f9 100644 --- a/esp-hal-common/src/soc/esp32c6/mod.rs +++ b/esp-hal-common/src/soc/esp32c6/mod.rs @@ -10,6 +10,9 @@ //! * I2S_DEFAULT_CLK_SRC: 2 - I2S clock source //! * I2S_SCLK: 160_000_000 - I2S clock frequency +use self::peripherals::{LP_CLKRST, TIMG0, TIMG1}; +use crate::{timer::Wdt, Rtc}; + pub mod efuse; pub mod gpio; pub mod lp_core; @@ -36,3 +39,14 @@ pub(crate) mod constants { pub const SOC_DRAM_LOW: u32 = 0x4080_0000; pub const SOC_DRAM_HIGH: u32 = 0x4088_0000; } + +#[export_name = "__post_init"] +unsafe fn post_init() { + // RTC domain must be enabled before we try to disable + let mut rtc = Rtc::new(LP_CLKRST::steal()); + rtc.swd.disable(); + rtc.rwdt.disable(); + + Wdt::::set_wdt_enabled(false); + Wdt::::set_wdt_enabled(false); +} diff --git a/esp-hal-common/src/soc/esp32h2/mod.rs b/esp-hal-common/src/soc/esp32h2/mod.rs index 8cfa25ed54a..04be9c9d79f 100644 --- a/esp-hal-common/src/soc/esp32h2/mod.rs +++ b/esp-hal-common/src/soc/esp32h2/mod.rs @@ -10,6 +10,9 @@ //! * I2S_DEFAULT_CLK_SRC: 1 - I2S clock source //! * I2S_SCLK: 96_000_000 - I2S clock frequency +use self::peripherals::{LP_CLKRST, TIMG0, TIMG1}; +use crate::{timer::Wdt, Rtc}; + pub mod efuse; pub mod gpio; pub mod peripherals; @@ -35,3 +38,14 @@ pub(crate) mod constants { pub const SOC_DRAM_LOW: u32 = 0x4080_0000; pub const SOC_DRAM_HIGH: u32 = 0x4085_0000; } + +#[export_name = "__post_init"] +unsafe fn post_init() { + // RTC domain must be enabled before we try to disable + let mut rtc = Rtc::new(LP_CLKRST::steal()); + rtc.swd.disable(); + rtc.rwdt.disable(); + + Wdt::::set_wdt_enabled(false); + Wdt::::set_wdt_enabled(false); +} diff --git a/esp-hal-common/src/soc/esp32s2/mod.rs b/esp-hal-common/src/soc/esp32s2/mod.rs index 2534fb63af0..a1b35e99041 100644 --- a/esp-hal-common/src/soc/esp32s2/mod.rs +++ b/esp-hal-common/src/soc/esp32s2/mod.rs @@ -8,6 +8,10 @@ //! Also few constants are defined in this module for `ESP32-S2` chip: //! * I2S_SCLK: 160_000_000 - I2S clock frequency //! * I2S_DEFAULT_CLK_SRC: 2 - I2S clock source + +use self::peripherals::{RTC_CNTL, TIMG0, TIMG1}; +use crate::{timer::Wdt, Rtc}; + pub mod efuse; pub mod gpio; pub mod peripherals; @@ -26,3 +30,57 @@ pub(crate) mod constants { pub const SOC_DRAM_LOW: u32 = 0x3FFB_0000; pub const SOC_DRAM_HIGH: u32 = 0x4000_0000; } + +/// Function initializes ESP32 specific memories (RTC slow and fast) and +/// then calls original Reset function +/// +/// ENTRY point is defined in memory.x +/// *Note: the pre_init function is called in the original reset handler +/// after the initializations done in this function* +#[cfg(feature = "rt-xtensa")] +#[doc(hidden)] +#[no_mangle] +pub unsafe extern "C" fn ESP32Reset() -> ! { + // These symbols come from `memory.x` + extern "C" { + static mut _rtc_fast_bss_start: u32; + static mut _rtc_fast_bss_end: u32; + + static mut _rtc_slow_bss_start: u32; + static mut _rtc_slow_bss_end: u32; + + static mut _stack_start_cpu0: u32; + } + + // set stack pointer to end of memory: no need to retain stack up to this point + xtensa_lx::set_stack_pointer(&mut _stack_start_cpu0); + + // copying data from flash to various data segments is done by the bootloader + // initialization to zero needs to be done by the application + + // Initialize RTC RAM + xtensa_lx_rt::zero_bss(&mut _rtc_fast_bss_start, &mut _rtc_fast_bss_end); + xtensa_lx_rt::zero_bss(&mut _rtc_slow_bss_start, &mut _rtc_slow_bss_end); + + // continue with default reset handler + xtensa_lx_rt::Reset(); +} + +/// The ESP32 has a first stage bootloader that handles loading program data +/// into the right place therefore we skip loading it again. +#[doc(hidden)] +#[no_mangle] +#[rustfmt::skip] +pub extern "Rust" fn __init_data() -> bool { + false +} + +#[export_name = "__post_init"] +unsafe fn post_init() { + // RTC domain must be enabled before we try to disable + let mut rtc = Rtc::new(RTC_CNTL::steal()); + rtc.rwdt.disable(); + + Wdt::::set_wdt_enabled(false); + Wdt::::set_wdt_enabled(false); +} diff --git a/esp-hal-common/src/soc/esp32s3/mod.rs b/esp-hal-common/src/soc/esp32s3/mod.rs index 30c09ed46de..1ff65941861 100644 --- a/esp-hal-common/src/soc/esp32s3/mod.rs +++ b/esp-hal-common/src/soc/esp32s3/mod.rs @@ -8,6 +8,10 @@ //! Also few constants are defined in this module for `ESP32-S3` chip: //! * I2S_SCLK: 160_000_000 - I2S clock frequency //! * I2S_DEFAULT_CLK_SRC: 2 - I2S clock source + +use self::peripherals::{RTC_CNTL, TIMG0, TIMG1}; +use crate::{timer::Wdt, Rtc}; + pub mod cpu_control; pub mod efuse; pub mod gpio; @@ -29,3 +33,89 @@ pub(crate) mod constants { pub const SOC_DRAM_LOW: u32 = 0x3FC8_8000; pub const SOC_DRAM_HIGH: u32 = 0x3FD0_0000; } + +#[cfg(feature = "rt-xtensa")] +#[doc(hidden)] +#[link_section = ".rwtext"] +pub unsafe fn configure_cpu_caches() { + // this is just the bare minimum we need to run code from flash + // consider implementing more advanced configurations + // see https://github.com/apache/incubator-nuttx/blob/master/arch/xtensa/src/esp32s3/esp32s3_start.c + + extern "C" { + fn rom_config_instruction_cache_mode( + cfg_cache_size: u32, + cfg_cache_ways: u8, + cfg_cache_line_size: u8, + ); + } + + // ideally these should be configurable + const CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE: u32 = 0x4000; // ESP32S3_INSTRUCTION_CACHE_16KB + const CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS: u8 = 8; // ESP32S3_INSTRUCTION_CACHE_8WAYS + const CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE: u8 = 32; // ESP32S3_INSTRUCTION_CACHE_LINE_32B + + // Configure the mode of instruction cache: cache size, cache line size. + rom_config_instruction_cache_mode( + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE, + CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS, + CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE, + ); +} + +/// Function initializes ESP32S3 specific memories (RTC slow and fast) and +/// then calls original Reset function +/// +/// ENTRY point is defined in memory.x +/// *Note: the pre_init function is called in the original reset handler +/// after the initializations done in this function* +#[cfg(feature = "rt-xtensa")] +#[doc(hidden)] +#[no_mangle] +#[link_section = ".rwtext"] +pub unsafe extern "C" fn ESP32Reset() -> ! { + configure_cpu_caches(); + + // These symbols come from `memory.x` + extern "C" { + static mut _rtc_fast_bss_start: u32; + static mut _rtc_fast_bss_end: u32; + + static mut _rtc_slow_bss_start: u32; + static mut _rtc_slow_bss_end: u32; + + static mut _stack_start_cpu0: u32; + } + + // set stack pointer to end of memory: no need to retain stack up to this point + xtensa_lx::set_stack_pointer(&mut _stack_start_cpu0); + + // copying data from flash to various data segments is done by the bootloader + // initialization to zero needs to be done by the application + + // Initialize RTC RAM + xtensa_lx_rt::zero_bss(&mut _rtc_fast_bss_start, &mut _rtc_fast_bss_end); + xtensa_lx_rt::zero_bss(&mut _rtc_slow_bss_start, &mut _rtc_slow_bss_end); + + // continue with default reset handler + xtensa_lx_rt::Reset(); +} + +/// The ESP32 has a first stage bootloader that handles loading program data +/// into the right place therefore we skip loading it again. +#[doc(hidden)] +#[no_mangle] +#[rustfmt::skip] +pub extern "Rust" fn __init_data() -> bool { + false +} + +#[export_name = "__post_init"] +unsafe fn post_init() { + // RTC domain must be enabled before we try to disable + let mut rtc = Rtc::new(RTC_CNTL::steal()); + rtc.rwdt.disable(); + + Wdt::::set_wdt_enabled(false); + Wdt::::set_wdt_enabled(false); +} diff --git a/esp32-hal/src/lib.rs b/esp32-hal/src/lib.rs index d8ccf6033df..151698b5534 100644 --- a/esp32-hal/src/lib.rs +++ b/esp32-hal/src/lib.rs @@ -60,62 +60,3 @@ #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")] pub use esp_hal_common::*; - -/// Function initializes ESP32 specific memories (RTC slow and fast) and -/// then calls original Reset function -/// -/// ENTRY point is defined in memory.x -/// *Note: the pre_init function is called in the original reset handler -/// after the initializations done in this function* -#[cfg(feature = "rt")] -#[doc(hidden)] -#[no_mangle] -pub unsafe extern "C" fn ESP32Reset() -> ! { - // These symbols come from `memory.x` - extern "C" { - static mut _rtc_fast_bss_start: u32; - static mut _rtc_fast_bss_end: u32; - - static mut _rtc_slow_bss_start: u32; - static mut _rtc_slow_bss_end: u32; - - static mut _stack_start_cpu0: u32; - } - - // set stack pointer to end of memory: no need to retain stack up to this point - esp_hal_common::xtensa_lx::set_stack_pointer(&mut _stack_start_cpu0); - - // copying data from flash to various data segments is done by the bootloader - // initialization to zero needs to be done by the application - - // Initialize RTC RAM - esp_hal_common::xtensa_lx_rt::zero_bss(&mut _rtc_fast_bss_start, &mut _rtc_fast_bss_end); - esp_hal_common::xtensa_lx_rt::zero_bss(&mut _rtc_slow_bss_start, &mut _rtc_slow_bss_end); - - // continue with default reset handler - esp_hal_common::xtensa_lx_rt::Reset(); -} - -/// The ESP32 has a first stage bootloader that handles loading program data -/// into the right place therefore we skip loading it again. -#[doc(hidden)] -#[no_mangle] -#[rustfmt::skip] -pub extern "Rust" fn __init_data() -> bool { - false -} - -#[export_name = "__post_init"] -unsafe fn post_init() { - use esp_hal_common::{ - peripherals::{RTC_CNTL, TIMG0, TIMG1}, - timer::Wdt, - }; - - // RTC domain must be enabled before we try to disable - let mut rtc = Rtc::new(RTC_CNTL::steal()); - rtc.rwdt.disable(); - - Wdt::::set_wdt_enabled(false); - Wdt::::set_wdt_enabled(false); -} diff --git a/esp32c2-hal/src/lib.rs b/esp32c2-hal/src/lib.rs index c4e53d67067..6fda9cdc2e5 100644 --- a/esp32c2-hal/src/lib.rs +++ b/esp32c2-hal/src/lib.rs @@ -55,18 +55,3 @@ #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")] pub use esp_hal_common::*; - -#[export_name = "__post_init"] -unsafe fn post_init() { - use esp_hal_common::{ - peripherals::{RTC_CNTL, TIMG0}, - timer::Wdt, - }; - - // RTC domain must be enabled before we try to disable - let mut rtc = Rtc::new(RTC_CNTL::steal()); - rtc.swd.disable(); - rtc.rwdt.disable(); - - Wdt::::set_wdt_enabled(false); -} diff --git a/esp32c3-hal/src/lib.rs b/esp32c3-hal/src/lib.rs index 5c0fdd14fdc..dd2403bbd48 100644 --- a/esp32c3-hal/src/lib.rs +++ b/esp32c3-hal/src/lib.rs @@ -54,19 +54,3 @@ #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")] pub use esp_hal_common::*; - -#[export_name = "__post_init"] -unsafe fn post_init() { - use esp_hal_common::{ - peripherals::{RTC_CNTL, TIMG0, TIMG1}, - timer::Wdt, - }; - - // RTC domain must be enabled before we try to disable - let mut rtc = Rtc::new(RTC_CNTL::steal()); - rtc.swd.disable(); - rtc.rwdt.disable(); - - Wdt::::set_wdt_enabled(false); - Wdt::::set_wdt_enabled(false); -} diff --git a/esp32c6-hal/src/lib.rs b/esp32c6-hal/src/lib.rs index 6f561001c6a..b34b312fe14 100644 --- a/esp32c6-hal/src/lib.rs +++ b/esp32c6-hal/src/lib.rs @@ -55,19 +55,3 @@ #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")] pub use esp_hal_common::*; - -#[export_name = "__post_init"] -unsafe fn post_init() { - use esp_hal_common::{ - peripherals::{LP_CLKRST, TIMG0, TIMG1}, - timer::Wdt, - }; - - // RTC domain must be enabled before we try to disable - let mut rtc = Rtc::new(LP_CLKRST::steal()); - rtc.swd.disable(); - rtc.rwdt.disable(); - - Wdt::::set_wdt_enabled(false); - Wdt::::set_wdt_enabled(false); -} diff --git a/esp32h2-hal/src/lib.rs b/esp32h2-hal/src/lib.rs index 998759da742..a56051fbf3e 100644 --- a/esp32h2-hal/src/lib.rs +++ b/esp32h2-hal/src/lib.rs @@ -55,19 +55,3 @@ #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")] pub use esp_hal_common::*; - -#[export_name = "__post_init"] -unsafe fn post_init() { - use esp_hal_common::{ - peripherals::{LP_CLKRST, TIMG0, TIMG1}, - timer::Wdt, - }; - - // RTC domain must be enabled before we try to disable - let mut rtc = Rtc::new(LP_CLKRST::steal()); - rtc.swd.disable(); - rtc.rwdt.disable(); - - Wdt::::set_wdt_enabled(false); - Wdt::::set_wdt_enabled(false); -} diff --git a/esp32s2-hal/src/lib.rs b/esp32s2-hal/src/lib.rs index b77dd10ca0c..94f87552464 100644 --- a/esp32s2-hal/src/lib.rs +++ b/esp32s2-hal/src/lib.rs @@ -60,62 +60,3 @@ #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")] pub use esp_hal_common::*; - -/// Function initializes ESP32 specific memories (RTC slow and fast) and -/// then calls original Reset function -/// -/// ENTRY point is defined in memory.x -/// *Note: the pre_init function is called in the original reset handler -/// after the initializations done in this function* -#[cfg(feature = "rt")] -#[doc(hidden)] -#[no_mangle] -pub unsafe extern "C" fn ESP32Reset() -> ! { - // These symbols come from `memory.x` - extern "C" { - static mut _rtc_fast_bss_start: u32; - static mut _rtc_fast_bss_end: u32; - - static mut _rtc_slow_bss_start: u32; - static mut _rtc_slow_bss_end: u32; - - static mut _stack_start_cpu0: u32; - } - - // set stack pointer to end of memory: no need to retain stack up to this point - esp_hal_common::xtensa_lx::set_stack_pointer(&mut _stack_start_cpu0); - - // copying data from flash to various data segments is done by the bootloader - // initialization to zero needs to be done by the application - - // Initialize RTC RAM - esp_hal_common::xtensa_lx_rt::zero_bss(&mut _rtc_fast_bss_start, &mut _rtc_fast_bss_end); - esp_hal_common::xtensa_lx_rt::zero_bss(&mut _rtc_slow_bss_start, &mut _rtc_slow_bss_end); - - // continue with default reset handler - esp_hal_common::xtensa_lx_rt::Reset(); -} - -/// The ESP32 has a first stage bootloader that handles loading program data -/// into the right place therefore we skip loading it again. -#[doc(hidden)] -#[no_mangle] -#[rustfmt::skip] -pub extern "Rust" fn __init_data() -> bool { - false -} - -#[export_name = "__post_init"] -unsafe fn post_init() { - use esp_hal_common::{ - peripherals::{RTC_CNTL, TIMG0, TIMG1}, - timer::Wdt, - }; - - // RTC domain must be enabled before we try to disable - let mut rtc = Rtc::new(RTC_CNTL::steal()); - rtc.rwdt.disable(); - - Wdt::::set_wdt_enabled(false); - Wdt::::set_wdt_enabled(false); -} diff --git a/esp32s3-hal/src/lib.rs b/esp32s3-hal/src/lib.rs index b4ea01e8ce1..3852d1c94b0 100644 --- a/esp32s3-hal/src/lib.rs +++ b/esp32s3-hal/src/lib.rs @@ -61,94 +61,3 @@ #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")] pub use esp_hal_common::*; - -#[cfg(feature = "rt")] -#[doc(hidden)] -#[link_section = ".rwtext"] -pub unsafe fn configure_cpu_caches() { - // this is just the bare minimum we need to run code from flash - // consider implementing more advanced configurations - // see https://github.com/apache/incubator-nuttx/blob/master/arch/xtensa/src/esp32s3/esp32s3_start.c - - extern "C" { - fn rom_config_instruction_cache_mode( - cfg_cache_size: u32, - cfg_cache_ways: u8, - cfg_cache_line_size: u8, - ); - } - - // ideally these should be configurable - const CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE: u32 = 0x4000; // ESP32S3_INSTRUCTION_CACHE_16KB - const CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS: u8 = 8; // ESP32S3_INSTRUCTION_CACHE_8WAYS - const CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE: u8 = 32; // ESP32S3_INSTRUCTION_CACHE_LINE_32B - - // Configure the mode of instruction cache: cache size, cache line size. - rom_config_instruction_cache_mode( - CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE, - CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS, - CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE, - ); -} - -/// Function initializes ESP32S3 specific memories (RTC slow and fast) and -/// then calls original Reset function -/// -/// ENTRY point is defined in memory.x -/// *Note: the pre_init function is called in the original reset handler -/// after the initializations done in this function* -#[cfg(feature = "rt")] -#[doc(hidden)] -#[no_mangle] -#[link_section = ".rwtext"] -pub unsafe extern "C" fn ESP32Reset() -> ! { - configure_cpu_caches(); - - // These symbols come from `memory.x` - extern "C" { - static mut _rtc_fast_bss_start: u32; - static mut _rtc_fast_bss_end: u32; - - static mut _rtc_slow_bss_start: u32; - static mut _rtc_slow_bss_end: u32; - - static mut _stack_start_cpu0: u32; - } - - // set stack pointer to end of memory: no need to retain stack up to this point - esp_hal_common::xtensa_lx::set_stack_pointer(&mut _stack_start_cpu0); - - // copying data from flash to various data segments is done by the bootloader - // initialization to zero needs to be done by the application - - // Initialize RTC RAM - esp_hal_common::xtensa_lx_rt::zero_bss(&mut _rtc_fast_bss_start, &mut _rtc_fast_bss_end); - esp_hal_common::xtensa_lx_rt::zero_bss(&mut _rtc_slow_bss_start, &mut _rtc_slow_bss_end); - - // continue with default reset handler - esp_hal_common::xtensa_lx_rt::Reset(); -} - -/// The ESP32 has a first stage bootloader that handles loading program data -/// into the right place therefore we skip loading it again. -#[doc(hidden)] -#[no_mangle] -#[rustfmt::skip] -pub extern "Rust" fn __init_data() -> bool { - false -} - -#[export_name = "__post_init"] -unsafe fn post_init() { - use esp_hal_common::{ - peripherals::{RTC_CNTL, TIMG0, TIMG1}, - timer::Wdt, - }; - - // RTC domain must be enabled before we try to disable - let mut rtc = Rtc::new(RTC_CNTL::steal()); - rtc.rwdt.disable(); - - Wdt::::set_wdt_enabled(false); - Wdt::::set_wdt_enabled(false); -} From 0e3c658fa2224b411f02739cdd80ab7988b5b075 Mon Sep 17 00:00:00 2001 From: Jesse Braham Date: Fri, 22 Dec 2023 10:11:56 -0800 Subject: [PATCH 2/2] Simplify module paths --- esp-hal-common/src/soc/esp32/mod.rs | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/esp-hal-common/src/soc/esp32/mod.rs b/esp-hal-common/src/soc/esp32/mod.rs index b70edda1616..bb31a02bcb8 100644 --- a/esp-hal-common/src/soc/esp32/mod.rs +++ b/esp-hal-common/src/soc/esp32/mod.rs @@ -49,17 +49,17 @@ pub unsafe extern "C" fn ESP32Reset() -> ! { } // set stack pointer to end of memory: no need to retain stack up to this point - esp_hal_common::xtensa_lx::set_stack_pointer(&mut _stack_start_cpu0); + xtensa_lx::set_stack_pointer(&mut _stack_start_cpu0); // copying data from flash to various data segments is done by the bootloader // initialization to zero needs to be done by the application // Initialize RTC RAM - esp_hal_common::xtensa_lx_rt::zero_bss(&mut _rtc_fast_bss_start, &mut _rtc_fast_bss_end); - esp_hal_common::xtensa_lx_rt::zero_bss(&mut _rtc_slow_bss_start, &mut _rtc_slow_bss_end); + xtensa_lx_rt::zero_bss(&mut _rtc_fast_bss_start, &mut _rtc_fast_bss_end); + xtensa_lx_rt::zero_bss(&mut _rtc_slow_bss_start, &mut _rtc_slow_bss_end); // continue with default reset handler - esp_hal_common::xtensa_lx_rt::Reset(); + xtensa_lx_rt::Reset(); } /// The ESP32 has a first stage bootloader that handles loading program data