From d7bb3e2b6d6eef48d973b662127bae3d6dc737f1 Mon Sep 17 00:00:00 2001
From: Jesse Braham <jesse@beta7.io>
Date: Tue, 2 Jan 2024 08:44:31 -0800
Subject: [PATCH 1/3] Add `rt-riscv` and `rt-xtensa` features to
 `esp-hal-common` to allow enabling/disable runtime support

---
 esp-hal-common/Cargo.toml           | 23 ++++++++++++++---------
 esp-hal-common/src/interrupt/mod.rs |  4 ++--
 esp-hal-common/src/lib.rs           | 12 +++++++-----
 esp-hal-common/src/prelude.rs       |  4 +++-
 esp32-hal/Cargo.toml                |  2 +-
 esp32c2-hal/Cargo.toml              |  2 +-
 esp32c3-hal/Cargo.toml              |  2 +-
 esp32c6-hal/Cargo.toml              |  2 +-
 esp32h2-hal/Cargo.toml              |  2 +-
 esp32s2-hal/Cargo.toml              |  2 +-
 esp32s3-hal/Cargo.toml              |  2 +-
 11 files changed, 33 insertions(+), 24 deletions(-)

diff --git a/esp-hal-common/Cargo.toml b/esp-hal-common/Cargo.toml
index b56a755d007..26dee6d3717 100644
--- a/esp-hal-common/Cargo.toml
+++ b/esp-hal-common/Cargo.toml
@@ -48,7 +48,8 @@ embassy-sync       = { version = "0.5.0", optional = true }
 embassy-time       = { version = "0.2.0", optional = true }
 
 # RISC-V
-esp-riscv-rt = { version = "0.6.0", optional = true, path = "../esp-riscv-rt" }
+riscv        = { version = "0.10.1", optional = true }
+esp-riscv-rt = { version = "0.6.0",  optional = true, path = "../esp-riscv-rt" }
 
 # Xtensa
 xtensa-lx    = { version = "0.8.0",  optional = true }
@@ -73,18 +74,22 @@ basic-toml = "0.1.7"
 serde      = { version = "1.0.193", features = ["derive"] }
 
 [features]
-esp32   = ["xtensa", "esp32/rt",   "procmacros/esp32",   "xtensa-lx/esp32",   "xtensa-lx-rt/esp32"]
-esp32c2 = ["riscv",  "esp32c2/rt", "procmacros/esp32c2", "portable-atomic/unsafe-assume-single-core"]
-esp32c3 = ["riscv",  "esp32c3/rt", "procmacros/esp32c3", "portable-atomic/unsafe-assume-single-core"]
-esp32c6 = ["riscv",  "esp32c6/rt", "procmacros/esp32c6"]
-esp32h2 = ["riscv",  "esp32h2/rt", "procmacros/esp32h2"]
-esp32s2 = ["xtensa", "esp32s2/rt", "procmacros/esp32s2", "xtensa-lx/esp32s2", "xtensa-lx-rt/esp32s2", "usb-otg", "portable-atomic/critical-section"]
-esp32s3 = ["xtensa", "esp32s3/rt", "procmacros/esp32s3", "xtensa-lx/esp32s3", "xtensa-lx-rt/esp32s3", "usb-otg"]
+esp32   = ["dep:esp32",   "xtensa", "procmacros/esp32",   "xtensa-lx/esp32",   "xtensa-lx-rt?/esp32"]
+esp32c2 = ["dep:esp32c2", "riscv",  "procmacros/esp32c2", "portable-atomic/unsafe-assume-single-core"]
+esp32c3 = ["dep:esp32c3", "riscv",  "procmacros/esp32c3", "portable-atomic/unsafe-assume-single-core"]
+esp32c6 = ["dep:esp32c6", "riscv",  "procmacros/esp32c6"]
+esp32h2 = ["dep:esp32h2", "riscv",  "procmacros/esp32h2"]
+esp32s2 = ["dep:esp32s2", "xtensa", "procmacros/esp32s2", "xtensa-lx/esp32s2", "xtensa-lx-rt?/esp32s2", "usb-otg", "portable-atomic/critical-section"]
+esp32s3 = ["dep:esp32s3", "xtensa", "procmacros/esp32s3", "xtensa-lx/esp32s3", "xtensa-lx-rt?/esp32s3", "usb-otg"]
 
 # Crystal frequency selection (ESP32 and ESP32-C2 only!)
 xtal-26mhz = []
 xtal-40mhz = []
 
+# Runetime support
+rt-riscv  = ["esp-riscv-rt/zero-bss", "esp32c2?/rt", "esp32c3?/rt", "esp32c6?/rt", "esp32h2?/rt"]
+rt-xtensa = ["dep:xtensa-lx-rt", "esp32?/rt", "esp32s2?/rt", "esp32s3?/rt"]
+
 # Only certain chips support flip-link (ESP32-C6 and ESPS32-H2)
 flip-link = ["esp-riscv-rt/fix-sp"]
 
@@ -150,7 +155,7 @@ embassy-generic-queue-64  = ["embassy-time/generic-queue-64"]
 embassy-generic-queue-128 = ["embassy-time/generic-queue-128"]
 
 # Architecture-specific features (intended for internal use)
-riscv  = ["critical-section/restore-state-u8", "esp-riscv-rt", "esp-riscv-rt/zero-bss"]
+riscv  = ["dep:riscv", "critical-section/restore-state-u8"]
 xtensa = ["critical-section/restore-state-u32"]
 
 # Initialize / clear data sections and RTC memory
diff --git a/esp-hal-common/src/interrupt/mod.rs b/esp-hal-common/src/interrupt/mod.rs
index 308ab9fffb7..f7b92eee38e 100644
--- a/esp-hal-common/src/interrupt/mod.rs
+++ b/esp-hal-common/src/interrupt/mod.rs
@@ -53,9 +53,9 @@
 //! ```
 
 #[cfg(riscv)]
-pub use riscv::*;
+pub use self::riscv::*;
 #[cfg(xtensa)]
-pub use xtensa::*;
+pub use self::xtensa::*;
 
 #[cfg(riscv)]
 mod riscv;
diff --git a/esp-hal-common/src/lib.rs b/esp-hal-common/src/lib.rs
index 2a0577a5a5d..f5d3bafd565 100644
--- a/esp-hal-common/src/lib.rs
+++ b/esp-hal-common/src/lib.rs
@@ -35,12 +35,12 @@
 // MUST be the first module
 mod fmt;
 
-#[cfg(riscv)]
+#[cfg(feature = "rt-riscv")]
 pub use esp_riscv_rt::{self, entry, riscv};
 pub use procmacros as macros;
 #[cfg(xtensa)]
 pub use xtensa_lx;
-#[cfg(xtensa)]
+#[cfg(feature = "rt-xtensa")]
 pub use xtensa_lx_rt::{self, entry};
 
 #[cfg(adc)]
@@ -104,7 +104,10 @@ pub mod hmac;
 pub mod i2c;
 #[cfg(any(i2s0, i2s1))]
 pub mod i2s;
-#[cfg(any(dport, interrupt_core0, interrupt_core1))]
+#[cfg(all(
+    any(dport, interrupt_core0, interrupt_core1),
+    any(feature = "rt-riscv", feature = "rt-xtensa")
+))]
 pub mod interrupt;
 #[cfg(ledc)]
 pub mod ledc;
@@ -150,6 +153,7 @@ pub mod uart;
 pub mod usb_serial_jtag;
 
 /// State of the CPU saved when entering exception or interrupt
+#[cfg(any(feature = "rt-riscv", feature = "rt-xtensa"))]
 pub mod trapframe {
     #[cfg(riscv)]
     pub use esp_riscv_rt::TrapFrame;
@@ -278,8 +282,6 @@ mod critical_section_impl {
 
     #[cfg(riscv)]
     mod riscv {
-        use esp_riscv_rt::riscv;
-
         #[cfg(multi_core)]
         // The restore state is a u8 that is casted from a bool, so it has a value of
         // 0x00 or 0x01 before we add the reentry flag to it.
diff --git a/esp-hal-common/src/prelude.rs b/esp-hal-common/src/prelude.rs
index 83bef8e7ea7..f907e0ec1d5 100644
--- a/esp-hal-common/src/prelude.rs
+++ b/esp-hal-common/src/prelude.rs
@@ -34,6 +34,8 @@ pub use crate::dma::{
     DmaTransfer as _esp_hal_dma_DmaTransfer,
     DmaTransferRxTx as _esp_hal_dma_DmaTransferRxTx,
 };
+#[cfg(any(feature = "rt-riscv", feature = "rt-xtensa"))]
+pub use crate::entry;
 #[cfg(gpio)]
 pub use crate::gpio::{
     InputPin as _esp_hal_gpio_InputPin,
@@ -59,4 +61,4 @@ pub use crate::timer::{
 };
 #[cfg(any(uart0, uart1, uart2))]
 pub use crate::uart::{Instance as _esp_hal_uart_Instance, UartPins as _esp_hal_uart_UartPins};
-pub use crate::{clock::Clock as _esp_hal_clock_Clock, entry, macros::*};
+pub use crate::{clock::Clock as _esp_hal_clock_Clock, macros::*};
diff --git a/esp32-hal/Cargo.toml b/esp32-hal/Cargo.toml
index 6a4c49b8131..5a5f9b89bb5 100644
--- a/esp32-hal/Cargo.toml
+++ b/esp32-hal/Cargo.toml
@@ -54,7 +54,7 @@ debug              = ["esp-hal-common/debug"]
 defmt              = ["esp-hal-common/defmt", "esp-println/defmt"]
 eh1                = ["esp-hal-common/eh1"]
 log                = ["esp-hal-common/log", "esp-println/log"]
-rt                 = []
+rt                 = ["esp-hal-common/rt-xtensa"]
 ufmt               = ["esp-hal-common/ufmt"]
 vectored           = ["esp-hal-common/vectored"]
 xtal-26mhz         = ["esp-hal-common/xtal-26mhz"]
diff --git a/esp32c2-hal/Cargo.toml b/esp32c2-hal/Cargo.toml
index b19dd50e0dc..a096b2c2ea5 100644
--- a/esp32c2-hal/Cargo.toml
+++ b/esp32c2-hal/Cargo.toml
@@ -55,7 +55,7 @@ direct-vectoring     = ["esp-hal-common/direct-vectoring"]
 eh1                  = ["esp-hal-common/eh1"]
 interrupt-preemption = ["esp-hal-common/interrupt-preemption"]
 log                  = ["esp-hal-common/log", "esp-println/log"]
-rt                   = []
+rt                   = ["esp-hal-common/rt-riscv"]
 ufmt                 = ["esp-hal-common/ufmt"]
 vectored             = ["esp-hal-common/vectored"]
 xtal-26mhz           = ["esp-hal-common/xtal-26mhz"]
diff --git a/esp32c3-hal/Cargo.toml b/esp32c3-hal/Cargo.toml
index 6ed3426af5c..9050dacfa9f 100644
--- a/esp32c3-hal/Cargo.toml
+++ b/esp32c3-hal/Cargo.toml
@@ -58,7 +58,7 @@ direct-vectoring     = ["esp-hal-common/direct-vectoring"]
 eh1                  = ["esp-hal-common/eh1"]
 interrupt-preemption = ["esp-hal-common/interrupt-preemption"]
 log                  = ["esp-hal-common/log", "esp-println/log"]
-rt                   = []
+rt                   = ["esp-hal-common/rt-riscv"]
 ufmt                 = ["esp-hal-common/ufmt"]
 vectored             = ["esp-hal-common/vectored"]
 
diff --git a/esp32c6-hal/Cargo.toml b/esp32c6-hal/Cargo.toml
index 4dee3f3eb30..0fab5731c71 100644
--- a/esp32c6-hal/Cargo.toml
+++ b/esp32c6-hal/Cargo.toml
@@ -60,7 +60,7 @@ direct-vectoring     = ["esp-hal-common/direct-vectoring"]
 eh1                  = ["esp-hal-common/eh1"]
 interrupt-preemption = ["esp-hal-common/interrupt-preemption"]
 log                  = ["esp-hal-common/log", "esp-println/log"]
-rt                   = []
+rt                   = ["esp-hal-common/rt-riscv"]
 ufmt                 = ["esp-hal-common/ufmt"]
 vectored             = ["esp-hal-common/vectored"]
 flip-link            = ["esp-hal-common/flip-link"]
diff --git a/esp32h2-hal/Cargo.toml b/esp32h2-hal/Cargo.toml
index 3f4f2455bd4..e87d02d3672 100644
--- a/esp32h2-hal/Cargo.toml
+++ b/esp32h2-hal/Cargo.toml
@@ -60,7 +60,7 @@ direct-vectoring     = ["esp-hal-common/direct-vectoring"]
 eh1                  = ["esp-hal-common/eh1"]
 interrupt-preemption = ["esp-hal-common/interrupt-preemption"]
 log                  = ["esp-hal-common/log", "esp-println/log"]
-rt                   = []
+rt                   = ["esp-hal-common/rt-riscv"]
 ufmt                 = ["esp-hal-common/ufmt"]
 vectored             = ["esp-hal-common/vectored"]
 flip-link            = ["esp-hal-common/flip-link"]
diff --git a/esp32s2-hal/Cargo.toml b/esp32s2-hal/Cargo.toml
index a45238db200..13901d6d18f 100644
--- a/esp32s2-hal/Cargo.toml
+++ b/esp32s2-hal/Cargo.toml
@@ -59,7 +59,7 @@ debug     = ["esp-hal-common/debug"]
 defmt     = ["esp-hal-common/defmt", "esp-println/defmt"]
 eh1       = ["esp-hal-common/eh1"]
 log       = ["esp-hal-common/log", "esp-println/log"]
-rt        = []
+rt        = ["esp-hal-common/rt-xtensa"]
 ufmt      = ["esp-hal-common/ufmt"]
 vectored  = ["esp-hal-common/vectored"]
 
diff --git a/esp32s3-hal/Cargo.toml b/esp32s3-hal/Cargo.toml
index 88a7c204bc7..0a1653fc8e7 100644
--- a/esp32s3-hal/Cargo.toml
+++ b/esp32s3-hal/Cargo.toml
@@ -59,7 +59,7 @@ debug                = ["esp-hal-common/debug"]
 defmt                = ["esp-hal-common/defmt", "esp-println/defmt"]
 eh1                  = ["esp-hal-common/eh1"]
 log                  = ["esp-hal-common/log", "esp-println/log"]
-rt                   = []
+rt                   = ["esp-hal-common/rt-xtensa"]
 ufmt                 = ["esp-hal-common/ufmt"]
 vectored             = ["esp-hal-common/vectored"]
 

From 37e8b51389e906ba9a767136b0891d7eb63ddc88 Mon Sep 17 00:00:00 2001
From: Jesse Braham <jesse@beta7.io>
Date: Tue, 2 Jan 2024 08:45:03 -0800
Subject: [PATCH 2/3] Update the CI workflow to check the chip-specific HAL
 packages without default features

---
 .github/workflows/ci.yml | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index defd22290e7..82de3c803f8 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -157,6 +157,9 @@ jobs:
           cargo check --examples --features=embassy,embassy-time-timg0,embassy-executor-interrupt,embassy-executor-thread,log
       - name: check esp32-hal (psram)
         run: cd esp32-hal/ && cargo check --example=psram --features=psram-2m --release # This example requires release!
+      # Make sure we can build without default features enabled, too!
+      - name: check esp32-hal (no default features)
+        run: cd esp32-hal/ && cargo build --no-default-features --features=xtal-40mhz
       # Ensure documentation can be built
       - name: rustdoc
         run: cd esp32-hal/ && cargo doc --features=eh1
@@ -209,6 +212,9 @@ jobs:
           cd esp32c2-hal/
           cargo +nightly check --examples --features=embassy,embassy-time-timg0,embassy-executor-thread,defmt
           cargo +nightly check --examples --features=embassy,embassy-time-timg0,embassy-executor-thread,log
+      # Make sure we can build without default features enabled, too!
+      - name: check esp32c2-hal (no default features)
+        run: cd esp32c2-hal/ && cargo build --no-default-features --features=xtal-40mhz
       # Ensure documentation can be built
       - name: rustdoc
         run: cd esp32c2-hal/ && cargo doc --features=eh1
@@ -263,6 +269,9 @@ jobs:
           cd esp32c3-hal/
           cargo +nightly check --examples --features=embassy,embassy-time-timg0,embassy-executor-thread,defmt
           cargo +nightly check --examples --features=embassy,embassy-time-timg0,embassy-executor-thread,log
+      # Make sure we can build without default features enabled, too!
+      - name: check esp32c3-hal (no default features)
+        run: cd esp32c3-hal/ && cargo build --no-default-features
       # Ensure documentation can be built
       - name: rustdoc
         run: cd esp32c3-hal/ && cargo doc --features=eh1
@@ -328,6 +337,9 @@ jobs:
           cd esp32c6-hal/
           cargo +nightly check --examples --features=embassy,embassy-time-timg0,embassy-executor-thread,defmt
           cargo +nightly check --examples --features=embassy,embassy-time-timg0,embassy-executor-thread,log
+      # Make sure we can build without default features enabled, too!
+      - name: check esp32c6-hal (no default features)
+        run: cd esp32c6-hal/ && cargo build --no-default-features
       # Ensure documentation can be built
       - name: rustdoc
         run: cd esp32c6-hal/ && cargo doc --features=eh1
@@ -408,6 +420,9 @@ jobs:
           cd esp32h2-hal/
           cargo +nightly check --examples --features=embassy,embassy-time-timg0,embassy-executor-thread,defmt
           cargo +nightly check --examples --features=embassy,embassy-time-timg0,embassy-executor-thread,log
+      # Make sure we can build without default features enabled, too!
+      - name: check esp32h2-hal (no default features)
+        run: cd esp32h2-hal/ && cargo build --no-default-features
       # Ensure documentation can be built
       - name: rustdoc
         run: cd esp32h2-hal/ && cargo doc --features=eh1
@@ -483,6 +498,9 @@ jobs:
           cargo +esp check --examples --features=embassy,embassy-time-timg0,embassy-executor-interrupt,embassy-executor-thread,log
       - name: check esp32s2-hal (psram)
         run: cd esp32s2-hal/ && cargo +esp check --example=psram --features=psram-2m --release # This example requires release!
+      # Make sure we can build without default features enabled, too!
+      - name: check esp32s2-hal (no default features)
+        run: cd esp32s2-hal/ && cargo build --no-default-features
       # Ensure documentation can be built
       - name: rustdoc
         run: cd esp32s2-hal/ && cargo +esp doc --features=eh1
@@ -565,6 +583,9 @@ jobs:
           cd esp32s3-hal/
           cargo +esp check --examples --features=embassy,embassy-time-timg0,embassy-executor-interrupt,embassy-executor-thread,defmt
           cargo +esp check --examples --features=embassy,embassy-time-timg0,embassy-executor-interrupt,embassy-executor-thread,log
+      # Make sure we can build without default features enabled, too!
+      - name: check esp32s3-hal (no default features)
+        run: cd esp32s3-hal/ && cargo build --no-default-features
       # Ensure documentation can be built
       - name: rustdoc
         run: cd esp32s3-hal/ && cargo doc --features=eh1

From 5715ffae7339df2015741c2d580cb387cd50dabc Mon Sep 17 00:00:00 2001
From: Jesse Braham <jesse@beta7.io>
Date: Tue, 2 Jan 2024 09:05:24 -0800
Subject: [PATCH 3/3] Update `CHANGELOG.md`

---
 CHANGELOG.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index cef87fe7c23..184a20a0d84 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -13,6 +13,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 - ESP32-C6: Properly initialize PMU (#974)
 - Implement overriding base mac address (#1044)
+- Add `rt-riscv` and `rt-xtensa` features to enable/disable runtime support (#1057)
 
 ### Changed