diff --git a/esp-hal/Cargo.toml b/esp-hal/Cargo.toml index 307ec0c9181..6291fb2fe2f 100644 --- a/esp-hal/Cargo.toml +++ b/esp-hal/Cargo.toml @@ -56,13 +56,13 @@ xtensa-lx = { version = "0.9.0", optional = true } # IMPORTANT: # Each supported device MUST have its PAC included below along with a # corresponding feature. -esp32 = { version = "0.33.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "390c88b", features = ["critical-section", "rt"], optional = true } -esp32c2 = { version = "0.22.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "390c88b", features = ["critical-section", "rt"], optional = true } -esp32c3 = { version = "0.25.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "390c88b", features = ["critical-section", "rt"], optional = true } -esp32c6 = { version = "0.16.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "390c88b", features = ["critical-section", "rt"], optional = true } -esp32h2 = { version = "0.12.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "390c88b", features = ["critical-section", "rt"], optional = true } -esp32s2 = { version = "0.24.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "390c88b", features = ["critical-section", "rt"], optional = true } -esp32s3 = { version = "0.28.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "390c88b", features = ["critical-section", "rt"], optional = true } +esp32 = { version = "0.33.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "c364721", features = ["critical-section", "rt"], optional = true } +esp32c2 = { version = "0.22.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "c364721", features = ["critical-section", "rt"], optional = true } +esp32c3 = { version = "0.25.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "c364721", features = ["critical-section", "rt"], optional = true } +esp32c6 = { version = "0.16.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "c364721", features = ["critical-section", "rt"], optional = true } +esp32h2 = { version = "0.12.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "c364721", features = ["critical-section", "rt"], optional = true } +esp32s2 = { version = "0.24.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "c364721", features = ["critical-section", "rt"], optional = true } +esp32s3 = { version = "0.28.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "c364721", features = ["critical-section", "rt"], optional = true } [target.'cfg(target_arch = "riscv32")'.dependencies] esp-riscv-rt = { version = "0.9.0", path = "../esp-riscv-rt" } diff --git a/esp-hal/src/aes/esp32.rs b/esp-hal/src/aes/esp32.rs index f9920a9a4d3..dd69d4c5439 100644 --- a/esp-hal/src/aes/esp32.rs +++ b/esp-hal/src/aes/esp32.rs @@ -56,7 +56,7 @@ impl<'d> Aes<'d> { } pub(super) fn write_start(&mut self) { - self.aes.start().write(|w| w.start().set_bit()) + self.aes.start().write(|w| w.start().set_bit()); } pub(super) fn read_idle(&mut self) -> bool { diff --git a/esp-hal/src/aes/esp32cX.rs b/esp-hal/src/aes/esp32cX.rs index b20923cc9e3..9477b17579b 100644 --- a/esp-hal/src/aes/esp32cX.rs +++ b/esp-hal/src/aes/esp32cX.rs @@ -13,7 +13,7 @@ impl Aes<'_> { match enable_dma { true => self.aes.dma_enable().write(|w| w.dma_enable().set_bit()), false => self.aes.dma_enable().write(|w| w.dma_enable().clear_bit()), - } + }; } pub(super) fn write_key(&mut self, key: &[u8]) { @@ -34,7 +34,7 @@ impl Aes<'_> { } pub(super) fn write_start(&mut self) { - self.aes.trigger().write(|w| w.trigger().set_bit()) + self.aes.trigger().write(|w| w.trigger().set_bit()); } pub(super) fn read_idle(&mut self) -> bool { diff --git a/esp-hal/src/aes/esp32s2.rs b/esp-hal/src/aes/esp32s2.rs index 926612821c4..d00c34d20e8 100644 --- a/esp-hal/src/aes/esp32s2.rs +++ b/esp-hal/src/aes/esp32s2.rs @@ -21,7 +21,7 @@ impl<'d> Aes<'d> { match enable_dma { true => self.aes.dma_enable().write(|w| w.dma_enable().set_bit()), false => self.aes.dma_enable().write(|w| w.dma_enable().clear_bit()), - } + }; } pub(super) fn write_key(&mut self, key: &[u8]) { @@ -67,7 +67,7 @@ impl<'d> Aes<'d> { } pub(super) fn write_start(&mut self) { - self.aes.trigger().write(|w| w.trigger().set_bit()) + self.aes.trigger().write(|w| w.trigger().set_bit()); } pub(super) fn read_idle(&mut self) -> bool { diff --git a/esp-hal/src/aes/esp32s3.rs b/esp-hal/src/aes/esp32s3.rs index 6adc108449f..3e8085348a8 100644 --- a/esp-hal/src/aes/esp32s3.rs +++ b/esp-hal/src/aes/esp32s3.rs @@ -13,7 +13,7 @@ impl<'d> Aes<'d> { match enable_dma { true => self.aes.dma_enable().write(|w| w.dma_enable().set_bit()), false => self.aes.dma_enable().write(|w| w.dma_enable().clear_bit()), - } + }; } pub(super) fn write_key(&mut self, key: &[u8]) { @@ -39,7 +39,7 @@ impl<'d> Aes<'d> { } pub(super) fn write_start(&mut self) { - self.aes.trigger().write(|w| w.trigger().set_bit()) + self.aes.trigger().write(|w| w.trigger().set_bit()); } pub(super) fn read_idle(&mut self) -> bool { diff --git a/esp-hal/src/clock/clocks_ll/esp32c6.rs b/esp-hal/src/clock/clocks_ll/esp32c6.rs index ef349384ba7..71cec2c84f9 100644 --- a/esp-hal/src/clock/clocks_ll/esp32c6.rs +++ b/esp-hal/src/clock/clocks_ll/esp32c6.rs @@ -244,7 +244,7 @@ fn clk_ll_mspi_fast_set_hs_divider(divider: u32) { .mspi_clk_conf() .modify(|_, w| w.mspi_fast_hs_div_num().bits(5)), _ => panic!("Unsupported HS MSPI_FAST divider"), - } + }; } } diff --git a/esp-hal/src/dma/gdma.rs b/esp-hal/src/dma/gdma.rs index bff710a2ec8..8b5c387eadf 100644 --- a/esp-hal/src/dma/gdma.rs +++ b/esp-hal/src/dma/gdma.rs @@ -216,7 +216,7 @@ impl InterruptAccess for ChannelTxImpl { }; } w - }) + }); } fn is_listening(&self) -> EnumSet { @@ -250,7 +250,7 @@ impl InterruptAccess for ChannelTxImpl { }; } w - }) + }); } fn pending_interrupts(&self) -> EnumSet { @@ -438,7 +438,7 @@ impl InterruptAccess for ChannelRxImpl { }; } w - }) + }); } fn pending_interrupts(&self) -> EnumSet { diff --git a/esp-hal/src/dma/pdma.rs b/esp-hal/src/dma/pdma.rs index 1659eb5f95d..098da68add1 100644 --- a/esp-hal/src/dma/pdma.rs +++ b/esp-hal/src/dma/pdma.rs @@ -124,7 +124,7 @@ impl> InterruptAccess EnumSet { @@ -160,7 +160,7 @@ impl> InterruptAccess EnumSet { @@ -259,7 +259,7 @@ impl> InterruptAccess EnumSet { @@ -299,7 +299,7 @@ impl> InterruptAccess EnumSet { @@ -535,7 +535,7 @@ impl> InterruptAccess EnumSet { @@ -592,7 +592,7 @@ impl> InterruptAccess &'static AtomicWaker { @@ -676,7 +676,7 @@ impl> InterruptAccess EnumSet { @@ -740,7 +740,7 @@ impl> InterruptAccess &'static AtomicWaker { diff --git a/esp-hal/src/i2c/master/mod.rs b/esp-hal/src/i2c/master/mod.rs index 494a085f629..b6e07e3f97f 100644 --- a/esp-hal/src/i2c/master/mod.rs +++ b/esp-hal/src/i2c/master/mod.rs @@ -1091,13 +1091,7 @@ fn async_handler(info: &Info, state: &State) { #[cfg(not(any(esp32, esp32s2)))] w.txfifo_wm().clear_bit(); - cfg_if::cfg_if! { - if #[cfg(esp32)] { - w.ack_err().clear_bit() - } else { - w.nack().clear_bit() - } - } + w.nack().clear_bit() }); state.waker.wake(); @@ -1867,7 +1861,7 @@ impl Driver<'_> { // Handle error cases let retval = if interrupts.time_out().bit_is_set() { Err(Error::TimeOut) - } else if interrupts.ack_err().bit_is_set() { + } else if interrupts.nack().bit_is_set() { Err(Error::AckCheckFailed) } else if interrupts.arbitration_lost().bit_is_set() { Err(Error::ArbitrationLost) diff --git a/esp-hal/src/interrupt/software.rs b/esp-hal/src/interrupt/software.rs index 8b4284f7b33..92dfb32d4fa 100644 --- a/esp-hal/src/interrupt/software.rs +++ b/esp-hal/src/interrupt/software.rs @@ -93,7 +93,7 @@ impl SoftwareInterrupt { .cpu_intr_from_cpu_3() .write(|w| w.cpu_intr_from_cpu_3().set_bit()), _ => unreachable!(), - } + }; } /// Resets this software-interrupt @@ -120,7 +120,7 @@ impl SoftwareInterrupt { .cpu_intr_from_cpu_3() .write(|w| w.cpu_intr_from_cpu_3().clear_bit()), _ => unreachable!(), - } + }; } /// Unsafely create an instance of this peripheral out of thin air. diff --git a/esp-hal/src/mcpwm/operator.rs b/esp-hal/src/mcpwm/operator.rs index f467d9f32fc..6bb4e3e366e 100644 --- a/esp-hal/src/mcpwm/operator.rs +++ b/esp-hal/src/mcpwm/operator.rs @@ -313,7 +313,7 @@ impl<'d, PWM: PwmPeripheral, const OP: u8, const IS_A: bool> PwmPin<'d, PWM, OP, // SAFETY: // `bits` is a valid bit pattern - ch.gen((!IS_A) as usize).write(|w| unsafe { w.bits(bits) }) + ch.gen((!IS_A) as usize).write(|w| unsafe { w.bits(bits) }); } /// Set how a new timestamp syncs with the timer @@ -334,7 +334,7 @@ impl<'d, PWM: PwmPeripheral, const OP: u8, const IS_A: bool> PwmPin<'d, PWM, OP, } else { w.b_upmethod().bits(bits) } - }) + }); } /// Write a new timestamp. @@ -347,16 +347,16 @@ impl<'d, PWM: PwmPeripheral, const OP: u8, const IS_A: bool> PwmPin<'d, PWM, OP, #[cfg(esp32s3)] if IS_A { - ch.cmpr_value0().write(|w| unsafe { w.a().bits(value) }) + ch.cmpr_value0().write(|w| unsafe { w.a().bits(value) }); } else { - ch.cmpr_value1().write(|w| unsafe { w.b().bits(value) }) + ch.cmpr_value1().write(|w| unsafe { w.b().bits(value) }); } #[cfg(any(esp32, esp32c6, esp32h2))] if IS_A { - ch.gen_tstmp_a().write(|w| unsafe { w.a().bits(value) }) + ch.gen_tstmp_a().write(|w| unsafe { w.a().bits(value) }); } else { - ch.gen_tstmp_b().write(|w| unsafe { w.b().bits(value) }) + ch.gen_tstmp_b().write(|w| unsafe { w.b().bits(value) }); } } diff --git a/esp-hal/src/rsa/esp32cX.rs b/esp-hal/src/rsa/esp32cX.rs index 88f4bf99a50..e74eac7fd7f 100644 --- a/esp-hal/src/rsa/esp32cX.rs +++ b/esp-hal/src/rsa/esp32cX.rs @@ -26,7 +26,7 @@ impl Rsa<'_, DM> { /// When enabled rsa peripheral would generate an interrupt when a operation /// is finished. pub fn enable_disable_interrupt(&mut self, enable: bool) { - self.rsa.int_ena().write(|w| w.int_ena().bit(enable)) + self.rsa.int_ena().write(|w| w.int_ena().bit(enable)); } fn write_mode(&mut self, mode: u32) { @@ -52,7 +52,7 @@ impl Rsa<'_, DM> { .rsa .search_enable() .write(|w| w.search_enable().clear_bit()), - } + }; } /// Checks if the search functionality is enabled in the RSA hardware. @@ -87,7 +87,7 @@ impl Rsa<'_, DM> { .rsa .constant_time() .write(|w| w.constant_time().set_bit()), - } + }; } /// Starts the modular exponentiation operation. diff --git a/esp-hal/src/rsa/esp32sX.rs b/esp-hal/src/rsa/esp32sX.rs index bbdad42cac4..f4404bfa471 100644 --- a/esp-hal/src/rsa/esp32sX.rs +++ b/esp-hal/src/rsa/esp32sX.rs @@ -27,7 +27,7 @@ impl<'d, DM: crate::Mode> Rsa<'d, DM> { /// When enabled rsa peripheral would generate an interrupt when a operation /// is finished. pub fn enable_disable_interrupt(&mut self, enable: bool) { - self.rsa.int_ena().write(|w| w.int_ena().bit(enable)) + self.rsa.int_ena().write(|w| w.int_ena().bit(enable)); } fn write_mode(&mut self, mode: u32) { @@ -53,7 +53,7 @@ impl<'d, DM: crate::Mode> Rsa<'d, DM> { .rsa .search_enable() .write(|w| w.search_enable().clear_bit()), - } + }; } /// Checks if the search functionality is enabled in the RSA hardware. @@ -88,7 +88,7 @@ impl<'d, DM: crate::Mode> Rsa<'d, DM> { .rsa .constant_time() .write(|w| w.constant_time().set_bit()), - } + }; } /// Starts the modular exponentiation operation. diff --git a/esp-hal/src/rtc_cntl/mod.rs b/esp-hal/src/rtc_cntl/mod.rs index 987f687cb8c..71797a64a26 100644 --- a/esp-hal/src/rtc_cntl/mod.rs +++ b/esp-hal/src/rtc_cntl/mod.rs @@ -983,7 +983,7 @@ impl Rwdt { RwdtStage::Stage3 => rtc_cntl .wdtconfig4() .modify(|_, w| w.wdt_stg3_hold().bits(timeout_raw)), - } + }; #[cfg(any(esp32c6, esp32h2))] match stage { @@ -1003,7 +1003,7 @@ impl Rwdt { w.wdt_stg3_hold() .bits(timeout_raw >> (1 + Efuse::get_rwdt_multiplier())) }), - } + }; #[cfg(not(any(esp32, esp32c6, esp32h2)))] match stage { @@ -1023,7 +1023,7 @@ impl Rwdt { w.wdt_stg3_hold() .bits(timeout_raw >> (1 + Efuse::get_rwdt_multiplier())) }), - } + }; } self.set_write_protection(true); @@ -1048,7 +1048,7 @@ impl Rwdt { RwdtStage::Stage3 => rtc_cntl .wdtconfig0() .modify(|_, w| unsafe { w.wdt_stg3().bits(action as u8) }), - } + }; self.set_write_protection(true); } diff --git a/esp-hal/src/rtc_cntl/rtc/esp32c6.rs b/esp-hal/src/rtc_cntl/rtc/esp32c6.rs index a30929f62a6..ff7efe0ed22 100644 --- a/esp-hal/src/rtc_cntl/rtc/esp32c6.rs +++ b/esp-hal/src/rtc_cntl/rtc/esp32c6.rs @@ -267,7 +267,7 @@ fn modem_clock_hal_deselect_all_wifi_lpclk_source() { .clear_bit() .clk_wifipwr_lp_sel_xtal() .clear_bit() - }) + }); } } @@ -299,7 +299,7 @@ fn modem_lpcon_ll_set_wifi_lpclk_divisor_value(divider: u16) { unsafe { modem_lpcon() .wifi_lp_clk_conf() - .modify(|_, w| w.clk_wifipwr_lp_div_num().bits(divider)) + .modify(|_, w| w.clk_wifipwr_lp_div_num().bits(divider)); } } @@ -1534,16 +1534,19 @@ impl RtcClock { } else { cali_clk_sel = RtcCaliClkSel::CaliClk32k; match cal_clk { - RtcCalSel::RtcCalRtcMux | RtcCalSel::RtcCalRcSlow | RtcCalSel::RtcCalRcFast => (), - RtcCalSel::RtcCal32kRc => pcr - .ctrl_32k_conf() - .modify(|_, w| unsafe { w.clk_32k_sel().bits(0) }), - RtcCalSel::RtcCal32kXtal => pcr - .ctrl_32k_conf() - .modify(|_, w| unsafe { w.clk_32k_sel().bits(1) }), - RtcCalSel::RtcCal32kOscSlow => pcr - .ctrl_32k_conf() - .modify(|_, w| unsafe { w.clk_32k_sel().bits(2) }), + RtcCalSel::RtcCalRtcMux | RtcCalSel::RtcCalRcSlow | RtcCalSel::RtcCalRcFast => {} + RtcCalSel::RtcCal32kRc => { + pcr.ctrl_32k_conf() + .modify(|_, w| unsafe { w.clk_32k_sel().bits(0) }); + } + RtcCalSel::RtcCal32kXtal => { + pcr.ctrl_32k_conf() + .modify(|_, w| unsafe { w.clk_32k_sel().bits(1) }); + } + RtcCalSel::RtcCal32kOscSlow => { + pcr.ctrl_32k_conf() + .modify(|_, w| unsafe { w.clk_32k_sel().bits(2) }); + } } } diff --git a/esp-hal/src/rtc_cntl/rtc/esp32h2.rs b/esp-hal/src/rtc_cntl/rtc/esp32h2.rs index 61301d68131..5419df84ebe 100644 --- a/esp-hal/src/rtc_cntl/rtc/esp32h2.rs +++ b/esp-hal/src/rtc_cntl/rtc/esp32h2.rs @@ -383,16 +383,19 @@ impl RtcClock { } else { cali_clk_sel = RtcCaliClkSel::CaliClk32k; match cal_clk { - RtcCalSel::RtcCalRtcMux | RtcCalSel::RtcCalRcSlow | RtcCalSel::RtcCalRcFast => (), - RtcCalSel::RtcCal32kRc => pcr - .ctrl_32k_conf() - .modify(|_, w| unsafe { w.clk_32k_sel().bits(0) }), - RtcCalSel::RtcCal32kXtal => pcr - .ctrl_32k_conf() - .modify(|_, w| unsafe { w.clk_32k_sel().bits(1) }), - RtcCalSel::RtcCal32kOscSlow => pcr - .ctrl_32k_conf() - .modify(|_, w| unsafe { w.clk_32k_sel().bits(2) }), + RtcCalSel::RtcCalRtcMux | RtcCalSel::RtcCalRcSlow | RtcCalSel::RtcCalRcFast => {} + RtcCalSel::RtcCal32kRc => { + pcr.ctrl_32k_conf() + .modify(|_, w| unsafe { w.clk_32k_sel().bits(0) }); + } + RtcCalSel::RtcCal32kXtal => { + pcr.ctrl_32k_conf() + .modify(|_, w| unsafe { w.clk_32k_sel().bits(1) }); + } + RtcCalSel::RtcCal32kOscSlow => { + pcr.ctrl_32k_conf() + .modify(|_, w| unsafe { w.clk_32k_sel().bits(2) }); + } } } diff --git a/esp-hal/src/soc/esp32c6/lp_core.rs b/esp-hal/src/soc/esp32c6/lp_core.rs index 151e47268f1..ac7674071fc 100644 --- a/esp-hal/src/soc/esp32c6/lp_core.rs +++ b/esp-hal/src/soc/esp32c6/lp_core.rs @@ -63,12 +63,12 @@ impl<'d> LpCore<'d> { LpCoreClockSource::RcFastClk => unsafe { (*crate::soc::peripherals::LP_CLKRST::PTR) .lp_clk_conf() - .modify(|_, w| w.fast_clk_sel().clear_bit()) + .modify(|_, w| w.fast_clk_sel().clear_bit()); }, LpCoreClockSource::XtalD2Clk => unsafe { (*crate::soc::peripherals::LP_CLKRST::PTR) .lp_clk_conf() - .modify(|_, w| w.fast_clk_sel().set_bit()) + .modify(|_, w| w.fast_clk_sel().set_bit()); }, } diff --git a/esp-hal/src/soc/esp32s3/psram.rs b/esp-hal/src/soc/esp32s3/psram.rs index 27067c93724..1083b5ac896 100644 --- a/esp-hal/src/soc/esp32s3/psram.rs +++ b/esp-hal/src/soc/esp32s3/psram.rs @@ -708,7 +708,7 @@ pub(crate) mod utils { let iomux = &*esp32s3::IO_MUX::PTR; iomux .gpio(cs1_io as usize) - .modify(|_, w| w.mcu_sel().bits(FUNC_SPICS1_SPICS1)) + .modify(|_, w| w.mcu_sel().bits(FUNC_SPICS1_SPICS1)); } } else { unsafe { @@ -717,7 +717,7 @@ pub(crate) mod utils { let iomux = &*esp32s3::IO_MUX::PTR; iomux .gpio(cs1_io as usize) - .modify(|_, w| w.mcu_sel().bits(PIN_FUNC_GPIO)) + .modify(|_, w| w.mcu_sel().bits(PIN_FUNC_GPIO)); } } @@ -1156,7 +1156,7 @@ pub(crate) mod utils { spi.sram_cmd().modify(|_, w| w.sdout_oct().set_bit()); spi.sram_cmd().modify(|_, w| w.sdin_oct().set_bit()); - spi.cache_sctrl().modify(|_, w| w.sram_oct().set_bit()) + spi.cache_sctrl().modify(|_, w| w.sram_oct().set_bit()); } } @@ -1164,7 +1164,7 @@ pub(crate) mod utils { fn spi_flash_set_rom_required_regs() { // Disable the variable dummy mode when doing timing tuning let spi = unsafe { &*crate::peripherals::SPI1::PTR }; - spi.ddr().modify(|_, w| w.spi_fmem_var_dummy().clear_bit()) + spi.ddr().modify(|_, w| w.spi_fmem_var_dummy().clear_bit()); // STR /DTR mode setting is done every time when // `esp_rom_opiflash_exec_cmd` is called // @@ -1199,7 +1199,7 @@ pub(crate) mod utils { let pins = &[27usize, 28, 31, 32, 33, 34, 35, 36, 37]; for pin in pins { let iomux = &*esp32s3::IO_MUX::PTR; - iomux.gpio(*pin).modify(|_, w| w.fun_drv().bits(3)) + iomux.gpio(*pin).modify(|_, w| w.fun_drv().bits(3)); } } } @@ -1287,7 +1287,7 @@ pub(crate) mod utils { let iomux = &*esp32s3::IO_MUX::PTR; iomux .gpio(OCT_PSRAM_CS1_IO as usize) - .modify(|_, w| w.mcu_sel().bits(FUNC_SPICS1_SPICS1)) + .modify(|_, w| w.mcu_sel().bits(FUNC_SPICS1_SPICS1)); } // Set mspi cs1 drive strength @@ -1295,7 +1295,7 @@ pub(crate) mod utils { let iomux = &*esp32s3::IO_MUX::PTR; iomux .gpio(OCT_PSRAM_CS1_IO as usize) - .modify(|_, w| w.fun_drv().bits(3)) + .modify(|_, w| w.fun_drv().bits(3)); } // Set psram clock pin drive strength diff --git a/esp-hal/src/timer/timg.rs b/esp-hal/src/timer/timg.rs index 8f67b33db23..40be2cd2bf8 100644 --- a/esp-hal/src/timer/timg.rs +++ b/esp-hal/src/timer/timg.rs @@ -804,7 +804,7 @@ where fn set_divider(&self, divider: u16) { unsafe { Self::t() } .config() - .modify(|_, w| unsafe { w.divider().bits(divider) }) + .modify(|_, w| unsafe { w.divider().bits(divider) }); } } @@ -1074,7 +1074,7 @@ where MwdtStage::Stage3 => reg_block .wdtconfig5() .write(|w| w.wdt_stg3_hold().bits(timeout_raw)), - } + }; } #[cfg(any(esp32c2, esp32c3, esp32c6))] diff --git a/esp-hal/src/usb_serial_jtag.rs b/esp-hal/src/usb_serial_jtag.rs index 42c82f8aacd..c94c2be6c93 100644 --- a/esp-hal/src/usb_serial_jtag.rs +++ b/esp-hal/src/usb_serial_jtag.rs @@ -264,7 +264,7 @@ where pub fn reset_rx_packet_recv_interrupt(&mut self) { USB_DEVICE::register_block() .int_clr() - .write(|w| w.serial_out_recv_pkt().clear_bit_by_one()) + .write(|w| w.serial_out_recv_pkt().clear_bit_by_one()); } } @@ -408,7 +408,7 @@ pub trait Instance: crate::private::Sealed { Self::register_block() .int_clr() - .write(|w| w.serial_in_empty().clear_bit_by_one()) + .write(|w| w.serial_in_empty().clear_bit_by_one()); } /// Disable all receive interrupts for the peripheral @@ -419,7 +419,7 @@ pub trait Instance: crate::private::Sealed { Self::register_block() .int_clr() - .write(|w| w.serial_out_recv_pkt().clear_bit_by_one()) + .write(|w| w.serial_out_recv_pkt().clear_bit_by_one()); } } diff --git a/esp-ieee802154/src/hal.rs b/esp-ieee802154/src/hal.rs index c43cb379adf..dd116715977 100644 --- a/esp-ieee802154/src/hal.rs +++ b/esp-ieee802154/src/hal.rs @@ -244,7 +244,7 @@ pub(crate) fn set_tx_addr(addr: *const u8) { pub(crate) fn set_cmd(cmd: Command) { unsafe { &*IEEE802154::PTR } .command() - .modify(|_, w| unsafe { w.opcode().bits(cmd as u8) }) + .modify(|_, w| unsafe { w.opcode().bits(cmd as u8) }); } #[inline(always)] @@ -271,7 +271,7 @@ pub(crate) fn set_multipan_enable_mask(mask: u8) { // apparently the REGS are garbage and the struct is right? unsafe { &*IEEE802154::PTR } .ctrl_cfg() - .modify(|r, w| unsafe { w.bits(r.bits() & !(0b1111 << 29) | (mask as u32) << 29) }) + .modify(|r, w| unsafe { w.bits(r.bits() & !(0b1111 << 29) | (mask as u32) << 29) }); } #[inline(always)] @@ -333,7 +333,7 @@ pub(crate) fn set_cca_mode(cca_mode: CcaMode) { pub(crate) fn set_cca_threshold(cca_threshold: i8) { unsafe { &*IEEE802154::PTR } .ed_scan_cfg() - .modify(|_, w| unsafe { w.cca_ed_threshold().bits(cca_threshold as u8) }) + .modify(|_, w| unsafe { w.cca_ed_threshold().bits(cca_threshold as u8) }); } #[inline(always)]