From 0a95f08e53d91e2c321ca2ec580918c9becbb0a3 Mon Sep 17 00:00:00 2001 From: Zach Grimaldi Date: Thu, 12 Dec 2024 20:39:47 -0500 Subject: [PATCH 1/4] feat(uart): config option to disable the rx input checks --- esp-hal/src/uart.rs | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/esp-hal/src/uart.rs b/esp-hal/src/uart.rs index a727745b613..4d1bd8b9c5d 100644 --- a/esp-hal/src/uart.rs +++ b/esp-hal/src/uart.rs @@ -404,6 +404,8 @@ pub struct Config { pub rx_fifo_full_threshold: u16, /// Optional timeout value for RX operations. pub rx_timeout: Option, + /// Optionally disable forced checks on incoming RX inputs. + pub disable_rx_input_checks: bool, } impl Config { @@ -481,6 +483,12 @@ impl Config { self.rx_timeout = timeout; self } + + /// Disables forced checks on incoming RX inputs. + pub fn disable_rx_input_checks(mut self, disable: bool) -> Self { + self.disable_rx_input_checks = disable; + self + } } impl Default for Config { @@ -493,6 +501,7 @@ impl Default for Config { clock_source: Default::default(), rx_fifo_full_threshold: UART_FULL_THRESH_DEFAULT, rx_timeout: Some(UART_TOUT_THRESH_DEFAULT), + disable_rx_input_checks: false, } } } @@ -1268,9 +1277,11 @@ where // Setting err_wr_mask stops uart from storing data when data is wrong according // to reference manual - self.register_block() - .conf0() - .modify(|_, w| w.err_wr_mask().set_bit()); + if !config.disable_rx_input_checks { + self.register_block() + .conf0() + .modify(|_, w| w.err_wr_mask().set_bit()); + } crate::rom::ets_delay_us(15); From 4044083479252d1e3efce914411e56e66e394ec3 Mon Sep 17 00:00:00 2001 From: Zach Grimaldi Date: Thu, 12 Dec 2024 20:59:06 -0500 Subject: [PATCH 2/4] docs: add to changelog --- esp-hal/CHANGELOG.md | 1 + esp-hal/src/uart.rs | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/esp-hal/CHANGELOG.md b/esp-hal/CHANGELOG.md index f570383b6b3..316c2b46b08 100644 --- a/esp-hal/CHANGELOG.md +++ b/esp-hal/CHANGELOG.md @@ -32,6 +32,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 - `BurstConfig`, a device-specific configuration for configuring DMA transfers in burst mode (#2543) - `{DmaRxBuf, DmaTxBuf, DmaRxTxBuf}::set_burst_config` (#2543) - ESP32-S2: DMA support for AES (#2699) +- Added `disable_rx_input_checks` to `uart::Config` for cases like reading LIN Break (#2756) ### Changed diff --git a/esp-hal/src/uart.rs b/esp-hal/src/uart.rs index 4d1bd8b9c5d..1fce8627e91 100644 --- a/esp-hal/src/uart.rs +++ b/esp-hal/src/uart.rs @@ -404,7 +404,7 @@ pub struct Config { pub rx_fifo_full_threshold: u16, /// Optional timeout value for RX operations. pub rx_timeout: Option, - /// Optionally disable forced checks on incoming RX inputs. + /// Optionally disable forced checks on incoming RX data. pub disable_rx_input_checks: bool, } From b6366d6c614ca558027933b7f3df8faa7ff73031 Mon Sep 17 00:00:00 2001 From: Zach Grimaldi Date: Thu, 12 Dec 2024 21:27:01 -0500 Subject: [PATCH 3/4] fix: add to `apply_config` so that it can be toggled --- esp-hal/src/uart.rs | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/esp-hal/src/uart.rs b/esp-hal/src/uart.rs index 1fce8627e91..d3d488d017c 100644 --- a/esp-hal/src/uart.rs +++ b/esp-hal/src/uart.rs @@ -2352,6 +2352,7 @@ impl Info { self.change_data_bits(config.data_bits); self.change_parity(config.parity); self.change_stop_bits(config.stop_bits); + self.change_disable_rx_input_checks(config.disable_rx_input_checks); // Reset Tx/Rx FIFOs self.rxfifo_reset(); @@ -2619,6 +2620,12 @@ impl Info { .modify(|_, w| unsafe { w.stop_bit_num().bits(stop_bits as u8) }); } + fn change_disable_rx_input_checks(&self, disable: bool) { + self.register_block() + .conf0() + .modify(|_, w| w.rx_filter_en().bit(!disable)); + } + fn rxfifo_reset(&self) { fn rxfifo_rst(reg_block: &RegisterBlock, enable: bool) { reg_block.conf0().modify(|_, w| w.rxfifo_rst().bit(enable)); From 8f0609b5a7069f72f5d8ed71fb267a2bc7f886b3 Mon Sep 17 00:00:00 2001 From: Zach Grimaldi Date: Thu, 12 Dec 2024 21:31:22 -0500 Subject: [PATCH 4/4] fix: register name --- esp-hal/src/uart.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/esp-hal/src/uart.rs b/esp-hal/src/uart.rs index d3d488d017c..8ddc649ff57 100644 --- a/esp-hal/src/uart.rs +++ b/esp-hal/src/uart.rs @@ -2623,7 +2623,7 @@ impl Info { fn change_disable_rx_input_checks(&self, disable: bool) { self.register_block() .conf0() - .modify(|_, w| w.rx_filter_en().bit(!disable)); + .modify(|_, w| w.err_wr_mask().bit(!disable)); } fn rxfifo_reset(&self) {