diff --git a/esp-hal/CHANGELOG.md b/esp-hal/CHANGELOG.md
index 145bb8788d..604bfcdd6f 100644
--- a/esp-hal/CHANGELOG.md
+++ b/esp-hal/CHANGELOG.md
@@ -49,6 +49,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - `gpio::{Event, WakeEvent, GpioRegisterAccess}` now implement `Debug`, `Eq`, `PartialEq` and `Hash` (#2842)
 - `gpio::{Level, Pull, AlternateFunction, RtcFunction}` now implement `Hash` (#2842)
 - `gpio::{GpioPin, AnyPin, Io, Output, OutputOpenDrain, Input, Flex}` now implement `Debug`, `defmt::Format` (#2842)
+- Add `tx_idle_num` to `uart::Config` with documentation of the expected transmission behavior (#2859)
 - More interrupts are available in `esp_hal::spi::master::SpiInterrupt`, add `enable_listen`,`interrupts` and `clear_interrupts` for ESP32/ESP32-S2 (#2833)
 
 - The `ExtU64` and `RateExtU32` traits have been added to `esp_hal::time` (#2845)
diff --git a/esp-hal/src/uart.rs b/esp-hal/src/uart.rs
index 0091cdf22b..3cc194919b 100644
--- a/esp-hal/src/uart.rs
+++ b/esp-hal/src/uart.rs
@@ -418,6 +418,11 @@ pub struct Config {
     pub rx_fifo_full_threshold: u16,
     /// Optional timeout value for RX operations.
     pub rx_timeout: Option<u8>,
+    /// Duration between transfers in the unit of bit time, i.e. the time it
+    /// takes to transfer one bit. If you are expecting bytes written to
+    /// be sent immediately, set this to 0. Default value is 256,
+    /// maximum value is 1023.
+    pub tx_idle_num: u16,
 }
 
 impl Config {
@@ -507,6 +512,7 @@ impl Default for Config {
             clock_source: Default::default(),
             rx_fifo_full_threshold: UART_FULL_THRESH_DEFAULT,
             rx_timeout: Some(UART_TOUT_THRESH_DEFAULT),
+            tx_idle_num: 256,
         }
     }
 }
@@ -630,6 +636,10 @@ pub enum ConfigError {
     UnsupportedTimeout,
     /// The requested FIFO threshold is not supported.
     UnsupportedFifoThreshold,
+    /// The requested idle number is not supported.
+    /// Valid range is 0..=1023 in the unit of bit time,
+    /// i.e. the time it takes to transfer one bit.
+    UnsupportedIdleNum,
 }
 
 impl core::error::Error for ConfigError {}
@@ -641,6 +651,9 @@ impl core::fmt::Display for ConfigError {
             ConfigError::UnsupportedFifoThreshold => {
                 write!(f, "The requested FIFO threshold is not supported")
             }
+            ConfigError::UnsupportedIdleNum => {
+                write!(f, "The requested tx_idle_num is not supported.")
+            }
         }
     }
 }
@@ -2361,6 +2374,7 @@ impl Info {
         self.change_data_bits(config.data_bits);
         self.change_parity(config.parity);
         self.change_stop_bits(config.stop_bits);
+        self.change_tx_idle(config.tx_idle_num)?;
 
         // Reset Tx/Rx FIFOs
         self.rxfifo_reset();
@@ -2628,6 +2642,18 @@ impl Info {
             .modify(|_, w| unsafe { w.stop_bit_num().bits(stop_bits as u8) });
     }
 
+    fn change_tx_idle(&self, idle_num: u16) -> Result<(), ConfigError> {
+        // Bits 10:19 => 10-bit register has max value of 1023.
+        if idle_num > 0x3FF {
+            return Err(ConfigError::UnsupportedIdleNum);
+        }
+        self.register_block()
+            .idle_conf()
+            .modify(|_, w| unsafe { w.tx_idle_num().bits(idle_num) });
+
+        Ok(())
+    }
+
     fn rxfifo_reset(&self) {
         fn rxfifo_rst(reg_block: &RegisterBlock, enable: bool) {
             reg_block.conf0().modify(|_, w| w.rxfifo_rst().bit(enable));