From 54457716b71b5056f1794b8766aa763e7c82e3ec Mon Sep 17 00:00:00 2001 From: Zach Grimaldi Date: Sat, 21 Dec 2024 13:32:58 -0500 Subject: [PATCH 1/4] feat: uart configurable `tx_idle_num` --- esp-hal/CHANGELOG.md | 1 + esp-hal/src/uart.rs | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/esp-hal/CHANGELOG.md b/esp-hal/CHANGELOG.md index 145bb8788d..604bfcdd6f 100644 --- a/esp-hal/CHANGELOG.md +++ b/esp-hal/CHANGELOG.md @@ -49,6 +49,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 - `gpio::{Event, WakeEvent, GpioRegisterAccess}` now implement `Debug`, `Eq`, `PartialEq` and `Hash` (#2842) - `gpio::{Level, Pull, AlternateFunction, RtcFunction}` now implement `Hash` (#2842) - `gpio::{GpioPin, AnyPin, Io, Output, OutputOpenDrain, Input, Flex}` now implement `Debug`, `defmt::Format` (#2842) +- Add `tx_idle_num` to `uart::Config` with documentation of the expected transmission behavior (#2859) - More interrupts are available in `esp_hal::spi::master::SpiInterrupt`, add `enable_listen`,`interrupts` and `clear_interrupts` for ESP32/ESP32-S2 (#2833) - The `ExtU64` and `RateExtU32` traits have been added to `esp_hal::time` (#2845) diff --git a/esp-hal/src/uart.rs b/esp-hal/src/uart.rs index 0091cdf22b..5fc6e457f8 100644 --- a/esp-hal/src/uart.rs +++ b/esp-hal/src/uart.rs @@ -418,6 +418,11 @@ pub struct Config { pub rx_fifo_full_threshold: u16, /// Optional timeout value for RX operations. pub rx_timeout: Option, + /// Duration between transfers in bits. The duration of time would + /// be based on your configured baud rate. If you are expecting bytes + /// written to be sent immediately, set this to 0. Default value is 256, + /// maximum value is 1023. + pub tx_idle_num: u16, } impl Config { @@ -463,6 +468,20 @@ impl Config { self } + /// Sets duration between transfers in bits. The duration of time would + /// be based on your configured baud rate. If you are expecting bytes + /// written to be sent immediately, set this to 0. Default value is 256, + /// maximum value is 1023. + pub fn tx_idle_num(mut self, tx_idle_num: u16) -> Self { + // Bits 10:19 => 10-bit register has max value of 1023. + assert!( + tx_idle_num <= 0x3FF, + "Invalid tx_idle_num, 10-bit register has max value of 1023." + ); + self.tx_idle_num = tx_idle_num; + self + } + /// Calculates the total symbol length in bits based on the configured /// data bits, parity, and stop bits. pub fn symbol_length(&self) -> u8 { @@ -507,6 +526,7 @@ impl Default for Config { clock_source: Default::default(), rx_fifo_full_threshold: UART_FULL_THRESH_DEFAULT, rx_timeout: Some(UART_TOUT_THRESH_DEFAULT), + tx_idle_num: 256, } } } @@ -2361,6 +2381,7 @@ impl Info { self.change_data_bits(config.data_bits); self.change_parity(config.parity); self.change_stop_bits(config.stop_bits); + self.change_tx_idle(config.tx_idle_num); // Reset Tx/Rx FIFOs self.rxfifo_reset(); @@ -2628,6 +2649,17 @@ impl Info { .modify(|_, w| unsafe { w.stop_bit_num().bits(stop_bits as u8) }); } + fn change_tx_idle(&self, idle_num: u16) { + // Bits 10:19 => 10-bit register has max value of 1023. + assert!( + idle_num <= 0x3FF, + "Invalid idle_num, 10-bit register has max value of 1023." + ); + self.register_block() + .idle_conf() + .modify(|_, w| unsafe { w.tx_idle_num().bits(idle_num) }); + } + fn rxfifo_reset(&self) { fn rxfifo_rst(reg_block: &RegisterBlock, enable: bool) { reg_block.conf0().modify(|_, w| w.rxfifo_rst().bit(enable)); From 67e8d737217c5ce0671c9fa81a5f437b73d53ae7 Mon Sep 17 00:00:00 2001 From: Zach Grimaldi Date: Sat, 21 Dec 2024 14:45:48 -0500 Subject: [PATCH 2/4] fix: remove extraneous setter --- esp-hal/src/uart.rs | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/esp-hal/src/uart.rs b/esp-hal/src/uart.rs index 5fc6e457f8..5273a659a0 100644 --- a/esp-hal/src/uart.rs +++ b/esp-hal/src/uart.rs @@ -468,20 +468,6 @@ impl Config { self } - /// Sets duration between transfers in bits. The duration of time would - /// be based on your configured baud rate. If you are expecting bytes - /// written to be sent immediately, set this to 0. Default value is 256, - /// maximum value is 1023. - pub fn tx_idle_num(mut self, tx_idle_num: u16) -> Self { - // Bits 10:19 => 10-bit register has max value of 1023. - assert!( - tx_idle_num <= 0x3FF, - "Invalid tx_idle_num, 10-bit register has max value of 1023." - ); - self.tx_idle_num = tx_idle_num; - self - } - /// Calculates the total symbol length in bits based on the configured /// data bits, parity, and stop bits. pub fn symbol_length(&self) -> u8 { From 32057789119978dbd8757e50f08d502673536d7c Mon Sep 17 00:00:00 2001 From: Zach Grimaldi Date: Sat, 21 Dec 2024 14:54:40 -0500 Subject: [PATCH 3/4] fix: use `ConfigError` instead of `assert!`; clarify unit of bit time --- esp-hal/src/uart.rs | 30 +++++++++++++++++++++--------- 1 file changed, 21 insertions(+), 9 deletions(-) diff --git a/esp-hal/src/uart.rs b/esp-hal/src/uart.rs index 5273a659a0..ae95e6cb22 100644 --- a/esp-hal/src/uart.rs +++ b/esp-hal/src/uart.rs @@ -418,9 +418,9 @@ pub struct Config { pub rx_fifo_full_threshold: u16, /// Optional timeout value for RX operations. pub rx_timeout: Option, - /// Duration between transfers in bits. The duration of time would - /// be based on your configured baud rate. If you are expecting bytes - /// written to be sent immediately, set this to 0. Default value is 256, + /// Duration between transfers in the unit of bit time, i.e. the time it + /// takes to transfer one bit. If you are expecting bytes written to + /// be sent immediately, set this to 0. Default value is 256, /// maximum value is 1023. pub tx_idle_num: u16, } @@ -636,6 +636,10 @@ pub enum ConfigError { UnsupportedTimeout, /// The requested FIFO threshold is not supported. UnsupportedFifoThreshold, + /// The requested idle number is not supported. + /// Valid range is 0..=1023 in the unit of bit time, + /// i.e. the time it takes to transfer one bit. + UnsupportedIdleNum, } impl core::error::Error for ConfigError {} @@ -647,6 +651,9 @@ impl core::fmt::Display for ConfigError { ConfigError::UnsupportedFifoThreshold => { write!(f, "The requested FIFO threshold is not supported") } + ConfigError::UnsupportedIdleNum => { + write!(f, "The requested tx_idle_num is not supported.") + } } } } @@ -2367,7 +2374,7 @@ impl Info { self.change_data_bits(config.data_bits); self.change_parity(config.parity); self.change_stop_bits(config.stop_bits); - self.change_tx_idle(config.tx_idle_num); + self.change_tx_idle(config.tx_idle_num)?; // Reset Tx/Rx FIFOs self.rxfifo_reset(); @@ -2635,15 +2642,20 @@ impl Info { .modify(|_, w| unsafe { w.stop_bit_num().bits(stop_bits as u8) }); } - fn change_tx_idle(&self, idle_num: u16) { + fn change_tx_idle(&self, idle_num: u16) -> Result<(), ConfigError> { // Bits 10:19 => 10-bit register has max value of 1023. - assert!( - idle_num <= 0x3FF, - "Invalid idle_num, 10-bit register has max value of 1023." - ); + // assert!( + // idle_num <= 0x3FF, + // "Invalid idle_num, 10-bit register has max value of 1023." + // ); + if idle_num > 0x3FF { + return Err(ConfigError::UnsupportedIdleNum); + } self.register_block() .idle_conf() .modify(|_, w| unsafe { w.tx_idle_num().bits(idle_num) }); + + Ok(()) } fn rxfifo_reset(&self) { From e06448461bd0ecf03d2716c813afaf1f8a39bdf3 Mon Sep 17 00:00:00 2001 From: Zach Grimaldi Date: Sat, 21 Dec 2024 14:57:20 -0500 Subject: [PATCH 4/4] fix: remove unneeded assert --- esp-hal/src/uart.rs | 4 ---- 1 file changed, 4 deletions(-) diff --git a/esp-hal/src/uart.rs b/esp-hal/src/uart.rs index ae95e6cb22..3cc194919b 100644 --- a/esp-hal/src/uart.rs +++ b/esp-hal/src/uart.rs @@ -2644,10 +2644,6 @@ impl Info { fn change_tx_idle(&self, idle_num: u16) -> Result<(), ConfigError> { // Bits 10:19 => 10-bit register has max value of 1023. - // assert!( - // idle_num <= 0x3FF, - // "Invalid idle_num, 10-bit register has max value of 1023." - // ); if idle_num > 0x3FF { return Err(ConfigError::UnsupportedIdleNum); }