From cce522a46389ec5695ae6e828c2a727bf19b9001 Mon Sep 17 00:00:00 2001 From: bjoernQ Date: Tue, 7 Nov 2023 14:58:16 +0100 Subject: [PATCH 1/2] Configurable LP Core clock --- esp-hal-common/src/soc/esp32c6/lp_core.rs | 36 +++++++++++++++++++++++ esp32c6-lp-hal/src/delay.rs | 2 +- esp32c6-lp-hal/src/lib.rs | 11 ++++++- 3 files changed, 47 insertions(+), 2 deletions(-) diff --git a/esp-hal-common/src/soc/esp32c6/lp_core.rs b/esp-hal-common/src/soc/esp32c6/lp_core.rs index 4c322e03e7f..8ef3e4f0570 100644 --- a/esp-hal-common/src/soc/esp32c6/lp_core.rs +++ b/esp-hal-common/src/soc/esp32c6/lp_core.rs @@ -68,20 +68,56 @@ pub enum LpCoreWakeupSource { HpCpu, } +/// Clock sources for the LP core +#[derive(Debug, Clone, Copy)] +pub enum LpCoreClockSource { + /// 17.5 MHz clock + /// + /// Might not be very accurate + RcFastClk, + /// 20 MHz clock + XtalD2Clk, +} + pub struct LpCore<'d> { _lp_core: PeripheralRef<'d, crate::soc::peripherals::LP_CORE>, } impl<'d> LpCore<'d> { + /// Create a new instance using [LpCoreClockSource::RcFastClk] pub fn new(lp_core: impl Peripheral

+ 'd) -> Self { + LpCore::new_with_clock(lp_core, LpCoreClockSource::RcFastClk) + } + + /// Create a new instance using the given clock + pub fn new_with_clock( + lp_core: impl Peripheral

+ 'd, + clk_src: LpCoreClockSource, + ) -> Self { crate::into_ref!(lp_core); + + match clk_src { + LpCoreClockSource::RcFastClk => unsafe { + (&*crate::soc::peripherals::LP_CLKRST::PTR) + .lp_clk_conf + .modify(|_, w| w.fast_clk_sel().clear_bit()) + }, + LpCoreClockSource::XtalD2Clk => unsafe { + (&*crate::soc::peripherals::LP_CLKRST::PTR) + .lp_clk_conf + .modify(|_, w| w.fast_clk_sel().set_bit()) + }, + } + Self { _lp_core: lp_core } } + /// Stop the LP core pub fn stop(&mut self) { ulp_lp_core_stop(); } + /// Start the LP core pub fn run(&mut self, wakeup_src: LpCoreWakeupSource) { ulp_lp_core_run(wakeup_src); } diff --git a/esp32c6-lp-hal/src/delay.rs b/esp32c6-lp-hal/src/delay.rs index e74a0c3c83b..2439495e521 100644 --- a/esp32c6-lp-hal/src/delay.rs +++ b/esp32c6-lp-hal/src/delay.rs @@ -14,7 +14,7 @@ pub struct Delay { impl Delay { pub fn new() -> Self { Self { - rv_delay: riscv::delay::McycleDelay::new(CPU_CLOCK), + rv_delay: riscv::delay::McycleDelay::new(unsafe { CPU_CLOCK }), } } } diff --git a/esp32c6-lp-hal/src/lib.rs b/esp32c6-lp-hal/src/lib.rs index 2c116927488..3bfa0fe3d12 100644 --- a/esp32c6-lp-hal/src/lib.rs +++ b/esp32c6-lp-hal/src/lib.rs @@ -14,7 +14,11 @@ pub mod riscv { } pub mod prelude; -const CPU_CLOCK: u32 = 16_000_000; +// LP_FAST_CLK is not very accurate, for now use a rough estimate +const LP_FAST_CLK_HZ: u32 = 16_000_000; +const XTAL_D2_CLK_HZ: u32 = 20_000_000; + +pub static mut CPU_CLOCK: u32 = LP_FAST_CLK_HZ; global_asm!( r#" @@ -60,6 +64,11 @@ unsafe extern "C" fn lp_core_startup() -> ! { fn main() -> !; } + let clkrst = &*esp32c6_lp::LP_CLKRST::PTR; + if clkrst.lp_clk_conf.read().fast_clk_sel().bit_is_set() { + CPU_CLOCK = XTAL_D2_CLK_HZ; + } + main(); } From 95a0f11ec99eeb82da5e40d7b3a03f1e07f1e145 Mon Sep 17 00:00:00 2001 From: bjoernQ Date: Tue, 7 Nov 2023 15:00:58 +0100 Subject: [PATCH 2/2] CHANGELOG.md entry --- CHANGELOG.md | 1 + 1 file changed, 1 insertion(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index 70adf1ee5ac..6392c7f82d8 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 ## [Unreleased] ### Added +- ESP32-C6: LP core clock is configurable (#907) ### Changed