diff --git a/src/spi.rs b/src/spi.rs
index 934efdd3345..b541f7c3652 100644
--- a/src/spi.rs
+++ b/src/spi.rs
@@ -243,6 +243,11 @@ pub mod config {
         pub duplex: Duplex,
         pub bit_order: BitOrder,
         pub cs_active_high: bool,
+        /// On Half-Duplex transactions: `cs_pre_delay_us % 16`  corresponds to the number of SPI bit-cycles cs should be activated before the transmission.
+        /// On Full-Duplex transactions: `cs_pre_delay_us != 0`  will add 1 microsecond of cs activation before transmission
+        pub cs_pre_delay_us: Option<u16>, // u16 as per the C struct has a uint16_t, cf: esp-idf/components/driver/spi/include/driver/spi_master.h spi_device_interface_config_t
+        ///< Amount of SPI bit-cycles the cs should stay active after the transmission (0-16)
+        pub cs_post_delay_us: Option<u8>, // u8 as per the C struct had a uint8_t, cf: esp-idf/components/driver/spi/include/driver/spi_master.h spi_device_interface_config_t
         pub input_delay_ns: i32,
         pub polling: bool,
         pub allow_pre_post_delays: bool,
@@ -290,6 +295,22 @@ pub mod config {
             self
         }
 
+        /// On Half-Duplex transactions: `cs_pre_delay_us % 16`  corresponds to the number of SPI bit-cycles cs should be activated before the transmission
+        /// On Full-Duplex transactions: `cs_pre_delay_us != 0`  will add 1 microsecond of cs activation before transmission
+        #[must_use]
+        pub fn cs_pre_delay_us(mut self, delay_us: u16) -> Self {
+            self.cs_pre_delay_us = Some(delay_us);
+            self
+        }
+
+        /// Add an aditional Amount of SPI bit-cycles the cs should be activated after the transmission (0-16).
+        /// This only works on half-duplex transactions.
+        #[must_use]
+        pub fn cs_post_delay_us(mut self, delay_us: u8) -> Self {
+            self.cs_post_delay_us = Some(delay_us);
+            self
+        }
+
         #[must_use]
         pub fn input_delay_ns(mut self, input_delay_ns: i32) -> Self {
             self.input_delay_ns = input_delay_ns;
@@ -324,6 +345,8 @@ pub mod config {
                 cs_active_high: false,
                 duplex: Duplex::Full,
                 bit_order: BitOrder::MsbFirst,
+                cs_pre_delay_us: None,
+                cs_post_delay_us: None,
                 input_delay_ns: 0,
                 polling: true,
                 allow_pre_post_delays: false,
@@ -490,6 +513,8 @@ where
                 0_u32
             } | config.duplex.as_flags()
                 | config.bit_order.as_flags(),
+            cs_ena_pretrans: config.cs_pre_delay_us.unwrap_or(0),
+            cs_ena_posttrans: config.cs_post_delay_us.unwrap_or(0),
             post_cb: Some(spi_notify),
             ..Default::default()
         };
@@ -795,6 +820,8 @@ where
             } | config.duplex.as_flags()
                 | config.bit_order.as_flags(),
             post_cb: Some(spi_notify),
+            cs_ena_pretrans: config.cs_pre_delay_us.unwrap_or(0),
+            cs_ena_posttrans: config.cs_post_delay_us.unwrap_or(0),
             ..Default::default()
         };
 
@@ -1343,8 +1370,8 @@ where
         })
     }
 
-    /// Add an aditional delay of x in uSeconds before transaction
-    /// between chip select and first clk out
+    /// Add an aditional Amount of SPI bit-cycles the cs should be activated before the transmission (0-16).
+    /// This only works on half-duplex transactions.
     pub fn cs_pre_delay_us(&mut self, delay_us: u32) -> &mut Self {
         self.pre_delay_us = Some(delay_us);