A buffer in between of IF and ID to handle RVC.
Instruction data struction from instruction fetch unit.
- Bundle component
| name | type | description |
|---|---|---|
| pf0 | Bool | page fault on the first half of instruction |
| pf1 | Bool | page fault on the second half of instruction |
| ae0 | Bool | access exception on the first half of instruction |
| ae1 | Bool | access exception on the second half of instruction |
| replay | Bool | replay this instruction due to instruction cache |
| btb_hit | Bool | indicated a predicted branch target (taken) |
| rvc | Bool | RVC instructions |
| inst | ExpandedInstruction | expanded instruction |
| raw | UInt | raw instruction |
Buffer for decoding RVC instructions This module is not fully implemented yet.
- I/O, type and parameters
| name | type | direction | description |
|---|---|---|---|
| p | Parameters | param | configuration |
| imem | DecoupledIO[FrontendResp] | I | fetched instructiond from instruction cache |
| kill | Bool | I | kill instructions from core pipe |
| pc | UInt | O | current PC of IF |
| btb_resp | BTBResp | O | update to BTB for RAS |
| inst | Vec[DecoupledIO[Instruction]] | O | instructions for core pipe |
Last updated: 08/07/2017
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