Testbench simulation of the built model has no output

[brtsfr]

Firstly, i managed to build a model into vivado project. Here are some info during the process.



Then i turned to develop my project in vivado. i tried to write a testbench and do simulation. With the help from #1059, i had a better understanding of the port signals and control logic. So i wrote a testbench with my understanding. It's attached here.
`module tb_pjt1;

// input signal of the DUT are reg, output signal are wire
reg   [15:0] conv2d_input_V_data_0_V_TDATA;     // input data
wire  [15:0] layer16_out_V_data_0_V_TDATA;      // output probability of class0    
wire  [15:0] layer16_out_V_data_1_V_TDATA;      // output probability of class1
reg   ap_clk;                                   // system clock
reg   ap_rst_n;                                 // reset low active
reg   conv2d_input_V_data_0_V_TVALID;           // valid indication of input data
wire  conv2d_input_V_data_0_V_TREADY;           // *** data are permitted to input ?
reg   ap_start;                                 // *** start of the logic, no need of manual reset ?
wire  layer16_out_V_data_0_V_TVALID;            // valid indication of output
reg   layer16_out_V_data_0_V_TREADY;            // *** ready to receive ouput, no need of manual reset ?
wire  layer16_out_V_data_1_V_TVALID;            // valid indication of output
reg   layer16_out_V_data_1_V_TREADY;            // *** ready to receive ouput, no need of manual reset ?
wire  ap_done;                                  // automatically reset when logic is finished
wire  ap_ready;                                 // automatically reset when data are readin
wire  ap_idle;                                  // ready to start again

parameter WIDTH = 13;  
parameter DEPTH = 64;
 
integer i, j;
integer file_r;
 
reg [WIDTH-1:0] data0 [DEPTH-1:0]; 
reg din_ok;

// initial reset
initial begin
    ap_clk   = 1'b0;
    ap_rst_n = 1'b0;
    conv2d_input_V_data_0_V_TVALID = 1'b0;
    ap_start = 1'b0;
    layer16_out_V_data_0_V_TREADY = 1'b0;
    layer16_out_V_data_1_V_TREADY = 1'b0;
    din_ok = 1'b0;
    #20
    ap_rst_n = 1'b1;                  // step 0: reset signal
end

// 125MHz clk
always #4 ap_clk = !ap_clk;           // step 0: sysclk

// load data
initial begin
    data0[0] = 13'b0000000000000; data0[1] = 13'b0000000000000; data0[2] = 13'b0000000000000; data0[3] = 13'b0000000000000; data0[4] = 13'b0000000000000;
    data0[5] = 13'b0000000000000; data0[6] = 13'b0000000000000; data0[7] = 13'b0000000000000; data0[8] = 13'b0000000000000; data0[9] = 13'b0000000000000;
    data0[10] = 13'b0000000000000; data0[11] = 13'b0000000000000; data0[12] = 13'b0000000000000; data0[13] = 13'b0000000000000; data0[14] = 13'b0000000000000;
    data0[15] = 13'b0000000000000; data0[16] = 13'b0000000000000; data0[17] = 13'b0000000000000; data0[18] = 13'b0000000000000; data0[19] = 13'b0000000000000;
    data0[20] = 13'b0000000000000; data0[21] = 13'b0000000000000; data0[22] = 13'b0000000000000; data0[23] = 13'b0000000000000; data0[24] = 13'b0000000000000;
    data0[25] = 13'b0000000000000; data0[26] = 13'b0000000000000; data0[27] = 13'b0000000000000; data0[28] = 13'b0000000000000; data0[29] = 13'b0000000000000;
    data0[30] = 13'b0000000000000; data0[31] = 13'b0000000000000; data0[32] = 13'b0000000000000; data0[33] = 13'b0000010110000; data0[34] = 13'b0000000000000;
    data0[35] = 13'b0000000000000; data0[36] = 13'b0000000000000; data0[37] = 13'b0000000000000; data0[38] = 13'b0000000000000; data0[39] = 13'b0000000000000;
    data0[40] = 13'b0000000100000; data0[41] = 13'b0000110100101; data0[42] = 13'b0000010010010; data0[43] = 13'b0000000000000; data0[44] = 13'b0000000000000;
    data0[45] = 13'b0000000000000; data0[46] = 13'b0000000000000; data0[47] = 13'b0000000000000; data0[48] = 13'b0000000000000; data0[49] = 13'b0000100001000;
    data0[50] = 13'b0000001010100; data0[51] = 13'b0000000000000; data0[52] = 13'b0000000000000; data0[53] = 13'b0000000000000; data0[54] = 13'b0000000000000;
    data0[55] = 13'b0000000000000; data0[56] = 13'b0000000000000; data0[57] = 13'b0000000000001; data0[58] = 13'b0000000000000; data0[59] = 13'b0000000000000;
    data0[60] = 13'b0000000000000; data0[61] = 13'b0000000000000; data0[62] = 13'b0000000000000; data0[63] = 13'b0000000000000;

    din_ok = 1'b1;
end

// FSM
parameter            IDLE   = 3'd0 ;
parameter            READY  = 3'd1 ;                        
parameter            INPUT  = 3'd2 ;                        
parameter            DONE   = 3'd3 ;                        

reg [2:0]            st_next ;
reg [2:0]            st_cur ;


always @(posedge ap_clk or negedge ap_rst_n) begin
    if (!ap_rst_n) begin
        st_cur   <= 'b0 ;
    end
    else begin
        st_cur   <= st_next ;
    end
end


always @(*) begin
    case(st_cur)
        IDLE:
            case (din_ok)
                1'b0:     st_next =  IDLE ;
                1'b1:     st_next = READY ;
                default:   st_next = IDLE ;
            endcase
        READY:
            st_next = INPUT ;

        INPUT:
            case (j==DEPTH)
                1'b0:     st_next = INPUT ;
                1'b1:     st_next =  DONE ;
                default:  st_next = INPUT ;
            endcase
        DONE:
            st_next = IDLE ;

        default:    st_next = IDLE ;
    endcase
end


always @(posedge ap_clk or negedge ap_rst_n) begin
    if (!ap_rst_n) begin
        j <= 1'b0;
        layer16_out_V_data_0_V_TREADY <= 1'b0;                  
        layer16_out_V_data_1_V_TREADY <= 1'b0;  
        ap_start <= 1'b0;  
        conv2d_input_V_data_0_V_TVALID <= 1'b0;              
    end
    else if (st_cur == IDLE) begin
        j <= 1'b0;
    end
    else if (st_cur == READY ) begin
        layer16_out_V_data_0_V_TREADY <= 1'b1;                  
        layer16_out_V_data_1_V_TREADY <= 1'b1;                  
    end
    //else if (st_cur == INPUT && conv2d_input_V_data_0_V_TREADY == 1'b1) begin
    else if (st_cur == INPUT) begin
        ap_start <= 1'b1;                                       // step 1: set signal
        conv2d_input_V_data_0_V_TDATA <= {3'b0, data0[j]};      // step 1：input data
        conv2d_input_V_data_0_V_TVALID <= 1'b1;                 // step 1: set valid
        j <= j + 1'b1;
        
    end
    else if (st_cur == DONE) begin
        //ap_start <= 1'b0;
        conv2d_input_V_data_0_V_TVALID <= 1'b0;                 // clear TVALID
        j <= 1'b0;
        din_ok <= 1'b0;                                         // make the state holds on IDLE
    end
    else begin
        j <= 1'b0;
        //layer16_out_V_data_0_V_TREADY <= 1'b0;                  
        //layer16_out_V_data_1_V_TREADY <= 1'b0;  
        //ap_start <= 1'b0;  
        conv2d_input_V_data_0_V_TVALID <= 1'b0;
    end
end

prj_1 prj_1_i(
    .conv2d_input_V_data_0_V_TDATA(conv2d_input_V_data_0_V_TDATA),
    .layer16_out_V_data_0_V_TDATA(layer16_out_V_data_0_V_TDATA),
    .layer16_out_V_data_1_V_TDATA(layer16_out_V_data_1_V_TDATA),
    .ap_clk(ap_clk),
    .ap_rst_n(ap_rst_n),
    .conv2d_input_V_data_0_V_TVALID(conv2d_input_V_data_0_V_TVALID),
    .conv2d_input_V_data_0_V_TREADY(conv2d_input_V_data_0_V_TREADY),
    .ap_start(ap_start),
    .layer16_out_V_data_0_V_TVALID(layer16_out_V_data_0_V_TVALID),
    .layer16_out_V_data_0_V_TREADY(layer16_out_V_data_0_V_TREADY),
    .layer16_out_V_data_1_V_TVALID(layer16_out_V_data_1_V_TVALID),
    .layer16_out_V_data_1_V_TREADY(layer16_out_V_data_1_V_TREADY),
    .ap_done(ap_done),
    .ap_ready(ap_ready),
    .ap_idle(ap_idle)  
);

endmodule`

During the simulation, i checked the start and end point of data transmission. i believe data are correctly readin, and testbench is running as expected. Here are screenshots.

Somehow the output are not observed. Maybe there are still some missing parts of the control logic or timing. Please have a look and give me some hints, thanks a lot!

[brtsfr]

hi,@gioregg, i read your post #1059 and understood that you are writting testbench. i am also trying to get some output with testbench. maybe we can discuss and help out. thanks.