DSP slice register usage

[franhervas99]

Hi everyone,
Is there a way of customizing the behavior of DSP slices inside the FPGA from the python script?
My point is that it should be necessary to say how to use the DSP resources inside the FPGA, for example saying to use them fully pipelined (to increase frequency) or viceversa.
Thank you in advance!
Fran.

[bo3z]

This is not exposed in Python as it is too low-level for most users. As a first step, you could modify the build_prj.tcl script (I guess you are using Vivado/ Vitis): https://github.com/fastmachinelearning/hls4ml/blob/main/hls4ml/templates/vivado/build_prj.tcl to add the corresponding flag during synthesis.

Future work might look into adding general support for synthesis and PnR flags that are exposed from the Python interface, but so far it hasn't been a priority. If you find a way to implement such a feauture, supporting arbitrary Vivado flags, that can be passed by the user, we would welcome a PR contribution.