From 55ec412183d2fb074d69ab9d45c3f2531b7157f4 Mon Sep 17 00:00:00 2001
From: Xeonacid <h.dwwwwww@gmail.com>
Date: Fri, 27 Dec 2024 05:41:44 +0100
Subject: [PATCH] upgpatch: rocm-opencl-runtime 6.2.4-1

---
 rocm-opencl-runtime/riscv64.patch             | 13 ++++--
 .../rocm-opencl-runtime-clr-riscv-fence.patch | 46 +++++++++++++++++++
 ...-opencl-runtime-clr-riscv-hard-float.patch | 12 +++++
 3 files changed, 66 insertions(+), 5 deletions(-)
 create mode 100644 rocm-opencl-runtime/rocm-opencl-runtime-clr-riscv-fence.patch
 create mode 100644 rocm-opencl-runtime/rocm-opencl-runtime-clr-riscv-hard-float.patch

diff --git a/rocm-opencl-runtime/riscv64.patch b/rocm-opencl-runtime/riscv64.patch
index 9a3dfc40a..424c0fafd 100644
--- a/rocm-opencl-runtime/riscv64.patch
+++ b/rocm-opencl-runtime/riscv64.patch
@@ -1,15 +1,18 @@
 diff --git PKGBUILD PKGBUILD
-index 5b66968..49a70da 100644
+index 9f649e8..64e2fa5 100644
 --- PKGBUILD
 +++ PKGBUILD
-@@ -41,3 +41,10 @@
+@@ -40,3 +40,13 @@
      echo '/opt/rocm/lib/libamdocl64.so' > 'amdocl64.icd'
      install -Dm644 'amdocl64.icd' "$pkgdir/etc/OpenCL/vendors/amdocl64.icd"
  }
 +
-+source+=("$pkgname-only-enable-SIMD-on-x86.patch::https://github.com/ROCm-Developer-Tools/clr/commit/4c3450cccd8f4064b1e011e6b84e7ca4567121a3.diff")
-+sha256sums+=('b20e8678851331093bf99d9d202b221f5ffd144e9ceb153728434e750df5349e')
++source+=("$pkgname-clr-riscv-hard-float.patch"
++         "$pkgname-clr-riscv-fence.patch")
++sha256sums+=('b8d9643df110fd016796fe5e3ffda0b13bfe6ba430304322684a691bc35b84ff'
++             '1ddd118ec6f2f285adca0bd2511d7c3cff8c9cbe66d84572228957f995e9525f')
 +
 +prepare() {
-+  patch -Np1 -d $_dirname -i ../$pkgname-only-enable-SIMD-on-x86.patch
++  patch -Np1 -d "$srcdir/$_dirname" -i "$srcdir/$pkgname-clr-riscv-hard-float.patch"
++  patch -Np1 -d "$srcdir/$_dirname" -i "$srcdir/$pkgname-clr-riscv-fence.patch"
 +}
diff --git a/rocm-opencl-runtime/rocm-opencl-runtime-clr-riscv-fence.patch b/rocm-opencl-runtime/rocm-opencl-runtime-clr-riscv-fence.patch
new file mode 100644
index 000000000..d09a7a0f6
--- /dev/null
+++ b/rocm-opencl-runtime/rocm-opencl-runtime-clr-riscv-fence.patch
@@ -0,0 +1,46 @@
+diff --git a/hipamd/src/hip_graph_internal.cpp b/hipamd/src/hip_graph_internal.cpp
+index ebcf4c91e..33a9ad898 100644
+--- a/hipamd/src/hip_graph_internal.cpp
++++ b/hipamd/src/hip_graph_internal.cpp
+@@ -443,9 +443,17 @@ hipError_t GraphExec::CaptureAQLPackets() {
+                  kernarg_pool_size_graph_ != 0) {
+         address dev_ptr = kernarg_pool_graph_ + kernarg_pool_size_graph_;
+         auto kSentinel = *reinterpret_cast<volatile unsigned char*>(dev_ptr - 1);
+-        _mm_sfence();
++#if defined(__x86_64__)
++          _mm_sfence();
++#elif defined(__riscv)
++          asm volatile("fence rw, rw");
++#endif
+         *(dev_ptr - 1) = kSentinel;
+-        _mm_mfence();
++#if defined(__x86_64__)
++          _mm_mfence();
++#elif defined(__riscv)
++          asm volatile("fence rw, rw");
++#endif
+         kSentinel = *reinterpret_cast<volatile unsigned char*>(dev_ptr - 1);
+       }
+     }
+diff --git a/rocclr/device/rocm/rocvirtual.cpp b/rocclr/device/rocm/rocvirtual.cpp
+index 169e81e65..2d8924de4 100644
+--- a/rocclr/device/rocm/rocvirtual.cpp
++++ b/rocclr/device/rocm/rocvirtual.cpp
+@@ -3247,9 +3247,17 @@ bool VirtualGPU::submitKernelInternal(const amd::NDRangeContainer& sizes,
+           auto kSentinel = *reinterpret_cast<volatile int*>(dev().info().hdpMemFlushCntl);
+         } else if (kernArgImpl == KernelArgImpl::DeviceKernelArgsReadback &&
+                    argSize != 0) {
++#if defined(__x86_64__)
+           _mm_sfence();
++#elif defined(__riscv)
++          asm volatile("fence rw, rw");
++#endif
+           *(argBuffer + argSize - 1) = *(parameters + argSize - 1);
++#if defined(__x86_64__)
+           _mm_mfence();
++#elif defined(__riscv)
++          asm volatile("fence rw, rw");
++#endif
+           auto kSentinel = *reinterpret_cast<volatile unsigned char*>(
+               argBuffer + argSize - 1);
+         }
diff --git a/rocm-opencl-runtime/rocm-opencl-runtime-clr-riscv-hard-float.patch b/rocm-opencl-runtime/rocm-opencl-runtime-clr-riscv-hard-float.patch
new file mode 100644
index 000000000..ee3b1827a
--- /dev/null
+++ b/rocm-opencl-runtime/rocm-opencl-runtime-clr-riscv-hard-float.patch
@@ -0,0 +1,12 @@
+diff '--color=auto' -Naur clr-rocm-6.0.0.orig/hipamd/src/hiprtc/CMakeLists.txt clr-rocm-6.0.0/hipamd/src/hiprtc/CMakeLists.txt
+--- clr-rocm-6.0.0.orig/hipamd/src/hiprtc/CMakeLists.txt	2024-02-16 10:53:57.198846626 -0500
++++ clr-rocm-6.0.0/hipamd/src/hiprtc/CMakeLists.txt	2024-02-16 10:56:30.945780069 -0500
+@@ -171,7 +171,7 @@
+   DEPENDS clang ${HIPRTC_GEN_HEADER})
+ add_custom_command(
+   OUTPUT ${HIPRTC_GEN_OBJ}
+-  COMMAND $<TARGET_FILE:llvm-mc> -o ${HIPRTC_GEN_OBJ} ${HIPRTC_GEN_MCIN} --filetype=obj
++  COMMAND $<TARGET_FILE:llvm-mc> -o ${HIPRTC_GEN_OBJ} ${HIPRTC_GEN_MCIN} --filetype=obj -mattr=+m,a,f,d,c
+   DEPENDS llvm-mc ${HIPRTC_GEN_PREPROCESSED} ${HIPRTC_GEN_MCIN})
+ 
+ # Create hiprtc-builtins library.