From 7af46fba923b82e9783bd90835ac22ed3dbef4c8 Mon Sep 17 00:00:00 2001 From: Anders Olofsson Date: Sun, 1 Nov 2015 21:06:34 +0100 Subject: [PATCH] ARMv7: Add pages with system registers --- README | 3 +- armv7.tex | 523 +++++++++++++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 502 insertions(+), 24 deletions(-) diff --git a/README b/README index 20e7993..29e9ef0 100644 --- a/README +++ b/README @@ -40,7 +40,8 @@ Note: I was unable to find the execution time for SETALC instruction ARM v7 ------ Instruction sets of ARM, Thumb and Thumb2 including version information -for ARM versions 6, 6T, 6k and 7. +for ARM versions 6, 6T, 6k and 7. Also includes extra pages with system +registers both for ARMv7-A/R and ARMv7-M. Floating point and coprocessor instructions are not included diff --git a/armv7.tex b/armv7.tex index faaa4ad..933c373 100644 --- a/armv7.tex +++ b/armv7.tex @@ -14,21 +14,23 @@ \usepackage[a4paper, landscape, margin=.1in]{geometry} \usepackage{amssymb} \usepackage{verbatim} +\usepackage{ulem} \def\sheetheaderfont{\bfseries} \def\sheettablefont{\footnotesize\sffamily} \def\sheetheadercolor{black!10} \def\sheetrowcolor{black!5} -\newcolumntype{N}{>{\raggedleft\arraybackslash}m{1.8em}} +\newcolumntype{N}{>{\raggedleft\arraybackslash}m{1.7em}} \def\tabcolsep{2pt} \def\arraystretch{1.3} \defsheet{asmtable}{4}{|m{4.6em} m{6.7em}|X|N|} \defsheet{table-lX}{2}{|l X|} \defsheet{table-lXN}{3}{|l|X|N|} \defsheet{table-llX}{3}{|l l X|} +\defsheet{table-llXr}{4}{|l l X r|} -\pagefooter{ARMv7 version 4 page \thepage} +\pagefooter{ARMv7 version 5 page \thepage} \begin{document} \begin{multicols}{3} @@ -39,7 +41,7 @@ \end{center} % \begin{asmtable}{Arithmetic Instructions} -ADC\{S\} & rx, ry, op2 & rx = ry $+$ op2 $+$ C & \\ +ADC\{S\} & rx, ry, op2 & rx = ry $+$ op2 $+$ C & \\ ADD\{S\} & rx, ry, op2 & rx = ry $+$ op2 & \\ ADDW & rx, ry, \#i$^{ }_{12}$ & rx = ry $+$ i$^{\emptyset}_{ }$ & T \\ ADR & rx, $\pm$rel$^{ }_{12}$ & rx = PC $\pm$ rel & \\ @@ -50,9 +52,9 @@ QDSUB & rx, ry, rz & rx = SATS(ry $-$ SATS(2$\times$rz, 32), 32) & D \\ QSUB & rx, ry, rz & rx = SATS(ry $-$ rz, 32) & D \\ RSB\{S\} & rx, ry, op2 & rx = op2 $-$ ry & \\ -RSC\{S\} & rx, ry, op2 & rx = op2 $-$ (ry $+$ C) & A \\ -SBC\{S\} & rx, ry, op2 & rx = ry $-$ (op2 $+$ C) & \\ -SDIV & rx, ry, rz & rx = ry $\sdiv$ rz & 7 \\ +RSC\{S\} & rx, ry, op2 & rx = op2 $-$ (ry $+$ C) & A \\ +SBC\{S\} & rx, ry, op2 & rx = ry $-$ (op2 $+$ C) & \\ +SDIV & rx, ry, rz & rx = ry $\sdiv$ rz & 7 \\ SSAT & rx, \#j$^{ }_{5}$, ry\{slr\} & rx = SATS(ry $\lsl\asr$ sh, j)$^{\pm}_{ }$ & 6 \\ SSAT16 & rx, \#j$^{ }_{4}$, ry & rx = SATS(ry$^{\pm}_{H1}$, j)$^{\pm}_{ }$:SATS(ry$^{\pm}_{H0}$, j)$^{\pm}_{ }$ & 6,D \\ SUB\{S\} & rx, ry, op2 & rx = ry $-$ op2 & \\ @@ -115,7 +117,7 @@ \begin{asmtable}{Branch and Jump Instructions} B & rel$^{ }_{26}$ & PC = PC $+$ rel$^{\pm}_{25:2}$:0$^{ }_{1:0}$ & A \\ B & rel$^{ }_{25}$ & PC = PC $+$ rel$^{\pm}_{24:1}$:0 & T \\ -Bcc & rel$^{ }_{21}$ & if(cc) PC = PC $+$ rel$^{\pm}_{20:1}$:0 & I \\ +Bcc & rel$^{ }_{21}$ & if(cc) PC = PC $+$ rel$^{\pm}_{20:1}$:0 & I \\ BKPT & \#i$^{ }_{16}$ & BreakPoint(i) & I \\ BL & rel$^{ }_{26}$ & LR=PC$^{ }_{31:1}$:0; PC$+$=rel$^{\pm}_{25:2}$:0$^{ }_{1:0}$ & A \\ BL & rel$^{ }_{25}$ & LR=PC$^{ }_{31:1}$:1; PC$+$=rel$^{\pm}_{24:1}$:0 & T \\ @@ -198,12 +200,12 @@ SMUaD & rx, ry, rz & rx = ry$^{\pm}_{H0}$ $\smul$ rz$^{\pm}_{H0}$ $\pm$ ry$^{\pm}_{H1}$ $\smul$ rz$^{\pm}_{H1}$ & 6,D \\ SMUaDX & rx, ry, rz & rx = ry$^{\pm}_{H0}$ $\smul$ rz$^{\pm}_{H1}$ $\pm$ ry$^{\pm}_{H1}$ $\smul$ rz$^{\pm}_{H0}$ & D \\ SMULxy & rx, ry, rz & rx = ry$^{\pm}_{Hx}$ $\smul$ rz$^{\pm}_{Hy}$ & D \\ -SMULL & rx, ry, rz, rw & ry:rx = rz $\smul$ rw & \\ -SMULL\{S\} & rx, ry, rz, rw & ry:rx = rz $\smul$ rw & A \\ +SMULL & rx, ry, rz, rw & ry:rx = rz $\smul$ rw & \\ +SMULL\{S\} & rx, ry, rz, rw & ry:rx = rz $\smul$ rw & A \\ SMULWy & rx, ry, rz & rx = (ry $\smul$ rz$^{\pm}_{Hy}$)$^{ }_{47:16}$ & D \\ UMAAL & rx, ry, rz, rw & ry:rx = ry $+$ rx $+$ rz $\umul$ rw & D \\ UMLAL & rx, ry, rz, rw & ry:rx $+$= rz $\umul$ rw & \\ -UMULL & rx, ry, rz, rw & ry:rx = rz $\umul$ rw & \\ +UMULL & rx, ry, rz, rw & ry:rx = rz $\umul$ rw & \\ \end{asmtable} % \begin{asmtable}{Parallel Instructions} @@ -327,19 +329,6 @@ $\smul$ $\sdiv$ $\asr$ & Operation is signed \\ \end{table-lX} % -\begin{table-lX}{Notes} -6 & Introduced in ARMv6 \\ -6k & Introduced in ARMv6k \\ -6t & Introduced in ARMv6T2 \\ -7 & Introduced in ARMv7 \\ -A & Only available in ARM mode \\ -D & Not available on ARMv7-M without DSP extension \\ -H & Thumb1 instruction can use high registers \\ -I & Can't be conditional \\ -S & Thumb16 instruction must have S suffix unless in IT block \\ -T & Only available in Thumb mode \\ -\end{table-lX} -% \begin{table-llX}{General Registers} R0-R3 & & Arguments and return values (useable by Thumb16) \\ R4-R7 & & General purpose (must be preserved, useable by Thumb16) \\ @@ -379,6 +368,16 @@ OSHST & Outer sharable, Write only \\ \end{table-lX} % +\begin{table-lX}{Notes for Instruction Set} +6,6k,6t,7 & Introduced in ARMv6, ARMv6k, ARMv6T2, or ARMv7 \\ +A & Only available in ARM mode \\ +D & Not available on ARM-M without DSP extension \\ +H & Thumb16 instruction can use high registers \\ +I & Can't be conditional \\ +S & Thumb16 instruction must have S suffix unless in IT block \\ +T & Only available in Thumb mode \\ +\end{table-lX} +% \begin{asmtable}{Thumb16 Bitwise and Move Instructions} AND\{S\} & rx, ry & rx = rx \& ry & S \\ ASR\{S\} & rx, ry, \#j$^{ }_{5}$ & rx = ry $\asr$ j & S \\ @@ -474,5 +473,483 @@ STRH & rx, [ry, rz] & [ry $+$ rz]$^{ }_{16}$ = rx$^{ }_{15:0}$ & \\ \end{asmtable} % +\begin{center} +{\Large\bfseries ARMv7-A \& ARMv7-R System} +\end{center} +% +\begin{table-llXr}{Current Program Status Register (CPSR)} +M & 0x0000001f & Processor Operating Mode & \\ +T & 0x00000020 & Instruction set (JT: 00=ARM, 01=Thumb) & \\ +F & 0x00000040 & FIQ exception masked & \\ +I & 0x00000080 & IRQ exception masked & \\ +A & 0x00000100 & Asynchronous abort masked & 6 \\ +E & 0x00000200 & Big-endian operation & 6 \\ +IT & 0x0600fc00 & IT state bits & 6t\\ +GE\{3..0\} & 0x000f0000 & SIMD Greater than or equal to & 6 \\ +J & 0x01000000 & Instr set (JT: 10=Jazelle, 11=ThumbEE) & 6 \\ +Q & 0x08000000 & Cumulative saturation bit & \\ +V & 0x10000000 & Overflow condition flag & \\ +C & 0x20000000 & Carry condition flag & \\ +Z & 0x40000000 & Zero condition flag & \\ +N & 0x80000000 & Negative condition flag & \\ +\end{table-llXr} +% +\begin{table-llXr}{Processor Operating Modes} +usr & 0x10 & User & \\ +fiq & 0x11 & FIQ & \\ +irq & 0x12 & IRQ & \\ +svc & 0x13 & Supervisor & \\ +mon & 0x16 & Monitor (Secure only) & S\\ +abt & 0x17 & Abort & \\ +hyp & 0x1a & Hypervisor (Non-secure only) & V \\ +und & 0x1b & Undefined & \\ +sys & 0x1f & System & \\ +\end{table-llXr} +% +\begin{table-lX}{Vectors} +0x00 & Reset \\ +0x04 & Undefined instruction \\ +0x08 & Supervisor Call / Secure Monitor Call / Hypervisor Call \\ +0x0c & Prefetch abort \\ +0x10 & Data abort \\ +0x14 & Hyp trap \\ +0x18 & IRQ interrupt \\ +0x1c & FIQ interrupt \\ +\end{table-lX} +% +\begin{table-lX}{Notes for System Registers and Tables} +6,6k,6t,7 & Introduced in ARMv6, ARMv6k, ARMv6T2, or ARMv7 \\ +%\sout{7} & Removed in ARMv7 \\ +A & Only present on ARM-A \\ +B & Banked between secure and non-secure usage \\ +R & Only present on ARM-R \\ +S & Only present with security extensions (Implies 6k,A) \\ +V & Only present with virtualization extensions (Implies 7,A) \\ +\end{table-lX} +% +\begin{table-llXr}{System Control Register (SCTLR)} +M & 0x00000001 & MMU enabled & B \\ +A & 0x00000002 & Alignment check enabled & B \\ +C & 0x00000004 & Data and unified caches enabled & B \\ +%W & 0x00000008 & Write buffer enabled & \sout{7} \\ +CP15BEN & 0x00000020 & CP15 barrier enable & 7,B \\ +%B & 0x00000080 & Legacy Big endian BE-32 format & \sout{7} \\ +%S & 0x00000100 & System protection & \sout{7} \\ +%R & 0x00000200 & ROM protection & \sout{7} \\ +SW & 0x00000400 & Enable SWP and SWPB instructions & 6,B \\ +Z & 0x00000800 & Program flow prediction enabled & B \\ +I & 0x00001000 & Instruction cache enabled & B \\ +V & 0x00002000 & High exception vectors & B \\ +RR & 0x00004000 & Round Robin select (Non-Secure RO) & \\ +%L4 & 0x00008000 & Inhibit thumb interworking & \sout{7} \\ +HA & 0x00020000 & Hardware access flag enable & B,S \\ +BR & 0x00020000 & Background region enable & 7,R \\ +WXN & 0x00080000 & Write force to XN & V \\ +DZ & 0x00080000 & Divide by zero causes undefined instruction & 7,R \\ +UWXN & 0x00100000 & Unprivileged write forced to XN for PL1 & V \\ +FI & 0x00200000 & Fast Interrupts (Non-Secure RO) & 6 \\ +%U & 0x00400000 & Unaligned access support & 6,\sout{7} \\ +%XP & 0x00800000 & Select virtual memory support model & 6,\sout{7} \\ +VE & 0x01000000 & Interrupt Vectors Enable & 6,B \\ +EE & 0x02000000 & Exception Endianess & 6,B \\ +%L2 & 0x04000000 & Level 2 cache support & 6,\sout{7} \\ +NMFI & 0x08000000 & Non-maskable FIQ support (RO) & 6 \\ +TRE & 0x10000000 & TEX remap functionality enabled & B,S \\ +AFE & 0x20000000 & Access flag enable & B,S \\ +TE & 0x40000000 & Thumb exception enable & 6t,B \\ +IE & 0x80000000 & Big-endian byte order in instructions & 7,R \\ +\end{table-llXr} +% +\begin{table-llX}{Coprocessor Access Control Register (CPACR)} +CP\{0..13\} & 3$\lsl$(2$\umul$\{0..13\}) & CP\{0..13\} access (00=denied, 01=privileged mode only, 11=privileged or user mode) \\ +TRCDIS & 0x10000000 & Disable CP14 access to trace registers \\ +D32DIS & 0x40000000 & Disable use of D16-D31 registers \\ +ASEDIS & 0x80000000 & Disable advanced SIMD functionality \\ +\end{table-llX} +% +\begin{table-llXr}{CP15 System Control Registers} +SCTLR & c1,0,c0,0 & System Control Register & \\ +ACTLR & c1,0,c0,1 & Auxiliary Control Register & 6,B \\ +CPACR & c1,0,c0,2 & Coprocessor Access Control Register & 6 \\ +SCR & c1,0,c1,0 & Secure Configuration (Secure only) & S \\ +SDER & c1,0,c1,1 & Secure Debug Enable (Secure only) & S \\ +NSACR & c1,0,c1,2 & Non-Secure Access Control (Non-Secure RO) & S \\ +\end{table-llXr} +% +\begin{table-llXr}{CP15 Security Extension Registers (ARM-A Only)} +VBAR & c12,0,c0,0 & Vector Base Register & B \\ +MVBAR & c12,0,c0,1 & Monitor Vector Base Address (Secure only) & \\ +ISR & c12,0,c1,0 & Interrupt Status Register (RO) & \\ +\end{table-llXr} +% +\begin{table-llXr}{Secure Configuration Register (SCR)} +NS & 0x001 & System state is non-secure unless in Monitor mode & \\ +IRQ & 0x002 & IRQs taken to Monitor mode & \\ +FIQ & 0x004 & FIQs taken to Monitor mode & \\ +EA & 0x008 & External aborts taken to Monitor mode & \\ +FW & 0x010 & CPSR.F writeable in non-secure state & \\ +AW & 0x020 & CPSR.A writeable in non-secure state & \\ +nET & 0x040 & Disable early termination & \\ +SCD & 0x080 & Secure monitor call disable & V \\ +HCE & 0x100 & Hyp Call enable & V \\ +SIF & 0x200 & Secure instruction fetch & V \\ +\end{table-llXr} +% +\begin{table-llX}{Non-Secure Access Control Register (NSACR)} +CP\{0..13\} & 1 $\lsl$ \{0..13\} & CP\{0..13\} can be accessed in non-secure state \\ +NSD32DIS & 0x00004000 & CPACR.D32DIS is fixed 1 in non-secure state \\ +NSASEDIS & 0x00008000 & CPACR.ASEDIS is fixed 1 in non-secure state \\ +RFR & 0x00080000 & Reserve FIQ mode for non-secure \\ +NSTRCDIS & 0x00100000 & Disable non-secure access to CP14 trace regs \\ +\end{table-llX} +% +\begin{table-llXr}{CP15 Memory System Fault Registers} +DFSR & c5,0,c0,0 & Data Fault Status Register & B \\ +IFSR & c5,0,c0,1 & Instruction Fault Status Register & 6,B \\ +ADFSR & c5,0,c1,0 & Auxiliary DFSR & 7,B \\ +AIFSR & c5,0,c1,1 & Auxiliary IFSR & 7,B \\ +DFAR & c6,0,c0,0 & Data Fault Address Register & B \\ +IFAR & c6,0,c0,2 & Instruction Fault Address Register & 6,B \\ +DRBAR & c6,0,c1,0 & Data Region Base Address Register & R \\ +IRBAR & c6,0,c1,1 & Instruction Region Base Address Register & R \\ +DRSR & c6,0,c1,2 & Data Region Size and Enable Register & R \\ +IRSR & c6,0,c1,3 & Instruction Region Size and Enable Register & R \\ +DRACR & c6,0,c1,4 & Data Region Access Control Register & R \\ +IRACR & c6,0,c1,5 & Instruction Region Access Control Register & R \\ +RGNR & c6,0,c2,0 & MPU Region Number Register & R \\ +\end{table-llXr} +% +\begin{table-llXr}{CP15 Generic Timer Registers} +CNTFRQ & c14,0,c0,0 & Counter Frequency Reg (Non-Secure RO) & 7 \\ +CNTKCTL & c14,0,c1,0 & Timer PL1 Control Register & 7 \\ +CNTP\_TVAL & c14,0,c2,0 & PL1 Physical TimerValue Register & 7,B \\ +CNTP\_CTL & c14,0,c2,1 & PL1 Physical Timer Control Register & 7,B \\ +CNTV\_TVAL & c14,0,c3,0 & Virtual TimerValue Register & 7 \\ +CNTV\_CTL & c14,0,c3,1 & Virtual TimerControl Register & 7 \\ +CNTPCT & c14,0 & Physical Count Register (RO) & 7 \\ +CNTVCT & c14,1 & Virtual Count Register (RO) & 7 \\ +CNTP\_CVAL & c14,2 & PL1 Physical Timer CompareValue Register & 7,B \\ +CNTV\_CVAL & c14,3 & Virtual Timer CompareValue Register & 7 \\ +\end{table-llXr} +% +\begin{table-llXr}{CP15 ID Registers (Read-Only)} +MIDR & c0,0,c0,0 & Main ID Register & \\ +CTR & c0,0,c0,1 & Cache Type Register & \\ +TCMTR & c0,0,c0,2 & TCM Type Register & \\ +TLBTR & c0,0,c0,3 & TLB Type Register & A \\ +MPUIR & c0,0,c0,4 & MPU Type Register & R \\ +MPIDR & c0,0,c0,5 & Multiprocessor Affinity Register & \\ +REVIDR & c0,0,c0,6 & Revision ID & \\ +ID\_PFR\{0..1\} & c0,0,c1,\{0..1\} & Processor Feature Registers & 6 \\ +ID\_DFR0 & c0,0,c1,2 & Debug Feature Register 0 & 6 \\ +ID\_AFR0 & c0,0,c1,3 & Auxiliary Feature Register 0 & 6 \\ +ID\_MMFR\{0..3\} & c0,0,c1,\{4..7\} & Memory Model Feature Regs & 6 \\ +ID\_ISAR\{0..5\} & c0,0,c2,\{0..5\} & Instruction Set Attribute Regs & 6 \\ +CCSIDR & c0,1,c0,0 & Cache Size ID Register & 7 \\ +CLIDR & c0,1,c0,1 & Cache Level ID Register & 7 \\ +AIDR & c0,1,c0,7 & Auxiliary ID Register & 7 \\ +CSSELR & c0,2,c0,0 & Cache Size Selection Register (RW) & 7,B \\ +\end{table-llXr} +% +\begin{table-llXr}{CP15 Cache Maintenance Registers (Write Only)} +CP15WFI & c7,0,c0,4 & Wait for interrupt operation & \\ +ICIALLUIS & c7,0,c1,0 & Inv all instr caches to PoU Inner Sharable & 7 \\ +BPIALLIS & c7,0,c1,6 & Inv all branche predictors Inner Sharable & 7 \\ +PAR & c7,0,c4,0 & Physical Address Register (RW) & 7,A,B \\ +ICIALLU & c7,0,c5,0 & Invalidate all instruction caches to PoU & \\ +ICIMVAU & c7,0,c5,1 & Inv instruction caches by MVA to PoU & \\ +% & c7,0,c5,2 & Invalidate instruction cache line by set/way & \sout{7} \\ +CP15ISB & c7,0,c5,4 & Instruction Sync Barrier operation & 7 \\ +BPIALL & c7,0,c5,6 & Invalidate all branch predictors & \\ +BPIMVA & c7,0,c5,7 & Invalidate MVA from branch predictors & \\ +% & c7,0,c6,0 & Invalidate data cache & \sout{7} \\ +DCIMVAC & c7,0,c6,1 & Inv data cache line my MVA to PoC & \\ +DCISW & c7,0,c6,2 & Invalidate data cache line by set/way & \\ +% & c7,0,c7,0 & Invalidate unified cache & \sout{7} \\ +% & c7,0,c7,1 & Invalidate unified cache line by MVA & \sout{7} \\ +% & c7,0,c7,2 & Invalidate unified cache line by set/way & \sout{7} \\ +ATS1CPR & c7,0,c8,0 & PL1 read translation (Current state) & 7,A \\ +ATS1CPW & c7,0,c8,1 & PL1 write translation (Current state) & 7,A \\ +ATS1CUR & c7,0,c8,2 & Unpriv read translation (Current state) & 7,A \\ +ATS1CUW & c7,0,c8,3 & Unpriv write translation (Current state) & 7,A \\ +ATS12NSOPR & c7,0,c8,4 & PL1 read translation (NS state) & 7,S \\ +ATS12NSOPW & c7,0,c8,5 & PL1 write translation (NS state) & 7,S \\ +ATS12NSOUR & c7,0,c8,6 & Unprivileged read translation (NS state) & 7,S \\ +ATS12NSOUW & c7,0,c8,7 & Unprivileged write translation (NS state) & 7,S \\ +% & c7,0,c10,0 & Clean data cache & 6,\sout{7} \\ +DCCMVAC & c7,0,c10,1 & Clean data cache line my MVA to PoC & \\ +DCCSW & c7,0,c10,2 & Clean data cache line by set/way & \\ +% & c7,0,c10,3 & Test and clean data cache & \sout{7} \\ +CP15DSB & c7,0,c10,4 & Data Synchronization Barrier operation & 7 \\ +CP15DMB & c7,0,c10,5 & Data Memory Barrier operation & 7 \\ +% & c7,0,c10,6 & Cache Dirty Status Register & 6,\sout{7} \\ +% & c7,0,c11,0 & Clean entire unified cache & \sout{7} \\ +DCCMVAU & c7,0,c11,1 & Clean data cache line by MVA to PoU & \\ +% & c7,0,c11,2 & Clean unified cache line by set/way & \sout{7} \\ +% & c7,0,c13,1 & Prefetch instruction cache line by MVA & \sout{7} \\ +% & c7,0,c14,0 & Clean and invalidate data cache & 6,\sout{7} \\ +DCCIMVAC & c7,0,c14,1 & Clean and inv data c-line by MVA to PoC & \\ +DCCISW & c7,0,c14,2 & Clean and inv data c-line by set/way & \\ +% & c7,0,c14,3 & Test and clean and invalidate data cache & \sout{7} \\ +% & c7,0,c15,1 & Clean and invalidate unified cache line by MVA & \sout{7} \\ +% & c7,0,c15,2 & Clean and invalidate unified cache line by set/way & \sout{7} \\ +PAR & c7,0 & Physical Address Register (RW) & 7,A,B \\ +\end{table-llXr} +% +\begin{table-llXr}{CP15 Memory Protection and Control Registers (ARM-A only)} +TTBR0 & c2,0,c0,0 & Translation Table Base 0 & B \\ +TTBR1 & c2,0,c0,1 & Translation Table Base 1 & 6,B \\ +TTBCR & c2,0,c0,2 & Translation Table Base Control & 6,B \\ +TTBR0 & c2,0 & Translation Table Base 0 (LPAE only) & 7,B \\ +TTBR1 & c2,1 & Translation Table Base 1 (LPAE only) & 7,B \\ +DACR & c3,0,c0,0 & Domain Access Contorl Register & B \\ +\end{table-llXr} +% +\begin{table-llXr}{CP15 TLB Maintenance Operation Regs (Write Only, ARM-A Only)} +TLBIALLIS & c8,0,c3,0 & Invalidate entire TLB IS & 7 \\ +TLBIMVAIS & c8,0,c3,1 & Invalidate unified TLB by MVA and ASID IS & 7 \\ +TLBIASIDIS & c8,0,c3,2 & Invalidate unified TLB by ASID match IS & 7 \\ +TLBIMVAAIS & c8,0,c3,3 & Inv unified TLB entry by MVA all ASID IS & 7 \\ +ITLIALL & c8,0,c5,0 & Invalidate instruction TLB & \\ +ITLIMVA & c8,0,c5,1 & Inv instr TLB entry by MVA all ASID IS & \\ +ITLIASID & c8,0,c5,2 & Invalidate instruction TLB by ASID match & 6 \\ +DTLBIALL & c8,0,c6,0 & Invalidate data TLB & \\ +DTLBIMVA & c8,0,c6,1 & Invalidate data TLB entry by MVA and ASID & \\ +DTLBIASID & c8,0,c6,2 & Invalidate data TLB by ASID match & 6 \\ +TLBIALL & c8,0,c7,0 & Invalidate unified TLB & \\ +TLBIMVA & c8,0,c7,1 & Inv unified TLB entry by MVA and ASID & \\ +TLBIASID & c8,0,c7,2 & Invalidate unified TLB by ASID match & 6 \\ +TLBIMVAA & c8,0,c7,3 & Inval unified TLB entries by MVA all ASID & 6 \\ +\end{table-llXr} +% +\begin{table-llXr}{CP15 Performance Monitor Registers (ARM-R Only)} +PMCR & c9,0,c12,0 & PM Control Register & \\ +PMCNTENSET & c9,0,c12,1 & PM Count Enable Set Register & \\ +PMCNTENCLR & c9,0,c12,2 & PM Count Enable Clear Register & \\ +PMOVSR & c9,0,c12,3 & PM Overflow Flag Status Register & \\ +PMSWINC & c9,0,c12,4 & PM Software Increment Register & \\ +PMSELR & c9,0,c12,5 & PM Event Counter Selection Register & \\ +PMCEID0 & c9,0,c12,6 & PM Common Event Identification Register 0 & \\ +PMCEID1 & c9,0,c12,7 & PM Common Event Identification Register 1 & \\ +PMCCNTR & c9,0,c13,0 & PM Cycle Count Register & \\ +PMXEVTYPER & c9,0,c13,1 & PM Event Type Select Register & \\ +PMXEVCNTR & c9,0,c13,2 & PM Event Count Register & \\ +PMUSERENR & c9,0,c14,0 & PM User Enable Register & \\ +PMINTENSET & c9,0,c14,1 & PM Interrupt Enable Set Register & \\ +PMINTENCLR & c9,0,c14,2 & PM Interrupt Enable Clear Register & \\ +\end{table-llXr} +% +\begin{table-llXr}{CP15 Memory Mapping Registers (ARM-A Only)} +PRRR & c10,0,c2,0 & Primary Region Remap Register & 6,B \\ +NMRR & c10,0,c2,1 & Normal Memory Remap Register & 6,B \\ +AMAIR0 & c10,0,c3,0 & Aux Memory Attribute Indirection Reg 0 & 7 \\ +AMAIR1 & c10,0,c3,1 & Aux Memory Attribute Indirection Reg 1 & 7 \\ +\end{table-llXr} +% +\begin{table-llXr}{CP15 Process, Context, and Thread ID Registers} +FCSEIDR & c13,0,c0,0 & FSCE PID Register & A,B \\ +CONTEXIDR & c13,0,c0,1 & Context ID Register & 6,B \\ +TPIDRURW & c13,0,c0,2 & User Read/Write Thread ID & 6,B \\ +TPIDRURO & c13,0,c0,3 & User Read-only Thread ID & 6,B \\ +TPIDRPRW & c13,0,c0,4 & PL1 only Thread ID & 6,B \\ +\end{table-llXr} +% +\begin{table-llX}{CP15 Virtualization Extension Registers (ARM-A Only)} +VPIDR & c0,4,c0,0 & Virtualization Processor ID Register \\ +VMPIDR & c0,4,c0,5 & Virtualization Multiproc ID Register \\ +HSCTLR & c1,4,c0,0 & Hyp System Control Register \\ +HACTLR & c1,4,c0,1 & Hyp Auxiliary Control Register \\ +HCR & c1,4,c1,0 & Hyp Configuration Register \\ +HDCR & c1,4,c1,1 & Hyp Debug Configuration Register \\ +HCPTR & c1,4,c1,2 & Hyp Coprocessor Trap Register \\ +HSTR & c1,4,c1,3 & Hyp System Trap Register \\ +HACR & c1,4,c1,7 & Hyp Auxiliary Configuration Register \\ +HTCR & c2,4,c0,2 & Hyp Translation Control Register \\ +VTCR & c2,4,c1,2 & Virtualization Translation Control Reg \\ +HTTBR & c2,4 & Hyp Translation Table Base Reg \\ +VTTBR & c2,6 & Virt Translation Table Base Reg \\ +HADFSR & c5,4,c1,0 & Hyp Auxiliary DFSR \\ +HAIFSR & c5,4,c1,1 & Hyp Auxiliary IFSR \\ +HSR & c5,4,c2,0 & Hyp Syndrome Register \\ +HDFAR & c6,4,c0,0 & Hyp Data Fault Address Register \\ +HIFAR & c6,4,c0,2 & Hyp Instruction Fault Address Register \\ +HPFAR & c6,4,c0,4 & Hyp IPA Fault Address Register \\ +ATS1HR & c7,4,c8,0 & Addr Tran Stage 1 Hyp mode Read (WO) \\ +ATS1HW & c7,4,c8,1 & Addr Tran Stage 1 Hyp mode Write (WO) \\ +TLBIALLHIS & c8,4,c3,0 & Inv entry hyp unif TLB IS (WO) \\ +TLBIMVAHIS & c8,4,c3,1 & Inv hyp unif TLB entry by MVA IS (WO) \\ +TLBIALLNSNHIS & c8,4,c3,4 & Inv non-sec/hyp uni TLB IS (WO) \\ +TLBIALLH & c8,4,c7,0 & Inv hyp unified (WO) \\ +TLBIMVAH & c8,4,c7,1 & Inv hyp unif TLB by MVA (WO) \\ +TLBIALLNSNH & c8,4,c7,4 & Inv non-sec/hyp unif TLB (WO) \\ +HMAIR0 & c10,4,c2,0 & Hyp Mem Attribute Indirection Reg 0 \\ +HMAIR1 & c10,4,c2,1 & Hyp Mem Attribute Indirection Reg 1 \\ +HAMAIR0 & c10,4,c3,0 & Hyp Aux Mem Attr Indirection Reg 0 \\ +HAMAIR1 & c10,4,c3,1 & Hyp Aux Mem Attr Indirection Reg 1 \\ +HVBAR & c12,4,c0,0 & Hyp Vector Base Address Register \\ +HTPIDR & c13,4,c0,2 & Hyp Read/Write Thread ID \\ +CNTHCTL & c14,4,c1,0 & Timer PL2 Control Register \\ +CNTHP\_TVAL & c14,4,c2,0 & PL2 Physical TimerValue Register \\ +CNTHP\_CTL & c14,4,c2,1 & PL2 Physical Timer Control Register \\ +CNTVOFF & c14,4 & Virtual Offset Register \\ +CNTHP\_CVAL & c14,6 & PL2 Physical Timer CompareValue Register \\ +\end{table-llX} +% +\begin{center} +{\Large\bfseries ARMv7-M System} +\end{center} +% +\begin{table-lX}{Special Registers} +\{I\}\{E\}\{A\}PSR & Program Status Registers \\ +XPSR & Alias for IEAPSR \\ +MSP & Main Stack Pointer \\ +PSP & Process Stack Pointer \\ +PRIMASK & Exceptions Mask Register \\ +BASEPRI & Base Priority Register \\ +BASEPRI\_MAX & Alias for BASEPRI that ignores writes of lower value \\ +FAULTMASK & Raise exception priority to HardFloat \\ +CONTROL & Special-Purpose Control Register \\ +\end{table-lX} +% +\begin{table-llX}{Program Status Register (xPSR)} + & 0x000001ff & Exception number (RO) \\ +IT & 0x0600fc00 & IT state bits \\ +GE\{3..0\} & 0x000f0000 & SIMD Greater than or equal to (DSP extension only) \\ +Q & 0x08000000 & Cumulative saturation bit \\ +V & 0x10000000 & Overflow condition flag \\ +C & 0x20000000 & Carry condition flag \\ +Z & 0x40000000 & Zero condition flag \\ +N & 0x80000000 & Negative condition flag \\ +\end{table-llX} +% +\begin{table-lX}{Vector Table} +0 & Main SP register value at reset \\ +1 & Reset \\ +2 & NMI \\ +3 & HardFault \\ +4 & MemManage \\ +5 & BusFault \\ +6 & UsageFault \\ +11 & SVCall \\ +12 & DebugMonitor \\ +14 & PendSV \\ +15 & SysTick \\ +16+\{n\} & External interrupt \{n\} \\ +\end{table-lX} +% +\begin{table-lX}{Address Map} +0x00000000-0x1fffffff & On-chip ROM or flash memory \\ +0x20000000-0x3fffffff & On-chip SRAM \\ +0x40000000-0x5fffffff & On-chip Peripherals \\ +0x60000000-0x7fffffff & RAM with write-back cache \\ +0x80000000-0x9fffffff & RAM with write-through cache \\ +0xa0000000-0xbfffffff & Shared device space \\ +0xc0000000-0xdfffffff & Non-shared device space \\ +0xe0000000-0xffffffff & System segment \\ +\end{table-lX} +% +\begin{table-llX}{Interrupt Control and State Register (ICSR)} +VECTACTIVE & 0x000001ff & Current executing exception (RO) \\ +RETTOBASE & 0x00000800 & No active exceptions (except by IPSR) (RO) \\ +VECTPENDING & 0x001ff000 & Highest pending and enabled exception (RO) \\ +ISRPENDING & 0x00400000 & External interrupt is pending (RO) \\ +ISRPREEMPT & 0x00800000 & Will service exception on debug exit (RO) \\ +PENDSTCLR & 0x02000000 & Clear pending SysTick exception \\ +PENDSTSET & 0x04000000 & Make SysTick exception pending \\ +PENDSVCLR & 0x08000000 & Clear pending PendSV exception \\ +PENDSVSET & 0x10000000 & Make PendSV exception pending \\ +NMIPENDSET & 0x80000000 & Make NMI exception active \\ +\end{table-llX} +% +\begin{table-llX}{SysTick Control and Status Register (SYST\_CSR)} +ENABLE & 0x00000001 & Counter is operating \\ +TICKINT & 0x00000002 & SysTick exception on counter zero \\ +CLKSOURCE & 0x00000004 & SysTick uses processor clock \\ +COUNTFLAG & 0x00010000 & Timer has reached zero since last read (RO) \\ +\end{table-llX} +% +\begin{table-llX}{System Control Registers} +ICTR & 0xe000e004 & Interrupt Controller Type Register \\ +ACTLR & 0xe000e008 & Auxiliary Control Register \\ +ICSR & 0xe000ed04 & Interrupt Control and State Register \\ +VTOR & 0xe000ed08 & Vector Table Offset Register \\ +AIRCR & 0xe000ed0c & App Interrupt and Reset Ctrl Reg \\ +SCR & 0xe000ed10 & System Control Register \\ +CCR & 0xe000ed14 & Configuration and Control Register \\ +SHPR\{1..3\} & 0xe000ed\{18..20\} & System Handler Priority Registers \\ +SHCSR & 0xe000ed24 & System Handler Control and State Reg \\ +CFSR & 0xe000ed28 & Configurable Fault Status Register \\ +HFSR & 0xe000ed2c & HardFault Status Register \\ +DFSR & 0xe000ed30 & Debug Fault Status Register \\ +MMFAR & 0xe000ed34 & MemManage Fault Address Registers \\ +BFAR & 0xe000ed38 & BusFault Address Register \\ +AFAR & 0xe000ed3c & Auxiliary Fault Status Register \\ +CPACR & 0xe000ed88 & Coprocessor Access Control Register \\ +\end{table-llX} +% +\begin{table-llX}{CPUID Registers (Read Only)} +CPUID & 0xe000ed00 & CPUID Base Register \\ +ID\_PFR\{0..1\} & 0xe000ed4\{0..4\} & Processor Feature Registers \\ +ID\_DFR0 & 0xe000ed48 & Debug Feature Register \\ +ID\_AFR0 & 0xe000ed4c & Auxiliary Feature Register \\ +ID\_MMFR\{0..3\} & 0xe000ed5\{0..c\} & Memory Model Feature Registers \\ +ID\_ISAR\{0..4\} & 0xe000ed\{60..70\} & Instruction Set Attribute Regs \\ +ID\_CLIDR & 0xe000ed78 & Cache Level ID Register \\ +ID\_CTR & 0xe000ed7c & Cache Type Register \\ +ID\_CCSIDR & 0xe000ed80 & Cache Size ID Register \\ +ID\_CSSELR & 0xe000ed84 & Cache Size Selection Register \\ +\end{table-llX} +% +\begin{table-llX}{System Timer Registers} +SYST\_CSR & 0xe000e010 & SysTick Control and Status Register \\ +SYST\_RVR & 0xe000e014 & SysTick Reload Value Register \\ +SYST\_CVR & 0xe000e018 & SysTick Current Value Register \\ +SYST\_CALIB & 0xe000e01c & SysTick Calibration Value Register \\ +\end{table-llX} +% +\begin{table-llX}{External Interrupt Controller Registers} +NVIC\_ISER\{0..15\} & 0xe000e1\{00..3c\} & Interrupt Set-Enable Registers \\ +NVIC\_ICER\{0..15\} & 0xe000e1\{80..bc\} & Interrupt Clear-Enable Registers \\ +NVIC\_ISPR\{0..15\} & 0xe000e2\{00..3c\} & Interrupt Set-Pending Registers \\ +NVIC\_ICPR\{0..15\} & 0xe000e2\{80..bc\} & Interrupt Clear-Pending Registers \\ +NVIC\_IABR\{0..15\} & 0xe000e3\{00..3c\} & Interrupt Active Bit Registers \\ +NVIC\_IPR\{0..123\} & 0xe000e\{400..5ec\} & Interrupt Priority Registers \\ +\end{table-llX} +% +\begin{table-llX}{Memory Protection Unit Registers} +MPU\_TYPE & 0xe000ed90 & MPU Type Register (RO) \\ +MPU\_CTRL & 0xe000ed94 & MPU Control Register \\ +MPU\_RNR & 0xe000ed98 & MPU Region Number Register \\ +MPU\_RBAR & 0xe000ed9c & MPU Region Base Address Register \\ +MPU\_RASR & 0xe000eda0 & MPU Region Attribute and Size Register \\ +\end{table-llX} +% +\begin{table-llX}{SW Trigger Interrupt Registers} +STIR & 0xe000ef00 & Software Triggered Interrupt Register (WO) \\ +FPCCR & 0xe000ef34 & Floating Point Context Control Register \\ +FPCAR & 0xe000ef38 & Floating Point Context Address Register \\ +FPDSCR & 0xe000ef3c & Floating Point Default Status Control Reg \\ +MVFR\{0..2\} & 0xe000ef4\{0..8\} & Medial and FP Feature Registers (RO) \\ +\end{table-llX} +% +\begin{table-llX}{Cache and Branch Predictior Maintenance (Write-Only)} +ICIALLU & 0xe000ef50 & I-cache invalidate all to PoU \\ +ICIMVAU & 0xe000ef58 & I-cache invalidate by MVA to PoU \\ +DCIMVAC & 0xe000ef5c & D-cache invalidate by MVA to PoC \\ +DCISW & 0xe000ef60 & D-cache invalidate by set-way \\ +DCCMVAU & 0xe000ef64 & D-cache clean by MVA to PoU \\ +DCCMVAC & 0xe000ef68 & D-cache clean by MVA to PoC \\ +DCCSW & 0xe000ef6c & D-cache clean by set-way \\ +DCCIMVAC & 0xe000ef70 & D-cache clean and invalidate by MVA to PoC \\ +DCCISW & 0xe000ef74 & D-cache clean and invalidate by set-way \\ +BPIALL & 0xe000ef78 & Branch predictor invalidate all \\ +\end{table-llX} +% +\begin{table-llX}{Microcontroller-specific ID Registers} +PID\{4..7\} & 0xe000efd\{0..c\} & Peripheral Identification Registers \\ +PID\{0..3\} & 0xe000efe\{0..c\} & Peripheral Identification Registers \\ +CID\{0..3\} & 0xe000eff\{0..c\} & Component Identification Registers \\ +\end{table-llX} +% \end{multicols} \end{document}