From 331c26feb399e4b9b97f14fb047bfb3309419c42 Mon Sep 17 00:00:00 2001 From: Wayne Ren Date: Sat, 29 Dec 2018 14:43:10 +0800 Subject: [PATCH 01/28] device: rs9113: eliminate the compile warning * eliminate the compile warnning for mwdt and gnu Signed-off-by: Wayne Ren --- .../wifi/rs9113/common/rsi_common_apis.c | 2 +- .../rs9113/driver/rsi_driver_event_handlers.c | 6 +- .../rs9113/driver/rsi_setregion_countryinfo.c | 2 +- .../peripheral/wifi/rs9113/driver/rsi_utils.c | 2 +- .../peripheral/wifi/rs9113/driver/rsi_wlan.c | 7 +- .../wifi/rs9113/hal/rsi_hal_mcu_random.c | 1 + .../wifi/rs9113/hal/rsi_hal_mcu_timer.c | 89 ++++++------------- .../wifi/rs9113/include/rsi_wlan_apis.h | 2 +- .../wifi/rs9113/os/free_rtos/rsi_os_wrapper.c | 2 +- .../peripheral/wifi/rs9113/rs9113_adapter.c | 12 +-- .../wifi/rs9113/wlan/rsi_wlan_apis.c | 2 +- 11 files changed, 50 insertions(+), 77 deletions(-) diff --git a/device/peripheral/wifi/rs9113/common/rsi_common_apis.c b/device/peripheral/wifi/rs9113/common/rsi_common_apis.c index 76b146d3c..39d835135 100644 --- a/device/peripheral/wifi/rs9113/common/rsi_common_apis.c +++ b/device/peripheral/wifi/rs9113/common/rsi_common_apis.c @@ -95,7 +95,7 @@ void rsi_common_set_status(int32_t status) int32_t rsi_driver_init(uint8_t *buffer, uint32_t length) { uint32_t actual_length=0; - int32_t status = RSI_SUCCESS; + //int32_t status = RSI_SUCCESS; //! Memset user buffer memset(buffer, 0, length); diff --git a/device/peripheral/wifi/rs9113/driver/rsi_driver_event_handlers.c b/device/peripheral/wifi/rs9113/driver/rsi_driver_event_handlers.c index ae2aaffa3..a6fe0db88 100644 --- a/device/peripheral/wifi/rs9113/driver/rsi_driver_event_handlers.c +++ b/device/peripheral/wifi/rs9113/driver/rsi_driver_event_handlers.c @@ -286,9 +286,9 @@ void rsi_rx_event_handler(void) rsi_pkt_t *rx_pkt = NULL; #ifdef RSI_SPI_INTR_FIX #ifdef RSI_SPI_INTERFACE - uint16_t retval = 0; - uint8_t int_status = 0; - rsi_reg_flags_t flags; + // uint16_t retval = 0; + //uint8_t int_status = 0; + //rsi_reg_flags_t flags; #endif #endif diff --git a/device/peripheral/wifi/rs9113/driver/rsi_setregion_countryinfo.c b/device/peripheral/wifi/rs9113/driver/rsi_setregion_countryinfo.c index b0c95eb23..ca7da6e20 100644 --- a/device/peripheral/wifi/rs9113/driver/rsi_setregion_countryinfo.c +++ b/device/peripheral/wifi/rs9113/driver/rsi_setregion_countryinfo.c @@ -48,7 +48,7 @@ void extract_setregionap_country_info(rsi_req_set_region_ap_t *rsi_set_region_ap { //! The given domain rules are generic rules for some of the countries //! USER can configure the domain regulations for the respective countries - uint8_t region_code; + uint8_t region_code = 0; if(!strcmp(RSI_COUNTRY_CODE,"US ")) region_code = REGION_US; diff --git a/device/peripheral/wifi/rs9113/driver/rsi_utils.c b/device/peripheral/wifi/rs9113/driver/rsi_utils.c index ed64abf4c..94ce6572c 100644 --- a/device/peripheral/wifi/rs9113/driver/rsi_utils.c +++ b/device/peripheral/wifi/rs9113/driver/rsi_utils.c @@ -204,7 +204,7 @@ void rsi_ascii_dev_address_to_6bytes_rev(uint8_t *hex_addr, int8_t *ascii_mac_ad int8_t hex_to_ascii (uint8_t hex_num) { - uint8_t ascii; + uint8_t ascii = 0; switch (hex_num & 0x0F) { case 0: diff --git a/device/peripheral/wifi/rs9113/driver/rsi_wlan.c b/device/peripheral/wifi/rs9113/driver/rsi_wlan.c index b65d4f333..a5cc0d647 100644 --- a/device/peripheral/wifi/rs9113/driver/rsi_wlan.c +++ b/device/peripheral/wifi/rs9113/driver/rsi_wlan.c @@ -800,16 +800,17 @@ int32_t rsi_driver_wlan_send_cmd(rsi_wlan_cmd_request_t cmd, rsi_pkt_t *pkt) int32_t rsi_driver_process_wlan_recv_cmd(rsi_pkt_t *pkt) { uint8_t cmd_type; - uint8_t ip_version,sockID,sock_id; + //uint8_t ip_version,sockID,sock_id; int32_t status = RSI_SUCCESS; uint16_t copy_length; uint8_t *host_desc; uint8_t *payload; uint16_t payload_length; - uint16_t length; - uint8_t buffers_freed; + //uint16_t length; + //uint8_t buffers_freed; int8_t wlan_pkt_pending = 0; + //! Get wlan cb struct pointer rsi_wlan_cb_t *rsi_wlan_cb = rsi_driver_cb->wlan_cb; diff --git a/device/peripheral/wifi/rs9113/hal/rsi_hal_mcu_random.c b/device/peripheral/wifi/rs9113/hal/rsi_hal_mcu_random.c index b58e28167..c9f549388 100644 --- a/device/peripheral/wifi/rs9113/hal/rsi_hal_mcu_random.c +++ b/device/peripheral/wifi/rs9113/hal/rsi_hal_mcu_random.c @@ -23,6 +23,7 @@ * Includes */ #include "rsi_driver.h" +#include /** diff --git a/device/peripheral/wifi/rs9113/hal/rsi_hal_mcu_timer.c b/device/peripheral/wifi/rs9113/hal/rsi_hal_mcu_timer.c index 1619a0f2e..bca622051 100644 --- a/device/peripheral/wifi/rs9113/hal/rsi_hal_mcu_timer.c +++ b/device/peripheral/wifi/rs9113/hal/rsi_hal_mcu_timer.c @@ -1,34 +1,39 @@ -/** - * @file rsi_hal_mcu_timer.c - * @version 0.1 - * @date 15 Aug 2015 - * - * Copyright(C) Redpine Signals 2015 - * All rights reserved by Redpine Signals. - * - * @section License - * This program should be used on your own responsibility. - * Redpine Signals assumes no responsibility for any losses - * incurred by customers or third parties arising from the use of this file. +/* ------------------------------------------ + * Copyright (c) 2018, Synopsys, Inc. All rights reserved. + + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + + * 1) Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + + * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * @brief HAL TIMER: Functions related to HAL timers - * - * @section Description - * This file contains the list of functions for configuring the microcontroller timers. - * Following are list of API's which need to be defined in this file. - * - */ - +--------------------------------------------- */ /** * Includes */ #include "rsi_driver.h" -#include "embARC_error.h" -#include "arc_timer.h" -#include "board.h" -//#include "embARC.h" +#include "embARC.h" @@ -85,17 +90,11 @@ int32_t rsi_timer_start(uint8_t timer_node, uint8_t mode, uint8_t type, uint32_t int32_t rsi_timer_stop(uint8_t timer_node) { - //! Stop the timer // timer_stop(timer_node); return 0; - - } - - - /*===================================================*/ /** * @fn uint32_t rsi_timer_read(uint8_t timer_node) @@ -109,21 +108,13 @@ int32_t rsi_timer_stop(uint8_t timer_node) uint32_t rsi_timer_read(uint8_t timer_node) { - volatile uint32_t timer_val = 0; //! read the timer and return timer value // timer_current(timer_node, (void *)(&timer_val)); return timer_val; - - } - - - - - /*===================================================*/ /** * @fn void rsi_delay_us(uint32_t delay) @@ -136,16 +127,10 @@ uint32_t rsi_timer_read(uint8_t timer_node) */ void rsi_delay_us(uint32_t delay_us) { - //! call the API for delay in micro seconds - return; - } - - - /*===================================================*/ /** * @fn void rsi_delay_ms(uint32_t delay) @@ -158,8 +143,6 @@ void rsi_delay_us(uint32_t delay_us) */ void rsi_delay_ms(uint32_t delay_ms) { - - //! call the API for delay in milli seconds #ifdef OS_FREERTOS @@ -167,19 +150,5 @@ void rsi_delay_ms(uint32_t delay_ms) #else board_delay_ms(delay_ms, OSP_DELAY_OS_COMPAT_ENABLE); #endif - return; - } - - - - - - - - - - - - diff --git a/device/peripheral/wifi/rs9113/include/rsi_wlan_apis.h b/device/peripheral/wifi/rs9113/include/rsi_wlan_apis.h index 67b74eb82..d3dd075a4 100644 --- a/device/peripheral/wifi/rs9113/include/rsi_wlan_apis.h +++ b/device/peripheral/wifi/rs9113/include/rsi_wlan_apis.h @@ -639,7 +639,7 @@ typedef struct rsi_scan_info_s //! reserved uint8_t reserved[2]; -}rsi_scan_info_t; +} rsi_scan_info_t; //! multicast command request structure typedef struct rsi_req_multicast_filter_info_s diff --git a/device/peripheral/wifi/rs9113/os/free_rtos/rsi_os_wrapper.c b/device/peripheral/wifi/rs9113/os/free_rtos/rsi_os_wrapper.c index f8ea9c8e3..a69b1dc35 100644 --- a/device/peripheral/wifi/rs9113/os/free_rtos/rsi_os_wrapper.c +++ b/device/peripheral/wifi/rs9113/os/free_rtos/rsi_os_wrapper.c @@ -219,7 +219,7 @@ rsi_error_t rsi_semaphore_create(rsi_semaphore_handle_t *semaphore,uint32_t coun *p_semaphore = xSemaphoreCreateBinary(); - if(*semaphore == NULL) + if(*p_semaphore == NULL) { return RSI_ERROR_IN_OS_OPERATION; } diff --git a/device/peripheral/wifi/rs9113/rs9113_adapter.c b/device/peripheral/wifi/rs9113/rs9113_adapter.c index f79f56dc7..9e7f13391 100644 --- a/device/peripheral/wifi/rs9113/rs9113_adapter.c +++ b/device/peripheral/wifi/rs9113/rs9113_adapter.c @@ -185,8 +185,9 @@ int32_t rs9113_wnic_init(DEV_WNIC_PTR rs9113_wnic, uint32_t network_type) //! Task created for Driver task if (driver_task_handle == NULL) { - rsi_task_create(rsi_wireless_driver_task, "driver_task", RSI_DRIVER_TASK_STACK_SIZE, NULL, RSI_DRIVER_TASK_PRIORITY, - &driver_task_handle); + rsi_task_create((rsi_task_function_t)rsi_wireless_driver_task, + (uint8_t *)"driver_task", RSI_DRIVER_TASK_STACK_SIZE, NULL, + RSI_DRIVER_TASK_PRIORITY, &driver_task_handle); } //a short delay to wait the device get ready @@ -196,7 +197,7 @@ int32_t rs9113_wnic_init(DEV_WNIC_PTR rs9113_wnic, uint32_t network_type) dbg_printf(DBG_MORE_INFO, "rsi_wireless_init return 0x%x\r\n", ercd); RS9113_CHECK_EXP(ercd == E_OK, E_SYS); //register rs9113 on receive callback function - rsi_wlan_register_callbacks(RSI_WLAN_DATA_RECEIVE_NOTIFY_CB, rswifi_on_input); + rsi_wlan_register_callbacks(RSI_WLAN_DATA_RECEIVE_NOTIFY_CB, (void *)rswifi_on_input); rs9113_info->power_status = WNIC_POWER_NORMAL; rs9113_info->init_status = WNIC_INIT_SUCCESSFUL; /* stop initialization process */ @@ -373,9 +374,10 @@ int32_t rs9113_get_scan_result_cnt(DEV_WNIC_PTR rs9113_wnic) return ercd; } -static rsi_scan_info_t *p_scan_result = &(scan_result.scan_info); + int32_t rs9113_get_scan_result(DEV_WNIC_PTR rs9113_wnic, uint32_t index, WNIC_SCAN_RESULT *result) { + static rsi_scan_info_t *p_scan_result = (rsi_scan_info_t *)(&(scan_result.scan_info)); int32_t ercd = E_OK; DEV_WNIC_INFO *rs9113_info; rsi_scan_info_t *p_scan_result_temp; @@ -547,7 +549,7 @@ int32_t rs9113_wnic_connect(DEV_WNIC_PTR rs9113_wnic, uint32_t security, const u } //register rs9113 on receive callback function - rsi_wlan_register_callbacks(RSI_WLAN_DATA_RECEIVE_NOTIFY_CB, rswifi_on_input); + rsi_wlan_register_callbacks(RSI_WLAN_DATA_RECEIVE_NOTIFY_CB, (void *)rswifi_on_input); rs9113_info->mac_status = WNIC_MAC_NOT_UPDATED; rs9113_info->conn_status = WNIC_CONNECTED; rs9113_on_ops = &(rs9113_wnic->wnic_on_ops); diff --git a/device/peripheral/wifi/rs9113/wlan/rsi_wlan_apis.c b/device/peripheral/wifi/rs9113/wlan/rsi_wlan_apis.c index 7bb8dbc56..1735b0185 100644 --- a/device/peripheral/wifi/rs9113/wlan/rsi_wlan_apis.c +++ b/device/peripheral/wifi/rs9113/wlan/rsi_wlan_apis.c @@ -629,7 +629,7 @@ int32_t rsi_wlan_connect_async(int8_t *ssid, rsi_security_mode_t sec_type, void #endif //! Send EAP command for EAP security - if((wlan_cb->opermode == RSI_WLAN_ENTERPRISE_CLIENT_MODE)) + if(wlan_cb->opermode == RSI_WLAN_ENTERPRISE_CLIENT_MODE) { credentials = (rsi_eap_credentials_t *)secret_key; From fe6c32548ee862667ef8006348a6ef0916410217 Mon Sep 17 00:00:00 2001 From: Wayne Ren Date: Sat, 29 Dec 2018 14:45:04 +0800 Subject: [PATCH 02/28] middlware: lwip: eliminate the compile warning elminate the compile warning msg Signed-off-by: Wayne Ren --- middleware/lwip-contrib/ports/arc/include/arch/cc.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/middleware/lwip-contrib/ports/arc/include/arch/cc.h b/middleware/lwip-contrib/ports/arc/include/arch/cc.h index f5d5f87b4..85dd0ff79 100644 --- a/middleware/lwip-contrib/ports/arc/include/arch/cc.h +++ b/middleware/lwip-contrib/ports/arc/include/arch/cc.h @@ -66,6 +66,8 @@ // Extra defintion needed by Metaware Toolchain #ifdef __MW__ +#define SZT_F "d" + #endif /* __MW__ */ /* Define platform endianness */ From fa5a9dc2bc9aaecd713f63ba59225d8bb533d530 Mon Sep 17 00:00:00 2001 From: Wayne Ren Date: Sat, 29 Dec 2018 15:22:34 +0800 Subject: [PATCH 03/28] middleware: mbedtls: update the embarc support update the embarc support in mbedtls Signed-off-by: Wayne Ren --- ...ARC-FreeRTOS-LwIP-support-to-mbedtls.patch | 36 +-- ...ight-and-add-the-support-of-DW-timer.patch | 243 ++++++++++++++++++ 2 files changed, 261 insertions(+), 18 deletions(-) create mode 100644 middleware/mbedtls/0002-update-the-copyright-and-add-the-support-of-DW-timer.patch diff --git a/middleware/mbedtls/0001-Add-embARC-FreeRTOS-LwIP-support-to-mbedtls.patch b/middleware/mbedtls/0001-Add-embARC-FreeRTOS-LwIP-support-to-mbedtls.patch index 875cdacb4..4b6617bfa 100644 --- a/middleware/mbedtls/0001-Add-embARC-FreeRTOS-LwIP-support-to-mbedtls.patch +++ b/middleware/mbedtls/0001-Add-embARC-FreeRTOS-LwIP-support-to-mbedtls.patch @@ -1,17 +1,17 @@ -From 77dd67234edd55942f9ddb4eef2deba0b4b84569 Mon Sep 17 00:00:00 2001 +From cb4bf4d8b82dcfcb5049ae3a25d6ce7e72859ed2 Mon Sep 17 00:00:00 2001 From: XiangcaiHuang Date: Thu, 17 Aug 2017 11:21:12 +0800 -Subject: [PATCH] Add embARC (FreeRTOS+LwIP) support to mbedtls +Subject: [PATCH 1/2] Add embARC (FreeRTOS+LwIP) support to mbedtls --- - library/net_sockets.c => embARC/net_alt.c | 94 ++------------------- - embARC/threading_alt.c | 80 ++++++++++++++++++ - embARC/threading_alt.h | 65 ++++++++++++++ - embARC/timing_alt.c | 111 ++++++++++++++++++++++++ - embARC/timing_alt.h | 136 ++++++++++++++++++++++++++++++ + library/net_sockets.c => embARC/net_alt.c | 94 ++------------- + embARC/threading_alt.c | 80 +++++++++++++ + embARC/threading_alt.h | 65 +++++++++++ + embARC/timing_alt.c | 111 ++++++++++++++++++ + embARC/timing_alt.h | 136 ++++++++++++++++++++++ library/ssl_srv.c | 2 + - library/ssl_tls.c | 21 ++++- - library/threading.c | 11 +++ + library/ssl_tls.c | 21 +++- + library/threading.c | 11 ++ 8 files changed, 434 insertions(+), 86 deletions(-) rename library/net_sockets.c => embARC/net_alt.c (85%) create mode 100644 embARC/threading_alt.c @@ -23,7 +23,7 @@ diff --git a/library/net_sockets.c b/embARC/net_alt.c similarity index 85% rename from library/net_sockets.c rename to embARC/net_alt.c -index cc06cbf..5c0bf0c 100644 +index cc06cbfad..5c0bf0c83 100644 --- a/library/net_sockets.c +++ b/embARC/net_alt.c @@ -27,98 +27,26 @@ @@ -189,7 +189,7 @@ index cc06cbf..5c0bf0c 100644 diff --git a/embARC/threading_alt.c b/embARC/threading_alt.c new file mode 100644 -index 0000000..4f830a9 +index 000000000..4f830a911 --- /dev/null +++ b/embARC/threading_alt.c @@ -0,0 +1,80 @@ @@ -275,7 +275,7 @@ index 0000000..4f830a9 +#endif /* MBEDTLS_THREADING_C */ diff --git a/embARC/threading_alt.h b/embARC/threading_alt.h new file mode 100644 -index 0000000..8ffee49 +index 000000000..8ffee49df --- /dev/null +++ b/embARC/threading_alt.h @@ -0,0 +1,65 @@ @@ -347,7 +347,7 @@ index 0000000..8ffee49 \ No newline at end of file diff --git a/embARC/timing_alt.c b/embARC/timing_alt.c new file mode 100644 -index 0000000..aaa5aab +index 000000000..aaa5aab62 --- /dev/null +++ b/embARC/timing_alt.c @@ -0,0 +1,111 @@ @@ -464,7 +464,7 @@ index 0000000..aaa5aab + diff --git a/embARC/timing_alt.h b/embARC/timing_alt.h new file mode 100644 -index 0000000..151765d +index 000000000..151765d34 --- /dev/null +++ b/embARC/timing_alt.h @@ -0,0 +1,136 @@ @@ -605,7 +605,7 @@ index 0000000..151765d + +#endif /* timing.h */ diff --git a/library/ssl_srv.c b/library/ssl_srv.c -index fc0d2d7..b5ea02c 100644 +index fc0d2d7b4..b5ea02c5d 100644 --- a/library/ssl_srv.c +++ b/library/ssl_srv.c @@ -3016,6 +3016,8 @@ curve_matching_done: @@ -618,7 +618,7 @@ index fc0d2d7..b5ea02c 100644 ssl->out_msglen = 4 + n; ssl->out_msgtype = MBEDTLS_SSL_MSG_HANDSHAKE; diff --git a/library/ssl_tls.c b/library/ssl_tls.c -index 84a04ae..2153c80 100644 +index 84a04ae53..2153c80ab 100644 --- a/library/ssl_tls.c +++ b/library/ssl_tls.c @@ -3608,6 +3608,24 @@ static int ssl_parse_record_header( mbedtls_ssl_context *ssl ) @@ -657,7 +657,7 @@ index 84a04ae..2153c80 100644 if( 0 != ret ) { diff --git a/library/threading.c b/library/threading.c -index 83ec01a..92ae7ee 100644 +index 83ec01a45..92ae7eefe 100644 --- a/library/threading.c +++ b/library/threading.c @@ -82,6 +82,16 @@ int (*mbedtls_mutex_unlock)( mbedtls_threading_mutex_t * ) = threading_mutex_unl @@ -686,5 +686,5 @@ index 83ec01a..92ae7ee 100644 /* * Set functions pointers and initialize global mutexes -- -2.13.2.windows.1 +2.17.1.windows.2 diff --git a/middleware/mbedtls/0002-update-the-copyright-and-add-the-support-of-DW-timer.patch b/middleware/mbedtls/0002-update-the-copyright-and-add-the-support-of-DW-timer.patch new file mode 100644 index 000000000..50290e67e --- /dev/null +++ b/middleware/mbedtls/0002-update-the-copyright-and-add-the-support-of-DW-timer.patch @@ -0,0 +1,243 @@ +From 3dbb8cfe1e5a83ccfb717b04b3178ffe2e4b6e12 Mon Sep 17 00:00:00 2001 +From: Wayne Ren +Date: Sat, 29 Dec 2018 15:16:37 +0800 +Subject: [PATCH 2/2] update the copyright and add the support of DW timer + +* update copyright +* There is no TIMER1 in EMSDP, instead, use DW timer 0 channel 0 +as timer for mbedtls + +Signed-off-by: Wayne Ren +--- + embARC/threading_alt.c | 48 ++++++++++++++++++-------------- + embARC/threading_alt.h | 50 +++++++++++++++++++--------------- + embARC/timing_alt.c | 62 ++++++++++++++++++++++++++++-------------- + embARC/timing_alt.h | 6 +--- + 4 files changed, 98 insertions(+), 68 deletions(-) + +diff --git a/embARC/threading_alt.c b/embARC/threading_alt.c +index 4f830a911..d3467f5c5 100644 +--- a/embARC/threading_alt.c ++++ b/embARC/threading_alt.c +@@ -1,23 +1,31 @@ +-/* +- * Threading abstraction layer +- * +- * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved +- * SPDX-License-Identifier: Apache-2.0 +- * +- * Licensed under the Apache License, Version 2.0 (the "License"); you may +- * not use this file except in compliance with the License. +- * You may obtain a copy of the License at +- * +- * http://www.apache.org/licenses/LICENSE-2.0 +- * +- * Unless required by applicable law or agreed to in writing, software +- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +- * See the License for the specific language governing permissions and +- * limitations under the License. +- * +- * This file is part of mbed TLS (https://tls.mbed.org) +- */ ++/* ------------------------------------------ ++ * Copyright (c) 2018, Synopsys, Inc. All rights reserved. ++ ++ * Redistribution and use in source and binary forms, with or without modification, ++ * are permitted provided that the following conditions are met: ++ ++ * 1) Redistributions of source code must retain the above copyright notice, this ++ * list of conditions and the following disclaimer. ++ ++ * 2) Redistributions in binary form must reproduce the above copyright notice, ++ * this list of conditions and the following disclaimer in the documentation and/or ++ * other materials provided with the distribution. ++ ++ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may ++ * be used to endorse or promote products derived from this software without ++ * specific prior written permission. ++ ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ++ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++--------------------------------------------- */ + + #if !defined(MBEDTLS_CONFIG_FILE) + #include "mbedtls/config.h" +diff --git a/embARC/threading_alt.h b/embARC/threading_alt.h +index 8ffee49df..beb9096e3 100644 +--- a/embARC/threading_alt.h ++++ b/embARC/threading_alt.h +@@ -1,25 +1,31 @@ +-/** +- * \file threading.h +- * +- * \brief Threading abstraction layer +- * +- * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved +- * SPDX-License-Identifier: Apache-2.0 +- * +- * Licensed under the Apache License, Version 2.0 (the "License"); you may +- * not use this file except in compliance with the License. +- * You may obtain a copy of the License at +- * +- * http://www.apache.org/licenses/LICENSE-2.0 +- * +- * Unless required by applicable law or agreed to in writing, software +- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +- * See the License for the specific language governing permissions and +- * limitations under the License. +- * +- * This file is part of mbed TLS (https://tls.mbed.org) +- */ ++/* ------------------------------------------ ++ * Copyright (c) 2018, Synopsys, Inc. All rights reserved. ++ ++ * Redistribution and use in source and binary forms, with or without modification, ++ * are permitted provided that the following conditions are met: ++ ++ * 1) Redistributions of source code must retain the above copyright notice, this ++ * list of conditions and the following disclaimer. ++ ++ * 2) Redistributions in binary form must reproduce the above copyright notice, ++ * this list of conditions and the following disclaimer in the documentation and/or ++ * other materials provided with the distribution. ++ ++ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may ++ * be used to endorse or promote products derived from this software without ++ * specific prior written permission. ++ ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ++ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++--------------------------------------------- */ + #ifndef MBEDTLS_THREADING_ALT_H + #define MBEDTLS_THREADING_ALT_H + +diff --git a/embARC/timing_alt.c b/embARC/timing_alt.c +index aaa5aab62..b017d9dad 100644 +--- a/embARC/timing_alt.c ++++ b/embARC/timing_alt.c +@@ -1,23 +1,31 @@ +-/* +- * Portable interface to the CPU cycle counter +- * +- * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved +- * SPDX-License-Identifier: Apache-2.0 +- * +- * Licensed under the Apache License, Version 2.0 (the "License"); you may +- * not use this file except in compliance with the License. +- * You may obtain a copy of the License at +- * +- * http://www.apache.org/licenses/LICENSE-2.0 +- * +- * Unless required by applicable law or agreed to in writing, software +- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +- * See the License for the specific language governing permissions and +- * limitations under the License. +- * +- * This file is part of mbed TLS (https://tls.mbed.org) +- */ ++/* ------------------------------------------ ++ * Copyright (c) 2018, Synopsys, Inc. All rights reserved. ++ ++ * Redistribution and use in source and binary forms, with or without modification, ++ * are permitted provided that the following conditions are met: ++ ++ * 1) Redistributions of source code must retain the above copyright notice, this ++ * list of conditions and the following disclaimer. ++ ++ * 2) Redistributions in binary form must reproduce the above copyright notice, ++ * this list of conditions and the following disclaimer in the documentation and/or ++ * other materials provided with the distribution. ++ ++ * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may ++ * be used to endorse or promote products derived from this software without ++ * specific prior written permission. ++ ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ++ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++--------------------------------------------- */ + /* + * Modified for port to ARC processor + */ +@@ -62,17 +70,29 @@ unsigned long mbedtls_timing_get_timer( struct mbedtls_timing_hr_time *val, int + + static void mbedtls_alarm_handler(void *param) { + mbedtls_timing_alarmed = 1; ++#if ARC_FEATURE_TIMER1_PRESENT > 0 + int_disable(INTNO_TIMER1); ++#endif + } + + + void mbedtls_set_alarm( int seconds ) + { +- mbedtls_timing_alarmed = 0; ++#if ARC_FEATURE_TIMER1_PRESENT > 0 + int_disable(INTNO_TIMER1); /* disable first then enable */ + int_handler_install(INTNO_TIMER1, mbedtls_alarm_handler); + timer_start(TIMER_1, TIMER_CTRL_IE, 1000 * seconds * (BOARD_CPU_CLOCK / BOARD_SYS_TIMER_HZ)); + int_enable(INTNO_TIMER1); ++#elif defined(BOARD_EMSDP) ++ DEV_PWM_TIMER_PTR timer = pwm_timer_get_dev(DW_PWM_TIMER_0_ID); ++ ++ timer->pwm_timer_open(); ++ ++ timer->pwm_timer_write(0, DEV_PWM_TIMER_MODE_TIMER, 1000 * seconds, 0); ++ timer->pwm_timer_control(0, PWM_TIMER_CMD_SET_ISR, (void *)(mbedtls_alarm_handler)); ++ timer->pwm_timer_control(0, PWM_TIMER_CMD_ENA_ISR, (void *)(0)); ++#endif ++ mbedtls_timing_alarmed = 0; + } + + void mbedtls_timing_set_delay( void *data, uint32_t int_ms, uint32_t fin_ms ) +diff --git a/embARC/timing_alt.h b/embARC/timing_alt.h +index 151765d34..a3463ba91 100644 +--- a/embARC/timing_alt.h ++++ b/embARC/timing_alt.h +@@ -1,5 +1,5 @@ + /* ------------------------------------------ +- * Copyright (c) 2015, Synopsys, Inc. All rights reserved. ++ * Copyright (c) 2018, Synopsys, Inc. All rights reserved. + + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: +@@ -25,10 +25,6 @@ + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- * +- * \version 2015.10 +- * \date 2015-12-29 +- * \author Wayne Ren(Wei.Ren@synopsys.com) + --------------------------------------------- */ + #ifndef _TIMING_ALT_H_ + #define _TIMING_ALT_H_ +-- +2.17.1.windows.2 + From 179f4b6b05711f16fb5a58607dde3c4abc91c831 Mon Sep 17 00:00:00 2001 From: Wayne Ren Date: Sat, 29 Dec 2018 15:24:01 +0800 Subject: [PATCH 04/28] example: update the mbedtls related examples now it can compile for emsdp Signed-off-by: Wayne Ren --- .../sec/mbedtls/dtls/client/FreeRTOSConfig.h | 2 +- .../sec/mbedtls/dtls/client/README.rst | 50 +++++++++++++++++ .../freertos/sec/mbedtls/dtls/client/makefile | 12 +++-- .../sec/mbedtls/dtls/client/readme.txt | 36 ------------- .../sec/mbedtls/dtls/server/FreeRTOSConfig.h | 2 +- .../sec/mbedtls/dtls/server/README.rst | 46 ++++++++++++++++ .../freertos/sec/mbedtls/dtls/server/makefile | 12 +++-- .../sec/mbedtls/dtls/server/readme.txt | 35 ------------ .../sec/mbedtls/ssl/client2/FreeRTOSConfig.h | 2 +- .../sec/mbedtls/ssl/client2/README.rst | 53 +++++++++++++++++++ .../freertos/sec/mbedtls/ssl/client2/makefile | 12 +++-- .../sec/mbedtls/ssl/client2/readme.txt | 37 ------------- .../sec/mbedtls/ssl/server2/FreeRTOSConfig.h | 2 +- .../sec/mbedtls/ssl/server2/README.rst | 49 +++++++++++++++++ .../freertos/sec/mbedtls/ssl/server2/makefile | 14 +++-- .../sec/mbedtls/ssl/server2/readme.txt | 36 ------------- 16 files changed, 238 insertions(+), 162 deletions(-) delete mode 100644 example/freertos/sec/mbedtls/dtls/client/readme.txt delete mode 100644 example/freertos/sec/mbedtls/dtls/server/readme.txt delete mode 100644 example/freertos/sec/mbedtls/ssl/client2/readme.txt delete mode 100644 example/freertos/sec/mbedtls/ssl/server2/readme.txt diff --git a/example/freertos/sec/mbedtls/dtls/client/FreeRTOSConfig.h b/example/freertos/sec/mbedtls/dtls/client/FreeRTOSConfig.h index 88dac0885..cf1ef2dcc 100644 --- a/example/freertos/sec/mbedtls/dtls/client/FreeRTOSConfig.h +++ b/example/freertos/sec/mbedtls/dtls/client/FreeRTOSConfig.h @@ -86,7 +86,7 @@ #define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) #define configMAX_PRIORITIES ( 10 ) #define configMINIMAL_STACK_SIZE ( ( unsigned short ) 104 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1024 * 1024 ) ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32 * 1024 ) ) #define configMAX_TASK_NAME_LEN ( 20 ) #define configUSE_TRACE_FACILITY 0 #define configUSE_16_BIT_TICKS 0 diff --git a/example/freertos/sec/mbedtls/dtls/client/README.rst b/example/freertos/sec/mbedtls/dtls/client/README.rst index 1e04c5cfc..34fcb6797 100644 --- a/example/freertos/sec/mbedtls/dtls/client/README.rst +++ b/example/freertos/sec/mbedtls/dtls/client/README.rst @@ -2,3 +2,53 @@ FreeRTOS mbed TLS Example: DTLS Client ###################################### + + +Overview +******** + +This example takes reference from mbedtls **dtls_client** to test dtls client functionality. + + +Detailed Description +==================== + +* Extra Required Tools + +* Extra Required Peripherals + + - Digilent PMOD WIFI(MRF24WG0MA) + - SD Card to store certification file, key file + +.. note:: + EMSDP has board WiFi module, no need to use PMOD WiFI. + +.. note:: + The memory footprint of this example is larger then + the default configuration of |iotdk|. Without optimization ,this example doesnot support |iotdk| + +Buidling and Running +******************** + +1. Before building this example, it's required to get the mbedtls code and apply specific patch through the ``apply_embarc_patch.sh`` by the following commands + +.. code-block:: console + + cd /middleware/mbedtls + sh apply_embarc_patch.sh + +2. In pc node or mbedtls dtls_server node, run the server application to listen. + +3. Copy the ``tests`` dir in ``middleware/mbedtls`` into the SD card of secure server node, it will load CA file and key file. + +4. Change SERVER_NAME and SERVER_ADDR in dtls_client.c to the dtls_server node's IP address. And build this application again. + +5. When initialization finished and network connected, run **main** in ntshell, it will try to do dtls communication. + +Sample Output +============= + +.. code-block:: console + + + diff --git a/example/freertos/sec/mbedtls/dtls/client/makefile b/example/freertos/sec/mbedtls/dtls/client/makefile index e56d9f8e0..25ec75b01 100644 --- a/example/freertos/sec/mbedtls/dtls/client/makefile +++ b/example/freertos/sec/mbedtls/dtls/client/makefile @@ -1,11 +1,17 @@ # Application name APPL ?= mbedtls_dtls_client -EXT_DEV_LIST += wifi/mrf24g sensor/temperature/adt7420 +BOARD ?= emsk + +ifeq ($(BOARD), emsdp) +EXT_DEV_LIST += wifi/rs9113 +else +EXT_DEV_LIST += wifi/mrf24g +endif # Heap Size Settings -HEAPSZ ?= 1048576 -STACKSZ ?= 1048576 +HEAPSZ ?= 8192 +STACKSZ ?= 2048 APPL_DEFINES = -DMBEDTLS_CONFIG_FILE=\"mbedtls_config.h\" diff --git a/example/freertos/sec/mbedtls/dtls/client/readme.txt b/example/freertos/sec/mbedtls/dtls/client/readme.txt deleted file mode 100644 index 49f817923..000000000 --- a/example/freertos/sec/mbedtls/dtls/client/readme.txt +++ /dev/null @@ -1,36 +0,0 @@ -/* - * - * Copyright (C) 2016 by Synopsys, Inc. - * - * - * - */ -/*! -\defgroup EMBARC_APP_FREERTOS_SEC_MBEDTLS_DTLS_CLIENT embARC DTLS Secure Client using mbed TLS -\ingroup EMBARC_APPS_TOTAL -\ingroup EMBARC_APPS_OS_FREERTOS -\ingroup EMBARC_APPS_MID_LWIP -\ingroup EMBARC_APPS_MID_MBEDTLS -\brief embARC example for DTLS secure client using mbed TLS -\details -### Extra Required Tools - -### Extra Required Peripherals - - Digilent PMOD WIFI(MRF24WG0MA) - - SD Card to store certification file, key file - -### Design Concept - This example takes from mbedtls dtls_client to test dtls client functionality. - -### Usage Manual - - In pc node or EMSK mbedtls dtls_server node, run the server application to listen, refer to \ref EMBARC_APP_FREERTOS_SEC_MBEDTLS_DTLS_SERVER "Run mbedtls dtls_server". - - Copy the **tests** dir in middleware/mbedtls into the SD card of secure server node, it will load CA file and key file. - - Change SERVER_NAME and SERVER_ADDR in dtls_client.c to the dtls_server node's IP address. And build this application again. - - When initialization finished and network connected, run **main** in ntshell, it will try to do dtls communication. - - ![ScreenShot of mbedtls dtls client](pic/images/example/emsk/freertos_sec_mbedtls_dtls_client.jpg) - -### Extra Comments - -*/ - diff --git a/example/freertos/sec/mbedtls/dtls/server/FreeRTOSConfig.h b/example/freertos/sec/mbedtls/dtls/server/FreeRTOSConfig.h index 88dac0885..cf1ef2dcc 100644 --- a/example/freertos/sec/mbedtls/dtls/server/FreeRTOSConfig.h +++ b/example/freertos/sec/mbedtls/dtls/server/FreeRTOSConfig.h @@ -86,7 +86,7 @@ #define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) #define configMAX_PRIORITIES ( 10 ) #define configMINIMAL_STACK_SIZE ( ( unsigned short ) 104 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1024 * 1024 ) ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32 * 1024 ) ) #define configMAX_TASK_NAME_LEN ( 20 ) #define configUSE_TRACE_FACILITY 0 #define configUSE_16_BIT_TICKS 0 diff --git a/example/freertos/sec/mbedtls/dtls/server/README.rst b/example/freertos/sec/mbedtls/dtls/server/README.rst index b92789995..61c66bb83 100644 --- a/example/freertos/sec/mbedtls/dtls/server/README.rst +++ b/example/freertos/sec/mbedtls/dtls/server/README.rst @@ -2,3 +2,49 @@ FreeRTOS mbed TLS Example: DTLS Server ###################################### + +Overview +******** + +This example takes reference from mbedtls **dtls_server** to test dtls client functionality. + + +Detailed Description +==================== + +* Extra Required Tools + +* Extra Required Peripherals + + - Digilent PMOD WIFI(MRF24WG0MA) + - SD Card to store certification file, key file + +.. note:: + EMSDP has board WiFi module, no need to use PMOD WiFI. + +.. note:: + The memory footprint of this example is larger then + the default configuration of |iotdk|. Without optimization ,this example doesnot support |iotdk| + + +Buidling and Running +******************** + +1. Before building this example, it's required to get the mbedtls code and apply specific patch through the ``apply_embarc_patch.sh`` by the following commands + +.. code-block:: console + + cd /middleware/mbedtls + sh apply_embarc_patch.sh + + +2. Copy the ``tests`` dir in ``middleware/mbedtls`` into the SD card of secure server node, it will load CA file and key file. + +3. When initialization finished and network connected, run **main** in ntshell, it will try to do dtls communication. + +4. In pc node or mbedtls dtls_client node, run the client application to connect to the server node. + +Sample Output +============= + +.. code-block:: console \ No newline at end of file diff --git a/example/freertos/sec/mbedtls/dtls/server/makefile b/example/freertos/sec/mbedtls/dtls/server/makefile index 514e5c139..6d60e2a4d 100644 --- a/example/freertos/sec/mbedtls/dtls/server/makefile +++ b/example/freertos/sec/mbedtls/dtls/server/makefile @@ -1,11 +1,17 @@ # Application name APPL ?= mbedtls_dtls_server -EXT_DEV_LIST += wifi/mrf24g sensor/temperature/adt7420 +BOARD ?= emsk + +ifeq ($(BOARD), emsdp) +EXT_DEV_LIST += wifi/rs9113 +else +EXT_DEV_LIST += wifi/mrf24g +endif # Heap Size Settings -HEAPSZ ?= 1048576 -STACKSZ ?= 1048576 +HEAPSZ ?= 8192 +STACKSZ ?= 2048 APPL_DEFINES = -DMBEDTLS_CONFIG_FILE=\"mbedtls_config.h\" diff --git a/example/freertos/sec/mbedtls/dtls/server/readme.txt b/example/freertos/sec/mbedtls/dtls/server/readme.txt deleted file mode 100644 index ec200338a..000000000 --- a/example/freertos/sec/mbedtls/dtls/server/readme.txt +++ /dev/null @@ -1,35 +0,0 @@ -/* - * - * Copyright (C) 2016 by Synopsys, Inc. - * - * - * - */ -/*! -\defgroup EMBARC_APP_FREERTOS_SEC_MBEDTLS_DTLS_SERVER embARC DTLS Secure Server using mbed TLS -\ingroup EMBARC_APPS_TOTAL -\ingroup EMBARC_APPS_OS_FREERTOS -\ingroup EMBARC_APPS_MID_LWIP -\ingroup EMBARC_APPS_MID_MBEDTLS -\brief embARC example for DTLS secure server using mbed TLS -\details -### Extra Required Tools - -### Extra Required Peripherals - - Digilent PMOD WIFI(MRF24WG0MA) - - SD Card to store certification file, key file - -### Design Concept - This example takes from mbedtls dtls_server to test dtls server functionality. - -### Usage Manual - - Copy the **tests** dir in middleware/mbedtls into the SD card of secure server node, it will load CA file and key file. - - When initialization finished and network connected, run **main** in ntshell, it will try to do dtls communication. - - In pc node or EMSK mbedtls dtls client node, run the client application to connect to the server node, refer to \ref EMBARC_APP_FREERTOS_SEC_MBEDTLS_DTLS_CLIENT "Run mbedtls dtls_client". - - ![ScreenShot of mbedtls dtls server](pic/images/example/emsk/freertos_sec_mbedtls_dtls_server.jpg) - -### Extra Comments - -*/ - diff --git a/example/freertos/sec/mbedtls/ssl/client2/FreeRTOSConfig.h b/example/freertos/sec/mbedtls/ssl/client2/FreeRTOSConfig.h index 88dac0885..cf1ef2dcc 100644 --- a/example/freertos/sec/mbedtls/ssl/client2/FreeRTOSConfig.h +++ b/example/freertos/sec/mbedtls/ssl/client2/FreeRTOSConfig.h @@ -86,7 +86,7 @@ #define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) #define configMAX_PRIORITIES ( 10 ) #define configMINIMAL_STACK_SIZE ( ( unsigned short ) 104 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1024 * 1024 ) ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32 * 1024 ) ) #define configMAX_TASK_NAME_LEN ( 20 ) #define configUSE_TRACE_FACILITY 0 #define configUSE_16_BIT_TICKS 0 diff --git a/example/freertos/sec/mbedtls/ssl/client2/README.rst b/example/freertos/sec/mbedtls/ssl/client2/README.rst index dc3ecdb6f..936375954 100644 --- a/example/freertos/sec/mbedtls/ssl/client2/README.rst +++ b/example/freertos/sec/mbedtls/ssl/client2/README.rst @@ -2,3 +2,56 @@ FreeRTOS mbed SSL Example: SSL Client ##################################### + + +Overview +******** + +This example takes reference from mbedtls **ssL_client2 ** to test ssl client functionality. + + +Detailed Description +==================== + +* Extra Required Tools + +* Extra Required Peripherals + + - Digilent PMOD WIFI(MRF24WG0MA) + - SD Card to store certification file, key file + +.. note:: + EMSDP has board WiFi module, no need to use PMOD WiFI. + +.. note:: + The memory footprint of this example is larger then + the default configuration of |iotdk|. Without optimization , + this example doesnot support |iotdk| + + +Buidling and Running +******************** + +1. Before building this example, it's required to get the mbedtls code and +apply specific patch through the ``apply_embarc_patch.sh`` by the following +commands + +.. code-block:: console + + cd /middleware/mbedtls + sh apply_embarc_patch.sh + +2. In pc node or mbedtls ssl server node, run the server application to listen. + +3. Copy the ``tests`` dir in ``middleware/mbedtls`` into the SD card of secure +server node, it will load CA file and key file. + +4. Here the mbedtls ssl server node's ip address is 192.168.43.76, we can get +it from console output of uart. When initialization finished and network +connected, run **main server_addr=192.168.43.76 auth_mode=optional** in +ntshell, it will try to do ssl communication. + +Sample Output +============= + +.. code-block:: console \ No newline at end of file diff --git a/example/freertos/sec/mbedtls/ssl/client2/makefile b/example/freertos/sec/mbedtls/ssl/client2/makefile index 240540563..4324a87c4 100644 --- a/example/freertos/sec/mbedtls/ssl/client2/makefile +++ b/example/freertos/sec/mbedtls/ssl/client2/makefile @@ -1,11 +1,17 @@ # Application name APPL ?= mbedtls_ssl_client2 -EXT_DEV_LIST += wifi/mrf24g sensor/temperature/adt7420 +BOARD ?= emsk + +ifeq ($(BOARD), emsdp) +EXT_DEV_LIST += wifi/rs9113 +else +EXT_DEV_LIST += wifi/mrf24g +endif # Heap Size Settings -HEAPSZ ?= 1048576 -STACKSZ ?= 1048576 +HEAPSZ ?= 8192 +STACKSZ ?= 2048 APPL_DEFINES = -DNTCONF_EDITOR_MAXLEN=256 -DMBEDTLS_CONFIG_FILE=\"mbedtls_config.h\" diff --git a/example/freertos/sec/mbedtls/ssl/client2/readme.txt b/example/freertos/sec/mbedtls/ssl/client2/readme.txt deleted file mode 100644 index 3992c4ae4..000000000 --- a/example/freertos/sec/mbedtls/ssl/client2/readme.txt +++ /dev/null @@ -1,37 +0,0 @@ -/* - * - * Copyright (C) 2016 by Synopsys, Inc. - * - * - * - */ -/*! -\defgroup EMBARC_APP_FREERTOS_SEC_MBEDTLS_SSL_CLIENT2 embARC SSL Secure Client using mbed TLS -\ingroup EMBARC_APPS_TOTAL -\ingroup EMBARC_APPS_OS_FREERTOS -\ingroup EMBARC_APPS_MID_LWIP -\ingroup EMBARC_APPS_MID_MBEDTLS -\brief embARC example for SSL secure client using mbed TLS -\details -### Extra Required Tools - -### Extra Required Peripherals - - Digilent PMOD WIFI(MRF24WG0MA) - - SD Card to store certification file, key file - -### Design Concept - This example takes from mbedtls ssL_client2 to test ssl client functionality. - -### Usage Manual - - In pc node or EMSK mbedtls ssl server node, run the server application to listen, refer to \ref EMBARC_APP_FREERTOS_SEC_MBEDTLS_SSL_SERVER2 "Run mbedtls ssl server". - - Copy the **tests** dir in middleware/mbedtls into the SD card of secure server node, it will load CA file and key file. - - Here the mbedtls ssl server node's ip address is 192.168.43.76, we can get it from console output of uart. - - When initialization finished and network connected, run **main server_addr=192.168.43.76 auth_mode=optional** in ntshell, it will try to do ssl communication. - - Run **main -h** for how to run this example. - - ![ScreenShot of mbedtls ssl client2](pic/images/example/emsk/freertos_sec_mbedtls_ssl_client2.jpg) - -### Extra Comments - -*/ - diff --git a/example/freertos/sec/mbedtls/ssl/server2/FreeRTOSConfig.h b/example/freertos/sec/mbedtls/ssl/server2/FreeRTOSConfig.h index 88dac0885..cf1ef2dcc 100644 --- a/example/freertos/sec/mbedtls/ssl/server2/FreeRTOSConfig.h +++ b/example/freertos/sec/mbedtls/ssl/server2/FreeRTOSConfig.h @@ -86,7 +86,7 @@ #define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) #define configMAX_PRIORITIES ( 10 ) #define configMINIMAL_STACK_SIZE ( ( unsigned short ) 104 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1024 * 1024 ) ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32 * 1024 ) ) #define configMAX_TASK_NAME_LEN ( 20 ) #define configUSE_TRACE_FACILITY 0 #define configUSE_16_BIT_TICKS 0 diff --git a/example/freertos/sec/mbedtls/ssl/server2/README.rst b/example/freertos/sec/mbedtls/ssl/server2/README.rst index f212c4b9c..7403e5205 100644 --- a/example/freertos/sec/mbedtls/ssl/server2/README.rst +++ b/example/freertos/sec/mbedtls/ssl/server2/README.rst @@ -2,3 +2,52 @@ FreeRTOS mbed SSL Example: SSL Server ##################################### + + +Overview +******** + +This example takes reference from mbedtls **ssl_server2 ** to test ssl server +functionality. + + +Detailed Description +==================== + +* Extra Required Tools + +* Extra Required Peripherals + + - Digilent PMOD WIFI(MRF24WG0MA) + - SD Card to store certification file, key file + +.. note:: + EMSDP has board WiFi module, no need to use PMOD WiFI. + +.. note:: + The memory footprint of this example is larger then + the default configuration of |iotdk|. Without optimization , + this example doesnot support |iotdk| + + +Buidling and Running +******************** + +1. Before building this example, it's required to get the mbedtls code and +apply specific patch through the ``apply_embarc_patch.sh`` by the following +commands + +.. code-block:: console + + cd /middleware/mbedtls + sh apply_embarc_patch.sh + +2. Copy the ``tests`` dir in ``middleware/mbedtls`` into the SD card of secure +server node, it will load CA file and key file. + +3. When initialization finished and network connected, run **main auth_mode=optional** in ntshell, it will wait for ssl client to connect to it. + +Sample Output +============= + +.. code-block:: console \ No newline at end of file diff --git a/example/freertos/sec/mbedtls/ssl/server2/makefile b/example/freertos/sec/mbedtls/ssl/server2/makefile index d05a76a02..def58166b 100644 --- a/example/freertos/sec/mbedtls/ssl/server2/makefile +++ b/example/freertos/sec/mbedtls/ssl/server2/makefile @@ -1,13 +1,17 @@ # Application name APPL ?= mbedtls_ssl_server2 -EXT_DEV_LIST += wifi/mrf24g sensor/temperature/adt7420 +BOARD ?= emsk -# Heap Size Settings -HEAPSZ ?= 1048576 -STACKSZ ?= 1048576 +ifeq ($(BOARD), emsdp) +EXT_DEV_LIST += wifi/rs9113 +else +EXT_DEV_LIST += wifi/mrf24g +endif -APPL_DEFINES = -DNTCONF_EDITOR_MAXLEN=256 -DMBEDTLS_CONFIG_FILE=\"mbedtls_config.h\" +# Heap Size Settings +HEAPSZ ?= 8192 +STACKSZ ?= 2048 # # root dir of embARC diff --git a/example/freertos/sec/mbedtls/ssl/server2/readme.txt b/example/freertos/sec/mbedtls/ssl/server2/readme.txt deleted file mode 100644 index f6ba55766..000000000 --- a/example/freertos/sec/mbedtls/ssl/server2/readme.txt +++ /dev/null @@ -1,36 +0,0 @@ -/* - * - * Copyright (C) 2016 by Synopsys, Inc. - * - * - * - */ -/*! -\defgroup EMBARC_APP_FREERTOS_SEC_MBEDTLS_SSL_SERVER2 embARC SSL Secure Server using mbed TLS -\ingroup EMBARC_APPS_TOTAL -\ingroup EMBARC_APPS_OS_FREERTOS -\ingroup EMBARC_APPS_MID_LWIP -\ingroup EMBARC_APPS_MID_MBEDTLS -\brief embARC example for SSL secure server using mbed TLS -\details -### Extra Required Tools - -### Extra Required Peripherals - - Digilent PMOD WIFI(MRF24WG0MA) - - SD Card to store certification file, key file - -### Design Concept - This example takes from mbedtls ssl_server2 to test ssl server functionality. - -### Usage Manual - - Copy the **tests** dir in middleware/mbedtls into the SD card of secure server node, it will load CA file and key file. - - When initialization finished and network connected, run **main auth_mode=optional** in ntshell, it will wait for ssl client to connect to it. - - Refer to \ref EMBARC_APP_FREERTOS_SEC_MBEDTLS_SSL_CLIENT2 "Run mbedtls ssl client" about how to run ssl client example. - - ![ScreenShot of mbedtls ssl server](pic/images/example/emsk/freertos_sec_mbedtls_ssl_server2.jpg) - - -### Extra Comments - -*/ - From fa3c44bcee7cf9fdfe92bbe080b1f7f72be198f5 Mon Sep 17 00:00:00 2001 From: Watson Zeng Date: Mon, 7 Jan 2019 16:10:42 +0800 Subject: [PATCH 05/28] middleware: mbedtls: update to mbedtls-2.16.0 example: sec: mbedtls: bugs fix in emsk and emsdp Signed-off-by: Watson Zeng --- .../peripheral/wifi/rs9113/rs9113_adapter.c | 2 +- .../sec/mbedtls/dtls/client/dtls_client.c | 518 ++-- .../freertos/sec/mbedtls/dtls/client/makefile | 11 +- .../sec/mbedtls/dtls/server/dtls_server.c | 616 ++-- .../freertos/sec/mbedtls/dtls/server/makefile | 10 +- .../freertos/sec/mbedtls/ssl/client2/makefile | 11 +- .../sec/mbedtls/ssl/client2/ssl_client2.c | 2586 ++++++++--------- .../freertos/sec/mbedtls/ssl/server2/makefile | 10 +- .../sec/mbedtls/ssl/server2/ssl_server2.c | 65 +- ...ARC-FreeRTOS-LwIP-support-to-mbedtls.patch | 92 +- ...ight-and-add-the-support-of-DW-timer.patch | 4 +- middleware/mbedtls/apply_embARC_patch.sh | 2 +- 12 files changed, 1966 insertions(+), 1961 deletions(-) diff --git a/device/peripheral/wifi/rs9113/rs9113_adapter.c b/device/peripheral/wifi/rs9113/rs9113_adapter.c index 9e7f13391..f1df39b27 100644 --- a/device/peripheral/wifi/rs9113/rs9113_adapter.c +++ b/device/peripheral/wifi/rs9113/rs9113_adapter.c @@ -40,7 +40,7 @@ #include "rs9113_adapter.h" #include "rsi_driver.h" -#define DBG_MORE +#define DBG_LESS #include "embARC_debug.h" #define RS9113_CHECK_EXP(EXPR, ERROR_CODE) CHECK_EXP(EXPR, ercd, ERROR_CODE, error_exit) diff --git a/example/freertos/sec/mbedtls/dtls/client/dtls_client.c b/example/freertos/sec/mbedtls/dtls/client/dtls_client.c index 86e2fd501..9b9c01c31 100644 --- a/example/freertos/sec/mbedtls/dtls/client/dtls_client.c +++ b/example/freertos/sec/mbedtls/dtls/client/dtls_client.c @@ -34,18 +34,18 @@ #endif #if !defined(MBEDTLS_SSL_CLI_C) || !defined(MBEDTLS_SSL_PROTO_DTLS) || \ - !defined(MBEDTLS_NET_C) || !defined(MBEDTLS_TIMING_C) || \ - !defined(MBEDTLS_ENTROPY_C) || !defined(MBEDTLS_CTR_DRBG_C) || \ - !defined(MBEDTLS_X509_CRT_PARSE_C) || !defined(MBEDTLS_RSA_C) || \ - !defined(MBEDTLS_CERTS_C) + !defined(MBEDTLS_NET_C) || !defined(MBEDTLS_TIMING_C) || \ + !defined(MBEDTLS_ENTROPY_C) || !defined(MBEDTLS_CTR_DRBG_C) || \ + !defined(MBEDTLS_X509_CRT_PARSE_C) || !defined(MBEDTLS_RSA_C) || \ + !defined(MBEDTLS_CERTS_C) int main( void ) { - mbedtls_printf( "MBEDTLS_SSL_CLI_C and/or MBEDTLS_SSL_PROTO_DTLS and/or " - "MBEDTLS_NET_C and/or MBEDTLS_TIMING_C and/or " - "MBEDTLS_ENTROPY_C and/or MBEDTLS_CTR_DRBG_C and/or " - "MBEDTLS_X509_CRT_PARSE_C and/or MBEDTLS_RSA_C and/or " - "MBEDTLS_CERTS_C and/or MBEDTLS_PEM_PARSE_C not defined.\n" ); - return( 0 ); + mbedtls_printf( "MBEDTLS_SSL_CLI_C and/or MBEDTLS_SSL_PROTO_DTLS and/or " + "MBEDTLS_NET_C and/or MBEDTLS_TIMING_C and/or " + "MBEDTLS_ENTROPY_C and/or MBEDTLS_CTR_DRBG_C and/or " + "MBEDTLS_X509_CRT_PARSE_C and/or MBEDTLS_RSA_C and/or " + "MBEDTLS_CERTS_C and/or MBEDTLS_PEM_PARSE_C not defined.\n" ); + return( 0 ); } #else @@ -70,281 +70,281 @@ int main( void ) #define DEBUG_LEVEL 0 +mbedtls_net_context server_fd; +mbedtls_entropy_context entropy; +mbedtls_ctr_drbg_context ctr_drbg; +mbedtls_ssl_context ssl; +mbedtls_ssl_config conf; +mbedtls_x509_crt cacert; +mbedtls_timing_delay_context timer; +unsigned char buf[1024]; + static void my_debug( void *ctx, int level, - const char *file, int line, - const char *str ) + const char *file, int line, + const char *str ) { - ((void) level); + ((void) level); - mbedtls_fprintf( (FILE *) ctx, "%s:%04d: %s", file, line, str ); - fflush( (FILE *) ctx ); + mbedtls_fprintf( (FILE *) ctx, "%s:%04d: %s", file, line, str ); + fflush( (FILE *) ctx ); } int main( int argc, char *argv[] ) { - int ret, len; - mbedtls_net_context server_fd; - uint32_t flags; - unsigned char buf[1024]; - const char *pers = "dtls_client"; - int retry_left = MAX_RETRY; - - mbedtls_entropy_context entropy; - mbedtls_ctr_drbg_context ctr_drbg; - mbedtls_ssl_context ssl; - mbedtls_ssl_config conf; - mbedtls_x509_crt cacert; - mbedtls_timing_delay_context timer; - - ((void) argc); - ((void) argv); + int ret, len; + uint32_t flags; + const char *pers = "dtls_client"; + int retry_left = MAX_RETRY; + + ((void) argc); + ((void) argv); #if defined(MBEDTLS_DEBUG_C) - mbedtls_debug_set_threshold( DEBUG_LEVEL ); + mbedtls_debug_set_threshold( DEBUG_LEVEL ); #endif - /* - * 0. Initialize the RNG and the session data - */ - mbedtls_net_init( &server_fd ); - mbedtls_ssl_init( &ssl ); - mbedtls_ssl_config_init( &conf ); - mbedtls_x509_crt_init( &cacert ); - mbedtls_ctr_drbg_init( &ctr_drbg ); - - mbedtls_printf( "\n . Seeding the random number generator..." ); - fflush( stdout ); - - mbedtls_entropy_init( &entropy ); - if( ( ret = mbedtls_ctr_drbg_seed( &ctr_drbg, mbedtls_entropy_func, &entropy, - (const unsigned char *) pers, - strlen( pers ) ) ) != 0 ) - { - mbedtls_printf( " failed\n ! mbedtls_ctr_drbg_seed returned %d\n", ret ); - goto exit; - } - - mbedtls_printf( " ok\n" ); - - /* - * 0. Load certificates - */ - mbedtls_printf( " . Loading the CA root certificate ..." ); - fflush( stdout ); - - ret = mbedtls_x509_crt_parse( &cacert, (const unsigned char *) mbedtls_test_cas_pem, - mbedtls_test_cas_pem_len ); - if( ret < 0 ) - { - mbedtls_printf( " failed\n ! mbedtls_x509_crt_parse returned -0x%x\n\n", -ret ); - goto exit; - } - - mbedtls_printf( " ok (%d skipped)\n", ret ); - - /* - * 1. Start the connection - */ - mbedtls_printf( " . Connecting to udp/%s/%s...", SERVER_NAME, SERVER_PORT ); - fflush( stdout ); - - if( ( ret = mbedtls_net_connect( &server_fd, SERVER_ADDR, - SERVER_PORT, MBEDTLS_NET_PROTO_UDP ) ) != 0 ) - { - mbedtls_printf( " failed\n ! mbedtls_net_connect returned %d\n\n", ret ); - goto exit; - } - - mbedtls_printf( " ok\n" ); - - /* - * 2. Setup stuff - */ - mbedtls_printf( " . Setting up the DTLS structure..." ); - fflush( stdout ); - - if( ( ret = mbedtls_ssl_config_defaults( &conf, - MBEDTLS_SSL_IS_CLIENT, - MBEDTLS_SSL_TRANSPORT_DATAGRAM, - MBEDTLS_SSL_PRESET_DEFAULT ) ) != 0 ) - { - mbedtls_printf( " failed\n ! mbedtls_ssl_config_defaults returned %d\n\n", ret ); - goto exit; - } - - /* OPTIONAL is usually a bad choice for security, but makes interop easier - * in this simplified example, in which the ca chain is hardcoded. - * Production code should set a proper ca chain and use REQUIRED. */ - mbedtls_ssl_conf_authmode( &conf, MBEDTLS_SSL_VERIFY_OPTIONAL ); - mbedtls_ssl_conf_ca_chain( &conf, &cacert, NULL ); - mbedtls_ssl_conf_rng( &conf, mbedtls_ctr_drbg_random, &ctr_drbg ); - mbedtls_ssl_conf_dbg( &conf, my_debug, stdout ); - - if( ( ret = mbedtls_ssl_setup( &ssl, &conf ) ) != 0 ) - { - mbedtls_printf( " failed\n ! mbedtls_ssl_setup returned %d\n\n", ret ); - goto exit; - } - - if( ( ret = mbedtls_ssl_set_hostname( &ssl, SERVER_NAME ) ) != 0 ) - { - mbedtls_printf( " failed\n ! mbedtls_ssl_set_hostname returned %d\n\n", ret ); - goto exit; - } - - mbedtls_ssl_set_bio( &ssl, &server_fd, - mbedtls_net_send, mbedtls_net_recv, mbedtls_net_recv_timeout ); - - mbedtls_ssl_set_timer_cb( &ssl, &timer, mbedtls_timing_set_delay, - mbedtls_timing_get_delay ); - - mbedtls_printf( " ok\n" ); - - /* - * 4. Handshake - */ - mbedtls_printf( " . Performing the SSL/TLS handshake..." ); - fflush( stdout ); - - do ret = mbedtls_ssl_handshake( &ssl ); - while( ret == MBEDTLS_ERR_SSL_WANT_READ || - ret == MBEDTLS_ERR_SSL_WANT_WRITE ); - - if( ret != 0 ) - { - mbedtls_printf( " failed\n ! mbedtls_ssl_handshake returned -0x%x\n\n", -ret ); - goto exit; - } - - mbedtls_printf( " ok\n" ); - - /* - * 5. Verify the server certificate - */ - mbedtls_printf( " . Verifying peer X.509 certificate..." ); - - /* In real life, we would have used MBEDTLS_SSL_VERIFY_REQUIRED so that the - * handshake would not succeed if the peer's cert is bad. Even if we used - * MBEDTLS_SSL_VERIFY_OPTIONAL, we would bail out here if ret != 0 */ - if( ( flags = mbedtls_ssl_get_verify_result( &ssl ) ) != 0 ) - { - char vrfy_buf[512]; - - mbedtls_printf( " failed\n" ); - - mbedtls_x509_crt_verify_info( vrfy_buf, sizeof( vrfy_buf ), " ! ", flags ); - - mbedtls_printf( "%s\n", vrfy_buf ); - } - else - mbedtls_printf( " ok\n" ); - - /* - * 6. Write the echo request - */ + /* + * 0. Initialize the RNG and the session data + */ + mbedtls_net_init( &server_fd ); + mbedtls_ssl_init( &ssl ); + mbedtls_ssl_config_init( &conf ); + mbedtls_x509_crt_init( &cacert ); + mbedtls_ctr_drbg_init( &ctr_drbg ); + + mbedtls_printf( "\n . Seeding the random number generator..." ); + fflush( stdout ); + + mbedtls_entropy_init( &entropy ); + if( ( ret = mbedtls_ctr_drbg_seed( &ctr_drbg, mbedtls_entropy_func, &entropy, + (const unsigned char *) pers, + strlen( pers ) ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ctr_drbg_seed returned %d\n", ret ); + goto exit; + } + + mbedtls_printf( " ok\n" ); + + /* + * 0. Load certificates + */ + mbedtls_printf( " . Loading the CA root certificate ..." ); + fflush( stdout ); + + ret = mbedtls_x509_crt_parse( &cacert, (const unsigned char *) mbedtls_test_cas_pem, + mbedtls_test_cas_pem_len ); + if( ret < 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_x509_crt_parse returned -0x%x\n\n", -ret ); + goto exit; + } + + mbedtls_printf( " ok (%d skipped)\n", ret ); + + /* + * 1. Start the connection + */ + mbedtls_printf( " . Connecting to udp/%s/%s...", SERVER_NAME, SERVER_PORT ); + fflush( stdout ); + + if( ( ret = mbedtls_net_connect( &server_fd, SERVER_ADDR, + SERVER_PORT, MBEDTLS_NET_PROTO_UDP ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_net_connect returned %d\n\n", ret ); + goto exit; + } + + mbedtls_printf( " ok\n" ); + + /* + * 2. Setup stuff + */ + mbedtls_printf( " . Setting up the DTLS structure..." ); + fflush( stdout ); + + if( ( ret = mbedtls_ssl_config_defaults( &conf, + MBEDTLS_SSL_IS_CLIENT, + MBEDTLS_SSL_TRANSPORT_DATAGRAM, + MBEDTLS_SSL_PRESET_DEFAULT ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_config_defaults returned %d\n\n", ret ); + goto exit; + } + + /* OPTIONAL is usually a bad choice for security, but makes interop easier + * in this simplified example, in which the ca chain is hardcoded. + * Production code should set a proper ca chain and use REQUIRED. */ + mbedtls_ssl_conf_authmode( &conf, MBEDTLS_SSL_VERIFY_OPTIONAL ); + mbedtls_ssl_conf_ca_chain( &conf, &cacert, NULL ); + mbedtls_ssl_conf_rng( &conf, mbedtls_ctr_drbg_random, &ctr_drbg ); + mbedtls_ssl_conf_dbg( &conf, my_debug, stdout ); + + if( ( ret = mbedtls_ssl_setup( &ssl, &conf ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_setup returned %d\n\n", ret ); + goto exit; + } + + if( ( ret = mbedtls_ssl_set_hostname( &ssl, SERVER_NAME ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_set_hostname returned %d\n\n", ret ); + goto exit; + } + + mbedtls_ssl_set_bio( &ssl, &server_fd, + mbedtls_net_send, mbedtls_net_recv, mbedtls_net_recv_timeout ); + + mbedtls_ssl_set_timer_cb( &ssl, &timer, mbedtls_timing_set_delay, + mbedtls_timing_get_delay ); + + mbedtls_printf( " ok\n" ); + + /* + * 4. Handshake + */ + mbedtls_printf( " . Performing the SSL/TLS handshake..." ); + fflush( stdout ); + + do ret = mbedtls_ssl_handshake( &ssl ); + while( ret == MBEDTLS_ERR_SSL_WANT_READ || + ret == MBEDTLS_ERR_SSL_WANT_WRITE ); + + if( ret != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_handshake returned -0x%x\n\n", -ret ); + goto exit; + } + + mbedtls_printf( " ok\n" ); + + /* + * 5. Verify the server certificate + */ + mbedtls_printf( " . Verifying peer X.509 certificate..." ); + + /* In real life, we would have used MBEDTLS_SSL_VERIFY_REQUIRED so that the + * handshake would not succeed if the peer's cert is bad. Even if we used + * MBEDTLS_SSL_VERIFY_OPTIONAL, we would bail out here if ret != 0 */ + if( ( flags = mbedtls_ssl_get_verify_result( &ssl ) ) != 0 ) + { + char vrfy_buf[512]; + + mbedtls_printf( " failed\n" ); + + mbedtls_x509_crt_verify_info( vrfy_buf, sizeof( vrfy_buf ), " ! ", flags ); + + mbedtls_printf( "%s\n", vrfy_buf ); + } + else + mbedtls_printf( " ok\n" ); + + /* + * 6. Write the echo request + */ send_request: - mbedtls_printf( " > Write to server:" ); - fflush( stdout ); - - len = sizeof( MESSAGE ) - 1; - - do ret = mbedtls_ssl_write( &ssl, (unsigned char *) MESSAGE, len ); - while( ret == MBEDTLS_ERR_SSL_WANT_READ || - ret == MBEDTLS_ERR_SSL_WANT_WRITE ); - - if( ret < 0 ) - { - mbedtls_printf( " failed\n ! mbedtls_ssl_write returned %d\n\n", ret ); - goto exit; - } - - len = ret; - mbedtls_printf( " %d bytes written\n\n%s\n\n", len, MESSAGE ); - - /* - * 7. Read the echo response - */ - mbedtls_printf( " < Read from server:" ); - fflush( stdout ); - - len = sizeof( buf ) - 1; - memset( buf, 0, sizeof( buf ) ); - - do ret = mbedtls_ssl_read( &ssl, buf, len ); - while( ret == MBEDTLS_ERR_SSL_WANT_READ || - ret == MBEDTLS_ERR_SSL_WANT_WRITE ); - - if( ret <= 0 ) - { - switch( ret ) - { - case MBEDTLS_ERR_SSL_TIMEOUT: - mbedtls_printf( " timeout\n\n" ); - if( retry_left-- > 0 ) - goto send_request; - goto exit; - - case MBEDTLS_ERR_SSL_PEER_CLOSE_NOTIFY: - mbedtls_printf( " connection was closed gracefully\n" ); - ret = 0; - goto close_notify; - - default: - mbedtls_printf( " mbedtls_ssl_read returned -0x%x\n\n", -ret ); - goto exit; - } - } - - len = ret; - mbedtls_printf( " %d bytes read\n\n%s\n\n", len, buf ); - - /* - * 8. Done, cleanly close the connection - */ + mbedtls_printf( " > Write to server:" ); + fflush( stdout ); + + len = sizeof( MESSAGE ) - 1; + + do ret = mbedtls_ssl_write( &ssl, (unsigned char *) MESSAGE, len ); + while( ret == MBEDTLS_ERR_SSL_WANT_READ || + ret == MBEDTLS_ERR_SSL_WANT_WRITE ); + + if( ret < 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_write returned %d\n\n", ret ); + goto exit; + } + + len = ret; + mbedtls_printf( " %d bytes written\n\n%s\n\n", len, MESSAGE ); + + /* + * 7. Read the echo response + */ + mbedtls_printf( " < Read from server:" ); + fflush( stdout ); + + len = sizeof( buf ) - 1; + memset( buf, 0, sizeof( buf ) ); + + do ret = mbedtls_ssl_read( &ssl, buf, len ); + while( ret == MBEDTLS_ERR_SSL_WANT_READ || + ret == MBEDTLS_ERR_SSL_WANT_WRITE ); + + if( ret <= 0 ) + { + switch( ret ) + { + case MBEDTLS_ERR_SSL_TIMEOUT: + mbedtls_printf( " timeout\n\n" ); + if( retry_left-- > 0 ) + goto send_request; + goto exit; + + case MBEDTLS_ERR_SSL_PEER_CLOSE_NOTIFY: + mbedtls_printf( " connection was closed gracefully\n" ); + ret = 0; + goto close_notify; + + default: + mbedtls_printf( " mbedtls_ssl_read returned -0x%x\n\n", -ret ); + goto exit; + } + } + + len = ret; + mbedtls_printf( " %d bytes read\n\n%s\n\n", len, buf ); + + /* + * 8. Done, cleanly close the connection + */ close_notify: - mbedtls_printf( " . Closing the connection..." ); + mbedtls_printf( " . Closing the connection..." ); - /* No error checking, the connection might be closed already */ - do ret = mbedtls_ssl_close_notify( &ssl ); - while( ret == MBEDTLS_ERR_SSL_WANT_WRITE ); - ret = 0; + /* No error checking, the connection might be closed already */ + do ret = mbedtls_ssl_close_notify( &ssl ); + while( ret == MBEDTLS_ERR_SSL_WANT_WRITE ); + ret = 0; - mbedtls_printf( " done\n" ); + mbedtls_printf( " done\n" ); - /* - * 9. Final clean-ups and exit - */ + /* + * 9. Final clean-ups and exit + */ exit: #ifdef MBEDTLS_ERROR_C - if( ret != 0 ) - { - char error_buf[100]; - mbedtls_strerror( ret, error_buf, 100 ); - mbedtls_printf( "Last error was: %d - %s\n\n", ret, error_buf ); - } + if( ret != 0 ) + { + char error_buf[100]; + mbedtls_strerror( ret, error_buf, 100 ); + mbedtls_printf( "Last error was: %d - %s\n\n", ret, error_buf ); + } #endif - mbedtls_net_free( &server_fd ); + mbedtls_net_free( &server_fd ); - mbedtls_x509_crt_free( &cacert ); - mbedtls_ssl_free( &ssl ); - mbedtls_ssl_config_free( &conf ); - mbedtls_ctr_drbg_free( &ctr_drbg ); - mbedtls_entropy_free( &entropy ); + mbedtls_x509_crt_free( &cacert ); + mbedtls_ssl_free( &ssl ); + mbedtls_ssl_config_free( &conf ); + mbedtls_ctr_drbg_free( &ctr_drbg ); + mbedtls_entropy_free( &entropy ); #if defined(_WIN32) - mbedtls_printf( " + Press Enter to exit this program.\n" ); - fflush( stdout ); getchar(); + mbedtls_printf( " + Press Enter to exit this program.\n" ); + fflush( stdout ); getchar(); #endif - /* Shell can not handle large exit numbers -> 1 for errors */ - if( ret < 0 ) - ret = 1; + /* Shell can not handle large exit numbers -> 1 for errors */ + if( ret < 0 ) + ret = 1; - return( ret ); + return( ret ); } #endif /* MBEDTLS_SSL_CLI_C && MBEDTLS_SSL_PROTO_DTLS && MBEDTLS_NET_C && - MBEDTLD_TIMING_C && MBEDTLS_ENTROPY_C && MBEDTLS_CTR_DRBG_C && - MBEDTLS_X509_CRT_PARSE_C && MBEDTLS_RSA_C && MBEDTLS_CERTS_C && - MBEDTLS_PEM_PARSE_C */ + MBEDTLD_TIMING_C && MBEDTLS_ENTROPY_C && MBEDTLS_CTR_DRBG_C && + MBEDTLS_X509_CRT_PARSE_C && MBEDTLS_RSA_C && MBEDTLS_CERTS_C && + MBEDTLS_PEM_PARSE_C */ diff --git a/example/freertos/sec/mbedtls/dtls/client/makefile b/example/freertos/sec/mbedtls/dtls/client/makefile index 25ec75b01..f5bf02431 100644 --- a/example/freertos/sec/mbedtls/dtls/client/makefile +++ b/example/freertos/sec/mbedtls/dtls/client/makefile @@ -6,14 +6,19 @@ BOARD ?= emsk ifeq ($(BOARD), emsdp) EXT_DEV_LIST += wifi/rs9113 else -EXT_DEV_LIST += wifi/mrf24g +EXT_DEV_LIST += wifi/mrf24g sensor/temperature/adt7420 endif # Heap Size Settings -HEAPSZ ?= 8192 +HEAPSZ ?= 1024*96 STACKSZ ?= 2048 -APPL_DEFINES = -DMBEDTLS_CONFIG_FILE=\"mbedtls_config.h\" +APPL_DEFINES += -DMBEDTLS_CONFIG_FILE=\"mbedtls_config.h\" \ + -DTASK_STACK_SIZE_WIFI=1024 \ + -DTASK_STACK_SIZE_NTSHELL=4096 \ + -DNTSHELL_USE_CMDS_ARC=0 \ + -DNTSHELL_USE_CMDS_PERIPHERAL=0 + # # root dir of embARC diff --git a/example/freertos/sec/mbedtls/dtls/server/dtls_server.c b/example/freertos/sec/mbedtls/dtls/server/dtls_server.c index df0fc780a..0e20d1c89 100644 --- a/example/freertos/sec/mbedtls/dtls/server/dtls_server.c +++ b/example/freertos/sec/mbedtls/dtls/server/dtls_server.c @@ -34,21 +34,21 @@ #endif #if !defined(MBEDTLS_SSL_SRV_C) || !defined(MBEDTLS_SSL_PROTO_DTLS) || \ - !defined(MBEDTLS_SSL_COOKIE_C) || !defined(MBEDTLS_NET_C) || \ - !defined(MBEDTLS_ENTROPY_C) || !defined(MBEDTLS_CTR_DRBG_C) || \ - !defined(MBEDTLS_X509_CRT_PARSE_C) || !defined(MBEDTLS_RSA_C) || \ - !defined(MBEDTLS_CERTS_C) || !defined(MBEDTLS_PEM_PARSE_C) || \ - !defined(MBEDTLS_TIMING_C) + !defined(MBEDTLS_SSL_COOKIE_C) || !defined(MBEDTLS_NET_C) || \ + !defined(MBEDTLS_ENTROPY_C) || !defined(MBEDTLS_CTR_DRBG_C) || \ + !defined(MBEDTLS_X509_CRT_PARSE_C) || !defined(MBEDTLS_RSA_C) || \ + !defined(MBEDTLS_CERTS_C) || !defined(MBEDTLS_PEM_PARSE_C) || \ + !defined(MBEDTLS_TIMING_C) int main( void ) { - printf( "MBEDTLS_SSL_SRV_C and/or MBEDTLS_SSL_PROTO_DTLS and/or " - "MBEDTLS_SSL_COOKIE_C and/or MBEDTLS_NET_C and/or " - "MBEDTLS_ENTROPY_C and/or MBEDTLS_CTR_DRBG_C and/or " - "MBEDTLS_X509_CRT_PARSE_C and/or MBEDTLS_RSA_C and/or " - "MBEDTLS_CERTS_C and/or MBEDTLS_PEM_PARSE_C and/or " - "MBEDTLS_TIMING_C not defined.\n" ); - return( 0 ); + printf( "MBEDTLS_SSL_SRV_C and/or MBEDTLS_SSL_PROTO_DTLS and/or " + "MBEDTLS_SSL_COOKIE_C and/or MBEDTLS_NET_C and/or " + "MBEDTLS_ENTROPY_C and/or MBEDTLS_CTR_DRBG_C and/or " + "MBEDTLS_X509_CRT_PARSE_C and/or MBEDTLS_RSA_C and/or " + "MBEDTLS_CERTS_C and/or MBEDTLS_PEM_PARSE_C and/or " + "MBEDTLS_TIMING_C not defined.\n" ); + return( 0 ); } #else @@ -78,347 +78,347 @@ int main( void ) #define READ_TIMEOUT_MS 10000 /* 5 seconds */ #define DEBUG_LEVEL 0 +mbedtls_net_context listen_fd, client_fd; +mbedtls_ssl_cookie_ctx cookie_ctx; +mbedtls_entropy_context entropy; +mbedtls_ctr_drbg_context ctr_drbg; +mbedtls_ssl_context ssl; +mbedtls_ssl_config conf; +mbedtls_x509_crt srvcert; +mbedtls_pk_context pkey; +mbedtls_timing_delay_context timer; +#if defined(MBEDTLS_SSL_CACHE_C) +mbedtls_ssl_cache_context cache; +#endif +unsigned char buf[1024]; + static void my_debug( void *ctx, int level, - const char *file, int line, - const char *str ) + const char *file, int line, + const char *str ) { - ((void) level); + ((void) level); - mbedtls_fprintf( (FILE *) ctx, "%s:%04d: %s", file, line, str ); - fflush( (FILE *) ctx ); + mbedtls_fprintf( (FILE *) ctx, "%s:%04d: %s", file, line, str ); + fflush( (FILE *) ctx ); } int main( void ) { - int ret, len; - mbedtls_net_context listen_fd, client_fd; - unsigned char buf[1024]; - const char *pers = "dtls_server"; - unsigned char client_ip[16] = { 0 }; - size_t cliip_len; - mbedtls_ssl_cookie_ctx cookie_ctx; - - mbedtls_entropy_context entropy; - mbedtls_ctr_drbg_context ctr_drbg; - mbedtls_ssl_context ssl; - mbedtls_ssl_config conf; - mbedtls_x509_crt srvcert; - mbedtls_pk_context pkey; - mbedtls_timing_delay_context timer; -#if defined(MBEDTLS_SSL_CACHE_C) - mbedtls_ssl_cache_context cache; -#endif - - mbedtls_net_init( &listen_fd ); - mbedtls_net_init( &client_fd ); - mbedtls_ssl_init( &ssl ); - mbedtls_ssl_config_init( &conf ); - mbedtls_ssl_cookie_init( &cookie_ctx ); + int ret, len; + const char *pers = "dtls_server"; + unsigned char client_ip[16] = { 0 }; + size_t cliip_len; + + mbedtls_net_init( &listen_fd ); + mbedtls_net_init( &client_fd ); + mbedtls_ssl_init( &ssl ); + mbedtls_ssl_config_init( &conf ); + mbedtls_ssl_cookie_init( &cookie_ctx ); #if defined(MBEDTLS_SSL_CACHE_C) - mbedtls_ssl_cache_init( &cache ); + mbedtls_ssl_cache_init( &cache ); #endif - mbedtls_x509_crt_init( &srvcert ); - mbedtls_pk_init( &pkey ); - mbedtls_entropy_init( &entropy ); - mbedtls_ctr_drbg_init( &ctr_drbg ); + mbedtls_x509_crt_init( &srvcert ); + mbedtls_pk_init( &pkey ); + mbedtls_entropy_init( &entropy ); + mbedtls_ctr_drbg_init( &ctr_drbg ); #if defined(MBEDTLS_DEBUG_C) - mbedtls_debug_set_threshold( DEBUG_LEVEL ); + mbedtls_debug_set_threshold( DEBUG_LEVEL ); #endif - /* - * 1. Load the certificates and private RSA key - */ - printf( "\n . Loading the server cert. and key..." ); - fflush( stdout ); - - /* - * This demonstration program uses embedded test certificates. - * Instead, you may want to use mbedtls_x509_crt_parse_file() to read the - * server and CA certificates, as well as mbedtls_pk_parse_keyfile(). - */ - ret = mbedtls_x509_crt_parse( &srvcert, (const unsigned char *) mbedtls_test_srv_crt, - mbedtls_test_srv_crt_len ); - if( ret != 0 ) - { - printf( " failed\n ! mbedtls_x509_crt_parse returned %d\n\n", ret ); - goto exit; - } - - ret = mbedtls_x509_crt_parse( &srvcert, (const unsigned char *) mbedtls_test_cas_pem, - mbedtls_test_cas_pem_len ); - if( ret != 0 ) - { - printf( " failed\n ! mbedtls_x509_crt_parse returned %d\n\n", ret ); - goto exit; - } - - ret = mbedtls_pk_parse_key( &pkey, (const unsigned char *) mbedtls_test_srv_key, - mbedtls_test_srv_key_len, NULL, 0 ); - if( ret != 0 ) - { - printf( " failed\n ! mbedtls_pk_parse_key returned %d\n\n", ret ); - goto exit; - } - - printf( " ok\n" ); - - /* - * 2. Setup the "listening" UDP socket - */ - printf( " . Bind on udp/*/4433 ..." ); - fflush( stdout ); - - if( ( ret = mbedtls_net_bind( &listen_fd, NULL, "4433", MBEDTLS_NET_PROTO_UDP ) ) != 0 ) - { - printf( " failed\n ! mbedtls_net_bind returned %d\n\n", ret ); - goto exit; - } - - printf( " ok\n" ); - - /* - * 3. Seed the RNG - */ - printf( " . Seeding the random number generator..." ); - fflush( stdout ); - - if( ( ret = mbedtls_ctr_drbg_seed( &ctr_drbg, mbedtls_entropy_func, &entropy, - (const unsigned char *) pers, - strlen( pers ) ) ) != 0 ) - { - printf( " failed\n ! mbedtls_ctr_drbg_seed returned %d\n", ret ); - goto exit; - } - - printf( " ok\n" ); - - /* - * 4. Setup stuff - */ - printf( " . Setting up the DTLS data..." ); - fflush( stdout ); - - if( ( ret = mbedtls_ssl_config_defaults( &conf, - MBEDTLS_SSL_IS_SERVER, - MBEDTLS_SSL_TRANSPORT_DATAGRAM, - MBEDTLS_SSL_PRESET_DEFAULT ) ) != 0 ) - { - mbedtls_printf( " failed\n ! mbedtls_ssl_config_defaults returned %d\n\n", ret ); - goto exit; - } - - mbedtls_ssl_conf_rng( &conf, mbedtls_ctr_drbg_random, &ctr_drbg ); - mbedtls_ssl_conf_dbg( &conf, my_debug, stdout ); + /* + * 1. Load the certificates and private RSA key + */ + printf( "\n . Loading the server cert. and key..." ); + fflush( stdout ); + + /* + * This demonstration program uses embedded test certificates. + * Instead, you may want to use mbedtls_x509_crt_parse_file() to read the + * server and CA certificates, as well as mbedtls_pk_parse_keyfile(). + */ + ret = mbedtls_x509_crt_parse( &srvcert, (const unsigned char *) mbedtls_test_srv_crt, + mbedtls_test_srv_crt_len ); + if( ret != 0 ) + { + printf( " failed\n ! mbedtls_x509_crt_parse returned %d\n\n", ret ); + goto exit; + } + + ret = mbedtls_x509_crt_parse( &srvcert, (const unsigned char *) mbedtls_test_cas_pem, + mbedtls_test_cas_pem_len ); + if( ret != 0 ) + { + printf( " failed\n ! mbedtls_x509_crt_parse returned %d\n\n", ret ); + goto exit; + } + + ret = mbedtls_pk_parse_key( &pkey, (const unsigned char *) mbedtls_test_srv_key, + mbedtls_test_srv_key_len, NULL, 0 ); + if( ret != 0 ) + { + printf( " failed\n ! mbedtls_pk_parse_key returned %d\n\n", ret ); + goto exit; + } + + printf( " ok\n" ); + + /* + * 2. Setup the "listening" UDP socket + */ + printf( " . Bind on udp/*/4433 ..." ); + fflush( stdout ); + + if( ( ret = mbedtls_net_bind( &listen_fd, NULL, "4433", MBEDTLS_NET_PROTO_UDP ) ) != 0 ) + { + printf( " failed\n ! mbedtls_net_bind returned %d\n\n", ret ); + goto exit; + } + + printf( " ok\n" ); + + /* + * 3. Seed the RNG + */ + printf( " . Seeding the random number generator..." ); + fflush( stdout ); + + if( ( ret = mbedtls_ctr_drbg_seed( &ctr_drbg, mbedtls_entropy_func, &entropy, + (const unsigned char *) pers, + strlen( pers ) ) ) != 0 ) + { + printf( " failed\n ! mbedtls_ctr_drbg_seed returned %d\n", ret ); + goto exit; + } + + printf( " ok\n" ); + + /* + * 4. Setup stuff + */ + printf( " . Setting up the DTLS data..." ); + fflush( stdout ); + + if( ( ret = mbedtls_ssl_config_defaults( &conf, + MBEDTLS_SSL_IS_SERVER, + MBEDTLS_SSL_TRANSPORT_DATAGRAM, + MBEDTLS_SSL_PRESET_DEFAULT ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_config_defaults returned %d\n\n", ret ); + goto exit; + } + + mbedtls_ssl_conf_rng( &conf, mbedtls_ctr_drbg_random, &ctr_drbg ); + mbedtls_ssl_conf_dbg( &conf, my_debug, stdout ); #if defined(MBEDTLS_SSL_CACHE_C) - mbedtls_ssl_conf_session_cache( &conf, &cache, - mbedtls_ssl_cache_get, - mbedtls_ssl_cache_set ); + mbedtls_ssl_conf_session_cache( &conf, &cache, + mbedtls_ssl_cache_get, + mbedtls_ssl_cache_set ); #endif - mbedtls_ssl_conf_ca_chain( &conf, srvcert.next, NULL ); + mbedtls_ssl_conf_ca_chain( &conf, srvcert.next, NULL ); if( ( ret = mbedtls_ssl_conf_own_cert( &conf, &srvcert, &pkey ) ) != 0 ) - { - printf( " failed\n ! mbedtls_ssl_conf_own_cert returned %d\n\n", ret ); - goto exit; - } + { + printf( " failed\n ! mbedtls_ssl_conf_own_cert returned %d\n\n", ret ); + goto exit; + } - if( ( ret = mbedtls_ssl_cookie_setup( &cookie_ctx, - mbedtls_ctr_drbg_random, &ctr_drbg ) ) != 0 ) - { - printf( " failed\n ! mbedtls_ssl_cookie_setup returned %d\n\n", ret ); - goto exit; - } + if( ( ret = mbedtls_ssl_cookie_setup( &cookie_ctx, + mbedtls_ctr_drbg_random, &ctr_drbg ) ) != 0 ) + { + printf( " failed\n ! mbedtls_ssl_cookie_setup returned %d\n\n", ret ); + goto exit; + } - mbedtls_ssl_conf_dtls_cookies( &conf, mbedtls_ssl_cookie_write, mbedtls_ssl_cookie_check, - &cookie_ctx ); + mbedtls_ssl_conf_dtls_cookies( &conf, mbedtls_ssl_cookie_write, mbedtls_ssl_cookie_check, + &cookie_ctx ); - if( ( ret = mbedtls_ssl_setup( &ssl, &conf ) ) != 0 ) - { - printf( " failed\n ! mbedtls_ssl_setup returned %d\n\n", ret ); - goto exit; - } + if( ( ret = mbedtls_ssl_setup( &ssl, &conf ) ) != 0 ) + { + printf( " failed\n ! mbedtls_ssl_setup returned %d\n\n", ret ); + goto exit; + } - mbedtls_ssl_set_timer_cb( &ssl, &timer, mbedtls_timing_set_delay, - mbedtls_timing_get_delay ); + mbedtls_ssl_set_timer_cb( &ssl, &timer, mbedtls_timing_set_delay, + mbedtls_timing_get_delay ); - printf( " ok\n" ); + printf( " ok\n" ); reset: #ifdef MBEDTLS_ERROR_C - if( ret != 0 ) - { - char error_buf[100]; - mbedtls_strerror( ret, error_buf, 100 ); - printf("Last error was: %d - %s\n\n", ret, error_buf ); - } + if( ret != 0 ) + { + char error_buf[100]; + mbedtls_strerror( ret, error_buf, 100 ); + printf("Last error was: %d - %s\n\n", ret, error_buf ); + } #endif - mbedtls_net_free( &client_fd ); - - mbedtls_ssl_session_reset( &ssl ); - - /* - * 3. Wait until a client connects - */ - printf( " . Waiting for a remote connection ..." ); - fflush( stdout ); - - if( ( ret = mbedtls_net_accept( &listen_fd, &client_fd, - client_ip, sizeof( client_ip ), &cliip_len ) ) != 0 ) - { - printf( " failed\n ! mbedtls_net_accept returned %d\n\n", ret ); - goto exit; - } - - /* For HelloVerifyRequest cookies */ - if( ( ret = mbedtls_ssl_set_client_transport_id( &ssl, - client_ip, cliip_len ) ) != 0 ) - { - printf( " failed\n ! " - "mbedtls_ssl_set_client_transport_id() returned -0x%x\n\n", -ret ); - goto exit; - } - - mbedtls_ssl_set_bio( &ssl, &client_fd, - mbedtls_net_send, mbedtls_net_recv, mbedtls_net_recv_timeout ); - - printf( " ok\n" ); - - /* - * 5. Handshake - */ - printf( " . Performing the DTLS handshake..." ); - fflush( stdout ); - - do ret = mbedtls_ssl_handshake( &ssl ); - while( ret == MBEDTLS_ERR_SSL_WANT_READ || - ret == MBEDTLS_ERR_SSL_WANT_WRITE ); - - if( ret == MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED ) - { - printf( " hello verification requested\n" ); - ret = 0; - goto reset; - } - else if( ret != 0 ) - { - printf( " failed\n ! mbedtls_ssl_handshake returned -0x%x\n\n", -ret ); - goto reset; - } - - printf( " ok\n" ); - - /* - * 6. Read the echo Request - */ - printf( " < Read from client:" ); - fflush( stdout ); - - len = sizeof( buf ) - 1; - memset( buf, 0, sizeof( buf ) ); - - do ret = mbedtls_ssl_read( &ssl, buf, len ); - while( ret == MBEDTLS_ERR_SSL_WANT_READ || - ret == MBEDTLS_ERR_SSL_WANT_WRITE ); - - if( ret <= 0 ) - { - switch( ret ) - { - case MBEDTLS_ERR_SSL_TIMEOUT: - printf( " timeout\n\n" ); - goto reset; - - case MBEDTLS_ERR_SSL_PEER_CLOSE_NOTIFY: - printf( " connection was closed gracefully\n" ); - ret = 0; - goto close_notify; - - default: - printf( " mbedtls_ssl_read returned -0x%x\n\n", -ret ); - goto reset; - } - } - - len = ret; - printf( " %d bytes read\n\n%s\n\n", len, buf ); - - /* - * 7. Write the 200 Response - */ - printf( " > Write to client:" ); - fflush( stdout ); - - do ret = mbedtls_ssl_write( &ssl, buf, len ); - while( ret == MBEDTLS_ERR_SSL_WANT_READ || - ret == MBEDTLS_ERR_SSL_WANT_WRITE ); - - if( ret < 0 ) - { - printf( " failed\n ! mbedtls_ssl_write returned %d\n\n", ret ); - goto exit; - } - - len = ret; - printf( " %d bytes written\n\n%s\n\n", len, buf ); - - /* - * 8. Done, cleanly close the connection - */ + mbedtls_net_free( &client_fd ); + + mbedtls_ssl_session_reset( &ssl ); + + /* + * 3. Wait until a client connects + */ + printf( " . Waiting for a remote connection ..." ); + fflush( stdout ); + + if( ( ret = mbedtls_net_accept( &listen_fd, &client_fd, + client_ip, sizeof( client_ip ), &cliip_len ) ) != 0 ) + { + printf( " failed\n ! mbedtls_net_accept returned %d\n\n", ret ); + goto exit; + } + + /* For HelloVerifyRequest cookies */ + if( ( ret = mbedtls_ssl_set_client_transport_id( &ssl, + client_ip, cliip_len ) ) != 0 ) + { + printf( " failed\n ! " + "mbedtls_ssl_set_client_transport_id() returned -0x%x\n\n", -ret ); + goto exit; + } + + mbedtls_ssl_set_bio( &ssl, &client_fd, + mbedtls_net_send, mbedtls_net_recv, mbedtls_net_recv_timeout ); + + printf( " ok\n" ); + + /* + * 5. Handshake + */ + printf( " . Performing the DTLS handshake..." ); + fflush( stdout ); + + do ret = mbedtls_ssl_handshake( &ssl ); + while( ret == MBEDTLS_ERR_SSL_WANT_READ || + ret == MBEDTLS_ERR_SSL_WANT_WRITE ); + + if( ret == MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED ) + { + printf( " hello verification requested\n" ); + ret = 0; + goto reset; + } + else if( ret != 0 ) + { + printf( " failed\n ! mbedtls_ssl_handshake returned -0x%x\n\n", -ret ); + goto reset; + } + + printf( " ok\n" ); + + /* + * 6. Read the echo Request + */ + printf( " < Read from client:" ); + fflush( stdout ); + + len = sizeof( buf ) - 1; + memset( buf, 0, sizeof( buf ) ); + + do ret = mbedtls_ssl_read( &ssl, buf, len ); + while( ret == MBEDTLS_ERR_SSL_WANT_READ || + ret == MBEDTLS_ERR_SSL_WANT_WRITE ); + + if( ret <= 0 ) + { + switch( ret ) + { + case MBEDTLS_ERR_SSL_TIMEOUT: + printf( " timeout\n\n" ); + goto reset; + + case MBEDTLS_ERR_SSL_PEER_CLOSE_NOTIFY: + printf( " connection was closed gracefully\n" ); + ret = 0; + goto close_notify; + + default: + printf( " mbedtls_ssl_read returned -0x%x\n\n", -ret ); + goto reset; + } + } + + len = ret; + printf( " %d bytes read\n\n%s\n\n", len, buf ); + + /* + * 7. Write the 200 Response + */ + printf( " > Write to client:" ); + fflush( stdout ); + + do ret = mbedtls_ssl_write( &ssl, buf, len ); + while( ret == MBEDTLS_ERR_SSL_WANT_READ || + ret == MBEDTLS_ERR_SSL_WANT_WRITE ); + + if( ret < 0 ) + { + printf( " failed\n ! mbedtls_ssl_write returned %d\n\n", ret ); + goto exit; + } + + len = ret; + printf( " %d bytes written\n\n%s\n\n", len, buf ); + + /* + * 8. Done, cleanly close the connection + */ close_notify: - printf( " . Closing the connection..." ); + printf( " . Closing the connection..." ); - /* No error checking, the connection might be closed already */ - do ret = mbedtls_ssl_close_notify( &ssl ); - while( ret == MBEDTLS_ERR_SSL_WANT_WRITE ); - ret = 0; + /* No error checking, the connection might be closed already */ + do ret = mbedtls_ssl_close_notify( &ssl ); + while( ret == MBEDTLS_ERR_SSL_WANT_WRITE ); + ret = 0; - printf( " done\n" ); + printf( " done\n" ); - goto reset; + goto reset; - /* - * Final clean-ups and exit - */ + /* + * Final clean-ups and exit + */ exit: #ifdef MBEDTLS_ERROR_C - if( ret != 0 ) - { - char error_buf[100]; - mbedtls_strerror( ret, error_buf, 100 ); - printf( "Last error was: %d - %s\n\n", ret, error_buf ); - } + if( ret != 0 ) + { + char error_buf[100]; + mbedtls_strerror( ret, error_buf, 100 ); + printf( "Last error was: %d - %s\n\n", ret, error_buf ); + } #endif - mbedtls_net_free( &client_fd ); - mbedtls_net_free( &listen_fd ); + mbedtls_net_free( &client_fd ); + mbedtls_net_free( &listen_fd ); - mbedtls_x509_crt_free( &srvcert ); - mbedtls_pk_free( &pkey ); - mbedtls_ssl_free( &ssl ); - mbedtls_ssl_config_free( &conf ); - mbedtls_ssl_cookie_free( &cookie_ctx ); + mbedtls_x509_crt_free( &srvcert ); + mbedtls_pk_free( &pkey ); + mbedtls_ssl_free( &ssl ); + mbedtls_ssl_config_free( &conf ); + mbedtls_ssl_cookie_free( &cookie_ctx ); #if defined(MBEDTLS_SSL_CACHE_C) - mbedtls_ssl_cache_free( &cache ); + mbedtls_ssl_cache_free( &cache ); #endif - mbedtls_ctr_drbg_free( &ctr_drbg ); - mbedtls_entropy_free( &entropy ); + mbedtls_ctr_drbg_free( &ctr_drbg ); + mbedtls_entropy_free( &entropy ); #if defined(_WIN32) - printf( " Press Enter to exit this program.\n" ); - fflush( stdout ); getchar(); + printf( " Press Enter to exit this program.\n" ); + fflush( stdout ); getchar(); #endif - /* Shell can not handle large exit numbers -> 1 for errors */ - if( ret < 0 ) - ret = 1; + /* Shell can not handle large exit numbers -> 1 for errors */ + if( ret < 0 ) + ret = 1; - return( ret ); + return( ret ); } #endif /* MBEDTLS_SSL_SRV_C && MBEDTLS_SSL_PROTO_DTLS && - MBEDTLS_SSL_COOKIE_C && MBEDTLS_NET_C && MBEDTLS_ENTROPY_C && - MBEDTLS_CTR_DRBG_C && MBEDTLS_X509_CRT_PARSE_C && MBEDTLS_RSA_C - && MBEDTLS_CERTS_C && MBEDTLS_PEM_PARSE_C && MBEDTLS_TIMING_C */ + MBEDTLS_SSL_COOKIE_C && MBEDTLS_NET_C && MBEDTLS_ENTROPY_C && + MBEDTLS_CTR_DRBG_C && MBEDTLS_X509_CRT_PARSE_C && MBEDTLS_RSA_C + && MBEDTLS_CERTS_C && MBEDTLS_PEM_PARSE_C && MBEDTLS_TIMING_C */ diff --git a/example/freertos/sec/mbedtls/dtls/server/makefile b/example/freertos/sec/mbedtls/dtls/server/makefile index 6d60e2a4d..0797cbe81 100644 --- a/example/freertos/sec/mbedtls/dtls/server/makefile +++ b/example/freertos/sec/mbedtls/dtls/server/makefile @@ -6,14 +6,18 @@ BOARD ?= emsk ifeq ($(BOARD), emsdp) EXT_DEV_LIST += wifi/rs9113 else -EXT_DEV_LIST += wifi/mrf24g +EXT_DEV_LIST += wifi/mrf24g sensor/temperature/adt7420 endif # Heap Size Settings -HEAPSZ ?= 8192 +HEAPSZ ?= 1024*96 STACKSZ ?= 2048 -APPL_DEFINES = -DMBEDTLS_CONFIG_FILE=\"mbedtls_config.h\" +APPL_DEFINES += -DMBEDTLS_CONFIG_FILE=\"mbedtls_config.h\" \ + -DTASK_STACK_SIZE_WIFI=1024 \ + -DTASK_STACK_SIZE_NTSHELL=4096 \ + -DNTSHELL_USE_CMDS_ARC=0 \ + -DNTSHELL_USE_CMDS_PERIPHERAL=0 # # root dir of embARC diff --git a/example/freertos/sec/mbedtls/ssl/client2/makefile b/example/freertos/sec/mbedtls/ssl/client2/makefile index 4324a87c4..84579de11 100644 --- a/example/freertos/sec/mbedtls/ssl/client2/makefile +++ b/example/freertos/sec/mbedtls/ssl/client2/makefile @@ -6,15 +6,18 @@ BOARD ?= emsk ifeq ($(BOARD), emsdp) EXT_DEV_LIST += wifi/rs9113 else -EXT_DEV_LIST += wifi/mrf24g +EXT_DEV_LIST += wifi/mrf24g sensor/temperature/adt7420 endif # Heap Size Settings -HEAPSZ ?= 8192 +HEAPSZ ?= 1024*96 STACKSZ ?= 2048 -APPL_DEFINES = -DNTCONF_EDITOR_MAXLEN=256 -DMBEDTLS_CONFIG_FILE=\"mbedtls_config.h\" - +APPL_DEFINES += -DNTCONF_EDITOR_MAXLEN=256 -DMBEDTLS_CONFIG_FILE=\"mbedtls_config.h\" \ + -DTASK_STACK_SIZE_WIFI=1024 \ + -DTASK_STACK_SIZE_NTSHELL=4096 \ + -DNTSHELL_USE_CMDS_ARC=0 \ + -DNTSHELL_USE_CMDS_PERIPHERAL=0 # # root dir of embARC # diff --git a/example/freertos/sec/mbedtls/ssl/client2/ssl_client2.c b/example/freertos/sec/mbedtls/ssl/client2/ssl_client2.c index 908b5dea8..7af67787d 100644 --- a/example/freertos/sec/mbedtls/ssl/client2/ssl_client2.c +++ b/example/freertos/sec/mbedtls/ssl/client2/ssl_client2.c @@ -35,14 +35,14 @@ #endif #if !defined(MBEDTLS_ENTROPY_C) || \ - !defined(MBEDTLS_SSL_TLS_C) || !defined(MBEDTLS_SSL_CLI_C) || \ - !defined(MBEDTLS_NET_C) || !defined(MBEDTLS_CTR_DRBG_C) + !defined(MBEDTLS_SSL_TLS_C) || !defined(MBEDTLS_SSL_CLI_C) || \ + !defined(MBEDTLS_NET_C) || !defined(MBEDTLS_CTR_DRBG_C) int main( void ) { - mbedtls_printf("MBEDTLS_ENTROPY_C and/or " - "MBEDTLS_SSL_TLS_C and/or MBEDTLS_SSL_CLI_C and/or " - "MBEDTLS_NET_C and/or MBEDTLS_CTR_DRBG_C and/or not defined.\n"); - return( 0 ); + mbedtls_printf("MBEDTLS_ENTROPY_C and/or " + "MBEDTLS_SSL_TLS_C and/or MBEDTLS_SSL_CLI_C and/or " + "MBEDTLS_NET_C and/or MBEDTLS_CTR_DRBG_C and/or not defined.\n"); + return( 0 ); } #else @@ -107,16 +107,16 @@ int main( void ) #if defined(MBEDTLS_X509_CRT_PARSE_C) #if defined(MBEDTLS_FS_IO) #define USAGE_IO \ - " ca_file=%%s The single file containing the top-level CA(s) you fully trust\n" \ - " default: \"\" (pre-loaded)\n" \ - " ca_path=%%s The path containing the top-level CA(s) you fully trust\n" \ - " default: \"\" (pre-loaded) (overrides ca_file)\n" \ - " crt_file=%%s Your own cert and chain (in bottom to top order, top may be omitted)\n" \ - " default: \"\" (pre-loaded)\n" \ - " key_file=%%s default: \"\" (pre-loaded)\n" + " ca_file=%%s The single file containing the top-level CA(s) you fully trust\n" \ + " default: \"\" (pre-loaded)\n" \ + " ca_path=%%s The path containing the top-level CA(s) you fully trust\n" \ + " default: \"\" (pre-loaded) (overrides ca_file)\n" \ + " crt_file=%%s Your own cert and chain (in bottom to top order, top may be omitted)\n" \ + " default: \"\" (pre-loaded)\n" \ + " key_file=%%s default: \"\" (pre-loaded)\n" #else #define USAGE_IO \ - " No file operations available (MBEDTLS_FS_IO not defined)\n" + " No file operations available (MBEDTLS_FS_IO not defined)\n" #endif /* MBEDTLS_FS_IO */ #else #define USAGE_IO "" @@ -124,211 +124,211 @@ int main( void ) #if defined(MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED) #define USAGE_PSK \ - " psk=%%s default: \"\" (in hex, without 0x)\n" \ - " psk_identity=%%s default: \"Client_identity\"\n" + " psk=%%s default: \"\" (in hex, without 0x)\n" \ + " psk_identity=%%s default: \"Client_identity\"\n" #else #define USAGE_PSK "" #endif /* MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED */ #if defined(MBEDTLS_SSL_SESSION_TICKETS) #define USAGE_TICKETS \ - " tickets=%%d default: 1 (enabled)\n" + " tickets=%%d default: 1 (enabled)\n" #else #define USAGE_TICKETS "" #endif /* MBEDTLS_SSL_SESSION_TICKETS */ #if defined(MBEDTLS_SSL_TRUNCATED_HMAC) #define USAGE_TRUNC_HMAC \ - " trunc_hmac=%%d default: library default\n" + " trunc_hmac=%%d default: library default\n" #else #define USAGE_TRUNC_HMAC "" #endif /* MBEDTLS_SSL_TRUNCATED_HMAC */ #if defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH) #define USAGE_MAX_FRAG_LEN \ - " max_frag_len=%%d default: 16384 (tls default)\n" \ - " options: 512, 1024, 2048, 4096\n" + " max_frag_len=%%d default: 16384 (tls default)\n" \ + " options: 512, 1024, 2048, 4096\n" #else #define USAGE_MAX_FRAG_LEN "" #endif /* MBEDTLS_SSL_MAX_FRAGMENT_LENGTH */ #if defined(MBEDTLS_SSL_CBC_RECORD_SPLITTING) #define USAGE_RECSPLIT \ - " recsplit=0/1 default: (library default: on)\n" + " recsplit=0/1 default: (library default: on)\n" #else #define USAGE_RECSPLIT #endif #if defined(MBEDTLS_DHM_C) #define USAGE_DHMLEN \ - " dhmlen=%%d default: (library default: 1024 bits)\n" + " dhmlen=%%d default: (library default: 1024 bits)\n" #else #define USAGE_DHMLEN #endif #if defined(MBEDTLS_SSL_ALPN) #define USAGE_ALPN \ - " alpn=%%s default: \"\" (disabled)\n" \ - " example: spdy/1,http/1.1\n" + " alpn=%%s default: \"\" (disabled)\n" \ + " example: spdy/1,http/1.1\n" #else #define USAGE_ALPN "" #endif /* MBEDTLS_SSL_ALPN */ #if defined(MBEDTLS_SSL_PROTO_DTLS) #define USAGE_DTLS \ - " dtls=%%d default: 0 (TLS)\n" \ - " hs_timeout=%%d-%%d default: (library default: 1000-60000)\n" \ - " range of DTLS handshake timeouts in millisecs\n" + " dtls=%%d default: 0 (TLS)\n" \ + " hs_timeout=%%d-%%d default: (library default: 1000-60000)\n" \ + " range of DTLS handshake timeouts in millisecs\n" #else #define USAGE_DTLS "" #endif #if defined(MBEDTLS_SSL_FALLBACK_SCSV) #define USAGE_FALLBACK \ - " fallback=0/1 default: (library default: off)\n" + " fallback=0/1 default: (library default: off)\n" #else #define USAGE_FALLBACK "" #endif #if defined(MBEDTLS_SSL_EXTENDED_MASTER_SECRET) #define USAGE_EMS \ - " extended_ms=0/1 default: (library default: on)\n" + " extended_ms=0/1 default: (library default: on)\n" #else #define USAGE_EMS "" #endif #if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC) #define USAGE_ETM \ - " etm=0/1 default: (library default: on)\n" + " etm=0/1 default: (library default: on)\n" #else #define USAGE_ETM "" #endif #if defined(MBEDTLS_SSL_RENEGOTIATION) #define USAGE_RENEGO \ - " renegotiation=%%d default: 0 (disabled)\n" \ - " renegotiate=%%d default: 0 (disabled)\n" + " renegotiation=%%d default: 0 (disabled)\n" \ + " renegotiate=%%d default: 0 (disabled)\n" #else #define USAGE_RENEGO "" #endif #if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) #define USAGE_ECJPAKE \ - " ecjpake_pw=%%s default: none (disabled)\n" + " ecjpake_pw=%%s default: none (disabled)\n" #else #define USAGE_ECJPAKE "" #endif #define USAGE \ - "\n usage: ssl_client2 param=<>...\n" \ - "\n acceptable parameters:\n" \ - " server_name=%%s default: localhost\n" \ - " server_addr=%%s default: given by name\n" \ - " server_port=%%d default: 4433\n" \ - " request_page=%%s default: \".\"\n" \ - " request_size=%%d default: about 34 (basic request)\n" \ - " (minimum: 0, max: 16384)\n" \ - " debug_level=%%d default: 0 (disabled)\n" \ - " nbio=%%d default: 0 (blocking I/O)\n" \ - " options: 1 (non-blocking), 2 (added delays)\n" \ - " read_timeout=%%d default: 0 ms (no timeout)\n" \ - " max_resend=%%d default: 0 (no resend on timeout)\n" \ - "\n" \ - USAGE_DTLS \ - "\n" \ - " auth_mode=%%s default: (library default: none)\n" \ - " options: none, optional, required\n" \ - USAGE_IO \ - "\n" \ - USAGE_PSK \ - USAGE_ECJPAKE \ - "\n" \ - " allow_legacy=%%d default: (library default: no)\n" \ - USAGE_RENEGO \ - " exchanges=%%d default: 1\n" \ - " reconnect=%%d default: 0 (disabled)\n" \ - " reco_delay=%%d default: 0 seconds\n" \ - " reconnect_hard=%%d default: 0 (disabled)\n" \ - USAGE_TICKETS \ - USAGE_MAX_FRAG_LEN \ - USAGE_TRUNC_HMAC \ - USAGE_ALPN \ - USAGE_FALLBACK \ - USAGE_EMS \ - USAGE_ETM \ - USAGE_RECSPLIT \ - USAGE_DHMLEN \ - "\n" \ - " arc4=%%d default: (library default: 0)\n" \ - " min_version=%%s default: (library default: tls1)\n" \ - " max_version=%%s default: (library default: tls1_2)\n" \ - " force_version=%%s default: \"\" (none)\n" \ - " options: ssl3, tls1, tls1_1, tls1_2, dtls1, dtls1_2\n" \ - "\n" \ - " force_ciphersuite= default: all enabled\n"\ - " acceptable ciphersuite names:\n" + "\n usage: ssl_client2 param=<>...\n" \ + "\n acceptable parameters:\n" \ + " server_name=%%s default: localhost\n" \ + " server_addr=%%s default: given by name\n" \ + " server_port=%%d default: 4433\n" \ + " request_page=%%s default: \".\"\n" \ + " request_size=%%d default: about 34 (basic request)\n" \ + " (minimum: 0, max: 16384)\n" \ + " debug_level=%%d default: 0 (disabled)\n" \ + " nbio=%%d default: 0 (blocking I/O)\n" \ + " options: 1 (non-blocking), 2 (added delays)\n" \ + " read_timeout=%%d default: 0 ms (no timeout)\n" \ + " max_resend=%%d default: 0 (no resend on timeout)\n" \ + "\n" \ + USAGE_DTLS \ + "\n" \ + " auth_mode=%%s default: (library default: none)\n" \ + " options: none, optional, required\n" \ + USAGE_IO \ + "\n" \ + USAGE_PSK \ + USAGE_ECJPAKE \ + "\n" \ + " allow_legacy=%%d default: (library default: no)\n" \ + USAGE_RENEGO \ + " exchanges=%%d default: 1\n" \ + " reconnect=%%d default: 0 (disabled)\n" \ + " reco_delay=%%d default: 0 seconds\n" \ + " reconnect_hard=%%d default: 0 (disabled)\n" \ + USAGE_TICKETS \ + USAGE_MAX_FRAG_LEN \ + USAGE_TRUNC_HMAC \ + USAGE_ALPN \ + USAGE_FALLBACK \ + USAGE_EMS \ + USAGE_ETM \ + USAGE_RECSPLIT \ + USAGE_DHMLEN \ + "\n" \ + " arc4=%%d default: (library default: 0)\n" \ + " min_version=%%s default: (library default: tls1)\n" \ + " max_version=%%s default: (library default: tls1_2)\n" \ + " force_version=%%s default: \"\" (none)\n" \ + " options: ssl3, tls1, tls1_1, tls1_2, dtls1, dtls1_2\n" \ + "\n" \ + " force_ciphersuite= default: all enabled\n"\ + " acceptable ciphersuite names:\n" /* * global options */ struct options { - const char *server_name; /* hostname of the server (client only) */ - const char *server_addr; /* address of the server (client only) */ - const char *server_port; /* port on which the ssl service runs */ - int debug_level; /* level of debugging */ - int nbio; /* should I/O be blocking? */ - uint32_t read_timeout; /* timeout on mbedtls_ssl_read() in milliseconds */ - int max_resend; /* DTLS times to resend on read timeout */ - const char *request_page; /* page on server to request */ - int request_size; /* pad request with header to requested size */ - const char *ca_file; /* the file with the CA certificate(s) */ - const char *ca_path; /* the path with the CA certificate(s) reside */ - const char *crt_file; /* the file with the client certificate */ - const char *key_file; /* the file with the client key */ - const char *psk; /* the pre-shared key */ - const char *psk_identity; /* the pre-shared key identity */ - const char *ecjpake_pw; /* the EC J-PAKE password */ - int force_ciphersuite[2]; /* protocol/ciphersuite to use, or all */ - int renegotiation; /* enable / disable renegotiation */ - int allow_legacy; /* allow legacy renegotiation */ - int renegotiate; /* attempt renegotiation? */ - int renego_delay; /* delay before enforcing renegotiation */ - int exchanges; /* number of data exchanges */ - int min_version; /* minimum protocol version accepted */ - int max_version; /* maximum protocol version accepted */ - int arc4; /* flag for arc4 suites support */ - int auth_mode; /* verify mode for connection */ - unsigned char mfl_code; /* code for maximum fragment length */ - int trunc_hmac; /* negotiate truncated hmac or not */ - int recsplit; /* enable record splitting? */ - int dhmlen; /* minimum DHM params len in bits */ - int reconnect; /* attempt to resume session */ - int reco_delay; /* delay in seconds before resuming session */ - int reconnect_hard; /* unexpectedly reconnect from the same port */ - int tickets; /* enable / disable session tickets */ - const char *alpn_string; /* ALPN supported protocols */ - int transport; /* TLS or DTLS? */ - uint32_t hs_to_min; /* Initial value of DTLS handshake timer */ - uint32_t hs_to_max; /* Max value of DTLS handshake timer */ - int fallback; /* is this a fallback connection? */ - int extended_ms; /* negotiate extended master secret? */ - int etm; /* negotiate encrypt then mac? */ + const char *server_name; /* hostname of the server (client only) */ + const char *server_addr; /* address of the server (client only) */ + const char *server_port; /* port on which the ssl service runs */ + int debug_level; /* level of debugging */ + int nbio; /* should I/O be blocking? */ + uint32_t read_timeout; /* timeout on mbedtls_ssl_read() in milliseconds */ + int max_resend; /* DTLS times to resend on read timeout */ + const char *request_page; /* page on server to request */ + int request_size; /* pad request with header to requested size */ + const char *ca_file; /* the file with the CA certificate(s) */ + const char *ca_path; /* the path with the CA certificate(s) reside */ + const char *crt_file; /* the file with the client certificate */ + const char *key_file; /* the file with the client key */ + const char *psk; /* the pre-shared key */ + const char *psk_identity; /* the pre-shared key identity */ + const char *ecjpake_pw; /* the EC J-PAKE password */ + int force_ciphersuite[2]; /* protocol/ciphersuite to use, or all */ + int renegotiation; /* enable / disable renegotiation */ + int allow_legacy; /* allow legacy renegotiation */ + int renegotiate; /* attempt renegotiation? */ + int renego_delay; /* delay before enforcing renegotiation */ + int exchanges; /* number of data exchanges */ + int min_version; /* minimum protocol version accepted */ + int max_version; /* maximum protocol version accepted */ + int arc4; /* flag for arc4 suites support */ + int auth_mode; /* verify mode for connection */ + unsigned char mfl_code; /* code for maximum fragment length */ + int trunc_hmac; /* negotiate truncated hmac or not */ + int recsplit; /* enable record splitting? */ + int dhmlen; /* minimum DHM params len in bits */ + int reconnect; /* attempt to resume session */ + int reco_delay; /* delay in seconds before resuming session */ + int reconnect_hard; /* unexpectedly reconnect from the same port */ + int tickets; /* enable / disable session tickets */ + const char *alpn_string; /* ALPN supported protocols */ + int transport; /* TLS or DTLS? */ + uint32_t hs_to_min; /* Initial value of DTLS handshake timer */ + uint32_t hs_to_max; /* Max value of DTLS handshake timer */ + int fallback; /* is this a fallback connection? */ + int extended_ms; /* negotiate extended master secret? */ + int etm; /* negotiate encrypt then mac? */ } opt; static void my_debug( void *ctx, int level, - const char *file, int line, - const char *str ) + const char *file, int line, + const char *str ) { - const char *p, *basename; + const char *p, *basename; - /* Extract basename from file */ - for( p = basename = file; *p != '\0'; p++ ) - if( *p == '/' || *p == '\\' ) - basename = p + 1; + /* Extract basename from file */ + for( p = basename = file; *p != '\0'; p++ ) + if( *p == '/' || *p == '\\' ) + basename = p + 1; - mbedtls_fprintf( (FILE *) ctx, "%s:%04d: |%d| %s", basename, line, level, str ); - fflush( (FILE *) ctx ); + mbedtls_fprintf( (FILE *) ctx, "%s:%04d: |%d| %s", basename, line, level, str ); + fflush( (FILE *) ctx ); } /* @@ -337,36 +337,36 @@ static void my_debug( void *ctx, int level, */ static int my_recv( void *ctx, unsigned char *buf, size_t len ) { - static int first_try = 1; - int ret; - - if( first_try ) - { - first_try = 0; - return( MBEDTLS_ERR_SSL_WANT_READ ); - } - - ret = mbedtls_net_recv( ctx, buf, len ); - if( ret != MBEDTLS_ERR_SSL_WANT_READ ) - first_try = 1; /* Next call will be a new operation */ - return( ret ); + static int first_try = 1; + int ret; + + if( first_try ) + { + first_try = 0; + return( MBEDTLS_ERR_SSL_WANT_READ ); + } + + ret = mbedtls_net_recv( ctx, buf, len ); + if( ret != MBEDTLS_ERR_SSL_WANT_READ ) + first_try = 1; /* Next call will be a new operation */ + return( ret ); } static int my_send( void *ctx, const unsigned char *buf, size_t len ) { - static int first_try = 1; - int ret; - - if( first_try ) - { - first_try = 0; - return( MBEDTLS_ERR_SSL_WANT_WRITE ); - } - - ret = mbedtls_net_send( ctx, buf, len ); - if( ret != MBEDTLS_ERR_SSL_WANT_WRITE ) - first_try = 1; /* Next call will be a new operation */ - return( ret ); + static int first_try = 1; + int ret; + + if( first_try ) + { + first_try = 0; + return( MBEDTLS_ERR_SSL_WANT_WRITE ); + } + + ret = mbedtls_net_send( ctx, buf, len ); + if( ret != MBEDTLS_ERR_SSL_WANT_WRITE ) + first_try = 1; /* Next call will be a new operation */ + return( ret ); } #if defined(MBEDTLS_X509_CRT_PARSE_C) @@ -375,1296 +375,1296 @@ static int my_send( void *ctx, const unsigned char *buf, size_t len ) */ static int my_verify( void *data, mbedtls_x509_crt *crt, int depth, uint32_t *flags ) { - char buf[1024]; - ((void) data); - - mbedtls_printf( "\nVerify requested for (Depth %d):\n", depth ); - mbedtls_x509_crt_info( buf, sizeof( buf ) - 1, "", crt ); - mbedtls_printf( "%s", buf ); - - if ( ( *flags ) == 0 ) - mbedtls_printf( " This certificate has no flags\n" ); - else - { - mbedtls_x509_crt_verify_info( buf, sizeof( buf ), " ! ", *flags ); - mbedtls_printf( "%s\n", buf ); - } - - return( 0 ); + char buf[1024]; + ((void) data); + + mbedtls_printf( "\nVerify requested for (Depth %d):\n", depth ); + mbedtls_x509_crt_info( buf, sizeof( buf ) - 1, "", crt ); + mbedtls_printf( "%s", buf ); + + if ( ( *flags ) == 0 ) + mbedtls_printf( " This certificate has no flags\n" ); + else + { + mbedtls_x509_crt_verify_info( buf, sizeof( buf ), " ! ", *flags ); + mbedtls_printf( "%s\n", buf ); + } + + return( 0 ); } #endif /* MBEDTLS_X509_CRT_PARSE_C */ -int main( int argc, char *argv[] ) -{ - int ret = 0, len, tail_len, i, written, frags, retry_left; - mbedtls_net_context server_fd; - unsigned char buf[MBEDTLS_SSL_MAX_CONTENT_LEN + 1]; +mbedtls_net_context server_fd; +unsigned char buf[MBEDTLS_SSL_MAX_CONTENT_LEN + 1]; #if defined(MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED) - unsigned char psk[MBEDTLS_PSK_MAX_LEN]; - size_t psk_len = 0; +unsigned char psk[MBEDTLS_PSK_MAX_LEN]; +size_t psk_len = 0; #endif #if defined(MBEDTLS_SSL_ALPN) - const char *alpn_list[10]; +const char *alpn_list[10]; #endif - const char *pers = "ssl_client2"; - - mbedtls_entropy_context entropy; - mbedtls_ctr_drbg_context ctr_drbg; - mbedtls_ssl_context ssl; - mbedtls_ssl_config conf; - mbedtls_ssl_session saved_session; +const char *pers = "ssl_client2"; +mbedtls_entropy_context entropy; +mbedtls_ctr_drbg_context ctr_drbg; +mbedtls_ssl_context ssl; +mbedtls_ssl_config conf; +mbedtls_ssl_session saved_session; #if defined(MBEDTLS_TIMING_C) - mbedtls_timing_delay_context timer; +mbedtls_timing_delay_context timer; #endif #if defined(MBEDTLS_X509_CRT_PARSE_C) - uint32_t flags; - mbedtls_x509_crt cacert; - mbedtls_x509_crt clicert; - mbedtls_pk_context pkey; +uint32_t flags; +mbedtls_x509_crt cacert; +mbedtls_x509_crt clicert; +mbedtls_pk_context pkey; #endif - char *p, *q; - const int *list; - - /* - * Make sure memory references are valid. - */ - mbedtls_net_init( &server_fd ); - mbedtls_ssl_init( &ssl ); - mbedtls_ssl_config_init( &conf ); - memset( &saved_session, 0, sizeof( mbedtls_ssl_session ) ); - mbedtls_ctr_drbg_init( &ctr_drbg ); + +int main( int argc, char *argv[] ) +{ + int ret = 0, len, tail_len, i, written, frags, retry_left; + char *p, *q; + const int *list; + + /* + * Make sure memory references are valid. + */ + mbedtls_net_init( &server_fd ); + mbedtls_ssl_init( &ssl ); + mbedtls_ssl_config_init( &conf ); + memset( &saved_session, 0, sizeof( mbedtls_ssl_session ) ); + mbedtls_ctr_drbg_init( &ctr_drbg ); #if defined(MBEDTLS_X509_CRT_PARSE_C) - mbedtls_x509_crt_init( &cacert ); - mbedtls_x509_crt_init( &clicert ); - mbedtls_pk_init( &pkey ); + mbedtls_x509_crt_init( &cacert ); + mbedtls_x509_crt_init( &clicert ); + mbedtls_pk_init( &pkey ); #endif #if defined(MBEDTLS_SSL_ALPN) - memset( (void * ) alpn_list, 0, sizeof( alpn_list ) ); + memset( (void * ) alpn_list, 0, sizeof( alpn_list ) ); #endif - if( argc == 0 ) - { - usage: - if( ret == 0 ) - ret = 1; - - mbedtls_printf( USAGE ); - - list = mbedtls_ssl_list_ciphersuites(); - while( *list ) - { - mbedtls_printf(" %-42s", mbedtls_ssl_get_ciphersuite_name( *list ) ); - list++; - if( !*list ) - break; - mbedtls_printf(" %s\n", mbedtls_ssl_get_ciphersuite_name( *list ) ); - list++; - } - mbedtls_printf("\n"); - goto exit; - } - - opt.server_name = DFL_SERVER_NAME; - opt.server_addr = DFL_SERVER_ADDR; - opt.server_port = DFL_SERVER_PORT; - opt.debug_level = DFL_DEBUG_LEVEL; - opt.nbio = DFL_NBIO; - opt.read_timeout = DFL_READ_TIMEOUT; - opt.max_resend = DFL_MAX_RESEND; - opt.request_page = DFL_REQUEST_PAGE; - opt.request_size = DFL_REQUEST_SIZE; - opt.ca_file = DFL_CA_FILE; - opt.ca_path = DFL_CA_PATH; - opt.crt_file = DFL_CRT_FILE; - opt.key_file = DFL_KEY_FILE; - opt.psk = DFL_PSK; - opt.psk_identity = DFL_PSK_IDENTITY; - opt.ecjpake_pw = DFL_ECJPAKE_PW; - opt.force_ciphersuite[0]= DFL_FORCE_CIPHER; - opt.renegotiation = DFL_RENEGOTIATION; - opt.allow_legacy = DFL_ALLOW_LEGACY; - opt.renegotiate = DFL_RENEGOTIATE; - opt.exchanges = DFL_EXCHANGES; - opt.min_version = DFL_MIN_VERSION; - opt.max_version = DFL_MAX_VERSION; - opt.arc4 = DFL_ARC4; - opt.auth_mode = DFL_AUTH_MODE; - opt.mfl_code = DFL_MFL_CODE; - opt.trunc_hmac = DFL_TRUNC_HMAC; - opt.recsplit = DFL_RECSPLIT; - opt.dhmlen = DFL_DHMLEN; - opt.reconnect = DFL_RECONNECT; - opt.reco_delay = DFL_RECO_DELAY; - opt.reconnect_hard = DFL_RECONNECT_HARD; - opt.tickets = DFL_TICKETS; - opt.alpn_string = DFL_ALPN_STRING; - opt.transport = DFL_TRANSPORT; - opt.hs_to_min = DFL_HS_TO_MIN; - opt.hs_to_max = DFL_HS_TO_MAX; - opt.fallback = DFL_FALLBACK; - opt.extended_ms = DFL_EXTENDED_MS; - opt.etm = DFL_ETM; - - for( i = 1; i < argc; i++ ) - { - p = argv[i]; - if( ( q = strchr( p, '=' ) ) == NULL ) - goto usage; - *q++ = '\0'; - - if( strcmp( p, "server_name" ) == 0 ) - opt.server_name = q; - else if( strcmp( p, "server_addr" ) == 0 ) - opt.server_addr = q; - else if( strcmp( p, "server_port" ) == 0 ) - opt.server_port = q; - else if( strcmp( p, "dtls" ) == 0 ) - { - int t = atoi( q ); - if( t == 0 ) - opt.transport = MBEDTLS_SSL_TRANSPORT_STREAM; - else if( t == 1 ) - opt.transport = MBEDTLS_SSL_TRANSPORT_DATAGRAM; - else - goto usage; - } - else if( strcmp( p, "debug_level" ) == 0 ) - { - opt.debug_level = atoi( q ); - if( opt.debug_level < 0 || opt.debug_level > 65535 ) - goto usage; - } - else if( strcmp( p, "nbio" ) == 0 ) - { - opt.nbio = atoi( q ); - if( opt.nbio < 0 || opt.nbio > 2 ) - goto usage; - } - else if( strcmp( p, "read_timeout" ) == 0 ) - opt.read_timeout = atoi( q ); - else if( strcmp( p, "max_resend" ) == 0 ) - { - opt.max_resend = atoi( q ); - if( opt.max_resend < 0 ) - goto usage; - } - else if( strcmp( p, "request_page" ) == 0 ) - opt.request_page = q; - else if( strcmp( p, "request_size" ) == 0 ) - { - opt.request_size = atoi( q ); - if( opt.request_size < 0 || opt.request_size > MBEDTLS_SSL_MAX_CONTENT_LEN ) - goto usage; - } - else if( strcmp( p, "ca_file" ) == 0 ) - opt.ca_file = q; - else if( strcmp( p, "ca_path" ) == 0 ) - opt.ca_path = q; - else if( strcmp( p, "crt_file" ) == 0 ) - opt.crt_file = q; - else if( strcmp( p, "key_file" ) == 0 ) - opt.key_file = q; - else if( strcmp( p, "psk" ) == 0 ) - opt.psk = q; - else if( strcmp( p, "psk_identity" ) == 0 ) - opt.psk_identity = q; - else if( strcmp( p, "ecjpake_pw" ) == 0 ) - opt.ecjpake_pw = q; - else if( strcmp( p, "force_ciphersuite" ) == 0 ) - { - opt.force_ciphersuite[0] = mbedtls_ssl_get_ciphersuite_id( q ); - - if( opt.force_ciphersuite[0] == 0 ) - { - ret = 2; - goto usage; - } - opt.force_ciphersuite[1] = 0; - } - else if( strcmp( p, "renegotiation" ) == 0 ) - { - opt.renegotiation = (atoi( q )) ? MBEDTLS_SSL_RENEGOTIATION_ENABLED : - MBEDTLS_SSL_RENEGOTIATION_DISABLED; - } - else if( strcmp( p, "allow_legacy" ) == 0 ) - { - switch( atoi( q ) ) - { - case -1: opt.allow_legacy = MBEDTLS_SSL_LEGACY_BREAK_HANDSHAKE; break; - case 0: opt.allow_legacy = MBEDTLS_SSL_LEGACY_NO_RENEGOTIATION; break; - case 1: opt.allow_legacy = MBEDTLS_SSL_LEGACY_ALLOW_RENEGOTIATION; break; - default: goto usage; - } - } - else if( strcmp( p, "renegotiate" ) == 0 ) - { - opt.renegotiate = atoi( q ); - if( opt.renegotiate < 0 || opt.renegotiate > 1 ) - goto usage; - } - else if( strcmp( p, "exchanges" ) == 0 ) - { - opt.exchanges = atoi( q ); - if( opt.exchanges < 1 ) - goto usage; - } - else if( strcmp( p, "reconnect" ) == 0 ) - { - opt.reconnect = atoi( q ); - if( opt.reconnect < 0 || opt.reconnect > 2 ) - goto usage; - } - else if( strcmp( p, "reco_delay" ) == 0 ) - { - opt.reco_delay = atoi( q ); - if( opt.reco_delay < 0 ) - goto usage; - } - else if( strcmp( p, "reconnect_hard" ) == 0 ) - { - opt.reconnect_hard = atoi( q ); - if( opt.reconnect_hard < 0 || opt.reconnect_hard > 1 ) - goto usage; - } - else if( strcmp( p, "tickets" ) == 0 ) - { - opt.tickets = atoi( q ); - if( opt.tickets < 0 || opt.tickets > 2 ) - goto usage; - } - else if( strcmp( p, "alpn" ) == 0 ) - { - opt.alpn_string = q; - } - else if( strcmp( p, "fallback" ) == 0 ) - { - switch( atoi( q ) ) - { - case 0: opt.fallback = MBEDTLS_SSL_IS_NOT_FALLBACK; break; - case 1: opt.fallback = MBEDTLS_SSL_IS_FALLBACK; break; - default: goto usage; - } - } - else if( strcmp( p, "extended_ms" ) == 0 ) - { - switch( atoi( q ) ) - { - case 0: opt.extended_ms = MBEDTLS_SSL_EXTENDED_MS_DISABLED; break; - case 1: opt.extended_ms = MBEDTLS_SSL_EXTENDED_MS_ENABLED; break; - default: goto usage; - } - } - else if( strcmp( p, "etm" ) == 0 ) - { - switch( atoi( q ) ) - { - case 0: opt.etm = MBEDTLS_SSL_ETM_DISABLED; break; - case 1: opt.etm = MBEDTLS_SSL_ETM_ENABLED; break; - default: goto usage; - } - } - else if( strcmp( p, "min_version" ) == 0 ) - { - if( strcmp( q, "ssl3" ) == 0 ) - opt.min_version = MBEDTLS_SSL_MINOR_VERSION_0; - else if( strcmp( q, "tls1" ) == 0 ) - opt.min_version = MBEDTLS_SSL_MINOR_VERSION_1; - else if( strcmp( q, "tls1_1" ) == 0 || - strcmp( q, "dtls1" ) == 0 ) - opt.min_version = MBEDTLS_SSL_MINOR_VERSION_2; - else if( strcmp( q, "tls1_2" ) == 0 || - strcmp( q, "dtls1_2" ) == 0 ) - opt.min_version = MBEDTLS_SSL_MINOR_VERSION_3; - else - goto usage; - } - else if( strcmp( p, "max_version" ) == 0 ) - { - if( strcmp( q, "ssl3" ) == 0 ) - opt.max_version = MBEDTLS_SSL_MINOR_VERSION_0; - else if( strcmp( q, "tls1" ) == 0 ) - opt.max_version = MBEDTLS_SSL_MINOR_VERSION_1; - else if( strcmp( q, "tls1_1" ) == 0 || - strcmp( q, "dtls1" ) == 0 ) - opt.max_version = MBEDTLS_SSL_MINOR_VERSION_2; - else if( strcmp( q, "tls1_2" ) == 0 || - strcmp( q, "dtls1_2" ) == 0 ) - opt.max_version = MBEDTLS_SSL_MINOR_VERSION_3; - else - goto usage; - } - else if( strcmp( p, "arc4" ) == 0 ) - { - switch( atoi( q ) ) - { - case 0: opt.arc4 = MBEDTLS_SSL_ARC4_DISABLED; break; - case 1: opt.arc4 = MBEDTLS_SSL_ARC4_ENABLED; break; - default: goto usage; - } - } - else if( strcmp( p, "force_version" ) == 0 ) - { - if( strcmp( q, "ssl3" ) == 0 ) - { - opt.min_version = MBEDTLS_SSL_MINOR_VERSION_0; - opt.max_version = MBEDTLS_SSL_MINOR_VERSION_0; - } - else if( strcmp( q, "tls1" ) == 0 ) - { - opt.min_version = MBEDTLS_SSL_MINOR_VERSION_1; - opt.max_version = MBEDTLS_SSL_MINOR_VERSION_1; - } - else if( strcmp( q, "tls1_1" ) == 0 ) - { - opt.min_version = MBEDTLS_SSL_MINOR_VERSION_2; - opt.max_version = MBEDTLS_SSL_MINOR_VERSION_2; - } - else if( strcmp( q, "tls1_2" ) == 0 ) - { - opt.min_version = MBEDTLS_SSL_MINOR_VERSION_3; - opt.max_version = MBEDTLS_SSL_MINOR_VERSION_3; - } - else if( strcmp( q, "dtls1" ) == 0 ) - { - opt.min_version = MBEDTLS_SSL_MINOR_VERSION_2; - opt.max_version = MBEDTLS_SSL_MINOR_VERSION_2; - opt.transport = MBEDTLS_SSL_TRANSPORT_DATAGRAM; - } - else if( strcmp( q, "dtls1_2" ) == 0 ) - { - opt.min_version = MBEDTLS_SSL_MINOR_VERSION_3; - opt.max_version = MBEDTLS_SSL_MINOR_VERSION_3; - opt.transport = MBEDTLS_SSL_TRANSPORT_DATAGRAM; - } - else - goto usage; - } - else if( strcmp( p, "auth_mode" ) == 0 ) - { - if( strcmp( q, "none" ) == 0 ) - opt.auth_mode = MBEDTLS_SSL_VERIFY_NONE; - else if( strcmp( q, "optional" ) == 0 ) - opt.auth_mode = MBEDTLS_SSL_VERIFY_OPTIONAL; - else if( strcmp( q, "required" ) == 0 ) - opt.auth_mode = MBEDTLS_SSL_VERIFY_REQUIRED; - else - goto usage; - } - else if( strcmp( p, "max_frag_len" ) == 0 ) - { - if( strcmp( q, "512" ) == 0 ) - opt.mfl_code = MBEDTLS_SSL_MAX_FRAG_LEN_512; - else if( strcmp( q, "1024" ) == 0 ) - opt.mfl_code = MBEDTLS_SSL_MAX_FRAG_LEN_1024; - else if( strcmp( q, "2048" ) == 0 ) - opt.mfl_code = MBEDTLS_SSL_MAX_FRAG_LEN_2048; - else if( strcmp( q, "4096" ) == 0 ) - opt.mfl_code = MBEDTLS_SSL_MAX_FRAG_LEN_4096; - else - goto usage; - } - else if( strcmp( p, "trunc_hmac" ) == 0 ) - { - switch( atoi( q ) ) - { - case 0: opt.trunc_hmac = MBEDTLS_SSL_TRUNC_HMAC_DISABLED; break; - case 1: opt.trunc_hmac = MBEDTLS_SSL_TRUNC_HMAC_ENABLED; break; - default: goto usage; - } - } - else if( strcmp( p, "hs_timeout" ) == 0 ) - { - if( ( p = strchr( q, '-' ) ) == NULL ) - goto usage; - *p++ = '\0'; - opt.hs_to_min = atoi( q ); - opt.hs_to_max = atoi( p ); - if( opt.hs_to_min == 0 || opt.hs_to_max < opt.hs_to_min ) - goto usage; - } - else if( strcmp( p, "recsplit" ) == 0 ) - { - opt.recsplit = atoi( q ); - if( opt.recsplit < 0 || opt.recsplit > 1 ) - goto usage; - } - else if( strcmp( p, "dhmlen" ) == 0 ) - { - opt.dhmlen = atoi( q ); - if( opt.dhmlen < 0 ) - goto usage; - } - else - goto usage; - } + if( argc == 0 ) + { + usage: + if( ret == 0 ) + ret = 1; + + mbedtls_printf( USAGE ); + + list = mbedtls_ssl_list_ciphersuites(); + while( *list ) + { + mbedtls_printf(" %-42s", mbedtls_ssl_get_ciphersuite_name( *list ) ); + list++; + if( !*list ) + break; + mbedtls_printf(" %s\n", mbedtls_ssl_get_ciphersuite_name( *list ) ); + list++; + } + mbedtls_printf("\n"); + goto exit; + } + + opt.server_name = DFL_SERVER_NAME; + opt.server_addr = DFL_SERVER_ADDR; + opt.server_port = DFL_SERVER_PORT; + opt.debug_level = DFL_DEBUG_LEVEL; + opt.nbio = DFL_NBIO; + opt.read_timeout = DFL_READ_TIMEOUT; + opt.max_resend = DFL_MAX_RESEND; + opt.request_page = DFL_REQUEST_PAGE; + opt.request_size = DFL_REQUEST_SIZE; + opt.ca_file = DFL_CA_FILE; + opt.ca_path = DFL_CA_PATH; + opt.crt_file = DFL_CRT_FILE; + opt.key_file = DFL_KEY_FILE; + opt.psk = DFL_PSK; + opt.psk_identity = DFL_PSK_IDENTITY; + opt.ecjpake_pw = DFL_ECJPAKE_PW; + opt.force_ciphersuite[0]= DFL_FORCE_CIPHER; + opt.renegotiation = DFL_RENEGOTIATION; + opt.allow_legacy = DFL_ALLOW_LEGACY; + opt.renegotiate = DFL_RENEGOTIATE; + opt.exchanges = DFL_EXCHANGES; + opt.min_version = DFL_MIN_VERSION; + opt.max_version = DFL_MAX_VERSION; + opt.arc4 = DFL_ARC4; + opt.auth_mode = DFL_AUTH_MODE; + opt.mfl_code = DFL_MFL_CODE; + opt.trunc_hmac = DFL_TRUNC_HMAC; + opt.recsplit = DFL_RECSPLIT; + opt.dhmlen = DFL_DHMLEN; + opt.reconnect = DFL_RECONNECT; + opt.reco_delay = DFL_RECO_DELAY; + opt.reconnect_hard = DFL_RECONNECT_HARD; + opt.tickets = DFL_TICKETS; + opt.alpn_string = DFL_ALPN_STRING; + opt.transport = DFL_TRANSPORT; + opt.hs_to_min = DFL_HS_TO_MIN; + opt.hs_to_max = DFL_HS_TO_MAX; + opt.fallback = DFL_FALLBACK; + opt.extended_ms = DFL_EXTENDED_MS; + opt.etm = DFL_ETM; + + for( i = 1; i < argc; i++ ) + { + p = argv[i]; + if( ( q = strchr( p, '=' ) ) == NULL ) + goto usage; + *q++ = '\0'; + + if( strcmp( p, "server_name" ) == 0 ) + opt.server_name = q; + else if( strcmp( p, "server_addr" ) == 0 ) + opt.server_addr = q; + else if( strcmp( p, "server_port" ) == 0 ) + opt.server_port = q; + else if( strcmp( p, "dtls" ) == 0 ) + { + int t = atoi( q ); + if( t == 0 ) + opt.transport = MBEDTLS_SSL_TRANSPORT_STREAM; + else if( t == 1 ) + opt.transport = MBEDTLS_SSL_TRANSPORT_DATAGRAM; + else + goto usage; + } + else if( strcmp( p, "debug_level" ) == 0 ) + { + opt.debug_level = atoi( q ); + if( opt.debug_level < 0 || opt.debug_level > 65535 ) + goto usage; + } + else if( strcmp( p, "nbio" ) == 0 ) + { + opt.nbio = atoi( q ); + if( opt.nbio < 0 || opt.nbio > 2 ) + goto usage; + } + else if( strcmp( p, "read_timeout" ) == 0 ) + opt.read_timeout = atoi( q ); + else if( strcmp( p, "max_resend" ) == 0 ) + { + opt.max_resend = atoi( q ); + if( opt.max_resend < 0 ) + goto usage; + } + else if( strcmp( p, "request_page" ) == 0 ) + opt.request_page = q; + else if( strcmp( p, "request_size" ) == 0 ) + { + opt.request_size = atoi( q ); + if( opt.request_size < 0 || opt.request_size > MBEDTLS_SSL_MAX_CONTENT_LEN ) + goto usage; + } + else if( strcmp( p, "ca_file" ) == 0 ) + opt.ca_file = q; + else if( strcmp( p, "ca_path" ) == 0 ) + opt.ca_path = q; + else if( strcmp( p, "crt_file" ) == 0 ) + opt.crt_file = q; + else if( strcmp( p, "key_file" ) == 0 ) + opt.key_file = q; + else if( strcmp( p, "psk" ) == 0 ) + opt.psk = q; + else if( strcmp( p, "psk_identity" ) == 0 ) + opt.psk_identity = q; + else if( strcmp( p, "ecjpake_pw" ) == 0 ) + opt.ecjpake_pw = q; + else if( strcmp( p, "force_ciphersuite" ) == 0 ) + { + opt.force_ciphersuite[0] = mbedtls_ssl_get_ciphersuite_id( q ); + + if( opt.force_ciphersuite[0] == 0 ) + { + ret = 2; + goto usage; + } + opt.force_ciphersuite[1] = 0; + } + else if( strcmp( p, "renegotiation" ) == 0 ) + { + opt.renegotiation = (atoi( q )) ? MBEDTLS_SSL_RENEGOTIATION_ENABLED : + MBEDTLS_SSL_RENEGOTIATION_DISABLED; + } + else if( strcmp( p, "allow_legacy" ) == 0 ) + { + switch( atoi( q ) ) + { + case -1: opt.allow_legacy = MBEDTLS_SSL_LEGACY_BREAK_HANDSHAKE; break; + case 0: opt.allow_legacy = MBEDTLS_SSL_LEGACY_NO_RENEGOTIATION; break; + case 1: opt.allow_legacy = MBEDTLS_SSL_LEGACY_ALLOW_RENEGOTIATION; break; + default: goto usage; + } + } + else if( strcmp( p, "renegotiate" ) == 0 ) + { + opt.renegotiate = atoi( q ); + if( opt.renegotiate < 0 || opt.renegotiate > 1 ) + goto usage; + } + else if( strcmp( p, "exchanges" ) == 0 ) + { + opt.exchanges = atoi( q ); + if( opt.exchanges < 1 ) + goto usage; + } + else if( strcmp( p, "reconnect" ) == 0 ) + { + opt.reconnect = atoi( q ); + if( opt.reconnect < 0 || opt.reconnect > 2 ) + goto usage; + } + else if( strcmp( p, "reco_delay" ) == 0 ) + { + opt.reco_delay = atoi( q ); + if( opt.reco_delay < 0 ) + goto usage; + } + else if( strcmp( p, "reconnect_hard" ) == 0 ) + { + opt.reconnect_hard = atoi( q ); + if( opt.reconnect_hard < 0 || opt.reconnect_hard > 1 ) + goto usage; + } + else if( strcmp( p, "tickets" ) == 0 ) + { + opt.tickets = atoi( q ); + if( opt.tickets < 0 || opt.tickets > 2 ) + goto usage; + } + else if( strcmp( p, "alpn" ) == 0 ) + { + opt.alpn_string = q; + } + else if( strcmp( p, "fallback" ) == 0 ) + { + switch( atoi( q ) ) + { + case 0: opt.fallback = MBEDTLS_SSL_IS_NOT_FALLBACK; break; + case 1: opt.fallback = MBEDTLS_SSL_IS_FALLBACK; break; + default: goto usage; + } + } + else if( strcmp( p, "extended_ms" ) == 0 ) + { + switch( atoi( q ) ) + { + case 0: opt.extended_ms = MBEDTLS_SSL_EXTENDED_MS_DISABLED; break; + case 1: opt.extended_ms = MBEDTLS_SSL_EXTENDED_MS_ENABLED; break; + default: goto usage; + } + } + else if( strcmp( p, "etm" ) == 0 ) + { + switch( atoi( q ) ) + { + case 0: opt.etm = MBEDTLS_SSL_ETM_DISABLED; break; + case 1: opt.etm = MBEDTLS_SSL_ETM_ENABLED; break; + default: goto usage; + } + } + else if( strcmp( p, "min_version" ) == 0 ) + { + if( strcmp( q, "ssl3" ) == 0 ) + opt.min_version = MBEDTLS_SSL_MINOR_VERSION_0; + else if( strcmp( q, "tls1" ) == 0 ) + opt.min_version = MBEDTLS_SSL_MINOR_VERSION_1; + else if( strcmp( q, "tls1_1" ) == 0 || + strcmp( q, "dtls1" ) == 0 ) + opt.min_version = MBEDTLS_SSL_MINOR_VERSION_2; + else if( strcmp( q, "tls1_2" ) == 0 || + strcmp( q, "dtls1_2" ) == 0 ) + opt.min_version = MBEDTLS_SSL_MINOR_VERSION_3; + else + goto usage; + } + else if( strcmp( p, "max_version" ) == 0 ) + { + if( strcmp( q, "ssl3" ) == 0 ) + opt.max_version = MBEDTLS_SSL_MINOR_VERSION_0; + else if( strcmp( q, "tls1" ) == 0 ) + opt.max_version = MBEDTLS_SSL_MINOR_VERSION_1; + else if( strcmp( q, "tls1_1" ) == 0 || + strcmp( q, "dtls1" ) == 0 ) + opt.max_version = MBEDTLS_SSL_MINOR_VERSION_2; + else if( strcmp( q, "tls1_2" ) == 0 || + strcmp( q, "dtls1_2" ) == 0 ) + opt.max_version = MBEDTLS_SSL_MINOR_VERSION_3; + else + goto usage; + } + else if( strcmp( p, "arc4" ) == 0 ) + { + switch( atoi( q ) ) + { + case 0: opt.arc4 = MBEDTLS_SSL_ARC4_DISABLED; break; + case 1: opt.arc4 = MBEDTLS_SSL_ARC4_ENABLED; break; + default: goto usage; + } + } + else if( strcmp( p, "force_version" ) == 0 ) + { + if( strcmp( q, "ssl3" ) == 0 ) + { + opt.min_version = MBEDTLS_SSL_MINOR_VERSION_0; + opt.max_version = MBEDTLS_SSL_MINOR_VERSION_0; + } + else if( strcmp( q, "tls1" ) == 0 ) + { + opt.min_version = MBEDTLS_SSL_MINOR_VERSION_1; + opt.max_version = MBEDTLS_SSL_MINOR_VERSION_1; + } + else if( strcmp( q, "tls1_1" ) == 0 ) + { + opt.min_version = MBEDTLS_SSL_MINOR_VERSION_2; + opt.max_version = MBEDTLS_SSL_MINOR_VERSION_2; + } + else if( strcmp( q, "tls1_2" ) == 0 ) + { + opt.min_version = MBEDTLS_SSL_MINOR_VERSION_3; + opt.max_version = MBEDTLS_SSL_MINOR_VERSION_3; + } + else if( strcmp( q, "dtls1" ) == 0 ) + { + opt.min_version = MBEDTLS_SSL_MINOR_VERSION_2; + opt.max_version = MBEDTLS_SSL_MINOR_VERSION_2; + opt.transport = MBEDTLS_SSL_TRANSPORT_DATAGRAM; + } + else if( strcmp( q, "dtls1_2" ) == 0 ) + { + opt.min_version = MBEDTLS_SSL_MINOR_VERSION_3; + opt.max_version = MBEDTLS_SSL_MINOR_VERSION_3; + opt.transport = MBEDTLS_SSL_TRANSPORT_DATAGRAM; + } + else + goto usage; + } + else if( strcmp( p, "auth_mode" ) == 0 ) + { + if( strcmp( q, "none" ) == 0 ) + opt.auth_mode = MBEDTLS_SSL_VERIFY_NONE; + else if( strcmp( q, "optional" ) == 0 ) + opt.auth_mode = MBEDTLS_SSL_VERIFY_OPTIONAL; + else if( strcmp( q, "required" ) == 0 ) + opt.auth_mode = MBEDTLS_SSL_VERIFY_REQUIRED; + else + goto usage; + } + else if( strcmp( p, "max_frag_len" ) == 0 ) + { + if( strcmp( q, "512" ) == 0 ) + opt.mfl_code = MBEDTLS_SSL_MAX_FRAG_LEN_512; + else if( strcmp( q, "1024" ) == 0 ) + opt.mfl_code = MBEDTLS_SSL_MAX_FRAG_LEN_1024; + else if( strcmp( q, "2048" ) == 0 ) + opt.mfl_code = MBEDTLS_SSL_MAX_FRAG_LEN_2048; + else if( strcmp( q, "4096" ) == 0 ) + opt.mfl_code = MBEDTLS_SSL_MAX_FRAG_LEN_4096; + else + goto usage; + } + else if( strcmp( p, "trunc_hmac" ) == 0 ) + { + switch( atoi( q ) ) + { + case 0: opt.trunc_hmac = MBEDTLS_SSL_TRUNC_HMAC_DISABLED; break; + case 1: opt.trunc_hmac = MBEDTLS_SSL_TRUNC_HMAC_ENABLED; break; + default: goto usage; + } + } + else if( strcmp( p, "hs_timeout" ) == 0 ) + { + if( ( p = strchr( q, '-' ) ) == NULL ) + goto usage; + *p++ = '\0'; + opt.hs_to_min = atoi( q ); + opt.hs_to_max = atoi( p ); + if( opt.hs_to_min == 0 || opt.hs_to_max < opt.hs_to_min ) + goto usage; + } + else if( strcmp( p, "recsplit" ) == 0 ) + { + opt.recsplit = atoi( q ); + if( opt.recsplit < 0 || opt.recsplit > 1 ) + goto usage; + } + else if( strcmp( p, "dhmlen" ) == 0 ) + { + opt.dhmlen = atoi( q ); + if( opt.dhmlen < 0 ) + goto usage; + } + else + goto usage; + } #if defined(MBEDTLS_DEBUG_C) - mbedtls_debug_set_threshold( opt.debug_level ); + mbedtls_debug_set_threshold( opt.debug_level ); #endif - if( opt.force_ciphersuite[0] > 0 ) - { - const mbedtls_ssl_ciphersuite_t *ciphersuite_info; - ciphersuite_info = mbedtls_ssl_ciphersuite_from_id( opt.force_ciphersuite[0] ); - - if( opt.max_version != -1 && - ciphersuite_info->min_minor_ver > opt.max_version ) - { - mbedtls_printf("forced ciphersuite not allowed with this protocol version\n"); - ret = 2; - goto usage; - } - if( opt.min_version != -1 && - ciphersuite_info->max_minor_ver < opt.min_version ) - { - mbedtls_printf("forced ciphersuite not allowed with this protocol version\n"); - ret = 2; - goto usage; - } - - /* If the server selects a version that's not supported by - * this suite, then there will be no common ciphersuite... */ - if( opt.max_version == -1 || - opt.max_version > ciphersuite_info->max_minor_ver ) - { - opt.max_version = ciphersuite_info->max_minor_ver; - } - if( opt.min_version < ciphersuite_info->min_minor_ver ) - { - opt.min_version = ciphersuite_info->min_minor_ver; - /* DTLS starts with TLS 1.1 */ - if( opt.transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM && - opt.min_version < MBEDTLS_SSL_MINOR_VERSION_2 ) - opt.min_version = MBEDTLS_SSL_MINOR_VERSION_2; - } - - /* Enable RC4 if needed and not explicitly disabled */ - if( ciphersuite_info->cipher == MBEDTLS_CIPHER_ARC4_128 ) - { - if( opt.arc4 == MBEDTLS_SSL_ARC4_DISABLED ) - { - mbedtls_printf("forced RC4 ciphersuite with RC4 disabled\n"); - ret = 2; - goto usage; - } - - opt.arc4 = MBEDTLS_SSL_ARC4_ENABLED; - } - } + if( opt.force_ciphersuite[0] > 0 ) + { + const mbedtls_ssl_ciphersuite_t *ciphersuite_info; + ciphersuite_info = mbedtls_ssl_ciphersuite_from_id( opt.force_ciphersuite[0] ); + + if( opt.max_version != -1 && + ciphersuite_info->min_minor_ver > opt.max_version ) + { + mbedtls_printf("forced ciphersuite not allowed with this protocol version\n"); + ret = 2; + goto usage; + } + if( opt.min_version != -1 && + ciphersuite_info->max_minor_ver < opt.min_version ) + { + mbedtls_printf("forced ciphersuite not allowed with this protocol version\n"); + ret = 2; + goto usage; + } + + /* If the server selects a version that's not supported by + * this suite, then there will be no common ciphersuite... */ + if( opt.max_version == -1 || + opt.max_version > ciphersuite_info->max_minor_ver ) + { + opt.max_version = ciphersuite_info->max_minor_ver; + } + if( opt.min_version < ciphersuite_info->min_minor_ver ) + { + opt.min_version = ciphersuite_info->min_minor_ver; + /* DTLS starts with TLS 1.1 */ + if( opt.transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM && + opt.min_version < MBEDTLS_SSL_MINOR_VERSION_2 ) + opt.min_version = MBEDTLS_SSL_MINOR_VERSION_2; + } + + /* Enable RC4 if needed and not explicitly disabled */ + if( ciphersuite_info->cipher == MBEDTLS_CIPHER_ARC4_128 ) + { + if( opt.arc4 == MBEDTLS_SSL_ARC4_DISABLED ) + { + mbedtls_printf("forced RC4 ciphersuite with RC4 disabled\n"); + ret = 2; + goto usage; + } + + opt.arc4 = MBEDTLS_SSL_ARC4_ENABLED; + } + } #if defined(MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED) - /* - * Unhexify the pre-shared key if any is given - */ - if( strlen( opt.psk ) ) - { - unsigned char c; - size_t j; - - if( strlen( opt.psk ) % 2 != 0 ) - { - mbedtls_printf("pre-shared key not valid hex\n"); - goto exit; - } - - psk_len = strlen( opt.psk ) / 2; - - for( j = 0; j < strlen( opt.psk ); j += 2 ) - { - c = opt.psk[j]; - if( c >= '0' && c <= '9' ) - c -= '0'; - else if( c >= 'a' && c <= 'f' ) - c -= 'a' - 10; - else if( c >= 'A' && c <= 'F' ) - c -= 'A' - 10; - else - { - mbedtls_printf("pre-shared key not valid hex\n"); - goto exit; - } - psk[ j / 2 ] = c << 4; - - c = opt.psk[j + 1]; - if( c >= '0' && c <= '9' ) - c -= '0'; - else if( c >= 'a' && c <= 'f' ) - c -= 'a' - 10; - else if( c >= 'A' && c <= 'F' ) - c -= 'A' - 10; - else - { - mbedtls_printf("pre-shared key not valid hex\n"); - goto exit; - } - psk[ j / 2 ] |= c; - } - } + /* + * Unhexify the pre-shared key if any is given + */ + if( strlen( opt.psk ) ) + { + unsigned char c; + size_t j; + + if( strlen( opt.psk ) % 2 != 0 ) + { + mbedtls_printf("pre-shared key not valid hex\n"); + goto exit; + } + + psk_len = strlen( opt.psk ) / 2; + + for( j = 0; j < strlen( opt.psk ); j += 2 ) + { + c = opt.psk[j]; + if( c >= '0' && c <= '9' ) + c -= '0'; + else if( c >= 'a' && c <= 'f' ) + c -= 'a' - 10; + else if( c >= 'A' && c <= 'F' ) + c -= 'A' - 10; + else + { + mbedtls_printf("pre-shared key not valid hex\n"); + goto exit; + } + psk[ j / 2 ] = c << 4; + + c = opt.psk[j + 1]; + if( c >= '0' && c <= '9' ) + c -= '0'; + else if( c >= 'a' && c <= 'f' ) + c -= 'a' - 10; + else if( c >= 'A' && c <= 'F' ) + c -= 'A' - 10; + else + { + mbedtls_printf("pre-shared key not valid hex\n"); + goto exit; + } + psk[ j / 2 ] |= c; + } + } #endif /* MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED */ #if defined(MBEDTLS_SSL_ALPN) - if( opt.alpn_string != NULL ) - { - p = (char *) opt.alpn_string; - i = 0; - - /* Leave room for a final NULL in alpn_list */ - while( i < (int) sizeof alpn_list - 1 && *p != '\0' ) - { - alpn_list[i++] = p; - - /* Terminate the current string and move on to next one */ - while( *p != ',' && *p != '\0' ) - p++; - if( *p == ',' ) - *p++ = '\0'; - } - } + if( opt.alpn_string != NULL ) + { + p = (char *) opt.alpn_string; + i = 0; + + /* Leave room for a final NULL in alpn_list */ + while( i < (int) sizeof alpn_list - 1 && *p != '\0' ) + { + alpn_list[i++] = p; + + /* Terminate the current string and move on to next one */ + while( *p != ',' && *p != '\0' ) + p++; + if( *p == ',' ) + *p++ = '\0'; + } + } #endif /* MBEDTLS_SSL_ALPN */ - /* - * 0. Initialize the RNG and the session data - */ - mbedtls_printf( "\n . Seeding the random number generator..." ); - fflush( stdout ); + /* + * 0. Initialize the RNG and the session data + */ + mbedtls_printf( "\n . Seeding the random number generator..." ); + fflush( stdout ); - mbedtls_entropy_init( &entropy ); - if( ( ret = mbedtls_ctr_drbg_seed( &ctr_drbg, mbedtls_entropy_func, &entropy, - (const unsigned char *) pers, - strlen( pers ) ) ) != 0 ) - { - mbedtls_printf( " failed\n ! mbedtls_ctr_drbg_seed returned -0x%x\n", -ret ); - goto exit; - } + mbedtls_entropy_init( &entropy ); + if( ( ret = mbedtls_ctr_drbg_seed( &ctr_drbg, mbedtls_entropy_func, &entropy, + (const unsigned char *) pers, + strlen( pers ) ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ctr_drbg_seed returned -0x%x\n", -ret ); + goto exit; + } - mbedtls_printf( " ok\n" ); + mbedtls_printf( " ok\n" ); #if defined(MBEDTLS_X509_CRT_PARSE_C) - /* - * 1.1. Load the trusted CA - */ - mbedtls_printf( " . Loading the CA root certificate ..." ); - fflush( stdout ); + /* + * 1.1. Load the trusted CA + */ + mbedtls_printf( " . Loading the CA root certificate ..." ); + fflush( stdout ); #if defined(MBEDTLS_FS_IO) - if( strlen( opt.ca_path ) ) - if( strcmp( opt.ca_path, "none" ) == 0 ) - ret = 0; - else - ret = mbedtls_x509_crt_parse_path( &cacert, opt.ca_path ); - else if( strlen( opt.ca_file ) ) - if( strcmp( opt.ca_file, "none" ) == 0 ) - ret = 0; - else - ret = mbedtls_x509_crt_parse_file( &cacert, opt.ca_file ); - else + if( strlen( opt.ca_path ) ) + if( strcmp( opt.ca_path, "none" ) == 0 ) + ret = 0; + else + ret = mbedtls_x509_crt_parse_path( &cacert, opt.ca_path ); + else if( strlen( opt.ca_file ) ) + if( strcmp( opt.ca_file, "none" ) == 0 ) + ret = 0; + else + ret = mbedtls_x509_crt_parse_file( &cacert, opt.ca_file ); + else #endif #if defined(MBEDTLS_CERTS_C) - for( i = 0; mbedtls_test_cas[i] != NULL; i++ ) - { - ret = mbedtls_x509_crt_parse( &cacert, - (const unsigned char *) mbedtls_test_cas[i], - mbedtls_test_cas_len[i] ); - if( ret != 0 ) - break; - } + for( i = 0; mbedtls_test_cas[i] != NULL; i++ ) + { + ret = mbedtls_x509_crt_parse( &cacert, + (const unsigned char *) mbedtls_test_cas[i], + mbedtls_test_cas_len[i] ); + if( ret != 0 ) + break; + } #else - { - ret = 1; - mbedtls_printf("MBEDTLS_CERTS_C not defined."); - } + { + ret = 1; + mbedtls_printf("MBEDTLS_CERTS_C not defined."); + } #endif - if( ret < 0 ) - { - mbedtls_printf( " failed\n ! mbedtls_x509_crt_parse returned -0x%x\n\n", -ret ); - goto exit; - } - - mbedtls_printf( " ok (%d skipped)\n", ret ); - - /* - * 1.2. Load own certificate and private key - * - * (can be skipped if client authentication is not required) - */ - mbedtls_printf( " . Loading the client cert. and key..." ); - fflush( stdout ); + if( ret < 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_x509_crt_parse returned -0x%x\n\n", -ret ); + goto exit; + } + + mbedtls_printf( " ok (%d skipped)\n", ret ); + + /* + * 1.2. Load own certificate and private key + * + * (can be skipped if client authentication is not required) + */ + mbedtls_printf( " . Loading the client cert. and key..." ); + fflush( stdout ); #if defined(MBEDTLS_FS_IO) - if( strlen( opt.crt_file ) ) - if( strcmp( opt.crt_file, "none" ) == 0 ) - ret = 0; - else - ret = mbedtls_x509_crt_parse_file( &clicert, opt.crt_file ); - else + if( strlen( opt.crt_file ) ) + if( strcmp( opt.crt_file, "none" ) == 0 ) + ret = 0; + else + ret = mbedtls_x509_crt_parse_file( &clicert, opt.crt_file ); + else #endif #if defined(MBEDTLS_CERTS_C) - ret = mbedtls_x509_crt_parse( &clicert, (const unsigned char *) mbedtls_test_cli_crt, - mbedtls_test_cli_crt_len ); + ret = mbedtls_x509_crt_parse( &clicert, (const unsigned char *) mbedtls_test_cli_crt, + mbedtls_test_cli_crt_len ); #else - { - ret = 1; - mbedtls_printf("MBEDTLS_CERTS_C not defined."); - } + { + ret = 1; + mbedtls_printf("MBEDTLS_CERTS_C not defined."); + } #endif - if( ret != 0 ) - { - mbedtls_printf( " failed\n ! mbedtls_x509_crt_parse returned -0x%x\n\n", -ret ); - goto exit; - } + if( ret != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_x509_crt_parse returned -0x%x\n\n", -ret ); + goto exit; + } #if defined(MBEDTLS_FS_IO) - if( strlen( opt.key_file ) ) - if( strcmp( opt.key_file, "none" ) == 0 ) - ret = 0; - else - ret = mbedtls_pk_parse_keyfile( &pkey, opt.key_file, "" ); - else + if( strlen( opt.key_file ) ) + if( strcmp( opt.key_file, "none" ) == 0 ) + ret = 0; + else + ret = mbedtls_pk_parse_keyfile( &pkey, opt.key_file, "" ); + else #endif #if defined(MBEDTLS_CERTS_C) - ret = mbedtls_pk_parse_key( &pkey, (const unsigned char *) mbedtls_test_cli_key, - mbedtls_test_cli_key_len, NULL, 0 ); + ret = mbedtls_pk_parse_key( &pkey, (const unsigned char *) mbedtls_test_cli_key, + mbedtls_test_cli_key_len, NULL, 0 ); #else - { - ret = 1; - mbedtls_printf("MBEDTLS_CERTS_C not defined."); - } + { + ret = 1; + mbedtls_printf("MBEDTLS_CERTS_C not defined."); + } #endif - if( ret != 0 ) - { - mbedtls_printf( " failed\n ! mbedtls_pk_parse_key returned -0x%x\n\n", -ret ); - goto exit; - } + if( ret != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_pk_parse_key returned -0x%x\n\n", -ret ); + goto exit; + } - mbedtls_printf( " ok\n" ); + mbedtls_printf( " ok\n" ); #endif /* MBEDTLS_X509_CRT_PARSE_C */ - /* - * 2. Start the connection - */ - if( opt.server_addr == NULL) - opt.server_addr = opt.server_name; - - mbedtls_printf( " . Connecting to %s/%s/%s...", - opt.transport == MBEDTLS_SSL_TRANSPORT_STREAM ? "tcp" : "udp", - opt.server_addr, opt.server_port ); - fflush( stdout ); - - if( ( ret = mbedtls_net_connect( &server_fd, opt.server_addr, opt.server_port, - opt.transport == MBEDTLS_SSL_TRANSPORT_STREAM ? - MBEDTLS_NET_PROTO_TCP : MBEDTLS_NET_PROTO_UDP ) ) != 0 ) - { - mbedtls_printf( " failed\n ! mbedtls_net_connect returned -0x%x\n\n", -ret ); - goto exit; - } - - if( opt.nbio > 0 ) - ret = mbedtls_net_set_nonblock( &server_fd ); - else - ret = mbedtls_net_set_block( &server_fd ); - if( ret != 0 ) - { - mbedtls_printf( " failed\n ! net_set_(non)block() returned -0x%x\n\n", -ret ); - goto exit; - } - - mbedtls_printf( " ok\n" ); - - /* - * 3. Setup stuff - */ - mbedtls_printf( " . Setting up the SSL/TLS structure..." ); - fflush( stdout ); - - if( ( ret = mbedtls_ssl_config_defaults( &conf, - MBEDTLS_SSL_IS_CLIENT, - opt.transport, - MBEDTLS_SSL_PRESET_DEFAULT ) ) != 0 ) - { - mbedtls_printf( " failed\n ! mbedtls_ssl_config_defaults returned -0x%x\n\n", -ret ); - goto exit; - } + /* + * 2. Start the connection + */ + if( opt.server_addr == NULL) + opt.server_addr = opt.server_name; + + mbedtls_printf( " . Connecting to %s/%s/%s...", + opt.transport == MBEDTLS_SSL_TRANSPORT_STREAM ? "tcp" : "udp", + opt.server_addr, opt.server_port ); + fflush( stdout ); + + if( ( ret = mbedtls_net_connect( &server_fd, opt.server_addr, opt.server_port, + opt.transport == MBEDTLS_SSL_TRANSPORT_STREAM ? + MBEDTLS_NET_PROTO_TCP : MBEDTLS_NET_PROTO_UDP ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_net_connect returned -0x%x\n\n", -ret ); + goto exit; + } + + if( opt.nbio > 0 ) + ret = mbedtls_net_set_nonblock( &server_fd ); + else + ret = mbedtls_net_set_block( &server_fd ); + if( ret != 0 ) + { + mbedtls_printf( " failed\n ! net_set_(non)block() returned -0x%x\n\n", -ret ); + goto exit; + } + + mbedtls_printf( " ok\n" ); + + /* + * 3. Setup stuff + */ + mbedtls_printf( " . Setting up the SSL/TLS structure..." ); + fflush( stdout ); + + if( ( ret = mbedtls_ssl_config_defaults( &conf, + MBEDTLS_SSL_IS_CLIENT, + opt.transport, + MBEDTLS_SSL_PRESET_DEFAULT ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_config_defaults returned -0x%x\n\n", -ret ); + goto exit; + } #if defined(MBEDTLS_X509_CRT_PARSE_C) - if( opt.debug_level > 0 ) - mbedtls_ssl_conf_verify( &conf, my_verify, NULL ); + if( opt.debug_level > 0 ) + mbedtls_ssl_conf_verify( &conf, my_verify, NULL ); #endif - if( opt.auth_mode != DFL_AUTH_MODE ) - mbedtls_ssl_conf_authmode( &conf, opt.auth_mode ); + if( opt.auth_mode != DFL_AUTH_MODE ) + mbedtls_ssl_conf_authmode( &conf, opt.auth_mode ); #if defined(MBEDTLS_SSL_PROTO_DTLS) - if( opt.hs_to_min != DFL_HS_TO_MIN || opt.hs_to_max != DFL_HS_TO_MAX ) - mbedtls_ssl_conf_handshake_timeout( &conf, opt.hs_to_min, opt.hs_to_max ); + if( opt.hs_to_min != DFL_HS_TO_MIN || opt.hs_to_max != DFL_HS_TO_MAX ) + mbedtls_ssl_conf_handshake_timeout( &conf, opt.hs_to_min, opt.hs_to_max ); #endif /* MBEDTLS_SSL_PROTO_DTLS */ #if defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH) - if( ( ret = mbedtls_ssl_conf_max_frag_len( &conf, opt.mfl_code ) ) != 0 ) - { - mbedtls_printf( " failed\n ! mbedtls_ssl_conf_max_frag_len returned %d\n\n", ret ); - goto exit; - } + if( ( ret = mbedtls_ssl_conf_max_frag_len( &conf, opt.mfl_code ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_conf_max_frag_len returned %d\n\n", ret ); + goto exit; + } #endif #if defined(MBEDTLS_SSL_TRUNCATED_HMAC) - if( opt.trunc_hmac != DFL_TRUNC_HMAC ) - mbedtls_ssl_conf_truncated_hmac( &conf, opt.trunc_hmac ); + if( opt.trunc_hmac != DFL_TRUNC_HMAC ) + mbedtls_ssl_conf_truncated_hmac( &conf, opt.trunc_hmac ); #endif #if defined(MBEDTLS_SSL_EXTENDED_MASTER_SECRET) - if( opt.extended_ms != DFL_EXTENDED_MS ) - mbedtls_ssl_conf_extended_master_secret( &conf, opt.extended_ms ); + if( opt.extended_ms != DFL_EXTENDED_MS ) + mbedtls_ssl_conf_extended_master_secret( &conf, opt.extended_ms ); #endif #if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC) - if( opt.etm != DFL_ETM ) - mbedtls_ssl_conf_encrypt_then_mac( &conf, opt.etm ); + if( opt.etm != DFL_ETM ) + mbedtls_ssl_conf_encrypt_then_mac( &conf, opt.etm ); #endif #if defined(MBEDTLS_SSL_CBC_RECORD_SPLITTING) - if( opt.recsplit != DFL_RECSPLIT ) - mbedtls_ssl_conf_cbc_record_splitting( &conf, opt.recsplit - ? MBEDTLS_SSL_CBC_RECORD_SPLITTING_ENABLED - : MBEDTLS_SSL_CBC_RECORD_SPLITTING_DISABLED ); + if( opt.recsplit != DFL_RECSPLIT ) + mbedtls_ssl_conf_cbc_record_splitting( &conf, opt.recsplit + ? MBEDTLS_SSL_CBC_RECORD_SPLITTING_ENABLED + : MBEDTLS_SSL_CBC_RECORD_SPLITTING_DISABLED ); #endif #if defined(MBEDTLS_DHM_C) - if( opt.dhmlen != DFL_DHMLEN ) - mbedtls_ssl_conf_dhm_min_bitlen( &conf, opt.dhmlen ); + if( opt.dhmlen != DFL_DHMLEN ) + mbedtls_ssl_conf_dhm_min_bitlen( &conf, opt.dhmlen ); #endif #if defined(MBEDTLS_SSL_ALPN) - if( opt.alpn_string != NULL ) - if( ( ret = mbedtls_ssl_conf_alpn_protocols( &conf, alpn_list ) ) != 0 ) - { - mbedtls_printf( " failed\n ! mbedtls_ssl_conf_alpn_protocols returned %d\n\n", ret ); - goto exit; - } + if( opt.alpn_string != NULL ) + if( ( ret = mbedtls_ssl_conf_alpn_protocols( &conf, alpn_list ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_conf_alpn_protocols returned %d\n\n", ret ); + goto exit; + } #endif - mbedtls_ssl_conf_rng( &conf, mbedtls_ctr_drbg_random, &ctr_drbg ); - mbedtls_ssl_conf_dbg( &conf, my_debug, stdout ); + mbedtls_ssl_conf_rng( &conf, mbedtls_ctr_drbg_random, &ctr_drbg ); + mbedtls_ssl_conf_dbg( &conf, my_debug, stdout ); - mbedtls_ssl_conf_read_timeout( &conf, opt.read_timeout ); + mbedtls_ssl_conf_read_timeout( &conf, opt.read_timeout ); #if defined(MBEDTLS_SSL_SESSION_TICKETS) - mbedtls_ssl_conf_session_tickets( &conf, opt.tickets ); + mbedtls_ssl_conf_session_tickets( &conf, opt.tickets ); #endif - if( opt.force_ciphersuite[0] != DFL_FORCE_CIPHER ) - mbedtls_ssl_conf_ciphersuites( &conf, opt.force_ciphersuite ); + if( opt.force_ciphersuite[0] != DFL_FORCE_CIPHER ) + mbedtls_ssl_conf_ciphersuites( &conf, opt.force_ciphersuite ); #if defined(MBEDTLS_ARC4_C) - if( opt.arc4 != DFL_ARC4 ) - mbedtls_ssl_conf_arc4_support( &conf, opt.arc4 ); + if( opt.arc4 != DFL_ARC4 ) + mbedtls_ssl_conf_arc4_support( &conf, opt.arc4 ); #endif - if( opt.allow_legacy != DFL_ALLOW_LEGACY ) - mbedtls_ssl_conf_legacy_renegotiation( &conf, opt.allow_legacy ); + if( opt.allow_legacy != DFL_ALLOW_LEGACY ) + mbedtls_ssl_conf_legacy_renegotiation( &conf, opt.allow_legacy ); #if defined(MBEDTLS_SSL_RENEGOTIATION) - mbedtls_ssl_conf_renegotiation( &conf, opt.renegotiation ); + mbedtls_ssl_conf_renegotiation( &conf, opt.renegotiation ); #endif #if defined(MBEDTLS_X509_CRT_PARSE_C) - if( strcmp( opt.ca_path, "none" ) != 0 && - strcmp( opt.ca_file, "none" ) != 0 ) - { - mbedtls_ssl_conf_ca_chain( &conf, &cacert, NULL ); - } - if( strcmp( opt.crt_file, "none" ) != 0 && - strcmp( opt.key_file, "none" ) != 0 ) - { - if( ( ret = mbedtls_ssl_conf_own_cert( &conf, &clicert, &pkey ) ) != 0 ) - { - mbedtls_printf( " failed\n ! mbedtls_ssl_conf_own_cert returned %d\n\n", ret ); - goto exit; - } - } + if( strcmp( opt.ca_path, "none" ) != 0 && + strcmp( opt.ca_file, "none" ) != 0 ) + { + mbedtls_ssl_conf_ca_chain( &conf, &cacert, NULL ); + } + if( strcmp( opt.crt_file, "none" ) != 0 && + strcmp( opt.key_file, "none" ) != 0 ) + { + if( ( ret = mbedtls_ssl_conf_own_cert( &conf, &clicert, &pkey ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_conf_own_cert returned %d\n\n", ret ); + goto exit; + } + } #endif #if defined(MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED) - if( ( ret = mbedtls_ssl_conf_psk( &conf, psk, psk_len, - (const unsigned char *) opt.psk_identity, - strlen( opt.psk_identity ) ) ) != 0 ) - { - mbedtls_printf( " failed\n ! mbedtls_ssl_conf_psk returned %d\n\n", ret ); - goto exit; - } + if( ( ret = mbedtls_ssl_conf_psk( &conf, psk, psk_len, + (const unsigned char *) opt.psk_identity, + strlen( opt.psk_identity ) ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_conf_psk returned %d\n\n", ret ); + goto exit; + } #endif - if( opt.min_version != DFL_MIN_VERSION ) - mbedtls_ssl_conf_min_version( &conf, MBEDTLS_SSL_MAJOR_VERSION_3, opt.min_version ); + if( opt.min_version != DFL_MIN_VERSION ) + mbedtls_ssl_conf_min_version( &conf, MBEDTLS_SSL_MAJOR_VERSION_3, opt.min_version ); - if( opt.max_version != DFL_MAX_VERSION ) - mbedtls_ssl_conf_max_version( &conf, MBEDTLS_SSL_MAJOR_VERSION_3, opt.max_version ); + if( opt.max_version != DFL_MAX_VERSION ) + mbedtls_ssl_conf_max_version( &conf, MBEDTLS_SSL_MAJOR_VERSION_3, opt.max_version ); #if defined(MBEDTLS_SSL_FALLBACK_SCSV) - if( opt.fallback != DFL_FALLBACK ) - mbedtls_ssl_conf_fallback( &conf, opt.fallback ); + if( opt.fallback != DFL_FALLBACK ) + mbedtls_ssl_conf_fallback( &conf, opt.fallback ); #endif - if( ( ret = mbedtls_ssl_setup( &ssl, &conf ) ) != 0 ) - { - mbedtls_printf( " failed\n ! mbedtls_ssl_setup returned -0x%x\n\n", -ret ); - goto exit; - } + if( ( ret = mbedtls_ssl_setup( &ssl, &conf ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_setup returned -0x%x\n\n", -ret ); + goto exit; + } #if defined(MBEDTLS_X509_CRT_PARSE_C) - if( ( ret = mbedtls_ssl_set_hostname( &ssl, opt.server_name ) ) != 0 ) - { - mbedtls_printf( " failed\n ! mbedtls_ssl_set_hostname returned %d\n\n", ret ); - goto exit; - } + if( ( ret = mbedtls_ssl_set_hostname( &ssl, opt.server_name ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_set_hostname returned %d\n\n", ret ); + goto exit; + } #endif #if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) - if( opt.ecjpake_pw != DFL_ECJPAKE_PW ) - { - if( ( ret = mbedtls_ssl_set_hs_ecjpake_password( &ssl, - (const unsigned char *) opt.ecjpake_pw, - strlen( opt.ecjpake_pw ) ) ) != 0 ) - { - mbedtls_printf( " failed\n ! mbedtls_ssl_set_hs_ecjpake_password returned %d\n\n", ret ); - goto exit; - } - } + if( opt.ecjpake_pw != DFL_ECJPAKE_PW ) + { + if( ( ret = mbedtls_ssl_set_hs_ecjpake_password( &ssl, + (const unsigned char *) opt.ecjpake_pw, + strlen( opt.ecjpake_pw ) ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_set_hs_ecjpake_password returned %d\n\n", ret ); + goto exit; + } + } #endif - if( opt.nbio == 2 ) - mbedtls_ssl_set_bio( &ssl, &server_fd, my_send, my_recv, NULL ); - else - mbedtls_ssl_set_bio( &ssl, &server_fd, mbedtls_net_send, mbedtls_net_recv, - opt.nbio == 0 ? mbedtls_net_recv_timeout : NULL ); + if( opt.nbio == 2 ) + mbedtls_ssl_set_bio( &ssl, &server_fd, my_send, my_recv, NULL ); + else + mbedtls_ssl_set_bio( &ssl, &server_fd, mbedtls_net_send, mbedtls_net_recv, + opt.nbio == 0 ? mbedtls_net_recv_timeout : NULL ); #if defined(MBEDTLS_TIMING_C) - mbedtls_ssl_set_timer_cb( &ssl, &timer, mbedtls_timing_set_delay, - mbedtls_timing_get_delay ); + mbedtls_ssl_set_timer_cb( &ssl, &timer, mbedtls_timing_set_delay, + mbedtls_timing_get_delay ); #endif - mbedtls_printf( " ok\n" ); - - /* - * 4. Handshake - */ - mbedtls_printf( " . Performing the SSL/TLS handshake..." ); - fflush( stdout ); - - while( ( ret = mbedtls_ssl_handshake( &ssl ) ) != 0 ) - { - if( ret != MBEDTLS_ERR_SSL_WANT_READ && ret != MBEDTLS_ERR_SSL_WANT_WRITE ) - { - mbedtls_printf( " failed\n ! mbedtls_ssl_handshake returned -0x%x\n", -ret ); - if( ret == MBEDTLS_ERR_X509_CERT_VERIFY_FAILED ) - mbedtls_printf( - " Unable to verify the server's certificate. " - "Either it is invalid,\n" - " or you didn't set ca_file or ca_path " - "to an appropriate value.\n" - " Alternatively, you may want to use " - "auth_mode=optional for testing purposes.\n" ); - mbedtls_printf( "\n" ); - goto exit; - } - } - - mbedtls_printf( " ok\n [ Protocol is %s ]\n [ Ciphersuite is %s ]\n", - mbedtls_ssl_get_version( &ssl ), mbedtls_ssl_get_ciphersuite( &ssl ) ); - - if( ( ret = mbedtls_ssl_get_record_expansion( &ssl ) ) >= 0 ) - mbedtls_printf( " [ Record expansion is %d ]\n", ret ); - else - mbedtls_printf( " [ Record expansion is unknown (compression) ]\n" ); + mbedtls_printf( " ok\n" ); + + /* + * 4. Handshake + */ + mbedtls_printf( " . Performing the SSL/TLS handshake..." ); + fflush( stdout ); + + while( ( ret = mbedtls_ssl_handshake( &ssl ) ) != 0 ) + { + if( ret != MBEDTLS_ERR_SSL_WANT_READ && ret != MBEDTLS_ERR_SSL_WANT_WRITE ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_handshake returned -0x%x\n", -ret ); + if( ret == MBEDTLS_ERR_X509_CERT_VERIFY_FAILED ) + mbedtls_printf( + " Unable to verify the server's certificate. " + "Either it is invalid,\n" + " or you didn't set ca_file or ca_path " + "to an appropriate value.\n" + " Alternatively, you may want to use " + "auth_mode=optional for testing purposes.\n" ); + mbedtls_printf( "\n" ); + goto exit; + } + } + + mbedtls_printf( " ok\n [ Protocol is %s ]\n [ Ciphersuite is %s ]\n", + mbedtls_ssl_get_version( &ssl ), mbedtls_ssl_get_ciphersuite( &ssl ) ); + + if( ( ret = mbedtls_ssl_get_record_expansion( &ssl ) ) >= 0 ) + mbedtls_printf( " [ Record expansion is %d ]\n", ret ); + else + mbedtls_printf( " [ Record expansion is unknown (compression) ]\n" ); #if defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH) - mbedtls_printf( " [ Maximum fragment length is %u ]\n", - (unsigned int) mbedtls_ssl_get_max_frag_len( &ssl ) ); + mbedtls_printf( " [ Maximum fragment length is %u ]\n", + (unsigned int) mbedtls_ssl_get_max_frag_len( &ssl ) ); #endif #if defined(MBEDTLS_SSL_ALPN) - if( opt.alpn_string != NULL ) - { - const char *alp = mbedtls_ssl_get_alpn_protocol( &ssl ); - mbedtls_printf( " [ Application Layer Protocol is %s ]\n", - alp ? alp : "(none)" ); - } + if( opt.alpn_string != NULL ) + { + const char *alp = mbedtls_ssl_get_alpn_protocol( &ssl ); + mbedtls_printf( " [ Application Layer Protocol is %s ]\n", + alp ? alp : "(none)" ); + } #endif - if( opt.reconnect != 0 ) - { - mbedtls_printf(" . Saving session for reuse..." ); - fflush( stdout ); + if( opt.reconnect != 0 ) + { + mbedtls_printf(" . Saving session for reuse..." ); + fflush( stdout ); - if( ( ret = mbedtls_ssl_get_session( &ssl, &saved_session ) ) != 0 ) - { - mbedtls_printf( " failed\n ! mbedtls_ssl_get_session returned -0x%x\n\n", -ret ); - goto exit; - } + if( ( ret = mbedtls_ssl_get_session( &ssl, &saved_session ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_get_session returned -0x%x\n\n", -ret ); + goto exit; + } - mbedtls_printf( " ok\n" ); - } + mbedtls_printf( " ok\n" ); + } #if defined(MBEDTLS_X509_CRT_PARSE_C) - /* - * 5. Verify the server certificate - */ - mbedtls_printf( " . Verifying peer X.509 certificate..." ); - - if( ( flags = mbedtls_ssl_get_verify_result( &ssl ) ) != 0 ) - { - char vrfy_buf[512]; - - mbedtls_printf( " failed\n" ); - - mbedtls_x509_crt_verify_info( vrfy_buf, sizeof( vrfy_buf ), " ! ", flags ); - - mbedtls_printf( "%s\n", vrfy_buf ); - } - else - mbedtls_printf( " ok\n" ); - - if( mbedtls_ssl_get_peer_cert( &ssl ) != NULL ) - { - mbedtls_printf( " . Peer certificate information ...\n" ); - mbedtls_x509_crt_info( (char *) buf, sizeof( buf ) - 1, " ", - mbedtls_ssl_get_peer_cert( &ssl ) ); - mbedtls_printf( "%s\n", buf ); - } + /* + * 5. Verify the server certificate + */ + mbedtls_printf( " . Verifying peer X.509 certificate..." ); + + if( ( flags = mbedtls_ssl_get_verify_result( &ssl ) ) != 0 ) + { + char vrfy_buf[512]; + + mbedtls_printf( " failed\n" ); + + mbedtls_x509_crt_verify_info( vrfy_buf, sizeof( vrfy_buf ), " ! ", flags ); + + mbedtls_printf( "%s\n", vrfy_buf ); + } + else + mbedtls_printf( " ok\n" ); + + if( mbedtls_ssl_get_peer_cert( &ssl ) != NULL ) + { + mbedtls_printf( " . Peer certificate information ...\n" ); + mbedtls_x509_crt_info( (char *) buf, sizeof( buf ) - 1, " ", + mbedtls_ssl_get_peer_cert( &ssl ) ); + mbedtls_printf( "%s\n", buf ); + } #endif /* MBEDTLS_X509_CRT_PARSE_C */ #if defined(MBEDTLS_SSL_RENEGOTIATION) - if( opt.renegotiate ) - { - /* - * Perform renegotiation (this must be done when the server is waiting - * for input from our side). - */ - mbedtls_printf( " . Performing renegotiation..." ); - fflush( stdout ); - while( ( ret = mbedtls_ssl_renegotiate( &ssl ) ) != 0 ) - { - if( ret != MBEDTLS_ERR_SSL_WANT_READ && - ret != MBEDTLS_ERR_SSL_WANT_WRITE ) - { - mbedtls_printf( " failed\n ! mbedtls_ssl_renegotiate returned %d\n\n", ret ); - goto exit; - } - } - mbedtls_printf( " ok\n" ); - } + if( opt.renegotiate ) + { + /* + * Perform renegotiation (this must be done when the server is waiting + * for input from our side). + */ + mbedtls_printf( " . Performing renegotiation..." ); + fflush( stdout ); + while( ( ret = mbedtls_ssl_renegotiate( &ssl ) ) != 0 ) + { + if( ret != MBEDTLS_ERR_SSL_WANT_READ && + ret != MBEDTLS_ERR_SSL_WANT_WRITE ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_renegotiate returned %d\n\n", ret ); + goto exit; + } + } + mbedtls_printf( " ok\n" ); + } #endif /* MBEDTLS_SSL_RENEGOTIATION */ - /* - * 6. Write the GET request - */ - retry_left = opt.max_resend; + /* + * 6. Write the GET request + */ + retry_left = opt.max_resend; send_request: - mbedtls_printf( " > Write to server:" ); - fflush( stdout ); - - len = mbedtls_snprintf( (char *) buf, sizeof(buf) - 1, GET_REQUEST, - opt.request_page ); - tail_len = (int) strlen( GET_REQUEST_END ); - - /* Add padding to GET request to reach opt.request_size in length */ - if( opt.request_size != DFL_REQUEST_SIZE && - len + tail_len < opt.request_size ) - { - memset( buf + len, 'A', opt.request_size - len - tail_len ); - len += opt.request_size - len - tail_len; - } - - strncpy( (char *) buf + len, GET_REQUEST_END, sizeof(buf) - len - 1 ); - len += tail_len; - - /* Truncate if request size is smaller than the "natural" size */ - if( opt.request_size != DFL_REQUEST_SIZE && - len > opt.request_size ) - { - len = opt.request_size; - - /* Still end with \r\n unless that's really not possible */ - if( len >= 2 ) buf[len - 2] = '\r'; - if( len >= 1 ) buf[len - 1] = '\n'; - } - - if( opt.transport == MBEDTLS_SSL_TRANSPORT_STREAM ) - { - for( written = 0, frags = 0; written < len; written += ret, frags++ ) - { - while( ( ret = mbedtls_ssl_write( &ssl, buf + written, len - written ) ) - <= 0 ) - { - if( ret != MBEDTLS_ERR_SSL_WANT_READ && - ret != MBEDTLS_ERR_SSL_WANT_WRITE ) - { - mbedtls_printf( " failed\n ! mbedtls_ssl_write returned -0x%x\n\n", -ret ); - goto exit; - } - } - } - } - else /* Not stream, so datagram */ - { - do ret = mbedtls_ssl_write( &ssl, buf, len ); - while( ret == MBEDTLS_ERR_SSL_WANT_READ || - ret == MBEDTLS_ERR_SSL_WANT_WRITE ); - - if( ret < 0 ) - { - mbedtls_printf( " failed\n ! mbedtls_ssl_write returned %d\n\n", ret ); - goto exit; - } - - frags = 1; - written = ret; - } - - buf[written] = '\0'; - mbedtls_printf( " %d bytes written in %d fragments\n\n%s\n", written, frags, (char *) buf ); - - /* - * 7. Read the HTTP response - */ - mbedtls_printf( " < Read from server:" ); - fflush( stdout ); - - /* - * TLS and DTLS need different reading styles (stream vs datagram) - */ - if( opt.transport == MBEDTLS_SSL_TRANSPORT_STREAM ) - { - do - { - len = sizeof( buf ) - 1; - memset( buf, 0, sizeof( buf ) ); - ret = mbedtls_ssl_read( &ssl, buf, len ); - - if( ret == MBEDTLS_ERR_SSL_WANT_READ || - ret == MBEDTLS_ERR_SSL_WANT_WRITE ) - continue; - - if( ret <= 0 ) - { - switch( ret ) - { - case MBEDTLS_ERR_SSL_PEER_CLOSE_NOTIFY: - mbedtls_printf( " connection was closed gracefully\n" ); - ret = 0; - goto close_notify; - - case 0: - case MBEDTLS_ERR_NET_CONN_RESET: - mbedtls_printf( " connection was reset by peer\n" ); - ret = 0; - goto reconnect; - - default: - mbedtls_printf( " mbedtls_ssl_read returned -0x%x\n", -ret ); - goto exit; - } - } - - len = ret; - buf[len] = '\0'; - mbedtls_printf( " %d bytes read\n\n%s", len, (char *) buf ); - - /* End of message should be detected according to the syntax of the - * application protocol (eg HTTP), just use a dummy test here. */ - if( ret > 0 && buf[len-1] == '\n' ) - { - ret = 0; - break; - } - } - while( 1 ); - } - else /* Not stream, so datagram */ - { - len = sizeof( buf ) - 1; - memset( buf, 0, sizeof( buf ) ); - - do ret = mbedtls_ssl_read( &ssl, buf, len ); - while( ret == MBEDTLS_ERR_SSL_WANT_READ || - ret == MBEDTLS_ERR_SSL_WANT_WRITE ); - - if( ret <= 0 ) - { - switch( ret ) - { - case MBEDTLS_ERR_SSL_TIMEOUT: - mbedtls_printf( " timeout\n" ); - if( retry_left-- > 0 ) - goto send_request; - goto exit; - - case MBEDTLS_ERR_SSL_PEER_CLOSE_NOTIFY: - mbedtls_printf( " connection was closed gracefully\n" ); - ret = 0; - goto close_notify; - - default: - mbedtls_printf( " mbedtls_ssl_read returned -0x%x\n", -ret ); - goto exit; - } - } - - len = ret; - buf[len] = '\0'; - mbedtls_printf( " %d bytes read\n\n%s", len, (char *) buf ); - ret = 0; - } - - /* - * 7b. Simulate hard reset and reconnect from same port? - */ - if( opt.reconnect_hard != 0 ) - { - opt.reconnect_hard = 0; - - mbedtls_printf( " . Restarting connection from same port..." ); - fflush( stdout ); - - if( ( ret = mbedtls_ssl_session_reset( &ssl ) ) != 0 ) - { - mbedtls_printf( " failed\n ! mbedtls_ssl_session_reset returned -0x%x\n\n", -ret ); - goto exit; - } - - while( ( ret = mbedtls_ssl_handshake( &ssl ) ) != 0 ) - { - if( ret != MBEDTLS_ERR_SSL_WANT_READ && - ret != MBEDTLS_ERR_SSL_WANT_WRITE ) - { - mbedtls_printf( " failed\n ! mbedtls_ssl_handshake returned -0x%x\n\n", -ret ); - goto exit; - } - } - - mbedtls_printf( " ok\n" ); - - goto send_request; - } - - /* - * 7c. Continue doing data exchanges? - */ - if( --opt.exchanges > 0 ) - goto send_request; - - /* - * 8. Done, cleanly close the connection - */ + mbedtls_printf( " > Write to server:" ); + fflush( stdout ); + + len = mbedtls_snprintf( (char *) buf, sizeof(buf) - 1, GET_REQUEST, + opt.request_page ); + tail_len = (int) strlen( GET_REQUEST_END ); + + /* Add padding to GET request to reach opt.request_size in length */ + if( opt.request_size != DFL_REQUEST_SIZE && + len + tail_len < opt.request_size ) + { + memset( buf + len, 'A', opt.request_size - len - tail_len ); + len += opt.request_size - len - tail_len; + } + + strncpy( (char *) buf + len, GET_REQUEST_END, sizeof(buf) - len - 1 ); + len += tail_len; + + /* Truncate if request size is smaller than the "natural" size */ + if( opt.request_size != DFL_REQUEST_SIZE && + len > opt.request_size ) + { + len = opt.request_size; + + /* Still end with \r\n unless that's really not possible */ + if( len >= 2 ) buf[len - 2] = '\r'; + if( len >= 1 ) buf[len - 1] = '\n'; + } + + if( opt.transport == MBEDTLS_SSL_TRANSPORT_STREAM ) + { + for( written = 0, frags = 0; written < len; written += ret, frags++ ) + { + while( ( ret = mbedtls_ssl_write( &ssl, buf + written, len - written ) ) + <= 0 ) + { + if( ret != MBEDTLS_ERR_SSL_WANT_READ && + ret != MBEDTLS_ERR_SSL_WANT_WRITE ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_write returned -0x%x\n\n", -ret ); + goto exit; + } + } + } + } + else /* Not stream, so datagram */ + { + do ret = mbedtls_ssl_write( &ssl, buf, len ); + while( ret == MBEDTLS_ERR_SSL_WANT_READ || + ret == MBEDTLS_ERR_SSL_WANT_WRITE ); + + if( ret < 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_write returned %d\n\n", ret ); + goto exit; + } + + frags = 1; + written = ret; + } + + buf[written] = '\0'; + mbedtls_printf( " %d bytes written in %d fragments\n\n%s\n", written, frags, (char *) buf ); + + /* + * 7. Read the HTTP response + */ + mbedtls_printf( " < Read from server:" ); + fflush( stdout ); + + /* + * TLS and DTLS need different reading styles (stream vs datagram) + */ + if( opt.transport == MBEDTLS_SSL_TRANSPORT_STREAM ) + { + do + { + len = sizeof( buf ) - 1; + memset( buf, 0, sizeof( buf ) ); + ret = mbedtls_ssl_read( &ssl, buf, len ); + + if( ret == MBEDTLS_ERR_SSL_WANT_READ || + ret == MBEDTLS_ERR_SSL_WANT_WRITE ) + continue; + + if( ret <= 0 ) + { + switch( ret ) + { + case MBEDTLS_ERR_SSL_PEER_CLOSE_NOTIFY: + mbedtls_printf( " connection was closed gracefully\n" ); + ret = 0; + goto close_notify; + + case 0: + case MBEDTLS_ERR_NET_CONN_RESET: + mbedtls_printf( " connection was reset by peer\n" ); + ret = 0; + goto reconnect; + + default: + mbedtls_printf( " mbedtls_ssl_read returned -0x%x\n", -ret ); + goto exit; + } + } + + len = ret; + buf[len] = '\0'; + mbedtls_printf( " %d bytes read\n\n%s", len, (char *) buf ); + + /* End of message should be detected according to the syntax of the + * application protocol (eg HTTP), just use a dummy test here. */ + if( ret > 0 && buf[len-1] == '\n' ) + { + ret = 0; + break; + } + } + while( 1 ); + } + else /* Not stream, so datagram */ + { + len = sizeof( buf ) - 1; + memset( buf, 0, sizeof( buf ) ); + + do ret = mbedtls_ssl_read( &ssl, buf, len ); + while( ret == MBEDTLS_ERR_SSL_WANT_READ || + ret == MBEDTLS_ERR_SSL_WANT_WRITE ); + + if( ret <= 0 ) + { + switch( ret ) + { + case MBEDTLS_ERR_SSL_TIMEOUT: + mbedtls_printf( " timeout\n" ); + if( retry_left-- > 0 ) + goto send_request; + goto exit; + + case MBEDTLS_ERR_SSL_PEER_CLOSE_NOTIFY: + mbedtls_printf( " connection was closed gracefully\n" ); + ret = 0; + goto close_notify; + + default: + mbedtls_printf( " mbedtls_ssl_read returned -0x%x\n", -ret ); + goto exit; + } + } + + len = ret; + buf[len] = '\0'; + mbedtls_printf( " %d bytes read\n\n%s", len, (char *) buf ); + ret = 0; + } + + /* + * 7b. Simulate hard reset and reconnect from same port? + */ + if( opt.reconnect_hard != 0 ) + { + opt.reconnect_hard = 0; + + mbedtls_printf( " . Restarting connection from same port..." ); + fflush( stdout ); + + if( ( ret = mbedtls_ssl_session_reset( &ssl ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_session_reset returned -0x%x\n\n", -ret ); + goto exit; + } + + while( ( ret = mbedtls_ssl_handshake( &ssl ) ) != 0 ) + { + if( ret != MBEDTLS_ERR_SSL_WANT_READ && + ret != MBEDTLS_ERR_SSL_WANT_WRITE ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_handshake returned -0x%x\n\n", -ret ); + goto exit; + } + } + + mbedtls_printf( " ok\n" ); + + goto send_request; + } + + /* + * 7c. Continue doing data exchanges? + */ + if( --opt.exchanges > 0 ) + goto send_request; + + /* + * 8. Done, cleanly close the connection + */ close_notify: - mbedtls_printf( " . Closing the connection..." ); - fflush( stdout ); + mbedtls_printf( " . Closing the connection..." ); + fflush( stdout ); - /* No error checking, the connection might be closed already */ - do ret = mbedtls_ssl_close_notify( &ssl ); - while( ret == MBEDTLS_ERR_SSL_WANT_WRITE ); - ret = 0; + /* No error checking, the connection might be closed already */ + do ret = mbedtls_ssl_close_notify( &ssl ); + while( ret == MBEDTLS_ERR_SSL_WANT_WRITE ); + ret = 0; - mbedtls_printf( " done\n" ); + mbedtls_printf( " done\n" ); - /* - * 9. Reconnect? - */ + /* + * 9. Reconnect? + */ reconnect: - if( opt.reconnect != 0 ) - { - --opt.reconnect; + if( opt.reconnect != 0 ) + { + --opt.reconnect; - mbedtls_net_free( &server_fd ); + mbedtls_net_free( &server_fd ); #if defined(MBEDTLS_TIMING_C) - if( opt.reco_delay > 0 ) - mbedtls_net_usleep( 1000000 * opt.reco_delay ); + if( opt.reco_delay > 0 ) + mbedtls_net_usleep( 1000000 * opt.reco_delay ); #endif - mbedtls_printf( " . Reconnecting with saved session..." ); - - if( ( ret = mbedtls_ssl_session_reset( &ssl ) ) != 0 ) - { - mbedtls_printf( " failed\n ! mbedtls_ssl_session_reset returned -0x%x\n\n", -ret ); - goto exit; - } - - if( ( ret = mbedtls_ssl_set_session( &ssl, &saved_session ) ) != 0 ) - { - mbedtls_printf( " failed\n ! mbedtls_ssl_conf_session returned %d\n\n", ret ); - goto exit; - } - - if( ( ret = mbedtls_net_connect( &server_fd, opt.server_addr, opt.server_port, - opt.transport == MBEDTLS_SSL_TRANSPORT_STREAM ? - MBEDTLS_NET_PROTO_TCP : MBEDTLS_NET_PROTO_UDP ) ) != 0 ) - { - mbedtls_printf( " failed\n ! mbedtls_net_connect returned -0x%x\n\n", -ret ); - goto exit; - } - - if( opt.nbio > 0 ) - ret = mbedtls_net_set_nonblock( &server_fd ); - else - ret = mbedtls_net_set_block( &server_fd ); - if( ret != 0 ) - { - mbedtls_printf( " failed\n ! net_set_(non)block() returned -0x%x\n\n", - -ret ); - goto exit; - } - - while( ( ret = mbedtls_ssl_handshake( &ssl ) ) != 0 ) - { - if( ret != MBEDTLS_ERR_SSL_WANT_READ && - ret != MBEDTLS_ERR_SSL_WANT_WRITE ) - { - mbedtls_printf( " failed\n ! mbedtls_ssl_handshake returned -0x%x\n\n", -ret ); - goto exit; - } - } - - mbedtls_printf( " ok\n" ); - - goto send_request; - } - - /* - * Cleanup and exit - */ + mbedtls_printf( " . Reconnecting with saved session..." ); + + if( ( ret = mbedtls_ssl_session_reset( &ssl ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_session_reset returned -0x%x\n\n", -ret ); + goto exit; + } + + if( ( ret = mbedtls_ssl_set_session( &ssl, &saved_session ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_conf_session returned %d\n\n", ret ); + goto exit; + } + + if( ( ret = mbedtls_net_connect( &server_fd, opt.server_addr, opt.server_port, + opt.transport == MBEDTLS_SSL_TRANSPORT_STREAM ? + MBEDTLS_NET_PROTO_TCP : MBEDTLS_NET_PROTO_UDP ) ) != 0 ) + { + mbedtls_printf( " failed\n ! mbedtls_net_connect returned -0x%x\n\n", -ret ); + goto exit; + } + + if( opt.nbio > 0 ) + ret = mbedtls_net_set_nonblock( &server_fd ); + else + ret = mbedtls_net_set_block( &server_fd ); + if( ret != 0 ) + { + mbedtls_printf( " failed\n ! net_set_(non)block() returned -0x%x\n\n", + -ret ); + goto exit; + } + + while( ( ret = mbedtls_ssl_handshake( &ssl ) ) != 0 ) + { + if( ret != MBEDTLS_ERR_SSL_WANT_READ && + ret != MBEDTLS_ERR_SSL_WANT_WRITE ) + { + mbedtls_printf( " failed\n ! mbedtls_ssl_handshake returned -0x%x\n\n", -ret ); + goto exit; + } + } + + mbedtls_printf( " ok\n" ); + + goto send_request; + } + + /* + * Cleanup and exit + */ exit: #ifdef MBEDTLS_ERROR_C - if( ret != 0 ) - { - char error_buf[100]; - mbedtls_strerror( ret, error_buf, 100 ); - mbedtls_printf("Last error was: -0x%X - %s\n\n", -ret, error_buf ); - } + if( ret != 0 ) + { + char error_buf[100]; + mbedtls_strerror( ret, error_buf, 100 ); + mbedtls_printf("Last error was: -0x%X - %s\n\n", -ret, error_buf ); + } #endif - mbedtls_net_free( &server_fd ); + mbedtls_net_free( &server_fd ); #if defined(MBEDTLS_X509_CRT_PARSE_C) - mbedtls_x509_crt_free( &clicert ); - mbedtls_x509_crt_free( &cacert ); - mbedtls_pk_free( &pkey ); + mbedtls_x509_crt_free( &clicert ); + mbedtls_x509_crt_free( &cacert ); + mbedtls_pk_free( &pkey ); #endif - mbedtls_ssl_session_free( &saved_session ); - mbedtls_ssl_free( &ssl ); - mbedtls_ssl_config_free( &conf ); - mbedtls_ctr_drbg_free( &ctr_drbg ); - mbedtls_entropy_free( &entropy ); + mbedtls_ssl_session_free( &saved_session ); + mbedtls_ssl_free( &ssl ); + mbedtls_ssl_config_free( &conf ); + mbedtls_ctr_drbg_free( &ctr_drbg ); + mbedtls_entropy_free( &entropy ); #if defined(_WIN32) - mbedtls_printf( " + Press Enter to exit this program.\n" ); - fflush( stdout ); getchar(); + mbedtls_printf( " + Press Enter to exit this program.\n" ); + fflush( stdout ); getchar(); #endif - // Shell can not handle large exit numbers -> 1 for errors - if( ret < 0 ) - ret = 1; + // Shell can not handle large exit numbers -> 1 for errors + if( ret < 0 ) + ret = 1; - return( ret ); + return( ret ); } #endif /* MBEDTLS_BIGNUM_C && MBEDTLS_ENTROPY_C && MBEDTLS_SSL_TLS_C && - MBEDTLS_SSL_CLI_C && MBEDTLS_NET_C && MBEDTLS_RSA_C && - MBEDTLS_CTR_DRBG_C MBEDTLS_TIMING_C */ + MBEDTLS_SSL_CLI_C && MBEDTLS_NET_C && MBEDTLS_RSA_C && + MBEDTLS_CTR_DRBG_C MBEDTLS_TIMING_C */ diff --git a/example/freertos/sec/mbedtls/ssl/server2/makefile b/example/freertos/sec/mbedtls/ssl/server2/makefile index def58166b..602e44933 100644 --- a/example/freertos/sec/mbedtls/ssl/server2/makefile +++ b/example/freertos/sec/mbedtls/ssl/server2/makefile @@ -6,13 +6,19 @@ BOARD ?= emsk ifeq ($(BOARD), emsdp) EXT_DEV_LIST += wifi/rs9113 else -EXT_DEV_LIST += wifi/mrf24g +EXT_DEV_LIST += wifi/mrf24g sensor/temperature/adt7420 endif # Heap Size Settings -HEAPSZ ?= 8192 +HEAPSZ ?= 1024*96 STACKSZ ?= 2048 +APPL_DEFINES += -DNTCONF_EDITOR_MAXLEN=256 -DMBEDTLS_CONFIG_FILE=\"mbedtls_config.h\" \ + -DTASK_STACK_SIZE_WIFI=1024 \ + -DTASK_STACK_SIZE_NTSHELL=4096 \ + -DNTSHELL_USE_CMDS_ARC=0 \ + -DNTSHELL_USE_CMDS_PERIPHERAL=0 + # # root dir of embARC # diff --git a/example/freertos/sec/mbedtls/ssl/server2/ssl_server2.c b/example/freertos/sec/mbedtls/ssl/server2/ssl_server2.c index b586a7008..2226946ca 100644 --- a/example/freertos/sec/mbedtls/ssl/server2/ssl_server2.c +++ b/example/freertos/sec/mbedtls/ssl/server2/ssl_server2.c @@ -774,61 +774,62 @@ void term_handler( int sig ) } #endif -int main( int argc, char *argv[] ) -{ - int ret = 0, len, written, frags, exchanges_left; - int version_suites[4][2]; - unsigned char buf[IO_BUF_LEN]; +unsigned char buf[IO_BUF_LEN]; #if defined(MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED) - unsigned char psk[MBEDTLS_PSK_MAX_LEN]; - size_t psk_len = 0; - psk_entry *psk_info = NULL; +unsigned char psk[MBEDTLS_PSK_MAX_LEN]; +size_t psk_len = 0; +psk_entry *psk_info = NULL; #endif - const char *pers = "ssl_server2"; - unsigned char client_ip[16] = { 0 }; - size_t cliip_len; +const char *pers = "ssl_server2"; +unsigned char client_ip[16] = { 0 }; +size_t cliip_len; #if defined(MBEDTLS_SSL_COOKIE_C) - mbedtls_ssl_cookie_ctx cookie_ctx; +mbedtls_ssl_cookie_ctx cookie_ctx; #endif - - mbedtls_entropy_context entropy; - mbedtls_ctr_drbg_context ctr_drbg; - mbedtls_ssl_context ssl; - mbedtls_ssl_config conf; +mbedtls_entropy_context entropy; +mbedtls_ctr_drbg_context ctr_drbg; +mbedtls_ssl_context ssl; +mbedtls_ssl_config conf; #if defined(MBEDTLS_TIMING_C) - mbedtls_timing_delay_context timer; +mbedtls_timing_delay_context timer; #endif #if defined(MBEDTLS_SSL_RENEGOTIATION) - unsigned char renego_period[8] = { 0 }; +unsigned char renego_period[8] = { 0 }; #endif #if defined(MBEDTLS_X509_CRT_PARSE_C) - uint32_t flags; - mbedtls_x509_crt cacert; - mbedtls_x509_crt srvcert; - mbedtls_pk_context pkey; - mbedtls_x509_crt srvcert2; - mbedtls_pk_context pkey2; - int key_cert_init = 0, key_cert_init2 = 0; +uint32_t flags; +mbedtls_x509_crt cacert; +mbedtls_x509_crt srvcert; +mbedtls_pk_context pkey; +mbedtls_x509_crt srvcert2; +mbedtls_pk_context pkey2; +int key_cert_init = 0, key_cert_init2 = 0; #endif #if defined(MBEDTLS_DHM_C) && defined(MBEDTLS_FS_IO) - mbedtls_dhm_context dhm; +mbedtls_dhm_context dhm; #endif #if defined(MBEDTLS_SSL_CACHE_C) - mbedtls_ssl_cache_context cache; +mbedtls_ssl_cache_context cache; #endif #if defined(MBEDTLS_SSL_SESSION_TICKETS) - mbedtls_ssl_ticket_context ticket_ctx; +mbedtls_ssl_ticket_context ticket_ctx; #endif #if defined(SNI_OPTION) - sni_entry *sni_info = NULL; +sni_entry *sni_info = NULL; #endif #if defined(MBEDTLS_SSL_ALPN) - const char *alpn_list[10]; +const char *alpn_list[10]; #endif #if defined(MBEDTLS_MEMORY_BUFFER_ALLOC_C) - unsigned char alloc_buf[100000]; +unsigned char alloc_buf[100000]; #endif +int main( int argc, char *argv[] ) +{ + int ret = 0, len, written, frags, exchanges_left; + int version_suites[4][2]; + + int i; char *p, *q; const int *list; diff --git a/middleware/mbedtls/0001-Add-embARC-FreeRTOS-LwIP-support-to-mbedtls.patch b/middleware/mbedtls/0001-Add-embARC-FreeRTOS-LwIP-support-to-mbedtls.patch index 4b6617bfa..e7338ab8c 100644 --- a/middleware/mbedtls/0001-Add-embARC-FreeRTOS-LwIP-support-to-mbedtls.patch +++ b/middleware/mbedtls/0001-Add-embARC-FreeRTOS-LwIP-support-to-mbedtls.patch @@ -1,37 +1,37 @@ -From cb4bf4d8b82dcfcb5049ae3a25d6ce7e72859ed2 Mon Sep 17 00:00:00 2001 +From 0d228d14b1fb16f909ab03ff45b4635b90494ca8 Mon Sep 17 00:00:00 2001 From: XiangcaiHuang Date: Thu, 17 Aug 2017 11:21:12 +0800 Subject: [PATCH 1/2] Add embARC (FreeRTOS+LwIP) support to mbedtls --- - library/net_sockets.c => embARC/net_alt.c | 94 ++------------- + library/net_sockets.c => embARC/net_alt.c | 99 ++-------------- embARC/threading_alt.c | 80 +++++++++++++ embARC/threading_alt.h | 65 +++++++++++ embARC/timing_alt.c | 111 ++++++++++++++++++ embARC/timing_alt.h | 136 ++++++++++++++++++++++ - library/ssl_srv.c | 2 + - library/ssl_tls.c | 21 +++- + library/ssl_tls.c | 18 +++ library/threading.c | 11 ++ - 8 files changed, 434 insertions(+), 86 deletions(-) - rename library/net_sockets.c => embARC/net_alt.c (85%) + 7 files changed, 431 insertions(+), 89 deletions(-) + rename library/net_sockets.c => embARC/net_alt.c (86%) create mode 100644 embARC/threading_alt.c create mode 100644 embARC/threading_alt.h create mode 100644 embARC/timing_alt.c create mode 100644 embARC/timing_alt.h diff --git a/library/net_sockets.c b/embARC/net_alt.c -similarity index 85% +similarity index 86% rename from library/net_sockets.c rename to embARC/net_alt.c -index cc06cbfad..5c0bf0c83 100644 +index 816b1303d..751ec3cb3 100644 --- a/library/net_sockets.c +++ b/embARC/net_alt.c -@@ -27,98 +27,26 @@ +@@ -32,104 +32,29 @@ #if defined(MBEDTLS_NET_C) -#if !defined(unix) && !defined(__unix__) && !defined(__unix) && \ -- !defined(__APPLE__) && !defined(_WIN32) +- !defined(__APPLE__) && !defined(_WIN32) && !defined(__QNXNTO__) && \ +- !defined(__HAIKU__) -#error "This module only works on Unix and Windows, see MBEDTLS_NET_C in config.h" -#endif - @@ -45,15 +45,18 @@ index cc06cbfad..5c0bf0c83 100644 +#include "mbedtls/net.h" #include -- + -#if (defined(_WIN32) || defined(_WIN32_WCE)) && !defined(EFIX64) && \ - !defined(EFI32) - --#ifdef _WIN32_WINNT +-#define IS_EINTR( ret ) ( ( ret ) == WSAEINTR ) +- +-#if !defined(_WIN32_WINNT) || (_WIN32_WINNT < 0x0501) -#undef _WIN32_WINNT --#endif -/* Enables getaddrinfo() & Co */ -#define _WIN32_WINNT 0x0501 +-#endif +- -#include - -#include @@ -67,8 +70,8 @@ index cc06cbfad..5c0bf0c83 100644 -#endif -#endif /* _MSC_VER */ - --#define read(fd,buf,len) recv(fd,(char*)buf,(int) len,0) --#define write(fd,buf,len) send(fd,(char*)buf,(int) len,0) +-#define read(fd,buf,len) recv( fd, (char*)( buf ), (int)( len ), 0 ) +-#define write(fd,buf,len) send( fd, (char*)( buf ), (int)( len ), 0 ) -#define close(fd) closesocket(fd) - -static int wsa_init_done = 0; @@ -86,10 +89,12 @@ index cc06cbfad..5c0bf0c83 100644 #include #include + #define IS_EINTR( ret ) ( ( ret ) == EINTR ) + -#endif /* ( _WIN32 || _WIN32_WCE ) && !EFIX64 && !EFI32 */ - -/* Some MS functions want int and MSVC warns if we pass size_t, -- * but the standard fucntions use socklen_t, so cast only for MSVC */ +- * but the standard functions use socklen_t, so cast only for MSVC */ -#if defined(_MSC_VER) -#define MSVC_INT_CAST (int) -#else @@ -129,16 +134,20 @@ index cc06cbfad..5c0bf0c83 100644 return( 0 ); } -@@ -272,7 +200,7 @@ static int net_would_block( const mbedtls_net_context *ctx ) +@@ -286,10 +211,10 @@ static int net_would_block( const mbedtls_net_context *ctx ) /* * Never return 'WOULD BLOCK' on a non-blocking socket */ - if( ( fcntl( ctx->fd, F_GETFL ) & O_NONBLOCK ) != O_NONBLOCK ) + if( ( fcntl( ctx->fd, F_GETFL, 0 ) & O_NONBLOCK ) != O_NONBLOCK ) - return( 0 ); + { + errno = err; +- return( 0 ); ++ return ( 0 ); + } - switch( errno ) -@@ -301,14 +229,8 @@ int mbedtls_net_accept( mbedtls_net_context *bind_ctx, + switch( errno = err ) +@@ -318,14 +243,8 @@ int mbedtls_net_accept( mbedtls_net_context *bind_ctx, struct sockaddr_storage client_addr; @@ -153,7 +162,7 @@ index cc06cbfad..5c0bf0c83 100644 /* Is this a TCP or UDP socket? */ if( getsockopt( bind_ctx->fd, SOL_SOCKET, SO_TYPE, -@@ -394,6 +316,7 @@ int mbedtls_net_accept( mbedtls_net_context *bind_ctx, +@@ -411,6 +330,7 @@ int mbedtls_net_accept( mbedtls_net_context *bind_ctx, } else { @@ -161,7 +170,7 @@ index cc06cbfad..5c0bf0c83 100644 struct sockaddr_in6 *addr6 = (struct sockaddr_in6 *) &client_addr; *ip_len = sizeof( addr6->sin6_addr.s6_addr ); -@@ -401,6 +324,7 @@ int mbedtls_net_accept( mbedtls_net_context *bind_ctx, +@@ -418,6 +338,7 @@ int mbedtls_net_accept( mbedtls_net_context *bind_ctx, return( MBEDTLS_ERR_NET_BUFFER_TOO_SMALL ); memcpy( client_ip, &addr6->sin6_addr.s6_addr, *ip_len); @@ -169,7 +178,7 @@ index cc06cbfad..5c0bf0c83 100644 } } -@@ -417,7 +341,7 @@ int mbedtls_net_set_block( mbedtls_net_context *ctx ) +@@ -434,7 +355,7 @@ int mbedtls_net_set_block( mbedtls_net_context *ctx ) u_long n = 0; return( ioctlsocket( ctx->fd, FIONBIO, &n ) ); #else @@ -178,7 +187,7 @@ index cc06cbfad..5c0bf0c83 100644 #endif } -@@ -428,7 +352,7 @@ int mbedtls_net_set_nonblock( mbedtls_net_context *ctx ) +@@ -445,7 +366,7 @@ int mbedtls_net_set_nonblock( mbedtls_net_context *ctx ) u_long n = 1; return( ioctlsocket( ctx->fd, FIONBIO, &n ) ); #else @@ -604,24 +613,11 @@ index 000000000..151765d34 +#endif + +#endif /* timing.h */ -diff --git a/library/ssl_srv.c b/library/ssl_srv.c -index fc0d2d7b4..b5ea02c5d 100644 ---- a/library/ssl_srv.c -+++ b/library/ssl_srv.c -@@ -3016,6 +3016,8 @@ curve_matching_done: - #endif /* MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED) || - MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED || - MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED */ -+ // mask dead store of p -+ (void)p; - - ssl->out_msglen = 4 + n; - ssl->out_msgtype = MBEDTLS_SSL_MSG_HANDSHAKE; diff --git a/library/ssl_tls.c b/library/ssl_tls.c -index 84a04ae53..2153c80ab 100644 +index 38690fa66..fbdfc7683 100644 --- a/library/ssl_tls.c +++ b/library/ssl_tls.c -@@ -3608,6 +3608,24 @@ static int ssl_parse_record_header( mbedtls_ssl_context *ssl ) +@@ -4119,6 +4119,24 @@ static int ssl_parse_record_header( mbedtls_ssl_context *ssl ) "expected %d, received %d", ssl->in_epoch, rec_epoch ) ); @@ -646,21 +642,11 @@ index 84a04ae53..2153c80ab 100644 #if defined(MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE) && defined(MBEDTLS_SSL_SRV_C) /* * Check for an epoch 0 ClientHello. We can't use in_msg here to -@@ -3737,7 +3755,8 @@ int mbedtls_ssl_read_record( mbedtls_ssl_context *ssl ) - - ret = mbedtls_ssl_handle_message_type( ssl ); - -- } while( MBEDTLS_ERR_SSL_NON_FATAL == ret ); -+ } while( MBEDTLS_ERR_SSL_NON_FATAL == ret || -+ ( MBEDTLS_ERR_SSL_WANT_READ == ret && ssl->in_msglen ) ); - - if( 0 != ret ) - { diff --git a/library/threading.c b/library/threading.c -index 83ec01a45..92ae7eefe 100644 +index 7c90c7c59..30d65b926 100644 --- a/library/threading.c +++ b/library/threading.c -@@ -82,6 +82,16 @@ int (*mbedtls_mutex_unlock)( mbedtls_threading_mutex_t * ) = threading_mutex_unl +@@ -120,6 +120,16 @@ int (*mbedtls_mutex_unlock)( mbedtls_threading_mutex_t * ) = threading_mutex_unl #endif /* MBEDTLS_THREADING_PTHREAD */ #if defined(MBEDTLS_THREADING_ALT) @@ -677,7 +663,7 @@ index 83ec01a45..92ae7eefe 100644 static int threading_mutex_fail( mbedtls_threading_mutex_t *mutex ) { ((void) mutex ); -@@ -97,6 +107,7 @@ void (*mbedtls_mutex_init)( mbedtls_threading_mutex_t * ) = threading_mutex_dumm +@@ -135,6 +145,7 @@ void (*mbedtls_mutex_init)( mbedtls_threading_mutex_t * ) = threading_mutex_dumm void (*mbedtls_mutex_free)( mbedtls_threading_mutex_t * ) = threading_mutex_dummy; int (*mbedtls_mutex_lock)( mbedtls_threading_mutex_t * ) = threading_mutex_fail; int (*mbedtls_mutex_unlock)( mbedtls_threading_mutex_t * ) = threading_mutex_fail; @@ -686,5 +672,5 @@ index 83ec01a45..92ae7eefe 100644 /* * Set functions pointers and initialize global mutexes -- -2.17.1.windows.2 +2.18.0.windows.1 diff --git a/middleware/mbedtls/0002-update-the-copyright-and-add-the-support-of-DW-timer.patch b/middleware/mbedtls/0002-update-the-copyright-and-add-the-support-of-DW-timer.patch index 50290e67e..0de1189f0 100644 --- a/middleware/mbedtls/0002-update-the-copyright-and-add-the-support-of-DW-timer.patch +++ b/middleware/mbedtls/0002-update-the-copyright-and-add-the-support-of-DW-timer.patch @@ -1,4 +1,4 @@ -From 3dbb8cfe1e5a83ccfb717b04b3178ffe2e4b6e12 Mon Sep 17 00:00:00 2001 +From 94684fb7616db867d6a666dd99ef690a6af28a58 Mon Sep 17 00:00:00 2001 From: Wayne Ren Date: Sat, 29 Dec 2018 15:16:37 +0800 Subject: [PATCH 2/2] update the copyright and add the support of DW timer @@ -239,5 +239,5 @@ index 151765d34..a3463ba91 100644 #ifndef _TIMING_ALT_H_ #define _TIMING_ALT_H_ -- -2.17.1.windows.2 +2.18.0.windows.1 diff --git a/middleware/mbedtls/apply_embARC_patch.sh b/middleware/mbedtls/apply_embARC_patch.sh index 46a576922..4d658e33e 100755 --- a/middleware/mbedtls/apply_embARC_patch.sh +++ b/middleware/mbedtls/apply_embARC_patch.sh @@ -2,7 +2,7 @@ ## REPO CONFIGURATION REPO_LINK="https://github.com/ARMmbed/mbedtls.git" -REPO_COMMIT="mbedtls-2.4.1" +REPO_COMMIT="mbedtls-2.16.0" SRC_DIRS="library,include" PREV_DIR=$(pwd) From 3f87e611599462b42eeef825e1f1e7fcd21a2878 Mon Sep 17 00:00:00 2001 From: Wayne Ren Date: Tue, 8 Jan 2019 10:28:12 +0800 Subject: [PATCH 06/28] examples: remove doxygen comments These doxygen comments are not required any more Signed-off-by: Wayne Ren --- board/emsk/drivers/flash_obj/flash_obj.c | 2 +- example/baremetal/arc_feature/cache/main.c | 2 +- .../arc_feature/timer_interrupt/main.c | 2 - example/baremetal/axs103/main.c | 37 ---------- example/baremetal/ble_hm1x/main.c | 62 +--------------- example/baremetal/blinky/main.c | 35 --------- example/baremetal/cxx/main.cpp | 35 --------- example/baremetal/dma_spiflash/main.c | 39 ---------- example/baremetal/graphic_u8glib/main.c | 53 -------------- example/baremetal/openthread/cli/main.c | 73 ------------------- example/baremetal/openthread/ncp/main.c | 73 ------------------- .../secret_normal/background_container.c | 46 +----------- .../secret_normal/background_container.h | 6 +- .../secureshield/secret_normal/container1.c | 6 -- .../secureshield/secret_normal/container1.h | 6 -- .../secureshield/secret_normal/container2.c | 7 -- .../secureshield/secret_normal/container2.h | 6 -- .../secret_normal/container_cfg.c | 6 -- .../secret_secure/background_container.c | 44 ----------- .../secret_secure/background_container.h | 5 -- .../secureshield/secret_secure/container2.c | 6 -- .../secureshield/secret_secure/container2.h | 6 -- .../secret_secure/container_cfg.c | 6 -- .../secret_secure/secure/container1.c | 6 -- .../secret_secure/secure/container1.h | 6 -- .../secret_secure_sid/background_container.c | 49 +------------ .../secret_secure_sid/background_container.h | 6 +- .../secret_secure_sid/container2.c | 6 +- .../secret_secure_sid/container2.h | 6 +- .../secret_secure_sid/container_cfg.c | 6 +- .../test_case/background_container.c | 1 - .../secureshield/test_case/container1.c | 6 -- .../secureshield/test_case/container2.c | 6 -- .../secureshield/test_case/container_cfg.c | 30 ++++++++ .../kernel_secure/background_container.c | 40 ---------- .../kernel_secure/background_container.h | 5 -- example/freertos/kernel_secure/container1.c | 6 -- example/freertos/kernel_secure/container2.c | 5 -- example/freertos/kernel_secure/container2.h | 6 +- .../freertos/kernel_secure/container_cfg.c | 5 -- example/freertos/net/httpserver/main.c | 38 ---------- example/freertos/net/ntshell/main.c | 42 ----------- 42 files changed, 41 insertions(+), 797 deletions(-) diff --git a/board/emsk/drivers/flash_obj/flash_obj.c b/board/emsk/drivers/flash_obj/flash_obj.c index d5ec577aa..4151fc4b2 100644 --- a/board/emsk/drivers/flash_obj/flash_obj.c +++ b/board/emsk/drivers/flash_obj/flash_obj.c @@ -210,7 +210,7 @@ DEV_FLASH_PTR flash_get_dev(int32_t flash_id) { static uint32_t install_flag = 0; - /* intall device objects */ + /* install device objects */ if (install_flag == 0) { install_flag = 1; emsk_flash_obj_all_install(); diff --git a/example/baremetal/arc_feature/cache/main.c b/example/baremetal/arc_feature/cache/main.c index 21eb0abb4..e118e834d 100644 --- a/example/baremetal/arc_feature/cache/main.c +++ b/example/baremetal/arc_feature/cache/main.c @@ -30,7 +30,7 @@ #include "embARC.h" #include "embARC_debug.h" -#ifdef BOARD_EMDK +#ifdef BOARD_EMSDP //EMDK only has 2 way cache, it might have some chances that the cache get switched out before locking, // causing cached data being wrote to memory in advance // If that is the case, please test other lines of cache_data diff --git a/example/baremetal/arc_feature/timer_interrupt/main.c b/example/baremetal/arc_feature/timer_interrupt/main.c index 1d33030c9..d2a00f48b 100644 --- a/example/baremetal/arc_feature/timer_interrupt/main.c +++ b/example/baremetal/arc_feature/timer_interrupt/main.c @@ -86,10 +86,8 @@ int main(void) timer_current(TIMER_1, &val); EMBARC_PRINTF("cnt:%d\r\n", val); timer_stop(TIMER_1); /* Stop it first since it might be enabled before */ -#ifndef BOARD_EMSDP int_handler_install(INTNO_TIMER1, timer1_isr); int_enable(INTNO_TIMER1); -#endif } else { EMBARC_PRINTF("timer 1 is not present\r\n"); } diff --git a/example/baremetal/axs103/main.c b/example/baremetal/axs103/main.c index 78ac43887..7b6cdad29 100644 --- a/example/baremetal/axs103/main.c +++ b/example/baremetal/axs103/main.c @@ -27,41 +27,6 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * --------------------------------------------- */ - -/** - * \defgroup EMBARC_APP_BAREMETAL_ARC_FEATURE_AXS103 embARC AXS 103 board test Example - * \ingroup EMBARC_APPS_TOTAL - * \ingroup EMBARC_APPS_BAREMETAL - * \ingroup EMBARC_APPS_BOARD_AXS - * \brief embARC example for testing AXS 103 board function - * - * \details - * ### Extra Required Tools - * - * ### Extra Required Peripherals - * - * ### Design Concept - * This example is designed to test the AXS 103 hardware board. - * - * ### Usage Manual - * Configure your axs 103 hardware according the hardware user manual, - * then run it, and see the uart console output. - * ![ScreenShot of axs 103 board test under baremetal](pic/images/example/emsk/baremetal_arc_feature_axs103.jpg) - * - * ### Extra Comments - * Tested and supported on v1.1 firmware version of AXS103. - */ - -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_ARC_FEATURE_AXS103 - * \brief main source of example - */ - -/** - * \addtogroup EMBARC_APP_BAREMETAL_ARC_FEATURE_AXS103 - * @{ - */ /* embARC HAL */ #include "embARC.h" #include "embARC_debug.h" @@ -131,5 +96,3 @@ int main(void) while(1); return E_SYS; } - -/** @} */ \ No newline at end of file diff --git a/example/baremetal/ble_hm1x/main.c b/example/baremetal/ble_hm1x/main.c index 9af06b242..fe26aa242 100644 --- a/example/baremetal/ble_hm1x/main.c +++ b/example/baremetal/ble_hm1x/main.c @@ -27,64 +27,6 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * --------------------------------------------- */ - -/** - * \defgroup EMBARC_APP_BAREMETAL_BLE_HM1X embARC BLE_HM1X Example - * \ingroup EMBARC_APPS_TOTAL - * \ingroup EMBARC_APPS_BAREMETAL - * \brief embARC example for BLE HM10 device via UART - * - * \details - * ### Extra Required Tools - * * BLE APP on SmartPhone: - * - Android: BLE Android ComAssistant - * - iOS: [LightBlue](http://itunes.apple.com/us/app/lightblue-bluetooth-low-energy/id557428110?mt=8) - * - * ### Extra Required Peripherals - * * UART Based BLE Device HM-10 - * - * ### Design Concept - * This example is designed to test how to operate UART-based BLE device HM10 via UART - * and demonstrate how to use HM-10 BLE API defined in hm1x.h. - * - * ### Usage Manual - * - How to connect HM-10 to \ref EMBARC_BOARD_CONNECTION "EMSK". - * \code - * HM10-DV33 <----> J1-PIN6 - * HM10-GND <----> J1-PIN5 - * HM10-TXD <----> J1-PIN4 - * HM10-RXD <----> J1-PIN3 - * \endcode - * - * - How to use this example - * - * This example demonstrates how to use the API of HM-10 - * located in *device/peripheral/ble*, the APIs contains information about send AT command and receive response, - * and read or write data to BLE device. \n - * The example performs tests on the HM-10 BLE device using different uart baudrate, - * which take approximately 2 minutes, then the device will enter to receive and send mode. - * Users can use a BLE-UART APP on their smartphone which must support BLE, - * for android please use BLE Android ComAssistant, - * for iOS please use [LightBlue](http://itunes.apple.com/us/app/lightblue-bluetooth-low-energy/id557428110?mt=8). - * - * ![ScreenShot of ble_hm1x-uart message under baremetal](pic/images/example/emsk/emsk_ble_hm1x.jpg) - * - * ### Extra Comments - * - */ - -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_BLE_HM1X - * \brief example of how to use HM-10 BLE device - * This example shows how to use hm1x api declared in hm1x.h in baremetal. - */ - -/** - * \addtogroup EMBARC_APP_BAREMETAL_BLE_HM1X - * @{ - */ - #include "embARC.h" #include "embARC_debug.h" @@ -234,6 +176,4 @@ int main(void) } return E_SYS; /* system error */ -} - -/** @} */ +} \ No newline at end of file diff --git a/example/baremetal/blinky/main.c b/example/baremetal/blinky/main.c index cd998fb9d..bf9e589d3 100644 --- a/example/baremetal/blinky/main.c +++ b/example/baremetal/blinky/main.c @@ -27,39 +27,6 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * --------------------------------------------- */ - -/** - * \defgroup EMBARC_APP_BAREMETAL_BLINKY embARC Blinky Example - * \ingroup EMBARC_APPS_TOTAL - * \ingroup EMBARC_APPS_BAREMETAL - * \brief embARC example for toggle leds on board - * - * \details - * ### Extra Required Tools - * - * ### Extra Required Peripherals - * - * ### Design Concept - * This example is designed to test board without any extra peripheral - * - * ### Usage Manual - * Toggle all leds on board in 1s period - * - * ### Extra Comments - * - */ - -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_BLINKY - * \brief main source file for blinky example - */ - -/** - * \addtogroup EMBARC_APP_BAREMETAL_BLINKY - * @{ - */ -/* embARC HAL */ #include "embARC.h" #include "embARC_debug.h" @@ -80,5 +47,3 @@ int main(void) return E_SYS; } - -/** @} */ \ No newline at end of file diff --git a/example/baremetal/cxx/main.cpp b/example/baremetal/cxx/main.cpp index 506a649e6..d3b1b7a16 100644 --- a/example/baremetal/cxx/main.cpp +++ b/example/baremetal/cxx/main.cpp @@ -28,40 +28,6 @@ * --------------------------------------------- */ -/** - * \defgroup EMBARC_APP_BAREMETAL_CXX embARC C++ Support Test Example - * \ingroup EMBARC_APPS_TOTAL - * \ingroup EMBARC_APPS_BAREMETAL - * \brief Test C++ support in embARC - * - * \details - * ### Extra Required Tools - * - * ### Extra Required Peripherals - * - * ### Design Concept - * This example is designed to test C++ support in embARC. - * - * ### Usage Manual - * Here we take EMSK 2.3 EM7D for example, you can run the program using Metaware toolset. - * - Re-configure the EMSK 2.3 board to EM7D configuration. - * - Command: gmake BD_VER=23 CUR_CORE=arcem7d run - * - Running screenshot as follows - * ![ScreenShot for C++ support test in embARC](pic/images/example/emsk/baremetal_c++.jpg) - * - * ### Extra Comments - */ - -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_CXX - * \brief main source of this example - */ - -/** - * \addtogroup EMBARC_APP_BAREMETAL_CXX - * @{ - */ #include "embARC.h" #include "embARC_debug.h" @@ -163,4 +129,3 @@ int main(void) EMBARC_PRINTF("x and y are the same\r\n"); } } -/** @} */ \ No newline at end of file diff --git a/example/baremetal/dma_spiflash/main.c b/example/baremetal/dma_spiflash/main.c index f4d2c5318..2ec0d8a70 100644 --- a/example/baremetal/dma_spiflash/main.c +++ b/example/baremetal/dma_spiflash/main.c @@ -28,45 +28,6 @@ * --------------------------------------------- */ -/** - * \defgroup EMBARC_APP_BAREMETAL_DMA_SPIFLASH embARC SPIFlash with uDMA Test Example - * \ingroup EMBARC_APPS_TOTAL - * \ingroup EMBARC_APPS_BAREMETAL - * \brief Compare SPIFlash working frequency using poll spi and spi with uDMA - * - * \details - * ### Extra Required Tools - * - * ### Extra Required Peripherals - * - * ### Design Concept - * This example is designed to test SPIFlash driver with uDMA enhanced. - * - * ### Usage Manual - * Here we take EMSK 2.3 EM9D for example, you can run the program using Metaware toolset. - * - Re-configure the EMSK 2.3 board to EM9D configuration. - * - Command: gmake BD_VER=23 CUR_CORE=arcem9d run - * - Running screenshot as follows - * ![ScreenShot for SPIFlash erase/write/read test using uDMA](pic/images/example/emsk/baremetal_dma_spiflash.jpg) - * - * ### Extra Comments - * - Tested in EMSK 2.3 EM9D, for drivers with DMA, spiflash working frequency can achieve 12Mhz. - * - For drivers without DMA, spiflash working frequency can achieve 2Mhz. - * - This example will stuck at the max frequency that SPI can achieve at that situation. - * - This example required that the ARC core configuration should has uDMA option and DW SPI also enabled DMA interface with uDMA. - */ - -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_DMA_SPIFLASH - * \brief main source of example of spiflash with dma - */ - -/** - * \addtogroup EMBARC_APP_BAREMETAL_DMA_SPIFLASH - * @{ - */ -/* embARC HAL */ #include "embARC.h" #include "embARC_debug.h" #include "spi_flash.h" diff --git a/example/baremetal/graphic_u8glib/main.c b/example/baremetal/graphic_u8glib/main.c index f1d616bb9..a6cfad23e 100644 --- a/example/baremetal/graphic_u8glib/main.c +++ b/example/baremetal/graphic_u8glib/main.c @@ -28,58 +28,6 @@ * --------------------------------------------- */ -/** - * \defgroup EMBARC_APP_BAREMETAL_GRAPHIC_U8GLIB embARC Graphic Example on SSD1306 - * \ingroup EMBARC_APPS_TOTAL - * \ingroup EMBARC_APPS_BAREMETAL - * \ingroup EMBARC_APPS_MID_U8GLIB - * \brief U8glib graphic test on OLED SSD1306 - * - * \details - * ### Extra Required Tools - * - * ### Extra Required Peripherals - * * [PMOD OLED based on SSD1306 128x64 monochrome] - * - * ### Design Concept - * This example is a graphic test based on OLED ssd1306 and U8glib. - * - * ### Usage Manual - * - How to connect SSD1306 to \ref EMBARC_BOARD_CONNECTION "EMSK". - * \code - * SSD1306-I2C-SCL <----> J2-PIN3 - * SSD1306-I2C-SDA <----> J2-PIN4 - * SSD1306-GND <----> J2-PIN5 - * SSD1306-DV33 <----> J2-PIN6 - * \endcode - * - * - How to use this example - * - * This example demonstrates how to use U8glib functions of drawing box, line and ASCII characters. - * Dynamic graphics are shown in SSD1306. - * And display width & height information is shown in Tera Term. - * - * ![ScreenShot of SSD1306](pic/images/example/emsk/emsk_graphic_test_u8glib1.jpg) - * ![ScreenShot of u8glib tests in SSD1306](pic/images/example/emsk/emsk_graphic_test_u8glib2.jpg) - * - * - * ### Extra Comments - * - */ - -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_GRAPHIC_U8GLIB - * \brief U8glib graphic test of SSD1306 - * This example is a graphic test based on OLED SSD1306 and U8glib. - */ - -/** - * \addtogroup EMBARC_APP_BAREMETAL_GRAPHIC_U8GLIB - * @{ - */ - -/* embARC HAL */ #include "embARC.h" #include "embARC_debug.h" @@ -190,4 +138,3 @@ int main(void) return E_SYS; } -/** @} */ diff --git a/example/baremetal/openthread/cli/main.c b/example/baremetal/openthread/cli/main.c index 706ba6486..a7bc82b6e 100644 --- a/example/baremetal/openthread/cli/main.c +++ b/example/baremetal/openthread/cli/main.c @@ -28,77 +28,6 @@ * --------------------------------------------- */ -/** - * \defgroup EMBARC_APP_BAREMETAL_OPENTHREAD_CLI embARC OpenThread CLI example on MRF24J40 - * \ingroup EMBARC_APPS_TOTAL - * \ingroup EMBARC_APPS_BAREMETAL - * \ingroup EMBARC_APPS_MID_OPENTHREAD - * \brief OpenThread command line interface example on MRF24J40 - * - * \details - * ### Extra Required Tools - * - * ### Extra Required Peripherals - * * 2 x EMSK - * * 2 x Digilent PMOD RF2 (MRF24J40) - * * 1 x SD card - * - * ### Design Concept - * This example is an OpenThread Command Line Interface (CLI) application on PMOD RF2 (MRF24J40). - * The mesh network is established, and IPv6 is configured with using bi-/multi-boards as Thread nodes. - * The node status can be shown on the terminal via UART. There are dozens of commands supported in the CLI example. - * The OpenThread CLI reference is in OT_CLI.md. - * - * ### Usage Manual - * - See \ref EMBARC_BOARD_CONNECTION "EMSK" to connect PMOD RF2 (MRF24J40). - * - * - How to use this example - * - * * Program the secondary bootloader application into onboard SPI flash of EMSKs. - * * Generate boot.bin of the Openthread CLI example using "make bin". - * * Run Openthread CLI example with boot.bin from SD card. Make sure Bit 4 of the onboard DIP switch is ON to enable - * the secondary bootloader. - * - Insert SD Card back to one EMSK. Press the reset button to reboot it. Wait for loading boot.bin from SD card. - * - Get SD card from one EMSK and insert it to the other EMSK. Press the reset button to reboot it. Wait for loading boot.bin from SD card. - * - Enter “1” and press Enter button in one Tera Term. Enter “2” and press Enter button in the other one. - * The number will not be shown directly in the Tera Term until pressing Enter button from the keyboard. - * - Enter the following commands in the two terminal windows, "panid 0x1234", "ifconfig up", "thread start", to start - * start Thread process. - * - Wait 20 seconds for completing Thread configuration. Enter “state” to see the state of the node, one leader and one router. - * - Enter other commands in the OpenThread CLI reference (OT_CLI.md) to get more information. For example, - * “ipaddr” is used to show the IP address of the Thread node. Enter “ipaddr” in one ternimal to get the Thread node IP address, - * such as **fe80:0:0:0:f065:44eb:ef9f:57c8**. Enter “ping fe80:0:0:0:f065:44eb:ef9f:57c8” in the other ternimal to ping the Thread node. - * The Internet Control Messages Protocol (ICMP) is implemented in the OpenThread for **ping** command. - * - * - * - * ### Extra Comments - * * A few seconds are required to make connections of Thread nodes. - * * Use AC adapter to ensure a steady power supply. - * * Open two Tera Term emulators to connect EMSKs with different COM ports. - * * The self-boot mode preparation is included in the above steps. - * * “make run” is not supported because EMSK boards are both v2.x and it can lead to conflict. - * See \ref sect_example_usage_HowToDebugMultiBoards "how to debug multiple boards in embARC" for more information. - * * Enter number to generate the pseudo-random number for OpenThread. Recommend enter number in order, such as “1”, “2” and “3”. - * Using same number in different nodes may lead error. - * * Make sure the compiler configuration (TOOLCHAIN, BD_VER, CUR_CORE) of the secondary bootloader and bin file. - * For example, the bootloader for EMSK 2.3/ARCEM7D cannot boot the program for EMSK 2.3/ARCEM11D. - * - */ - -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_OPENTHREAD_CLI - * \brief example of how to use OpenThread command-line interface - * This example demonstrates a minimal OpenThread application to - * show the OpenThread configuration and management interfaces via a basic command-line interface. - */ - -/** - * \addtogroup EMBARC_APP_BAREMETAL_OPENTHREAD_CLI - * @{ - */ - #include "embARC.h" #include "embARC_debug.h" @@ -180,5 +109,3 @@ int main(void) return 0; } - -/** @} */ diff --git a/example/baremetal/openthread/ncp/main.c b/example/baremetal/openthread/ncp/main.c index 0d9c354b8..be98a577a 100644 --- a/example/baremetal/openthread/ncp/main.c +++ b/example/baremetal/openthread/ncp/main.c @@ -28,78 +28,6 @@ * --------------------------------------------- */ -/** - * \defgroup EMBARC_APP_BAREMETAL_OPENTHREAD_NCP embARC OpenThread NCP example on MRF24J40 - * \ingroup EMBARC_APPS_TOTAL - * \ingroup EMBARC_APPS_BAREMETAL - * \ingroup EMBARC_APPS_MID_OPENTHREAD - * \brief OpenThread Network Co-Processor (NCP) on MRF24J40 - * - * \details - * ### Extra Required Tools - * - * ### Extra Required Peripherals - * * 2 x EMSK - * * 2 x Digilent PMOD RF2 (MRF24J40) - * * 2 x SD card - * - * ### Design Concept - * This example is an OpenThread Network Co-Processor (NCP) application on PMOD RF2 (MRF24J40). - * This example can serve as a low-power wireless Network Co-Processor (NCP) to join Thread network - * and communicate with Userspace WPAN Network Daemon (wpantund) on Unix-like operating systems. - * This example can be used along with OpenThread wpantund to provide Internet connectivity to the Thread network. - * For more information about NCP and wpantund, see README.md for reference. - * The NCP status can not be shown on the terminal via UART, it might show messy code. - * - * ### Usage Manual - * - See \ref EMBARC_BOARD_CONNECTION "EMSK" to connect PMOD RF2 (MRF24J40). - * - * - How to use this example - * - * * Program the secondary bootloader application into onboard SPI flash of EMSKs. - * * Generate boot.bin of the Openthread NCP example using "make bin". - * * Run an Openthread CLI example first with boot.bin from SD card, see `cli\README.md` for more information. - * - Insert SD Card back to one EMSK. It will run the CLI example. Press the reset button to reboot it. Wait for loading boot.bin from SD card. - * - Enter “1” and press Enter button in the Tera Term. Enter the number here to generate pseudo random number for OpenThread. - * - Enter the following commands in the two terminal windows, "panid 0x1234", "ifconfig up", "thread start", to start - * Thread process. - * - Wait 20 seconds for completing Thread configuration. Enter “state” to see the state of the node, it will be the leader. - * * Run Openthread NCP example with boot.bin from SD card. Make sure Bit 4 of the onboard DIP switch is ON to enable - * the secondary bootloader. - * - Insert the other SD card to the other EMSK. It will run the NCP example. Press the reset button to reboot it. Wait for loading boot.bin from SD card. - * - Enter **2** and press Enter button in the NCP's Tera Term. - * - After entering **2** in the NCP's Tera Term, the NCP will start up automatically. - * It will show you some messy code in the last line, just ignore it. - * - Install and Run OpenThread wpantund, and join the NCP to the Thread network created by CLI. See README.md for more information. - * - Ping to each other between Linux host and CLI Node. - * - * - * - * ### Extra Comments - * * Use AC adapter to ensure a steady power supply. - * * The self-boot mode preparation is included in the above steps. - * * “make run” is not supported because EMSK boards are both v2.x and it can lead to conflict. - * See \ref sect_example_usage_HowToDebugMultiBoards "how to debug multiple boards in embARC" for more information. - * * Enter number to generate the pseudo-random number for OpenThread. Recommend enter number in order, such as “1”, “2” and “3”. - * Using same number in different nodes may lead error. - * * Make sure the compiler configuration (TOOLCHAIN, BD_VER, CUR_CORE) of the secondary bootloader and bin file. - * For example, the bootloader for EMSK 2.3/ARCEM7D cannot boot the program for EMSK 2.3/ARCEM11D. - * - */ - -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_OPENTHREAD_NCP - * \brief example of how to use OpenThread Network Co-Processor (NCP) - * This example demonstrates a minimal OpenThread application to show the OpenThread NCP - * joins Thread network and communicates with wpantund on Unix-like operating systems. - */ - -/** - * \addtogroup EMBARC_APP_BAREMETAL_OPENTHREAD_NCP - * @{ - */ - #include "embARC.h" #include "embARC_debug.h" @@ -180,4 +108,3 @@ int main(void) return 0; } -/** @} */ diff --git a/example/baremetal/secureshield/secret_normal/background_container.c b/example/baremetal/secureshield/secret_normal/background_container.c index 913010ae3..7fca8c5bd 100644 --- a/example/baremetal/secureshield/secret_normal/background_container.c +++ b/example/baremetal/secureshield/secret_normal/background_container.c @@ -27,49 +27,7 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * --------------------------------------------- */ -/** - * \defgroup EMBARC_APP_BAREMETAL_SECURESHIELD_SECRET_NORMAL embARC Secureshield Secret Normal Example - * \ingroup EMBARC_APPS_TOTAL - * \ingroup EMBARC_APPS_BAREMETAL - * \brief embARC Secureshield secret normal example - * - * \details - * ### Extra Required Tools - * - * ### Extra Required Peripherals - * - Designware nSIM Tool or - * - EMSK 2.2 arcem7d configuration / EMSK 2.3 arcem7d configuration - * - * ### Design Concept - * This example is designed to show how data could be protected with SecureShield. The application demonstrates a secure keystore component. It's similar to the 'secret' example, but protects the secrets differently: - * - all containers are normal containers, no secure privileges. - * - to initialize the secret data in container 1, a private const data section is used; others cannot access this data. In an application with secure persistent storage like EEPROM or flash, it would be stored there. - * - a shared memory region is created for container 1 and container 2 to exchange data; others cannot access this region. - * - an application specific linker script is created to show how shared memory is created and how the initialization data is protected. - * - for further information on the application, see the 'secret' application - * - * ### Usage Manual - * When this example start to run, please try the following ntshell commands: - * - Run ntshell command **main -h** to see how to run this example. - * - Run ntshell command **main -p embarc** or **main -t** to get the secret. - * - * ![ScreenShot of secureshield example](pic/images/example/emsk/baremetal_secureshield_secret2.jpg) - * - * ### Extra Comments - * - */ - -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_SECURESHIELD_SECRET_NORMAL - * \brief secureshield secret normal example source file - */ - -/** - * \addtogroup EMBARC_APP_BAREMETAL_SECURESHIELD_SECRET_NORMAL - * @{ - */ -/* embARC HAL */ + #include #include #include @@ -213,5 +171,3 @@ int main(int argc, char **argv) error_exit: return E_OK; } - -/** @} */ diff --git a/example/baremetal/secureshield/secret_normal/background_container.h b/example/baremetal/secureshield/secret_normal/background_container.h index 99b66a618..5e4abb39c 100644 --- a/example/baremetal/secureshield/secret_normal/background_container.h +++ b/example/baremetal/secureshield/secret_normal/background_container.h @@ -27,11 +27,7 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * --------------------------------------------- */ -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_SECURESHIELD_SECRET_NORMAL - * \brief background container head file - */ + #ifndef BACKGROUND_CONTAINER_H #define BACKGROUND_CONTAINER_H diff --git a/example/baremetal/secureshield/secret_normal/container1.c b/example/baremetal/secureshield/secret_normal/container1.c index 3c27c4386..1525729f3 100644 --- a/example/baremetal/secureshield/secret_normal/container1.c +++ b/example/baremetal/secureshield/secret_normal/container1.c @@ -28,12 +28,6 @@ * --------------------------------------------- */ -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_SECURESHIELD_SECRET_NORMAL - * \brief secureshield secret normal example container1 source file - */ - #include #include #include "embARC.h" diff --git a/example/baremetal/secureshield/secret_normal/container1.h b/example/baremetal/secureshield/secret_normal/container1.h index da1dfe6ec..d63009cd4 100644 --- a/example/baremetal/secureshield/secret_normal/container1.h +++ b/example/baremetal/secureshield/secret_normal/container1.h @@ -28,12 +28,6 @@ * --------------------------------------------- */ -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_SECURESHIELD_SECRET_NORMAL - * \brief secureshield secret normal example container1 head file - */ - #ifndef CONTAINER1_H #define CONTAINER1_H diff --git a/example/baremetal/secureshield/secret_normal/container2.c b/example/baremetal/secureshield/secret_normal/container2.c index b0078de44..78b080d48 100644 --- a/example/baremetal/secureshield/secret_normal/container2.c +++ b/example/baremetal/secureshield/secret_normal/container2.c @@ -28,13 +28,6 @@ * --------------------------------------------- */ -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_SECURESHIELD_SECRET_NORMAL - * \brief secureshield secret normal example container2 source file - */ - - #include "embARC.h" #include "embARC_debug.h" #include "embARC_assert.h" diff --git a/example/baremetal/secureshield/secret_normal/container2.h b/example/baremetal/secureshield/secret_normal/container2.h index 0cb6fee15..15d7fe1ec 100644 --- a/example/baremetal/secureshield/secret_normal/container2.h +++ b/example/baremetal/secureshield/secret_normal/container2.h @@ -28,12 +28,6 @@ * --------------------------------------------- */ -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_SECURESHIELD_SECRET_NORMAL - * \brief secureshield secret normal example container2 header file - */ - #ifndef CONTAINER2_H #define CONTAINER2_H diff --git a/example/baremetal/secureshield/secret_normal/container_cfg.c b/example/baremetal/secureshield/secret_normal/container_cfg.c index 9cc1fd403..f949ca6e4 100644 --- a/example/baremetal/secureshield/secret_normal/container_cfg.c +++ b/example/baremetal/secureshield/secret_normal/container_cfg.c @@ -28,12 +28,6 @@ * --------------------------------------------- */ -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_SECURESHIELD_SECRET_NORMAL - * \brief secureshield secret normal example container configuration file - */ - #include "embARC.h" #include "container1.h" #include "container2.h" diff --git a/example/baremetal/secureshield/secret_secure/background_container.c b/example/baremetal/secureshield/secret_secure/background_container.c index e425ebdab..be9cd6e7f 100644 --- a/example/baremetal/secureshield/secret_secure/background_container.c +++ b/example/baremetal/secureshield/secret_secure/background_container.c @@ -27,49 +27,7 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * --------------------------------------------- */ -/** - * \defgroup EMBARC_APP_BAREMETAL_SECURESHIELD_SECRET_SECURE embARC SecureShield Secret Secure Example - * \ingroup EMBARC_APPS_TOTAL - * \ingroup EMBARC_APPS_BAREMETAL - * \brief embARC SecureShield secret secure example - * - * \details - * ### Extra Required Tools - * - * ### Extra Required Peripherals - * - Designware nSIM Tool or - * - EMSK 2.2 arcem7d configuration - * - * ### Design Concept - * This example is designed to show how data could be protected with SecureShield. The application demonstrates a secure keystore component. - * - The secret and password are protected in the context of container 1 which is a container with secure privileges. - * - You need to input the right password to get the secret from the non-trusted background container; container 2 is trusted and can access the secret without password. - * - The init value of secret and password are stored in the data section of secure container 1. Non-secure containers can not access them directly. - * - Secure container 2 can use the container 1 secret internally for implementing other services. The background application can request such a service, without knowing or obtaining the secret itself. - * - For demonstration purpose, the background container can obtain the secret as well (using the password). Since the background container stores the result in global, public memory, this is normally not secure and not recommended. Instead see Container 2 for how to securely use the secret. - * - * ### Usage Manual - * When this example start to run, please try the following ntshell commands: - * - Run ntshell command **main -h** to see how to run this example. - * - Run ntshell command **main -p embarc** or **main -t** to get the secret. - * ![ScreenShot of secureshield example](pic/images/example/emsk/baremetal_secureshield_secret.jpg) - * - * ### Extra Comments - * - */ - -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_SECURESHIELD_SECRET_SECURE - * \brief secureshield secret secure example background container source file - */ - -/** - * \addtogroup EMBARC_APP_BAREMETAL_SECURESHIELD_SECRET_SECURE - * @{ - */ -/* embARC HAL */ #include #include #include @@ -216,5 +174,3 @@ int main(int argc, char **argv) error_exit: return E_OK; } - -/** @} */ \ No newline at end of file diff --git a/example/baremetal/secureshield/secret_secure/background_container.h b/example/baremetal/secureshield/secret_secure/background_container.h index b6631b315..5e4abb39c 100644 --- a/example/baremetal/secureshield/secret_secure/background_container.h +++ b/example/baremetal/secureshield/secret_secure/background_container.h @@ -27,11 +27,6 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * --------------------------------------------- */ -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_SECURESHIELD_SECRET_SECURE - * \brief background container head file - */ #ifndef BACKGROUND_CONTAINER_H #define BACKGROUND_CONTAINER_H diff --git a/example/baremetal/secureshield/secret_secure/container2.c b/example/baremetal/secureshield/secret_secure/container2.c index 5d6aea5f4..433278442 100644 --- a/example/baremetal/secureshield/secret_secure/container2.c +++ b/example/baremetal/secureshield/secret_secure/container2.c @@ -28,12 +28,6 @@ * --------------------------------------------- */ -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_SECURESHIELD_SECRET_SECURE - * \brief secureshield secret secure example container2 source file - */ - #include #include #include diff --git a/example/baremetal/secureshield/secret_secure/container2.h b/example/baremetal/secureshield/secret_secure/container2.h index 1a8eb26c5..441d77857 100644 --- a/example/baremetal/secureshield/secret_secure/container2.h +++ b/example/baremetal/secureshield/secret_secure/container2.h @@ -28,12 +28,6 @@ * --------------------------------------------- */ -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_SECURESHIELD_SECRET_SECURE - * \brief secureshield secret secure example container2 header file - */ - #ifndef CONTAINER2_H #define CONTAINER2_H diff --git a/example/baremetal/secureshield/secret_secure/container_cfg.c b/example/baremetal/secureshield/secret_secure/container_cfg.c index 64b2ea744..c234aca3f 100644 --- a/example/baremetal/secureshield/secret_secure/container_cfg.c +++ b/example/baremetal/secureshield/secret_secure/container_cfg.c @@ -28,12 +28,6 @@ * --------------------------------------------- */ -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_SECURESHIELD_SECRET_SECURE - * \brief secureshield secret secure example container configuration file - */ - #include "embARC.h" #include "container1.h" #include "container2.h" diff --git a/example/baremetal/secureshield/secret_secure/secure/container1.c b/example/baremetal/secureshield/secret_secure/secure/container1.c index 0df187844..0536b2300 100644 --- a/example/baremetal/secureshield/secret_secure/secure/container1.c +++ b/example/baremetal/secureshield/secret_secure/secure/container1.c @@ -28,12 +28,6 @@ * --------------------------------------------- */ -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_SECURESHIELD_SECRET_SECURE - * \brief secureshield secret secure example container1 source file - */ - #undef LIB_SECURESHIELD_OVERRIDES #include #include diff --git a/example/baremetal/secureshield/secret_secure/secure/container1.h b/example/baremetal/secureshield/secret_secure/secure/container1.h index 3dd41d782..fcc66a5bc 100644 --- a/example/baremetal/secureshield/secret_secure/secure/container1.h +++ b/example/baremetal/secureshield/secret_secure/secure/container1.h @@ -28,12 +28,6 @@ * --------------------------------------------- */ -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_SECURESHIELD_SECRET_SECURE - * \brief secureshield secret secure example container1 head file - */ - #ifndef CONTAINER1_H #define CONTAINER1_H diff --git a/example/baremetal/secureshield/secret_secure_sid/background_container.c b/example/baremetal/secureshield/secret_secure_sid/background_container.c index fc3374dfa..be9cd6e7f 100644 --- a/example/baremetal/secureshield/secret_secure_sid/background_container.c +++ b/example/baremetal/secureshield/secret_secure_sid/background_container.c @@ -27,52 +27,7 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * --------------------------------------------- */ -/** - * \defgroup EMBARC_APP_BAREMETAL_SECURESHIELD_SECRET_SECURE_SID embARC Secureshield Secret with SID Example - * \ingroup EMBARC_APPS_TOTAL - * \ingroup EMBARC_APPS_BAREMETAL - * \brief embARC Secureshield secret with SID example - * - * \details - * ### Extra Required Tools - * - * ### Extra Required Peripherals - * - Designware nSIM Tool or EMSK 2.3 arcem7d configuration - * - * ### Design Concept - * This example is designed to show how data could be protected with SecureShield. The application demonstrates a secure keystore component. - * - The secret and password are protected in the context of container 1 which is a container with secure privileges. - * - You need to input the right password to get the secret from the non-trusted background container; container 2 is trusted and can access the secret without password. - * - The init value of secret and password are stored in the data section of secure container 1. Non-secure containers can not access them directly. - * - Secure container 2 can use the container 1 secret internally for implementing other services. The background application can request such a service, without knowing or obtaining the secret itself. - * - For demonstration purpose, the background container can obtain the secret as well (using the password). Since the background container stores the result in global, public memory, this is normally not secure and not recommended. Instead see Container 2 for how to securely use the secret. - * - The difference between this example and secret secure example is MPU reprogramming is avoidded through SID enabled. All containers MPU configuration will be loaded into MPU hardware. - * - * ### Usage Manual - * Here we take EMSK 2.3 EM7D for example, you can run the program using Metaware toolset. - * - Re-configure the EMSK 2.3 board to EM7D configuration. - * - Command: gmake BOARD=emsk BD_VER=23 CUR_CORE=arcem7d run - * - * When this example start to run, please try the following ntshell commands: - * - Run ntshell command **main -h** to see how to run this example. - * - Run ntshell command **main -p embarc** or **main -t** to get the secret. - * ![ScreenShot of secureshield v2 sid example](pic/images/example/emsk/baremetal_secureshield_secret_v2_sid.jpg) - * - * ### Extra Comments - * - */ - -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_SECURESHIELD_SECRET_SECURE_SID - * \brief secureshield background container and main application - */ - -/** - * \addtogroup EMBARC_APP_BAREMETAL_SECURESHIELD_SECRET_SECURE_SID - * @{ - */ -/* embARC HAL */ + #include #include #include @@ -219,5 +174,3 @@ int main(int argc, char **argv) error_exit: return E_OK; } - -/** @} */ \ No newline at end of file diff --git a/example/baremetal/secureshield/secret_secure_sid/background_container.h b/example/baremetal/secureshield/secret_secure_sid/background_container.h index f3341fe85..5e4abb39c 100644 --- a/example/baremetal/secureshield/secret_secure_sid/background_container.h +++ b/example/baremetal/secureshield/secret_secure_sid/background_container.h @@ -27,11 +27,7 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * --------------------------------------------- */ -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_SECURESHIELD_SECRET_SECURE_SID - * \brief secureshield background container header file - */ + #ifndef BACKGROUND_CONTAINER_H #define BACKGROUND_CONTAINER_H diff --git a/example/baremetal/secureshield/secret_secure_sid/container2.c b/example/baremetal/secureshield/secret_secure_sid/container2.c index 9d56d8acf..821eba391 100644 --- a/example/baremetal/secureshield/secret_secure_sid/container2.c +++ b/example/baremetal/secureshield/secret_secure_sid/container2.c @@ -27,11 +27,7 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * --------------------------------------------- */ -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_SECURESHIELD_SECRET_SECURE_SID - * \brief secureshield container 2 implementation - */ + #include #include #include diff --git a/example/baremetal/secureshield/secret_secure_sid/container2.h b/example/baremetal/secureshield/secret_secure_sid/container2.h index 3082d72c2..bd02e6247 100644 --- a/example/baremetal/secureshield/secret_secure_sid/container2.h +++ b/example/baremetal/secureshield/secret_secure_sid/container2.h @@ -27,11 +27,7 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * --------------------------------------------- */ -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_SECURESHIELD_SECRET_SECURE_SID - * \brief secureshield container 2 implementation - */ + #ifndef CONTAINER2_H #define CONTAINER2_H diff --git a/example/baremetal/secureshield/secret_secure_sid/container_cfg.c b/example/baremetal/secureshield/secret_secure_sid/container_cfg.c index 097091859..108d00478 100644 --- a/example/baremetal/secureshield/secret_secure_sid/container_cfg.c +++ b/example/baremetal/secureshield/secret_secure_sid/container_cfg.c @@ -27,11 +27,7 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * --------------------------------------------- */ -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_SECURESHIELD_SECRET_SECURE_SID - * \brief secureshield container configuration file - */ + #include "embARC.h" #include "container1.h" #include "container2.h" diff --git a/example/baremetal/secureshield/test_case/background_container.c b/example/baremetal/secureshield/test_case/background_container.c index a6cf6dc2a..2f5b50177 100644 --- a/example/baremetal/secureshield/test_case/background_container.c +++ b/example/baremetal/secureshield/test_case/background_container.c @@ -31,7 +31,6 @@ #include "embARC_debug.h" #include "embARC_assert.h" - #include "container1.h" #include "container2.h" #include "container3.h" diff --git a/example/baremetal/secureshield/test_case/container1.c b/example/baremetal/secureshield/test_case/container1.c index ae6075805..00529dd4a 100644 --- a/example/baremetal/secureshield/test_case/container1.c +++ b/example/baremetal/secureshield/test_case/container1.c @@ -28,12 +28,6 @@ * --------------------------------------------- */ -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_SECURESHIELD_TEST_CASE - * \brief secureshield test case example container1 source file - */ - #include "embARC.h" #include "embARC_debug.h" #include "embARC_assert.h" diff --git a/example/baremetal/secureshield/test_case/container2.c b/example/baremetal/secureshield/test_case/container2.c index deb0c6c30..79acf3b11 100644 --- a/example/baremetal/secureshield/test_case/container2.c +++ b/example/baremetal/secureshield/test_case/container2.c @@ -28,12 +28,6 @@ * --------------------------------------------- */ -/** - * \file - * \ingroup EMBARC_APP_BAREMETAL_SECURESHIELD_TEST_CASE - * \brief secureshield test case example container2 source file - */ - #include "embARC.h" #include "embARC_debug.h" #include "embARC_assert.h" diff --git a/example/baremetal/secureshield/test_case/container_cfg.c b/example/baremetal/secureshield/test_case/container_cfg.c index c6cd4ddb1..8f3addc42 100644 --- a/example/baremetal/secureshield/test_case/container_cfg.c +++ b/example/baremetal/secureshield/test_case/container_cfg.c @@ -1,3 +1,33 @@ +/* ------------------------------------------ + * Copyright (c) 2017, Synopsys, Inc. All rights reserved. + + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + + * 1) Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + + * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +--------------------------------------------- */ + #include "embARC.h" #include "container1.h" #include "container2.h" diff --git a/example/freertos/kernel_secure/background_container.c b/example/freertos/kernel_secure/background_container.c index 4f11e45ab..b7b097d02 100644 --- a/example/freertos/kernel_secure/background_container.c +++ b/example/freertos/kernel_secure/background_container.c @@ -27,45 +27,7 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * --------------------------------------------- */ -/** - * \defgroup EMBARC_APP_FREERTOS_KERNEL_SECURE embARC FreeRTOS kernel example with secureshield - * \ingroup EMBARC_APPS_TOTAL - * \ingroup EMBARC_APPS_BAREMETAL - * \brief Test FreeRTOS working with secureshield runtime - * - * \details - * ### Extra Required Tools - * - * ### Extra Required Peripherals - * - * ### Design Concept - * This example is designed to show how FreeRTOS is integrated with SecureShield. - * Here, trap_s is used to trigger a task context switch request. So application - * should not use trap exception. - * - * As container switch is not with task switch. So during a container call, task scheduler - * should be suspended to avoid a task context. - * - * ### Usage Manual - * Here we take EMSK 2.3 EM7D for example, you can run the program using Metaware toolset. - * - Re-configure the EMSK 2.3 board to EM7D configuration. - * - Command: gmake BOARD=emsk BD_VER=23 CUR_CORE=arcem7d run - * - Running screenshot as follows - * ![ScreenShot for FreeRTOS kernel with secureshield in embARC](pic/images/example/emsk/freertos_kernel_secure.jpg) - * - * ### Extra Comments - */ - -/** - * \file - * \ingroup EMBARC_APP_FREERTOS_KERNEL_SECURE - * \brief main source of this example - */ -/** - * \addtogroup EMBARC_APP_FREERTOS_KERNEL_SECURE - * @{ - */ #include "embARC.h" #include "embARC_debug.h" @@ -276,5 +238,3 @@ static void interrupt_low_pri(void *p_exinf) t_nest_int = perf_end(); perf_start(); } - -/** @} */ \ No newline at end of file diff --git a/example/freertos/kernel_secure/background_container.h b/example/freertos/kernel_secure/background_container.h index b5735bd86..cf36fb1a4 100644 --- a/example/freertos/kernel_secure/background_container.h +++ b/example/freertos/kernel_secure/background_container.h @@ -27,11 +27,6 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * --------------------------------------------- */ -/** - * \file - * \ingroup EMBARC_APP_FREERTOS_KERNEL_SECURE - * \brief background container head file - */ #ifndef BACKGROUND_CONTAINER_H #define BACKGROUND_CONTAINER_H diff --git a/example/freertos/kernel_secure/container1.c b/example/freertos/kernel_secure/container1.c index 084bf4f86..e63314ee5 100644 --- a/example/freertos/kernel_secure/container1.c +++ b/example/freertos/kernel_secure/container1.c @@ -28,12 +28,6 @@ * --------------------------------------------- */ -/** - * \file - * \ingroup EMBARC_APP_FREERTOS_KERNEL_SECURE - * \brief freertos kernel secure example container1 source file - */ - #include #include #include "embARC.h" diff --git a/example/freertos/kernel_secure/container2.c b/example/freertos/kernel_secure/container2.c index 41ff8ad0a..78b080d48 100644 --- a/example/freertos/kernel_secure/container2.c +++ b/example/freertos/kernel_secure/container2.c @@ -27,11 +27,6 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * --------------------------------------------- */ -/** - * \file - * \ingroup EMBARC_APP_FREERTOS_KERNEL_SECURE - * \brief freertos kernel secure example container2 source file - */ #include "embARC.h" #include "embARC_debug.h" diff --git a/example/freertos/kernel_secure/container2.h b/example/freertos/kernel_secure/container2.h index 8e24ef775..15d7fe1ec 100644 --- a/example/freertos/kernel_secure/container2.h +++ b/example/freertos/kernel_secure/container2.h @@ -27,11 +27,7 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * --------------------------------------------- */ -/** - * \file - * \ingroup EMBARC_APP_FREERTOS_KERNEL_SECURE - * \brief freertos kernel secure example container2 head file - */ + #ifndef CONTAINER2_H #define CONTAINER2_H diff --git a/example/freertos/kernel_secure/container_cfg.c b/example/freertos/kernel_secure/container_cfg.c index 5d550495b..0774c520f 100644 --- a/example/freertos/kernel_secure/container_cfg.c +++ b/example/freertos/kernel_secure/container_cfg.c @@ -27,11 +27,6 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * --------------------------------------------- */ -/** - * \file - * \ingroup EMBARC_APP_FREERTOS_KERNEL_SECURE - * \brief freertos kernel secure example container configuration file - */ #include "embARC.h" #include "container1.h" diff --git a/example/freertos/net/httpserver/main.c b/example/freertos/net/httpserver/main.c index 6442da85c..0e062a3c4 100644 --- a/example/freertos/net/httpserver/main.c +++ b/example/freertos/net/httpserver/main.c @@ -28,42 +28,6 @@ * --------------------------------------------- */ -/** - * \defgroup EMBARC_APP_FREERTOS_NET_HTTPSERVER embARC LwIP HTTPServer Example - * \ingroup EMBARC_APPS_TOTAL - * \ingroup EMBARC_APPS_OS_FREERTOS - * \ingroup EMBARC_APPS_MID_LWIP - * \brief embARC Example for LwIP HTTPServer on FreeRTOS - * - * \details - * ### Extra Required Tools - * - * ### Extra Required Peripherals - * * Digilent PMOD WIFI(MRF24WG0MA) - * - * ### Design Concept - * This example is designed to show how to use LwIP netconn API to serve as a httpserver. - * - * ### Usage Manual - * The Pmod modules should be connected to \ref EMBARC_BOARD_CONNECTION "EMSK". - * This is an example using TCP/IP connection to work as a small web httpserver. - * - * ![ScreenShot of httpserver under freertos](pic/images/example/emsk/emsk_lwip_freertos_httpserver.jpg) - * - * ### Extra Comments - * - */ - -/** - * \file - * \ingroup EMBARC_APP_FREERTOS_NET_HTTPSERVER - * \brief http server using TCP connection example - */ - -/** - * \addtogroup EMBARC_APP_FREERTOS_NET_HTTPSERVER - * @{ - */ #include "embARC.h" #include "embARC_debug.h" @@ -77,5 +41,3 @@ int main(void) return 0; } - -/** @} */ \ No newline at end of file diff --git a/example/freertos/net/ntshell/main.c b/example/freertos/net/ntshell/main.c index e3b13d3aa..cfe366fca 100644 --- a/example/freertos/net/ntshell/main.c +++ b/example/freertos/net/ntshell/main.c @@ -27,47 +27,6 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * --------------------------------------------- */ -/** - * \defgroup EMBARC_APP_FREERTOS_NET_NTSHELL embARC Net Example on NT-Shell - * \ingroup EMBARC_APPS_TOTAL - * \ingroup EMBARC_APPS_OS_FREERTOS - * \ingroup EMBARC_APPS_MID_LWIP - * \ingroup EMBARC_APPS_MID_NTSHELL - * \ingroup EMBARC_APPS_MID_FATFS - * \brief embARC Example for NT-Shell on LwIP and FreeRTOS - * - * \details - * ### Extra Required Tools - * - * ### Extra Required Peripherals - * * Digilent PMOD WIFI(MRF24WG0MA) - * * Digilent PMOD TMP2 - * - * ### Design Concept - * The Pmod modules should be connected to \ref EMBARC_BOARD_CONNECTION "EMSK". - * This example is designed to show how to use NT-Shell over network in FreeRTOS. - * - * ### Usage Manual - * This is an example running NT-Shell command interface ver network, and use telnet to connect to it - * - when program is running and connected to the wifi hotspot, then you can connect your laptop to the same wifi hotspot that emsk connected to - * - use *telnet* command to connect to the ip address of emsk, and see the output then you can run some ntshell commands, but this is not quite stable to be used - * - * ![ScreenShot of NT-Shell under FreeRTOS](/doc/documents/pic/images/example/emsk/emsk_lwip_freertos_ntshell.jpg) - * - * ### Extra Comments - * - */ - -/** - * \file - * \ingroup EMBARC_APP_FREERTOS_NET_NTSHELL - * \brief main source of LwIP NT-Shell example - */ - -/** - * \addtogroup EMBARC_APP_FREERTOS_NET_NTSHELL - * @{ - */ #include "embARC.h" #include "embARC_debug.h" @@ -94,4 +53,3 @@ int main(void) return 0; } -/** @} */ \ No newline at end of file From fed32288c12d9365ecacb0cbe4b176d74b1cc4b5 Mon Sep 17 00:00:00 2001 From: Wayne Ren Date: Tue, 8 Jan 2019 15:01:33 +0800 Subject: [PATCH 07/28] os: freertos: update to 10.1.1 update freertos to V 10.1.1 Signed-off-by: Wayne Ren --- os/freertos/croutine.c | 94 +- os/freertos/event_groups.c | 203 +-- os/freertos/include/FreeRTOS.h | 273 ++-- os/freertos/include/StackMacros.h | 96 +- os/freertos/include/croutine.h | 92 +- os/freertos/include/deprecated_definitions.h | 92 +- os/freertos/include/event_groups.h | 98 +- os/freertos/include/list.h | 103 +- os/freertos/include/message_buffer.h | 798 +++++++++++ os/freertos/include/mpu_prototypes.h | 131 +- os/freertos/include/mpu_wrappers.h | 119 +- os/freertos/include/portable.h | 92 +- os/freertos/include/projdefs.h | 101 +- os/freertos/include/queue.h | 221 +-- os/freertos/include/semphr.h | 127 +- os/freertos/include/stack_macros.h | 129 ++ os/freertos/include/stream_buffer.h | 855 ++++++++++++ os/freertos/include/task.h | 250 ++-- os/freertos/include/timers.h | 112 +- os/freertos/list.c | 122 +- os/freertos/portable/MemMang/ReadMe.url | 5 + os/freertos/portable/MemMang/heap_1.c | 94 +- os/freertos/portable/MemMang/heap_2.c | 92 +- os/freertos/portable/MemMang/heap_3.c | 92 +- os/freertos/portable/MemMang/heap_4.c | 92 +- os/freertos/portable/MemMang/heap_5.c | 92 +- os/freertos/queue.c | 855 ++++++++---- os/freertos/stream_buffer.c | 1263 ++++++++++++++++++ os/freertos/tasks.c | 937 ++++++++----- os/freertos/timers.c | 203 ++- os/hal/inc/os_hal_inc.h | 3 +- 31 files changed, 5470 insertions(+), 2366 deletions(-) create mode 100644 os/freertos/include/message_buffer.h create mode 100644 os/freertos/include/stack_macros.h create mode 100644 os/freertos/include/stream_buffer.h create mode 100644 os/freertos/portable/MemMang/ReadMe.url create mode 100644 os/freertos/stream_buffer.c diff --git a/os/freertos/croutine.c b/os/freertos/croutine.c index 993e09b29..be1717418 100644 --- a/os/freertos/croutine.c +++ b/os/freertos/croutine.c @@ -1,71 +1,29 @@ /* - FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ + * FreeRTOS Kernel V10.1.1 + * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ #include "FreeRTOS.h" #include "task.h" @@ -302,7 +260,7 @@ CRCB_t *pxCRCB; ( void ) uxListRemove( &( pxCRCB->xGenericListItem ) ); /* Is the co-routine waiting on an event also? */ - if( pxCRCB->xEventListItem.pvContainer ) + if( pxCRCB->xEventListItem.pxContainer ) { ( void ) uxListRemove( &( pxCRCB->xEventListItem ) ); } diff --git a/os/freertos/event_groups.c b/os/freertos/event_groups.c index b8df5fd95..f28016c7e 100644 --- a/os/freertos/event_groups.c +++ b/os/freertos/event_groups.c @@ -1,71 +1,29 @@ /* - FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ + * FreeRTOS Kernel V10.1.1 + * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ /* Standard includes. */ #include @@ -81,11 +39,11 @@ task.h is included from an application file. */ #include "timers.h" #include "event_groups.h" -/* Lint e961 and e750 are suppressed as a MISRA exception justified because the -MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the -header files above, but not in this file, in order to generate the correct -privileged Vs unprivileged linkage and placement. */ -#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */ +/* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified +because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined +for the header files above, but not in this file, in order to generate the +correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */ /* The following bit fields convey control information in a task's event list item value. It is important they don't clash with the @@ -102,7 +60,7 @@ taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */ #define eventEVENT_BITS_CONTROL_BYTES 0xff000000UL #endif -typedef struct xEventGroupDefinition +typedef struct EventGroupDef_t { EventBits_t uxEventBits; List_t xTasksWaitingForBits; /*< List of tasks waiting for a bit to be set. */ @@ -139,8 +97,18 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, co /* A StaticEventGroup_t object must be provided. */ configASSERT( pxEventGroupBuffer ); + #if( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + variable of type StaticEventGroup_t equals the size of the real + event group structure. */ + volatile size_t xSize = sizeof( StaticEventGroup_t ); + configASSERT( xSize == sizeof( EventGroup_t ) ); + } /*lint !e529 xSize is referenced if configASSERT() is defined. */ + #endif /* configASSERT_DEFINED */ + /* The user has provided a statically allocated event group - use it. */ - pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 EventGroup_t and StaticEventGroup_t are guaranteed to have the same size and alignment requirement - checked by configASSERT(). */ + pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 !e9087 EventGroup_t and StaticEventGroup_t are deliberately aliased for data hiding purposes and guaranteed to have the same size and alignment requirement - checked by configASSERT(). */ if( pxEventBits != NULL ) { @@ -160,10 +128,13 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, co } else { + /* xEventGroupCreateStatic should only ever be called with + pxEventGroupBuffer pointing to a pre-allocated (compile time + allocated) StaticEventGroup_t variable. */ traceEVENT_GROUP_CREATE_FAILED(); } - return ( EventGroupHandle_t ) pxEventBits; + return pxEventBits; } #endif /* configSUPPORT_STATIC_ALLOCATION */ @@ -175,8 +146,20 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, co { EventGroup_t *pxEventBits; - /* Allocate the event group. */ - pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); + /* Allocate the event group. Justification for MISRA deviation as + follows: pvPortMalloc() always ensures returned memory blocks are + aligned per the requirements of the MCU stack. In this case + pvPortMalloc() must return a pointer that is guaranteed to meet the + alignment requirements of the EventGroup_t structure - which (if you + follow it through) is the alignment requirements of the TickType_t type + (EventBits_t being of TickType_t itself). Therefore, whenever the + stack alignment requirements are greater than or equal to the + TickType_t alignment requirements the cast is safe. In other cases, + where the natural word size of the architecture is less than + sizeof( TickType_t ), the TickType_t variables will be accessed in two + or more reads operations, and the alignment requirements is only that + of each individual read. */ + pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); /*lint !e9087 !e9079 see comment above. */ if( pxEventBits != NULL ) { @@ -196,10 +179,10 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, co } else { - traceEVENT_GROUP_CREATE_FAILED(); + traceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */ } - return ( EventGroupHandle_t ) pxEventBits; + return pxEventBits; } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ @@ -208,7 +191,7 @@ static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, co EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) { EventBits_t uxOriginalBitValue, uxReturn; -EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +EventGroup_t *pxEventBits = xEventGroup; BaseType_t xAlreadyYielded; BaseType_t xTimeoutOccurred = pdFALSE; @@ -259,6 +242,7 @@ BaseType_t xTimeoutOccurred = pdFALSE; /* The rendezvous bits were not set, but no block time was specified - just return the current event bit value. */ uxReturn = pxEventBits->uxEventBits; + xTimeoutOccurred = pdTRUE; } } } @@ -317,13 +301,16 @@ BaseType_t xTimeoutOccurred = pdFALSE; traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ); + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xTimeoutOccurred; + return uxReturn; } /*-----------------------------------------------------------*/ EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) { -EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +EventGroup_t *pxEventBits = xEventGroup; EventBits_t uxReturn, uxControlBits = 0; BaseType_t xWaitConditionMet, xAlreadyYielded; BaseType_t xTimeoutOccurred = pdFALSE; @@ -368,6 +355,7 @@ BaseType_t xTimeoutOccurred = pdFALSE; /* The wait condition has not been met, but no block time was specified, so just return the current value. */ uxReturn = uxCurrentEventBits; + xTimeoutOccurred = pdTRUE; } else { @@ -449,11 +437,9 @@ BaseType_t xTimeoutOccurred = pdFALSE; { mtCOVERAGE_TEST_MARKER(); } + xTimeoutOccurred = pdTRUE; } taskEXIT_CRITICAL(); - - /* Prevent compiler warnings when trace macros are not used. */ - xTimeoutOccurred = pdFALSE; } else { @@ -465,13 +451,16 @@ BaseType_t xTimeoutOccurred = pdFALSE; } traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ); + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xTimeoutOccurred; + return uxReturn; } /*-----------------------------------------------------------*/ EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) { -EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +EventGroup_t *pxEventBits = xEventGroup; EventBits_t uxReturn; /* Check the user is not attempting to clear the bits used by the kernel @@ -503,7 +492,7 @@ EventBits_t uxReturn; BaseType_t xReturn; traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ); - xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ return xReturn; } @@ -514,7 +503,7 @@ EventBits_t uxReturn; EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) { UBaseType_t uxSavedInterruptStatus; -EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +EventGroup_t const * const pxEventBits = xEventGroup; EventBits_t uxReturn; uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); @@ -524,16 +513,16 @@ EventBits_t uxReturn; portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return uxReturn; -} +} /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */ /*-----------------------------------------------------------*/ EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) { ListItem_t *pxListItem, *pxNext; ListItem_t const *pxListEnd; -List_t *pxList; +List_t const * pxList; EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits; -EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +EventGroup_t *pxEventBits = xEventGroup; BaseType_t xMatchFound = pdFALSE; /* Check the user is not attempting to set the bits used by the kernel @@ -542,7 +531,7 @@ BaseType_t xMatchFound = pdFALSE; configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); pxList = &( pxEventBits->xTasksWaitingForBits ); - pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ vTaskSuspendAll(); { traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ); @@ -602,7 +591,7 @@ BaseType_t xMatchFound = pdFALSE; eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows that is was unblocked due to its required bits matching, rather than because it timed out. */ - ( void ) xTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET ); + vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET ); } /* Move onto the next list item. Note pxListItem->pxNext is not @@ -623,7 +612,7 @@ BaseType_t xMatchFound = pdFALSE; void vEventGroupDelete( EventGroupHandle_t xEventGroup ) { -EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; +EventGroup_t *pxEventBits = xEventGroup; const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits ); vTaskSuspendAll(); @@ -633,9 +622,9 @@ const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits ); while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 ) { /* Unblock the task, returning 0 as the event list is being deleted - and cannot therefore have any bits set. */ - configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) ); - ( void ) xTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET ); + and cannot therefore have any bits set. */ + configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) ); + vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET ); } #if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) @@ -667,7 +656,7 @@ const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits ); an interrupt. */ void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) { - ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); + ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ } /*-----------------------------------------------------------*/ @@ -675,7 +664,7 @@ void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet an interrupt. */ void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) { - ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); + ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ } /*-----------------------------------------------------------*/ @@ -721,7 +710,7 @@ BaseType_t xWaitConditionMet = pdFALSE; BaseType_t xReturn; traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ); - xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ return xReturn; } @@ -734,7 +723,7 @@ BaseType_t xWaitConditionMet = pdFALSE; UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) { UBaseType_t xReturn; - EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup; + EventGroup_t const *pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ if( xEventGroup == NULL ) { @@ -748,5 +737,17 @@ BaseType_t xWaitConditionMet = pdFALSE; return xReturn; } -#endif +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vEventGroupSetNumber( void * xEventGroup, UBaseType_t uxEventGroupNumber ) + { + ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + diff --git a/os/freertos/include/FreeRTOS.h b/os/freertos/include/FreeRTOS.h index f81172dbe..c4b5c3b04 100644 --- a/os/freertos/include/FreeRTOS.h +++ b/os/freertos/include/FreeRTOS.h @@ -1,71 +1,29 @@ /* - FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ + * FreeRTOS Kernel V10.1.1 + * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ #ifndef INC_FREERTOS_H #define INC_FREERTOS_H @@ -126,6 +84,10 @@ extern "C" { #error Missing definition: configMAX_PRIORITIES must be defined in FreeRTOSConfig.h. See the Configuration section of the FreeRTOS API documentation for details. #endif +#if configMAX_PRIORITIES < 1 + #error configMAX_PRIORITIES must be defined to be greater than or equal to 1. +#endif + #ifndef configUSE_PREEMPTION #error Missing definition: configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. #endif @@ -142,10 +104,6 @@ extern "C" { #error Missing definition: configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. #endif -#ifndef configMAX_PRIORITIES - #error configMAX_PRIORITIES must be defined to be greater than or equal to 1. -#endif - #ifndef configUSE_CO_ROUTINES #define configUSE_CO_ROUTINES 0 #endif @@ -396,6 +354,14 @@ extern "C" { #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ) #endif +#ifndef traceBLOCKING_ON_QUEUE_PEEK + /* Task is about to block because it cannot read from a + queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + upon which the read was attempted. pxCurrentTCB points to the TCB of the + task that attempted the read. */ + #define traceBLOCKING_ON_QUEUE_PEEK( pxQueue ) +#endif + #ifndef traceBLOCKING_ON_QUEUE_SEND /* Task is about to block because it cannot write to a queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore @@ -408,6 +374,14 @@ extern "C" { #define configCHECK_FOR_STACK_OVERFLOW 0 #endif +#ifndef configRECORD_STACK_HIGH_ADDRESS + #define configRECORD_STACK_HIGH_ADDRESS 0 +#endif + +#ifndef configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H + #define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0 +#endif + /* The following event macros are embedded in the kernel API calls. */ #ifndef traceMOVED_TASK_TO_READY_STATE @@ -474,6 +448,10 @@ extern "C" { #define traceQUEUE_PEEK( pxQueue ) #endif +#ifndef traceQUEUE_PEEK_FAILED + #define traceQUEUE_PEEK_FAILED( pxQueue ) +#endif + #ifndef traceQUEUE_PEEK_FROM_ISR #define traceQUEUE_PEEK_FROM_ISR( pxQueue ) #endif @@ -658,6 +636,58 @@ extern "C" { #define traceTASK_NOTIFY_GIVE_FROM_ISR() #endif +#ifndef traceSTREAM_BUFFER_CREATE_FAILED + #define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED + #define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE + #define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_DELETE + #define traceSTREAM_BUFFER_DELETE( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RESET + #define traceSTREAM_BUFFER_RESET( xStreamBuffer ) +#endif + +#ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND + #define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND + #define traceSTREAM_BUFFER_SEND( xStreamBuffer, xBytesSent ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND_FAILED + #define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND_FROM_ISR + #define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xBytesSent ) +#endif + +#ifndef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE + #define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE + #define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE_FAILED + #define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE_FROM_ISR + #define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength ) +#endif + #ifndef configGENERATE_RUN_TIME_STATS #define configGENERATE_RUN_TIME_STATS 0 #endif @@ -708,6 +738,10 @@ extern "C" { #define configUSE_TICKLESS_IDLE 0 #endif +#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING + #define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x ) +#endif + #ifndef configPRE_SLEEP_PROCESSING #define configPRE_SLEEP_PROCESSING( x ) #endif @@ -724,6 +758,10 @@ extern "C" { #define portTASK_USES_FLOATING_POINT() #endif +#ifndef portTASK_CALLS_SECURE_FUNCTIONS + #define portTASK_CALLS_SECURE_FUNCTIONS() +#endif + #ifndef configUSE_TIME_SLICING #define configUSE_TIME_SLICING 1 #endif @@ -768,6 +806,10 @@ extern "C" { #define configUSE_TASK_NOTIFICATIONS 1 #endif +#ifndef configUSE_POSIX_ERRNO + #define configUSE_POSIX_ERRNO 0 +#endif + #ifndef portTICK_TYPE_IS_ATOMIC #define portTICK_TYPE_IS_ATOMIC 0 #endif @@ -782,6 +824,19 @@ extern "C" { #define configSUPPORT_DYNAMIC_ALLOCATION 1 #endif +#ifndef configSTACK_DEPTH_TYPE + /* Defaults to uint16_t for backward compatibility, but can be overridden + in FreeRTOSConfig.h if uint16_t is too restrictive. */ + #define configSTACK_DEPTH_TYPE uint16_t +#endif + +#ifndef configMESSAGE_BUFFER_LENGTH_TYPE + /* Defaults to size_t for backward compatibility, but can be overridden + in FreeRTOSConfig.h if lengths will always be less than the number of bytes + in a size_t. */ + #define configMESSAGE_BUFFER_LENGTH_TYPE size_t +#endif + /* Sanity check the configuration. */ #if( configUSE_TICKLESS_IDLE != 0 ) #if( INCLUDE_vTaskSuspend != 1 ) @@ -797,6 +852,10 @@ extern "C" { #error configUSE_MUTEXES must be set to 1 to use recursive mutexes #endif +#ifndef configINITIAL_TICK_COUNT + #define configINITIAL_TICK_COUNT 0 +#endif + #if( portTICK_TYPE_IS_ATOMIC == 0 ) /* Either variables of tick type cannot be read atomically, or portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when @@ -820,6 +879,32 @@ V8 if desired. */ #define configENABLE_BACKWARD_COMPATIBILITY 1 #endif +#ifndef configPRINTF + /* configPRINTF() was not defined, so define it away to nothing. To use + configPRINTF() then define it as follows (where MyPrintFunction() is + provided by the application writer): + + void MyPrintFunction(const char *pcFormat, ... ); + #define configPRINTF( X ) MyPrintFunction X + + Then call like a standard printf() function, but placing brackets around + all parameters so they are passed as a single parameter. For example: + configPRINTF( ("Value = %d", MyVariable) ); */ + #define configPRINTF( X ) +#endif + +#ifndef configMAX + /* The application writer has not provided their own MAX macro, so define + the following generic implementation. */ + #define configMAX( a, b ) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) ) +#endif + +#ifndef configMIN + /* The application writer has not provided their own MAX macro, so define + the following generic implementation. */ + #define configMIN( a, b ) ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) ) +#endif + #if configENABLE_BACKWARD_COMPATIBILITY == 1 #define eTaskStateGet eTaskGetState #define portTickType TickType_t @@ -847,6 +932,10 @@ V8 if desired. */ #define pdTASK_CODE TaskFunction_t #define xListItem ListItem_t #define xList List_t + + /* For libraries that break the list data hiding, and access list structure + members directly (which is not supposed to be done). */ + #define pxContainer pvContainer #endif /* configENABLE_BACKWARD_COMPATIBILITY */ #if( configUSE_ALTERNATIVE_API != 0 ) @@ -917,7 +1006,7 @@ typedef struct xSTATIC_TCB UBaseType_t uxDummy5; void *pxDummy6; uint8_t ucDummy7[ configMAX_TASK_NAME_LEN ]; - #if ( portSTACK_GROWTH > 0 ) + #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) void *pxDummy8; #endif #if ( portCRITICAL_NESTING_IN_TCB == 1 ) @@ -949,6 +1038,12 @@ typedef struct xSTATIC_TCB uint8_t uxDummy20; #endif + #if( INCLUDE_xTaskAbortDelay == 1 ) + uint8_t ucDummy21; + #endif + #if ( configUSE_POSIX_ERRNO == 1 ) + int iDummy22; + #endif } StaticTask_t; /* @@ -1044,17 +1139,45 @@ typedef struct xSTATIC_TIMER StaticListItem_t xDummy2; TickType_t xDummy3; UBaseType_t uxDummy4; - void *pvDummy5[ 2 ]; + void *pvDummy5; + TaskFunction_t pvDummy6; #if( configUSE_TRACE_FACILITY == 1 ) - UBaseType_t uxDummy6; + UBaseType_t uxDummy7; #endif #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) - uint8_t ucDummy7; + uint8_t ucDummy8; #endif } StaticTimer_t; +/* +* In line with software engineering best practice, especially when supplying a +* library that is likely to change in future versions, FreeRTOS implements a +* strict data hiding policy. This means the stream buffer structure used +* internally by FreeRTOS is not accessible to application code. However, if +* the application writer wants to statically allocate the memory required to +* create a stream buffer then the size of the stream buffer object needs to be +* know. The StaticStreamBuffer_t structure below is provided for this purpose. +* Its size and alignment requirements are guaranteed to match those of the +* genuine structure, no matter which architecture is being used, and no matter +* how the values in FreeRTOSConfig.h are set. Its contents are somewhat +* obfuscated in the hope users will recognise that it would be unwise to make +* direct use of the structure members. +*/ +typedef struct xSTATIC_STREAM_BUFFER +{ + size_t uxDummy1[ 4 ]; + void * pvDummy2[ 3 ]; + uint8_t ucDummy3; + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy4; + #endif +} StaticStreamBuffer_t; + +/* Message buffers are built on stream buffers. */ +typedef StaticStreamBuffer_t StaticMessageBuffer_t; + #ifdef __cplusplus } #endif diff --git a/os/freertos/include/StackMacros.h b/os/freertos/include/StackMacros.h index 13c6b829b..b6eaec3fe 100644 --- a/os/freertos/include/StackMacros.h +++ b/os/freertos/include/StackMacros.h @@ -1,75 +1,37 @@ /* - FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ + * FreeRTOS Kernel V10.1.1 + * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ #ifndef STACK_MACROS_H #define STACK_MACROS_H +#ifndef _MSC_VER /* Visual Studio doesn't support #warning. */ + #warning The name of this file has changed to stack_macros.h. Please update your code accordingly. This source file (which has the original name) will be removed in future released. +#endif + /* * Call the stack overflow hook function if the stack of the task being swapped * out is currently overflowed, or looks like it might have overflowed in the diff --git a/os/freertos/include/croutine.h b/os/freertos/include/croutine.h index 4f003a0ba..6f66fdcb1 100644 --- a/os/freertos/include/croutine.h +++ b/os/freertos/include/croutine.h @@ -1,71 +1,29 @@ /* - FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ + * FreeRTOS Kernel V10.1.1 + * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ #ifndef CO_ROUTINE_H #define CO_ROUTINE_H diff --git a/os/freertos/include/deprecated_definitions.h b/os/freertos/include/deprecated_definitions.h index 4ea816ccf..c74784736 100644 --- a/os/freertos/include/deprecated_definitions.h +++ b/os/freertos/include/deprecated_definitions.h @@ -1,71 +1,29 @@ /* - FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ + * FreeRTOS Kernel V10.1.1 + * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ #ifndef DEPRECATED_DEFINITIONS_H #define DEPRECATED_DEFINITIONS_H diff --git a/os/freertos/include/event_groups.h b/os/freertos/include/event_groups.h index 7331c91c2..e40c544b8 100644 --- a/os/freertos/include/event_groups.h +++ b/os/freertos/include/event_groups.h @@ -1,71 +1,29 @@ /* - FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ + * FreeRTOS Kernel V10.1.1 + * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ #ifndef EVENT_GROUPS_H #define EVENT_GROUPS_H @@ -120,7 +78,8 @@ extern "C" { * \defgroup EventGroupHandle_t EventGroupHandle_t * \ingroup EventGroup */ -typedef void * EventGroupHandle_t; +struct EventGroupDef_t; +typedef struct EventGroupDef_t * EventGroupHandle_t; /* * The type that holds event bits always matches TickType_t - therefore the @@ -446,7 +405,7 @@ EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBit * \ingroup EventGroup */ #if( configUSE_TRACE_FACILITY == 1 ) - BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION; + BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; #else #define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ) #endif @@ -786,6 +745,7 @@ void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToCl #if (configUSE_TRACE_FACILITY == 1) UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) PRIVILEGED_FUNCTION; + void vEventGroupSetNumber( void* xEventGroup, UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION; #endif #ifdef __cplusplus diff --git a/os/freertos/include/list.h b/os/freertos/include/list.h index a080d27de..43e0ffffb 100644 --- a/os/freertos/include/list.h +++ b/os/freertos/include/list.h @@ -1,71 +1,29 @@ /* - FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ + * FreeRTOS Kernel V10.1.1 + * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ /* * This is the list implementation used by the scheduler. While it is tailored @@ -178,6 +136,7 @@ use of FreeRTOS.*/ /* * Definition of the only type of object that a list can contain. */ +struct xLIST; struct xLIST_ITEM { listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ @@ -185,7 +144,7 @@ struct xLIST_ITEM struct xLIST_ITEM * configLIST_VOLATILE pxNext; /*< Pointer to the next ListItem_t in the list. */ struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; /*< Pointer to the previous ListItem_t in the list. */ void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */ - void * configLIST_VOLATILE pvContainer; /*< Pointer to the list in which this list item is placed (if any). */ + struct xLIST * configLIST_VOLATILE pxContainer; /*< Pointer to the list in which this list item is placed (if any). */ listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ }; typedef struct xLIST_ITEM ListItem_t; /* For some reason lint wants this as two separate definitions. */ @@ -205,7 +164,7 @@ typedef struct xMINI_LIST_ITEM MiniListItem_t; typedef struct xLIST { listFIRST_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ - configLIST_VOLATILE UBaseType_t uxNumberOfItems; + volatile UBaseType_t uxNumberOfItems; ListItem_t * configLIST_VOLATILE pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */ MiniListItem_t xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */ listSECOND_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ @@ -288,7 +247,7 @@ typedef struct xLIST * \page listLIST_IS_EMPTY listLIST_IS_EMPTY * \ingroup LinkedList */ -#define listLIST_IS_EMPTY( pxList ) ( ( BaseType_t ) ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ) +#define listLIST_IS_EMPTY( pxList ) ( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE ) /* * Access macro to return the number of items in the list. @@ -356,7 +315,7 @@ List_t * const pxConstList = ( pxList ); \ * @param pxListItem The list item we want to know if is in the list. * @return pdTRUE if the list item is in the list, otherwise pdFALSE. */ -#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( BaseType_t ) ( ( pxListItem )->pvContainer == ( void * ) ( pxList ) ) ) +#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) ) /* * Return the list a list item is contained within (referenced from). @@ -364,7 +323,7 @@ List_t * const pxConstList = ( pxList ); \ * @param pxListItem The list item being queried. * @return A pointer to the List_t object that references the pxListItem */ -#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pvContainer ) +#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pxContainer ) /* * This provides a crude means of knowing if a list has been initialised, as diff --git a/os/freertos/include/message_buffer.h b/os/freertos/include/message_buffer.h new file mode 100644 index 000000000..e62e42d28 --- /dev/null +++ b/os/freertos/include/message_buffer.h @@ -0,0 +1,798 @@ +/* + * FreeRTOS Kernel V10.1.1 + * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +/* + * Message buffers build functionality on top of FreeRTOS stream buffers. + * Whereas stream buffers are used to send a continuous stream of data from one + * task or interrupt to another, message buffers are used to send variable + * length discrete messages from one task or interrupt to another. Their + * implementation is light weight, making them particularly suited for interrupt + * to task and core to core communication scenarios. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xMessageBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xMessageBufferRead()) inside a critical section and set the receive + * timeout to 0. + * + * Message buffers hold variable length messages. To enable that, when a + * message is written to the message buffer an additional sizeof( size_t ) bytes + * are also written to store the message's length (that happens internally, with + * the API function). sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so writing a 10 byte message to a message buffer on a 32-bit + * architecture will actually reduce the available space in the message buffer + * by 14 bytes (10 byte are used by the message, and 4 bytes to hold the length + * of the message). + */ + +#ifndef FREERTOS_MESSAGE_BUFFER_H +#define FREERTOS_MESSAGE_BUFFER_H + +/* Message buffers are built onto of stream buffers. */ +#include "stream_buffer.h" + +#if defined( __cplusplus ) +extern "C" { +#endif + +/** + * Type by which message buffers are referenced. For example, a call to + * xMessageBufferCreate() returns an MessageBufferHandle_t variable that can + * then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(), + * etc. + */ +typedef void * MessageBufferHandle_t; + +/*-----------------------------------------------------------*/ + +/** + * message_buffer.h + * +
+MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );
+
+ * + * Creates a new message buffer using dynamically allocated memory. See + * xMessageBufferCreateStatic() for a version that uses statically allocated + * memory (memory that is allocated at compile time). + * + * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in + * FreeRTOSConfig.h for xMessageBufferCreate() to be available. + * + * @param xBufferSizeBytes The total number of bytes (not messages) the message + * buffer will be able to hold at any one time. When a message is written to + * the message buffer an additional sizeof( size_t ) bytes are also written to + * store the message's length. sizeof( size_t ) is typically 4 bytes on a + * 32-bit architecture, so on most 32-bit architectures a 10 byte message will + * take up 14 bytes of message buffer space. + * + * @return If NULL is returned, then the message buffer cannot be created + * because there is insufficient heap memory available for FreeRTOS to allocate + * the message buffer data structures and storage area. A non-NULL value being + * returned indicates that the message buffer has been created successfully - + * the returned value should be stored as the handle to the created message + * buffer. + * + * Example use: +
+
+void vAFunction( void )
+{
+MessageBufferHandle_t xMessageBuffer;
+const size_t xMessageBufferSizeBytes = 100;
+
+    // Create a message buffer that can hold 100 bytes.  The memory used to hold
+    // both the message buffer structure and the messages themselves is allocated
+    // dynamically.  Each message added to the buffer consumes an additional 4
+    // bytes which are used to hold the lengh of the message.
+    xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes );
+
+    if( xMessageBuffer == NULL )
+    {
+        // There was not enough heap memory space available to create the
+        // message buffer.
+    }
+    else
+    {
+        // The message buffer was created successfully and can now be used.
+    }
+
+
+ * \defgroup xMessageBufferCreate xMessageBufferCreate + * \ingroup MessageBufferManagement + */ +#define xMessageBufferCreate( xBufferSizeBytes ) ( MessageBufferHandle_t ) xStreamBufferGenericCreate( xBufferSizeBytes, ( size_t ) 0, pdTRUE ) + +/** + * message_buffer.h + * +
+MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,
+                                                  uint8_t *pucMessageBufferStorageArea,
+                                                  StaticMessageBuffer_t *pxStaticMessageBuffer );
+
+ * Creates a new message buffer using statically allocated memory. See + * xMessageBufferCreate() for a version that uses dynamically allocated memory. + * + * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the + * pucMessageBufferStorageArea parameter. When a message is written to the + * message buffer an additional sizeof( size_t ) bytes are also written to store + * the message's length. sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so on most 32-bit architecture a 10 byte message will take up + * 14 bytes of message buffer space. The maximum number of bytes that can be + * stored in the message buffer is actually (xBufferSizeBytes - 1). + * + * @param pucMessageBufferStorageArea Must point to a uint8_t array that is at + * least xBufferSizeBytes + 1 big. This is the array to which messages are + * copied when they are written to the message buffer. + * + * @param pxStaticMessageBuffer Must point to a variable of type + * StaticMessageBuffer_t, which will be used to hold the message buffer's data + * structure. + * + * @return If the message buffer is created successfully then a handle to the + * created message buffer is returned. If either pucMessageBufferStorageArea or + * pxStaticmessageBuffer are NULL then NULL is returned. + * + * Example use: +
+
+// Used to dimension the array used to hold the messages.  The available space
+// will actually be one less than this, so 999.
+#define STORAGE_SIZE_BYTES 1000
+
+// Defines the memory that will actually hold the messages within the message
+// buffer.
+static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+
+// The variable used to hold the message buffer structure.
+StaticMessageBuffer_t xMessageBufferStruct;
+
+void MyFunction( void )
+{
+MessageBufferHandle_t xMessageBuffer;
+
+    xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucBufferStorage ),
+                                                 ucBufferStorage,
+                                                 &xMessageBufferStruct );
+
+    // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer
+    // parameters were NULL, xMessageBuffer will not be NULL, and can be used to
+    // reference the created message buffer in other message buffer API calls.
+
+    // Other code that uses the message buffer can go here.
+}
+
+
+ * \defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic + * \ingroup MessageBufferManagement + */ +#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) ( MessageBufferHandle_t ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, 0, pdTRUE, pucMessageBufferStorageArea, pxStaticMessageBuffer ) + +/** + * message_buffer.h + * +
+size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,
+                           const void *pvTxData,
+                           size_t xDataLengthBytes,
+                           TickType_t xTicksToWait );
+
+ *
+ * Sends a discrete message to the message buffer.  The message can be any
+ * length that fits within the buffer's free space, and is copied into the
+ * buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferSend() to write to a message buffer from a task.  Use
+ * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer to which a message is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the message that is to be copied into the
+ * message buffer.
+ *
+ * @param xDataLengthBytes The length of the message.  That is, the number of
+ * bytes to copy from pvTxData into the message buffer.  When a message is
+ * written to the message buffer an additional sizeof( size_t ) bytes are also
+ * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
+ * on a 32-bit architecture, so on most 32-bit architecture setting
+ * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
+ * bytes (20 bytes of message data and 4 bytes to hold the message length).
+ *
+ * @param xTicksToWait The maximum amount of time the calling task should remain
+ * in the Blocked state to wait for enough space to become available in the
+ * message buffer, should the message buffer have insufficient space when
+ * xMessageBufferSend() is called.  The calling task will never block if
+ * xTicksToWait is zero.  The block time is specified in tick periods, so the
+ * absolute time it represents is dependent on the tick frequency.  The macro
+ * pdMS_TO_TICKS() can be used to convert a time specified in milliseconds into
+ * a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will cause
+ * the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
+ * CPU time when they are in the Blocked state.
+ *
+ * @return The number of bytes written to the message buffer.  If the call to
+ * xMessageBufferSend() times out before there was enough space to write the
+ * message into the message buffer then zero is returned.  If the call did not
+ * time out then xDataLengthBytes is returned.
+ *
+ * Example use:
+
+void vAFunction( MessageBufferHandle_t xMessageBuffer )
+{
+size_t xBytesSent;
+uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+char *pcStringToSend = "String to send";
+const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+
+    // Send an array to the message buffer, blocking for a maximum of 100ms to
+    // wait for enough space to be available in the message buffer.
+    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+
+    if( xBytesSent != sizeof( ucArrayToSend ) )
+    {
+        // The call to xMessageBufferSend() times out before there was enough
+        // space in the buffer for the data to be written.
+    }
+
+    // Send the string to the message buffer.  Return immediately if there is
+    // not enough space in the buffer.
+    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The string could not be added to the message buffer because there was
+        // not enough free space in the buffer.
+    }
+}
+

+ * \defgroup xMessageBufferSend xMessageBufferSend
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) xStreamBufferSend( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait )
+
+/**
+ * message_buffer.h
+ *
+
+size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,
+                                  const void *pvTxData,
+                                  size_t xDataLengthBytes,
+                                  BaseType_t *pxHigherPriorityTaskWoken );
+
+ *
+ * Interrupt safe version of the API function that sends a discrete message to
+ * the message buffer.  The message can be any length that fits within the
+ * buffer's free space, and is copied into the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferSend() to write to a message buffer from a task.  Use
+ * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer to which a message is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the message that is to be copied into the
+ * message buffer.
+ *
+ * @param xDataLengthBytes The length of the message.  That is, the number of
+ * bytes to copy from pvTxData into the message buffer.  When a message is
+ * written to the message buffer an additional sizeof( size_t ) bytes are also
+ * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
+ * on a 32-bit architecture, so on most 32-bit architecture setting
+ * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
+ * bytes (20 bytes of message data and 4 bytes to hold the message length).
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
+ * have a task blocked on it waiting for data.  Calling
+ * xMessageBufferSendFromISR() can make data available, and so cause a task that
+ * was waiting for data to leave the Blocked state.  If calling
+ * xMessageBufferSendFromISR() causes a task to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently executing task (the
+ * task that was interrupted), then, internally, xMessageBufferSendFromISR()
+ * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
+ * xMessageBufferSendFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  This will
+ * ensure that the interrupt returns directly to the highest priority Ready
+ * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
+ * is passed into the function.  See the code example below for an example.
+ *
+ * @return The number of bytes actually written to the message buffer.  If the
+ * message buffer didn't have enough free space for the message to be stored
+ * then 0 is returned, otherwise xDataLengthBytes is returned.
+ *
+ * Example use:
+
+// A message buffer that has already been created.
+MessageBufferHandle_t xMessageBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+size_t xBytesSent;
+char *pcStringToSend = "String to send";
+BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+
+    // Attempt to send the string to the message buffer.
+    xBytesSent = xMessageBufferSendFromISR( xMessageBuffer,
+                                            ( void * ) pcStringToSend,
+                                            strlen( pcStringToSend ),
+                                            &xHigherPriorityTaskWoken );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The string could not be added to the message buffer because there was
+        // not enough free space in the buffer.
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xMessageBufferSendFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+

+ * \defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferSendFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+
+size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,
+                              void *pvRxData,
+                              size_t xBufferLengthBytes,
+                              TickType_t xTicksToWait );
+

+ *
+ * Receives a discrete message from a message buffer.  Messages can be of
+ * variable length and are copied out of the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
+ * xMessageBufferReceiveFromISR() to read from a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer from which a message
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received message is
+ * to be copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
+ * parameter.  This sets the maximum length of the message that can be received.
+ * If xBufferLengthBytes is too small to hold the next message then the message
+ * will be left in the message buffer and 0 will be returned.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for a message, should the message buffer be empty.
+ * xMessageBufferReceive() will return immediately if xTicksToWait is zero and
+ * the message buffer is empty.  The block time is specified in tick periods, so
+ * the absolute time it represents is dependent on the tick frequency.  The
+ * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
+ * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
+ * cause the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
+ * CPU time when they are in the Blocked state.
+ *
+ * @return The length, in bytes, of the message read from the message buffer, if
+ * any.  If xMessageBufferReceive() times out before a message became available
+ * then zero is returned.  If the length of the message is greater than
+ * xBufferLengthBytes then the message will be left in the message buffer and
+ * zero is returned.
+ *
+ * Example use:
+
+void vAFunction( MessageBuffer_t xMessageBuffer )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+
+    // Receive the next message from the message buffer.  Wait in the Blocked
+    // state (so not using any CPU processing time) for a maximum of 100ms for
+    // a message to become available.
+    xReceivedBytes = xMessageBufferReceive( xMessageBuffer,
+                                            ( void * ) ucRxData,
+                                            sizeof( ucRxData ),
+                                            xBlockTime );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains a message that is xReceivedBytes long.  Process
+        // the message here....
+    }
+}
+

+ * \defgroup xMessageBufferReceive xMessageBufferReceive
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) xStreamBufferReceive( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait )
+
+
+/**
+ * message_buffer.h
+ *
+
+size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,
+                                     void *pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * An interrupt safe version of the API function that receives a discrete
+ * message from a message buffer.  Messages can be of variable length and are
+ * copied out of the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
+ * xMessageBufferReceiveFromISR() to read from a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer from which a message
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received message is
+ * to be copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
+ * parameter.  This sets the maximum length of the message that can be received.
+ * If xBufferLengthBytes is too small to hold the next message then the message
+ * will be left in the message buffer and 0 will be returned.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
+ * have a task blocked on it waiting for space to become available.  Calling
+ * xMessageBufferReceiveFromISR() can make space available, and so cause a task
+ * that is waiting for space to leave the Blocked state.  If calling
+ * xMessageBufferReceiveFromISR() causes a task to leave the Blocked state, and
+ * the unblocked task has a priority higher than the currently executing task
+ * (the task that was interrupted), then, internally,
+ * xMessageBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
+ * If xMessageBufferReceiveFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  That will
+ * ensure the interrupt returns directly to the highest priority Ready state
+ * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
+ * passed into the function.  See the code example below for an example.
+ *
+ * @return The length, in bytes, of the message read from the message buffer, if
+ * any.
+ *
+ * Example use:
+
+// A message buffer that has already been created.
+MessageBuffer_t xMessageBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+
+    // Receive the next message from the message buffer.
+    xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer,
+                                                  ( void * ) ucRxData,
+                                                  sizeof( ucRxData ),
+                                                  &xHigherPriorityTaskWoken );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains a message that is xReceivedBytes long.  Process
+        // the message here....
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xMessageBufferReceiveFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+

+ * \defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferReceiveFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+
+void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer );
+

+ *
+ * Deletes a message buffer that was previously created using a call to
+ * xMessageBufferCreate() or xMessageBufferCreateStatic().  If the message
+ * buffer was created using dynamic memory (that is, by xMessageBufferCreate()),
+ * then the allocated memory is freed.
+ *
+ * A message buffer handle must not be used after the message buffer has been
+ * deleted.
+ *
+ * @param xMessageBuffer The handle of the message buffer to be deleted.
+ *
+ */
+#define vMessageBufferDelete( xMessageBuffer ) vStreamBufferDelete( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+
+BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer ) );
+

+ *
+ * Tests to see if a message buffer is full.  A message buffer is full if it
+ * cannot accept any more messages, of any size, until space is made available
+ * by a message being removed from the message buffer.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return If the message buffer referenced by xMessageBuffer is full then
+ * pdTRUE is returned.  Otherwise pdFALSE is returned.
+ */
+#define xMessageBufferIsFull( xMessageBuffer ) xStreamBufferIsFull( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+
+BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer ) );
+

+ *
+ * Tests to see if a message buffer is empty (does not contain any messages).
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return If the message buffer referenced by xMessageBuffer is empty then
+ * pdTRUE is returned.  Otherwise pdFALSE is returned.
+ *
+ */
+#define xMessageBufferIsEmpty( xMessageBuffer ) xStreamBufferIsEmpty( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+
+BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer );
+

+ *
+ * Resets a message buffer to its initial empty state, discarding any message it
+ * contained.
+ *
+ * A message buffer can only be reset if there are no tasks blocked on it.
+ *
+ * @param xMessageBuffer The handle of the message buffer being reset.
+ *
+ * @return If the message buffer was reset then pdPASS is returned.  If the
+ * message buffer could not be reset because either there was a task blocked on
+ * the message queue to wait for space to become available, or to wait for a
+ * a message to be available, then pdFAIL is returned.
+ *
+ * \defgroup xMessageBufferReset xMessageBufferReset
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReset( xMessageBuffer ) xStreamBufferReset( ( StreamBufferHandle_t ) xMessageBuffer )
+
+
+/**
+ * message_buffer.h
+
+size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ) );
+

+ * Returns the number of bytes of free space in the message buffer.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return The number of bytes that can be written to the message buffer before
+ * the message buffer would be full.  When a message is written to the message
+ * buffer an additional sizeof( size_t ) bytes are also written to store the
+ * message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit
+ * architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size
+ * of the largest message that can be written to the message buffer is 6 bytes.
+ *
+ * \defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSpaceAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+ 
+ size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer ) );
+ 

+ * Returns the length (in bytes) of the next message in a message buffer.
+ * Useful if xMessageBufferReceive() returned 0 because the size of the buffer
+ * passed into xMessageBufferReceive() was too small to hold the next message.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return The length (in bytes) of the next message in the message buffer, or 0
+ * if the message buffer is empty.
+ *
+ * \defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferNextLengthBytes( xMessageBuffer ) xStreamBufferNextMessageLengthBytes( ( StreamBufferHandle_t ) xMessageBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * message_buffer.h
+ *
+
+BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * For advanced users only.
+ *
+ * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is sent to a message buffer or stream buffer.  If there was a task that
+ * was blocked on the message or stream buffer waiting for data to arrive then
+ * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
+ * from the Blocked state.  xMessageBufferSendCompletedFromISR() does the same
+ * thing.  It is provided to enable application writers to implement their own
+ * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which data was
+ * written.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xMessageBufferSendCompletedFromISR().  If calling
+ * xMessageBufferSendCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferSendCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+
+BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * For advanced users only.
+ *
+ * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is read out of a message buffer or stream buffer.  If there was a task
+ * that was blocked on the message or stream buffer waiting for data to arrive
+ * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
+ * remove it from the Blocked state.  xMessageBufferReceiveCompletedFromISR()
+ * does the same thing.  It is provided to enable application writers to
+ * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
+ * ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which data was
+ * read.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xMessageBufferReceiveCompletedFromISR().  If calling
+ * xMessageBufferReceiveCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferReceiveCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+
+#if defined( __cplusplus )
+} /* extern "C" */
+#endif
+
+#endif	/* !defined( FREERTOS_MESSAGE_BUFFER_H ) */
diff --git a/os/freertos/include/mpu_prototypes.h b/os/freertos/include/mpu_prototypes.h
index 8f7500b02..8510d402d 100644
--- a/os/freertos/include/mpu_prototypes.h
+++ b/os/freertos/include/mpu_prototypes.h
@@ -1,71 +1,29 @@
 /*
-    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
-
-    ***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-    ***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-    the FAQ page "My application does not run, what could be wrong?".  Have you
-    defined configASSERT()?
-
-    http://www.FreeRTOS.org/support - In return for receiving this top quality
-    embedded software for free we request you assist our global community by
-    participating in the support forum.
-
-    http://www.FreeRTOS.org/training - Investing in training allows your team to
-    be as productive as possible as early as possible.  Now you can receive
-    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-    Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
+ * FreeRTOS Kernel V10.1.1
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
 
 /*
  * When the MPU is used the standard (non MPU) API functions are mapped to
@@ -79,16 +37,17 @@
 #ifndef MPU_PROTOTYPES_H
 #define MPU_PROTOTYPES_H
 
-/* MPU versions of tasks.h API function. */
+/* MPU versions of tasks.h API functions. */
 BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask );
 TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer );
 BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask );
+BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask );
 void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );
 void MPU_vTaskDelete( TaskHandle_t xTaskToDelete );
 void MPU_vTaskDelay( const TickType_t xTicksToDelay );
 void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement );
 BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask );
-UBaseType_t MPU_uxTaskPriorityGet( TaskHandle_t xTask );
+UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask );
 eTaskState MPU_eTaskGetState( TaskHandle_t xTask );
 void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );
 void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );
@@ -122,9 +81,11 @@ BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * c
 void MPU_vTaskMissedYield( void );
 BaseType_t MPU_xTaskGetSchedulerState( void );
 
-/* MPU versions of queue.h API function. */
+/* MPU versions of queue.h API functions. */
 BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition );
-BaseType_t MPU_xQueueGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, const BaseType_t xJustPeek );
+BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait );
+BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait );
+BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait );
 UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue );
 UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue );
 void MPU_vQueueDelete( QueueHandle_t xQueue );
@@ -132,7 +93,7 @@ QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType );
 QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue );
 QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount );
 QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue );
-void* MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore );
+TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore );
 BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait );
 BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex );
 void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName );
@@ -149,9 +110,9 @@ void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber )
 UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue );
 uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue );
 
-/* MPU versions of timers.h API function. */
-TimerHandle_t MPU_xTimerCreate(	const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction );
-TimerHandle_t MPU_xTimerCreateStatic(	const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer );
+/* MPU versions of timers.h API functions. */
+TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction );
+TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer );
 void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer );
 void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );
 BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer );
@@ -163,7 +124,7 @@ TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer );
 BaseType_t MPU_xTimerCreateTimerTask( void );
 BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait );
 
-/* MPU versions of event_group.h API function. */
+/* MPU versions of event_group.h API functions. */
 EventGroupHandle_t MPU_xEventGroupCreate( void );
 EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer );
 EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait );
@@ -173,5 +134,23 @@ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits
 void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup );
 UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup );
 
+/* MPU versions of message/stream_buffer.h API functions. */
+size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait );
+size_t MPU_xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, BaseType_t * const pxHigherPriorityTaskWoken );
+size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait );
+size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer );
+size_t MPU_xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, BaseType_t * const pxHigherPriorityTaskWoken );
+void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
+BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
+BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
+BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
+size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
+size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
+BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
+StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer );
+StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer );
+
+
+
 #endif /* MPU_PROTOTYPES_H */
 
diff --git a/os/freertos/include/mpu_wrappers.h b/os/freertos/include/mpu_wrappers.h
index 78f5a9aea..f7a53c5e5 100644
--- a/os/freertos/include/mpu_wrappers.h
+++ b/os/freertos/include/mpu_wrappers.h
@@ -1,71 +1,29 @@
 /*
-    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
-
-    ***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-    ***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-    the FAQ page "My application does not run, what could be wrong?".  Have you
-    defined configASSERT()?
-
-    http://www.FreeRTOS.org/support - In return for receiving this top quality
-    embedded software for free we request you assist our global community by
-    participating in the support forum.
-
-    http://www.FreeRTOS.org/training - Investing in training allows your team to
-    be as productive as possible as early as possible.  Now you can receive
-    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-    Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
+ * FreeRTOS Kernel V10.1.1
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
 
 #ifndef MPU_WRAPPERS_H
 #define MPU_WRAPPERS_H
@@ -130,7 +88,9 @@ only for ports that are using the MPU. */
 
 		/* Map standard queue.h API functions to the MPU equivalents. */
 		#define xQueueGenericSend						MPU_xQueueGenericSend
-		#define xQueueGenericReceive					MPU_xQueueGenericReceive
+		#define xQueueReceive							MPU_xQueueReceive
+		#define xQueuePeek								MPU_xQueuePeek
+		#define xQueueSemaphoreTake						MPU_xQueueSemaphoreTake
 		#define uxQueueMessagesWaiting					MPU_uxQueueMessagesWaiting
 		#define uxQueueSpacesAvailable					MPU_uxQueueSpacesAvailable
 		#define vQueueDelete							MPU_vQueueDelete
@@ -177,8 +137,29 @@ only for ports that are using the MPU. */
 		#define xEventGroupSync							MPU_xEventGroupSync
 		#define vEventGroupDelete						MPU_vEventGroupDelete
 
-		/* Remove the privileged function macro. */
+		/* Map standard message/stream_buffer.h API functions to the MPU
+		equivalents. */
+		#define xStreamBufferSend						MPU_xStreamBufferSend
+		#define xStreamBufferSendFromISR				MPU_xStreamBufferSendFromISR
+		#define xStreamBufferReceive					MPU_xStreamBufferReceive
+		#define xStreamBufferNextMessageLengthBytes		MPU_xStreamBufferNextMessageLengthBytes
+		#define xStreamBufferReceiveFromISR				MPU_xStreamBufferReceiveFromISR
+		#define vStreamBufferDelete						MPU_vStreamBufferDelete
+		#define xStreamBufferIsFull						MPU_xStreamBufferIsFull
+		#define xStreamBufferIsEmpty					MPU_xStreamBufferIsEmpty
+		#define xStreamBufferReset						MPU_xStreamBufferReset
+		#define xStreamBufferSpacesAvailable			MPU_xStreamBufferSpacesAvailable
+		#define xStreamBufferBytesAvailable				MPU_xStreamBufferBytesAvailable
+		#define xStreamBufferSetTriggerLevel			MPU_xStreamBufferSetTriggerLevel
+		#define xStreamBufferGenericCreate				MPU_xStreamBufferGenericCreate
+		#define xStreamBufferGenericCreateStatic		MPU_xStreamBufferGenericCreateStatic
+
+
+		/* Remove the privileged function macro, but keep the PRIVILEGED_DATA
+		macro so applications can place data in privileged access sections
+		(useful when using statically allocated objects). */
 		#define PRIVILEGED_FUNCTION
+		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
 
 	#else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
 
diff --git a/os/freertos/include/portable.h b/os/freertos/include/portable.h
index b9f8be39d..15f0e650b 100644
--- a/os/freertos/include/portable.h
+++ b/os/freertos/include/portable.h
@@ -1,71 +1,29 @@
 /*
-    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
-
-    ***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-    ***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-    the FAQ page "My application does not run, what could be wrong?".  Have you
-    defined configASSERT()?
-
-    http://www.FreeRTOS.org/support - In return for receiving this top quality
-    embedded software for free we request you assist our global community by
-    participating in the support forum.
-
-    http://www.FreeRTOS.org/training - Investing in training allows your team to
-    be as productive as possible as early as possible.  Now you can receive
-    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-    Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
+ * FreeRTOS Kernel V10.1.1
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
 
 /*-----------------------------------------------------------
  * Portable layer API.  Each function must be defined for each port.
diff --git a/os/freertos/include/projdefs.h b/os/freertos/include/projdefs.h
index 0b63fd8a9..c8621737b 100644
--- a/os/freertos/include/projdefs.h
+++ b/os/freertos/include/projdefs.h
@@ -1,71 +1,29 @@
 /*
-    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
-
-    ***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-    ***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-    the FAQ page "My application does not run, what could be wrong?".  Have you
-    defined configASSERT()?
-
-    http://www.FreeRTOS.org/support - In return for receiving this top quality
-    embedded software for free we request you assist our global community by
-    participating in the support forum.
-
-    http://www.FreeRTOS.org/training - Investing in training allows your team to
-    be as productive as possible as early as possible.  Now you can receive
-    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-    Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
+ * FreeRTOS Kernel V10.1.1
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
 
 #ifndef PROJDEFS_H
 #define PROJDEFS_H
@@ -152,8 +110,13 @@ itself. */
 
 /* The following endian values are used by FreeRTOS+ components, not FreeRTOS
 itself. */
-#define pdFREERTOS_LITTLE_ENDIAN	0
-#define pdFREERTOS_BIG_ENDIAN		1
+#define pdFREERTOS_LITTLE_ENDIAN		0
+#define pdFREERTOS_BIG_ENDIAN			1
+
+/* Re-defining endian values for generic naming. */
+#define pdLITTLE_ENDIAN					pdFREERTOS_LITTLE_ENDIAN
+#define pdBIG_ENDIAN					pdFREERTOS_BIG_ENDIAN
+
 
 #endif /* PROJDEFS_H */
 
diff --git a/os/freertos/include/queue.h b/os/freertos/include/queue.h
index 30be36013..1967cca94 100644
--- a/os/freertos/include/queue.h
+++ b/os/freertos/include/queue.h
@@ -1,71 +1,29 @@
 /*
-    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
-
-    ***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-    ***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-    the FAQ page "My application does not run, what could be wrong?".  Have you
-    defined configASSERT()?
-
-    http://www.FreeRTOS.org/support - In return for receiving this top quality
-    embedded software for free we request you assist our global community by
-    participating in the support forum.
-
-    http://www.FreeRTOS.org/training - Investing in training allows your team to
-    be as productive as possible as early as possible.  Now you can receive
-    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-    Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
+ * FreeRTOS Kernel V10.1.1
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
 
 
 #ifndef QUEUE_H
@@ -79,27 +37,29 @@
 extern "C" {
 #endif
 
+#include "task.h"
 
 /**
  * Type by which queues are referenced.  For example, a call to xQueueCreate()
  * returns an QueueHandle_t variable that can then be used as a parameter to
  * xQueueSend(), xQueueReceive(), etc.
  */
-typedef void * QueueHandle_t;
+struct QueueDefinition; /* Using old naming convention so as not to break kernel aware debuggers. */
+typedef struct QueueDefinition * QueueHandle_t;
 
 /**
  * Type by which queue sets are referenced.  For example, a call to
  * xQueueCreateSet() returns an xQueueSet variable that can then be used as a
  * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc.
  */
-typedef void * QueueSetHandle_t;
+typedef struct QueueDefinition * QueueSetHandle_t;
 
 /**
  * Queue sets can contain both queues and semaphores, so the
  * QueueSetMemberHandle_t is defined as a type to be used where a parameter or
  * return value can be either an QueueHandle_t or an SemaphoreHandle_t.
  */
-typedef void * QueueSetMemberHandle_t;
+typedef struct QueueDefinition * QueueSetMemberHandle_t;
 
 /* For internal use only. */
 #define	queueSEND_TO_BACK		( ( BaseType_t ) 0 )
@@ -282,8 +242,6 @@ typedef void * QueueSetMemberHandle_t;
 							   );
  * 

  *
- * This is a macro that calls xQueueGenericSend().
- *
  * Post an item to the front of a queue.  The item is queued by copy, not by
  * reference.  This function must not be called from an interrupt service
  * routine.  See xQueueSendFromISR () for an alternative which may be used
@@ -696,12 +654,10 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQ
  * 
  BaseType_t xQueuePeek(
 							 QueueHandle_t xQueue,
-							 void *pvBuffer,
+							 void * const pvBuffer,
 							 TickType_t xTicksToWait
 						 );

  *
- * This is a macro that calls the xQueueGenericReceive() function.
- *
  * Receive an item from a queue without removing the item from the queue.
  * The item is received by copy so a buffer of adequate size must be
  * provided.  The number of bytes copied into the buffer was defined when
@@ -782,10 +738,10 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQ
 	// ... Rest of task code.
  }
  

- * \defgroup xQueueReceive xQueueReceive
+ * \defgroup xQueuePeek xQueuePeek
  * \ingroup QueueManagement
  */
-#define xQueuePeek( xQueue, pvBuffer, xTicksToWait ) xQueueGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdTRUE )
+BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
 
 /**
  * queue. h
@@ -829,8 +785,6 @@ BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer ) PRIV
 								 TickType_t xTicksToWait
 							);

  *
- * This is a macro that calls the xQueueGenericReceive() function.
- *
  * Receive an item from a queue.  The item is received by copy so a buffer of
  * adequate size must be provided.  The number of bytes copied into the buffer
  * was defined when the queue was created.
@@ -911,106 +865,7 @@ BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer ) PRIV
  * \defgroup xQueueReceive xQueueReceive
  * \ingroup QueueManagement
  */
-#define xQueueReceive( xQueue, pvBuffer, xTicksToWait ) xQueueGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdFALSE )
-
-
-/**
- * queue. h
- * 
- BaseType_t xQueueGenericReceive(
-									   QueueHandle_t	xQueue,
-									   void	*pvBuffer,
-									   TickType_t	xTicksToWait
-									   BaseType_t	xJustPeek
-									);

- *
- * It is preferred that the macro xQueueReceive() be used rather than calling
- * this function directly.
- *
- * Receive an item from a queue.  The item is received by copy so a buffer of
- * adequate size must be provided.  The number of bytes copied into the buffer
- * was defined when the queue was created.
- *
- * This function must not be used in an interrupt service routine.  See
- * xQueueReceiveFromISR for an alternative that can.
- *
- * @param xQueue The handle to the queue from which the item is to be
- * received.
- *
- * @param pvBuffer Pointer to the buffer into which the received item will
- * be copied.
- *
- * @param xTicksToWait The maximum amount of time the task should block
- * waiting for an item to receive should the queue be empty at the time
- * of the call.	 The time is defined in tick periods so the constant
- * portTICK_PERIOD_MS should be used to convert to real time if this is required.
- * xQueueGenericReceive() will return immediately if the queue is empty and
- * xTicksToWait is 0.
- *
- * @param xJustPeek When set to true, the item received from the queue is not
- * actually removed from the queue - meaning a subsequent call to
- * xQueueReceive() will return the same item.  When set to false, the item
- * being received from the queue is also removed from the queue.
- *
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
- *
- * Example usage:
-   
- struct AMessage
- {
-	char ucMessageID;
-	char ucData[ 20 ];
- } xMessage;
-
- QueueHandle_t xQueue;
-
- // Task to create a queue and post a value.
- void vATask( void *pvParameters )
- {
- struct AMessage *pxMessage;
-
-	// Create a queue capable of containing 10 pointers to AMessage structures.
-	// These should be passed by pointer as they contain a lot of data.
-	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
-	if( xQueue == 0 )
-	{
-		// Failed to create the queue.
-	}
-
-	// ...
-
-	// Send a pointer to a struct AMessage object.  Don't block if the
-	// queue is already full.
-	pxMessage = & xMessage;
-	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
-
-	// ... Rest of task code.
- }
-
- // Task to receive from the queue.
- void vADifferentTask( void *pvParameters )
- {
- struct AMessage *pxRxedMessage;
-
-	if( xQueue != 0 )
-	{
-		// Receive a message on the created queue.  Block for 10 ticks if a
-		// message is not immediately available.
-		if( xQueueGenericReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
-		{
-			// pcRxedMessage now points to the struct AMessage variable posted
-			// by vATask.
-		}
-	}
-
-	// ... Rest of task code.
- }
- 

- * \defgroup xQueueReceive xQueueReceive
- * \ingroup QueueManagement
- */
-BaseType_t xQueueGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, const BaseType_t xJustPeek ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
 
 /**
  * queue. h
@@ -1560,14 +1415,16 @@ QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION
 QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
 QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
 QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
-void* xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
 
 /*
  * For internal use only.  Use xSemaphoreTakeMutexRecursive() or
  * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.
  */
 BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-BaseType_t xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;
 
 /*
  * Reset a queue back to its original empty state.  The return value is now
@@ -1598,7 +1455,7 @@ BaseType_t xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) PRIVILEGED_FUNCTION
  * preferably in ROM/Flash), not on the stack.
  */
 #if( configQUEUE_REGISTRY_SIZE > 0 )
-	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
 #endif
 
 /*
diff --git a/os/freertos/include/semphr.h b/os/freertos/include/semphr.h
index a674b02a4..53b158afb 100644
--- a/os/freertos/include/semphr.h
+++ b/os/freertos/include/semphr.h
@@ -1,71 +1,29 @@
 /*
-    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
-
-    ***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-    ***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-    the FAQ page "My application does not run, what could be wrong?".  Have you
-    defined configASSERT()?
-
-    http://www.FreeRTOS.org/support - In return for receiving this top quality
-    embedded software for free we request you assist our global community by
-    participating in the support forum.
-
-    http://www.FreeRTOS.org/training - Investing in training allows your team to
-    be as productive as possible as early as possible.  Now you can receive
-    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-    Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
+ * FreeRTOS Kernel V10.1.1
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
 
 #ifndef SEMAPHORE_H
 #define SEMAPHORE_H
@@ -328,7 +286,7 @@ typedef QueueHandle_t SemaphoreHandle_t;
  * \defgroup xSemaphoreTake xSemaphoreTake
  * \ingroup Semaphores
  */
-#define xSemaphoreTake( xSemaphore, xBlockTime )		xQueueGenericReceive( ( QueueHandle_t ) ( xSemaphore ), NULL, ( xBlockTime ), pdFALSE )
+#define xSemaphoreTake( xSemaphore, xBlockTime )		xQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) )
 
 /**
  * semphr. h
@@ -392,23 +350,23 @@ typedef QueueHandle_t SemaphoreHandle_t;
 
             // ...
             // For some reason due to the nature of the code further calls to
-			// xSemaphoreTakeRecursive() are made on the same mutex.  In real
-			// code these would not be just sequential calls as this would make
-			// no sense.  Instead the calls are likely to be buried inside
-			// a more complex call structure.
+            // xSemaphoreTakeRecursive() are made on the same mutex.  In real
+            // code these would not be just sequential calls as this would make
+            // no sense.  Instead the calls are likely to be buried inside
+            // a more complex call structure.
             xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
             xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
 
             // The mutex has now been 'taken' three times, so will not be
-			// available to another task until it has also been given back
-			// three times.  Again it is unlikely that real code would have
-			// these calls sequentially, but instead buried in a more complex
-			// call structure.  This is just for illustrative purposes.
+            // available to another task until it has also been given back
+            // three times.  Again it is unlikely that real code would have
+            // these calls sequentially, but instead buried in a more complex
+            // call structure.  This is just for illustrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+            xSemaphoreGiveRecursive( xMutex );
             xSemaphoreGiveRecursive( xMutex );
-			xSemaphoreGiveRecursive( xMutex );
-			xSemaphoreGiveRecursive( xMutex );
 
-			// Now the mutex can be taken by other tasks.
+            // Now the mutex can be taken by other tasks.
         }
         else
         {
@@ -1154,6 +1112,17 @@ typedef QueueHandle_t SemaphoreHandle_t;
  */
 #define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) )
 
+/**
+ * semphr.h
+ * 
TaskHandle_t xSemaphoreGetMutexHolderFromISR( SemaphoreHandle_t xMutex );

+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ */
+#define xSemaphoreGetMutexHolderFromISR( xSemaphore ) xQueueGetMutexHolderFromISR( ( xSemaphore ) )
+
 /**
  * semphr.h
  * 
UBaseType_t uxSemaphoreGetCount( SemaphoreHandle_t xSemaphore );

diff --git a/os/freertos/include/stack_macros.h b/os/freertos/include/stack_macros.h
new file mode 100644
index 000000000..673ef6d8c
--- /dev/null
+++ b/os/freertos/include/stack_macros.h
@@ -0,0 +1,129 @@
+/*
+ * FreeRTOS Kernel V10.1.1
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef STACK_MACROS_H
+#define STACK_MACROS_H
+
+/*
+ * Call the stack overflow hook function if the stack of the task being swapped
+ * out is currently overflowed, or looks like it might have overflowed in the
+ * past.
+ *
+ * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
+ * the current stack state only - comparing the current top of stack value to
+ * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
+ * will also cause the last few stack bytes to be checked to ensure the value
+ * to which the bytes were set when the task was created have not been
+ * overwritten.  Note this second test does not guarantee that an overflowed
+ * stack will always be recognised.
+ */
+
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack )										\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+																										\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack )									\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;							\
+		const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;											\
+																										\
+		if( ( pulStack[ 0 ] != ulCheckValue ) ||														\
+			( pulStack[ 1 ] != ulCheckValue ) ||														\
+			( pulStack[ 2 ] != ulCheckValue ) ||														\
+			( pulStack[ 3 ] != ulCheckValue ) )															\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																								\
+	{																																	\
+	int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;																		\
+	static const uint8_t ucExpectedStackBytes[] = {	tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };	\
+																																		\
+																																		\
+		pcEndOfStack -= sizeof( ucExpectedStackBytes );																					\
+																																		\
+		/* Has the extremity of the task stack ever been written over? */																\
+		if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )					\
+		{																																\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );									\
+		}																																\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+/* Remove stack overflow macro if not being used. */
+#ifndef taskCHECK_FOR_STACK_OVERFLOW
+	#define taskCHECK_FOR_STACK_OVERFLOW()
+#endif
+
+
+
+#endif /* STACK_MACROS_H */
+
diff --git a/os/freertos/include/stream_buffer.h b/os/freertos/include/stream_buffer.h
new file mode 100644
index 000000000..6619fe061
--- /dev/null
+++ b/os/freertos/include/stream_buffer.h
@@ -0,0 +1,855 @@
+/*
+ * FreeRTOS Kernel V10.1.1
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Stream buffers are used to send a continuous stream of data from one task or
+ * interrupt to another.  Their implementation is light weight, making them
+ * particularly suited for interrupt to task and core to core communication
+ * scenarios.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferRead()) inside a critical section section and set the
+ * receive block time to 0.
+ *
+ */
+
+#ifndef STREAM_BUFFER_H
+#define STREAM_BUFFER_H
+
+#if defined( __cplusplus )
+extern "C" {
+#endif
+
+/**
+ * Type by which stream buffers are referenced.  For example, a call to
+ * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can
+ * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(),
+ * etc.
+ */
+struct StreamBufferDef_t;
+typedef struct StreamBufferDef_t * StreamBufferHandle_t;
+
+
+/**
+ * message_buffer.h
+ *
+
+StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );
+

+ *
+ * Creates a new stream buffer using dynamically allocated memory.  See
+ * xStreamBufferCreateStatic() for a version that uses statically allocated
+ * memory (memory that is allocated at compile time).
+ *
+ * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
+ * FreeRTOSConfig.h for xStreamBufferCreate() to be available.
+ *
+ * @param xBufferSizeBytes The total number of bytes the stream buffer will be
+ * able to hold at any one time.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * buffer before a task that is blocked on the stream buffer to wait for data is
+ * moved out of the blocked state.  For example, if a task is blocked on a read
+ * of an empty stream buffer that has a trigger level of 1 then the task will be
+ * unblocked when a single byte is written to the buffer or the task's block
+ * time expires.  As another example, if a task is blocked on a read of an empty
+ * stream buffer that has a trigger level of 10 then the task will not be
+ * unblocked until the stream buffer contains at least 10 bytes or the task's
+ * block time expires.  If a reading task's block time expires before the
+ * trigger level is reached then the task will still receive however many bytes
+ * are actually available.  Setting a trigger level of 0 will result in a
+ * trigger level of 1 being used.  It is not valid to specify a trigger level
+ * that is greater than the buffer size.
+ *
+ * @return If NULL is returned, then the stream buffer cannot be created
+ * because there is insufficient heap memory available for FreeRTOS to allocate
+ * the stream buffer data structures and storage area.  A non-NULL value being
+ * returned indicates that the stream buffer has been created successfully -
+ * the returned value should be stored as the handle to the created stream
+ * buffer.
+ *
+ * Example use:
+
+
+void vAFunction( void )
+{
+StreamBufferHandle_t xStreamBuffer;
+const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;
+
+    // Create a stream buffer that can hold 100 bytes.  The memory used to hold
+    // both the stream buffer structure and the data in the stream buffer is
+    // allocated dynamically.
+    xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
+
+    if( xStreamBuffer == NULL )
+    {
+        // There was not enough heap memory space available to create the
+        // stream buffer.
+    }
+    else
+    {
+        // The stream buffer was created successfully and can now be used.
+    }
+}
+

+ * \defgroup xStreamBufferCreate xStreamBufferCreate
+ * \ingroup StreamBufferManagement
+ */
+#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE )
+
+/**
+ * stream_buffer.h
+ *
+
+StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,
+                                                size_t xTriggerLevelBytes,
+                                                uint8_t *pucStreamBufferStorageArea,
+                                                StaticStreamBuffer_t *pxStaticStreamBuffer );
+

+ * Creates a new stream buffer using statically allocated memory.  See
+ * xStreamBufferCreate() for a version that uses dynamically allocated memory.
+ *
+ * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for
+ * xStreamBufferCreateStatic() to be available.
+ *
+ * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
+ * pucStreamBufferStorageArea parameter.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * buffer before a task that is blocked on the stream buffer to wait for data is
+ * moved out of the blocked state.  For example, if a task is blocked on a read
+ * of an empty stream buffer that has a trigger level of 1 then the task will be
+ * unblocked when a single byte is written to the buffer or the task's block
+ * time expires.  As another example, if a task is blocked on a read of an empty
+ * stream buffer that has a trigger level of 10 then the task will not be
+ * unblocked until the stream buffer contains at least 10 bytes or the task's
+ * block time expires.  If a reading task's block time expires before the
+ * trigger level is reached then the task will still receive however many bytes
+ * are actually available.  Setting a trigger level of 0 will result in a
+ * trigger level of 1 being used.  It is not valid to specify a trigger level
+ * that is greater than the buffer size.
+ *
+ * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at
+ * least xBufferSizeBytes + 1 big.  This is the array to which streams are
+ * copied when they are written to the stream buffer.
+ *
+ * @param pxStaticStreamBuffer Must point to a variable of type
+ * StaticStreamBuffer_t, which will be used to hold the stream buffer's data
+ * structure.
+ *
+ * @return If the stream buffer is created successfully then a handle to the
+ * created stream buffer is returned. If either pucStreamBufferStorageArea or
+ * pxStaticstreamBuffer are NULL then NULL is returned.
+ *
+ * Example use:
+
+
+// Used to dimension the array used to hold the streams.  The available space
+// will actually be one less than this, so 999.
+#define STORAGE_SIZE_BYTES 1000
+
+// Defines the memory that will actually hold the streams within the stream
+// buffer.
+static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+
+// The variable used to hold the stream buffer structure.
+StaticStreamBuffer_t xStreamBufferStruct;
+
+void MyFunction( void )
+{
+StreamBufferHandle_t xStreamBuffer;
+const size_t xTriggerLevel = 1;
+
+    xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucBufferStorage ),
+                                               xTriggerLevel,
+                                               ucBufferStorage,
+                                               &xStreamBufferStruct );
+
+    // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer
+    // parameters were NULL, xStreamBuffer will not be NULL, and can be used to
+    // reference the created stream buffer in other stream buffer API calls.
+
+    // Other code that uses the stream buffer can go here.
+}
+
+

+ * \defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic
+ * \ingroup StreamBufferManagement
+ */
+#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE, pucStreamBufferStorageArea, pxStaticStreamBuffer )
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                          const void *pvTxData,
+                          size_t xDataLengthBytes,
+                          TickType_t xTicksToWait );
+

+ *
+ * Sends bytes to a stream buffer.  The bytes are copied into the stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
+ * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which a stream is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the buffer that holds the bytes to be copied
+ * into the stream buffer.
+ *
+ * @param xDataLengthBytes   The maximum number of bytes to copy from pvTxData
+ * into the stream buffer.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for enough space to become available in the stream
+ * buffer, should the stream buffer contain too little space to hold the
+ * another xDataLengthBytes bytes.  The block time is specified in tick periods,
+ * so the absolute time it represents is dependent on the tick frequency.  The
+ * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
+ * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
+ * cause the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  If a task times out
+ * before it can write all xDataLengthBytes into the buffer it will still write
+ * as many bytes as possible.  A task does not use any CPU time when it is in
+ * the blocked state.
+ *
+ * @return The number of bytes written to the stream buffer.  If a task times
+ * out before it can write all xDataLengthBytes into the buffer it will still
+ * write as many bytes as possible.
+ *
+ * Example use:
+
+void vAFunction( StreamBufferHandle_t xStreamBuffer )
+{
+size_t xBytesSent;
+uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+char *pcStringToSend = "String to send";
+const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+
+    // Send an array to the stream buffer, blocking for a maximum of 100ms to
+    // wait for enough space to be available in the stream buffer.
+    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+
+    if( xBytesSent != sizeof( ucArrayToSend ) )
+    {
+        // The call to xStreamBufferSend() times out before there was enough
+        // space in the buffer for the data to be written, but it did
+        // successfully write xBytesSent bytes.
+    }
+
+    // Send the string to the stream buffer.  Return immediately if there is not
+    // enough space in the buffer.
+    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The entire string could not be added to the stream buffer because
+        // there was not enough free space in the buffer, but xBytesSent bytes
+        // were sent.  Could try again to send the remaining bytes.
+    }
+}
+

+ * \defgroup xStreamBufferSend xStreamBufferSend
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+						  const void *pvTxData,
+						  size_t xDataLengthBytes,
+						  TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+                                 const void *pvTxData,
+                                 size_t xDataLengthBytes,
+                                 BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * Interrupt safe version of the API function that sends a stream of bytes to
+ * the stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
+ * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which a stream is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the data that is to be copied into the stream
+ * buffer.
+ *
+ * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData
+ * into the stream buffer.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
+ * have a task blocked on it waiting for data.  Calling
+ * xStreamBufferSendFromISR() can make data available, and so cause a task that
+ * was waiting for data to leave the Blocked state.  If calling
+ * xStreamBufferSendFromISR() causes a task to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently executing task (the
+ * task that was interrupted), then, internally, xStreamBufferSendFromISR()
+ * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
+ * xStreamBufferSendFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  This will
+ * ensure that the interrupt returns directly to the highest priority Ready
+ * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
+ * is passed into the function.  See the example code below for an example.
+ *
+ * @return The number of bytes actually written to the stream buffer, which will
+ * be less than xDataLengthBytes if the stream buffer didn't have enough free
+ * space for all the bytes to be written.
+ *
+ * Example use:
+
+// A stream buffer that has already been created.
+StreamBufferHandle_t xStreamBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+size_t xBytesSent;
+char *pcStringToSend = "String to send";
+BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+
+    // Attempt to send the string to the stream buffer.
+    xBytesSent = xStreamBufferSendFromISR( xStreamBuffer,
+                                           ( void * ) pcStringToSend,
+                                           strlen( pcStringToSend ),
+                                           &xHigherPriorityTaskWoken );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // There was not enough free space in the stream buffer for the entire
+        // string to be written, ut xBytesSent bytes were written.
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xStreamBufferSendFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+

+ * \defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+								 const void *pvTxData,
+								 size_t xDataLengthBytes,
+								 BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                             void *pvRxData,
+                             size_t xBufferLengthBytes,
+                             TickType_t xTicksToWait );
+

+ *
+ * Receives bytes from a stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferReceive() to read from a stream buffer from a task.  Use
+ * xStreamBufferReceiveFromISR() to read from a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which bytes are to
+ * be received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received bytes will be
+ * copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the
+ * pvRxData parameter.  This sets the maximum number of bytes to receive in one
+ * call.  xStreamBufferReceive will return as many bytes as possible up to a
+ * maximum set by xBufferLengthBytes.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for data to become available if the stream buffer is
+ * empty.  xStreamBufferReceive() will return immediately if xTicksToWait is
+ * zero.  The block time is specified in tick periods, so the absolute time it
+ * represents is dependent on the tick frequency.  The macro pdMS_TO_TICKS() can
+ * be used to convert a time specified in milliseconds into a time specified in
+ * ticks.  Setting xTicksToWait to portMAX_DELAY will cause the task to wait
+ * indefinitely (without timing out), provided INCLUDE_vTaskSuspend is set to 1
+ * in FreeRTOSConfig.h.  A task does not use any CPU time when it is in the
+ * Blocked state.
+ *
+ * @return The number of bytes actually read from the stream buffer, which will
+ * be less than xBufferLengthBytes if the call to xStreamBufferReceive() timed
+ * out before xBufferLengthBytes were available.
+ *
+ * Example use:
+
+void vAFunction( StreamBuffer_t xStreamBuffer )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+
+    // Receive up to another sizeof( ucRxData ) bytes from the stream buffer.
+    // Wait in the Blocked state (so not using any CPU processing time) for a
+    // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be
+    // available.
+    xReceivedBytes = xStreamBufferReceive( xStreamBuffer,
+                                           ( void * ) ucRxData,
+                                           sizeof( ucRxData ),
+                                           xBlockTime );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains another xRecievedBytes bytes of data, which can
+        // be processed here....
+    }
+}
+

+ * \defgroup xStreamBufferReceive xStreamBufferReceive
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+							 void *pvRxData,
+							 size_t xBufferLengthBytes,
+							 TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+                                    void *pvRxData,
+                                    size_t xBufferLengthBytes,
+                                    BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * An interrupt safe version of the API function that receives bytes from a
+ * stream buffer.
+ *
+ * Use xStreamBufferReceive() to read bytes from a stream buffer from a task.
+ * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which a stream
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received bytes are
+ * copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the
+ * pvRxData parameter.  This sets the maximum number of bytes to receive in one
+ * call.  xStreamBufferReceive will return as many bytes as possible up to a
+ * maximum set by xBufferLengthBytes.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
+ * have a task blocked on it waiting for space to become available.  Calling
+ * xStreamBufferReceiveFromISR() can make space available, and so cause a task
+ * that is waiting for space to leave the Blocked state.  If calling
+ * xStreamBufferReceiveFromISR() causes a task to leave the Blocked state, and
+ * the unblocked task has a priority higher than the currently executing task
+ * (the task that was interrupted), then, internally,
+ * xStreamBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
+ * If xStreamBufferReceiveFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  That will
+ * ensure the interrupt returns directly to the highest priority Ready state
+ * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
+ * passed into the function.  See the code example below for an example.
+ *
+ * @return The number of bytes read from the stream buffer, if any.
+ *
+ * Example use:
+
+// A stream buffer that has already been created.
+StreamBuffer_t xStreamBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+
+    // Receive the next stream from the stream buffer.
+    xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer,
+                                                  ( void * ) ucRxData,
+                                                  sizeof( ucRxData ),
+                                                  &xHigherPriorityTaskWoken );
+
+    if( xReceivedBytes > 0 )
+    {
+        // ucRxData contains xReceivedBytes read from the stream buffer.
+        // Process the stream here....
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xStreamBufferReceiveFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+

+ * \defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+									void *pvRxData,
+									size_t xBufferLengthBytes,
+									BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Deletes a stream buffer that was previously created using a call to
+ * xStreamBufferCreate() or xStreamBufferCreateStatic().  If the stream
+ * buffer was created using dynamic memory (that is, by xStreamBufferCreate()),
+ * then the allocated memory is freed.
+ *
+ * A stream buffer handle must not be used after the stream buffer has been
+ * deleted.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to be deleted.
+ *
+ * \defgroup vStreamBufferDelete vStreamBufferDelete
+ * \ingroup StreamBufferManagement
+ */
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Queries a stream buffer to see if it is full.  A stream buffer is full if it
+ * does not have any free space, and therefore cannot accept any more data.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return If the stream buffer is full then pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferIsFull xStreamBufferIsFull
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Queries a stream buffer to see if it is empty.  A stream buffer is empty if
+ * it does not contain any data.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return If the stream buffer is empty then pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferIsEmpty xStreamBufferIsEmpty
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Resets a stream buffer to its initial, empty, state.  Any data that was in
+ * the stream buffer is discarded.  A stream buffer can only be reset if there
+ * are no tasks blocked waiting to either send to or receive from the stream
+ * buffer.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being reset.
+ *
+ * @return If the stream buffer is reset then pdPASS is returned.  If there was
+ * a task blocked waiting to send to or read from the stream buffer then the
+ * stream buffer is not reset and pdFAIL is returned.
+ *
+ * \defgroup xStreamBufferReset xStreamBufferReset
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Queries a stream buffer to see how much free space it contains, which is
+ * equal to the amount of data that can be sent to the stream buffer before it
+ * is full.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return The number of bytes that can be written to the stream buffer before
+ * the stream buffer would be full.
+ *
+ * \defgroup xStreamBufferSpacesAvailable xStreamBufferSpacesAvailable
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Queries a stream buffer to see how much data it contains, which is equal to
+ * the number of bytes that can be read from the stream buffer before the stream
+ * buffer would be empty.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return The number of bytes that can be read from the stream buffer before
+ * the stream buffer would be empty.
+ *
+ * \defgroup xStreamBufferBytesAvailable xStreamBufferBytesAvailable
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
+

+ *
+ * A stream buffer's trigger level is the number of bytes that must be in the
+ * stream buffer before a task that is blocked on the stream buffer to
+ * wait for data is moved out of the blocked state.  For example, if a task is
+ * blocked on a read of an empty stream buffer that has a trigger level of 1
+ * then the task will be unblocked when a single byte is written to the buffer
+ * or the task's block time expires.  As another example, if a task is blocked
+ * on a read of an empty stream buffer that has a trigger level of 10 then the
+ * task will not be unblocked until the stream buffer contains at least 10 bytes
+ * or the task's block time expires.  If a reading task's block time expires
+ * before the trigger level is reached then the task will still receive however
+ * many bytes are actually available.  Setting a trigger level of 0 will result
+ * in a trigger level of 1 being used.  It is not valid to specify a trigger
+ * level that is greater than the buffer size.
+ *
+ * A trigger level is set when the stream buffer is created, and can be modified
+ * using xStreamBufferSetTriggerLevel().
+ *
+ * @param xStreamBuffer The handle of the stream buffer being updated.
+ *
+ * @param xTriggerLevel The new trigger level for the stream buffer.
+ *
+ * @return If xTriggerLevel was less than or equal to the stream buffer's length
+ * then the trigger level will be updated and pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferSetTriggerLevel xStreamBufferSetTriggerLevel
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * For advanced users only.
+ *
+ * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is sent to a message buffer or stream buffer.  If there was a task that
+ * was blocked on the message or stream buffer waiting for data to arrive then
+ * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
+ * from the Blocked state.  xStreamBufferSendCompletedFromISR() does the same
+ * thing.  It is provided to enable application writers to implement their own
+ * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which data was
+ * written.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xStreamBufferSendCompletedFromISR().  If calling
+ * xStreamBufferSendCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferSendCompletedFromISR xStreamBufferSendCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * For advanced users only.
+ *
+ * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is read out of a message buffer or stream buffer.  If there was a task
+ * that was blocked on the message or stream buffer waiting for data to arrive
+ * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
+ * remove it from the Blocked state.  xStreamBufferReceiveCompletedFromISR()
+ * does the same thing.  It is provided to enable application writers to
+ * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
+ * ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which data was
+ * read.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xStreamBufferReceiveCompletedFromISR().  If calling
+ * xStreamBufferReceiveCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferReceiveCompletedFromISR xStreamBufferReceiveCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/* Functions below here are not part of the public API. */
+StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
+												 size_t xTriggerLevelBytes,
+												 BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION;
+
+StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+													   size_t xTriggerLevelBytes,
+													   BaseType_t xIsMessageBuffer,
+													   uint8_t * const pucStreamBufferStorageArea,
+													   StaticStreamBuffer_t * const pxStaticStreamBuffer ) PRIVILEGED_FUNCTION;
+
+size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION;
+	UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+	uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+#endif
+
+#if defined( __cplusplus )
+}
+#endif
+
+#endif	/* !defined( STREAM_BUFFER_H ) */
diff --git a/os/freertos/include/task.h b/os/freertos/include/task.h
index d0643c09e..ef0d64381 100644
--- a/os/freertos/include/task.h
+++ b/os/freertos/include/task.h
@@ -1,71 +1,29 @@
 /*
-    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
-
-    ***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-    ***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-    the FAQ page "My application does not run, what could be wrong?".  Have you
-    defined configASSERT()?
-
-    http://www.FreeRTOS.org/support - In return for receiving this top quality
-    embedded software for free we request you assist our global community by
-    participating in the support forum.
-
-    http://www.FreeRTOS.org/training - Investing in training allows your team to
-    be as productive as possible as early as possible.  Now you can receive
-    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-    Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
+ * FreeRTOS Kernel V10.1.1
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
 
 
 #ifndef INC_TASK_H
@@ -85,10 +43,10 @@ extern "C" {
  * MACROS AND DEFINITIONS
  *----------------------------------------------------------*/
 
-#define tskKERNEL_VERSION_NUMBER "V9.0.0"
-#define tskKERNEL_VERSION_MAJOR 9
-#define tskKERNEL_VERSION_MINOR 0
-#define tskKERNEL_VERSION_BUILD 0
+#define tskKERNEL_VERSION_NUMBER "V10.1.1"
+#define tskKERNEL_VERSION_MAJOR 10
+#define tskKERNEL_VERSION_MINOR 1
+#define tskKERNEL_VERSION_BUILD 1
 
 /**
  * task. h
@@ -100,7 +58,8 @@ extern "C" {
  * \defgroup TaskHandle_t TaskHandle_t
  * \ingroup Tasks
  */
-typedef void * TaskHandle_t;
+struct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+typedef struct tskTaskControlBlock* TaskHandle_t;
 
 /*
  * Defines the prototype to which the application task hook function must
@@ -116,7 +75,7 @@ typedef enum
 	eBlocked,		/* The task being queried is in the Blocked state. */
 	eSuspended,		/* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */
 	eDeleted,		/* The task being queried has been deleted, but its TCB has not yet been freed. */
-	eInvalid			/* Used as an 'invalid state' value. */
+	eInvalid		/* Used as an 'invalid state' value. */
 } eTaskState;
 
 /* Actions that can be performed when vTaskNotify() is called. */
@@ -160,6 +119,9 @@ typedef struct xTASK_PARAMETERS
 	UBaseType_t uxPriority;
 	StackType_t *puxStackBuffer;
 	MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ];
+	#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+		StaticTask_t * const pxTaskBuffer;
+	#endif
 } TaskParameters_t;
 
 /* Used with the uxTaskGetSystemState() function to return the state of each task
@@ -174,7 +136,7 @@ typedef struct xTASK_STATUS
 	UBaseType_t uxBasePriority;		/* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex.  Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */
 	uint32_t ulRunTimeCounter;		/* The total run time allocated to the task so far, as defined by the run time stats clock.  See http://www.freertos.org/rtos-run-time-stats.html.  Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */
 	StackType_t *pxStackBase;		/* Points to the lowest address of the task's stack area. */
-	uint16_t usStackHighWaterMark;	/* The minimum amount of stack space that has remained for the task since the task was created.  The closer this value is to zero the closer the task has come to overflowing its stack. */
+	configSTACK_DEPTH_TYPE usStackHighWaterMark;	/* The minimum amount of stack space that has remained for the task since the task was created.  The closer this value is to zero the closer the task has come to overflowing its stack. */
 } TaskStatus_t;
 
 /* Possible return values for eTaskConfirmSleepModeStatus(). */
@@ -269,7 +231,7 @@ is used in assert() statements. */
  BaseType_t xTaskCreate(
 							  TaskFunction_t pvTaskCode,
 							  const char * const pcName,
-							  uint16_t usStackDepth,
+							  configSTACK_DEPTH_TYPE usStackDepth,
 							  void *pvParameters,
 							  UBaseType_t uxPriority,
 							  TaskHandle_t *pvCreatedTask
@@ -358,11 +320,11 @@ is used in assert() statements. */
  */
 #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
 	BaseType_t xTaskCreate(	TaskFunction_t pxTaskCode,
-							const char * const pcName,
-							const uint16_t usStackDepth,
+							const char * const pcName,	/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+							const configSTACK_DEPTH_TYPE usStackDepth,
 							void * const pvParameters,
 							UBaseType_t uxPriority,
-							TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+							TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
 #endif
 
 /**
@@ -474,12 +436,12 @@ is used in assert() statements. */
  */
 #if( configSUPPORT_STATIC_ALLOCATION == 1 )
 	TaskHandle_t xTaskCreateStatic(	TaskFunction_t pxTaskCode,
-									const char * const pcName,
+									const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
 									const uint32_t ulStackDepth,
 									void * const pvParameters,
 									UBaseType_t uxPriority,
 									StackType_t * const puxStackBuffer,
-									StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;
 #endif /* configSUPPORT_STATIC_ALLOCATION */
 
 /**
@@ -487,6 +449,8 @@ is used in assert() statements. */
  *
  BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );

  *
+ * Only available when configSUPPORT_DYNAMIC_ALLOCATION is set to 1.
+ *
  * xTaskCreateRestricted() should only be used in systems that include an MPU
  * implementation.
  *
@@ -494,6 +458,9 @@ is used in assert() statements. */
  * The function parameters define the memory regions and associated access
  * permissions allocated to the task.
  *
+ * See xTaskCreateRestrictedStatic() for a version that does not use any
+ * dynamic memory allocation.
+ *
  * @param pxTaskDefinition Pointer to a structure that contains a member
  * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
  * documentation) plus an optional stack buffer and the memory region
@@ -553,6 +520,94 @@ TaskHandle_t xHandle;
 	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
 #endif
 
+/**
+ * task. h
+ *
+ BaseType_t xTaskCreateRestrictedStatic( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );

+ *
+ * Only available when configSUPPORT_STATIC_ALLOCATION is set to 1.
+ *
+ * xTaskCreateRestrictedStatic() should only be used in systems that include an
+ * MPU implementation.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreateRestricted() then the stack is provided by the application writer,
+ * and the memory used to hold the task's data structure is automatically
+ * dynamically allocated inside the xTaskCreateRestricted() function.  If a task
+ * is created using xTaskCreateRestrictedStatic() then the application writer
+ * must provide the memory used to hold the task's data structures too.
+ * xTaskCreateRestrictedStatic() therefore allows a memory protected task to be
+ * created without using any dynamic memory allocation.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions.  If configSUPPORT_STATIC_ALLOCATION is set to 1 the structure
+ * contains an additional member, which is used to point to a variable of type
+ * StaticTask_t - which is then used to hold the task's data structure.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   
+// Create an TaskParameters_t structure that defines the task to be created.
+// The StaticTask_t variable is only included in the structure when
+// configSUPPORT_STATIC_ALLOCATION is set to 1.  The PRIVILEGED_DATA macro can
+// be used to force the variable into the RTOS kernel's privileged data area.
+static PRIVILEGED_DATA StaticTask_t xTaskBuffer;
+static const TaskParameters_t xCheckTaskParameters =
+{
+	vATask,		// pvTaskCode - the function that implements the task.
+	"ATask",	// pcName - just a text name for the task to assist debugging.
+	100,		// usStackDepth	- the stack size DEFINED IN WORDS.
+	NULL,		// pvParameters - passed into the task function as the function parameters.
+	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+
+	// xRegions - Allocate up to three separate memory regions for access by
+	// the task, with appropriate access permissions.  Different processors have
+	// different memory alignment requirements - refer to the FreeRTOS documentation
+	// for full information.
+	{
+		// Base address					Length	Parameters
+        { cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
+        { cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
+        { cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
+	}
+
+	&xTaskBuffer; // Holds the task's data structure.
+};
+
+int main( void )
+{
+TaskHandle_t xHandle;
+
+	// Create a task from the const structure defined above.  The task handle
+	// is requested (the second parameter is not NULL) but in this case just for
+	// demonstration purposes as its not actually used.
+	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+
+	// Start the scheduler.
+	vTaskStartScheduler();
+
+	// Will only get here if there was insufficient memory to create the idle
+	// and/or timer task.
+	for( ;; );
+}
+   

+ * \defgroup xTaskCreateRestrictedStatic xTaskCreateRestrictedStatic
+ * \ingroup Tasks
+ */
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+	BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
 /**
  * task. h
  *
@@ -780,7 +835,7 @@ BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
 
 /**
  * task. h
- * 
UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask );

+ * 
UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask );

  *
  * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available.
  * See the configuration section for more information.
@@ -823,15 +878,15 @@ BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
  * \defgroup uxTaskPriorityGet uxTaskPriorityGet
  * \ingroup TaskCtrl
  */
-UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
 
 /**
  * task. h
- * 
UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask );

+ * 
UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask );

  *
  * A version of uxTaskPriorityGet() that can be used from an ISR.
  */
-UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
 
 /**
  * task. h
@@ -2141,14 +2196,14 @@ void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTi
  * Removes a task from both the specified event list and the list of blocked
  * tasks, and places it on a ready queue.
  *
- * xTaskRemoveFromEventList()/xTaskRemoveFromUnorderedEventList() will be called
+ * xTaskRemoveFromEventList()/vTaskRemoveFromUnorderedEventList() will be called
  * if either an event occurs to unblock a task, or the block timeout period
  * expires.
  *
  * xTaskRemoveFromEventList() is used when the event list is in task priority
  * order.  It removes the list item from the head of the event list as that will
  * have the highest priority owning task of all the tasks on the event list.
- * xTaskRemoveFromUnorderedEventList() is used when the event list is not
+ * vTaskRemoveFromUnorderedEventList() is used when the event list is not
  * ordered and the event list items hold something other than the owning tasks
  * priority.  In this case the event list item value is updated to the value
  * passed in the xItemValue parameter.
@@ -2157,7 +2212,7 @@ void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTi
  * making the call, otherwise pdFALSE.
  */
 BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION;
-BaseType_t xTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue ) PRIVILEGED_FUNCTION;
+void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue ) PRIVILEGED_FUNCTION;
 
 /*
  * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
@@ -2207,7 +2262,7 @@ BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;
  * Raises the priority of the mutex holder to that of the calling task should
  * the mutex holder have a priority less than the calling task.
  */
-void vTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
 
 /*
  * Set the priority of a task back to its proper priority in the case that it
@@ -2215,6 +2270,16 @@ void vTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTIO
  */
 BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
 
+/*
+ * If a higher priority task attempting to obtain a mutex caused a lower
+ * priority task to inherit the higher priority task's priority - but the higher
+ * priority task then timed out without obtaining the mutex, then the lower
+ * priority task will disinherit the priority again - but only down as far as
+ * the highest priority task that is still waiting for the mutex (if there were
+ * more than one task waiting for the mutex).
+ */
+void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) PRIVILEGED_FUNCTION;
+
 /*
  * Get the uxTCBNumber assigned to the task referenced by the xTask parameter.
  */
@@ -2256,7 +2321,14 @@ eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;
  * For internal use only.  Increment the mutex held count when a mutex is
  * taken and return the handle of the task that has taken the mutex.
  */
-void *pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION;
+TaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Same as vTaskSetTimeOutState(), but without a critial
+ * section.
+ */
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
 
 #ifdef __cplusplus
 }
diff --git a/os/freertos/include/timers.h b/os/freertos/include/timers.h
index 798c955bb..ae8bc711d 100644
--- a/os/freertos/include/timers.h
+++ b/os/freertos/include/timers.h
@@ -1,71 +1,29 @@
 /*
-    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
-
-    ***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-    ***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-    the FAQ page "My application does not run, what could be wrong?".  Have you
-    defined configASSERT()?
-
-    http://www.FreeRTOS.org/support - In return for receiving this top quality
-    embedded software for free we request you assist our global community by
-    participating in the support forum.
-
-    http://www.FreeRTOS.org/training - Investing in training allows your team to
-    be as productive as possible as early as possible.  Now you can receive
-    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-    Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
+ * FreeRTOS Kernel V10.1.1
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
 
 
 #ifndef TIMERS_H
@@ -75,10 +33,10 @@
 	#error "include FreeRTOS.h must appear in source files before include timers.h"
 #endif
 
-/*lint -e537 This headers are only multiply included if the application code
+/*lint -save -e537 This headers are only multiply included if the application code
 happens to also be including task.h. */
 #include "task.h"
-/*lint +e537 */
+/*lint -restore */
 
 #ifdef __cplusplus
 extern "C" {
@@ -115,7 +73,8 @@ or interrupt version of the queue send function should be used. */
  * reference the subject timer in calls to other software timer API functions
  * (for example, xTimerStart(), xTimerReset(), etc.).
  */
-typedef void * TimerHandle_t;
+struct tmrTimerControl; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+typedef struct tmrTimerControl * TimerHandle_t;
 
 /*
  * Defines the prototype to which timer callback functions must conform.
@@ -266,11 +225,11 @@ typedef void (*PendedFunction_t)( void *, uint32_t );
  * @endverbatim
  */
 #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	TimerHandle_t xTimerCreate(	const char * const pcTimerName,
+	TimerHandle_t xTimerCreate(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
 								const TickType_t xTimerPeriodInTicks,
 								const UBaseType_t uxAutoReload,
 								void * const pvTimerID,
-								TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+								TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION;
 #endif
 
 /**
@@ -396,12 +355,12 @@ typedef void (*PendedFunction_t)( void *, uint32_t );
  * @endverbatim
  */
 #if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,
+	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
 										const TickType_t xTimerPeriodInTicks,
 										const UBaseType_t uxAutoReload,
 										void * const pvTimerID,
 										TimerCallbackFunction_t pxCallbackFunction,
-										StaticTimer_t *pxTimerBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+										StaticTimer_t *pxTimerBuffer ) PRIVILEGED_FUNCTION;
 #endif /* configSUPPORT_STATIC_ALLOCATION */
 
 /**
@@ -1305,6 +1264,11 @@ TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
 BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;
 BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
 
+#if( configUSE_TRACE_FACILITY == 1 )
+	void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION;
+	UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+#endif
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/os/freertos/list.c b/os/freertos/list.c
index 5e207c160..83e1a3ff6 100644
--- a/os/freertos/list.c
+++ b/os/freertos/list.c
@@ -1,71 +1,29 @@
 /*
-    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
-
-    ***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-    ***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-    the FAQ page "My application does not run, what could be wrong?".  Have you
-    defined configASSERT()?
-
-    http://www.FreeRTOS.org/support - In return for receiving this top quality
-    embedded software for free we request you assist our global community by
-    participating in the support forum.
-
-    http://www.FreeRTOS.org/training - Investing in training allows your team to
-    be as productive as possible as early as possible.  Now you can receive
-    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-    Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
+ * FreeRTOS Kernel V10.1.1
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
 
 
 #include 
@@ -81,7 +39,7 @@ void vListInitialise( List_t * const pxList )
 	/* The list structure contains a list item which is used to mark the
 	end of the list.  To initialise the list the list end is inserted
 	as the only list entry. */
-	pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );			/*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+	pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );			/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
 
 	/* The list end value is the highest possible value in the list to
 	ensure it remains at the end of the list. */
@@ -89,8 +47,8 @@ void vListInitialise( List_t * const pxList )
 
 	/* The list end next and previous pointers point to itself so we know
 	when the list is empty. */
-	pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );	/*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
-	pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+	pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );	/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+	pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
 
 	pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
 
@@ -104,7 +62,7 @@ void vListInitialise( List_t * const pxList )
 void vListInitialiseItem( ListItem_t * const pxItem )
 {
 	/* Make sure the list item is not recorded as being on a list. */
-	pxItem->pvContainer = NULL;
+	pxItem->pxContainer = NULL;
 
 	/* Write known values into the list item if
 	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
@@ -136,7 +94,7 @@ ListItem_t * const pxIndex = pxList->pxIndex;
 	pxIndex->pxPrevious = pxNewListItem;
 
 	/* Remember which list the item is in. */
-	pxNewListItem->pvContainer = ( void * ) pxList;
+	pxNewListItem->pxContainer = pxList;
 
 	( pxList->uxNumberOfItems )++;
 }
@@ -156,7 +114,7 @@ const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
 	/* Insert the new list item into the list, sorted in xItemValue order.
 
 	If the list already contains a list item with the same item value then the
-	new list item should be placed after it.  This ensures that TCB's which are
+	new list item should be placed after it.  This ensures that TCBs which are
 	stored in ready lists (all of which have the same xItemValue value) get a
 	share of the CPU.  However, if the xItemValue is the same as the back marker
 	the iteration loop below will not end.  Therefore the value is checked
@@ -169,18 +127,18 @@ const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
 	{
 		/* *** NOTE ***********************************************************
 		If you find your application is crashing here then likely causes are
-		listed below.  In addition see http://www.freertos.org/FAQHelp.html for
+		listed below.  In addition see https://www.freertos.org/FAQHelp.html for
 		more tips, and ensure configASSERT() is defined!
-		http://www.freertos.org/a00110.html#configASSERT
+		https://www.freertos.org/a00110.html#configASSERT
 
 			1) Stack overflow -
-			   see http://www.freertos.org/Stacks-and-stack-overflow-checking.html
+			   see https://www.freertos.org/Stacks-and-stack-overflow-checking.html
 			2) Incorrect interrupt priority assignment, especially on Cortex-M
 			   parts where numerically high priority values denote low actual
 			   interrupt priorities, which can seem counter intuitive.  See
-			   http://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition
+			   https://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition
 			   of configMAX_SYSCALL_INTERRUPT_PRIORITY on
-			   http://www.freertos.org/a00110.html
+			   https://www.freertos.org/a00110.html
 			3) Calling an API function from within a critical section or when
 			   the scheduler is suspended, or calling an API function that does
 			   not end in "FromISR" from an interrupt.
@@ -189,7 +147,7 @@ const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
 			   before vTaskStartScheduler() has been called?).
 		**********************************************************************/
 
-		for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+		for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
 		{
 			/* There is nothing to do here, just iterating to the wanted
 			insertion position. */
@@ -203,7 +161,7 @@ const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
 
 	/* Remember which list the item is in.  This allows fast removal of the
 	item later. */
-	pxNewListItem->pvContainer = ( void * ) pxList;
+	pxNewListItem->pxContainer = pxList;
 
 	( pxList->uxNumberOfItems )++;
 }
@@ -213,7 +171,7 @@ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
 {
 /* The list item knows which list it is in.  Obtain the list from the list
 item. */
-List_t * const pxList = ( List_t * ) pxItemToRemove->pvContainer;
+List_t * const pxList = pxItemToRemove->pxContainer;
 
 	pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
 	pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
@@ -231,7 +189,7 @@ List_t * const pxList = ( List_t * ) pxItemToRemove->pvContainer;
 		mtCOVERAGE_TEST_MARKER();
 	}
 
-	pxItemToRemove->pvContainer = NULL;
+	pxItemToRemove->pxContainer = NULL;
 	( pxList->uxNumberOfItems )--;
 
 	return pxList->uxNumberOfItems;
diff --git a/os/freertos/portable/MemMang/ReadMe.url b/os/freertos/portable/MemMang/ReadMe.url
new file mode 100644
index 000000000..6c23737db
--- /dev/null
+++ b/os/freertos/portable/MemMang/ReadMe.url
@@ -0,0 +1,5 @@
+[{000214A0-0000-0000-C000-000000000046}]
+Prop3=19,2
+[InternetShortcut]
+URL=http://www.freertos.org/a00111.html
+IDList=
diff --git a/os/freertos/portable/MemMang/heap_1.c b/os/freertos/portable/MemMang/heap_1.c
index 6dfb3cbcb..8df215c76 100644
--- a/os/freertos/portable/MemMang/heap_1.c
+++ b/os/freertos/portable/MemMang/heap_1.c
@@ -1,71 +1,29 @@
 /*
-    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
-
-    ***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-    ***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-    the FAQ page "My application does not run, what could be wrong?".  Have you
-    defined configASSERT()?
-
-    http://www.FreeRTOS.org/support - In return for receiving this top quality
-    embedded software for free we request you assist our global community by
-    participating in the support forum.
-
-    http://www.FreeRTOS.org/training - Investing in training allows your team to
-    be as productive as possible as early as possible.  Now you can receive
-    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-    Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
+ * FreeRTOS Kernel V10.1.1
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
 
 
 /*
@@ -94,7 +52,6 @@ task.h is included from an application file. */
 /* A few bytes might be lost to byte aligning the heap start address. */
 #define configADJUSTED_HEAP_SIZE	( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )
 
-/* Allocate the memory for the heap. */
 /* Allocate the memory for the heap. */
 #if( configAPPLICATION_ALLOCATED_HEAP == 1 )
 	/* The application writer has already defined the array used for the RTOS
@@ -104,6 +61,7 @@ task.h is included from an application file. */
 	static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
 #endif /* configAPPLICATION_ALLOCATED_HEAP */
 
+/* Index into the ucHeap array. */
 static size_t xNextFreeByte = ( size_t ) 0;
 
 /*-----------------------------------------------------------*/
diff --git a/os/freertos/portable/MemMang/heap_2.c b/os/freertos/portable/MemMang/heap_2.c
index bba855409..b48b87da4 100644
--- a/os/freertos/portable/MemMang/heap_2.c
+++ b/os/freertos/portable/MemMang/heap_2.c
@@ -1,71 +1,29 @@
 /*
-    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
-
-    ***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-    ***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-    the FAQ page "My application does not run, what could be wrong?".  Have you
-    defined configASSERT()?
-
-    http://www.FreeRTOS.org/support - In return for receiving this top quality
-    embedded software for free we request you assist our global community by
-    participating in the support forum.
-
-    http://www.FreeRTOS.org/training - Investing in training allows your team to
-    be as productive as possible as early as possible.  Now you can receive
-    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-    Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
+ * FreeRTOS Kernel V10.1.1
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
 
 /*
  * A sample implementation of pvPortMalloc() and vPortFree() that permits
diff --git a/os/freertos/portable/MemMang/heap_3.c b/os/freertos/portable/MemMang/heap_3.c
index f92200188..0bfd1c031 100644
--- a/os/freertos/portable/MemMang/heap_3.c
+++ b/os/freertos/portable/MemMang/heap_3.c
@@ -1,71 +1,29 @@
 /*
-    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
-
-    ***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-    ***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-    the FAQ page "My application does not run, what could be wrong?".  Have you
-    defined configASSERT()?
-
-    http://www.FreeRTOS.org/support - In return for receiving this top quality
-    embedded software for free we request you assist our global community by
-    participating in the support forum.
-
-    http://www.FreeRTOS.org/training - Investing in training allows your team to
-    be as productive as possible as early as possible.  Now you can receive
-    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-    Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
+ * FreeRTOS Kernel V10.1.1
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
 
 
 /*
diff --git a/os/freertos/portable/MemMang/heap_4.c b/os/freertos/portable/MemMang/heap_4.c
index e7c7ade68..ce7abe332 100644
--- a/os/freertos/portable/MemMang/heap_4.c
+++ b/os/freertos/portable/MemMang/heap_4.c
@@ -1,71 +1,29 @@
 /*
-    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
-
-    ***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-    ***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-    the FAQ page "My application does not run, what could be wrong?".  Have you
-    defined configASSERT()?
-
-    http://www.FreeRTOS.org/support - In return for receiving this top quality
-    embedded software for free we request you assist our global community by
-    participating in the support forum.
-
-    http://www.FreeRTOS.org/training - Investing in training allows your team to
-    be as productive as possible as early as possible.  Now you can receive
-    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-    Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
+ * FreeRTOS Kernel V10.1.1
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
 
 /*
  * A sample implementation of pvPortMalloc() and vPortFree() that combines
diff --git a/os/freertos/portable/MemMang/heap_5.c b/os/freertos/portable/MemMang/heap_5.c
index d53e41e84..d150f91d9 100644
--- a/os/freertos/portable/MemMang/heap_5.c
+++ b/os/freertos/portable/MemMang/heap_5.c
@@ -1,71 +1,29 @@
 /*
-    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
-
-    ***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-    ***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-    the FAQ page "My application does not run, what could be wrong?".  Have you
-    defined configASSERT()?
-
-    http://www.FreeRTOS.org/support - In return for receiving this top quality
-    embedded software for free we request you assist our global community by
-    participating in the support forum.
-
-    http://www.FreeRTOS.org/training - Investing in training allows your team to
-    be as productive as possible as early as possible.  Now you can receive
-    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-    Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
+ * FreeRTOS Kernel V10.1.1
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
 
 /*
  * A sample implementation of pvPortMalloc() that allows the heap to be defined
diff --git a/os/freertos/queue.c b/os/freertos/queue.c
index ce623bec2..a0dc6c5ba 100644
--- a/os/freertos/queue.c
+++ b/os/freertos/queue.c
@@ -1,71 +1,29 @@
 /*
-    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
-
-    ***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-    ***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-    the FAQ page "My application does not run, what could be wrong?".  Have you
-    defined configASSERT()?
-
-    http://www.FreeRTOS.org/support - In return for receiving this top quality
-    embedded software for free we request you assist our global community by
-    participating in the support forum.
-
-    http://www.FreeRTOS.org/training - Investing in training allows your team to
-    be as productive as possible as early as possible.  Now you can receive
-    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-    Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
+ * FreeRTOS Kernel V10.1.1
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
 
 #include 
 #include 
@@ -83,11 +41,11 @@ task.h is included from an application file. */
 	#include "croutine.h"
 #endif
 
-/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
-MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
-header files above, but not in this file, in order to generate the correct
-privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
 
 
 /* Constants used with the cRxLock and cTxLock structure members. */
@@ -98,17 +56,26 @@ privileged Vs unprivileged linkage and placement. */
 pcTail members are used as pointers into the queue storage area.  When the
 Queue_t structure is used to represent a mutex pcHead and pcTail pointers are
 not necessary, and the pcHead pointer is set to NULL to indicate that the
-pcTail pointer actually points to the mutex holder (if any).  Map alternative
-names to the pcHead and pcTail structure members to ensure the readability of
-the code is maintained despite this dual use of two structure members.  An
-alternative implementation would be to use a union, but use of a union is
-against the coding standard (although an exception to the standard has been
-permitted where the dual use also significantly changes the type of the
-structure member). */
-#define pxMutexHolder					pcTail
+structure instead holds a pointer to the mutex holder (if any).  Map alternative
+names to the pcHead and structure member to ensure the readability of the code
+is maintained.  The QueuePointers_t and SemaphoreData_t types are used to form
+a union as their usage is mutually exclusive dependent on what the queue is
+being used for. */
 #define uxQueueType						pcHead
 #define queueQUEUE_IS_MUTEX				NULL
 
+typedef struct QueuePointers
+{
+	int8_t *pcTail;					/*< Points to the byte at the end of the queue storage area.  Once more byte is allocated than necessary to store the queue items, this is used as a marker. */
+	int8_t *pcReadFrom;				/*< Points to the last place that a queued item was read from when the structure is used as a queue. */
+} QueuePointers_t;
+
+typedef struct SemaphoreData
+{
+	TaskHandle_t xMutexHolder;		 /*< The handle of the task that holds the mutex. */
+	UBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */
+} SemaphoreData_t;
+
 /* Semaphores do not actually store or copy data, so have an item size of
 zero. */
 #define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 )
@@ -125,18 +92,17 @@ zero. */
 /*
  * Definition of the queue used by the scheduler.
  * Items are queued by copy, not reference.  See the following link for the
- * rationale: http://www.freertos.org/Embedded-RTOS-Queues.html
+ * rationale: https://www.freertos.org/Embedded-RTOS-Queues.html
  */
-typedef struct QueueDefinition
+typedef struct QueueDefinition /* The old naming convention is used to prevent breaking kernel aware debuggers. */
 {
 	int8_t *pcHead;					/*< Points to the beginning of the queue storage area. */
-	int8_t *pcTail;					/*< Points to the byte at the end of the queue storage area.  Once more byte is allocated than necessary to store the queue items, this is used as a marker. */
 	int8_t *pcWriteTo;				/*< Points to the free next place in the storage area. */
 
-	union							/* Use of a union is an exception to the coding standard to ensure two mutually exclusive structure members don't appear simultaneously (wasting RAM). */
+	union
 	{
-		int8_t *pcReadFrom;			/*< Points to the last place that a queued item was read from when the structure is used as a queue. */
-		UBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */
+		QueuePointers_t xQueue;		/*< Data required exclusively when this structure is used as a queue. */
+		SemaphoreData_t xSemaphore; /*< Data required exclusively when this structure is used as a semaphore. */
 	} u;
 
 	List_t xTasksWaitingToSend;		/*< List of tasks that are blocked waiting to post onto this queue.  Stored in priority order. */
@@ -255,6 +221,16 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT
 	static void prvInitialiseMutex( Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
 #endif
 
+#if( configUSE_MUTEXES == 1 )
+	/*
+	 * If a task waiting for a mutex causes the mutex holder to inherit a
+	 * priority, but the waiting task times out, then the holder should
+	 * disinherit the priority - but only down to the highest priority of any
+	 * other tasks that are waiting for the same mutex.  This function returns
+	 * that priority.
+	 */
+	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+#endif
 /*-----------------------------------------------------------*/
 
 /*
@@ -278,16 +254,16 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT
 
 BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
 {
-Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+Queue_t * const pxQueue = xQueue;
 
 	configASSERT( pxQueue );
 
 	taskENTER_CRITICAL();
 	{
-		pxQueue->pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize );
+		pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
 		pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
 		pxQueue->pcWriteTo = pxQueue->pcHead;
-		pxQueue->u.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - ( UBaseType_t ) 1U ) * pxQueue->uxItemSize );
+		pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
 		pxQueue->cRxLock = queueUNLOCKED;
 		pxQueue->cTxLock = queueUNLOCKED;
 
@@ -353,13 +329,14 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 			the real queue and semaphore structures. */
 			volatile size_t xSize = sizeof( StaticQueue_t );
 			configASSERT( xSize == sizeof( Queue_t ) );
+			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
 		}
 		#endif /* configASSERT_DEFINED */
 
 		/* The address of a statically allocated queue was passed in, use it.
 		The address of a statically allocated storage area was also passed in
 		but is already set. */
-		pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+		pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
 
 		if( pxNewQueue != NULL )
 		{
@@ -374,6 +351,11 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 
 			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
 		}
+		else
+		{
+			traceQUEUE_CREATE_FAILED( ucQueueType );
+			mtCOVERAGE_TEST_MARKER();
+		}
 
 		return pxNewQueue;
 	}
@@ -403,13 +385,23 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 			xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 		}
 
-		pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes );
+		/* Allocate the queue and storage area.  Justification for MISRA
+		deviation as follows:  pvPortMalloc() always ensures returned memory
+		blocks are aligned per the requirements of the MCU stack.  In this case
+		pvPortMalloc() must return a pointer that is guaranteed to meet the
+		alignment requirements of the Queue_t structure - which in this case
+		is an int8_t *.  Therefore, whenever the stack alignment requirements
+		are greater than or equal to the pointer to char requirements the cast
+		is safe.  In other cases alignment requirements are not strict (one or
+		two bytes). */
+		pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
 
 		if( pxNewQueue != NULL )
 		{
 			/* Jump past the queue structure to find the location of the queue
 			storage area. */
-			pucQueueStorage = ( ( uint8_t * ) pxNewQueue ) + sizeof( Queue_t );
+			pucQueueStorage = ( uint8_t * ) pxNewQueue;
+			pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
 
 			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
 			{
@@ -422,6 +414,11 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 
 			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
 		}
+		else
+		{
+			traceQUEUE_CREATE_FAILED( ucQueueType );
+			mtCOVERAGE_TEST_MARKER();
+		}
 
 		return pxNewQueue;
 	}
@@ -481,11 +478,11 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT
 			correctly for a generic queue, but this function is creating a
 			mutex.  Overwrite those members that need to be set differently -
 			in particular the information required for priority inheritance. */
-			pxNewQueue->pxMutexHolder = NULL;
+			pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
 			pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
 
 			/* In case this is a recursive mutex. */
-			pxNewQueue->u.uxRecursiveCallCount = 0;
+			pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
 
 			traceCREATE_MUTEX( pxNewQueue );
 
@@ -505,13 +502,13 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT
 
 	QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
 	{
-	Queue_t *pxNewQueue;
+	QueueHandle_t xNewQueue;
 	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
 
-		pxNewQueue = ( Queue_t * ) xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
-		prvInitialiseMutex( pxNewQueue );
+		xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
+		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
 
-		return pxNewQueue;
+		return xNewQueue;
 	}
 
 #endif /* configUSE_MUTEXES */
@@ -521,17 +518,17 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT
 
 	QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )
 	{
-	Queue_t *pxNewQueue;
+	QueueHandle_t xNewQueue;
 	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
 
 		/* Prevent compiler warnings about unused parameters if
 		configUSE_TRACE_FACILITY does not equal 1. */
 		( void ) ucQueueType;
 
-		pxNewQueue = ( Queue_t * ) xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
-		prvInitialiseMutex( pxNewQueue );
+		xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
+		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
 
-		return pxNewQueue;
+		return xNewQueue;
 	}
 
 #endif /* configUSE_MUTEXES */
@@ -539,9 +536,10 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT
 
 #if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
 
-	void* xQueueGetMutexHolder( QueueHandle_t xSemaphore )
+	TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore )
 	{
-	void *pxReturn;
+	TaskHandle_t pxReturn;
+	Queue_t * const pxSemaphore = ( Queue_t * ) xSemaphore;
 
 		/* This function is called by xSemaphoreGetMutexHolder(), and should not
 		be called directly.  Note:  This is a good way of determining if the
@@ -550,9 +548,9 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT
 		following critical section exiting and the function returning. */
 		taskENTER_CRITICAL();
 		{
-			if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )
+			if( pxSemaphore->uxQueueType == queueQUEUE_IS_MUTEX )
 			{
-				pxReturn = ( void * ) ( ( Queue_t * ) xSemaphore )->pxMutexHolder;
+				pxReturn = pxSemaphore->u.xSemaphore.xMutexHolder;
 			}
 			else
 			{
@@ -567,6 +565,32 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT
 #endif
 /*-----------------------------------------------------------*/
 
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+	TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore )
+	{
+	TaskHandle_t pxReturn;
+
+		configASSERT( xSemaphore );
+
+		/* Mutexes cannot be used in interrupt service routines, so the mutex
+		holder should not change in an ISR, and therefore a critical section is
+		not required here. */
+		if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )
+		{
+			pxReturn = ( ( Queue_t * ) xSemaphore )->u.xSemaphore.xMutexHolder;
+		}
+		else
+		{
+			pxReturn = NULL;
+		}
+
+		return pxReturn;
+	} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+
+#endif
+/*-----------------------------------------------------------*/
+
 #if ( configUSE_RECURSIVE_MUTEXES == 1 )
 
 	BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )
@@ -576,25 +600,25 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT
 
 		configASSERT( pxMutex );
 
-		/* If this is the task that holds the mutex then pxMutexHolder will not
+		/* If this is the task that holds the mutex then xMutexHolder will not
 		change outside of this task.  If this task does not hold the mutex then
 		pxMutexHolder can never coincidentally equal the tasks handle, and as
 		this is the only condition we are interested in it does not matter if
 		pxMutexHolder is accessed simultaneously by another task.  Therefore no
 		mutual exclusion is required to test the pxMutexHolder variable. */
-		if( pxMutex->pxMutexHolder == ( void * ) xTaskGetCurrentTaskHandle() ) /*lint !e961 Not a redundant cast as TaskHandle_t is a typedef. */
+		if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
 		{
 			traceGIVE_MUTEX_RECURSIVE( pxMutex );
 
-			/* uxRecursiveCallCount cannot be zero if pxMutexHolder is equal to
+			/* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to
 			the task handle, therefore no underflow check is required.  Also,
 			uxRecursiveCallCount is only modified by the mutex holder, and as
 			there can only be one, no mutual exclusion is required to modify the
 			uxRecursiveCallCount member. */
-			( pxMutex->u.uxRecursiveCallCount )--;
+			( pxMutex->u.xSemaphore.uxRecursiveCallCount )--;
 
 			/* Has the recursive call count unwound to 0? */
-			if( pxMutex->u.uxRecursiveCallCount == ( UBaseType_t ) 0 )
+			if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 )
 			{
 				/* Return the mutex.  This will automatically unblock any other
 				task that might be waiting to access the mutex. */
@@ -636,21 +660,21 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT
 
 		traceTAKE_MUTEX_RECURSIVE( pxMutex );
 
-		if( pxMutex->pxMutexHolder == ( void * ) xTaskGetCurrentTaskHandle() ) /*lint !e961 Cast is not redundant as TaskHandle_t is a typedef. */
+		if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
 		{
-			( pxMutex->u.uxRecursiveCallCount )++;
+			( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
 			xReturn = pdPASS;
 		}
 		else
 		{
-			xReturn = xQueueGenericReceive( pxMutex, NULL, xTicksToWait, pdFALSE );
+			xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait );
 
 			/* pdPASS will only be returned if the mutex was successfully
 			obtained.  The calling task may have entered the Blocked state
 			before reaching here. */
 			if( xReturn != pdFAIL )
 			{
-				( pxMutex->u.uxRecursiveCallCount )++;
+				( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
 			}
 			else
 			{
@@ -724,7 +748,7 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQ
 {
 BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
 TimeOut_t xTimeOut;
-Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+Queue_t * const pxQueue = xQueue;
 
 	configASSERT( pxQueue );
 	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
@@ -736,9 +760,9 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 	#endif
 
 
-	/* This function relaxes the coding standard somewhat to allow return
-	statements within the function itself.  This is done in the interest
-	of execution time efficiency. */
+	/*lint -save -e904 This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
 	for( ;; )
 	{
 		taskENTER_CRITICAL();
@@ -750,13 +774,23 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 			if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
 			{
 				traceQUEUE_SEND( pxQueue );
-				xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
 
 				#if ( configUSE_QUEUE_SETS == 1 )
 				{
+				UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
 					if( pxQueue->pxQueueSetContainer != NULL )
 					{
-						if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) != pdFALSE )
+						if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
+						{
+							/* Do not notify the queue set as an existing item
+							was overwritten in the queue so the number of items
+							in the queue has not changed. */
+							mtCOVERAGE_TEST_MARKER();
+						}
+						else if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) != pdFALSE )
 						{
 							/* The queue is a member of a queue set, and posting
 							to the queue set caused a higher priority task to
@@ -803,6 +837,8 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 				}
 				#else /* configUSE_QUEUE_SETS */
 				{
+					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
 					/* If there was a task waiting for data to arrive on the
 					queue then unblock it now. */
 					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
@@ -855,7 +891,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 				{
 					/* The queue was full and a block time was specified so
 					configure the timeout structure. */
-					vTaskSetTimeOutState( &xTimeOut );
+					vTaskInternalSetTimeOutState( &xTimeOut );
 					xEntryTimeSet = pdTRUE;
 				}
 				else
@@ -882,8 +918,8 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
 
 				/* Unlocking the queue means queue events can effect the
-				event list.  It is possible	that interrupts occurring now
-				remove this task from the event	list again - but as the
+				event list.  It is possible that interrupts occurring now
+				remove this task from the event list again - but as the
 				scheduler is suspended the task will go onto the pending
 				ready last instead of the actual ready list. */
 				prvUnlockQueue( pxQueue );
@@ -914,7 +950,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 			traceQUEUE_SEND_FAILED( pxQueue );
 			return errQUEUE_FULL;
 		}
-	}
+	} /*lint -restore */
 }
 /*-----------------------------------------------------------*/
 
@@ -922,7 +958,7 @@ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pv
 {
 BaseType_t xReturn;
 UBaseType_t uxSavedInterruptStatus;
-Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+Queue_t * const pxQueue = xQueue;
 
 	configASSERT( pxQueue );
 	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
@@ -1073,7 +1109,7 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherP
 {
 BaseType_t xReturn;
 UBaseType_t uxSavedInterruptStatus;
-Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+Queue_t * const pxQueue = xQueue;
 
 	/* Similar to xQueueGenericSendFromISR() but used with semaphores where the
 	item size is 0.  Don't directly wake a task that was blocked on a queue
@@ -1090,7 +1126,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 	/* Normally a mutex would not be given from an interrupt, especially if
 	there is a mutex holder, as priority inheritance makes no sense for an
 	interrupts, only tasks. */
-	configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->pxMutexHolder != NULL ) ) );
+	configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );
 
 	/* RTOS ports that support interrupt nesting have the concept of a maximum
 	system call (or maximum API call) interrupt priority.  Interrupts that are
@@ -1127,7 +1163,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 			can be assumed there is no mutex holder and no need to determine if
 			priority disinheritance is needed.  Simply increase the count of
 			messages (semaphores) available. */
-			pxQueue->uxMessagesWaiting = uxMessagesWaiting + 1;
+			pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
 
 			/* The event list is not altered if the queue is locked.  This will
 			be done when the queue is unlocked later. */
@@ -1234,25 +1270,30 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 }
 /*-----------------------------------------------------------*/
 
-BaseType_t xQueueGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, const BaseType_t xJustPeeking )
+BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
 {
 BaseType_t xEntryTimeSet = pdFALSE;
 TimeOut_t xTimeOut;
-int8_t *pcOriginalReadPosition;
-Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+Queue_t * const pxQueue = xQueue;
 
-	configASSERT( pxQueue );
-	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	/* Check the pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* The buffer into which data is received can only be NULL if the data size
+	is zero (so no data is copied into the buffer. */
+	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* Cannot block if the scheduler is suspended. */
 	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
 	{
 		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
 	}
 	#endif
 
-	/* This function relaxes the coding standard somewhat to allow return
-	statements within the function itself.  This is done in the interest
-	of execution time efficiency. */
 
+	/*lint -save -e904  This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
 	for( ;; )
 	{
 		taskENTER_CRITICAL();
@@ -1263,44 +1304,19 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 			must be the highest priority task wanting to access the queue. */
 			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
 			{
-				/* Remember the read position in case the queue is only being
-				peeked. */
-				pcOriginalReadPosition = pxQueue->u.pcReadFrom;
-
+				/* Data available, remove one item. */
 				prvCopyDataFromQueue( pxQueue, pvBuffer );
+				traceQUEUE_RECEIVE( pxQueue );
+				pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
 
-				if( xJustPeeking == pdFALSE )
+				/* There is now space in the queue, were any tasks waiting to
+				post to the queue?  If so, unblock the highest priority waiting
+				task. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
 				{
-					traceQUEUE_RECEIVE( pxQueue );
-
-					/* Actually removing data, not just peeking. */
-					pxQueue->uxMessagesWaiting = uxMessagesWaiting - 1;
-
-					#if ( configUSE_MUTEXES == 1 )
-					{
-						if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
-						{
-							/* Record the information required to implement
-							priority inheritance should it become necessary. */
-							pxQueue->pxMutexHolder = ( int8_t * ) pvTaskIncrementMutexHeldCount(); /*lint !e961 Cast is not redundant as TaskHandle_t is a typedef. */
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-					#endif /* configUSE_MUTEXES */
-
-					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
 					{
-						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
-						{
-							queueYIELD_IF_USING_PREEMPTION();
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
+						queueYIELD_IF_USING_PREEMPTION();
 					}
 					else
 					{
@@ -1309,31 +1325,170 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 				}
 				else
 				{
-					traceQUEUE_PEEK( pxQueue );
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was empty and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_RECEIVE_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was empty and a block time was specified so
+					configure the timeout structure. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
 
-					/* The data is not being removed, so reset the read
-					pointer. */
-					pxQueue->u.pcReadFrom = pcOriginalReadPosition;
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
 
-					/* The data is being left in the queue, so see if there are
-					any other tasks waiting for the data. */
-					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* The timeout has not expired.  If the queue is still empty place
+			the task on the list of tasks waiting to receive from the queue. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* The queue contains data again.  Loop back to try and read the
+				data. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* Timed out.  If there is no data in the queue exit, otherwise loop
+			back and attempt to read the data. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceQUEUE_RECEIVE_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+
+#if( configUSE_MUTEXES == 1 )
+	BaseType_t xInheritanceOccurred = pdFALSE;
+#endif
+
+	/* Check the queue pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* Check this really is a semaphore, in which case the item size will be
+	0. */
+	configASSERT( pxQueue->uxItemSize == 0 );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904 This function relaxes the coding standard somewhat to allow return
+	statements within the function itself.  This is done in the interest
+	of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			/* Semaphores are queues with an item size of 0, and where the
+			number of messages in the queue is the semaphore's count value. */
+			const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxSemaphoreCount > ( UBaseType_t ) 0 )
+			{
+				traceQUEUE_RECEIVE( pxQueue );
+
+				/* Semaphores are queues with a data size of zero and where the
+				messages waiting is the semaphore's count.  Reduce the count. */
+				pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
 					{
-						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-						{
-							/* The task waiting has a higher priority than this task. */
-							queueYIELD_IF_USING_PREEMPTION();
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
+						/* Record the information required to implement
+						priority inheritance should it become necessary. */
+						pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
 					}
 					else
 					{
 						mtCOVERAGE_TEST_MARKER();
 					}
 				}
+				#endif /* configUSE_MUTEXES */
+
+				/* Check to see if other tasks are blocked waiting to give the
+				semaphore, and if so, unblock the highest priority such task. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
 
 				taskEXIT_CRITICAL();
 				return pdPASS;
@@ -1342,17 +1497,26 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 			{
 				if( xTicksToWait == ( TickType_t ) 0 )
 				{
-					/* The queue was empty and no block time is specified (or
-					the block time has expired) so leave now. */
+					/* For inheritance to have occurred there must have been an
+					initial timeout, and an adjusted timeout cannot become 0, as
+					if it were 0 the function would have exited. */
+					#if( configUSE_MUTEXES == 1 )
+					{
+						configASSERT( xInheritanceOccurred == pdFALSE );
+					}
+					#endif /* configUSE_MUTEXES */
+
+					/* The semaphore count was 0 and no block time is specified
+					(or the block time has expired) so exit now. */
 					taskEXIT_CRITICAL();
 					traceQUEUE_RECEIVE_FAILED( pxQueue );
 					return errQUEUE_EMPTY;
 				}
 				else if( xEntryTimeSet == pdFALSE )
 				{
-					/* The queue was empty and a block time was specified so
-					configure the timeout structure. */
-					vTaskSetTimeOutState( &xTimeOut );
+					/* The semaphore count was 0 and a block time was specified
+					so configure the timeout structure ready to block. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
 					xEntryTimeSet = pdTRUE;
 				}
 				else
@@ -1364,7 +1528,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 		}
 		taskEXIT_CRITICAL();
 
-		/* Interrupts and other tasks can send to and receive from the queue
+		/* Interrupts and other tasks can give to and take from the semaphore
 		now the critical section has been exited. */
 
 		vTaskSuspendAll();
@@ -1373,6 +1537,10 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 		/* Update the timeout state to see if it has expired yet. */
 		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
 		{
+			/* A block time is specified and not expired.  If the semaphore
+			count is 0 then enter the Blocked state to wait for a semaphore to
+			become available.  As semaphores are implemented with queues the
+			queue being empty is equivalent to the semaphore count being 0. */
 			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
 			{
 				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
@@ -1383,7 +1551,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 					{
 						taskENTER_CRITICAL();
 						{
-							vTaskPriorityInherit( ( void * ) pxQueue->pxMutexHolder );
+							xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
 						}
 						taskEXIT_CRITICAL();
 					}
@@ -1407,18 +1575,48 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 			}
 			else
 			{
-				/* Try again. */
+				/* There was no timeout and the semaphore count was not 0, so
+				attempt to take the semaphore again. */
 				prvUnlockQueue( pxQueue );
 				( void ) xTaskResumeAll();
 			}
 		}
 		else
 		{
+			/* Timed out. */
 			prvUnlockQueue( pxQueue );
 			( void ) xTaskResumeAll();
 
+			/* If the semaphore count is 0 exit now as the timeout has
+			expired.  Otherwise return to attempt to take the semaphore that is
+			known to be available.  As semaphores are implemented by queues the
+			queue being empty is equivalent to the semaphore count being 0. */
 			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
 			{
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					/* xInheritanceOccurred could only have be set if
+					pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
+					test the mutex type again to check it is actually a mutex. */
+					if( xInheritanceOccurred != pdFALSE )
+					{
+						taskENTER_CRITICAL();
+						{
+							UBaseType_t uxHighestWaitingPriority;
+
+							/* This task blocking on the mutex caused another
+							task to inherit this task's priority.  Now this task
+							has timed out the priority should be disinherited
+							again, but only as low as the next highest priority
+							task that is waiting for the same mutex. */
+							uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
+							vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
+						}
+						taskEXIT_CRITICAL();
+					}
+				}
+				#endif /* configUSE_MUTEXES */
+
 				traceQUEUE_RECEIVE_FAILED( pxQueue );
 				return errQUEUE_EMPTY;
 			}
@@ -1427,7 +1625,156 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 				mtCOVERAGE_TEST_MARKER();
 			}
 		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+int8_t *pcOriginalReadPosition;
+Queue_t * const pxQueue = xQueue;
+
+	/* Check the pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* The buffer into which data is received can only be NULL if the data size
+	is zero (so no data is copied into the buffer. */
+	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
 	}
+	#endif
+
+
+	/*lint -save -e904  This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Remember the read position so it can be reset after the data
+				is read from the queue as this function is only peeking the
+				data, not removing it. */
+				pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
+
+				prvCopyDataFromQueue( pxQueue, pvBuffer );
+				traceQUEUE_PEEK( pxQueue );
+
+				/* The data is not being removed, so reset the read pointer. */
+				pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
+
+				/* The data is being left in the queue, so see if there are
+				any other tasks waiting for the data. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority than this task. */
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was empty and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_PEEK_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was empty and a block time was specified so
+					configure the timeout structure ready to enter the blocked
+					state. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* Timeout has not expired yet, check to see if there is data in the
+			queue now, and if not enter the Blocked state to wait for data. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_PEEK( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* There is data in the queue now, so don't enter the blocked
+				state, instead return to try and obtain the data. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* The timeout has expired.  If there is still no data in the queue
+			exit, otherwise go back and try to read the data again. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceQUEUE_PEEK_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
 }
 /*-----------------------------------------------------------*/
 
@@ -1435,7 +1782,7 @@ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, Ba
 {
 BaseType_t xReturn;
 UBaseType_t uxSavedInterruptStatus;
-Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+Queue_t * const pxQueue = xQueue;
 
 	configASSERT( pxQueue );
 	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
@@ -1468,7 +1815,7 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 			traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
 
 			prvCopyDataFromQueue( pxQueue, pvBuffer );
-			pxQueue->uxMessagesWaiting = uxMessagesWaiting - 1;
+			pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
 
 			/* If the queue is locked the event list will not be modified.
 			Instead update the lock count so the task that unlocks the queue
@@ -1527,7 +1874,7 @@ BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,  void * const pvBuffer )
 BaseType_t xReturn;
 UBaseType_t uxSavedInterruptStatus;
 int8_t *pcOriginalReadPosition;
-Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+Queue_t * const pxQueue = xQueue;
 
 	configASSERT( pxQueue );
 	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
@@ -1558,9 +1905,9 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 
 			/* Remember the read position so it can be reset as nothing is
 			actually being removed from the queue. */
-			pcOriginalReadPosition = pxQueue->u.pcReadFrom;
+			pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
 			prvCopyDataFromQueue( pxQueue, pvBuffer );
-			pxQueue->u.pcReadFrom = pcOriginalReadPosition;
+			pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
 
 			xReturn = pdPASS;
 		}
@@ -1595,9 +1942,8 @@ UBaseType_t uxReturn;
 UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
 {
 UBaseType_t uxReturn;
-Queue_t *pxQueue;
+Queue_t * const pxQueue = xQueue;
 
-	pxQueue = ( Queue_t * ) xQueue;
 	configASSERT( pxQueue );
 
 	taskENTER_CRITICAL();
@@ -1613,10 +1959,10 @@ Queue_t *pxQueue;
 UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
 {
 UBaseType_t uxReturn;
+Queue_t * const pxQueue = xQueue;
 
-	configASSERT( xQueue );
-
-	uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
+	configASSERT( pxQueue );
+	uxReturn = pxQueue->uxMessagesWaiting;
 
 	return uxReturn;
 } /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
@@ -1624,7 +1970,7 @@ UBaseType_t uxReturn;
 
 void vQueueDelete( QueueHandle_t xQueue )
 {
-Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+Queue_t * const pxQueue = xQueue;
 
 	configASSERT( pxQueue );
 	traceQUEUE_DELETE( pxQueue );
@@ -1694,6 +2040,33 @@ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
 #endif /* configUSE_TRACE_FACILITY */
 /*-----------------------------------------------------------*/
 
+#if( configUSE_MUTEXES == 1 )
+
+	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
+	{
+	UBaseType_t uxHighestPriorityOfWaitingTasks;
+
+		/* If a task waiting for a mutex causes the mutex holder to inherit a
+		priority, but the waiting task times out, then the holder should
+		disinherit the priority - but only down to the highest priority of any
+		other tasks that are waiting for the same mutex.  For this purpose,
+		return the priority of the highest priority task that is waiting for the
+		mutex. */
+		if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
+		{
+			uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
+		}
+		else
+		{
+			uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
+		}
+
+		return uxHighestPriorityOfWaitingTasks;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
 static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
 {
 BaseType_t xReturn = pdFALSE;
@@ -1710,8 +2083,8 @@ UBaseType_t uxMessagesWaiting;
 			if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
 			{
 				/* The mutex is no longer being held. */
-				xReturn = xTaskPriorityDisinherit( ( void * ) pxQueue->pxMutexHolder );
-				pxQueue->pxMutexHolder = NULL;
+				xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
+				pxQueue->u.xSemaphore.xMutexHolder = NULL;
 			}
 			else
 			{
@@ -1722,9 +2095,9 @@ UBaseType_t uxMessagesWaiting;
 	}
 	else if( xPosition == queueSEND_TO_BACK )
 	{
-		( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. */
-		pxQueue->pcWriteTo += pxQueue->uxItemSize;
-		if( pxQueue->pcWriteTo >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+		( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+		pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+		if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
 		{
 			pxQueue->pcWriteTo = pxQueue->pcHead;
 		}
@@ -1735,11 +2108,11 @@ UBaseType_t uxMessagesWaiting;
 	}
 	else
 	{
-		( void ) memcpy( ( void * ) pxQueue->u.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-		pxQueue->u.pcReadFrom -= pxQueue->uxItemSize;
-		if( pxQueue->u.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+		( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes.  Assert checks null pointer only used when length is 0. */
+		pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
+		if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
 		{
-			pxQueue->u.pcReadFrom = ( pxQueue->pcTail - pxQueue->uxItemSize );
+			pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
 		}
 		else
 		{
@@ -1767,7 +2140,7 @@ UBaseType_t uxMessagesWaiting;
 		}
 	}
 
-	pxQueue->uxMessagesWaiting = uxMessagesWaiting + 1;
+	pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
 
 	return xReturn;
 }
@@ -1777,16 +2150,16 @@ static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer
 {
 	if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
 	{
-		pxQueue->u.pcReadFrom += pxQueue->uxItemSize;
-		if( pxQueue->u.pcReadFrom >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
+		pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+		if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
 		{
-			pxQueue->u.pcReadFrom = pxQueue->pcHead;
+			pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
 		}
 		else
 		{
 			mtCOVERAGE_TEST_MARKER();
 		}
-		( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. */
+		( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
 	}
 }
 /*-----------------------------------------------------------*/
@@ -1935,9 +2308,10 @@ BaseType_t xReturn;
 BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )
 {
 BaseType_t xReturn;
+Queue_t * const pxQueue = xQueue;
 
-	configASSERT( xQueue );
-	if( ( ( Queue_t * ) xQueue )->uxMessagesWaiting == ( UBaseType_t ) 0 )
+	configASSERT( pxQueue );
+	if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
 	{
 		xReturn = pdTRUE;
 	}
@@ -1974,9 +2348,10 @@ BaseType_t xReturn;
 BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
 {
 BaseType_t xReturn;
+Queue_t * const pxQueue = xQueue;
 
-	configASSERT( xQueue );
-	if( ( ( Queue_t * ) xQueue )->uxMessagesWaiting == ( ( Queue_t * ) xQueue )->uxLength )
+	configASSERT( pxQueue );
+	if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
 	{
 		xReturn = pdTRUE;
 	}
@@ -1994,7 +2369,7 @@ BaseType_t xReturn;
 	BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait )
 	{
 	BaseType_t xReturn;
-	Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+	Queue_t * const pxQueue = xQueue;
 
 		/* If the queue is already full we may have to block.  A critical section
 		is required to prevent an interrupt removing something from the queue
@@ -2071,7 +2446,7 @@ BaseType_t xReturn;
 	BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait )
 	{
 	BaseType_t xReturn;
-	Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+	Queue_t * const pxQueue = xQueue;
 
 		/* If the queue is already empty we may have to block.  A critical section
 		is required to prevent an interrupt adding something to the queue
@@ -2108,17 +2483,17 @@ BaseType_t xReturn;
 			if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
 			{
 				/* Data is available from the queue. */
-				pxQueue->u.pcReadFrom += pxQueue->uxItemSize;
-				if( pxQueue->u.pcReadFrom >= pxQueue->pcTail )
+				pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+				if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
 				{
-					pxQueue->u.pcReadFrom = pxQueue->pcHead;
+					pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
 				}
 				else
 				{
 					mtCOVERAGE_TEST_MARKER();
 				}
 				--( pxQueue->uxMessagesWaiting );
-				( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+				( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
 
 				xReturn = pdPASS;
 
@@ -2160,7 +2535,7 @@ BaseType_t xReturn;
 
 	BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken )
 	{
-	Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+	Queue_t * const pxQueue = xQueue;
 
 		/* Cannot block within an ISR so if there is no space on the queue then
 		exit without doing anything. */
@@ -2209,24 +2584,24 @@ BaseType_t xReturn;
 	BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxCoRoutineWoken )
 	{
 	BaseType_t xReturn;
-	Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+	Queue_t * const pxQueue = xQueue;
 
 		/* We cannot block from an ISR, so check there is data available. If
 		not then just leave without doing anything. */
 		if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
 		{
 			/* Copy the data from the queue. */
-			pxQueue->u.pcReadFrom += pxQueue->uxItemSize;
-			if( pxQueue->u.pcReadFrom >= pxQueue->pcTail )
+			pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+			if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
 			{
-				pxQueue->u.pcReadFrom = pxQueue->pcHead;
+				pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
 			}
 			else
 			{
 				mtCOVERAGE_TEST_MARKER();
 			}
 			--( pxQueue->uxMessagesWaiting );
-			( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+			( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
 
 			if( ( *pxCoRoutineWoken ) == pdFALSE )
 			{
@@ -2316,7 +2691,7 @@ BaseType_t xReturn;
 		}
 
 		return pcReturn;
-	}
+	} /*lint !e818 xQueue cannot be a pointer to const because it is a typedef. */
 
 #endif /* configQUEUE_REGISTRY_SIZE */
 /*-----------------------------------------------------------*/
@@ -2357,7 +2732,7 @@ BaseType_t xReturn;
 
 	void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
 	{
-	Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+	Queue_t * const pxQueue = xQueue;
 
 		/* This function should not be called by application code hence the
 		'Restricted' in its name.  It is not part of the public API.  It is
@@ -2395,7 +2770,7 @@ BaseType_t xReturn;
 	{
 	QueueSetHandle_t pxQueue;
 
-		pxQueue = xQueueGenericCreate( uxEventQueueLength, sizeof( Queue_t * ), queueQUEUE_TYPE_SET );
+		pxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET );
 
 		return pxQueue;
 	}
@@ -2478,7 +2853,7 @@ BaseType_t xReturn;
 	{
 	QueueSetMemberHandle_t xReturn = NULL;
 
-		( void ) xQueueGenericReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait, pdFALSE ); /*lint !e961 Casting from one typedef to another is not redundant. */
+		( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); /*lint !e961 Casting from one typedef to another is not redundant. */
 		return xReturn;
 	}
 
diff --git a/os/freertos/stream_buffer.c b/os/freertos/stream_buffer.c
new file mode 100644
index 000000000..23cb444b4
--- /dev/null
+++ b/os/freertos/stream_buffer.c
@@ -0,0 +1,1263 @@
+/*
+ * FreeRTOS Kernel V10.1.1
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "stream_buffer.h"
+
+#if( configUSE_TASK_NOTIFICATIONS != 1 )
+	#error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c
+#endif
+
+/* Lint e961, e9021 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+/* If the user has not provided application specific Rx notification macros,
+or #defined the notification macros away, them provide default implementations
+that uses task notifications. */
+/*lint -save -e9026 Function like macros allowed and needed here so they can be overidden. */
+#ifndef sbRECEIVE_COMPLETED
+	#define sbRECEIVE_COMPLETED( pxStreamBuffer )										\
+		vTaskSuspendAll();																\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )						\
+			{																			\
+				( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend,			\
+									  ( uint32_t ) 0,									\
+									  eNoAction );										\
+				( pxStreamBuffer )->xTaskWaitingToSend = NULL;							\
+			}																			\
+		}																				\
+		( void ) xTaskResumeAll();
+#endif /* sbRECEIVE_COMPLETED */
+
+#ifndef sbRECEIVE_COMPLETED_FROM_ISR
+	#define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,								\
+										  pxHigherPriorityTaskWoken )					\
+	{																					\
+	UBaseType_t uxSavedInterruptStatus;													\
+																						\
+		uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();		\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )						\
+			{																			\
+				( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,	\
+											 ( uint32_t ) 0,							\
+											 eNoAction,									\
+											 pxHigherPriorityTaskWoken );				\
+				( pxStreamBuffer )->xTaskWaitingToSend = NULL;							\
+			}																			\
+		}																				\
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );					\
+	}
+#endif /* sbRECEIVE_COMPLETED_FROM_ISR */
+
+/* If the user has not provided an application specific Tx notification macro,
+or #defined the notification macro away, them provide a default implementation
+that uses task notifications. */
+#ifndef sbSEND_COMPLETED
+	#define sbSEND_COMPLETED( pxStreamBuffer )											\
+		vTaskSuspendAll();																\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )						\
+			{																			\
+				( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToReceive,		\
+									  ( uint32_t ) 0,									\
+									  eNoAction );										\
+				( pxStreamBuffer )->xTaskWaitingToReceive = NULL;						\
+			}																			\
+		}																				\
+		( void ) xTaskResumeAll();
+#endif /* sbSEND_COMPLETED */
+
+#ifndef sbSEND_COMPLETE_FROM_ISR
+	#define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )		\
+	{																					\
+	UBaseType_t uxSavedInterruptStatus;													\
+																						\
+		uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();		\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )						\
+			{																			\
+				( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,	\
+											 ( uint32_t ) 0,							\
+											 eNoAction,									\
+											 pxHigherPriorityTaskWoken );				\
+				( pxStreamBuffer )->xTaskWaitingToReceive = NULL;						\
+			}																			\
+		}																				\
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );					\
+	}
+#endif /* sbSEND_COMPLETE_FROM_ISR */
+/*lint -restore (9026) */
+
+/* The number of bytes used to hold the length of a message in the buffer. */
+#define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )
+
+/* Bits stored in the ucFlags field of the stream buffer. */
+#define sbFLAGS_IS_MESSAGE_BUFFER		( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */
+#define sbFLAGS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */
+
+/*-----------------------------------------------------------*/
+
+/* Structure that hold state information on the buffer. */
+typedef struct StreamBufferDef_t /*lint !e9058 Style convention uses tag. */
+{
+	volatile size_t xTail;				/* Index to the next item to read within the buffer. */
+	volatile size_t xHead;				/* Index to the next item to write within the buffer. */
+	size_t xLength;						/* The length of the buffer pointed to by pucBuffer. */
+	size_t xTriggerLevelBytes;			/* The number of bytes that must be in the stream buffer before a task that is waiting for data is unblocked. */
+	volatile TaskHandle_t xTaskWaitingToReceive; /* Holds the handle of a task waiting for data, or NULL if no tasks are waiting. */
+	volatile TaskHandle_t xTaskWaitingToSend;	/* Holds the handle of a task waiting to send data to a message buffer that is full. */
+	uint8_t *pucBuffer;					/* Points to the buffer itself - that is - the RAM that stores the data passed through the buffer. */
+	uint8_t ucFlags;
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxStreamBufferNumber;		/* Used for tracing purposes. */
+	#endif
+} StreamBuffer_t;
+
+/*
+ * The number of bytes available to be read from the buffer.
+ */
+static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/*
+ * Add xCount bytes from pucData into the pxStreamBuffer message buffer.
+ * Returns the number of bytes written, which will either equal xCount in the
+ * success case, or 0 if there was not enough space in the buffer (in which case
+ * no data is written into the buffer).
+ */
+static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the stream buffer is being used as a message buffer, then reads an entire
+ * message out of the buffer.  If the stream buffer is being used as a stream
+ * buffer then read as many bytes as possible from the buffer.
+ * prvReadBytesFromBuffer() is called to actually extract the bytes from the
+ * buffer's data storage area.
+ */
+static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
+										void *pvRxData,
+										size_t xBufferLengthBytes,
+										size_t xBytesAvailable,
+										size_t xBytesToStoreMessageLength ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the stream buffer is being used as a message buffer, then writes an entire
+ * message to the buffer.  If the stream buffer is being used as a stream
+ * buffer then write as many bytes as possible to the buffer.
+ * prvWriteBytestoBuffer() is called to actually send the bytes to the buffer's
+ * data storage area.
+ */
+static size_t prvWriteMessageToBuffer(  StreamBuffer_t * const pxStreamBuffer,
+										const void * pvTxData,
+										size_t xDataLengthBytes,
+										size_t xSpace,
+										size_t xRequiredSpace ) PRIVILEGED_FUNCTION;
+
+/*
+ * Read xMaxCount bytes from the pxStreamBuffer message buffer and write them
+ * to pucData.
+ */
+static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer,
+									  uint8_t *pucData,
+									  size_t xMaxCount,
+									  size_t xBytesAvailable ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to
+ * initialise the members of the newly created stream buffer structure.
+ */
+static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
+										  uint8_t * const pucBuffer,
+										  size_t xBufferSizeBytes,
+										  size_t xTriggerLevelBytes,
+										  uint8_t ucFlags ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer )
+	{
+	uint8_t *pucAllocatedMemory;
+	uint8_t ucFlags;
+
+		/* In case the stream buffer is going to be used as a message buffer
+		(that is, it will hold discrete messages with a little meta data that
+		says how big the next message is) check the buffer will be large enough
+		to hold at least one message. */
+		if( xIsMessageBuffer == pdTRUE )
+		{
+			/* Is a message buffer but not statically allocated. */
+			ucFlags = sbFLAGS_IS_MESSAGE_BUFFER;
+			configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+		}
+		else
+		{
+			/* Not a message buffer and not statically allocated. */
+			ucFlags = 0;
+			configASSERT( xBufferSizeBytes > 0 );
+		}
+		configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
+
+		/* A trigger level of 0 would cause a waiting task to unblock even when
+		the buffer was empty. */
+		if( xTriggerLevelBytes == ( size_t ) 0 )
+		{
+			xTriggerLevelBytes = ( size_t ) 1;
+		}
+
+		/* A stream buffer requires a StreamBuffer_t structure and a buffer.
+		Both are allocated in a single call to pvPortMalloc().  The
+		StreamBuffer_t structure is placed at the start of the allocated memory
+		and the buffer follows immediately after.  The requested size is
+		incremented so the free space is returned as the user would expect -
+		this is a quirk of the implementation that means otherwise the free
+		space would be reported as one byte smaller than would be logically
+		expected. */
+		xBufferSizeBytes++;
+		pucAllocatedMemory = ( uint8_t * ) pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) ); /*lint !e9079 malloc() only returns void*. */
+
+		if( pucAllocatedMemory != NULL )
+		{
+			prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pucAllocatedMemory, /* Structure at the start of the allocated memory. */ /*lint !e9087 Safe cast as allocated memory is aligned. */ /*lint !e826 Area is not too small and alignment is guaranteed provided malloc() behaves as expected and returns aligned buffer. */
+										   pucAllocatedMemory + sizeof( StreamBuffer_t ),  /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */
+										   xBufferSizeBytes,
+										   xTriggerLevelBytes,
+										   ucFlags );
+
+			traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pucAllocatedMemory ), xIsMessageBuffer );
+		}
+		else
+		{
+			traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );
+		}
+
+		return ( StreamBufferHandle_t ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+														   size_t xTriggerLevelBytes,
+														   BaseType_t xIsMessageBuffer,
+														   uint8_t * const pucStreamBufferStorageArea,
+														   StaticStreamBuffer_t * const pxStaticStreamBuffer )
+	{
+	StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */
+	StreamBufferHandle_t xReturn;
+	uint8_t ucFlags;
+
+		configASSERT( pucStreamBufferStorageArea );
+		configASSERT( pxStaticStreamBuffer );
+		configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
+
+		/* A trigger level of 0 would cause a waiting task to unblock even when
+		the buffer was empty. */
+		if( xTriggerLevelBytes == ( size_t ) 0 )
+		{
+			xTriggerLevelBytes = ( size_t ) 1;
+		}
+
+		if( xIsMessageBuffer != pdFALSE )
+		{
+			/* Statically allocated message buffer. */
+			ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED;
+		}
+		else
+		{
+			/* Statically allocated stream buffer. */
+			ucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED;
+		}
+
+		/* In case the stream buffer is going to be used as a message buffer
+		(that is, it will hold discrete messages with a little meta data that
+		says how big the next message is) check the buffer will be large enough
+		to hold at least one message. */
+		configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticStreamBuffer_t equals the size of the real
+			message buffer structure. */
+			volatile size_t xSize = sizeof( StaticStreamBuffer_t );
+			configASSERT( xSize == sizeof( StreamBuffer_t ) );
+		} /*lint !e529 xSize is referenced is configASSERT() is defined. */
+		#endif /* configASSERT_DEFINED */
+
+		if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) )
+		{
+			prvInitialiseNewStreamBuffer( pxStreamBuffer,
+										  pucStreamBufferStorageArea,
+										  xBufferSizeBytes,
+										  xTriggerLevelBytes,
+										  ucFlags );
+
+			/* Remember this was statically allocated in case it is ever deleted
+			again. */
+			pxStreamBuffer->ucFlags |= sbFLAGS_IS_STATICALLY_ALLOCATED;
+
+			traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer );
+
+			xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer; /*lint !e9087 Data hiding requires cast to opaque type. */
+		}
+		else
+		{
+			xReturn = NULL;
+			traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * pxStreamBuffer = xStreamBuffer;
+
+	configASSERT( pxStreamBuffer );
+
+	traceSTREAM_BUFFER_DELETE( xStreamBuffer );
+
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) pdFALSE )
+	{
+		#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+		{
+			/* Both the structure and the buffer were allocated using a single call
+			to pvPortMalloc(), hence only one call to vPortFree() is required. */
+			vPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */
+		}
+		#else
+		{
+			/* Should not be possible to get here, ucFlags must be corrupt.
+			Force an assert. */
+			configASSERT( xStreamBuffer == ( StreamBufferHandle_t ) ~0 );
+		}
+		#endif
+	}
+	else
+	{
+		/* The structure and buffer were not allocated dynamically and cannot be
+		freed - just scrub the structure so future use will assert. */
+		( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn = pdFAIL;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	UBaseType_t uxStreamBufferNumber;
+#endif
+
+	configASSERT( pxStreamBuffer );
+
+	#if( configUSE_TRACE_FACILITY == 1 )
+	{
+		/* Store the stream buffer number so it can be restored after the
+		reset. */
+		uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber;
+	}
+	#endif
+
+	/* Can only reset a message buffer if there are no tasks blocked on it. */
+	taskENTER_CRITICAL();
+	{
+		if( pxStreamBuffer->xTaskWaitingToReceive == NULL )
+		{
+			if( pxStreamBuffer->xTaskWaitingToSend == NULL )
+			{
+				prvInitialiseNewStreamBuffer( pxStreamBuffer,
+											  pxStreamBuffer->pucBuffer,
+											  pxStreamBuffer->xLength,
+											  pxStreamBuffer->xTriggerLevelBytes,
+											  pxStreamBuffer->ucFlags );
+				xReturn = pdPASS;
+
+				#if( configUSE_TRACE_FACILITY == 1 )
+				{
+					pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+				}
+				#endif
+
+				traceSTREAM_BUFFER_RESET( xStreamBuffer );
+			}
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	/* It is not valid for the trigger level to be 0. */
+	if( xTriggerLevel == ( size_t ) 0 )
+	{
+		xTriggerLevel = ( size_t ) 1;
+	}
+
+	/* The trigger level is the number of bytes that must be in the stream
+	buffer before a task that is waiting for data is unblocked. */
+	if( xTriggerLevel <= pxStreamBuffer->xLength )
+	{
+		pxStreamBuffer->xTriggerLevelBytes = xTriggerLevel;
+		xReturn = pdPASS;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xSpace;
+
+	configASSERT( pxStreamBuffer );
+
+	xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail;
+	xSpace -= pxStreamBuffer->xHead;
+	xSpace -= ( size_t ) 1;
+
+	if( xSpace >= pxStreamBuffer->xLength )
+	{
+		xSpace -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xSpace;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	xReturn = prvBytesInBuffer( pxStreamBuffer );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+						  const void *pvTxData,
+						  size_t xDataLengthBytes,
+						  TickType_t xTicksToWait )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xSpace = 0;
+size_t xRequiredSpace = xDataLengthBytes;
+TimeOut_t xTimeOut;
+
+	configASSERT( pvTxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This send function is used to write to both message buffers and stream
+	buffers.  If this is a message buffer then the space needed must be
+	increased by the amount of bytes needed to store the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+
+		/* Overflow? */
+		configASSERT( xRequiredSpace > xDataLengthBytes );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		vTaskSetTimeOutState( &xTimeOut );
+
+		do
+		{
+			/* Wait until the required number of bytes are free in the message
+			buffer. */
+			taskENTER_CRITICAL();
+			{
+				xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+
+				if( xSpace < xRequiredSpace )
+				{
+					/* Clear notification state as going to wait for space. */
+					( void ) xTaskNotifyStateClear( NULL );
+
+					/* Should only be one writer. */
+					configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );
+					pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle();
+				}
+				else
+				{
+					taskEXIT_CRITICAL();
+					break;
+				}
+			}
+			taskEXIT_CRITICAL();
+
+			traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer );
+			( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
+			pxStreamBuffer->xTaskWaitingToSend = NULL;
+
+		} while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	if( xSpace == ( size_t ) 0 )
+	{
+		xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
+
+	if( xReturn > ( size_t ) 0 )
+	{
+		traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn );
+
+		/* Was a task waiting for the data? */
+		if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
+		{
+			sbSEND_COMPLETED( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+		traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer );
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+								 const void *pvTxData,
+								 size_t xDataLengthBytes,
+								 BaseType_t * const pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xSpace;
+size_t xRequiredSpace = xDataLengthBytes;
+
+	configASSERT( pvTxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This send function is used to write to both message buffers and stream
+	buffers.  If this is a message buffer then the space needed must be
+	increased by the amount of bytes needed to store the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+	xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
+
+	if( xReturn > ( size_t ) 0 )
+	{
+		/* Was a task waiting for the data? */
+		if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
+		{
+			sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,
+									   const void * pvTxData,
+									   size_t xDataLengthBytes,
+									   size_t xSpace,
+									   size_t xRequiredSpace )
+{
+	BaseType_t xShouldWrite;
+	size_t xReturn;
+
+	if( xSpace == ( size_t ) 0 )
+	{
+		/* Doesn't matter if this is a stream buffer or a message buffer, there
+		is no space to write. */
+		xShouldWrite = pdFALSE;
+	}
+	else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 )
+	{
+		/* This is a stream buffer, as opposed to a message buffer, so writing a
+		stream of bytes rather than discrete messages.  Write as many bytes as
+		possible. */
+		xShouldWrite = pdTRUE;
+		xDataLengthBytes = configMIN( xDataLengthBytes, xSpace );
+	}
+	else if( xSpace >= xRequiredSpace )
+	{
+		/* This is a message buffer, as opposed to a stream buffer, and there
+		is enough space to write both the message length and the message itself
+		into the buffer.  Start by writing the length of the data, the data
+		itself will be written later in this function. */
+		xShouldWrite = pdTRUE;
+		( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH );
+	}
+	else
+	{
+		/* There is space available, but not enough space. */
+		xShouldWrite = pdFALSE;
+	}
+
+	if( xShouldWrite != pdFALSE )
+	{
+		/* Writes the data itself. */
+		xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */
+	}
+	else
+	{
+		xReturn = 0;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+							 void *pvRxData,
+							 size_t xBufferLengthBytes,
+							 TickType_t xTicksToWait )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+
+	configASSERT( pvRxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This receive function is used by both message buffers, which store
+	discrete messages, and stream buffers, which store a continuous stream of
+	bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		/* Checking if there is data and clearing the notification state must be
+		performed atomically. */
+		taskENTER_CRITICAL();
+		{
+			xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+			/* If this function was invoked by a message buffer read then
+			xBytesToStoreMessageLength holds the number of bytes used to hold
+			the length of the next discrete message.  If this function was
+			invoked by a stream buffer read then xBytesToStoreMessageLength will
+			be 0. */
+			if( xBytesAvailable <= xBytesToStoreMessageLength )
+			{
+				/* Clear notification state as going to wait for data. */
+				( void ) xTaskNotifyStateClear( NULL );
+
+				/* Should only be one reader. */
+				configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL );
+				pxStreamBuffer->xTaskWaitingToReceive = xTaskGetCurrentTaskHandle();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		if( xBytesAvailable <= xBytesToStoreMessageLength )
+		{
+			/* Wait for data to be available. */
+			traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer );
+			( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
+			pxStreamBuffer->xTaskWaitingToReceive = NULL;
+
+			/* Recheck the data available after blocking. */
+			xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+	}
+
+	/* Whether receiving a discrete message (where xBytesToStoreMessageLength
+	holds the number of bytes used to store the message length) or a stream of
+	bytes (where xBytesToStoreMessageLength is zero), the number of bytes
+	available must be greater than xBytesToStoreMessageLength to be able to
+	read bytes from the buffer. */
+	if( xBytesAvailable > xBytesToStoreMessageLength )
+	{
+		xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
+
+		/* Was a task waiting for space in the buffer? */
+		if( xReceivedLength != ( size_t ) 0 )
+		{
+			traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength );
+			sbRECEIVE_COMPLETED( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer );
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xBytesAvailable, xOriginalTail;
+configMESSAGE_BUFFER_LENGTH_TYPE xTempReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	/* Ensure the stream buffer is being used as a message buffer. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+		if( xBytesAvailable > sbBYTES_TO_STORE_MESSAGE_LENGTH )
+		{
+			/* The number of bytes available is greater than the number of bytes
+			required to hold the length of the next message, so another message
+			is available.  Return its length without removing the length bytes
+			from the buffer.  A copy of the tail is stored so the buffer can be
+			returned to its prior state as the message is not actually being
+			removed from the buffer. */
+			xOriginalTail = pxStreamBuffer->xTail;
+			( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempReturn, sbBYTES_TO_STORE_MESSAGE_LENGTH, xBytesAvailable );
+			xReturn = ( size_t ) xTempReturn;
+			pxStreamBuffer->xTail = xOriginalTail;
+		}
+		else
+		{
+			/* The minimum amount of bytes in a message buffer is
+			( sbBYTES_TO_STORE_MESSAGE_LENGTH + 1 ), so if xBytesAvailable is
+			less than sbBYTES_TO_STORE_MESSAGE_LENGTH the only other valid
+			value is 0. */
+			configASSERT( xBytesAvailable == 0 );
+			xReturn = 0;
+		}
+	}
+	else
+	{
+		xReturn = 0;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+									void *pvRxData,
+									size_t xBufferLengthBytes,
+									BaseType_t * const pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+
+	configASSERT( pvRxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This receive function is used by both message buffers, which store
+	discrete messages, and stream buffers, which store a continuous stream of
+	bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+	/* Whether receiving a discrete message (where xBytesToStoreMessageLength
+	holds the number of bytes used to store the message length) or a stream of
+	bytes (where xBytesToStoreMessageLength is zero), the number of bytes
+	available must be greater than xBytesToStoreMessageLength to be able to
+	read bytes from the buffer. */
+	if( xBytesAvailable > xBytesToStoreMessageLength )
+	{
+		xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
+
+		/* Was a task waiting for space in the buffer? */
+		if( xReceivedLength != ( size_t ) 0 )
+		{
+			sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength );
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
+										void *pvRxData,
+										size_t xBufferLengthBytes,
+										size_t xBytesAvailable,
+										size_t xBytesToStoreMessageLength )
+{
+size_t xOriginalTail, xReceivedLength, xNextMessageLength;
+configMESSAGE_BUFFER_LENGTH_TYPE xTempNextMessageLength;
+
+	if( xBytesToStoreMessageLength != ( size_t ) 0 )
+	{
+		/* A discrete message is being received.  First receive the length
+		of the message.  A copy of the tail is stored so the buffer can be
+		returned to its prior state if the length of the message is too
+		large for the provided buffer. */
+		xOriginalTail = pxStreamBuffer->xTail;
+		( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempNextMessageLength, xBytesToStoreMessageLength, xBytesAvailable );
+		xNextMessageLength = ( size_t ) xTempNextMessageLength;
+
+		/* Reduce the number of bytes available by the number of bytes just
+		read out. */
+		xBytesAvailable -= xBytesToStoreMessageLength;
+
+		/* Check there is enough space in the buffer provided by the
+		user. */
+		if( xNextMessageLength > xBufferLengthBytes )
+		{
+			/* The user has provided insufficient space to read the message
+			so return the buffer to its previous state (so the length of
+			the message is in the buffer again). */
+			pxStreamBuffer->xTail = xOriginalTail;
+			xNextMessageLength = 0;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		/* A stream of bytes is being received (as opposed to a discrete
+		message), so read as many bytes as possible. */
+		xNextMessageLength = xBufferLengthBytes;
+	}
+
+	/* Read the actual data. */
+	xReceivedLength = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xNextMessageLength, xBytesAvailable ); /*lint !e9079 Data storage area is implemented as uint8_t array for ease of sizing, indexing and alignment. */
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+size_t xTail;
+
+	configASSERT( pxStreamBuffer );
+
+	/* True if no bytes are available. */
+	xTail = pxStreamBuffer->xTail;
+	if( pxStreamBuffer->xHead == xTail )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer )
+{
+BaseType_t xReturn;
+size_t xBytesToStoreMessageLength;
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+
+	configASSERT( pxStreamBuffer );
+
+	/* This generic version of the receive function is used by both message
+	buffers, which store discrete messages, and stream buffers, which store a
+	continuous stream of bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	/* True if the available space equals zero. */
+	if( xStreamBufferSpacesAvailable( xStreamBuffer ) <= xBytesToStoreMessageLength )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	configASSERT( pxStreamBuffer );
+
+	uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )
+		{
+			( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,
+										 ( uint32_t ) 0,
+										 eNoAction,
+										 pxHigherPriorityTaskWoken );
+			( pxStreamBuffer )->xTaskWaitingToReceive = NULL;
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	configASSERT( pxStreamBuffer );
+
+	uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )
+		{
+			( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,
+										 ( uint32_t ) 0,
+										 eNoAction,
+										 pxHigherPriorityTaskWoken );
+			( pxStreamBuffer )->xTaskWaitingToSend = NULL;
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount )
+{
+size_t xNextHead, xFirstLength;
+
+	configASSERT( xCount > ( size_t ) 0 );
+
+	xNextHead = pxStreamBuffer->xHead;
+
+	/* Calculate the number of bytes that can be added in the first write -
+	which may be less than the total number of bytes that need to be added if
+	the buffer will wrap back to the beginning. */
+	xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount );
+
+	/* Write as many bytes as can be written in the first write. */
+	configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength );
+	( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+
+	/* If the number of bytes written was less than the number that could be
+	written in the first write... */
+	if( xCount > xFirstLength )
+	{
+		/* ...then write the remaining bytes to the start of the buffer. */
+		configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength );
+		( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xNextHead += xCount;
+	if( xNextHead >= pxStreamBuffer->xLength )
+	{
+		xNextHead -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxStreamBuffer->xHead = xNextHead;
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer, uint8_t *pucData, size_t xMaxCount, size_t xBytesAvailable )
+{
+size_t xCount, xFirstLength, xNextTail;
+
+	/* Use the minimum of the wanted bytes and the available bytes. */
+	xCount = configMIN( xBytesAvailable, xMaxCount );
+
+	if( xCount > ( size_t ) 0 )
+	{
+		xNextTail = pxStreamBuffer->xTail;
+
+		/* Calculate the number of bytes that can be read - which may be
+		less than the number wanted if the data wraps around to the start of
+		the buffer. */
+		xFirstLength = configMIN( pxStreamBuffer->xLength - xNextTail, xCount );
+
+		/* Obtain the number of bytes it is possible to obtain in the first
+		read.  Asserts check bounds of read and write. */
+		configASSERT( xFirstLength <= xMaxCount );
+		configASSERT( ( xNextTail + xFirstLength ) <= pxStreamBuffer->xLength );
+		( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xNextTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+
+		/* If the total number of wanted bytes is greater than the number
+		that could be read in the first read... */
+		if( xCount > xFirstLength )
+		{
+			/*...then read the remaining bytes from the start of the buffer. */
+			configASSERT( xCount <= xMaxCount );
+			( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Move the tail pointer to effectively remove the data read from
+		the buffer. */
+		xNextTail += xCount;
+
+		if( xNextTail >= pxStreamBuffer->xLength )
+		{
+			xNextTail -= pxStreamBuffer->xLength;
+		}
+
+		pxStreamBuffer->xTail = xNextTail;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer )
+{
+/* Returns the distance between xTail and xHead. */
+size_t xCount;
+
+	xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead;
+	xCount -= pxStreamBuffer->xTail;
+	if ( xCount >= pxStreamBuffer->xLength )
+	{
+		xCount -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
+										  uint8_t * const pucBuffer,
+										  size_t xBufferSizeBytes,
+										  size_t xTriggerLevelBytes,
+										  uint8_t ucFlags )
+{
+	/* Assert here is deliberately writing to the entire buffer to ensure it can
+	be written to without generating exceptions, and is setting the buffer to a
+	known value to assist in development/debugging. */
+	#if( configASSERT_DEFINED == 1 )
+	{
+		/* The value written just has to be identifiable when looking at the
+		memory.  Don't use 0xA5 as that is the stack fill value and could
+		result in confusion as to what is actually being observed. */
+		const BaseType_t xWriteValue = 0x55;
+		configASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer );
+	} /*lint !e529 !e438 xWriteValue is only used if configASSERT() is defined. */
+	#endif
+
+	( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */
+	pxStreamBuffer->pucBuffer = pucBuffer;
+	pxStreamBuffer->xLength = xBufferSizeBytes;
+	pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes;
+	pxStreamBuffer->ucFlags = ucFlags;
+}
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer )
+	{
+		return xStreamBuffer->uxStreamBufferNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber )
+	{
+		xStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer )
+	{
+		return ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER );
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
diff --git a/os/freertos/tasks.c b/os/freertos/tasks.c
index 6c261a651..c3db5909d 100644
--- a/os/freertos/tasks.c
+++ b/os/freertos/tasks.c
@@ -1,71 +1,29 @@
 /*
-    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
-
-    ***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-    ***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-    the FAQ page "My application does not run, what could be wrong?".  Have you
-    defined configASSERT()?
-
-    http://www.FreeRTOS.org/support - In return for receiving this top quality
-    embedded software for free we request you assist our global community by
-    participating in the support forum.
-
-    http://www.FreeRTOS.org/training - Investing in training allows your team to
-    be as productive as possible as early as possible.  Now you can receive
-    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-    Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
+ * FreeRTOS Kernel V10.1.1
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
 
 /* Standard includes. */
 #include 
@@ -80,13 +38,13 @@ task.h is included from an application file. */
 #include "FreeRTOS.h"
 #include "task.h"
 #include "timers.h"
-#include "StackMacros.h"
+#include "stack_macros.h"
 
-/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
-MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
-header files above, but not in this file, in order to generate the correct
-privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
 
 /* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting
 functions but without including stdio.h here. */
@@ -131,15 +89,27 @@ made to free the RAM that was allocated statically.
 tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a
 task to be created using either statically or dynamically allocated RAM.  Note
 that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with
-a statically allocated stack and a dynamically allocated TCB. */
-#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE ( ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) || ( portUSING_MPU_WRAPPERS == 1 ) )
+a statically allocated stack and a dynamically allocated TCB.
+!!!NOTE!!! If the definition of tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is
+changed then the definition of StaticTask_t must also be updated. */
+#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE	( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
 #define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB 		( ( uint8_t ) 0 )
 #define tskSTATICALLY_ALLOCATED_STACK_ONLY 			( ( uint8_t ) 1 )
 #define tskSTATICALLY_ALLOCATED_STACK_AND_TCB		( ( uint8_t ) 2 )
 
+/* If any of the following are set then task stacks are filled with a known
+value so the high water mark can be determined.  If none of the following are
+set then don't fill the stack so there is no unnecessary dependency on memset. */
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )
+	#define tskSET_NEW_STACKS_TO_KNOWN_VALUE	1
+#else
+	#define tskSET_NEW_STACKS_TO_KNOWN_VALUE	0
+#endif
+
 /*
  * Macros used by vListTask to indicate which state a task is in.
  */
+#define tskRUNNING_CHAR		( 'X' )
 #define tskBLOCKED_CHAR		( 'B' )
 #define tskREADY_CHAR		( 'R' )
 #define tskDELETED_CHAR		( 'D' )
@@ -153,6 +123,12 @@ a statically allocated stack and a dynamically allocated TCB. */
 	#define static
 #endif
 
+/* The name allocated to the Idle task.  This can be overridden by defining
+configIDLE_TASK_NAME in FreeRTOSConfig.h. */
+#ifndef configIDLE_TASK_NAME
+	#define configIDLE_TASK_NAME "IDLE"
+#endif
+
 #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
 
 	/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is
@@ -269,7 +245,7 @@ count overflows. */
  * task should be used in place of the parameter.  This macro simply checks to
  * see if the parameter is NULL and returns a pointer to the appropriate TCB.
  */
-#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? ( TCB_t * ) pxCurrentTCB : ( TCB_t * ) ( pxHandle ) )
+#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? pxCurrentTCB : ( pxHandle ) )
 
 /* The item value of the event list item is normally used to hold the priority
 of the task to which it belongs (coded to allow it to be held in reverse
@@ -290,7 +266,7 @@ to its original value when it is released. */
  * and stores task state information, including a pointer to the task's context
  * (the task's run time environment, including register values)
  */
-typedef struct tskTaskControlBlock
+typedef struct tskTaskControlBlock /* The old naming convention is used to prevent breaking kernel aware debuggers. */
 {
 	volatile StackType_t	*pxTopOfStack;	/*< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */
 
@@ -304,8 +280,8 @@ typedef struct tskTaskControlBlock
 	StackType_t			*pxStack;			/*< Points to the start of the stack. */
 	char				pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
 
-	#if ( portSTACK_GROWTH > 0 )
-		StackType_t		*pxEndOfStack;		/*< Points to the end of the stack on architectures where the stack grows up from low memory. */
+	#if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+		StackType_t		*pxEndOfStack;		/*< Points to the highest valid address for the stack. */
 	#endif
 
 	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
@@ -327,7 +303,7 @@ typedef struct tskTaskControlBlock
 	#endif
 
 	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
-		void *pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
+		void			*pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
 	#endif
 
 	#if( configGENERATE_RUN_TIME_STATS == 1 )
@@ -352,7 +328,7 @@ typedef struct tskTaskControlBlock
 
 	/* See the comments above the definition of
 	tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */
-	#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+	#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
 		uint8_t	ucStaticallyAllocated; 		/*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
 	#endif
 
@@ -360,18 +336,24 @@ typedef struct tskTaskControlBlock
 		uint8_t ucDelayAborted;
 	#endif
 
+	#if( configUSE_POSIX_ERRNO == 1 )
+		int iTaskErrno;
+	#endif
+
 } tskTCB;
 
 /* The old tskTCB name is maintained above then typedefed to the new TCB_t name
 below to enable the use of older kernel aware debuggers. */
 typedef tskTCB TCB_t;
 
-/*lint -e956 A manual analysis and inspection has been used to determine which
-static variables must be declared volatile. */
-
+/*lint -save -e956 A manual analysis and inspection has been used to determine
+which static variables must be declared volatile. */
 PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
 
-/* Lists for ready and blocked tasks. --------------------*/
+/* Lists for ready and blocked tasks. --------------------
+xDelayedTaskList1 and xDelayedTaskList2 could be move to function scople but
+doing so breaks some kernel aware debuggers and debuggers that rely on removing
+the static qualifier. */
 PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ];/*< Prioritised ready tasks. */
 PRIVILEGED_DATA static List_t xDelayedTaskList1;						/*< Delayed tasks. */
 PRIVILEGED_DATA static List_t xDelayedTaskList2;						/*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */
@@ -392,9 +374,15 @@ PRIVILEGED_DATA static List_t xPendingReadyList;						/*< Tasks that have been r
 
 #endif
 
+/* Global POSIX errno. Its value is changed upon context switching to match
+the errno of the currently running task. */
+#if ( configUSE_POSIX_ERRNO == 1 )
+	int FreeRTOS_errno = 0;
+#endif
+
 /* Other file private variables. --------------------------------*/
 PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks 	= ( UBaseType_t ) 0U;
-PRIVILEGED_DATA static volatile TickType_t xTickCount 				= ( TickType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xTickCount 				= ( TickType_t ) configINITIAL_TICK_COUNT;
 PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority 		= tskIDLE_PRIORITY;
 PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning 		= pdFALSE;
 PRIVILEGED_DATA static volatile UBaseType_t uxPendedTicks 			= ( UBaseType_t ) 0U;
@@ -416,26 +404,34 @@ PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended	= ( UBaseType_t
 
 #if ( configGENERATE_RUN_TIME_STATS == 1 )
 
+	/* Do not move these variables to function scope as doing so prevents the
+	code working with debuggers that need to remove the static qualifier. */
 	PRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL;	/*< Holds the value of a timer/counter the last time a task was switched in. */
 	PRIVILEGED_DATA static uint32_t ulTotalRunTime = 0UL;		/*< Holds the total amount of execution time as defined by the run time counter clock. */
 
 #endif
 
-/*lint +e956 */
+/*lint -restore */
 
 /*-----------------------------------------------------------*/
 
 /* Callback function prototypes. --------------------------*/
 #if(  configCHECK_FOR_STACK_OVERFLOW > 0 )
+
 	extern void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName );
+
 #endif
 
 #if( configUSE_TICK_HOOK > 0 )
-	extern void vApplicationTickHook( void );
+
+	extern void vApplicationTickHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */
+
 #endif
 
 #if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	extern void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize );
+
+	extern void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */
+
 #endif
 
 /* File private functions. --------------------------------*/
@@ -446,7 +442,9 @@ PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended	= ( UBaseType_t
  * is in any other state.
  */
 #if ( INCLUDE_vTaskSuspend == 1 )
+
 	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
 #endif /* INCLUDE_vTaskSuspend */
 
 /*
@@ -525,7 +523,7 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseT
  */
 #if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )
 
-	static uint16_t prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;
+	static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;
 
 #endif
 
@@ -565,13 +563,13 @@ static void prvResetNextTaskUnblockTime( void );
  * dynamically to fill in the structure's members.
  */
 static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
-									const char * const pcName,
+									const char * const pcName, 		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
 									const uint32_t ulStackDepth,
 									void * const pvParameters,
 									UBaseType_t uxPriority,
 									TaskHandle_t * const pxCreatedTask,
 									TCB_t *pxNewTCB,
-									const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;
 
 /*
  * Called after a new task has been created and initialised to place the task
@@ -579,17 +577,28 @@ static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
  */
 static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;
 
+/*
+ * freertos_tasks_c_additions_init() should only be called if the user definable
+ * macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro
+ * called by the function.
+ */
+#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+
+	static void freertos_tasks_c_additions_init( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
 /*-----------------------------------------------------------*/
 
 #if( configSUPPORT_STATIC_ALLOCATION == 1 )
 
 	TaskHandle_t xTaskCreateStatic(	TaskFunction_t pxTaskCode,
-									const char * const pcName,
+									const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
 									const uint32_t ulStackDepth,
 									void * const pvParameters,
 									UBaseType_t uxPriority,
 									StackType_t * const puxStackBuffer,
-									StaticTask_t * const pxTaskBuffer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									StaticTask_t * const pxTaskBuffer )
 	{
 	TCB_t *pxNewTCB;
 	TaskHandle_t xReturn;
@@ -597,14 +606,26 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;
 		configASSERT( puxStackBuffer != NULL );
 		configASSERT( pxTaskBuffer != NULL );
 
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticTask_t equals the size of the real task
+			structure. */
+			volatile size_t xSize = sizeof( StaticTask_t );
+			configASSERT( xSize == sizeof( TCB_t ) );
+			( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
+		}
+		#endif /* configASSERT_DEFINED */
+
+
 		if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
 		{
 			/* The memory used for the task's TCB and stack are passed into this
 			function - use them. */
-			pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+			pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
 			pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
 
-			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
 			{
 				/* Tasks can be created statically or dynamically, so note this
 				task was created statically in case the task is later deleted. */
@@ -626,7 +647,53 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;
 #endif /* SUPPORT_STATIC_ALLOCATION */
 /*-----------------------------------------------------------*/
 
-#if( portUSING_MPU_WRAPPERS == 1 )
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+
+		configASSERT( pxTaskDefinition->puxStackBuffer != NULL );
+		configASSERT( pxTaskDefinition->pxTaskBuffer != NULL );
+
+		if( ( pxTaskDefinition->puxStackBuffer != NULL ) && ( pxTaskDefinition->pxTaskBuffer != NULL ) )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends
+			on the implementation of the port malloc function and whether or
+			not static allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer;
+
+			/* Store the stack location in the TCB. */
+			pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
+
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created statically in case the task is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+			prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
+									pxTaskDefinition->pcName,
+									( uint32_t ) pxTaskDefinition->usStackDepth,
+									pxTaskDefinition->pvParameters,
+									pxTaskDefinition->uxPriority,
+									pxCreatedTask, pxNewTCB,
+									pxTaskDefinition->xRegions );
+
+			prvAddNewTaskToReadyList( pxNewTCB );
+			xReturn = pdPASS;
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
 
 	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
 	{
@@ -647,10 +714,14 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;
 				/* Store the stack location in the TCB. */
 				pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
 
-				/* Tasks can be created statically or dynamically, so note
-				this task had a statically allocated stack in case it is
-				later deleted.  The TCB was allocated dynamically. */
-				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY;
+				#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+				{
+					/* Tasks can be created statically or dynamically, so note
+					this task had a statically allocated stack in case it is
+					later deleted.  The TCB was allocated dynamically. */
+					pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY;
+				}
+				#endif
 
 				prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
 										pxTaskDefinition->pcName,
@@ -674,11 +745,11 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;
 #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
 
 	BaseType_t xTaskCreate(	TaskFunction_t pxTaskCode,
-							const char * const pcName,
-							const uint16_t usStackDepth,
+							const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+							const configSTACK_DEPTH_TYPE usStackDepth,
 							void * const pvParameters,
 							UBaseType_t uxPriority,
-							TaskHandle_t * const pxCreatedTask ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+							TaskHandle_t * const pxCreatedTask )
 	{
 	TCB_t *pxNewTCB;
 	BaseType_t xReturn;
@@ -713,12 +784,12 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;
 		StackType_t *pxStack;
 
 			/* Allocate space for the stack used by the task being created. */
-			pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+			pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
 
 			if( pxStack != NULL )
 			{
 				/* Allocate space for the TCB. */
-				pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e961 MISRA exception as the casts are only redundant for some paths. */
+				pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
 
 				if( pxNewTCB != NULL )
 				{
@@ -741,7 +812,7 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;
 
 		if( pxNewTCB != NULL )
 		{
-			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
 			{
 				/* Tasks can be created statically or dynamically, so note this
 				task was created dynamically in case it is later deleted. */
@@ -765,13 +836,13 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;
 /*-----------------------------------------------------------*/
 
 static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
-									const char * const pcName,
+									const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
 									const uint32_t ulStackDepth,
 									void * const pvParameters,
 									UBaseType_t uxPriority,
 									TaskHandle_t * const pxCreatedTask,
 									TCB_t *pxNewTCB,
-									const MemoryRegion_t * const xRegions ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const MemoryRegion_t * const xRegions )
 {
 StackType_t *pxTopOfStack;
 UBaseType_t x;
@@ -790,13 +861,15 @@ UBaseType_t x;
 		uxPriority &= ~portPRIVILEGE_BIT;
 	#endif /* portUSING_MPU_WRAPPERS == 1 */
 
+	configASSERT( pcName );
+
 	/* Avoid dependency on memset() if it is not required. */
-	#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )
+	#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
 	{
 		/* Fill the stack with a known value to assist debugging. */
 		( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
 	}
-	#endif /* ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) ) ) */
+	#endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */
 
 	/* Calculate the top of stack address.  This depends on whether the stack
 	grows from high memory to low (as per the 80x86) or vice versa.
@@ -804,11 +877,19 @@ UBaseType_t x;
 	by the port. */
 	#if( portSTACK_GROWTH < 0 )
 	{
-		pxTopOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
-		pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type. */
+		pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
+		pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type.  Checked by assert(). */
 
 		/* Check the alignment of the calculated top of stack is correct. */
 		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+		#if( configRECORD_STACK_HIGH_ADDRESS == 1 )
+		{
+			/* Also record the stack's high address, which may assist
+			debugging. */
+			pxNewTCB->pxEndOfStack = pxTopOfStack;
+		}
+		#endif /* configRECORD_STACK_HIGH_ADDRESS */
 	}
 	#else /* portSTACK_GROWTH */
 	{
@@ -831,7 +912,7 @@ UBaseType_t x;
 		/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
 		configMAX_TASK_NAME_LEN characters just in case the memory after the
 		string is not accessible (extremely unlikely). */
-		if( pcName[ x ] == 0x00 )
+		if( pcName[ x ] == ( char ) 0x00 )
 		{
 			break;
 		}
@@ -936,7 +1017,7 @@ UBaseType_t x;
 	/* Initialize the TCB stack to look as if the task was already running,
 	but had been interrupted by the scheduler.  The return address is set
 	to the start of the task function. Once the stack has been initialised
-	the	top of stack variable is updated. */
+	the top of stack variable is updated. */
 	#if( portUSING_MPU_WRAPPERS == 1 )
 	{
 		pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );
@@ -947,7 +1028,7 @@ UBaseType_t x;
 	}
 	#endif /* portUSING_MPU_WRAPPERS */
 
-	if( ( void * ) pxCreatedTask != NULL )
+	if( pxCreatedTask != NULL )
 	{
 		/* Pass the handle out in an anonymous way.  The handle can be used to
 		change the created task's priority, delete the created task, etc.*/
@@ -1269,8 +1350,8 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
 	eTaskState eTaskGetState( TaskHandle_t xTask )
 	{
 	eTaskState eReturn;
-	List_t *pxStateList;
-	const TCB_t * const pxTCB = ( TCB_t * ) xTask;
+	List_t const * pxStateList, *pxDelayedList, *pxOverflowedDelayedList;
+	const TCB_t * const pxTCB = xTask;
 
 		configASSERT( pxTCB );
 
@@ -1283,11 +1364,13 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
 		{
 			taskENTER_CRITICAL();
 			{
-				pxStateList = ( List_t * ) listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) );
+				pxStateList = listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) );
+				pxDelayedList = pxDelayedTaskList;
+				pxOverflowedDelayedList = pxOverflowDelayedTaskList;
 			}
 			taskEXIT_CRITICAL();
 
-			if( ( pxStateList == pxDelayedTaskList ) || ( pxStateList == pxOverflowDelayedTaskList ) )
+			if( ( pxStateList == pxDelayedList ) || ( pxStateList == pxOverflowedDelayedList ) )
 			{
 				/* The task being queried is referenced from one of the Blocked
 				lists. */
@@ -1298,11 +1381,30 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
 				else if( pxStateList == &xSuspendedTaskList )
 				{
 					/* The task being queried is referenced from the suspended
-					list.  Is it genuinely suspended or is it block
+					list.  Is it genuinely suspended or is it blocked
 					indefinitely? */
 					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )
 					{
-						eReturn = eSuspended;
+						#if( configUSE_TASK_NOTIFICATIONS == 1 )
+						{
+							/* The task does not appear on the event list item of
+							and of the RTOS objects, but could still be in the
+							blocked state if it is waiting on its notification
+							rather than waiting on an object. */
+							if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
+							{
+								eReturn = eBlocked;
+							}
+							else
+							{
+								eReturn = eSuspended;
+							}
+						}
+						#else
+						{
+							eReturn = eSuspended;
+						}
+						#endif
 					}
 					else
 					{
@@ -1337,15 +1439,15 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
 
 #if ( INCLUDE_uxTaskPriorityGet == 1 )
 
-	UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask )
+	UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask )
 	{
-	TCB_t *pxTCB;
+	TCB_t const *pxTCB;
 	UBaseType_t uxReturn;
 
 		taskENTER_CRITICAL();
 		{
-			/* If null is passed in here then it is the priority of the that
-			called uxTaskPriorityGet() that is being queried. */
+			/* If null is passed in here then it is the priority of the task
+			that called uxTaskPriorityGet() that is being queried. */
 			pxTCB = prvGetTCBFromHandle( xTask );
 			uxReturn = pxTCB->uxPriority;
 		}
@@ -1359,9 +1461,9 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
 
 #if ( INCLUDE_uxTaskPriorityGet == 1 )
 
-	UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask )
+	UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask )
 	{
-	TCB_t *pxTCB;
+	TCB_t const *pxTCB;
 	UBaseType_t uxReturn, uxSavedInterruptState;
 
 		/* RTOS ports that support interrupt nesting have the concept of a
@@ -1379,7 +1481,7 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
 		separate interrupt safe API to ensure interrupt entry is as fast and as
 		simple as possible.  More information (albeit Cortex-M specific) is
 		provided on the following link:
-		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		https://www.freertos.org/RTOS-Cortex-M3-M4.html */
 		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 
 		uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR();
@@ -1515,14 +1617,14 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
 				}
 
 				/* If the task is in the blocked or suspended list we need do
-				nothing more than change it's priority variable. However, if
+				nothing more than change its priority variable. However, if
 				the task is in a ready list it needs to be removed and placed
 				in the list appropriate to its new priority. */
 				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
 				{
-					/* The task is currently in its ready list - remove before adding
-					it to it's new ready list.  As we are in a critical section we
-					can do this even if the scheduler is suspended. */
+					/* The task is currently in its ready list - remove before
+					adding it to it's new ready list.  As we are in a critical
+					section we can do this even if the scheduler is suspended. */
 					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
 					{
 						/* It is known that the task is in its ready list so
@@ -1597,6 +1699,17 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
 			}
 
 			vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xStateListItem ) );
+
+			#if( configUSE_TASK_NOTIFICATIONS == 1 )
+			{
+				if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
+				{
+					/* The task was blocked to wait for a notification, but is
+					now suspended, so no notification was received. */
+					pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+				}
+			}
+			#endif
 		}
 		taskEXIT_CRITICAL();
 
@@ -1628,7 +1741,7 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
 				/* The scheduler is not running, but the task that was pointed
 				to by pxCurrentTCB has just been suspended and pxCurrentTCB
 				must be adjusted to point to a different task. */
-				if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks )
+				if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */
 				{
 					/* No other tasks are ready, so set pxCurrentTCB back to
 					NULL so when the next task is created pxCurrentTCB will
@@ -1656,7 +1769,7 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
 	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )
 	{
 	BaseType_t xReturn = pdFALSE;
-	const TCB_t * const pxTCB = ( TCB_t * ) xTask;
+	const TCB_t * const pxTCB = xTask;
 
 		/* Accesses xPendingReadyList so must be called from a critical
 		section. */
@@ -1672,7 +1785,7 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
 			{
 				/* Is it in the suspended list because it is in the	Suspended
 				state, or because is is blocked with no timeout? */
-				if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE )
+				if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) /*lint !e961.  The cast is only redundant when NULL is used. */
 				{
 					xReturn = pdTRUE;
 				}
@@ -1701,14 +1814,14 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
 
 	void vTaskResume( TaskHandle_t xTaskToResume )
 	{
-	TCB_t * const pxTCB = ( TCB_t * ) xTaskToResume;
+	TCB_t * const pxTCB = xTaskToResume;
 
 		/* It does not make sense to resume the calling task. */
 		configASSERT( xTaskToResume );
 
 		/* The parameter cannot be NULL as it is impossible to resume the
 		currently executing task. */
-		if( ( pxTCB != NULL ) && ( pxTCB != pxCurrentTCB ) )
+		if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) )
 		{
 			taskENTER_CRITICAL();
 			{
@@ -1716,12 +1829,12 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
 				{
 					traceTASK_RESUME( pxTCB );
 
-					/* As we are in a critical section we can access the ready
-					lists even if the scheduler is suspended. */
+					/* The ready list can be accessed even if the scheduler is
+					suspended because this is inside a critical section. */
 					( void ) uxListRemove(  &( pxTCB->xStateListItem ) );
 					prvAddTaskToReadyList( pxTCB );
 
-					/* We may have just resumed a higher priority task. */
+					/* A higher priority task may have just been resumed. */
 					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
 					{
 						/* This yield may not cause the task just resumed to run,
@@ -1756,7 +1869,7 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
 	BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )
 	{
 	BaseType_t xYieldRequired = pdFALSE;
-	TCB_t * const pxTCB = ( TCB_t * ) xTaskToResume;
+	TCB_t * const pxTCB = xTaskToResume;
 	UBaseType_t uxSavedInterruptStatus;
 
 		configASSERT( xTaskToResume );
@@ -1776,7 +1889,7 @@ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
 		separate interrupt safe API to ensure interrupt entry is as fast and as
 		simple as possible.  More information (albeit Cortex-M specific) is
 		provided on the following link:
-		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		https://www.freertos.org/RTOS-Cortex-M3-M4.html */
 		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 
 		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
@@ -1838,10 +1951,10 @@ BaseType_t xReturn;
 		address of the RAM then create the idle task. */
 		vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
 		xIdleTaskHandle = xTaskCreateStatic(	prvIdleTask,
-												"IDLE",
+												configIDLE_TASK_NAME,
 												ulIdleTaskStackSize,
-												( void * ) NULL,
-												( tskIDLE_PRIORITY | portPRIVILEGE_BIT ),
+												( void * ) NULL, /*lint !e961.  The cast is not redundant for all compilers. */
+												portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
 												pxIdleTaskStackBuffer,
 												pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
 
@@ -1858,9 +1971,10 @@ BaseType_t xReturn;
 	{
 		/* The Idle task is being created using dynamically allocated RAM. */
 		xReturn = xTaskCreate(	prvIdleTask,
-								"IDLE", configMINIMAL_STACK_SIZE,
+								configIDLE_TASK_NAME,
+								configMINIMAL_STACK_SIZE,
 								( void * ) NULL,
-								( tskIDLE_PRIORITY | portPRIVILEGE_BIT ),
+								portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
 								&xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
 	}
 	#endif /* configSUPPORT_STATIC_ALLOCATION */
@@ -1880,6 +1994,15 @@ BaseType_t xReturn;
 
 	if( xReturn == pdPASS )
 	{
+		/* freertos_tasks_c_additions_init() should only be called if the user
+		definable macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is
+		the only macro called by the function. */
+		#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+		{
+			freertos_tasks_c_additions_init();
+		}
+		#endif
+
 		/* Interrupts are turned off here, to ensure a tick does not occur
 		before or during the call to xPortStartScheduler().  The stacks of
 		the created tasks contain a status word with interrupts switched on
@@ -1897,13 +2020,18 @@ BaseType_t xReturn;
 
 		xNextTaskUnblockTime = portMAX_DELAY;
 		xSchedulerRunning = pdTRUE;
-		xTickCount = ( TickType_t ) 0U;
+		xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
 
 		/* If configGENERATE_RUN_TIME_STATS is defined then the following
 		macro must be defined to configure the timer/counter used to generate
-		the run time counter time base. */
+		the run time counter time base.   NOTE:  If configGENERATE_RUN_TIME_STATS
+		is set to 0 and the following line fails to build then ensure you do not
+		have portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() defined in your
+		FreeRTOSConfig.h file. */
 		portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();
 
+		traceTASK_SWITCHED_IN();
+
 		/* Setting up the timer tick is hardware specific and thus in the
 		portable interface. */
 		if( xPortStartScheduler() != pdFALSE )
@@ -2040,7 +2168,7 @@ BaseType_t xAlreadyYielded = pdFALSE;
 				appropriate ready list. */
 				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
 				{
-					pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) );
+					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 					( void ) uxListRemove( &( pxTCB->xEventListItem ) );
 					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
 					prvAddTaskToReadyList( pxTCB );
@@ -2157,7 +2285,7 @@ UBaseType_t uxSavedInterruptStatus;
 	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
 	safe API to ensure interrupt entry is as fast and as simple as possible.
 	More information (albeit Cortex-M specific) is provided on the following
-	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	link: https://www.freertos.org/RTOS-Cortex-M3-M4.html */
 	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 
 	uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();
@@ -2197,19 +2325,21 @@ TCB_t *pxTCB;
 	TCB_t *pxNextTCB, *pxFirstTCB, *pxReturn = NULL;
 	UBaseType_t x;
 	char cNextChar;
+	BaseType_t xBreakLoop;
 
 		/* This function is called with the scheduler suspended. */
 
 		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
 		{
-			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );
+			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );  /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 
 			do
 			{
-				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );
+				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 
 				/* Check each character in the name looking for a match or
 				mismatch. */
+				xBreakLoop = pdFALSE;
 				for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
 				{
 					cNextChar = pxNextTCB->pcTaskName[ x ];
@@ -2217,19 +2347,24 @@ TCB_t *pxTCB;
 					if( cNextChar != pcNameToQuery[ x ] )
 					{
 						/* Characters didn't match. */
-						break;
+						xBreakLoop = pdTRUE;
 					}
-					else if( cNextChar == 0x00 )
+					else if( cNextChar == ( char ) 0x00 )
 					{
 						/* Both strings terminated, a match must have been
 						found. */
 						pxReturn = pxNextTCB;
-						break;
+						xBreakLoop = pdTRUE;
 					}
 					else
 					{
 						mtCOVERAGE_TEST_MARKER();
 					}
+
+					if( xBreakLoop != pdFALSE )
+					{
+						break;
+					}
 				}
 
 				if( pxReturn != NULL )
@@ -2310,7 +2445,7 @@ TCB_t *pxTCB;
 		}
 		( void ) xTaskResumeAll();
 
-		return ( TaskHandle_t ) pxTCB;
+		return pxTCB;
 	}
 
 #endif /* INCLUDE_xTaskGetHandle */
@@ -2426,8 +2561,8 @@ implementations require configUSE_TICKLESS_IDLE to be set to a value other than
 
 	BaseType_t xTaskAbortDelay( TaskHandle_t xTask )
 	{
-	TCB_t *pxTCB = ( TCB_t * ) xTask;
-	BaseType_t xReturn = pdFALSE;
+	TCB_t *pxTCB = xTask;
+	BaseType_t xReturn;
 
 		configASSERT( pxTCB );
 
@@ -2437,6 +2572,8 @@ implementations require configUSE_TICKLESS_IDLE to be set to a value other than
 			it is actually in the Blocked state. */
 			if( eTaskGetState( xTask ) == eBlocked )
 			{
+				xReturn = pdPASS;
+
 				/* Remove the reference to the task from the blocked list.  An
 				interrupt won't touch the xStateListItem because the
 				scheduler is suspended. */
@@ -2485,10 +2622,10 @@ implementations require configUSE_TICKLESS_IDLE to be set to a value other than
 			}
 			else
 			{
-				mtCOVERAGE_TEST_MARKER();
+				xReturn = pdFAIL;
 			}
 		}
-		xTaskResumeAll();
+		( void ) xTaskResumeAll();
 
 		return xReturn;
 	}
@@ -2510,13 +2647,13 @@ BaseType_t xSwitchRequired = pdFALSE;
 	{
 		/* Minor optimisation.  The tick count cannot change in this
 		block. */
-		const TickType_t xConstTickCount = xTickCount + 1;
+		const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
 
 		/* Increment the RTOS tick, switching the delayed and overflowed
 		delayed lists if it wraps to 0. */
 		xTickCount = xConstTickCount;
 
-		if( xConstTickCount == ( TickType_t ) 0U )
+		if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
 		{
 			taskSWITCH_DELAYED_LISTS();
 		}
@@ -2549,7 +2686,7 @@ BaseType_t xSwitchRequired = pdFALSE;
 					item at the head of the delayed list.  This is the time
 					at which the task at the head of the delayed list must
 					be removed from the Blocked state. */
-					pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );
+					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 					xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
 
 					if( xConstTickCount < xItemValue )
@@ -2560,7 +2697,7 @@ BaseType_t xSwitchRequired = pdFALSE;
 						state -	so record the item value in
 						xNextTaskUnblockTime. */
 						xNextTaskUnblockTime = xItemValue;
-						break;
+						break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
 					}
 					else
 					{
@@ -2682,13 +2819,15 @@ BaseType_t xSwitchRequired = pdFALSE;
 		}
 		else
 		{
-			xTCB = ( TCB_t * ) xTask;
+			xTCB = xTask;
 		}
 
 		/* Save the hook function in the TCB.  A critical section is required as
 		the value can be accessed from an interrupt. */
 		taskENTER_CRITICAL();
+		{
 			xTCB->pxTaskTag = pxHookFunction;
+		}
 		taskEXIT_CRITICAL();
 	}
 
@@ -2709,7 +2848,7 @@ BaseType_t xSwitchRequired = pdFALSE;
 		}
 		else
 		{
-			xTCB = ( TCB_t * ) xTask;
+			xTCB = xTask;
 		}
 
 		/* Save the hook function in the TCB.  A critical section is required as
@@ -2736,11 +2875,11 @@ BaseType_t xSwitchRequired = pdFALSE;
 		/* If xTask is NULL then we are calling our own task hook. */
 		if( xTask == NULL )
 		{
-			xTCB = ( TCB_t * ) pxCurrentTCB;
+			xTCB = pxCurrentTCB;
 		}
 		else
 		{
-			xTCB = ( TCB_t * ) xTask;
+			xTCB = xTask;
 		}
 
 		if( xTCB->pxTaskTag != NULL )
@@ -2801,11 +2940,25 @@ void vTaskSwitchContext( void )
 		/* Check for stack overflow, if configured. */
 		taskCHECK_FOR_STACK_OVERFLOW();
 
+		/* Before the currently running task is switched out, save its errno. */
+		#if( configUSE_POSIX_ERRNO == 1 )
+		{
+			pxCurrentTCB->iTaskErrno = FreeRTOS_errno;
+		}
+		#endif
+
 		/* Select a new task to run using either the generic C or port
 		optimised asm code. */
-		taskSELECT_HIGHEST_PRIORITY_TASK();
+		taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 		traceTASK_SWITCHED_IN();
 
+		/* After the new task is switched in, update the global errno. */
+		#if( configUSE_POSIX_ERRNO == 1 )
+		{
+			FreeRTOS_errno = pxCurrentTCB->iTaskErrno;
+		}
+		#endif
+
 		#if ( configUSE_NEWLIB_REENTRANT == 1 )
 		{
 			/* Switch Newlib's _impure_ptr variable to point to the _reent
@@ -2909,7 +3062,7 @@ BaseType_t xReturn;
 
 	This function assumes that a check has already been made to ensure that
 	pxEventList is not empty. */
-	pxUnblockedTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
+	pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 	configASSERT( pxUnblockedTCB );
 	( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
 
@@ -2959,10 +3112,9 @@ BaseType_t xReturn;
 }
 /*-----------------------------------------------------------*/
 
-BaseType_t xTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue )
+void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue )
 {
 TCB_t *pxUnblockedTCB;
-BaseType_t xReturn;
 
 	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
 	the event flags implementation. */
@@ -2973,7 +3125,7 @@ BaseType_t xReturn;
 
 	/* Remove the event list form the event flag.  Interrupts do not access
 	event flags. */
-	pxUnblockedTCB = ( TCB_t * ) listGET_LIST_ITEM_OWNER( pxEventListItem );
+	pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 	configASSERT( pxUnblockedTCB );
 	( void ) uxListRemove( pxEventListItem );
 
@@ -2985,28 +3137,30 @@ BaseType_t xReturn;
 
 	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
 	{
-		/* Return true if the task removed from the event list has
-		a higher priority than the calling task.  This allows
-		the calling task to know if it should force a context
-		switch now. */
-		xReturn = pdTRUE;
-
-		/* Mark that a yield is pending in case the user is not using the
-		"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
+		/* The unblocked task has a priority above that of the calling task, so
+		a context switch is required.  This function is called with the
+		scheduler suspended so xYieldPending is set so the context switch
+		occurs immediately that the scheduler is resumed (unsuspended). */
 		xYieldPending = pdTRUE;
 	}
-	else
-	{
-		xReturn = pdFALSE;
-	}
-
-	return xReturn;
 }
 /*-----------------------------------------------------------*/
 
 void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
 {
 	configASSERT( pxTimeOut );
+	taskENTER_CRITICAL();
+	{
+		pxTimeOut->xOverflowCount = xNumOfOverflows;
+		pxTimeOut->xTimeOnEntering = xTickCount;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+	/* For internal use only as it does not use a critical section. */
 	pxTimeOut->xOverflowCount = xNumOfOverflows;
 	pxTimeOut->xTimeOnEntering = xTickCount;
 }
@@ -3023,9 +3177,10 @@ BaseType_t xReturn;
 	{
 		/* Minor optimisation.  The tick count cannot change in this block. */
 		const TickType_t xConstTickCount = xTickCount;
+		const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
 
 		#if( INCLUDE_xTaskAbortDelay == 1 )
-			if( pxCurrentTCB->ucDelayAborted != pdFALSE )
+			if( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE )
 			{
 				/* The delay was aborted, which is not the same as a time out,
 				but has the same result. */
@@ -3055,15 +3210,16 @@ BaseType_t xReturn;
 			was called. */
 			xReturn = pdTRUE;
 		}
-		else if( ( ( TickType_t ) ( xConstTickCount - pxTimeOut->xTimeOnEntering ) ) < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
+		else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
 		{
 			/* Not a genuine timeout. Adjust parameters for time remaining. */
-			*pxTicksToWait -= ( xConstTickCount - pxTimeOut->xTimeOnEntering );
-			vTaskSetTimeOutState( pxTimeOut );
+			*pxTicksToWait -= xElapsedTime;
+			vTaskInternalSetTimeOutState( pxTimeOut );
 			xReturn = pdFALSE;
 		}
 		else
 		{
+			*pxTicksToWait = 0;
 			xReturn = pdTRUE;
 		}
 	}
@@ -3084,11 +3240,11 @@ void vTaskMissedYield( void )
 	UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )
 	{
 	UBaseType_t uxReturn;
-	TCB_t *pxTCB;
+	TCB_t const *pxTCB;
 
 		if( xTask != NULL )
 		{
-			pxTCB = ( TCB_t * ) xTask;
+			pxTCB = xTask;
 			uxReturn = pxTCB->uxTaskNumber;
 		}
 		else
@@ -3106,11 +3262,11 @@ void vTaskMissedYield( void )
 
 	void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle )
 	{
-	TCB_t *pxTCB;
+	TCB_t * pxTCB;
 
 		if( xTask != NULL )
 		{
-			pxTCB = ( TCB_t * ) xTask;
+			pxTCB = xTask;
 			pxTCB->uxTaskNumber = uxHandle;
 		}
 	}
@@ -3136,6 +3292,11 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
 	/** THIS IS THE RTOS IDLE TASK - WHICH IS CREATED AUTOMATICALLY WHEN THE
 	SCHEDULER IS STARTED. **/
 
+	/* In case a task that has a secure context deletes itself, in which case
+	the idle task is responsible for deleting the task's secure context, if
+	any. */
+	portTASK_CALLS_SECURE_FUNCTIONS();
+
 	for( ;; )
 	{
 		/* See if any tasks have deleted themselves - if so then the idle task
@@ -3212,6 +3373,11 @@ static portTASK_FUNCTION( prvIdleTask, pvParameters )
 					configASSERT( xNextTaskUnblockTime >= xTickCount );
 					xExpectedIdleTime = prvGetExpectedIdleTime();
 
+					/* Define the following macro to set xExpectedIdleTime to 0
+					if the application does not want
+					portSUPPRESS_TICKS_AND_SLEEP() to be called. */
+					configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime );
+
 					if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
 					{
 						traceLOW_POWER_IDLE_BEGIN();
@@ -3369,37 +3535,22 @@ static void prvCheckTasksWaitingTermination( void )
 
 	#if ( INCLUDE_vTaskDelete == 1 )
 	{
-		BaseType_t xListIsEmpty;
+		TCB_t *pxTCB;
 
-		/* ucTasksDeleted is used to prevent vTaskSuspendAll() being called
-		too often in the idle task. */
+		/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
+		being called too often in the idle task. */
 		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
 		{
-			vTaskSuspendAll();
+			taskENTER_CRITICAL();
 			{
-				xListIsEmpty = listLIST_IS_EMPTY( &xTasksWaitingTermination );
+				pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+				--uxCurrentNumberOfTasks;
+				--uxDeletedTasksWaitingCleanUp;
 			}
-			( void ) xTaskResumeAll();
-
-			if( xListIsEmpty == pdFALSE )
-			{
-				TCB_t *pxTCB;
-
-				taskENTER_CRITICAL();
-				{
-					pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) );
-					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
-					--uxCurrentNumberOfTasks;
-					--uxDeletedTasksWaitingCleanUp;
-				}
-				taskEXIT_CRITICAL();
+			taskEXIT_CRITICAL();
 
-				prvDeleteTCB( pxTCB );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
+			prvDeleteTCB( pxTCB );
 		}
 	}
 	#endif /* INCLUDE_vTaskDelete */
@@ -3421,25 +3572,6 @@ static void prvCheckTasksWaitingTermination( void )
 		pxTaskStatus->pxStackBase = pxTCB->pxStack;
 		pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber;
 
-		#if ( INCLUDE_vTaskSuspend == 1 )
-		{
-			/* If the task is in the suspended list then there is a chance it is
-			actually just blocked indefinitely - so really it should be reported as
-			being in the Blocked state. */
-			if( pxTaskStatus->eCurrentState == eSuspended )
-			{
-				vTaskSuspendAll();
-				{
-					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
-					{
-						pxTaskStatus->eCurrentState = eBlocked;
-					}
-				}
-				xTaskResumeAll();
-			}
-		}
-		#endif /* INCLUDE_vTaskSuspend */
-
 		#if ( configUSE_MUTEXES == 1 )
 		{
 			pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority;
@@ -3460,16 +3592,42 @@ static void prvCheckTasksWaitingTermination( void )
 		}
 		#endif
 
-		/* Obtaining the task state is a little fiddly, so is only done if the value
-		of eState passed into this function is eInvalid - otherwise the state is
-		just set to whatever is passed in. */
+		/* Obtaining the task state is a little fiddly, so is only done if the
+		value of eState passed into this function is eInvalid - otherwise the
+		state is just set to whatever is passed in. */
 		if( eState != eInvalid )
 		{
-			pxTaskStatus->eCurrentState = eState;
+			if( pxTCB == pxCurrentTCB )
+			{
+				pxTaskStatus->eCurrentState = eRunning;
+			}
+			else
+			{
+				pxTaskStatus->eCurrentState = eState;
+
+				#if ( INCLUDE_vTaskSuspend == 1 )
+				{
+					/* If the task is in the suspended list then there is a
+					chance it is actually just blocked indefinitely - so really
+					it should be reported as being in the Blocked state. */
+					if( eState == eSuspended )
+					{
+						vTaskSuspendAll();
+						{
+							if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+							{
+								pxTaskStatus->eCurrentState = eBlocked;
+							}
+						}
+						( void ) xTaskResumeAll();
+					}
+				}
+				#endif /* INCLUDE_vTaskSuspend */
+			}
 		}
 		else
 		{
-			pxTaskStatus->eCurrentState = eTaskGetState( xTask );
+			pxTaskStatus->eCurrentState = eTaskGetState( pxTCB );
 		}
 
 		/* Obtaining the stack space takes some time, so the xGetFreeStackSpace
@@ -3499,12 +3657,12 @@ static void prvCheckTasksWaitingTermination( void )
 
 	static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState )
 	{
-	volatile TCB_t *pxNextTCB, *pxFirstTCB;
+	configLIST_VOLATILE TCB_t *pxNextTCB, *pxFirstTCB;
 	UBaseType_t uxTask = 0;
 
 		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
 		{
-			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );
+			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 
 			/* Populate an TaskStatus_t structure within the
 			pxTaskStatusArray array for each task that is referenced from
@@ -3512,7 +3670,7 @@ static void prvCheckTasksWaitingTermination( void )
 			meaning of each TaskStatus_t structure member. */
 			do
 			{
-				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );
+				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 				vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );
 				uxTask++;
 			} while( pxNextTCB != pxFirstTCB );
@@ -3530,7 +3688,7 @@ static void prvCheckTasksWaitingTermination( void )
 
 #if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )
 
-	static uint16_t prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
+	static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
 	{
 	uint32_t ulCount = 0U;
 
@@ -3542,7 +3700,7 @@ static void prvCheckTasksWaitingTermination( void )
 
 		ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */
 
-		return ( uint16_t ) ulCount;
+		return ( configSTACK_DEPTH_TYPE ) ulCount;
 	}
 
 #endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) ) */
@@ -3600,7 +3758,7 @@ static void prvCheckTasksWaitingTermination( void )
 			vPortFree( pxTCB->pxStack );
 			vPortFree( pxTCB );
 		}
-		#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE == 1 )
+		#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
 		{
 			/* The task could have been allocated statically or dynamically, so
 			check what was statically allocated before trying to free the
@@ -3622,7 +3780,7 @@ static void prvCheckTasksWaitingTermination( void )
 			{
 				/* Neither the stack nor the TCB were allocated dynamically, so
 				nothing needs to be freed. */
-				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	)
+				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
 				mtCOVERAGE_TEST_MARKER();
 			}
 		}
@@ -3650,7 +3808,7 @@ TCB_t *pxTCB;
 		the item at the head of the delayed list.  This is the time at
 		which the task at the head of the delayed list should be removed
 		from the Blocked state. */
-		( pxTCB ) = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );
+		( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
 	}
 }
@@ -3703,25 +3861,27 @@ TCB_t *pxTCB;
 
 #if ( configUSE_MUTEXES == 1 )
 
-	void vTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
+	BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
 	{
-	TCB_t * const pxTCB = ( TCB_t * ) pxMutexHolder;
+	TCB_t * const pxMutexHolderTCB = pxMutexHolder;
+	BaseType_t xReturn = pdFALSE;
 
 		/* If the mutex was given back by an interrupt while the queue was
-		locked then the mutex holder might now be NULL. */
+		locked then the mutex holder might now be NULL.  _RB_ Is this still
+		needed as interrupts can no longer use mutexes? */
 		if( pxMutexHolder != NULL )
 		{
 			/* If the holder of the mutex has a priority below the priority of
 			the task attempting to obtain the mutex then it will temporarily
 			inherit the priority of the task attempting to obtain the mutex. */
-			if( pxTCB->uxPriority < pxCurrentTCB->uxPriority )
+			if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
 			{
 				/* Adjust the mutex holder state to account for its new
 				priority.  Only reset the event list item value if the value is
-				not	being used for anything else. */
-				if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+				not being used for anything else. */
+				if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
 				{
-					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 				}
 				else
 				{
@@ -3730,11 +3890,11 @@ TCB_t *pxTCB;
 
 				/* If the task being modified is in the ready state it will need
 				to be moved into a new list. */
-				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxTCB->uxPriority ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
 				{
-					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
 					{
-						taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+						taskRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority );
 					}
 					else
 					{
@@ -3742,26 +3902,45 @@ TCB_t *pxTCB;
 					}
 
 					/* Inherit the priority before being moved into the new list. */
-					pxTCB->uxPriority = pxCurrentTCB->uxPriority;
-					prvAddTaskToReadyList( pxTCB );
+					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+					prvAddTaskToReadyList( pxMutexHolderTCB );
 				}
 				else
 				{
 					/* Just inherit the priority. */
-					pxTCB->uxPriority = pxCurrentTCB->uxPriority;
+					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
 				}
 
-				traceTASK_PRIORITY_INHERIT( pxTCB, pxCurrentTCB->uxPriority );
+				traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );
+
+				/* Inheritance occurred. */
+				xReturn = pdTRUE;
 			}
 			else
 			{
-				mtCOVERAGE_TEST_MARKER();
+				if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
+				{
+					/* The base priority of the mutex holder is lower than the
+					priority of the task attempting to take the mutex, but the
+					current priority of the mutex holder is not lower than the
+					priority of the task attempting to take the mutex.
+					Therefore the mutex holder must have already inherited a
+					priority, but inheritance would have occurred if that had
+					not been the case. */
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
 			}
 		}
 		else
 		{
 			mtCOVERAGE_TEST_MARKER();
 		}
+
+		return xReturn;
 	}
 
 #endif /* configUSE_MUTEXES */
@@ -3771,7 +3950,7 @@ TCB_t *pxTCB;
 
 	BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
 	{
-	TCB_t * const pxTCB = ( TCB_t * ) pxMutexHolder;
+	TCB_t * const pxTCB = pxMutexHolder;
 	BaseType_t xReturn = pdFALSE;
 
 		if( pxMutexHolder != NULL )
@@ -3781,7 +3960,6 @@ TCB_t *pxTCB;
 			interrupt, and if a mutex is given by the holding task then it must
 			be the running state task. */
 			configASSERT( pxTCB == pxCurrentTCB );
-
 			configASSERT( pxTCB->uxMutexesHeld );
 			( pxTCB->uxMutexesHeld )--;
 
@@ -3795,8 +3973,8 @@ TCB_t *pxTCB;
 					/* A task can only have an inherited priority if it holds
 					the mutex.  If the mutex is held by a task then it cannot be
 					given from an interrupt, and if a mutex is given by the
-					holding	task then it must be the running state task.  Remove
-					the	holding task from the ready	list. */
+					holding task then it must be the running state task.  Remove
+					the holding task from the ready list. */
 					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
 					{
 						taskRESET_READY_PRIORITY( pxTCB->uxPriority );
@@ -3848,6 +4026,108 @@ TCB_t *pxTCB;
 #endif /* configUSE_MUTEXES */
 /*-----------------------------------------------------------*/
 
+#if ( configUSE_MUTEXES == 1 )
+
+	void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask )
+	{
+	TCB_t * const pxTCB = pxMutexHolder;
+	UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
+	const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
+
+		if( pxMutexHolder != NULL )
+		{
+			/* If pxMutexHolder is not NULL then the holder must hold at least
+			one mutex. */
+			configASSERT( pxTCB->uxMutexesHeld );
+
+			/* Determine the priority to which the priority of the task that
+			holds the mutex should be set.  This will be the greater of the
+			holding task's base priority and the priority of the highest
+			priority task that is waiting to obtain the mutex. */
+			if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
+			{
+				uxPriorityToUse = uxHighestPriorityWaitingTask;
+			}
+			else
+			{
+				uxPriorityToUse = pxTCB->uxBasePriority;
+			}
+
+			/* Does the priority need to change? */
+			if( pxTCB->uxPriority != uxPriorityToUse )
+			{
+				/* Only disinherit if no other mutexes are held.  This is a
+				simplification in the priority inheritance implementation.  If
+				the task that holds the mutex is also holding other mutexes then
+				the other mutexes may have caused the priority inheritance. */
+				if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
+				{
+					/* If a task has timed out because it already holds the
+					mutex it was trying to obtain then it cannot of inherited
+					its own priority. */
+					configASSERT( pxTCB != pxCurrentTCB );
+
+					/* Disinherit the priority, remembering the previous
+					priority to facilitate determining the subject task's
+					state. */
+					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+					uxPriorityUsedOnEntry = pxTCB->uxPriority;
+					pxTCB->uxPriority = uxPriorityToUse;
+
+					/* Only reset the event list item value if the value is not
+					being used for anything else. */
+					if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+					{
+						listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* If the running task is not the task that holds the mutex
+					then the task that holds the mutex could be in either the
+					Ready, Blocked or Suspended states.  Only remove the task
+					from its current state list if it is in the Ready state as
+					the task's priority is going to change and there is one
+					Ready list per priority. */
+					if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+					{
+						if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+						{
+							taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+
+						prvAddTaskToReadyList( pxTCB );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
 #if ( portCRITICAL_NESTING_IN_TCB == 1 )
 
 	void vTaskEnterCritical( void )
@@ -3928,7 +4208,7 @@ TCB_t *pxTCB;
 		}
 
 		/* Terminate. */
-		pcBuffer[ x ] = 0x00;
+		pcBuffer[ x ] = ( char ) 0x00;
 
 		/* Return the new end of string. */
 		return &( pcBuffer[ x ] );
@@ -3937,12 +4217,12 @@ TCB_t *pxTCB;
 #endif /* ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
 
 	void vTaskList( char * pcWriteBuffer )
 	{
 	TaskStatus_t *pxTaskStatusArray;
-	volatile UBaseType_t uxArraySize, x;
+	UBaseType_t uxArraySize, x;
 	char cStatus;
 
 		/*
@@ -3971,7 +4251,7 @@ TCB_t *pxTCB;
 
 
 		/* Make sure the write buffer does not contain a string. */
-		*pcWriteBuffer = 0x00;
+		*pcWriteBuffer = ( char ) 0x00;
 
 		/* Take a snapshot of the number of tasks in case it changes while this
 		function is executing. */
@@ -3980,7 +4260,7 @@ TCB_t *pxTCB;
 		/* Allocate an array index for each task.  NOTE!  if
 		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
 		equate to NULL. */
-		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );
+		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
 
 		if( pxTaskStatusArray != NULL )
 		{
@@ -3992,6 +4272,9 @@ TCB_t *pxTCB;
 			{
 				switch( pxTaskStatusArray[ x ].eCurrentState )
 				{
+					case eRunning:		cStatus = tskRUNNING_CHAR;
+										break;
+
 					case eReady:		cStatus = tskREADY_CHAR;
 										break;
 
@@ -4004,9 +4287,10 @@ TCB_t *pxTCB;
 					case eDeleted:		cStatus = tskDELETED_CHAR;
 										break;
 
+					case eInvalid:		/* Fall through. */
 					default:			/* Should not get here, but it is included
 										to prevent static checking errors. */
-										cStatus = 0x00;
+										cStatus = ( char ) 0x00;
 										break;
 				}
 
@@ -4015,8 +4299,8 @@ TCB_t *pxTCB;
 				pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
 
 				/* Write the rest of the string. */
-				sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber );
-				pcWriteBuffer += strlen( pcWriteBuffer );
+				sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+				pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
 			}
 
 			/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
@@ -4029,15 +4313,15 @@ TCB_t *pxTCB;
 		}
 	}
 
-#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
 /*----------------------------------------------------------*/
 
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
 
 	void vTaskGetRunTimeStats( char *pcWriteBuffer )
 	{
 	TaskStatus_t *pxTaskStatusArray;
-	volatile UBaseType_t uxArraySize, x;
+	UBaseType_t uxArraySize, x;
 	uint32_t ulTotalTime, ulStatsAsPercentage;
 
 		#if( configUSE_TRACE_FACILITY != 1 )
@@ -4072,7 +4356,7 @@ TCB_t *pxTCB;
 		 */
 
 		/* Make sure the write buffer does not contain a string. */
-		*pcWriteBuffer = 0x00;
+		*pcWriteBuffer = ( char ) 0x00;
 
 		/* Take a snapshot of the number of tasks in case it changes while this
 		function is executing. */
@@ -4081,7 +4365,7 @@ TCB_t *pxTCB;
 		/* Allocate an array index for each task.  NOTE!  If
 		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
 		equate to NULL. */
-		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );
+		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
 
 		if( pxTaskStatusArray != NULL )
 		{
@@ -4092,7 +4376,7 @@ TCB_t *pxTCB;
 			ulTotalTime /= 100UL;
 
 			/* Avoid divide by zero errors. */
-			if( ulTotalTime > 0 )
+			if( ulTotalTime > 0UL )
 			{
 				/* Create a human readable table from the binary data. */
 				for( x = 0; x < uxArraySize; x++ )
@@ -4117,7 +4401,7 @@ TCB_t *pxTCB;
 						{
 							/* sizeof( int ) == sizeof( long ) so a smaller
 							printf() library can be used. */
-							sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage );
+							sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
 						}
 						#endif
 					}
@@ -4133,12 +4417,12 @@ TCB_t *pxTCB;
 						{
 							/* sizeof( int ) == sizeof( long ) so a smaller
 							printf() library can be used. */
-							sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter );
+							sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
 						}
 						#endif
 					}
 
-					pcWriteBuffer += strlen( pcWriteBuffer );
+					pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
 				}
 			}
 			else
@@ -4156,7 +4440,7 @@ TCB_t *pxTCB;
 		}
 	}
 
-#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */
+#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
 /*-----------------------------------------------------------*/
 
 TickType_t uxTaskResetEventItemValue( void )
@@ -4175,7 +4459,7 @@ TickType_t uxReturn;
 
 #if ( configUSE_MUTEXES == 1 )
 
-	void *pvTaskIncrementMutexHeldCount( void )
+	TaskHandle_t pvTaskIncrementMutexHeldCount( void )
 	{
 		/* If xSemaphoreCreateMutex() is called before any tasks have been created
 		then pxCurrentTCB will be NULL. */
@@ -4240,7 +4524,7 @@ TickType_t uxReturn;
 				}
 				else
 				{
-					pxCurrentTCB->ulNotifiedValue = ulReturn - 1;
+					pxCurrentTCB->ulNotifiedValue = ulReturn - ( uint32_t ) 1;
 				}
 			}
 			else
@@ -4315,7 +4599,7 @@ TickType_t uxReturn;
 			blocked state (because a notification was already pending) or the
 			task unblocked because of a notification.  Otherwise the task
 			unblocked because of a timeout. */
-			if( pxCurrentTCB->ucNotifyState == taskWAITING_NOTIFICATION )
+			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
 			{
 				/* A notification was not received. */
 				xReturn = pdFALSE;
@@ -4347,7 +4631,7 @@ TickType_t uxReturn;
 	uint8_t ucOriginalNotifyState;
 
 		configASSERT( xTaskToNotify );
-		pxTCB = ( TCB_t * ) xTaskToNotify;
+		pxTCB = xTaskToNotify;
 
 		taskENTER_CRITICAL();
 		{
@@ -4390,6 +4674,14 @@ TickType_t uxReturn;
 					/* The task is being notified without its notify value being
 					updated. */
 					break;
+
+				default:
+					/* Should not get here if all enums are handled.
+					Artificially force an assert by testing a value the
+					compiler can't assume is const. */
+					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
+
+					break;
 			}
 
 			traceTASK_NOTIFY();
@@ -4473,7 +4765,7 @@ TickType_t uxReturn;
 		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
 		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 
-		pxTCB = ( TCB_t * ) xTaskToNotify;
+		pxTCB = xTaskToNotify;
 
 		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
 		{
@@ -4515,6 +4807,13 @@ TickType_t uxReturn;
 					/* The task is being notified without its notify value being
 					updated. */
 					break;
+
+				default:
+					/* Should not get here if all enums are handled.
+					Artificially force an assert by testing a value the
+					compiler can't assume is const. */
+					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
+					break;
 			}
 
 			traceTASK_NOTIFY_FROM_ISR();
@@ -4546,13 +4845,11 @@ TickType_t uxReturn;
 					{
 						*pxHigherPriorityTaskWoken = pdTRUE;
 					}
-					else
-					{
-						/* Mark that a yield is pending in case the user is not
-						using the "xHigherPriorityTaskWoken" parameter to an ISR
-						safe FreeRTOS function. */
-						xYieldPending = pdTRUE;
-					}
+
+					/* Mark that a yield is pending in case the user is not
+					using the "xHigherPriorityTaskWoken" parameter to an ISR
+					safe FreeRTOS function. */
+					xYieldPending = pdTRUE;
 				}
 				else
 				{
@@ -4596,7 +4893,7 @@ TickType_t uxReturn;
 		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
 		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 
-		pxTCB = ( TCB_t * ) xTaskToNotify;
+		pxTCB = xTaskToNotify;
 
 		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
 		{
@@ -4636,13 +4933,11 @@ TickType_t uxReturn;
 					{
 						*pxHigherPriorityTaskWoken = pdTRUE;
 					}
-					else
-					{
-						/* Mark that a yield is pending in case the user is not
-						using the "xHigherPriorityTaskWoken" parameter in an ISR
-						safe FreeRTOS function. */
-						xYieldPending = pdTRUE;
-					}
+
+					/* Mark that a yield is pending in case the user is not
+					using the "xHigherPriorityTaskWoken" parameter in an ISR
+					safe FreeRTOS function. */
+					xYieldPending = pdTRUE;
 				}
 				else
 				{
@@ -4709,7 +5004,7 @@ const TickType_t xConstTickCount = xTickCount;
 	{
 		/* The current task must be in a ready list, so there is no need to
 		check, and the port reset macro can be called directly. */
-		portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );
+		portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task.  pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */
 	}
 	else
 	{
@@ -4800,8 +5095,26 @@ const TickType_t xConstTickCount = xTickCount;
 	#endif /* INCLUDE_vTaskSuspend */
 }
 
+/* Code below here allows additional code to be inserted into this source file,
+especially where access to file scope functions and data is needed (for example
+when performing module tests). */
 
 #ifdef FREERTOS_MODULE_TEST
 	#include "tasks_test_access_functions.h"
 #endif
 
+
+#if( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 )
+
+	#include "freertos_tasks_c_additions.h"
+
+	#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+		static void freertos_tasks_c_additions_init( void )
+		{
+			FREERTOS_TASKS_C_ADDITIONS_INIT();
+		}
+	#endif
+
+#endif
+
+
diff --git a/os/freertos/timers.c b/os/freertos/timers.c
index d4a821a26..3e9ac8137 100644
--- a/os/freertos/timers.c
+++ b/os/freertos/timers.c
@@ -1,71 +1,29 @@
 /*
-    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
-
-    ***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-    ***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-    the FAQ page "My application does not run, what could be wrong?".  Have you
-    defined configASSERT()?
-
-    http://www.FreeRTOS.org/support - In return for receiving this top quality
-    embedded software for free we request you assist our global community by
-    participating in the support forum.
-
-    http://www.FreeRTOS.org/training - Investing in training allows your team to
-    be as productive as possible as early as possible.  Now you can receive
-    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-    Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
+ * FreeRTOS Kernel V10.1.1
+ * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
 
 /* Standard includes. */
 #include 
@@ -84,11 +42,11 @@ task.h is included from an application file. */
 	#error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.
 #endif
 
-/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
-MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
-header files above, but not in this file, in order to generate the correct
-privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e9021 !e961 !e750. */
 
 
 /* This entire source file will be skipped if the application is not configured
@@ -100,8 +58,14 @@ configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
 /* Misc definitions. */
 #define tmrNO_DELAY		( TickType_t ) 0U
 
+/* The name assigned to the timer service task.  This can be overridden by
+defining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */
+#ifndef configTIMER_SERVICE_TASK_NAME
+	#define configTIMER_SERVICE_TASK_NAME "Tmr Svc"
+#endif
+
 /* The definition of the timers themselves. */
-typedef struct tmrTimerControl
+typedef struct tmrTimerControl /* The old naming convention is used to prevent breaking kernel aware debuggers. */
 {
 	const char				*pcTimerName;		/*<< Text name.  This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
 	ListItem_t				xTimerListItem;		/*<< Standard linked list item as used by all kernel features for event management. */
@@ -158,12 +122,15 @@ typedef struct tmrTimerQueueMessage
 	} u;
 } DaemonTaskMessage_t;
 
-/*lint -e956 A manual analysis and inspection has been used to determine which
-static variables must be declared volatile. */
+/*lint -save -e956 A manual analysis and inspection has been used to determine
+which static variables must be declared volatile. */
 
 /* The list in which active timers are stored.  Timers are referenced in expire
 time order, with the nearest expiry time at the front of the list.  Only the
-timer service task is allowed to access these lists. */
+timer service task is allowed to access these lists. 
+xActiveTimerList1 and xActiveTimerList2 could be at function scope but that
+breaks some kernel aware debuggers, and debuggers that reply on removing the
+static qualifier. */
 PRIVILEGED_DATA static List_t xActiveTimerList1;
 PRIVILEGED_DATA static List_t xActiveTimerList2;
 PRIVILEGED_DATA static List_t *pxCurrentTimerList;
@@ -173,7 +140,7 @@ PRIVILEGED_DATA static List_t *pxOverflowTimerList;
 PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;
 PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;
 
-/*lint +e956 */
+/*lint -restore */
 
 /*-----------------------------------------------------------*/
 
@@ -248,12 +215,12 @@ static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseTy
  * Called after a Timer_t structure has been allocated either statically or
  * dynamically to fill in the structure's members.
  */
-static void prvInitialiseNewTimer(	const char * const pcTimerName,
+static void prvInitialiseNewTimer(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
 									const TickType_t xTimerPeriodInTicks,
 									const UBaseType_t uxAutoReload,
 									void * const pvTimerID,
 									TimerCallbackFunction_t pxCallbackFunction,
-									Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION;
 /*-----------------------------------------------------------*/
 
 BaseType_t xTimerCreateTimerTask( void )
@@ -276,7 +243,7 @@ BaseType_t xReturn = pdFAIL;
 
 			vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
 			xTimerTaskHandle = xTaskCreateStatic(	prvTimerTask,
-													"Tmr Svc",
+													configTIMER_SERVICE_TASK_NAME,
 													ulTimerTaskStackSize,
 													NULL,
 													( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
@@ -291,7 +258,7 @@ BaseType_t xReturn = pdFAIL;
 		#else
 		{
 			xReturn = xTaskCreate(	prvTimerTask,
-									"Tmr Svc",
+									configTIMER_SERVICE_TASK_NAME,
 									configTIMER_TASK_STACK_DEPTH,
 									NULL,
 									( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
@@ -311,15 +278,15 @@ BaseType_t xReturn = pdFAIL;
 
 #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
 
-	TimerHandle_t xTimerCreate(	const char * const pcTimerName,
+	TimerHandle_t xTimerCreate(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
 								const TickType_t xTimerPeriodInTicks,
 								const UBaseType_t uxAutoReload,
 								void * const pvTimerID,
-								TimerCallbackFunction_t pxCallbackFunction ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+								TimerCallbackFunction_t pxCallbackFunction )
 	{
 	Timer_t *pxNewTimer;
 
-		pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) );
+		pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */
 
 		if( pxNewTimer != NULL )
 		{
@@ -343,12 +310,12 @@ BaseType_t xReturn = pdFAIL;
 
 #if( configSUPPORT_STATIC_ALLOCATION == 1 )
 
-	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,
+	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
 										const TickType_t xTimerPeriodInTicks,
 										const UBaseType_t uxAutoReload,
 										void * const pvTimerID,
 										TimerCallbackFunction_t pxCallbackFunction,
-										StaticTimer_t *pxTimerBuffer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+										StaticTimer_t *pxTimerBuffer )
 	{
 	Timer_t *pxNewTimer;
 
@@ -356,15 +323,16 @@ BaseType_t xReturn = pdFAIL;
 		{
 			/* Sanity check that the size of the structure used to declare a
 			variable of type StaticTimer_t equals the size of the real timer
-			structures. */
+			structure. */
 			volatile size_t xSize = sizeof( StaticTimer_t );
 			configASSERT( xSize == sizeof( Timer_t ) );
+			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
 		}
 		#endif /* configASSERT_DEFINED */
 
 		/* A pointer to a StaticTimer_t structure MUST be provided, use it. */
 		configASSERT( pxTimerBuffer );
-		pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+		pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */
 
 		if( pxNewTimer != NULL )
 		{
@@ -385,12 +353,12 @@ BaseType_t xReturn = pdFAIL;
 #endif /* configSUPPORT_STATIC_ALLOCATION */
 /*-----------------------------------------------------------*/
 
-static void prvInitialiseNewTimer(	const char * const pcTimerName,
+static void prvInitialiseNewTimer(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
 									const TickType_t xTimerPeriodInTicks,
 									const UBaseType_t uxAutoReload,
 									void * const pvTimerID,
 									TimerCallbackFunction_t pxCallbackFunction,
-									Timer_t *pxNewTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									Timer_t *pxNewTimer )
 {
 	/* 0 is not a valid value for xTimerPeriodInTicks. */
 	configASSERT( ( xTimerPeriodInTicks > 0 ) );
@@ -428,7 +396,7 @@ DaemonTaskMessage_t xMessage;
 		/* Send a command to the timer service task to start the xTimer timer. */
 		xMessage.xMessageID = xCommandID;
 		xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
-		xMessage.u.xTimerParameters.pxTimer = ( Timer_t * ) xTimer;
+		xMessage.u.xTimerParameters.pxTimer = xTimer;
 
 		if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
 		{
@@ -468,7 +436,7 @@ TaskHandle_t xTimerGetTimerDaemonTaskHandle( void )
 
 TickType_t xTimerGetPeriod( TimerHandle_t xTimer )
 {
-Timer_t *pxTimer = ( Timer_t * ) xTimer;
+Timer_t *pxTimer = xTimer;
 
 	configASSERT( xTimer );
 	return pxTimer->xTimerPeriodInTicks;
@@ -477,7 +445,7 @@ Timer_t *pxTimer = ( Timer_t * ) xTimer;
 
 TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer )
 {
-Timer_t * pxTimer = ( Timer_t * ) xTimer;
+Timer_t * pxTimer =  xTimer;
 TickType_t xReturn;
 
 	configASSERT( xTimer );
@@ -488,7 +456,7 @@ TickType_t xReturn;
 
 const char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
 {
-Timer_t *pxTimer = ( Timer_t * ) xTimer;
+Timer_t *pxTimer = xTimer;
 
 	configASSERT( xTimer );
 	return pxTimer->pcTimerName;
@@ -498,7 +466,7 @@ Timer_t *pxTimer = ( Timer_t * ) xTimer;
 static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
 {
 BaseType_t xResult;
-Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );
+Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 
 	/* Remove the timer from the list of active timers.  A check has already
 	been performed to ensure the list is not empty. */
@@ -760,7 +728,7 @@ TickType_t xTimeNow;
 			software timer. */
 			pxTimer = xMessage.u.xTimerParameters.pxTimer;
 
-			if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE )
+			if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
 			{
 				/* The timer is in a list, remove it. */
 				( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
@@ -884,7 +852,7 @@ BaseType_t xResult;
 		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
 
 		/* Remove the timer from the list. */
-		pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );
+		pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 		( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
 		traceTIMER_EXPIRED( pxTimer );
 
@@ -945,10 +913,10 @@ static void prvCheckForValidListAndQueue( void )
 			{
 				/* The timer queue is allocated statically in case
 				configSUPPORT_DYNAMIC_ALLOCATION is 0. */
-				static StaticQueue_t xStaticTimerQueue;
-				static uint8_t ucStaticTimerQueueStorage[ configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ];
+				static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+				static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
 
-				xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
+				xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
 			}
 			#else
 			{
@@ -981,7 +949,7 @@ static void prvCheckForValidListAndQueue( void )
 BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )
 {
 BaseType_t xTimerIsInActiveList;
-Timer_t *pxTimer = ( Timer_t * ) xTimer;
+Timer_t *pxTimer = xTimer;
 
 	configASSERT( xTimer );
 
@@ -991,7 +959,14 @@ Timer_t *pxTimer = ( Timer_t * ) xTimer;
 		/* Checking to see if it is in the NULL list in effect checks to see if
 		it is referenced from either the current or the overflow timer lists in
 		one go, but the logic has to be reversed, hence the '!'. */
-		xTimerIsInActiveList = ( BaseType_t ) !( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) );
+		if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdTRUE )
+		{
+			xTimerIsInActiveList = pdFALSE;
+		}
+		else
+		{
+			xTimerIsInActiveList = pdTRUE;
+		}
 	}
 	taskEXIT_CRITICAL();
 
@@ -1001,7 +976,7 @@ Timer_t *pxTimer = ( Timer_t * ) xTimer;
 
 void *pvTimerGetTimerID( const TimerHandle_t xTimer )
 {
-Timer_t * const pxTimer = ( Timer_t * ) xTimer;
+Timer_t * const pxTimer = xTimer;
 void *pvReturn;
 
 	configASSERT( xTimer );
@@ -1018,7 +993,7 @@ void *pvReturn;
 
 void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID )
 {
-Timer_t * const pxTimer = ( Timer_t * ) xTimer;
+Timer_t * const pxTimer = xTimer;
 
 	configASSERT( xTimer );
 
@@ -1083,6 +1058,26 @@ Timer_t * const pxTimer = ( Timer_t * ) xTimer;
 #endif /* INCLUDE_xTimerPendFunctionCall */
 /*-----------------------------------------------------------*/
 
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer )
+	{
+		return ( ( Timer_t * ) xTimer )->uxTimerNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber )
+	{
+		( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
 /* This entire source file will be skipped if the application is not configured
 to include software timer functionality.  If you want to include software timer
 functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
diff --git a/os/hal/inc/os_hal_inc.h b/os/hal/inc/os_hal_inc.h
index 1ef76454f..bbc5ac91d 100644
--- a/os/hal/inc/os_hal_inc.h
+++ b/os/hal/inc/os_hal_inc.h
@@ -57,9 +57,10 @@
 #include "projdefs.h"
 #include "queue.h"
 #include "semphr.h"
-#include "StackMacros.h"
+#include "stack_macros.h"
 #include "task.h"
 #include "timers.h"
+#include "stream_buffer.h"
 
 #include "arc_freertos_exceptions.h"
 

From 75a5ed4de9373fa1e2cd9c2d0e73f4802a105bef Mon Sep 17 00:00:00 2001
From: Wayne Ren 
Date: Wed, 9 Jan 2019 10:12:24 +0800
Subject: [PATCH 08/28] arc_hal: add hardware stack check support

add hardware stack check support both in baremetal and freertos

Signed-off-by: Wayne Ren 
---
 arc/startup/arc_startup.s                     |  17 ++
 inc/arc/arc.h                                 |   8 +-
 inc/arc/arc_feature_config.h                  |   6 +
 .../portable/Synopsys/ARC/arc_support.s       |  32 +++
 os/freertos/portable/Synopsys/ARC/port.c      | 232 +++++++++++++-----
 os/freertos/portable/Synopsys/ARC/portmacro.h |   5 +
 6 files changed, 233 insertions(+), 67 deletions(-)

diff --git a/arc/startup/arc_startup.s b/arc/startup/arc_startup.s
index d2b48951a..1253356c1 100644
--- a/arc/startup/arc_startup.s
+++ b/arc/startup/arc_startup.s
@@ -191,6 +191,23 @@ _s3_clear_bss_loop:
 	cmp	r0, r1
 	jlt	_s3_clear_bss_loop
 
+#if ARC_FEATURE_STACK_CHECK
+	mov r0, _e_stack
+	mov r1, _f_stack
+#if ARC_FEATURE_SEC_PRESENT
+	sr r1, [AUX_S_KSTACK_TOP]
+	sr r0, [AUX_S_KSTACK_BASE]
+	lr r0, [AUX_SEC_STAT]
+	bset r0, r0, AUX_SEC_STAT_BIT_SSC
+	sflag r0
+#else
+	sr r1, [AUX_KSTACK_TOP]
+	sr r0, [AUX_KSTACK_BASE]
+	lr r0, [AUX_STATUS32]
+	bset r0, r0, AUX_STATUS_BIT_SC
+	kflag r0
+#endif
+#endif
 /* STAGE 3: go to main */
 
 _arc_reset_call_main:
diff --git a/inc/arc/arc.h b/inc/arc/arc.h
index 691f0ff4c..c32353628 100644
--- a/inc/arc/arc.h
+++ b/inc/arc/arc.h
@@ -190,6 +190,7 @@
 #define AUX_STATUS_BIT_L		(12)	/*!< zero-overhead loop enable */
 #define AUX_STATUS_BIT_IE		(31)	/*!< interrupt enable */
 #define AUX_STATUS_BIT_HALT		(0)	/*!< halt bit */
+#define AUX_STATUS_BIT_SC		(14)	/*!< stack check bit */
 
 /* masks correspond to STATUS32 bit-field */
 #define AUX_STATUS_MASK_AE		(1<>>> AND MODIFIED BY <<<< the FreeRTOS exception.
-
-    ***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-    ***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-    the FAQ page "My application does not run, what could be wrong?".  Have you
-    defined configASSERT()?
-
-    http://www.FreeRTOS.org/support - In return for receiving this top quality
-    embedded software for free we request you assist our global community by
-    participating in the support forum.
-
-    http://www.FreeRTOS.org/training - Investing in training allows your team to
-    be as productive as possible as early as possible.  Now you can receive
-    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-    Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
+	FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+	All rights reserved
+
+	VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+	This file is part of the FreeRTOS distribution.
+
+	FreeRTOS is free software; you can redistribute it and/or modify it under
+	the terms of the GNU General Public License (version 2) as published by the
+	Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+	***************************************************************************
+	>>!   NOTE: The modification to the GPL is included to allow you to     !<<
+	>>!   distribute a combined work that includes FreeRTOS without being   !<<
+	>>!   obliged to provide the source code for proprietary components     !<<
+	>>!   outside of the FreeRTOS kernel.                                   !<<
+	***************************************************************************
+
+	FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+	WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+	FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+	link: http://www.freertos.org/a00114.html
+
+	***************************************************************************
+	 *                                                                       *
+	 *    FreeRTOS provides completely free yet professionally developed,    *
+	 *    robust, strictly quality controlled, supported, and cross          *
+	 *    platform software that is more than just the market leader, it     *
+	 *    is the industry's de facto standard.                               *
+	 *                                                                       *
+	 *    Help yourself get started quickly while simultaneously helping     *
+	 *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+	 *    tutorial book, reference manual, or both:                          *
+	 *    http://www.FreeRTOS.org/Documentation                              *
+	 *                                                                       *
+	***************************************************************************
+
+	http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+	the FAQ page "My application does not run, what could be wrong?".  Have you
+	defined configASSERT()?
+
+	http://www.FreeRTOS.org/support - In return for receiving this top quality
+	embedded software for free we request you assist our global community by
+	participating in the support forum.
+
+	http://www.FreeRTOS.org/training - Investing in training allows your team to
+	be as productive as possible as early as possible.  Now you can receive
+	FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+	Ltd, and the world's leading authority on the world's leading RTOS.
+
+	http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+	including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+	compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+	http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+	Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+	http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+	Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+	licenses offer ticketed support, indemnification and commercial middleware.
+
+	http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+	engineered and independently SIL3 certified version for use in safety and
+	mission critical applications that require provable dependability.
+
+	1 tab == 4 spaces!
 */
 /*
  * Implementation of functions defined in portable.h
@@ -221,3 +221,103 @@ void vPortEndTask(void)
 		vPortYield();
 	}
 }
+
+#if ARC_FEATURE_STACK_CHECK
+
+/*
+ * !!! Note !!!
+ * This a trick!!!
+ * It's a copy from task.c. We need to konw the definition of TCB for the purpose of hardware
+ * stack check. Pls don't forget to update it when FreeRTOS is updated.
+ */
+typedef struct tskTaskControlBlock /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+	volatile StackType_t	*pxTopOfStack;	/*< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */
+
+	#if ( portUSING_MPU_WRAPPERS == 1 )
+		xMPU_SETTINGS	xMPUSettings;		/*< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
+	#endif
+
+	ListItem_t			xStateListItem;	/*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
+	ListItem_t			xEventListItem;		/*< Used to reference a task from an event list. */
+	UBaseType_t			uxPriority;			/*< The priority of the task.  0 is the lowest priority. */
+	StackType_t			*pxStack;			/*< Points to the start of the stack. */
+	char				pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+	#if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+		StackType_t		*pxEndOfStack;		/*< Points to the highest valid address for the stack. */
+	#endif
+
+	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+		UBaseType_t		uxCriticalNesting;	/*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */
+	#endif
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t		uxTCBNumber;		/*< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */
+		UBaseType_t		uxTaskNumber;		/*< Stores a number specifically for use by third party trace code. */
+	#endif
+
+	#if ( configUSE_MUTEXES == 1 )
+		UBaseType_t		uxBasePriority;		/*< The priority last assigned to the task - used by the priority inheritance mechanism. */
+		UBaseType_t		uxMutexesHeld;
+	#endif
+
+	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+		TaskHookFunction_t pxTaskTag;
+	#endif
+
+	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+		void			*pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
+	#endif
+
+	#if( configGENERATE_RUN_TIME_STATS == 1 )
+		uint32_t		ulRunTimeCounter;	/*< Stores the amount of time the task has spent in the Running state. */
+	#endif
+
+	#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		/* Allocate a Newlib reent structure that is specific to this task.
+		Note Newlib support has been included by popular demand, but is not
+		used by the FreeRTOS maintainers themselves.  FreeRTOS is not
+		responsible for resulting newlib operation.  User must be familiar with
+		newlib and must provide system-wide implementations of the necessary
+		stubs. Be warned that (at the time of writing) the current newlib design
+		implements a system-wide malloc() that must be provided with locks. */
+		struct	_reent xNewLib_reent;
+	#endif
+
+	#if( configUSE_TASK_NOTIFICATIONS == 1 )
+		volatile uint32_t ulNotifiedValue;
+		volatile uint8_t ucNotifyState;
+	#endif
+
+	/* See the comments above the definition of
+	tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */
+	#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+		uint8_t	ucStaticallyAllocated; 		/*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
+	#endif
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+		uint8_t ucDelayAborted;
+	#endif
+
+	#if( configUSE_POSIX_ERRNO == 1 )
+		int iTaskErrno;
+	#endif
+
+} tskTCB;
+
+
+void vPortSetStackCheck(TaskHandle_t old, TaskHandle_t new)
+{
+
+	if (new != NULL) {
+#if ARC_FEATURE_SEC_PRESENT
+		_arc_aux_write(AUX_S_KSTACK_BASE, (uint32_t)(new->pxEndOfStack));
+		_arc_aux_write(AUX_S_KSTACK_TOP, (uint32_t)(new->pxStack));
+#else
+		_arc_aux_write(AUX_KSTACK_BASE, (uint32_t)(new->pxEndOfStack));
+		_arc_aux_write(AUX_KSTACK_TOP, (uint32_t)(new->pxStack));
+#endif
+	}
+}
+#endif
diff --git a/os/freertos/portable/Synopsys/ARC/portmacro.h b/os/freertos/portable/Synopsys/ARC/portmacro.h
index 58667b8ec..0d2a810fa 100644
--- a/os/freertos/portable/Synopsys/ARC/portmacro.h
+++ b/os/freertos/portable/Synopsys/ARC/portmacro.h
@@ -74,6 +74,11 @@
 extern "C" {
 #endif
 
+/* record stack high address for stack check */
+#ifndef configRECORD_STACK_HIGH_ADDRESS
+    #define configRECORD_STACK_HIGH_ADDRESS 1
+#endif
+
 /*-----------------------------------------------------------
  * Port specific definitions.
  *

From b617f690bf6b1e2cff051cd1cc775c9583dff8f5 Mon Sep 17 00:00:00 2001
From: Yuguo Zou 
Date: Tue, 8 Jan 2019 14:38:58 +0800
Subject: [PATCH 09/28] esp8266: fix board support (i.e. STAR9001444897)

Signed-off-by: Yuguo Zou 
---
 example/freertos/esp8266_wifi/esp8266.h | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/example/freertos/esp8266_wifi/esp8266.h b/example/freertos/esp8266_wifi/esp8266.h
index 350a01193..6cca0a40e 100644
--- a/example/freertos/esp8266_wifi/esp8266.h
+++ b/example/freertos/esp8266_wifi/esp8266.h
@@ -35,11 +35,15 @@
 #include "board.h"
 
 
-/** uart id which HM-10 BLE uses */
-#if defined(BOARD_EMSK)
+/** uart id which esp8266 uses */
+#ifndef ESP8266_UART_ID	//you can define this at board header file (e.g. emsk.h)
+#if defined(BOARD_EMSK) || defined(BOARD_HSDK)
 #define ESP8266_UART_ID		DW_UART_0_ID
-#else
+#elif defined(BOARD_EMSDP)|| defined(BOARD_IOTDK)
 #define ESP8266_UART_ID		DFSS_UART_1_ID
+#else
+#warning esp8266 is not supported on this board!
+#endif
 #endif
 
 typedef enum{

From 16f8165fd546c0f3dfa0ecfc47ea3afaa6966af3 Mon Sep 17 00:00:00 2001
From: Wayne Ren 
Date: Thu, 10 Jan 2019 10:15:32 +0800
Subject: [PATCH 10/28] os: freertos: optimize the task dispatch

optimize and bug fix the task dispatch code

Signed-off-by: Wayne Ren 
---
 .../portable/Synopsys/ARC/arc_support.s       | 31 ++++++-------------
 1 file changed, 9 insertions(+), 22 deletions(-)

diff --git a/os/freertos/portable/Synopsys/ARC/arc_support.s b/os/freertos/portable/Synopsys/ARC/arc_support.s
index d5d235a1e..1a6cd230b 100644
--- a/os/freertos/portable/Synopsys/ARC/arc_support.s
+++ b/os/freertos/portable/Synopsys/ARC/arc_support.s
@@ -98,7 +98,7 @@ dispatch:
 	mov	r1, dispatch_r
 	PUSH	r1			/* save return address */
 	ld	r0, [pxCurrentTCB]
-	b	dispatcher
+	bl	dispatcher
 
 /* return routine when task dispatch happened in task context */
 dispatch_r:
@@ -196,8 +196,7 @@ exc_entry_cpu:
 	ld	r0, [exc_nest_count]
 	add	r1, r0, 1
 	st	r1, [exc_nest_count]
-	cmp	r0, 0
-	bne	exc_handler_1
+	brne	r0, 0, exc_handler_1
 /* change to exception stack if interrupt happened in task context */
 	mov	sp, _e_stack
 exc_handler_1:
@@ -222,8 +221,7 @@ ret_exc:
 	st	r0, [r1]
 
 	ld	r0, [context_switch_reqflg]
-	cmp	r0, 0
-	bne	ret_exc_2
+	brne	r0, 0, ret_exc_2
 ret_exc_1:	/* return from non-task context, interrupts or exceptions are nested */
 
 	EXCEPTION_EPILOGUE
@@ -236,8 +234,7 @@ ret_exc_2:
 	st	r0, [context_switch_reqflg]
 
 	ld	r0, [pxCurrentTCB]
-	cmp	r0, 0
-	beq	ret_exc_r_1
+	breq	r0, 0, ret_exc_1
 
 	SAVE_CALLEE_REGS	/* save callee save registers */
 
@@ -248,7 +245,7 @@ ret_exc_2:
 	mov	r1, ret_exc_r	/* save return address */
 	PUSH	r1
 
-	b	dispatcher	/* r0->pxCurrentTCB */
+	bl	dispatcher	/* r0->pxCurrentTCB */
 
 ret_exc_r:
 	/* recover exception status */
@@ -257,7 +254,6 @@ ret_exc_r:
 	kflag	r0
 
 	RESTORE_CALLEE_REGS	/* recover registers */
-ret_exc_r_1:
 	EXCEPTION_EPILOGUE
 	rtie
 
@@ -288,8 +284,7 @@ exc_entry_int:
 	st	r2, [exc_nest_count]
 	seti	/* enable higher priority interrupt */
 
-	cmp	r3, 0
-	bne	irq_handler_1
+	brne	r3, 0, irq_handler_1
 /* change to exception stack if interrupt happened in task context */
 	mov	sp, _e_stack
 #if ARC_FEATURE_STACK_CHECK
@@ -334,8 +329,7 @@ ret_int:
 	st	r0, [r1]
 
 	ld	r0, [context_switch_reqflg]
-	cmp	r0, 0
-	bne	ret_int_2
+	brne	r0, 0, ret_int_2
 ret_int_1:	/* return from non-task context */
 	INTERRUPT_EPILOGUE
 	rtie
@@ -346,8 +340,7 @@ ret_int_2:
 	st	r0, [context_switch_reqflg]
 
 	ld	r0, [pxCurrentTCB]
-	cmp	r0, 0
-	beq	ret_int_r_1
+	breq 	r0, 0, ret_int_1
 
 	lr	r10, [AUX_IRQ_ACT]
 	PUSH	r10
@@ -358,16 +351,10 @@ ret_int_2:
 	mov	r1, ret_int_r	/* save return address */
 	PUSH	r1
 
-	b	dispatcher	/* r0->pxCurrentTCB */
+	bl	dispatcher	/* r0->pxCurrentTCB */
 
 ret_int_r:
 	RESTORE_CALLEE_REGS	/* recover registers */
-ret_int_r_1:
-	/*
-	 * whether to call the task exception routine
-	 * as it is jumped from dispatch, TCB is already in r1
-	 */
-	/* recover AUX_IRQ_ACT */
 	POPAX	AUX_IRQ_ACT
 	INTERRUPT_EPILOGUE
 	rtie

From 0bf2beca620f3b48d55de6e00005d3ade3990e4b Mon Sep 17 00:00:00 2001
From: Wayne Ren 
Date: Thu, 10 Jan 2019 10:16:30 +0800
Subject: [PATCH 11/28] device: rs9113: fix the bug in os wrapper.

semaphore post and mutex unclock may be called
in interrupt context,add corresponding code.

Signed-off-by: Wayne Ren 
---
 .../wifi/rs9113/os/free_rtos/rsi_os_wrapper.c | 43 ++++++++++++++-----
 1 file changed, 32 insertions(+), 11 deletions(-)

diff --git a/device/peripheral/wifi/rs9113/os/free_rtos/rsi_os_wrapper.c b/device/peripheral/wifi/rs9113/os/free_rtos/rsi_os_wrapper.c
index a69b1dc35..5de87ec73 100644
--- a/device/peripheral/wifi/rs9113/os/free_rtos/rsi_os_wrapper.c
+++ b/device/peripheral/wifi/rs9113/os/free_rtos/rsi_os_wrapper.c
@@ -26,11 +26,7 @@
  * Include files
  * */
 #include 
-#include 
-#include 
-#include 
-#include 
-
+#include "embARC.h"
 
 /*==============================================*/
 /**
@@ -136,7 +132,7 @@ rsi_error_t rsi_mutex_lock(volatile rsi_mutex_handle_t *mutex)
 	{
 		timeout_ms = portMAX_DELAY;
 	}
-	if(xSemaphoreTake(*mutex, timeout_ms) == pdPASS)
+	if(xSemaphoreTake((QueueHandle_t)*mutex, timeout_ms) == pdPASS)
 	{
 		return RSI_ERROR_NONE;
 	}
@@ -159,11 +155,26 @@ rsi_error_t rsi_mutex_lock(volatile rsi_mutex_handle_t *mutex)
  */
 rsi_error_t rsi_mutex_unlock(volatile rsi_mutex_handle_t *mutex)
 {
+	BaseType_t xHigherPriorityTaskWoken;
+
 	if(mutex == NULL)
 	{
 		return RSI_ERROR_INVALID_PARAM;
 	}
-	if(xSemaphoreGive(*mutex) == pdPASS)
+
+	if (arc_int_active()) {
+		xSemaphoreGiveFromISR((QueueHandle_t)*mutex, &xHigherPriorityTaskWoken);
+		if(xHigherPriorityTaskWoken != pdFALSE) {
+			portYIELD_FROM_ISR();
+			return RSI_ERROR_NONE;
+		}
+	} else {
+		if(xSemaphoreGive((QueueHandle_t)*mutex) == pdPASS)
+		{
+			return RSI_ERROR_NONE;
+		}
+	}
+	if(xSemaphoreGive((QueueHandle_t)*mutex) == pdPASS)
 	{
 		return RSI_ERROR_NONE;
 	}
@@ -275,7 +286,7 @@ rsi_error_t rsi_semaphore_wait(rsi_semaphore_handle_t *semaphore, uint32_t timeo
 	{
 		timeout_ms = portMAX_DELAY;
 	}
-	if(xSemaphoreTake(*semaphore, timeout_ms) == pdPASS)
+	if(xSemaphoreTake((QueueHandle_t)*semaphore, timeout_ms) == pdPASS)
 	{
 		return RSI_ERROR_NONE;
 	}
@@ -301,13 +312,23 @@ rsi_error_t rsi_semaphore_wait(rsi_semaphore_handle_t *semaphore, uint32_t timeo
 
 rsi_error_t rsi_semaphore_post(rsi_semaphore_handle_t *semaphore)
 {
+	BaseType_t xHigherPriorityTaskWoken;
 	if(semaphore == NULL)
 	{
 		return RSI_ERROR_INVALID_PARAM;
 	}
-	if(xSemaphoreGive(*semaphore) == pdPASS)
-	{
-		return RSI_ERROR_NONE;
+
+	if (arc_int_active()) {
+		xSemaphoreGiveFromISR(*semaphore, &xHigherPriorityTaskWoken);
+		if(xHigherPriorityTaskWoken != pdFALSE) {
+			portYIELD_FROM_ISR();
+			return RSI_ERROR_NONE;
+		}
+	} else {
+		if(xSemaphoreGive(*semaphore) == pdPASS)
+		{
+			return RSI_ERROR_NONE;
+		}
 	}
 	return RSI_ERROR_IN_OS_OPERATION;
 

From df3776b578ac26744257f7546535234490236596 Mon Sep 17 00:00:00 2001
From: Wayne Ren 
Date: Thu, 10 Jan 2019 10:28:50 +0800
Subject: [PATCH 12/28] board: emsdp: remove the content of rev1

rev1 is an early protype, no need now.

Signed-off-by: Wayne Ren 
---
 board/emsdp/emsdp.mk                          |    4 +-
 board/emsdp/rev1/configs/core_compiler.mk     |   15 -
 board/emsdp/rev1/configs/core_configs.mk      |   50 -
 .../rev1/configs/em11d_dfss/apexextensions.h  | 1544 ------
 .../rev1/configs/em11d_dfss/core_hardware.h   |   71 -
 .../rev1/configs/em11d_dfss/dsp_config.h      |   15 -
 .../emsdp/rev1/configs/em11d_dfss/io_config.h |  121 -
 .../configs/em11d_dfss/tcf/em11d_dfss.tcf     | 4841 -----------------
 .../rev1/configs/em6_scss/apexextensions.h    | 1621 ------
 .../rev1/configs/em6_scss/core_hardware.h     |   71 -
 .../emsdp/rev1/configs/em6_scss/dsp_config.h  |   27 -
 board/emsdp/rev1/configs/em6_scss/io_config.h |  116 -
 .../rev1/configs/em6_scss/tcf/em6_scss.tcf    | 4775 ----------------
 .../configs/em7d_esp_dfss/apexextensions.h    | 1544 ------
 .../configs/em7d_esp_dfss/core_hardware.h     |   71 -
 .../rev1/configs/em7d_esp_dfss/dsp_config.h   |   15 -
 .../rev1/configs/em7d_esp_dfss/io_config.h    |  121 -
 .../em7d_esp_dfss/tcf/em7d_esp_dfss.tcf       | 4839 ----------------
 board/emsdp/rev1/configs/emsdp_hardware.h     |  103 -
 board/emsdp/rev1/configs/target_mem_config.h  |  150 -
 20 files changed, 2 insertions(+), 20112 deletions(-)
 delete mode 100644 board/emsdp/rev1/configs/core_compiler.mk
 delete mode 100644 board/emsdp/rev1/configs/core_configs.mk
 delete mode 100644 board/emsdp/rev1/configs/em11d_dfss/apexextensions.h
 delete mode 100644 board/emsdp/rev1/configs/em11d_dfss/core_hardware.h
 delete mode 100644 board/emsdp/rev1/configs/em11d_dfss/dsp_config.h
 delete mode 100644 board/emsdp/rev1/configs/em11d_dfss/io_config.h
 delete mode 100644 board/emsdp/rev1/configs/em11d_dfss/tcf/em11d_dfss.tcf
 delete mode 100644 board/emsdp/rev1/configs/em6_scss/apexextensions.h
 delete mode 100644 board/emsdp/rev1/configs/em6_scss/core_hardware.h
 delete mode 100644 board/emsdp/rev1/configs/em6_scss/dsp_config.h
 delete mode 100644 board/emsdp/rev1/configs/em6_scss/io_config.h
 delete mode 100644 board/emsdp/rev1/configs/em6_scss/tcf/em6_scss.tcf
 delete mode 100644 board/emsdp/rev1/configs/em7d_esp_dfss/apexextensions.h
 delete mode 100644 board/emsdp/rev1/configs/em7d_esp_dfss/core_hardware.h
 delete mode 100644 board/emsdp/rev1/configs/em7d_esp_dfss/dsp_config.h
 delete mode 100644 board/emsdp/rev1/configs/em7d_esp_dfss/io_config.h
 delete mode 100644 board/emsdp/rev1/configs/em7d_esp_dfss/tcf/em7d_esp_dfss.tcf
 delete mode 100644 board/emsdp/rev1/configs/emsdp_hardware.h
 delete mode 100644 board/emsdp/rev1/configs/target_mem_config.h

diff --git a/board/emsdp/emsdp.mk b/board/emsdp/emsdp.mk
index b8e90f52f..65140857b 100644
--- a/board/emsdp/emsdp.mk
+++ b/board/emsdp/emsdp.mk
@@ -10,12 +10,12 @@
 BOARD_EMSDP_DIR = $(BOARDS_ROOT)/emsdp
 ##
 # board version definition
-# rev1 stands for revision 1
+# rev2 stands for revision 2
 # When you don't specify BD_VER
 # in any other place or through make options
 # it will select a proper BD_VER according to your core
 ##
-SUPPORTED_BD_VERS = rev1 rev2
+SUPPORTED_BD_VERS = rev2
 
 ## Select Board Version
 BD_VER ?= rev2
diff --git a/board/emsdp/rev1/configs/core_compiler.mk b/board/emsdp/rev1/configs/core_compiler.mk
deleted file mode 100644
index 9746fb26c..000000000
--- a/board/emsdp/rev1/configs/core_compiler.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-## Metaware Toolchain Options For Core ##
-COMMON_CORE_OPT_MW = @$(EMBARC_GENERATED_DIR)/$(GENE_CCAC_ARG)
-
-CCORE_OPT_MW   += $(COMMON_CORE_OPT_MW)
-CXXCORE_OPT_MW += $(COMMON_CORE_OPT_MW)
-ACORE_OPT_MW   += $(COMMON_CORE_OPT_MW)
-LCORE_OPT_MW   += $(COMMON_CORE_OPT_MW)
-
-## GNU Toolchain Options For Core ##
-COMMON_CORE_OPT_GNU = @$(EMBARC_GENERATED_DIR)/$(GENE_GCC_ARG)
-
-CCORE_OPT_GNU   += $(COMMON_CORE_OPT_GNU)
-CXXCORE_OPT_GNU += $(COMMON_CORE_OPT_GNU)
-ACORE_OPT_GNU   += $(COMMON_CORE_OPT_GNU)
-LCORE_OPT_GNU   += $(COMMON_CORE_OPT_GNU)
\ No newline at end of file
diff --git a/board/emsdp/rev1/configs/core_configs.mk b/board/emsdp/rev1/configs/core_configs.mk
deleted file mode 100644
index f3762250a..000000000
--- a/board/emsdp/rev1/configs/core_configs.mk
+++ /dev/null
@@ -1,50 +0,0 @@
-## Current Supported Core Configurations
-CORE_DIRS = $(sort $(dir $(wildcard $(BOARD_EMSDP_DIR)/$(VALID_BD_VER)/configs/*/core_hardware.h)))
-SUPPORTED_CORES := $(patsubst $(BOARD_EMSDP_DIR)/$(VALID_BD_VER)/configs/%/, %,$(CORE_DIRS))
-
-CUR_CORE ?= $(firstword $(SUPPORTED_CORES))
-
-override CUR_CORE := $(strip $(CUR_CORE))
-
-## Set Valid Core Configuration For Board
-VALID_CUR_CORE = $(call check_item_exist, $(CUR_CORE), $(SUPPORTED_CORES))
-
-BOARD_CORE_DIR = $(BOARD_EMSDP_DIR)/$(VALID_BD_VER)/configs/$(VALID_CUR_CORE)
-
-CORE_CONFIG_MK = $(BOARD_CORE_DIR)/core_config.mk
-
-##
-# load core specific makefie if exist
-##
-ifneq ($(wildcard $(CORE_CONFIG_MK)),)
-COMMON_COMPILE_PREREQUISITES += $(CORE_CONFIG_MK)
-include $(CORE_CONFIG_MK)
-endif
-
-ONCHIP_IP_LIST ?= . designware/spi designware/uart designware/gpio  \
-		designware/sdio designware/trng designware/pwm_timer \
-		subsystem/spi subsystem/gpio subsystem/uart subsystem/iic \
-		subsystem/i2s
-
-## Check TCF file existence
-ifneq ($(TCFFILE_IS_VALID),1)
-TCF ?= $(wildcard $(BOARD_CORE_DIR)/*/*.tcf)
-endif
-
-## If CUR_CORE is not in SUPPORT_CORES list, then force CUR_CORE and VALID_CUR_CORE to be TCF filename
-ifeq ($(TCFFILE_IS_VALID),1)
-ifeq ($(VALID_CUR_CORE),)
-override CUR_CORE := $(TCFFILE_NAME)
-override VALID_CUR_CORE := $(TCFFILE_NAME)
-endif
-endif
-
-## Check Core Configuration Supported
-ifneq ($(TCFFILE_IS_VALID),1)
-ifeq ($(VALID_CUR_CORE),)
-$(info BOARD $(BOARD)-$(BD_VER) Core Configurations - $(SUPPORTED_CORES) are supported)
-$(error $(CUR_CORE) is not supported in $(BOARD)-$(BD_VER), please check it!)
-endif
-endif
-
-CORE_DEFINES += -DCURRENT_CORE=$(VALID_CUR_CORE)
\ No newline at end of file
diff --git a/board/emsdp/rev1/configs/em11d_dfss/apexextensions.h b/board/emsdp/rev1/configs/em11d_dfss/apexextensions.h
deleted file mode 100644
index 943fecd72..000000000
--- a/board/emsdp/rev1/configs/em11d_dfss/apexextensions.h
+++ /dev/null
@@ -1,1544 +0,0 @@
-
-/* **** DO NOT EDIT - this file is generated by ARChitect2 ****
- *
- * Description: Header file declaring the compiler extensions for apex components 
- */
-
-#ifndef _apexextensions_H_
-#define _apexextensions_H_
-
-// User extension instruction - dsp_cos
-extern long dsp_cos(long);
-#pragma intrinsic(dsp_cos, opcode => 0x07, sub_opcode => 0x1E , latency_cycles => 8)
-
-// User extension instruction - dsp_sin
-extern long dsp_sin(long);
-#pragma intrinsic(dsp_sin, opcode => 0x07, sub_opcode => 0x1F , latency_cycles => 8)
-
-// User extension instruction - dsp_tan
-extern long dsp_tan(long);
-#pragma intrinsic(dsp_tan, opcode => 0x07, sub_opcode => 0x22 , latency_cycles => 11)
-
-// User extension instruction - dsp_acos
-extern long dsp_acos(long);
-#pragma intrinsic(dsp_acos, opcode => 0x07, sub_opcode => 0x23 , latency_cycles => 31)
-
-// User extension instruction - dsp_asin
-extern long dsp_asin(long);
-#pragma intrinsic(dsp_asin, opcode => 0x07, sub_opcode => 0x24 , latency_cycles => 31)
-
-// User extension instruction - dsp_atan
-extern long dsp_atan(long);
-#pragma intrinsic(dsp_atan, opcode => 0x07, sub_opcode => 0x25 , latency_cycles => 13)
-
-// User extension instruction - dsp_sqrt
-extern long dsp_sqrt(long);
-#pragma intrinsic(dsp_sqrt, opcode => 0x07, sub_opcode => 0x20 , latency_cycles => 31)
-
-// User extension instruction - dsp_sqrt15
-extern long dsp_sqrt15(long);
-#pragma intrinsic(dsp_sqrt15, opcode => 0x07, sub_opcode => 0x21 , latency_cycles => 15)
-
-#define APEX_COM_ARC_HARDWARE_DFSS_DSP_TRIG_PRESENT	1
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_GPIO0_PRESENT	1
-
-// User extension aux register io_gpio0_debounce
-#define AR_IO_GPIO0_DEBOUNCE 0x80017048
-#pragma Aux_register(0x80017048, name=>"io_gpio0_debounce")
-
-// User extension aux register io_gpio0_clken
-#define AR_IO_GPIO0_CLKEN 0x80017080
-#pragma Aux_register(0x80017080, name=>"io_gpio0_clken")
-
-// User extension aux register io_gpio0_swporta_dr
-#define AR_IO_GPIO0_SWPORTA_DR 0x80017000
-#pragma Aux_register(0x80017000, name=>"io_gpio0_swporta_dr")
-
-// User extension aux register io_gpio0_swporta_ddr
-#define AR_IO_GPIO0_SWPORTA_DDR 0x80017004
-#pragma Aux_register(0x80017004, name=>"io_gpio0_swporta_ddr")
-
-// User extension aux register io_gpio0_inten
-#define AR_IO_GPIO0_INTEN 0x80017030
-#pragma Aux_register(0x80017030, name=>"io_gpio0_inten")
-
-// User extension aux register io_gpio0_intmask
-#define AR_IO_GPIO0_INTMASK 0x80017034
-#pragma Aux_register(0x80017034, name=>"io_gpio0_intmask")
-
-// User extension aux register io_gpio0_inttype_level
-#define AR_IO_GPIO0_INTTYPE_LEVEL 0x80017038
-#pragma Aux_register(0x80017038, name=>"io_gpio0_inttype_level")
-
-// User extension aux register io_gpio0_int_polarity
-#define AR_IO_GPIO0_INT_POLARITY 0x8001703c
-#pragma Aux_register(0x8001703c, name=>"io_gpio0_int_polarity")
-
-// User extension aux register io_gpio0_intstatus
-#define AR_IO_GPIO0_INTSTATUS 0x80017040
-#pragma Aux_register(0x80017040, name=>"io_gpio0_intstatus")
-
-// User extension aux register io_gpio0_raw_intstatus
-#define AR_IO_GPIO0_RAW_INTSTATUS 0x80017044
-#pragma Aux_register(0x80017044, name=>"io_gpio0_raw_intstatus")
-
-// User extension aux register io_gpio0_porta_eoi
-#define AR_IO_GPIO0_PORTA_EOI 0x8001704c
-#pragma Aux_register(0x8001704c, name=>"io_gpio0_porta_eoi")
-
-// User extension aux register io_gpio0_ext_porta
-#define AR_IO_GPIO0_EXT_PORTA 0x80017050
-#pragma Aux_register(0x80017050, name=>"io_gpio0_ext_porta")
-
-// User extension aux register io_gpio0_ls_sync
-#define AR_IO_GPIO0_LS_SYNC 0x80017060
-#pragma Aux_register(0x80017060, name=>"io_gpio0_ls_sync")
-
-// User extension aux register io_gpio0_int_bothedge
-#define AR_IO_GPIO0_INT_BOTHEDGE 0x80017068
-#pragma Aux_register(0x80017068, name=>"io_gpio0_int_bothedge")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2C_MST0_PRESENT	1
-
-// User extension aux register io_i2c_mst0_clken
-#define AR_IO_I2C_MST0_CLKEN 0x800120c0
-#pragma Aux_register(0x800120c0, name=>"io_i2c_mst0_clken")
-
-// User extension aux register io_i2c_mst0_con
-#define AR_IO_I2C_MST0_CON 0x80012000
-#pragma Aux_register(0x80012000, name=>"io_i2c_mst0_con")
-
-// User extension aux register io_i2c_mst0_tar
-#define AR_IO_I2C_MST0_TAR 0x80012004
-#pragma Aux_register(0x80012004, name=>"io_i2c_mst0_tar")
-
-// User extension aux register io_i2c_mst0_data_cmd
-#define AR_IO_I2C_MST0_DATA_CMD 0x80012010
-#pragma Aux_register(0x80012010, name=>"io_i2c_mst0_data_cmd")
-
-// User extension aux register io_i2c_mst0_ss_scl_hcnt
-#define AR_IO_I2C_MST0_SS_SCL_HCNT 0x80012014
-#pragma Aux_register(0x80012014, name=>"io_i2c_mst0_ss_scl_hcnt")
-
-// User extension aux register io_i2c_mst0_ss_scl_lcnt
-#define AR_IO_I2C_MST0_SS_SCL_LCNT 0x80012018
-#pragma Aux_register(0x80012018, name=>"io_i2c_mst0_ss_scl_lcnt")
-
-// User extension aux register io_i2c_mst0_fs_scl_hcnt
-#define AR_IO_I2C_MST0_FS_SCL_HCNT 0x8001201c
-#pragma Aux_register(0x8001201c, name=>"io_i2c_mst0_fs_scl_hcnt")
-
-// User extension aux register io_i2c_mst0_fs_scl_lcnt
-#define AR_IO_I2C_MST0_FS_SCL_LCNT 0x80012020
-#pragma Aux_register(0x80012020, name=>"io_i2c_mst0_fs_scl_lcnt")
-
-// User extension aux register io_i2c_mst0_intr_stat
-#define AR_IO_I2C_MST0_INTR_STAT 0x8001202c
-#pragma Aux_register(0x8001202c, name=>"io_i2c_mst0_intr_stat")
-
-// User extension aux register io_i2c_mst0_intr_mask
-#define AR_IO_I2C_MST0_INTR_MASK 0x80012030
-#pragma Aux_register(0x80012030, name=>"io_i2c_mst0_intr_mask")
-
-// User extension aux register io_i2c_mst0_raw_intr_stat
-#define AR_IO_I2C_MST0_RAW_INTR_STAT 0x80012034
-#pragma Aux_register(0x80012034, name=>"io_i2c_mst0_raw_intr_stat")
-
-// User extension aux register io_i2c_mst0_rx_tl
-#define AR_IO_I2C_MST0_RX_TL 0x80012038
-#pragma Aux_register(0x80012038, name=>"io_i2c_mst0_rx_tl")
-
-// User extension aux register io_i2c_mst0_tx_tl
-#define AR_IO_I2C_MST0_TX_TL 0x8001203c
-#pragma Aux_register(0x8001203c, name=>"io_i2c_mst0_tx_tl")
-
-// User extension aux register io_i2c_mst0_clr_intr
-#define AR_IO_I2C_MST0_CLR_INTR 0x80012040
-#pragma Aux_register(0x80012040, name=>"io_i2c_mst0_clr_intr")
-
-// User extension aux register io_i2c_mst0_clr_rx_under
-#define AR_IO_I2C_MST0_CLR_RX_UNDER 0x80012044
-#pragma Aux_register(0x80012044, name=>"io_i2c_mst0_clr_rx_under")
-
-// User extension aux register io_i2c_mst0_clr_rx_over
-#define AR_IO_I2C_MST0_CLR_RX_OVER 0x80012048
-#pragma Aux_register(0x80012048, name=>"io_i2c_mst0_clr_rx_over")
-
-// User extension aux register io_i2c_mst0_clr_tx_over
-#define AR_IO_I2C_MST0_CLR_TX_OVER 0x8001204c
-#pragma Aux_register(0x8001204c, name=>"io_i2c_mst0_clr_tx_over")
-
-// User extension aux register io_i2c_mst0_clr_tx_abrt
-#define AR_IO_I2C_MST0_CLR_TX_ABRT 0x80012054
-#pragma Aux_register(0x80012054, name=>"io_i2c_mst0_clr_tx_abrt")
-
-// User extension aux register io_i2c_mst0_clr_activity
-#define AR_IO_I2C_MST0_CLR_ACTIVITY 0x8001205c
-#pragma Aux_register(0x8001205c, name=>"io_i2c_mst0_clr_activity")
-
-// User extension aux register io_i2c_mst0_clr_stop_det
-#define AR_IO_I2C_MST0_CLR_STOP_DET 0x80012060
-#pragma Aux_register(0x80012060, name=>"io_i2c_mst0_clr_stop_det")
-
-// User extension aux register io_i2c_mst0_clr_start_det
-#define AR_IO_I2C_MST0_CLR_START_DET 0x80012064
-#pragma Aux_register(0x80012064, name=>"io_i2c_mst0_clr_start_det")
-
-// User extension aux register io_i2c_mst0_enable
-#define AR_IO_I2C_MST0_ENABLE 0x8001206c
-#pragma Aux_register(0x8001206c, name=>"io_i2c_mst0_enable")
-
-// User extension aux register io_i2c_mst0_status
-#define AR_IO_I2C_MST0_STATUS 0x80012070
-#pragma Aux_register(0x80012070, name=>"io_i2c_mst0_status")
-
-// User extension aux register io_i2c_mst0_txflr
-#define AR_IO_I2C_MST0_TXFLR 0x80012074
-#pragma Aux_register(0x80012074, name=>"io_i2c_mst0_txflr")
-
-// User extension aux register io_i2c_mst0_rxflr
-#define AR_IO_I2C_MST0_RXFLR 0x80012078
-#pragma Aux_register(0x80012078, name=>"io_i2c_mst0_rxflr")
-
-// User extension aux register io_i2c_mst0_sda_hold
-#define AR_IO_I2C_MST0_SDA_HOLD 0x8001207c
-#pragma Aux_register(0x8001207c, name=>"io_i2c_mst0_sda_hold")
-
-// User extension aux register io_i2c_mst0_tx_abrt_source
-#define AR_IO_I2C_MST0_TX_ABRT_SOURCE 0x80012080
-#pragma Aux_register(0x80012080, name=>"io_i2c_mst0_tx_abrt_source")
-
-// User extension aux register io_i2c_mst0_enable_status
-#define AR_IO_I2C_MST0_ENABLE_STATUS 0x8001209c
-#pragma Aux_register(0x8001209c, name=>"io_i2c_mst0_enable_status")
-
-// User extension aux register io_i2c_mst0_fs_spklen
-#define AR_IO_I2C_MST0_FS_SPKLEN 0x800120a0
-#pragma Aux_register(0x800120a0, name=>"io_i2c_mst0_fs_spklen")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2C_SLV0_PRESENT	1
-
-// User extension aux register io_i2c_slv0_clken
-#define AR_IO_I2C_SLV0_CLKEN 0x800130c0
-#pragma Aux_register(0x800130c0, name=>"io_i2c_slv0_clken")
-
-// User extension aux register io_i2c_slv0_con
-#define AR_IO_I2C_SLV0_CON 0x80013000
-#pragma Aux_register(0x80013000, name=>"io_i2c_slv0_con")
-
-// User extension aux register io_i2c_slv0_sar
-#define AR_IO_I2C_SLV0_SAR 0x80013008
-#pragma Aux_register(0x80013008, name=>"io_i2c_slv0_sar")
-
-// User extension aux register io_i2c_slv0_data_cmd
-#define AR_IO_I2C_SLV0_DATA_CMD 0x80013010
-#pragma Aux_register(0x80013010, name=>"io_i2c_slv0_data_cmd")
-
-// User extension aux register io_i2c_slv0_intr_stat
-#define AR_IO_I2C_SLV0_INTR_STAT 0x8001302c
-#pragma Aux_register(0x8001302c, name=>"io_i2c_slv0_intr_stat")
-
-// User extension aux register io_i2c_slv0_intr_mask
-#define AR_IO_I2C_SLV0_INTR_MASK 0x80013030
-#pragma Aux_register(0x80013030, name=>"io_i2c_slv0_intr_mask")
-
-// User extension aux register io_i2c_slv0_raw_intr_stat
-#define AR_IO_I2C_SLV0_RAW_INTR_STAT 0x80013034
-#pragma Aux_register(0x80013034, name=>"io_i2c_slv0_raw_intr_stat")
-
-// User extension aux register io_i2c_slv0_rx_tl
-#define AR_IO_I2C_SLV0_RX_TL 0x80013038
-#pragma Aux_register(0x80013038, name=>"io_i2c_slv0_rx_tl")
-
-// User extension aux register io_i2c_slv0_tx_tl
-#define AR_IO_I2C_SLV0_TX_TL 0x8001303c
-#pragma Aux_register(0x8001303c, name=>"io_i2c_slv0_tx_tl")
-
-// User extension aux register io_i2c_slv0_clr_intr
-#define AR_IO_I2C_SLV0_CLR_INTR 0x80013040
-#pragma Aux_register(0x80013040, name=>"io_i2c_slv0_clr_intr")
-
-// User extension aux register io_i2c_slv0_clr_rx_under
-#define AR_IO_I2C_SLV0_CLR_RX_UNDER 0x80013044
-#pragma Aux_register(0x80013044, name=>"io_i2c_slv0_clr_rx_under")
-
-// User extension aux register io_i2c_slv0_clr_rx_over
-#define AR_IO_I2C_SLV0_CLR_RX_OVER 0x80013048
-#pragma Aux_register(0x80013048, name=>"io_i2c_slv0_clr_rx_over")
-
-// User extension aux register io_i2c_slv0_clr_tx_over
-#define AR_IO_I2C_SLV0_CLR_TX_OVER 0x8001304c
-#pragma Aux_register(0x8001304c, name=>"io_i2c_slv0_clr_tx_over")
-
-// User extension aux register io_i2c_slv0_clr_rd_req
-#define AR_IO_I2C_SLV0_CLR_RD_REQ 0x80013050
-#pragma Aux_register(0x80013050, name=>"io_i2c_slv0_clr_rd_req")
-
-// User extension aux register io_i2c_slv0_clr_tx_abrt
-#define AR_IO_I2C_SLV0_CLR_TX_ABRT 0x80013054
-#pragma Aux_register(0x80013054, name=>"io_i2c_slv0_clr_tx_abrt")
-
-// User extension aux register io_i2c_slv0_clr_rx_done
-#define AR_IO_I2C_SLV0_CLR_RX_DONE 0x80013058
-#pragma Aux_register(0x80013058, name=>"io_i2c_slv0_clr_rx_done")
-
-// User extension aux register io_i2c_slv0_clr_activity
-#define AR_IO_I2C_SLV0_CLR_ACTIVITY 0x8001305c
-#pragma Aux_register(0x8001305c, name=>"io_i2c_slv0_clr_activity")
-
-// User extension aux register io_i2c_slv0_clr_stop_det
-#define AR_IO_I2C_SLV0_CLR_STOP_DET 0x80013060
-#pragma Aux_register(0x80013060, name=>"io_i2c_slv0_clr_stop_det")
-
-// User extension aux register io_i2c_slv0_clr_start_det
-#define AR_IO_I2C_SLV0_CLR_START_DET 0x80013064
-#pragma Aux_register(0x80013064, name=>"io_i2c_slv0_clr_start_det")
-
-// User extension aux register io_i2c_slv0_enable
-#define AR_IO_I2C_SLV0_ENABLE 0x8001306c
-#pragma Aux_register(0x8001306c, name=>"io_i2c_slv0_enable")
-
-// User extension aux register io_i2c_slv0_status
-#define AR_IO_I2C_SLV0_STATUS 0x80013070
-#pragma Aux_register(0x80013070, name=>"io_i2c_slv0_status")
-
-// User extension aux register io_i2c_slv0_txflr
-#define AR_IO_I2C_SLV0_TXFLR 0x80013074
-#pragma Aux_register(0x80013074, name=>"io_i2c_slv0_txflr")
-
-// User extension aux register io_i2c_slv0_rxflr
-#define AR_IO_I2C_SLV0_RXFLR 0x80013078
-#pragma Aux_register(0x80013078, name=>"io_i2c_slv0_rxflr")
-
-// User extension aux register io_i2c_slv0_sda_hold
-#define AR_IO_I2C_SLV0_SDA_HOLD 0x8001307c
-#pragma Aux_register(0x8001307c, name=>"io_i2c_slv0_sda_hold")
-
-// User extension aux register io_i2c_slv0_tx_abrt_source
-#define AR_IO_I2C_SLV0_TX_ABRT_SOURCE 0x80013080
-#pragma Aux_register(0x80013080, name=>"io_i2c_slv0_tx_abrt_source")
-
-// User extension aux register io_i2c_slv0_sda_setup
-#define AR_IO_I2C_SLV0_SDA_SETUP 0x80013094
-#pragma Aux_register(0x80013094, name=>"io_i2c_slv0_sda_setup")
-
-// User extension aux register io_i2c_slv0_enable_status
-#define AR_IO_I2C_SLV0_ENABLE_STATUS 0x8001309c
-#pragma Aux_register(0x8001309c, name=>"io_i2c_slv0_enable_status")
-
-// User extension aux register io_i2c_slv0_fs_spklen
-#define AR_IO_I2C_SLV0_FS_SPKLEN 0x800130a0
-#pragma Aux_register(0x800130a0, name=>"io_i2c_slv0_fs_spklen")
-
-// User extension aux register io_i2c_slv0_clr_restart_det
-#define AR_IO_I2C_SLV0_CLR_RESTART_DET 0x800130a8
-#pragma Aux_register(0x800130a8, name=>"io_i2c_slv0_clr_restart_det")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_SPI_MST0_PRESENT	1
-
-// User extension aux register io_spi_mst0_ctrlr0
-#define AR_IO_SPI_MST0_CTRLR0 0x80010000
-#pragma Aux_register(0x80010000, name=>"io_spi_mst0_ctrlr0")
-
-// User extension aux register io_spi_mst0_ctrlr1
-#define AR_IO_SPI_MST0_CTRLR1 0x80010001
-#pragma Aux_register(0x80010001, name=>"io_spi_mst0_ctrlr1")
-
-// User extension aux register io_spi_mst0_spien
-#define AR_IO_SPI_MST0_SPIEN 0x80010002
-#pragma Aux_register(0x80010002, name=>"io_spi_mst0_spien")
-
-// User extension aux register io_spi_mst0_ser
-#define AR_IO_SPI_MST0_SER 0x80010004
-#pragma Aux_register(0x80010004, name=>"io_spi_mst0_ser")
-
-// User extension aux register io_spi_mst0_baudr
-#define AR_IO_SPI_MST0_BAUDR 0x80010005
-#pragma Aux_register(0x80010005, name=>"io_spi_mst0_baudr")
-
-// User extension aux register io_spi_mst0_txftlr
-#define AR_IO_SPI_MST0_TXFTLR 0x80010006
-#pragma Aux_register(0x80010006, name=>"io_spi_mst0_txftlr")
-
-// User extension aux register io_spi_mst0_rxftlr
-#define AR_IO_SPI_MST0_RXFTLR 0x80010007
-#pragma Aux_register(0x80010007, name=>"io_spi_mst0_rxftlr")
-
-// User extension aux register io_spi_mst0_txflr
-#define AR_IO_SPI_MST0_TXFLR 0x80010008
-#pragma Aux_register(0x80010008, name=>"io_spi_mst0_txflr")
-
-// User extension aux register io_spi_mst0_rxflr
-#define AR_IO_SPI_MST0_RXFLR 0x80010009
-#pragma Aux_register(0x80010009, name=>"io_spi_mst0_rxflr")
-
-// User extension aux register io_spi_mst0_sr
-#define AR_IO_SPI_MST0_SR 0x8001000a
-#pragma Aux_register(0x8001000a, name=>"io_spi_mst0_sr")
-
-// User extension aux register io_spi_mst0_imr
-#define AR_IO_SPI_MST0_IMR 0x8001000b
-#pragma Aux_register(0x8001000b, name=>"io_spi_mst0_imr")
-
-// User extension aux register io_spi_mst0_isr
-#define AR_IO_SPI_MST0_ISR 0x8001000c
-#pragma Aux_register(0x8001000c, name=>"io_spi_mst0_isr")
-
-// User extension aux register io_spi_mst0_risr
-#define AR_IO_SPI_MST0_RISR 0x8001000d
-#pragma Aux_register(0x8001000d, name=>"io_spi_mst0_risr")
-
-// User extension aux register io_spi_mst0_txoicr
-#define AR_IO_SPI_MST0_TXOICR 0x8001000e
-#pragma Aux_register(0x8001000e, name=>"io_spi_mst0_txoicr")
-
-// User extension aux register io_spi_mst0_rxoicr
-#define AR_IO_SPI_MST0_RXOICR 0x8001000f
-#pragma Aux_register(0x8001000f, name=>"io_spi_mst0_rxoicr")
-
-// User extension aux register io_spi_mst0_rxuicr
-#define AR_IO_SPI_MST0_RXUICR 0x80010010
-#pragma Aux_register(0x80010010, name=>"io_spi_mst0_rxuicr")
-
-// User extension aux register io_spi_mst0_icr
-#define AR_IO_SPI_MST0_ICR 0x80010012
-#pragma Aux_register(0x80010012, name=>"io_spi_mst0_icr")
-
-// User extension aux register io_spi_mst0_clken
-#define AR_IO_SPI_MST0_CLKEN 0x80010016
-#pragma Aux_register(0x80010016, name=>"io_spi_mst0_clken")
-
-// User extension aux register io_spi_mst0_dr
-#define AR_IO_SPI_MST0_DR 0x80010018
-#pragma Aux_register(0x80010018, name=>"io_spi_mst0_dr")
-
-// User extension aux register io_spi_mst0_rx_sample_dly
-#define AR_IO_SPI_MST0_RX_SAMPLE_DLY 0x8001003c
-#pragma Aux_register(0x8001003c, name=>"io_spi_mst0_rx_sample_dly")
-#define APEX_COM_ARC_HARDWARE_DFSS_SUBSYS_BCR_PRESENT	1
-
-// User extension aux register SUBSYS_BUILD
-#define AR_SUBSYS_BUILD 0xf0
-#pragma Aux_register(0xf0, name=>"SUBSYS_BUILD")
-
-// User extension aux register SUBSYS_DSP_0_BUILD
-#define AR_SUBSYS_DSP_0_BUILD 0xa00
-#pragma Aux_register(0xa00, name=>"SUBSYS_DSP_0_BUILD")
-
-// User extension aux register SUBSYS_DSP_0_CONFIG
-#define AR_SUBSYS_DSP_0_CONFIG 0xa02
-#pragma Aux_register(0xa02, name=>"SUBSYS_DSP_0_CONFIG")
-
-// User extension aux register SUBSYS_IO_0_BUILD
-#define AR_SUBSYS_IO_0_BUILD 0xa04
-#pragma Aux_register(0xa04, name=>"SUBSYS_IO_0_BUILD")
-
-// User extension aux register SUBSYS_IO_1_BUILD
-#define AR_SUBSYS_IO_1_BUILD 0xa05
-#pragma Aux_register(0xa05, name=>"SUBSYS_IO_1_BUILD")
-
-// User extension aux register SUBSYS_IO_2_BUILD
-#define AR_SUBSYS_IO_2_BUILD 0xa06
-#pragma Aux_register(0xa06, name=>"SUBSYS_IO_2_BUILD")
-
-// User extension aux register SUBSYS_UAUX_OFFSET
-#define AR_SUBSYS_UAUX_OFFSET 0xa1e
-#pragma Aux_register(0xa1e, name=>"SUBSYS_UAUX_OFFSET")
-
-// User extension aux register SUBSYS_APEX_OFFSET
-#define AR_SUBSYS_APEX_OFFSET 0xa1f
-#pragma Aux_register(0xa1f, name=>"SUBSYS_APEX_OFFSET")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_SPI_MST1_PRESENT	1
-
-// User extension aux register io_spi_mst1_ctrlr0
-#define AR_IO_SPI_MST1_CTRLR0 0x80010100
-#pragma Aux_register(0x80010100, name=>"io_spi_mst1_ctrlr0")
-
-// User extension aux register io_spi_mst1_ctrlr1
-#define AR_IO_SPI_MST1_CTRLR1 0x80010101
-#pragma Aux_register(0x80010101, name=>"io_spi_mst1_ctrlr1")
-
-// User extension aux register io_spi_mst1_spien
-#define AR_IO_SPI_MST1_SPIEN 0x80010102
-#pragma Aux_register(0x80010102, name=>"io_spi_mst1_spien")
-
-// User extension aux register io_spi_mst1_ser
-#define AR_IO_SPI_MST1_SER 0x80010104
-#pragma Aux_register(0x80010104, name=>"io_spi_mst1_ser")
-
-// User extension aux register io_spi_mst1_baudr
-#define AR_IO_SPI_MST1_BAUDR 0x80010105
-#pragma Aux_register(0x80010105, name=>"io_spi_mst1_baudr")
-
-// User extension aux register io_spi_mst1_txftlr
-#define AR_IO_SPI_MST1_TXFTLR 0x80010106
-#pragma Aux_register(0x80010106, name=>"io_spi_mst1_txftlr")
-
-// User extension aux register io_spi_mst1_rxftlr
-#define AR_IO_SPI_MST1_RXFTLR 0x80010107
-#pragma Aux_register(0x80010107, name=>"io_spi_mst1_rxftlr")
-
-// User extension aux register io_spi_mst1_txflr
-#define AR_IO_SPI_MST1_TXFLR 0x80010108
-#pragma Aux_register(0x80010108, name=>"io_spi_mst1_txflr")
-
-// User extension aux register io_spi_mst1_rxflr
-#define AR_IO_SPI_MST1_RXFLR 0x80010109
-#pragma Aux_register(0x80010109, name=>"io_spi_mst1_rxflr")
-
-// User extension aux register io_spi_mst1_sr
-#define AR_IO_SPI_MST1_SR 0x8001010a
-#pragma Aux_register(0x8001010a, name=>"io_spi_mst1_sr")
-
-// User extension aux register io_spi_mst1_imr
-#define AR_IO_SPI_MST1_IMR 0x8001010b
-#pragma Aux_register(0x8001010b, name=>"io_spi_mst1_imr")
-
-// User extension aux register io_spi_mst1_isr
-#define AR_IO_SPI_MST1_ISR 0x8001010c
-#pragma Aux_register(0x8001010c, name=>"io_spi_mst1_isr")
-
-// User extension aux register io_spi_mst1_risr
-#define AR_IO_SPI_MST1_RISR 0x8001010d
-#pragma Aux_register(0x8001010d, name=>"io_spi_mst1_risr")
-
-// User extension aux register io_spi_mst1_txoicr
-#define AR_IO_SPI_MST1_TXOICR 0x8001010e
-#pragma Aux_register(0x8001010e, name=>"io_spi_mst1_txoicr")
-
-// User extension aux register io_spi_mst1_rxoicr
-#define AR_IO_SPI_MST1_RXOICR 0x8001010f
-#pragma Aux_register(0x8001010f, name=>"io_spi_mst1_rxoicr")
-
-// User extension aux register io_spi_mst1_rxuicr
-#define AR_IO_SPI_MST1_RXUICR 0x80010110
-#pragma Aux_register(0x80010110, name=>"io_spi_mst1_rxuicr")
-
-// User extension aux register io_spi_mst1_icr
-#define AR_IO_SPI_MST1_ICR 0x80010112
-#pragma Aux_register(0x80010112, name=>"io_spi_mst1_icr")
-
-// User extension aux register io_spi_mst1_clken
-#define AR_IO_SPI_MST1_CLKEN 0x80010116
-#pragma Aux_register(0x80010116, name=>"io_spi_mst1_clken")
-
-// User extension aux register io_spi_mst1_dr
-#define AR_IO_SPI_MST1_DR 0x80010118
-#pragma Aux_register(0x80010118, name=>"io_spi_mst1_dr")
-
-// User extension aux register io_spi_mst1_rx_sample_dly
-#define AR_IO_SPI_MST1_RX_SAMPLE_DLY 0x8001013c
-#pragma Aux_register(0x8001013c, name=>"io_spi_mst1_rx_sample_dly")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_SPI_MST2_PRESENT	1
-
-// User extension aux register io_spi_mst2_ctrlr0
-#define AR_IO_SPI_MST2_CTRLR0 0x80010200
-#pragma Aux_register(0x80010200, name=>"io_spi_mst2_ctrlr0")
-
-// User extension aux register io_spi_mst2_ctrlr1
-#define AR_IO_SPI_MST2_CTRLR1 0x80010201
-#pragma Aux_register(0x80010201, name=>"io_spi_mst2_ctrlr1")
-
-// User extension aux register io_spi_mst2_spien
-#define AR_IO_SPI_MST2_SPIEN 0x80010202
-#pragma Aux_register(0x80010202, name=>"io_spi_mst2_spien")
-
-// User extension aux register io_spi_mst2_ser
-#define AR_IO_SPI_MST2_SER 0x80010204
-#pragma Aux_register(0x80010204, name=>"io_spi_mst2_ser")
-
-// User extension aux register io_spi_mst2_baudr
-#define AR_IO_SPI_MST2_BAUDR 0x80010205
-#pragma Aux_register(0x80010205, name=>"io_spi_mst2_baudr")
-
-// User extension aux register io_spi_mst2_txftlr
-#define AR_IO_SPI_MST2_TXFTLR 0x80010206
-#pragma Aux_register(0x80010206, name=>"io_spi_mst2_txftlr")
-
-// User extension aux register io_spi_mst2_rxftlr
-#define AR_IO_SPI_MST2_RXFTLR 0x80010207
-#pragma Aux_register(0x80010207, name=>"io_spi_mst2_rxftlr")
-
-// User extension aux register io_spi_mst2_txflr
-#define AR_IO_SPI_MST2_TXFLR 0x80010208
-#pragma Aux_register(0x80010208, name=>"io_spi_mst2_txflr")
-
-// User extension aux register io_spi_mst2_rxflr
-#define AR_IO_SPI_MST2_RXFLR 0x80010209
-#pragma Aux_register(0x80010209, name=>"io_spi_mst2_rxflr")
-
-// User extension aux register io_spi_mst2_sr
-#define AR_IO_SPI_MST2_SR 0x8001020a
-#pragma Aux_register(0x8001020a, name=>"io_spi_mst2_sr")
-
-// User extension aux register io_spi_mst2_imr
-#define AR_IO_SPI_MST2_IMR 0x8001020b
-#pragma Aux_register(0x8001020b, name=>"io_spi_mst2_imr")
-
-// User extension aux register io_spi_mst2_isr
-#define AR_IO_SPI_MST2_ISR 0x8001020c
-#pragma Aux_register(0x8001020c, name=>"io_spi_mst2_isr")
-
-// User extension aux register io_spi_mst2_risr
-#define AR_IO_SPI_MST2_RISR 0x8001020d
-#pragma Aux_register(0x8001020d, name=>"io_spi_mst2_risr")
-
-// User extension aux register io_spi_mst2_txoicr
-#define AR_IO_SPI_MST2_TXOICR 0x8001020e
-#pragma Aux_register(0x8001020e, name=>"io_spi_mst2_txoicr")
-
-// User extension aux register io_spi_mst2_rxoicr
-#define AR_IO_SPI_MST2_RXOICR 0x8001020f
-#pragma Aux_register(0x8001020f, name=>"io_spi_mst2_rxoicr")
-
-// User extension aux register io_spi_mst2_rxuicr
-#define AR_IO_SPI_MST2_RXUICR 0x80010210
-#pragma Aux_register(0x80010210, name=>"io_spi_mst2_rxuicr")
-
-// User extension aux register io_spi_mst2_icr
-#define AR_IO_SPI_MST2_ICR 0x80010212
-#pragma Aux_register(0x80010212, name=>"io_spi_mst2_icr")
-
-// User extension aux register io_spi_mst2_clken
-#define AR_IO_SPI_MST2_CLKEN 0x80010216
-#pragma Aux_register(0x80010216, name=>"io_spi_mst2_clken")
-
-// User extension aux register io_spi_mst2_dr
-#define AR_IO_SPI_MST2_DR 0x80010218
-#pragma Aux_register(0x80010218, name=>"io_spi_mst2_dr")
-
-// User extension aux register io_spi_mst2_rx_sample_dly
-#define AR_IO_SPI_MST2_RX_SAMPLE_DLY 0x8001023c
-#pragma Aux_register(0x8001023c, name=>"io_spi_mst2_rx_sample_dly")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_SPI_SLV0_PRESENT	1
-
-// User extension aux register io_spi_slv0_ctrlr0
-#define AR_IO_SPI_SLV0_CTRLR0 0x80011000
-#pragma Aux_register(0x80011000, name=>"io_spi_slv0_ctrlr0")
-
-// User extension aux register io_spi_slv0_spien
-#define AR_IO_SPI_SLV0_SPIEN 0x80011002
-#pragma Aux_register(0x80011002, name=>"io_spi_slv0_spien")
-
-// User extension aux register io_spi_slv0_txftlr
-#define AR_IO_SPI_SLV0_TXFTLR 0x80011006
-#pragma Aux_register(0x80011006, name=>"io_spi_slv0_txftlr")
-
-// User extension aux register io_spi_slv0_rxftlr
-#define AR_IO_SPI_SLV0_RXFTLR 0x80011007
-#pragma Aux_register(0x80011007, name=>"io_spi_slv0_rxftlr")
-
-// User extension aux register io_spi_slv0_txflr
-#define AR_IO_SPI_SLV0_TXFLR 0x80011008
-#pragma Aux_register(0x80011008, name=>"io_spi_slv0_txflr")
-
-// User extension aux register io_spi_slv0_rxflr
-#define AR_IO_SPI_SLV0_RXFLR 0x80011009
-#pragma Aux_register(0x80011009, name=>"io_spi_slv0_rxflr")
-
-// User extension aux register io_spi_slv0_sr
-#define AR_IO_SPI_SLV0_SR 0x8001100a
-#pragma Aux_register(0x8001100a, name=>"io_spi_slv0_sr")
-
-// User extension aux register io_spi_slv0_imr
-#define AR_IO_SPI_SLV0_IMR 0x8001100b
-#pragma Aux_register(0x8001100b, name=>"io_spi_slv0_imr")
-
-// User extension aux register io_spi_slv0_isr
-#define AR_IO_SPI_SLV0_ISR 0x8001100c
-#pragma Aux_register(0x8001100c, name=>"io_spi_slv0_isr")
-
-// User extension aux register io_spi_slv0_risr
-#define AR_IO_SPI_SLV0_RISR 0x8001100d
-#pragma Aux_register(0x8001100d, name=>"io_spi_slv0_risr")
-
-// User extension aux register io_spi_slv0_txoicr
-#define AR_IO_SPI_SLV0_TXOICR 0x8001100e
-#pragma Aux_register(0x8001100e, name=>"io_spi_slv0_txoicr")
-
-// User extension aux register io_spi_slv0_rxoicr
-#define AR_IO_SPI_SLV0_RXOICR 0x8001100f
-#pragma Aux_register(0x8001100f, name=>"io_spi_slv0_rxoicr")
-
-// User extension aux register io_spi_slv0_rxuicr
-#define AR_IO_SPI_SLV0_RXUICR 0x80011010
-#pragma Aux_register(0x80011010, name=>"io_spi_slv0_rxuicr")
-
-// User extension aux register io_spi_slv0_icr
-#define AR_IO_SPI_SLV0_ICR 0x80011012
-#pragma Aux_register(0x80011012, name=>"io_spi_slv0_icr")
-
-// User extension aux register io_spi_slv0_clken
-#define AR_IO_SPI_SLV0_CLKEN 0x80011016
-#pragma Aux_register(0x80011016, name=>"io_spi_slv0_clken")
-
-// User extension aux register io_spi_slv0_dr
-#define AR_IO_SPI_SLV0_DR 0x80011018
-#pragma Aux_register(0x80011018, name=>"io_spi_slv0_dr")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_GPIO1_PRESENT	1
-
-// User extension aux register io_gpio1_debounce
-#define AR_IO_GPIO1_DEBOUNCE 0x80017148
-#pragma Aux_register(0x80017148, name=>"io_gpio1_debounce")
-
-// User extension aux register io_gpio1_clken
-#define AR_IO_GPIO1_CLKEN 0x80017180
-#pragma Aux_register(0x80017180, name=>"io_gpio1_clken")
-
-// User extension aux register io_gpio1_swporta_dr
-#define AR_IO_GPIO1_SWPORTA_DR 0x80017100
-#pragma Aux_register(0x80017100, name=>"io_gpio1_swporta_dr")
-
-// User extension aux register io_gpio1_swporta_ddr
-#define AR_IO_GPIO1_SWPORTA_DDR 0x80017104
-#pragma Aux_register(0x80017104, name=>"io_gpio1_swporta_ddr")
-
-// User extension aux register io_gpio1_inten
-#define AR_IO_GPIO1_INTEN 0x80017130
-#pragma Aux_register(0x80017130, name=>"io_gpio1_inten")
-
-// User extension aux register io_gpio1_intmask
-#define AR_IO_GPIO1_INTMASK 0x80017134
-#pragma Aux_register(0x80017134, name=>"io_gpio1_intmask")
-
-// User extension aux register io_gpio1_inttype_level
-#define AR_IO_GPIO1_INTTYPE_LEVEL 0x80017138
-#pragma Aux_register(0x80017138, name=>"io_gpio1_inttype_level")
-
-// User extension aux register io_gpio1_int_polarity
-#define AR_IO_GPIO1_INT_POLARITY 0x8001713c
-#pragma Aux_register(0x8001713c, name=>"io_gpio1_int_polarity")
-
-// User extension aux register io_gpio1_intstatus
-#define AR_IO_GPIO1_INTSTATUS 0x80017140
-#pragma Aux_register(0x80017140, name=>"io_gpio1_intstatus")
-
-// User extension aux register io_gpio1_raw_intstatus
-#define AR_IO_GPIO1_RAW_INTSTATUS 0x80017144
-#pragma Aux_register(0x80017144, name=>"io_gpio1_raw_intstatus")
-
-// User extension aux register io_gpio1_porta_eoi
-#define AR_IO_GPIO1_PORTA_EOI 0x8001714c
-#pragma Aux_register(0x8001714c, name=>"io_gpio1_porta_eoi")
-
-// User extension aux register io_gpio1_ext_porta
-#define AR_IO_GPIO1_EXT_PORTA 0x80017150
-#pragma Aux_register(0x80017150, name=>"io_gpio1_ext_porta")
-
-// User extension aux register io_gpio1_ls_sync
-#define AR_IO_GPIO1_LS_SYNC 0x80017160
-#pragma Aux_register(0x80017160, name=>"io_gpio1_ls_sync")
-
-// User extension aux register io_gpio1_int_bothedge
-#define AR_IO_GPIO1_INT_BOTHEDGE 0x80017168
-#pragma Aux_register(0x80017168, name=>"io_gpio1_int_bothedge")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_GPIO2_PRESENT	1
-
-// User extension aux register io_gpio2_debounce
-#define AR_IO_GPIO2_DEBOUNCE 0x80017248
-#pragma Aux_register(0x80017248, name=>"io_gpio2_debounce")
-
-// User extension aux register io_gpio2_clken
-#define AR_IO_GPIO2_CLKEN 0x80017280
-#pragma Aux_register(0x80017280, name=>"io_gpio2_clken")
-
-// User extension aux register io_gpio2_swporta_dr
-#define AR_IO_GPIO2_SWPORTA_DR 0x80017200
-#pragma Aux_register(0x80017200, name=>"io_gpio2_swporta_dr")
-
-// User extension aux register io_gpio2_swporta_ddr
-#define AR_IO_GPIO2_SWPORTA_DDR 0x80017204
-#pragma Aux_register(0x80017204, name=>"io_gpio2_swporta_ddr")
-
-// User extension aux register io_gpio2_inten
-#define AR_IO_GPIO2_INTEN 0x80017230
-#pragma Aux_register(0x80017230, name=>"io_gpio2_inten")
-
-// User extension aux register io_gpio2_intmask
-#define AR_IO_GPIO2_INTMASK 0x80017234
-#pragma Aux_register(0x80017234, name=>"io_gpio2_intmask")
-
-// User extension aux register io_gpio2_inttype_level
-#define AR_IO_GPIO2_INTTYPE_LEVEL 0x80017238
-#pragma Aux_register(0x80017238, name=>"io_gpio2_inttype_level")
-
-// User extension aux register io_gpio2_int_polarity
-#define AR_IO_GPIO2_INT_POLARITY 0x8001723c
-#pragma Aux_register(0x8001723c, name=>"io_gpio2_int_polarity")
-
-// User extension aux register io_gpio2_intstatus
-#define AR_IO_GPIO2_INTSTATUS 0x80017240
-#pragma Aux_register(0x80017240, name=>"io_gpio2_intstatus")
-
-// User extension aux register io_gpio2_raw_intstatus
-#define AR_IO_GPIO2_RAW_INTSTATUS 0x80017244
-#pragma Aux_register(0x80017244, name=>"io_gpio2_raw_intstatus")
-
-// User extension aux register io_gpio2_porta_eoi
-#define AR_IO_GPIO2_PORTA_EOI 0x8001724c
-#pragma Aux_register(0x8001724c, name=>"io_gpio2_porta_eoi")
-
-// User extension aux register io_gpio2_ext_porta
-#define AR_IO_GPIO2_EXT_PORTA 0x80017250
-#pragma Aux_register(0x80017250, name=>"io_gpio2_ext_porta")
-
-// User extension aux register io_gpio2_ls_sync
-#define AR_IO_GPIO2_LS_SYNC 0x80017260
-#pragma Aux_register(0x80017260, name=>"io_gpio2_ls_sync")
-
-// User extension aux register io_gpio2_int_bothedge
-#define AR_IO_GPIO2_INT_BOTHEDGE 0x80017268
-#pragma Aux_register(0x80017268, name=>"io_gpio2_int_bothedge")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2C_MST1_PRESENT	1
-
-// User extension aux register io_i2c_mst1_clken
-#define AR_IO_I2C_MST1_CLKEN 0x800121c0
-#pragma Aux_register(0x800121c0, name=>"io_i2c_mst1_clken")
-
-// User extension aux register io_i2c_mst1_con
-#define AR_IO_I2C_MST1_CON 0x80012100
-#pragma Aux_register(0x80012100, name=>"io_i2c_mst1_con")
-
-// User extension aux register io_i2c_mst1_tar
-#define AR_IO_I2C_MST1_TAR 0x80012104
-#pragma Aux_register(0x80012104, name=>"io_i2c_mst1_tar")
-
-// User extension aux register io_i2c_mst1_data_cmd
-#define AR_IO_I2C_MST1_DATA_CMD 0x80012110
-#pragma Aux_register(0x80012110, name=>"io_i2c_mst1_data_cmd")
-
-// User extension aux register io_i2c_mst1_ss_scl_hcnt
-#define AR_IO_I2C_MST1_SS_SCL_HCNT 0x80012114
-#pragma Aux_register(0x80012114, name=>"io_i2c_mst1_ss_scl_hcnt")
-
-// User extension aux register io_i2c_mst1_ss_scl_lcnt
-#define AR_IO_I2C_MST1_SS_SCL_LCNT 0x80012118
-#pragma Aux_register(0x80012118, name=>"io_i2c_mst1_ss_scl_lcnt")
-
-// User extension aux register io_i2c_mst1_fs_scl_hcnt
-#define AR_IO_I2C_MST1_FS_SCL_HCNT 0x8001211c
-#pragma Aux_register(0x8001211c, name=>"io_i2c_mst1_fs_scl_hcnt")
-
-// User extension aux register io_i2c_mst1_fs_scl_lcnt
-#define AR_IO_I2C_MST1_FS_SCL_LCNT 0x80012120
-#pragma Aux_register(0x80012120, name=>"io_i2c_mst1_fs_scl_lcnt")
-
-// User extension aux register io_i2c_mst1_intr_stat
-#define AR_IO_I2C_MST1_INTR_STAT 0x8001212c
-#pragma Aux_register(0x8001212c, name=>"io_i2c_mst1_intr_stat")
-
-// User extension aux register io_i2c_mst1_intr_mask
-#define AR_IO_I2C_MST1_INTR_MASK 0x80012130
-#pragma Aux_register(0x80012130, name=>"io_i2c_mst1_intr_mask")
-
-// User extension aux register io_i2c_mst1_raw_intr_stat
-#define AR_IO_I2C_MST1_RAW_INTR_STAT 0x80012134
-#pragma Aux_register(0x80012134, name=>"io_i2c_mst1_raw_intr_stat")
-
-// User extension aux register io_i2c_mst1_rx_tl
-#define AR_IO_I2C_MST1_RX_TL 0x80012138
-#pragma Aux_register(0x80012138, name=>"io_i2c_mst1_rx_tl")
-
-// User extension aux register io_i2c_mst1_tx_tl
-#define AR_IO_I2C_MST1_TX_TL 0x8001213c
-#pragma Aux_register(0x8001213c, name=>"io_i2c_mst1_tx_tl")
-
-// User extension aux register io_i2c_mst1_clr_intr
-#define AR_IO_I2C_MST1_CLR_INTR 0x80012140
-#pragma Aux_register(0x80012140, name=>"io_i2c_mst1_clr_intr")
-
-// User extension aux register io_i2c_mst1_clr_rx_under
-#define AR_IO_I2C_MST1_CLR_RX_UNDER 0x80012144
-#pragma Aux_register(0x80012144, name=>"io_i2c_mst1_clr_rx_under")
-
-// User extension aux register io_i2c_mst1_clr_rx_over
-#define AR_IO_I2C_MST1_CLR_RX_OVER 0x80012148
-#pragma Aux_register(0x80012148, name=>"io_i2c_mst1_clr_rx_over")
-
-// User extension aux register io_i2c_mst1_clr_tx_over
-#define AR_IO_I2C_MST1_CLR_TX_OVER 0x8001214c
-#pragma Aux_register(0x8001214c, name=>"io_i2c_mst1_clr_tx_over")
-
-// User extension aux register io_i2c_mst1_clr_tx_abrt
-#define AR_IO_I2C_MST1_CLR_TX_ABRT 0x80012154
-#pragma Aux_register(0x80012154, name=>"io_i2c_mst1_clr_tx_abrt")
-
-// User extension aux register io_i2c_mst1_clr_activity
-#define AR_IO_I2C_MST1_CLR_ACTIVITY 0x8001215c
-#pragma Aux_register(0x8001215c, name=>"io_i2c_mst1_clr_activity")
-
-// User extension aux register io_i2c_mst1_clr_stop_det
-#define AR_IO_I2C_MST1_CLR_STOP_DET 0x80012160
-#pragma Aux_register(0x80012160, name=>"io_i2c_mst1_clr_stop_det")
-
-// User extension aux register io_i2c_mst1_clr_start_det
-#define AR_IO_I2C_MST1_CLR_START_DET 0x80012164
-#pragma Aux_register(0x80012164, name=>"io_i2c_mst1_clr_start_det")
-
-// User extension aux register io_i2c_mst1_enable
-#define AR_IO_I2C_MST1_ENABLE 0x8001216c
-#pragma Aux_register(0x8001216c, name=>"io_i2c_mst1_enable")
-
-// User extension aux register io_i2c_mst1_status
-#define AR_IO_I2C_MST1_STATUS 0x80012170
-#pragma Aux_register(0x80012170, name=>"io_i2c_mst1_status")
-
-// User extension aux register io_i2c_mst1_txflr
-#define AR_IO_I2C_MST1_TXFLR 0x80012174
-#pragma Aux_register(0x80012174, name=>"io_i2c_mst1_txflr")
-
-// User extension aux register io_i2c_mst1_rxflr
-#define AR_IO_I2C_MST1_RXFLR 0x80012178
-#pragma Aux_register(0x80012178, name=>"io_i2c_mst1_rxflr")
-
-// User extension aux register io_i2c_mst1_sda_hold
-#define AR_IO_I2C_MST1_SDA_HOLD 0x8001217c
-#pragma Aux_register(0x8001217c, name=>"io_i2c_mst1_sda_hold")
-
-// User extension aux register io_i2c_mst1_tx_abrt_source
-#define AR_IO_I2C_MST1_TX_ABRT_SOURCE 0x80012180
-#pragma Aux_register(0x80012180, name=>"io_i2c_mst1_tx_abrt_source")
-
-// User extension aux register io_i2c_mst1_enable_status
-#define AR_IO_I2C_MST1_ENABLE_STATUS 0x8001219c
-#pragma Aux_register(0x8001219c, name=>"io_i2c_mst1_enable_status")
-
-// User extension aux register io_i2c_mst1_fs_spklen
-#define AR_IO_I2C_MST1_FS_SPKLEN 0x800121a0
-#pragma Aux_register(0x800121a0, name=>"io_i2c_mst1_fs_spklen")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2C_MST2_PRESENT	1
-
-// User extension aux register io_i2c_mst2_clken
-#define AR_IO_I2C_MST2_CLKEN 0x800122c0
-#pragma Aux_register(0x800122c0, name=>"io_i2c_mst2_clken")
-
-// User extension aux register io_i2c_mst2_con
-#define AR_IO_I2C_MST2_CON 0x80012200
-#pragma Aux_register(0x80012200, name=>"io_i2c_mst2_con")
-
-// User extension aux register io_i2c_mst2_tar
-#define AR_IO_I2C_MST2_TAR 0x80012204
-#pragma Aux_register(0x80012204, name=>"io_i2c_mst2_tar")
-
-// User extension aux register io_i2c_mst2_data_cmd
-#define AR_IO_I2C_MST2_DATA_CMD 0x80012210
-#pragma Aux_register(0x80012210, name=>"io_i2c_mst2_data_cmd")
-
-// User extension aux register io_i2c_mst2_ss_scl_hcnt
-#define AR_IO_I2C_MST2_SS_SCL_HCNT 0x80012214
-#pragma Aux_register(0x80012214, name=>"io_i2c_mst2_ss_scl_hcnt")
-
-// User extension aux register io_i2c_mst2_ss_scl_lcnt
-#define AR_IO_I2C_MST2_SS_SCL_LCNT 0x80012218
-#pragma Aux_register(0x80012218, name=>"io_i2c_mst2_ss_scl_lcnt")
-
-// User extension aux register io_i2c_mst2_fs_scl_hcnt
-#define AR_IO_I2C_MST2_FS_SCL_HCNT 0x8001221c
-#pragma Aux_register(0x8001221c, name=>"io_i2c_mst2_fs_scl_hcnt")
-
-// User extension aux register io_i2c_mst2_fs_scl_lcnt
-#define AR_IO_I2C_MST2_FS_SCL_LCNT 0x80012220
-#pragma Aux_register(0x80012220, name=>"io_i2c_mst2_fs_scl_lcnt")
-
-// User extension aux register io_i2c_mst2_intr_stat
-#define AR_IO_I2C_MST2_INTR_STAT 0x8001222c
-#pragma Aux_register(0x8001222c, name=>"io_i2c_mst2_intr_stat")
-
-// User extension aux register io_i2c_mst2_intr_mask
-#define AR_IO_I2C_MST2_INTR_MASK 0x80012230
-#pragma Aux_register(0x80012230, name=>"io_i2c_mst2_intr_mask")
-
-// User extension aux register io_i2c_mst2_raw_intr_stat
-#define AR_IO_I2C_MST2_RAW_INTR_STAT 0x80012234
-#pragma Aux_register(0x80012234, name=>"io_i2c_mst2_raw_intr_stat")
-
-// User extension aux register io_i2c_mst2_rx_tl
-#define AR_IO_I2C_MST2_RX_TL 0x80012238
-#pragma Aux_register(0x80012238, name=>"io_i2c_mst2_rx_tl")
-
-// User extension aux register io_i2c_mst2_tx_tl
-#define AR_IO_I2C_MST2_TX_TL 0x8001223c
-#pragma Aux_register(0x8001223c, name=>"io_i2c_mst2_tx_tl")
-
-// User extension aux register io_i2c_mst2_clr_intr
-#define AR_IO_I2C_MST2_CLR_INTR 0x80012240
-#pragma Aux_register(0x80012240, name=>"io_i2c_mst2_clr_intr")
-
-// User extension aux register io_i2c_mst2_clr_rx_under
-#define AR_IO_I2C_MST2_CLR_RX_UNDER 0x80012244
-#pragma Aux_register(0x80012244, name=>"io_i2c_mst2_clr_rx_under")
-
-// User extension aux register io_i2c_mst2_clr_rx_over
-#define AR_IO_I2C_MST2_CLR_RX_OVER 0x80012248
-#pragma Aux_register(0x80012248, name=>"io_i2c_mst2_clr_rx_over")
-
-// User extension aux register io_i2c_mst2_clr_tx_over
-#define AR_IO_I2C_MST2_CLR_TX_OVER 0x8001224c
-#pragma Aux_register(0x8001224c, name=>"io_i2c_mst2_clr_tx_over")
-
-// User extension aux register io_i2c_mst2_clr_tx_abrt
-#define AR_IO_I2C_MST2_CLR_TX_ABRT 0x80012254
-#pragma Aux_register(0x80012254, name=>"io_i2c_mst2_clr_tx_abrt")
-
-// User extension aux register io_i2c_mst2_clr_activity
-#define AR_IO_I2C_MST2_CLR_ACTIVITY 0x8001225c
-#pragma Aux_register(0x8001225c, name=>"io_i2c_mst2_clr_activity")
-
-// User extension aux register io_i2c_mst2_clr_stop_det
-#define AR_IO_I2C_MST2_CLR_STOP_DET 0x80012260
-#pragma Aux_register(0x80012260, name=>"io_i2c_mst2_clr_stop_det")
-
-// User extension aux register io_i2c_mst2_clr_start_det
-#define AR_IO_I2C_MST2_CLR_START_DET 0x80012264
-#pragma Aux_register(0x80012264, name=>"io_i2c_mst2_clr_start_det")
-
-// User extension aux register io_i2c_mst2_enable
-#define AR_IO_I2C_MST2_ENABLE 0x8001226c
-#pragma Aux_register(0x8001226c, name=>"io_i2c_mst2_enable")
-
-// User extension aux register io_i2c_mst2_status
-#define AR_IO_I2C_MST2_STATUS 0x80012270
-#pragma Aux_register(0x80012270, name=>"io_i2c_mst2_status")
-
-// User extension aux register io_i2c_mst2_txflr
-#define AR_IO_I2C_MST2_TXFLR 0x80012274
-#pragma Aux_register(0x80012274, name=>"io_i2c_mst2_txflr")
-
-// User extension aux register io_i2c_mst2_rxflr
-#define AR_IO_I2C_MST2_RXFLR 0x80012278
-#pragma Aux_register(0x80012278, name=>"io_i2c_mst2_rxflr")
-
-// User extension aux register io_i2c_mst2_sda_hold
-#define AR_IO_I2C_MST2_SDA_HOLD 0x8001227c
-#pragma Aux_register(0x8001227c, name=>"io_i2c_mst2_sda_hold")
-
-// User extension aux register io_i2c_mst2_tx_abrt_source
-#define AR_IO_I2C_MST2_TX_ABRT_SOURCE 0x80012280
-#pragma Aux_register(0x80012280, name=>"io_i2c_mst2_tx_abrt_source")
-
-// User extension aux register io_i2c_mst2_enable_status
-#define AR_IO_I2C_MST2_ENABLE_STATUS 0x8001229c
-#pragma Aux_register(0x8001229c, name=>"io_i2c_mst2_enable_status")
-
-// User extension aux register io_i2c_mst2_fs_spklen
-#define AR_IO_I2C_MST2_FS_SPKLEN 0x800122a0
-#pragma Aux_register(0x800122a0, name=>"io_i2c_mst2_fs_spklen")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_UART0_PRESENT	1
-
-// User extension aux register io_uart0_clken
-#define AR_IO_UART0_CLKEN 0x800140c0
-#pragma Aux_register(0x800140c0, name=>"io_uart0_clken")
-
-// User extension aux register io_uart0_rbr_thr_dll
-#define AR_IO_UART0_RBR_THR_DLL 0x80014000
-#pragma Aux_register(0x80014000, name=>"io_uart0_rbr_thr_dll")
-
-// User extension aux register io_uart0_ier_dlh
-#define AR_IO_UART0_IER_DLH 0x80014004
-#pragma Aux_register(0x80014004, name=>"io_uart0_ier_dlh")
-
-// User extension aux register io_uart0_iir_fcr
-#define AR_IO_UART0_IIR_FCR 0x80014008
-#pragma Aux_register(0x80014008, name=>"io_uart0_iir_fcr")
-
-// User extension aux register io_uart0_lcr
-#define AR_IO_UART0_LCR 0x8001400c
-#pragma Aux_register(0x8001400c, name=>"io_uart0_lcr")
-
-// User extension aux register io_uart0_mcr
-#define AR_IO_UART0_MCR 0x80014010
-#pragma Aux_register(0x80014010, name=>"io_uart0_mcr")
-
-// User extension aux register io_uart0_lsr
-#define AR_IO_UART0_LSR 0x80014014
-#pragma Aux_register(0x80014014, name=>"io_uart0_lsr")
-
-// User extension aux register io_uart0_msr
-#define AR_IO_UART0_MSR 0x80014018
-#pragma Aux_register(0x80014018, name=>"io_uart0_msr")
-
-// User extension aux register io_uart0_usr
-#define AR_IO_UART0_USR 0x8001407c
-#pragma Aux_register(0x8001407c, name=>"io_uart0_usr")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_UART1_PRESENT	1
-
-// User extension aux register io_uart1_clken
-#define AR_IO_UART1_CLKEN 0x800141c0
-#pragma Aux_register(0x800141c0, name=>"io_uart1_clken")
-
-// User extension aux register io_uart1_rbr_thr_dll
-#define AR_IO_UART1_RBR_THR_DLL 0x80014100
-#pragma Aux_register(0x80014100, name=>"io_uart1_rbr_thr_dll")
-
-// User extension aux register io_uart1_ier_dlh
-#define AR_IO_UART1_IER_DLH 0x80014104
-#pragma Aux_register(0x80014104, name=>"io_uart1_ier_dlh")
-
-// User extension aux register io_uart1_iir_fcr
-#define AR_IO_UART1_IIR_FCR 0x80014108
-#pragma Aux_register(0x80014108, name=>"io_uart1_iir_fcr")
-
-// User extension aux register io_uart1_lcr
-#define AR_IO_UART1_LCR 0x8001410c
-#pragma Aux_register(0x8001410c, name=>"io_uart1_lcr")
-
-// User extension aux register io_uart1_mcr
-#define AR_IO_UART1_MCR 0x80014110
-#pragma Aux_register(0x80014110, name=>"io_uart1_mcr")
-
-// User extension aux register io_uart1_lsr
-#define AR_IO_UART1_LSR 0x80014114
-#pragma Aux_register(0x80014114, name=>"io_uart1_lsr")
-
-// User extension aux register io_uart1_msr
-#define AR_IO_UART1_MSR 0x80014118
-#pragma Aux_register(0x80014118, name=>"io_uart1_msr")
-
-// User extension aux register io_uart1_usr
-#define AR_IO_UART1_USR 0x8001417c
-#pragma Aux_register(0x8001417c, name=>"io_uart1_usr")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_UART2_PRESENT	1
-
-// User extension aux register io_uart2_clken
-#define AR_IO_UART2_CLKEN 0x800142c0
-#pragma Aux_register(0x800142c0, name=>"io_uart2_clken")
-
-// User extension aux register io_uart2_rbr_thr_dll
-#define AR_IO_UART2_RBR_THR_DLL 0x80014200
-#pragma Aux_register(0x80014200, name=>"io_uart2_rbr_thr_dll")
-
-// User extension aux register io_uart2_ier_dlh
-#define AR_IO_UART2_IER_DLH 0x80014204
-#pragma Aux_register(0x80014204, name=>"io_uart2_ier_dlh")
-
-// User extension aux register io_uart2_iir_fcr
-#define AR_IO_UART2_IIR_FCR 0x80014208
-#pragma Aux_register(0x80014208, name=>"io_uart2_iir_fcr")
-
-// User extension aux register io_uart2_lcr
-#define AR_IO_UART2_LCR 0x8001420c
-#pragma Aux_register(0x8001420c, name=>"io_uart2_lcr")
-
-// User extension aux register io_uart2_mcr
-#define AR_IO_UART2_MCR 0x80014210
-#pragma Aux_register(0x80014210, name=>"io_uart2_mcr")
-
-// User extension aux register io_uart2_lsr
-#define AR_IO_UART2_LSR 0x80014214
-#pragma Aux_register(0x80014214, name=>"io_uart2_lsr")
-
-// User extension aux register io_uart2_msr
-#define AR_IO_UART2_MSR 0x80014218
-#pragma Aux_register(0x80014218, name=>"io_uart2_msr")
-
-// User extension aux register io_uart2_usr
-#define AR_IO_UART2_USR 0x8001427c
-#pragma Aux_register(0x8001427c, name=>"io_uart2_usr")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_UART3_PRESENT	1
-
-// User extension aux register io_uart3_clken
-#define AR_IO_UART3_CLKEN 0x800143c0
-#pragma Aux_register(0x800143c0, name=>"io_uart3_clken")
-
-// User extension aux register io_uart3_rbr_thr_dll
-#define AR_IO_UART3_RBR_THR_DLL 0x80014300
-#pragma Aux_register(0x80014300, name=>"io_uart3_rbr_thr_dll")
-
-// User extension aux register io_uart3_ier_dlh
-#define AR_IO_UART3_IER_DLH 0x80014304
-#pragma Aux_register(0x80014304, name=>"io_uart3_ier_dlh")
-
-// User extension aux register io_uart3_iir_fcr
-#define AR_IO_UART3_IIR_FCR 0x80014308
-#pragma Aux_register(0x80014308, name=>"io_uart3_iir_fcr")
-
-// User extension aux register io_uart3_lcr
-#define AR_IO_UART3_LCR 0x8001430c
-#pragma Aux_register(0x8001430c, name=>"io_uart3_lcr")
-
-// User extension aux register io_uart3_mcr
-#define AR_IO_UART3_MCR 0x80014310
-#pragma Aux_register(0x80014310, name=>"io_uart3_mcr")
-
-// User extension aux register io_uart3_lsr
-#define AR_IO_UART3_LSR 0x80014314
-#pragma Aux_register(0x80014314, name=>"io_uart3_lsr")
-
-// User extension aux register io_uart3_msr
-#define AR_IO_UART3_MSR 0x80014318
-#pragma Aux_register(0x80014318, name=>"io_uart3_msr")
-
-// User extension aux register io_uart3_usr
-#define AR_IO_UART3_USR 0x8001437c
-#pragma Aux_register(0x8001437c, name=>"io_uart3_usr")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2S_RX_MST0_PRESENT	1
-
-// User extension aux register io_i2s_rx_mst0_ier
-#define AR_IO_I2S_RX_MST0_IER 0x8001a000
-#pragma Aux_register(0x8001a000, name=>"io_i2s_rx_mst0_ier")
-
-// User extension aux register io_i2s_rx_mst0_irer
-#define AR_IO_I2S_RX_MST0_IRER 0x8001a004
-#pragma Aux_register(0x8001a004, name=>"io_i2s_rx_mst0_irer")
-
-// User extension aux register io_i2s_rx_mst0_cer
-#define AR_IO_I2S_RX_MST0_CER 0x8001a00c
-#pragma Aux_register(0x8001a00c, name=>"io_i2s_rx_mst0_cer")
-
-// User extension aux register io_i2s_rx_mst0_ccr
-#define AR_IO_I2S_RX_MST0_CCR 0x8001a010
-#pragma Aux_register(0x8001a010, name=>"io_i2s_rx_mst0_ccr")
-
-// User extension aux register io_i2s_rx_mst0_rxffr
-#define AR_IO_I2S_RX_MST0_RXFFR 0x8001a014
-#pragma Aux_register(0x8001a014, name=>"io_i2s_rx_mst0_rxffr")
-
-// User extension aux register io_i2s_rx_mst0_lrbr
-#define AR_IO_I2S_RX_MST0_LRBR 0x8001a020
-#pragma Aux_register(0x8001a020, name=>"io_i2s_rx_mst0_lrbr")
-
-// User extension aux register io_i2s_rx_mst0_rrbr
-#define AR_IO_I2S_RX_MST0_RRBR 0x8001a024
-#pragma Aux_register(0x8001a024, name=>"io_i2s_rx_mst0_rrbr")
-
-// User extension aux register io_i2s_rx_mst0_rer
-#define AR_IO_I2S_RX_MST0_RER 0x8001a028
-#pragma Aux_register(0x8001a028, name=>"io_i2s_rx_mst0_rer")
-
-// User extension aux register io_i2s_rx_mst0_rcr
-#define AR_IO_I2S_RX_MST0_RCR 0x8001a030
-#pragma Aux_register(0x8001a030, name=>"io_i2s_rx_mst0_rcr")
-
-// User extension aux register io_i2s_rx_mst0_isr
-#define AR_IO_I2S_RX_MST0_ISR 0x8001a038
-#pragma Aux_register(0x8001a038, name=>"io_i2s_rx_mst0_isr")
-
-// User extension aux register io_i2s_rx_mst0_imr
-#define AR_IO_I2S_RX_MST0_IMR 0x8001a03c
-#pragma Aux_register(0x8001a03c, name=>"io_i2s_rx_mst0_imr")
-
-// User extension aux register io_i2s_rx_mst0_ror
-#define AR_IO_I2S_RX_MST0_ROR 0x8001a040
-#pragma Aux_register(0x8001a040, name=>"io_i2s_rx_mst0_ror")
-
-// User extension aux register io_i2s_rx_mst0_rfcr
-#define AR_IO_I2S_RX_MST0_RFCR 0x8001a048
-#pragma Aux_register(0x8001a048, name=>"io_i2s_rx_mst0_rfcr")
-
-// User extension aux register io_i2s_rx_mst0_rff
-#define AR_IO_I2S_RX_MST0_RFF 0x8001a050
-#pragma Aux_register(0x8001a050, name=>"io_i2s_rx_mst0_rff")
-
-// User extension aux register io_i2s_rx_mst0_rxdma
-#define AR_IO_I2S_RX_MST0_RXDMA 0x8001a1c0
-#pragma Aux_register(0x8001a1c0, name=>"io_i2s_rx_mst0_rxdma")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2S_TX_MST0_PRESENT	1
-
-// User extension aux register io_i2s_tx_mst0_ier
-#define AR_IO_I2S_TX_MST0_IER 0x80019000
-#pragma Aux_register(0x80019000, name=>"io_i2s_tx_mst0_ier")
-
-// User extension aux register io_i2s_tx_mst0_iter
-#define AR_IO_I2S_TX_MST0_ITER 0x80019008
-#pragma Aux_register(0x80019008, name=>"io_i2s_tx_mst0_iter")
-
-// User extension aux register io_i2s_tx_mst0_cer
-#define AR_IO_I2S_TX_MST0_CER 0x8001900c
-#pragma Aux_register(0x8001900c, name=>"io_i2s_tx_mst0_cer")
-
-// User extension aux register io_i2s_tx_mst0_ccr
-#define AR_IO_I2S_TX_MST0_CCR 0x80019010
-#pragma Aux_register(0x80019010, name=>"io_i2s_tx_mst0_ccr")
-
-// User extension aux register io_i2s_tx_mst0_txffr
-#define AR_IO_I2S_TX_MST0_TXFFR 0x80019018
-#pragma Aux_register(0x80019018, name=>"io_i2s_tx_mst0_txffr")
-
-// User extension aux register io_i2s_tx_mst0_lthr
-#define AR_IO_I2S_TX_MST0_LTHR 0x80019020
-#pragma Aux_register(0x80019020, name=>"io_i2s_tx_mst0_lthr")
-
-// User extension aux register io_i2s_tx_mst0_rthr
-#define AR_IO_I2S_TX_MST0_RTHR 0x80019024
-#pragma Aux_register(0x80019024, name=>"io_i2s_tx_mst0_rthr")
-
-// User extension aux register io_i2s_tx_mst0_ter
-#define AR_IO_I2S_TX_MST0_TER 0x8001902c
-#pragma Aux_register(0x8001902c, name=>"io_i2s_tx_mst0_ter")
-
-// User extension aux register io_i2s_tx_mst0_tcr
-#define AR_IO_I2S_TX_MST0_TCR 0x80019034
-#pragma Aux_register(0x80019034, name=>"io_i2s_tx_mst0_tcr")
-
-// User extension aux register io_i2s_tx_mst0_isr
-#define AR_IO_I2S_TX_MST0_ISR 0x80019038
-#pragma Aux_register(0x80019038, name=>"io_i2s_tx_mst0_isr")
-
-// User extension aux register io_i2s_tx_mst0_imr
-#define AR_IO_I2S_TX_MST0_IMR 0x8001903c
-#pragma Aux_register(0x8001903c, name=>"io_i2s_tx_mst0_imr")
-
-// User extension aux register io_i2s_tx_mst0_tor
-#define AR_IO_I2S_TX_MST0_TOR 0x80019044
-#pragma Aux_register(0x80019044, name=>"io_i2s_tx_mst0_tor")
-
-// User extension aux register io_i2s_tx_mst0_tfcr
-#define AR_IO_I2S_TX_MST0_TFCR 0x8001904c
-#pragma Aux_register(0x8001904c, name=>"io_i2s_tx_mst0_tfcr")
-
-// User extension aux register io_i2s_tx_mst0_tff
-#define AR_IO_I2S_TX_MST0_TFF 0x80019054
-#pragma Aux_register(0x80019054, name=>"io_i2s_tx_mst0_tff")
-
-// User extension aux register io_i2s_tx_mst0_txdma
-#define AR_IO_I2S_TX_MST0_TXDMA 0x800191c8
-#pragma Aux_register(0x800191c8, name=>"io_i2s_tx_mst0_txdma")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_PDM_RX0_PRESENT	1
-
-// User extension aux register io_pdm_rx0_pdm_en
-#define AR_IO_PDM_RX0_PDM_EN 0x8001b000
-#pragma Aux_register(0x8001b000, name=>"io_pdm_rx0_pdm_en")
-
-// User extension aux register io_pdm_rx0_pdm_ren
-#define AR_IO_PDM_RX0_PDM_REN 0x8001b004
-#pragma Aux_register(0x8001b004, name=>"io_pdm_rx0_pdm_ren")
-
-// User extension aux register io_pdm_rx0_cer
-#define AR_IO_PDM_RX0_CER 0x8001b00c
-#pragma Aux_register(0x8001b00c, name=>"io_pdm_rx0_cer")
-
-// User extension aux register io_pdm_rx0_rxffr
-#define AR_IO_PDM_RX0_RXFFR 0x8001b014
-#pragma Aux_register(0x8001b014, name=>"io_pdm_rx0_rxffr")
-
-// User extension aux register io_pdm_rx0_rer0
-#define AR_IO_PDM_RX0_RER0 0x8001b028
-#pragma Aux_register(0x8001b028, name=>"io_pdm_rx0_rer0")
-
-// User extension aux register io_pdm_rx0_isr
-#define AR_IO_PDM_RX0_ISR 0x8001b038
-#pragma Aux_register(0x8001b038, name=>"io_pdm_rx0_isr")
-
-// User extension aux register io_pdm_rx0_imr
-#define AR_IO_PDM_RX0_IMR 0x8001b03c
-#pragma Aux_register(0x8001b03c, name=>"io_pdm_rx0_imr")
-
-// User extension aux register io_pdm_rx0_ror
-#define AR_IO_PDM_RX0_ROR 0x8001b040
-#pragma Aux_register(0x8001b040, name=>"io_pdm_rx0_ror")
-
-// User extension aux register io_pdm_rx0_rfcr
-#define AR_IO_PDM_RX0_RFCR 0x8001b048
-#pragma Aux_register(0x8001b048, name=>"io_pdm_rx0_rfcr")
-
-// User extension aux register io_pdm_rx0_rxdma
-#define AR_IO_PDM_RX0_RXDMA 0x8001b1c0
-#pragma Aux_register(0x8001b1c0, name=>"io_pdm_rx0_rxdma")
-
-// User extension aux register io_pdm_rx0_pdm_rr
-#define AR_IO_PDM_RX0_PDM_RR 0x8001b1d0
-#pragma Aux_register(0x8001b1d0, name=>"io_pdm_rx0_pdm_rr")
-
-// User extension aux register io_pdm_rx0_cic_n
-#define AR_IO_PDM_RX0_CIC_N 0x8001b1d4
-#pragma Aux_register(0x8001b1d4, name=>"io_pdm_rx0_cic_n")
-
-// User extension aux register io_pdm_rx0_cic_d
-#define AR_IO_PDM_RX0_CIC_D 0x8001b1d8
-#pragma Aux_register(0x8001b1d8, name=>"io_pdm_rx0_cic_d")
-
-// User extension aux register io_pdm_rx0_dcrc
-#define AR_IO_PDM_RX0_DCRC 0x8001b1dc
-#pragma Aux_register(0x8001b1dc, name=>"io_pdm_rx0_dcrc")
-
-// User extension aux register io_pdm_rx0_brc_b0
-#define AR_IO_PDM_RX0_BRC_B0 0x8001b1e0
-#pragma Aux_register(0x8001b1e0, name=>"io_pdm_rx0_brc_b0")
-
-// User extension aux register io_pdm_rx0_brc_clp
-#define AR_IO_PDM_RX0_BRC_CLP 0x8001b1f0
-#pragma Aux_register(0x8001b1f0, name=>"io_pdm_rx0_brc_clp")
-#define APEX_COM_ARC_HARDWARE_FLOATING_POINT_UNIT_FPU_PRESENT	1
-
-// User extension aux register fpu_build
-#define AR_FPU_BUILD 0xc8
-#pragma Aux_register(0xc8, name=>"fpu_build")
-
-// User extension aux register fpu_ctrl
-#define AR_FPU_CTRL 0x300
-#pragma Aux_register(0x300, name=>"fpu_ctrl")
-
-// User extension aux register fpu_status
-#define AR_FPU_STATUS 0x301
-#pragma Aux_register(0x301, name=>"fpu_status")
-
-// User extension instruction fsmadd
-extern int fsmadd(int,int);
-#pragma intrinsic(fsmadd,opcode=>6,sub_opcode=>5, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fsmsub
-extern int fsmsub(int,int);
-#pragma intrinsic(fsmsub,opcode=>6,sub_opcode=>6, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fsmul
-extern int fsmul(int,int);
-#pragma intrinsic(fsmul,opcode=>6,sub_opcode=>0, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fsadd
-extern int fsadd(int,int);
-#pragma intrinsic(fsadd,opcode=>6,sub_opcode=>1, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fssub
-extern int fssub(int,int);
-#pragma intrinsic(fssub,opcode=>6,sub_opcode=>2, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fcvt32
-extern int fcvt32(int,int);
-#pragma intrinsic(fcvt32,opcode=>6,sub_opcode=>8, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fsdiv
-extern int fsdiv(int,int);
-#pragma intrinsic(fsdiv,opcode=>6,sub_opcode=>7, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fscmp
-extern int fscmp(int,int);
-#pragma intrinsic(fscmp,opcode=>6,sub_opcode=>3, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fscmp
-extern int fscmp_f(int,int);
-#pragma intrinsic(fscmp_f,opcode=>6,sub_opcode=>3, set_flags => 1, flags => "zncv", effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fscmpf
-extern int fscmpf(int,int);
-#pragma intrinsic(fscmpf,opcode=>6,sub_opcode=>4, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fscmpf
-extern int fscmpf_f(int,int);
-#pragma intrinsic(fscmpf_f,opcode=>6,sub_opcode=>4, set_flags => 1, flags => "zncv", effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fssqrt
-extern int fssqrt(int);
-#pragma intrinsic(fssqrt,opcode=>6,sub_opcode=>0, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-#define APEX_COM_ARC_HARDWARE_FLOATING_POINT_UNIT_FPU_DP_ASSIST_PRESENT	1
-
-// User extension aux register aux_dpfp1l
-#define AR_AUX_DPFP1L 0x302
-#pragma Aux_register(0x302, name=>"aux_dpfp1l")
-
-// User extension aux register aux_dpfp1h
-#define AR_AUX_DPFP1H 0x303
-#pragma Aux_register(0x303, name=>"aux_dpfp1h")
-
-// User extension aux register aux_dpfp2l
-#define AR_AUX_DPFP2L 0x304
-#pragma Aux_register(0x304, name=>"aux_dpfp2l")
-
-// User extension aux register aux_dpfp2h
-#define AR_AUX_DPFP2H 0x305
-#pragma Aux_register(0x305, name=>"aux_dpfp2h")
-
-// User extension instruction dmulh11
-extern int dmulh11(int,int);
-#pragma intrinsic(dmulh11,opcode=>6,sub_opcode=>48,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dmulh11
-extern int dmulh11_f(int,int);
-#pragma intrinsic(dmulh11_f,opcode=>6,sub_opcode=>48, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dmulh12
-extern int dmulh12(int,int);
-#pragma intrinsic(dmulh12,opcode=>6,sub_opcode=>49,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dmulh12
-extern int dmulh12_f(int,int);
-#pragma intrinsic(dmulh12_f,opcode=>6,sub_opcode=>49, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dmulh21
-extern int dmulh21(int,int);
-#pragma intrinsic(dmulh21,opcode=>6,sub_opcode=>50,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dmulh21
-extern int dmulh21_f(int,int);
-#pragma intrinsic(dmulh21_f,opcode=>6,sub_opcode=>50, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dmulh22
-extern int dmulh22(int,int);
-#pragma intrinsic(dmulh22,opcode=>6,sub_opcode=>51,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dmulh22
-extern int dmulh22_f(int,int);
-#pragma intrinsic(dmulh22_f,opcode=>6,sub_opcode=>51, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction daddh11
-extern int daddh11(int,int);
-#pragma intrinsic(daddh11,opcode=>6,sub_opcode=>52,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction daddh11
-extern int daddh11_f(int,int);
-#pragma intrinsic(daddh11_f,opcode=>6,sub_opcode=>52, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction daddh12
-extern int daddh12(int,int);
-#pragma intrinsic(daddh12,opcode=>6,sub_opcode=>53,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction daddh12
-extern int daddh12_f(int,int);
-#pragma intrinsic(daddh12_f,opcode=>6,sub_opcode=>53, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction daddh21
-extern int daddh21(int,int);
-#pragma intrinsic(daddh21,opcode=>6,sub_opcode=>54,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction daddh21
-extern int daddh21_f(int,int);
-#pragma intrinsic(daddh21_f,opcode=>6,sub_opcode=>54, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction daddh22
-extern int daddh22(int,int);
-#pragma intrinsic(daddh22,opcode=>6,sub_opcode=>55,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction daddh22
-extern int daddh22_f(int,int);
-#pragma intrinsic(daddh22_f,opcode=>6,sub_opcode=>55, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dsubh11
-extern int dsubh11(int,int);
-#pragma intrinsic(dsubh11,opcode=>6,sub_opcode=>56,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dsubh11
-extern int dsubh11_f(int,int);
-#pragma intrinsic(dsubh11_f,opcode=>6,sub_opcode=>56, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dsubh12
-extern int dsubh12(int,int);
-#pragma intrinsic(dsubh12,opcode=>6,sub_opcode=>57,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dsubh12
-extern int dsubh12_f(int,int);
-#pragma intrinsic(dsubh12_f,opcode=>6,sub_opcode=>57, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dsubh21
-extern int dsubh21(int,int);
-#pragma intrinsic(dsubh21,opcode=>6,sub_opcode=>58,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dsubh21
-extern int dsubh21_f(int,int);
-#pragma intrinsic(dsubh21_f,opcode=>6,sub_opcode=>58, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dsubh22
-extern int dsubh22(int,int);
-#pragma intrinsic(dsubh22,opcode=>6,sub_opcode=>59,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dsubh22
-extern int dsubh22_f(int,int);
-#pragma intrinsic(dsubh22_f,opcode=>6,sub_opcode=>59, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dexcl1
-extern int dexcl1(int,int);
-#pragma intrinsic(dexcl1,opcode=>6,sub_opcode=>60, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dexcl2
-extern int dexcl2(int,int);
-#pragma intrinsic(dexcl2,opcode=>6,sub_opcode=>61, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-
-#endif
-
-
diff --git a/board/emsdp/rev1/configs/em11d_dfss/core_hardware.h b/board/emsdp/rev1/configs/em11d_dfss/core_hardware.h
deleted file mode 100644
index 7922af9a5..000000000
--- a/board/emsdp/rev1/configs/em11d_dfss/core_hardware.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2018, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
---------------------------------------------- */
-#ifndef _CORE_HARDWARE_H_
-#define _CORE_HARDWARE_H_
-
-#define EMSDP_SPI0_INTR					(83)
-#define EMSDP_SPI1_INTR					(84)
-#define EMSDP_GPIO_INTR0				(85)
-#define EMSDP_GPIO_INTR1				(86)
-#define EMSDP_GPIO_INTR2				(87)
-#define EMSDP_GPIO_INTR3				(88)
-#define EMSDP_TIMER0_INTR0				(89)
-#define EMSDP_TIMER0_INTR1				(90)
-#define EMSDP_TIMER0_INTR2				(91)
-#define EMSDP_TIMER0_INTR3				(92)
-#define EMSDP_TIMER0_INTR4				(93)
-#define EMSDP_TIMER0_INTR5				(94)
-#define EMSDP_TIMER0_INTR6				(95)
-#define EMSDP_TIMER0_INTR7				(96)
-#define EMSDP_TIMER1_INTR0				(97)
-#define EMSDP_TIMER1_INTR1				(98)
-#define EMSDP_TIMER1_INTR2				(99)
-#define EMSDP_TIMER1_INTR3				(100)
-#define EMSDP_TIMER1_INTR4				(101)
-#define EMSDP_TIMER1_INTR5				(102)
-#define EMSDP_TIMER1_INTR6				(103)
-#define EMSDP_TIMER1_INTR7				(104)
-#define EMSDP_UART_INTR					(105)
-#define EMSDP_WDT_INTR					(106)
-#define EMSDP_DBG_UART_INTR				(107)
-#define EMSDP_SDIO_INTR					(108)
-#define EMSDP_REDPINE_SPI_INTR			(109)
-#define EMSDP_REDPINE_HOST_WAKEUP		(110)
-#define EMSDP_NIST_TRNG_INTR			(111)
-
-//EMSDP Peripheral Subsystem DMA assignments
-#define UART_DMA_TX						(9)
-#define UART_DMA_RX						(10)
-#define REDPINE_SPI_DMA_TX				(11)
-#define REDPINE_SPI_DMA_RX				(12)
-#define FLASH_SPI_DMA_TX				(13)
-#define FLASH_SPI_DMA_RX				(14)
-
-#endif //_CORE_HARDWARE_H_
diff --git a/board/emsdp/rev1/configs/em11d_dfss/dsp_config.h b/board/emsdp/rev1/configs/em11d_dfss/dsp_config.h
deleted file mode 100644
index 02a69fd24..000000000
--- a/board/emsdp/rev1/configs/em11d_dfss/dsp_config.h
+++ /dev/null
@@ -1,15 +0,0 @@
-
-/* **** DO NOT EDIT - this file is generated by ARChitect2 ****
- *
- * Description: Header file declaring the compiler extensions for eia components 
- */
-
-#ifndef _dsp_config_H_
-#define _dsp_config_H_
-
-
-#define DSP_TRIG_PRESENT
-
-#endif
-
-
diff --git a/board/emsdp/rev1/configs/em11d_dfss/io_config.h b/board/emsdp/rev1/configs/em11d_dfss/io_config.h
deleted file mode 100644
index 5b45b04d7..000000000
--- a/board/emsdp/rev1/configs/em11d_dfss/io_config.h
+++ /dev/null
@@ -1,121 +0,0 @@
-
-/* **** DO NOT EDIT - this file is generated by ARChitect2 ****
- *
- * Description: Header file declaring the compiler extensions for eia components 
- */
-
-#ifndef _io_config_H_
-#define _io_config_H_
-
-
-#define DMAC_INT_BASE (20)
-#define DMAC_ERR_BASE (DMAC_INT_BASE + DMAC_CHAN_CNT)
-#define DMAC_CHAN_CNT (16)
-#define DMAC_MEM_CHAN_CNT (16)
-#define DMAC_AUX_CHAN_CNT (0)
-#define IO_I2C_SLV0_PRESENT
-#define IO_I2C_SLV0_FS (16)
-#define IO_I2C_SLV0_INT_ERR (50)
-#define IO_I2C_SLV0_INT_RX_AVAIL (51)
-#define IO_I2C_SLV0_INT_TX_REQ (52)
-#define IO_I2C_SLV0_INT_RD_REQ (53)
-#define IO_I2C_SLV0_INT_STOP_DET (54)
-#define IO_I2C_SLV0_INT_RESTART_DET (55)
-#define IO_SPI_MST0_PRESENT
-#define IO_SPI_MST0_FS (16)
-#define IO_SPI_MST0_MAX_XFER_SIZE (16)
-#define IO_SPI_MST0_DMA_TX (3)
-#define IO_SPI_MST0_DMA_RX (4)
-#define IO_SPI_MST0_INT_ERR (63)
-#define IO_SPI_MST0_INT_RX_AVAIL (64)
-#define IO_SPI_MST0_INT_TX_REQ (65)
-#define IO_SPI_MST0_INT_IDLE (66)
-#define IO_SPI_SLV0_PRESENT
-#define IO_SPI_SLV0_FS (16)
-#define IO_SPI_SLV0_MAX_XFER_SIZE (16)
-#define IO_SPI_SLV0_DMA_TX (7)
-#define IO_SPI_SLV0_DMA_RX (8)
-#define IO_SPI_SLV0_INT_ERR (75)
-#define IO_SPI_SLV0_INT_RX_AVAIL (76)
-#define IO_SPI_SLV0_INT_TX_REQ (77)
-#define IO_SPI_SLV0_INT_IDLE (78)
-#define IO_I2C_MST0_PRESENT
-#define IO_I2C_MST0_FS (16)
-#define IO_I2C_MST0_INT_ERR (38)
-#define IO_I2C_MST0_INT_RX_AVAIL (39)
-#define IO_I2C_MST0_INT_TX_REQ (40)
-#define IO_I2C_MST0_INT_STOP_DET (41)
-#define IO_GPIO0_PRESENT
-#define IO_GPIO0_INT_INTR_FLAG (17)
-#define IO_GPIO0_DEBOUNCE (1)
-#define IO_UART0_PRESENT
-#define IO_UART0_FS (16)
-#define IO_UART0_INTR (79)
-#define IO_I2S_TX_MST0_PRESENT
-#define IO_I2S_TX_MST0_FS (8)
-#define IO_I2S_TX_MST0_FW (16)
-#define IO_I2S_TX_MST0_INT_TX_REQ (58)
-#define IO_I2S_TX_MST0_INT_ERR (59)
-#define IO_I2S_TX_MST0_DMA (1)
-#define IO_I2S_RX_MST0_PRESENT
-#define IO_I2S_RX_MST0_FS (8)
-#define IO_I2S_RX_MST0_FW (16)
-#define IO_I2S_RX_MST0_INT_RX_AVAIL (56)
-#define IO_I2S_RX_MST0_INT_ERR (57)
-#define IO_I2S_RX_MST0_DMA (0)
-#define IO_PDM_RX0_PRESENT
-#define IO_PDM_RX0_CH (1)
-#define IO_PDM_RX0_FS (16)
-#define IO_PDM_RX0_NS (4)
-#define IO_PDM_RX0_DS (2)
-#define IO_PDM_RX0_INT_RX_AVAIL (60)
-#define IO_PDM_RX0_INT_ERR (61)
-#define IO_PDM_RX0_INT_CLP (62)
-#define IO_PDM_RX0_DMA (2)
-#define IO_SPI_MST1_PRESENT
-#define IO_SPI_MST1_FS (16)
-#define IO_SPI_MST1_MAX_XFER_SIZE (16)
-#define IO_SPI_MST1_DMA_TX (5)
-#define IO_SPI_MST1_DMA_RX (6)
-#define IO_SPI_MST1_INT_ERR (67)
-#define IO_SPI_MST1_INT_RX_AVAIL (68)
-#define IO_SPI_MST1_INT_TX_REQ (69)
-#define IO_SPI_MST1_INT_IDLE (70)
-#define IO_I2C_MST1_PRESENT
-#define IO_I2C_MST1_FS (16)
-#define IO_I2C_MST1_INT_ERR (42)
-#define IO_I2C_MST1_INT_RX_AVAIL (43)
-#define IO_I2C_MST1_INT_TX_REQ (44)
-#define IO_I2C_MST1_INT_STOP_DET (45)
-#define IO_GPIO1_PRESENT
-#define IO_GPIO1_INT_INTR_FLAG (19)
-#define IO_GPIO1_DEBOUNCE (1)
-#define IO_UART1_PRESENT
-#define IO_UART1_FS (16)
-#define IO_UART1_INTR (80)
-#define IO_SPI_MST2_PRESENT
-#define IO_SPI_MST2_FS (16)
-#define IO_SPI_MST2_MAX_XFER_SIZE (16)
-#define IO_SPI_MST2_INT_ERR (71)
-#define IO_SPI_MST2_INT_RX_AVAIL (72)
-#define IO_SPI_MST2_INT_TX_REQ (73)
-#define IO_SPI_MST2_INT_IDLE (74)
-#define IO_I2C_MST2_PRESENT
-#define IO_I2C_MST2_FS (16)
-#define IO_I2C_MST2_INT_ERR (46)
-#define IO_I2C_MST2_INT_RX_AVAIL (47)
-#define IO_I2C_MST2_INT_TX_REQ (48)
-#define IO_I2C_MST2_INT_STOP_DET (49)
-#define IO_GPIO2_PRESENT
-#define IO_GPIO2_INT_INTR_FLAG (37)
-#define IO_GPIO2_DEBOUNCE (1)
-#define IO_UART2_PRESENT
-#define IO_UART2_FS (16)
-#define IO_UART2_INTR (81)
-#define IO_UART3_PRESENT
-#define IO_UART3_FS (16)
-#define IO_UART3_INTR (82)
-
-#endif
-
-
diff --git a/board/emsdp/rev1/configs/em11d_dfss/tcf/em11d_dfss.tcf b/board/emsdp/rev1/configs/em11d_dfss/tcf/em11d_dfss.tcf
deleted file mode 100644
index 490b4323f..000000000
--- a/board/emsdp/rev1/configs/em11d_dfss/tcf/em11d_dfss.tcf
+++ /dev/null
@@ -1,4841 +0,0 @@
-
-
-  
-  
-    
-  
-  
-    
-  
-  
-    
-  
-  
-    
-  
-  
-    
-  
-  
-    
-  
-  
-    
-# 
-# option  16/L32/U32  Instructions
-# ------  ----------  ---------------------
-#       
-# none	  -/-/-     None
-# wlh1	  1/1/1     MPYW/U, MPY/U, MPYH/U
-# wlh2	  2/2/2     MPYW/U, MPY/U, MPYH/U
-# wlh3	  2/3/3     MPYW/U, MPY/U, MPYH/U
-# wlh4	  2/4/5     MPYW/U, MPY/U, MPYH/U
-# wlh5	  5/9/9     MPYW/U, MPY/U, MPYH/U
-# 

-# 
--mpy_option none
-
-# code_protection --- The ARC EM architecture divides the memory into 16 regions, which can be protected individually.  This feature adds a 16-bit input to the processor core, one bit per region. When the protect bit is set, the processor disables any load or store to the corresponding region.  An attempt to access a protected region raises an EV_ProtV exception.
--code_protection false
-
-# stack_checking --- Stack checking is a mechanism for checking stack accesses and raising an exception when a stack overflow or underflow is detected.
--stack_checking true
-
-# unaligned_option --- This enables unaligned loads and stores.
--unaligned_option true
-
-# intvbase_preset --- This sets the interrupt vector base configuration register, VECBASE_AC_BUILD. The vector base address is aligned to a 1KB boundary, so the required address value should be divided by 1K (i.e. do not include the lower 10 bits). On reset, this register is loaded into the interrupt vector base address register, INT_VECTOR_BASE.
--intvbase_preset 0x0
-
-# intvbase_preset_s --- This sets the secure interrupt vector base configuration register, VECBASE_AC_BUILD. The vector base address is aligned to a 1KB boundary, so the required address value should be divided by 1K (i.e. do not include the lower 10 bits). On reset, this register is loaded into the interrupt vector base address register, INT_VECTOR_BASE_S.This is effective only when 2+2 mode is enabled.
--intvbase_preset_s 0x0
-
-# intvbase_ext --- Set this option to drive the upper 22 bits of the interrupt base vector externally, into signal intvbase_in.
--intvbase_ext false
-
-# nmi_option --- add Non-maskable external exception support
--nmi_option false
-
-# rgf_impl --- This defines whether the register file is implemented using flip-flops, or with a hard macro.
--rgf_impl flip_flops
-
-# rgf_num_regs --- This defines the size (in 32b register) of the processor register file.
--rgf_num_regs 32
-
-# rgf_wr_ports --- This defines the number of write ports on the register file.
--rgf_wr_ports 2
-
-# rgf_num_banks --- Dual register banks are useful if Fast IRQ has been configured, but may be selected even if not.
--rgf_num_banks 2
-
-# rgf_banked_regs --- This selects the number of registers that are replicated in the second register-file bank.
--rgf_banked_regs 32
-
-# turbo_boost --- This enables the Turbo Boost synthesis option. By enabling this option, the achievable clock frequency is increased, but at the cost of an additional cycle latency on branch instructions.
--turbo_boost true
-
-# infer_alu_adder --- infer: datapath is described as behavioral code: A + B
-# instantiate: datapath is instantiated as a detailed multi-stage code of a carry-lookahead adder.  It is generally preferable to use the infer option and add directives for your target synthesizer. 
--infer_alu_adder infer
-
-# infer_mpy_wtree --- infer: datapath is described as behavioral code: A * B (applies to only wlh3, wlh4 and wlh5 designs)
-# instantiate: datapath is instantiated as a detailed multi-stage code of a Wallace Tree multiplier It is generally preferable to use the infer option and add directives for your target synthesizer. 
--infer_mpy_wtree instantiate
-
-# scantest_ram_bypass_mux --- This mux is used to make logic trapped between flops and memory (aka shadow logic) to be covered by scantest without requiring advanced sequential ATPG on the memory to be applied. Will add delay to functional access time
--scantest_ram_bypass_mux false
-
-# logic_bist --- This option will OR LBIST_EN with test_mode
--logic_bist false
-
-# power_domains --- Adds three separate power domains to the core, and propagates power-gate control signals to the top level of the core. Also generates UPF constraints and commands in the low-power scripts
--power_domains false
-
-# dvfs --- Adds logic to the core to allow dynamic controlling of voltage and frequency and propagates the associated control signals to the top level of core
--dvfs false
-
-# voltage_domains --- Creates a voltage  domain split between RAM and std cell parts to support Ultra Low Voltage on cells and generates UPF constraints
--voltage_domains false
-
-# mem_bus_option --- The core supports two bus protocols for accessing external memory: AHB & AHB-Lite. AHB-Lite-single means instruction fetch and data access share a single AHB-Lite port. AHB-Lite-dual means separate AHB-Lite port for each initiator if present.
--mem_bus_option AHB
-
-# mem_bus_reg_interface --- Specifies whether the memory bus interface is registered.
--mem_bus_reg_interface true
-
-# dmi_burst_option --- This will enable high-throughput burst support on the DMI slave interfaces. By enabling this option, the peak DMI read throughput goes from 1 word per 3 cycles to N words per N+2 cycles, in which N is the AHB burst lengthDMI write throughput goes from 1 word per 3 cycles to 1 word per cycle.
--dmi_burst_option true
-
-# has_dmp_peripheral --- This option enables the redirection of load/store accesses to one segment (1/16) of the addressable space to a dedicated peripheral bus. This offers high system integration and reduces overall system cost.
--has_dmp_peripheral true
-
-# per0_base --- This option specifies the memory region assignment for this peripheral aperture
--per0_base 15
-
-# per0_limit --- This option specifies the end of this peripheral aperture
--per0_limit 0
-
-# per_bus_option --- The core supports one bus protocol for accessing the peripheral space, when enabled: AHB-Lite.
--per_bus_option AHB-Lite
-
-# per_bus_reg_interface --- Specifies whether the peripheral bus interface is registered.
--per_bus_reg_interface true
-
-# clock_gating --- This enables the insertion of architectural clock gate elements in the design. By enabling this option, the clocks to various parts of the design will be disabled when the logic they drive is not in use to save power.
--clock_gating false
-
-# back_compat --- This enables the addition of rst_a input in the clkgate module to support backward compatibility with the older EM and Subsystem releases.
--back_compat true
-
-# byte_parity --- If parity protection on the CCMs is configured, this option is used to enable parity protection on a per-byte basis. Otherwise, parity will be per word basis
--byte_parity false
-
-# prot_pipelined --- Check the box if CCM memories are configured for ECC, and you want single-bit errors to be corrected, written back to memory, and re-fetched. When unchecked, single bit errors are corrected when read from memory, but the offending memory location itself is not corrected with a writeback, no influence on Cache protection
--prot_pipelined false
-
-# cct_test_ena --- When ECC is configured, this option enables single bit error injection in CCT RAM models to demonstrate ECC protection on the RAMs. When enabled, the RAM models can only be used in HDL CCT simulation (no xCAM support) and are not intended for use in SoC level integration.
--cct_test_ena false
-
-# err_prot_ehce --- Enabled enhanced ECC architecture for CCM. Instruction fetch with single bit error is not replayed; ecc cac modules are shared to reduce area and timing opt.
--err_prot_ehce false
-
-
-######## dsp_sincos --- com.arc.hardware.dfss.dsp_sincos.1_0 ########
-
-# Create dsp_sincos
--create com.arc.hardware.dfss.dsp_sincos.1_0 System.CPUisle.ARCv2EM.dsp_sincos
-
-# dsp_sincos --- Command line option for APEX extension component 'dsp_sincos'.
--dsp_sincos true
-
-# assign_xpubit --- 
-#       
-# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
-# 

-# By default an extension is not assigned a bit in this register.  This means the extension is always available.
-# 

-# If you wish to assign an XPU bit number, select this option.
-# 
-# 
--assign_xpubit false
-
-# xpubit --- 
-# The XPU bit number for this extension.
-# 
--xpubit 0
-
-
-######## io_gpio0 --- com.arc.hardware.dfss.io_gpio0.1_0 ########
-
-# Create io_gpio0
--create com.arc.hardware.dfss.io_gpio0.1_0 System.CPUisle.ARCv2EM.io_gpio0
-
-# io_gpio0 --- Command line option for EIA extension component 'io_gpio0'.
--io_gpio0 true
-
-# io_gpio0_debounce --- Selects the inclusion of Debounce logic
--io_gpio0_debounce 1
-
-# io_gpio0_readback_sync --- Selects the inclusion of metastability registers on the read back path when reading the external 'ext_porta' signal
--io_gpio0_readback_sync 1
-
-# assign_xpubit --- 
-#       
-# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
-# 

-# By default an extension is not assigned a bit in this register.  This means the extension is always available.
-# 

-# If you wish to assign an XPU bit number, select this option.
-# 
-# 
--assign_xpubit false
-
-# xpubit --- 
-# The XPU bit number for this extension.
-# 
--xpubit 0
-
-# io_gpio0_direction_rst_value --- Reset value of the SWPORTA_DDR register, which determines the direction (input/output) of the GPIO interface. 0: input, 1: output.
--io_gpio0_direction_rst_value 0
-
-# io_gpio0_output_rst_value --- Reset value of the SWPORTA_DR register, which determines the reset value of the GPIO output ports. Bits corresponding to input ports are ignored.
--io_gpio0_output_rst_value 0x0
-
-
-######## io_i2c_mst0 --- com.arc.hardware.dfss.io_i2c_mst0.1_0 ########
-
-# Create io_i2c_mst0
--create com.arc.hardware.dfss.io_i2c_mst0.1_0 System.CPUisle.ARCv2EM.io_i2c_mst0
-
-# io_i2c_mst0 --- Command line option for APEX extension component 'io_i2c_mst0'.
--io_i2c_mst0 true
-
-# io_i2c_mst0_fs --- RX/TX FIFO size
--io_i2c_mst0_fs 16
-
-# io_i2c_mst0_dma_support --- Specifies whether the DMA handshake interface is included
--io_i2c_mst0_dma_support None
-
-# io_i2c_mst0_cdc_included --- Selects whether a clock-domain crossing (CDC) is included between the core clock and the serial clock. If no CDC is present, both clocks must be synchronous. Otherwise the core clock frequency may be higher than, lower than or equal to the serial clock frequency.
--io_i2c_mst0_cdc_included 0
-
-# assign_xpubit --- 
-#       
-# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
-# 

-# By default an extension is not assigned a bit in this register.  This means the extension is always available.
-# 

-# If you wish to assign an XPU bit number, select this option.
-# 
-# 
--assign_xpubit false
-
-# xpubit --- 
-# The XPU bit number for this extension.
-# 
--xpubit 0
-
-
-######## io_i2c_slv0 --- com.arc.hardware.dfss.io_i2c_slv0.1_0 ########
-
-# Create io_i2c_slv0
--create com.arc.hardware.dfss.io_i2c_slv0.1_0 System.CPUisle.ARCv2EM.io_i2c_slv0
-
-# io_i2c_slv0 --- Command line option for APEX extension component 'io_i2c_slv0'.
--io_i2c_slv0 true
-
-# io_i2c_slv0_fs --- RX/TX FIFO size
--io_i2c_slv0_fs 16
-
-# io_i2c_slv0_dma_support --- Specifies whether the DMA handshake interface is included
--io_i2c_slv0_dma_support None
-
-# assign_xpubit --- 
-#       
-# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
-# 

-# By default an extension is not assigned a bit in this register.  This means the extension is always available.
-# 

-# If you wish to assign an XPU bit number, select this option.
-# 
-# 
--assign_xpubit false
-
-# xpubit --- 
-# The XPU bit number for this extension.
-# 
--xpubit 0
-
-
-######## io_spi_mst0 --- com.arc.hardware.dfss.io_spi_mst0.1_0 ########
-
-# Create io_spi_mst0
--create com.arc.hardware.dfss.io_spi_mst0.1_0 System.CPUisle.ARCv2EM.io_spi_mst0
-
-# io_spi_mst0 --- Command line option for APEX extension component 'io_spi_mst0'.
--io_spi_mst0 true
-
-# io_spi_mst0_fz --- RX/TX FIFO depth
--io_spi_mst0_fs 16
-
-# io_spi_mst0_max_xfer_size --- This defines the maximum number of bits per word at the serial data port, which determines the FIFO width.
--io_spi_mst0_max_xfer_size 16
-
-# io_spi_mst0_cdc_included --- Selects whether a clock-domain crossing (CDC) is included between the core clock and the peripheral clock. If no CDC is present, both clocks must be synchronous. Otherwise the core clock frequency may be higher than or equal to the peripheral clock frequency.
--io_spi_mst0_cdc_included 0
-
-# io_spi_mst0_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel.
--io_spi_mst0_dma_support Memory-Based
-
-# assign_xpubit --- 
-#       
-# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
-# 

-# By default an extension is not assigned a bit in this register.  This means the extension is always available.
-# 

-# If you wish to assign an XPU bit number, select this option.
-# 
-# 
--assign_xpubit false
-
-# xpubit --- 
-# The XPU bit number for this extension.
-# 
--xpubit 0
-
-
-######## subsys_bcr --- com.arc.hardware.dfss.subsys_bcr.1_0 ########
-
-# Create subsys_bcr
--create com.arc.hardware.dfss.subsys_bcr.1_0 System.CPUisle.ARCv2EM.subsys_bcr
-
-# assign_xpubit --- 
-#       
-# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
-# 

-# By default an extension is not assigned a bit in this register.  This means the extension is always available.
-# 

-# If you wish to assign an XPU bit number, select this option.
-# 
-# 
--assign_xpubit false
-
-# xpubit --- 
-# The XPU bit number for this extension.
-# 
--xpubit 0
-
-
-######## io_spi_mst1 --- com.arc.hardware.dfss.io_spi_mst1.1_0 ########
-
-# Create io_spi_mst1
--create com.arc.hardware.dfss.io_spi_mst1.1_0 System.CPUisle.ARCv2EM.io_spi_mst1
-
-# io_spi_mst1 --- Command line option for APEX extension component 'io_spi_mst1'.
--io_spi_mst1 true
-
-# io_spi_mst1_fz --- RX/TX FIFO depth
--io_spi_mst1_fs 16
-
-# io_spi_mst1_max_xfer_size --- This defines the maximum number of bits per word at the serial data port, which determines the FIFO width.
--io_spi_mst1_max_xfer_size 16
-
-# io_spi_mst1_cdc_included --- Selects whether a clock-domain crossing (CDC) is included between the core clock and the peripheral clock. If no CDC is present, both clocks must be synchronous. Otherwise the core clock frequency may be higher than or equal to the peripheral clock frequency.
--io_spi_mst1_cdc_included 0
-
-# io_spi_mst1_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel.
--io_spi_mst1_dma_support Memory-Based
-
-# assign_xpubit --- 
-#       
-# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
-# 

-# By default an extension is not assigned a bit in this register.  This means the extension is always available.
-# 

-# If you wish to assign an XPU bit number, select this option.
-# 
-# 
--assign_xpubit false
-
-# xpubit --- 
-# The XPU bit number for this extension.
-# 
--xpubit 0
-
-
-######## io_spi_mst2 --- com.arc.hardware.dfss.io_spi_mst2.1_0 ########
-
-# Create io_spi_mst2
--create com.arc.hardware.dfss.io_spi_mst2.1_0 System.CPUisle.ARCv2EM.io_spi_mst2
-
-# io_spi_mst2 --- Command line option for APEX extension component 'io_spi_mst2'.
--io_spi_mst2 true
-
-# io_spi_mst2_fz --- RX/TX FIFO depth
--io_spi_mst2_fs 16
-
-# io_spi_mst2_max_xfer_size --- This defines the maximum number of bits per word at the serial data port, which determines the FIFO width.
--io_spi_mst2_max_xfer_size 16
-
-# io_spi_mst2_cdc_included --- Selects whether a clock-domain crossing (CDC) is included between the core clock and the peripheral clock. If no CDC is present, both clocks must be synchronous. Otherwise the core clock frequency may be higher than or equal to the peripheral clock frequency.
--io_spi_mst2_cdc_included 0
-
-# io_spi_mst2_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel.
--io_spi_mst2_dma_support None
-
-# assign_xpubit --- 
-#       
-# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
-# 

-# By default an extension is not assigned a bit in this register.  This means the extension is always available.
-# 

-# If you wish to assign an XPU bit number, select this option.
-# 
-# 
--assign_xpubit false
-
-# xpubit --- 
-# The XPU bit number for this extension.
-# 
--xpubit 0
-
-
-######## io_spi_slv0 --- com.arc.hardware.dfss.io_spi_slv0.1_0 ########
-
-# Create io_spi_slv0
--create com.arc.hardware.dfss.io_spi_slv0.1_0 System.CPUisle.ARCv2EM.io_spi_slv0
-
-# io_spi_slv0 --- Command line option for APEX extension component 'io_spi_slv0'.
--io_spi_slv0 true
-
-# io_spi_slv0_fz --- RX/TX FIFO depth
--io_spi_slv0_fs 16
-
-# io_spi_slv0_max_xfer_size --- This defines the maximum number of bits per word at the serial data port, which determines the FIFO width.
--io_spi_slv0_max_xfer_size 16
-
-# io_spi_slv0_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel.
--io_spi_slv0_dma_support Memory-Based
-
-# assign_xpubit --- 
-#       
-# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
-# 

-# By default an extension is not assigned a bit in this register.  This means the extension is always available.
-# 

-# If you wish to assign an XPU bit number, select this option.
-# 
-# 
--assign_xpubit false
-
-# xpubit --- 
-# The XPU bit number for this extension.
-# 
--xpubit 0
-
-
-######## io_gpio1 --- com.arc.hardware.dfss.io_gpio1.1_0 ########
-
-# Create io_gpio1
--create com.arc.hardware.dfss.io_gpio1.1_0 System.CPUisle.ARCv2EM.io_gpio1
-
-# io_gpio1 --- Command line option for EIA extension component 'io_gpio1'.
--io_gpio1 true
-
-# io_gpio1_debounce --- Selects the inclusion of Debounce logic
--io_gpio1_debounce 1
-
-# io_gpio1_readback_sync --- Selects the inclusion of metastability registers on the read back path when reading the external 'ext_porta' signal
--io_gpio1_readback_sync 1
-
-# assign_xpubit --- 
-#       
-# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
-# 

-# By default an extension is not assigned a bit in this register.  This means the extension is always available.
-# 

-# If you wish to assign an XPU bit number, select this option.
-# 
-# 
--assign_xpubit false
-
-# xpubit --- 
-# The XPU bit number for this extension.
-# 
--xpubit 0
-
-# io_gpio1_direction_rst_value --- Reset value of the SWPORTA_DDR register, which determines the direction (input/output) of the GPIO interface. 0: input, 1: output.
--io_gpio1_direction_rst_value 0
-
-# io_gpio1_output_rst_value --- Reset value of the SWPORTA_DR register, which determines the reset value of the GPIO output ports. Bits corresponding to input ports are ignored.
--io_gpio1_output_rst_value 0x0
-
-
-######## io_gpio2 --- com.arc.hardware.dfss.io_gpio2.1_0 ########
-
-# Create io_gpio2
--create com.arc.hardware.dfss.io_gpio2.1_0 System.CPUisle.ARCv2EM.io_gpio2
-
-# io_gpio2 --- Command line option for EIA extension component 'io_gpio2'.
--io_gpio2 true
-
-# io_gpio2_debounce --- Selects the inclusion of Debounce logic
--io_gpio2_debounce 1
-
-# io_gpio2_readback_sync --- Selects the inclusion of metastability registers on the read back path when reading the external 'ext_porta' signal
--io_gpio2_readback_sync 1
-
-# assign_xpubit --- 
-#       
-# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
-# 

-# By default an extension is not assigned a bit in this register.  This means the extension is always available.
-# 

-# If you wish to assign an XPU bit number, select this option.
-# 
-# 
--assign_xpubit false
-
-# xpubit --- 
-# The XPU bit number for this extension.
-# 
--xpubit 0
-
-# io_gpio2_direction_rst_value --- Reset value of the SWPORTA_DDR register, which determines the direction (input/output) of the GPIO interface. 0: input, 1: output.
--io_gpio2_direction_rst_value 0
-
-# io_gpio2_output_rst_value --- Reset value of the SWPORTA_DR register, which determines the reset value of the GPIO output ports. Bits corresponding to input ports are ignored.
--io_gpio2_output_rst_value 0x0
-
-
-######## io_i2c_mst1 --- com.arc.hardware.dfss.io_i2c_mst1.1_0 ########
-
-# Create io_i2c_mst1
--create com.arc.hardware.dfss.io_i2c_mst1.1_0 System.CPUisle.ARCv2EM.io_i2c_mst1
-
-# io_i2c_mst1 --- Command line option for APEX extension component 'io_i2c_mst1'.
--io_i2c_mst1 true
-
-# io_i2c_mst1_fs --- RX/TX FIFO size
--io_i2c_mst1_fs 16
-
-# io_i2c_mst1_dma_support --- Specifies whether the DMA handshake interface is included
--io_i2c_mst1_dma_support None
-
-# io_i2c_mst1_cdc_included --- Selects whether a clock-domain crossing (CDC) is included between the core clock and the serial clock. If no CDC is present, both clocks must be synchronous. Otherwise the core clock frequency may be higher than, lower than or equal to the serial clock frequency.
--io_i2c_mst1_cdc_included 0
-
-# assign_xpubit --- 
-#       
-# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
-# 

-# By default an extension is not assigned a bit in this register.  This means the extension is always available.
-# 

-# If you wish to assign an XPU bit number, select this option.
-# 
-# 
--assign_xpubit false
-
-# xpubit --- 
-# The XPU bit number for this extension.
-# 
--xpubit 0
-
-
-######## io_i2c_mst2 --- com.arc.hardware.dfss.io_i2c_mst2.1_0 ########
-
-# Create io_i2c_mst2
--create com.arc.hardware.dfss.io_i2c_mst2.1_0 System.CPUisle.ARCv2EM.io_i2c_mst2
-
-# io_i2c_mst2 --- Command line option for APEX extension component 'io_i2c_mst2'.
--io_i2c_mst2 true
-
-# io_i2c_mst2_fs --- RX/TX FIFO size
--io_i2c_mst2_fs 16
-
-# io_i2c_mst2_dma_support --- Specifies whether the DMA handshake interface is included
--io_i2c_mst2_dma_support None
-
-# io_i2c_mst2_cdc_included --- Selects whether a clock-domain crossing (CDC) is included between the core clock and the serial clock. If no CDC is present, both clocks must be synchronous. Otherwise the core clock frequency may be higher than, lower than or equal to the serial clock frequency.
--io_i2c_mst2_cdc_included 0
-
-# assign_xpubit --- 
-#       
-# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
-# 

-# By default an extension is not assigned a bit in this register.  This means the extension is always available.
-# 

-# If you wish to assign an XPU bit number, select this option.
-# 
-# 
--assign_xpubit false
-
-# xpubit --- 
-# The XPU bit number for this extension.
-# 
--xpubit 0
-
-
-######## io_uart0 --- com.arc.hardware.dfss.io_uart0.1_0 ########
-
-# Create io_uart0
--create com.arc.hardware.dfss.io_uart0.1_0 System.CPUisle.ARCv2EM.io_uart0
-
-# io_uart0 --- Command line option for EIA extension component 'io_uart0'.
--io_uart0 true
-
-# io_uart0_fifo_mode --- Set the UART FIFO mode
--io_uart0_fifo_mode 16
-
-# io_uart0_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel.
--io_uart0_dma_support None
-
-# assign_xpubit --- 
-#       
-# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
-# 

-# By default an extension is not assigned a bit in this register.  This means the extension is always available.
-# 

-# If you wish to assign an XPU bit number, select this option.
-# 
-# 
--assign_xpubit false
-
-# xpubit --- 
-# The XPU bit number for this extension.
-# 
--xpubit 0
-
-
-######## io_uart1 --- com.arc.hardware.dfss.io_uart1.1_0 ########
-
-# Create io_uart1
--create com.arc.hardware.dfss.io_uart1.1_0 System.CPUisle.ARCv2EM.io_uart1
-
-# io_uart1 --- Command line option for EIA extension component 'io_uart1'.
--io_uart1 true
-
-# io_uart1_fifo_mode --- Set the UART FIFO mode
--io_uart1_fifo_mode 16
-
-# io_uart1_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel.
--io_uart1_dma_support None
-
-# assign_xpubit --- 
-#       
-# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
-# 

-# By default an extension is not assigned a bit in this register.  This means the extension is always available.
-# 

-# If you wish to assign an XPU bit number, select this option.
-# 
-# 
--assign_xpubit false
-
-# xpubit --- 
-# The XPU bit number for this extension.
-# 
--xpubit 0
-
-
-######## io_uart2 --- com.arc.hardware.dfss.io_uart2.1_0 ########
-
-# Create io_uart2
--create com.arc.hardware.dfss.io_uart2.1_0 System.CPUisle.ARCv2EM.io_uart2
-
-# io_uart2 --- Command line option for EIA extension component 'io_uart2'.
--io_uart2 true
-
-# io_uart2_fifo_mode --- Set the UART FIFO mode
--io_uart2_fifo_mode 16
-
-# io_uart2_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel.
--io_uart2_dma_support None
-
-# assign_xpubit --- 
-#       
-# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
-# 

-# By default an extension is not assigned a bit in this register.  This means the extension is always available.
-# 

-# If you wish to assign an XPU bit number, select this option.
-# 
-# 
--assign_xpubit false
-
-# xpubit --- 
-# The XPU bit number for this extension.
-# 
--xpubit 0
-
-
-######## io_uart3 --- com.arc.hardware.dfss.io_uart3.1_0 ########
-
-# Create io_uart3
--create com.arc.hardware.dfss.io_uart3.1_0 System.CPUisle.ARCv2EM.io_uart3
-
-# io_uart3 --- Command line option for EIA extension component 'io_uart3'.
--io_uart3 true
-
-# io_uart3_fifo_mode --- Set the UART FIFO mode
--io_uart3_fifo_mode 16
-
-# io_uart3_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel.
--io_uart3_dma_support None
-
-# assign_xpubit --- 
-#       
-# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
-# 

-# By default an extension is not assigned a bit in this register.  This means the extension is always available.
-# 

-# If you wish to assign an XPU bit number, select this option.
-# 
-# 
--assign_xpubit false
-
-# xpubit --- 
-# The XPU bit number for this extension.
-# 
--xpubit 0
-
-
-######## io_i2s_rx_mst0 --- com.arc.hardware.dfss.io_i2s_rx_mst0.1_0 ########
-
-# Create io_i2s_rx_mst0
--create com.arc.hardware.dfss.io_i2s_rx_mst0.1_0 System.CPUisle.ARCv2EM.io_i2s_rx_mst0
-
-# io_i2s_rx_mst0 --- Command line option for APEX extension component 'io_i2s_rx_mst0'.
--io_i2s_rx_mst0 true
-
-# io_i2s_rx_mst0_fs --- RX FIFO size
--io_i2s_rx_mst0_fs 8
-
-# io_i2s_rx_mst0_fw --- RX FIFO width
--io_i2s_rx_mst0_fw 16
-
-# io_i2s_rx_mst0_dma_support --- Specifies whether the DMA handshake interface is included
--io_i2s_rx_mst0_dma_support Memory-Based
-
-# assign_xpubit --- 
-#       
-# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
-# 

-# By default an extension is not assigned a bit in this register.  This means the extension is always available.
-# 

-# If you wish to assign an XPU bit number, select this option.
-# 
-# 
--assign_xpubit false
-
-# xpubit --- 
-# The XPU bit number for this extension.
-# 
--xpubit 0
-
-
-######## io_i2s_tx_mst0 --- com.arc.hardware.dfss.io_i2s_tx_mst0.1_0 ########
-
-# Create io_i2s_tx_mst0
--create com.arc.hardware.dfss.io_i2s_tx_mst0.1_0 System.CPUisle.ARCv2EM.io_i2s_tx_mst0
-
-# io_i2s_tx_mst0 --- Command line option for APEX extension component 'io_i2s_tx_mst0'.
--io_i2s_tx_mst0 true
-
-# io_i2s_tx_mst0_fs --- TX FIFO size
--io_i2s_tx_mst0_fs 8
-
-# io_i2s_tx_mst0_fw --- TX FIFO width
--io_i2s_tx_mst0_fw 16
-
-# io_i2s_tx_mst0_dma_support --- Specifies whether the DMA handshake interface is included
--io_i2s_tx_mst0_dma_support Memory-Based
-
-# assign_xpubit --- 
-#       
-# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
-# 

-# By default an extension is not assigned a bit in this register.  This means the extension is always available.
-# 

-# If you wish to assign an XPU bit number, select this option.
-# 
-# 
--assign_xpubit false
-
-# xpubit --- 
-# The XPU bit number for this extension.
-# 
--xpubit 0
-
-
-######## io_pdm_rx0 --- com.arc.hardware.dfss.io_pdm_rx0.1_0 ########
-
-# Create io_pdm_rx0
--create com.arc.hardware.dfss.io_pdm_rx0.1_0 System.CPUisle.ARCv2EM.io_pdm_rx0
-
-# io_pdm_rx0 --- Command line option for APEX extension component 'io_pdm_rx0'.
--io_pdm_rx0 true
-
-# io_pdm_rx0_ch --- Number of Stereo Channels
--io_pdm_rx0_ch 1
-
-# io_pdm_rx0_fs --- RX FIFO size
--io_pdm_rx0_fs 16
-
-# io_pdm_rx0_ns --- Maximum number of CIC stages
--io_pdm_rx0_ns 4
-
-# io_pdm_rx0_ds --- Maximum delay in the COMB filter of the CIC filter
--io_pdm_rx0_ds 2
-
-# io_pdm_rx0_dma_support --- Specifies whether the DMA handshake interface is included
--io_pdm_rx0_dma_support Memory-Based
-
-# assign_xpubit --- 
-#       
-# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group.
-# 

-# By default an extension is not assigned a bit in this register.  This means the extension is always available.
-# 

-# If you wish to assign an XPU bit number, select this option.
-# 
-# 
--assign_xpubit false
-
-# xpubit --- 
-# The XPU bit number for this extension.
-# 
--xpubit 0
-
-
-######## DCCM --- com.arc.hardware.DCCM.1_0 ########
-
-# Create DCCM
--create com.arc.hardware.DCCM.1_0 System.CPUisle.ARCv2EM.DCCM
-
-# dccm_size --- This defines the size of the Data Closely Coupled Memory (DCCM) in bytes
--dccm_size 131072
-
-# dccm_base --- Sets the initial memory region assignment for DCCM
--dccm_base 8
-
-# dccm_interleave --- Split DCCM into even/odd memory banks.
--dccm_interleave false
-
-# dccm_prot --- Specifies the type of protection built for the DCCM.
--dccm_prot None
-
-# dccm_prot_level --- Specifies the level protection.
--dccm_prot_level Data_Only
-
-# dccm_prot_exceptions --- When the core is configured with ECC or Parity, cause exception generation hardware to be created for uncorrectable errors detected on the DCCM
--dccm_prot_exceptions true
-
-# dccm_sec_lvl --- Specifies the level of secure DCCM.
--dccm_sec_lvl Non_Secure
-
-# dccm_dmi --- This enables external access through a DMI (direct memory interface) port.
--dccm_dmi true
-
-
-######## DMA Controller --- com.arc.hardware.DMA_Controller.1_0 ########
-
-# Create DMA Controller
--create com.arc.hardware.DMA_Controller.1_0 "System.CPUisle.ARCv2EM.DMA Controller"
-
-# dmac_channels --- This options specifies the number of DMA channels implemented in the DMA controller
--dmac_channels 16
-
-# dmac_fifo_depth --- This option specifies the DMA transfer FIFO depth in 32b words.
--dmac_fifo_depth 2
-
-# dmac_int_config --- None: the DMA controller cannot raise an interrupt
-# Single-External: single done and single error interrupt signal for all DMA channels, and the interrupt signals are routed to a port at the top of the EM logical hierarchy
-# Multiple-External: each DMA channel can be configured to raise separate (per-channel) done and error interrupts, and the interrupt signals are routed to ports at the top of the EM logical hierarchy
-# Single-Internal: single done and single error interrupt signals for all DMA channels, and the interrupt signals are internal to the EM core
-# Multiple-Internal: each DMA channel can be configured to raise separate (per-channel) done and error interrupts, and the interrupt signals are internal to the EM core
--dmac_int_config Multiple-Internal
-
-# dmac_separate_error_interrupts --- This specifies whether there is a separate error interrupt per DMA channel, or just one.
--dmac_separate_error_interrupts false
-
-# dmac_registers --- This option defines the number of DMA channels with their registers located in auxiliary space.
--dmac_registers 0
-
-# dmac_mem_if --- This option specifies whether the DMA controller system memory interface is integrated into the existing EM system memory interfaces or has its own interface.
--dmac_mem_if integrated
-
-# dmac_per_if --- Internal vs DW peripheral interface. Specify (in hex) which channels have the DW interface, where bit 0 corresponds to DMA channel 0, bit 1 for DMA channel 1, etc.
-# Example: 4 channel DMA controller where -dmac_per_if is set to 0x9 = DMA Channels 0 and 3 configured with the DW req interface, DMA Channels 1 and 2 configured with the internal req interface.
--dmac_per_if 0x7e00
-
-
-######## DSP --- com.arc.hardware.DSP.1_0 ########
-
-# Create DSP
--create com.arc.hardware.DSP.1_0 System.CPUisle.ARCv2EM.DSP
-
-# dsp_complex --- Enable/disable support for single cycle 16b+16b complex instructions and butterfly operations, else 2-cycle complex instructions only without butterfly support
--dsp_complex true
-
-# dsp_itu --- Enable/disable support for ITU bit-accurate 1 bit fractional shift before accumulation, else 1-bit fractional shift result after accumulation only
--dsp_itu true
-
-# dsp_divsqrt --- Enable/disable support for divide and square root operations: DIV(U), REM(U), SQRT
--dsp_divsqrt radix2
-
-# dsp_accshift --- Select support for accumulator shift operations: no supported, limited shift support only or full shift support and convergent rounding
--dsp_accshift full
-
-# dsp_impl --- The datapath components may be inferred from Verilog for better area or optimized using carry-save components for better timing
--dsp_impl optimized
-
-
-######## Data Cache --- com.arc.hardware.Data_Cache.1_0 ########
-
-# Create Data Cache
--create com.arc.hardware.Data_Cache.1_0 "System.CPUisle.ARCv2EM.Data Cache"
-
-# dc_size --- This defines the total size of the Data Cache in bytes.
--dc_size 16384
-
-# dc_ways --- This defines the number of cache ways.
--dc_ways 2
-
-# dc_bsize --- This defines the cache line length in bytes.
--dc_bsize 32
-
-# dc_feature_level --- Feature Level, indicates locking and debug feature level  00 = Basic cache, with no locking or debug features  01 = Lock and flush features supported  10 = Lock, flush and advanced debug features supported  11 = Reserved
--dc_feature_level 2
-
-# dc_uncached_region --- Enable an uncached region defined by aux reg
--dc_uncached_region false
-
-# dc_prot --- Specifies the type of protection built for DCACHE.
--dc_prot None
-
-# dc_prot_level --- Specifies the level of protection.
--dc_prot_level Data_Only
-
-# dc_prot_exceptions --- Builds exception generation hardware for uncorrectable (fatal) errors detected on DCACHE.
--dc_prot_exceptions true
-
-
-######## Debug Interface --- com.arc.hardware.Debug_Interface.1_0 ########
-
-# Create Debug Interface
--create com.arc.hardware.Debug_Interface.1_0 "System.CPUisle.ARCv2EM.Debug Interface"
-
-# dbg_en_option --- Adds an enable pin to the existing debug interface
--dbg_en_option false
-
-# secure_debug --- This enables secure debug feature
--secure_debug false
-
-# scdbg_aux_unlk --- An internal demo module will be included when enable
--scdbg_aux_unlk false
-
-# dbg_apb_option --- Adds an additional APB debug port alongside the BVCI one
--dbg_apb_option false
-
-
-######## ICCM0 --- com.arc.hardware.ICCM0.1_0 ########
-
-# Create ICCM0
--create com.arc.hardware.ICCM0.1_0 System.CPUisle.ARCv2EM.ICCM0
-
-# iccm0_size --- This defines the size of ICCM0 in bytes.This ICCM has 0 wait states.
--iccm0_size 131072
-
-# iccm0_base --- Sets the initial memory region assignment for ICCM0
--iccm0_base 6
-
-# iccm0_wide --- Creates ICCM0 as 64b memory to reduce accesses.
--iccm0_wide false
-
-# iccm0_prot --- Specifies the type of protection built for ICCM0.
--iccm0_prot None
-
-# iccm0_prot_level --- Specifies the level of protection.
--iccm0_prot_level Data_Only
-
-# iccm0_prot_exceptions --- When the core is configured with ECC or Parity, cause exception generation hardware to be created for uncorrectable errors detected on the ICCM0
--iccm0_prot_exceptions true
-
-# iccm0_sec_lvl --- Specifies the level of secure ICCM0.
--iccm0_sec_lvl Non_Secure
-
-# iccm0_dmi --- This enables external access through a DMI (direct memory interface) port.
--iccm0_dmi true
-
-
-######## Instruction Cache --- com.arc.hardware.Instruction_Cache.1_0 ########
-
-# Create Instruction Cache
--create com.arc.hardware.Instruction_Cache.1_0 "System.CPUisle.ARCv2EM.Instruction Cache"
-
-# ic_size --- This defines the total size of the instruction cache in bytes.
--ic_size 16384
-
-# ic_ways --- This defines the number of cache ways
--ic_ways 2
-
-# ic_bsize --- This defines the cache line length in bytes.
--ic_bsize 64
-
-# ic_disable_on_reset --- The instruction cache may be enabled immediately after reset, depending on this option.  If this option is enabled, the last cache operation is set to failed, and the direct cache-RAM access is enabled.  Furthermore, the instruction cache is invalidated  all cache lines are invalidated and unlocked, and the tag RAM is cleared.
--ic_disable_on_reset false
-
-# ic_feature_level --- This defines the feature level of the cache.
--ic_feature_level 1
-
-# ic_pwr_opt_level --- This selects power-optimization options in the micro-architecture of the instruction cache.
--ic_pwr_opt_level 0
-
-# ic_prot --- Specifies the type of protection built for ICACHE.
--ic_prot None
-
-# ic_prot_level --- Specifies the level of protection.
--ic_prot_level Data_Only
-
-# ic_prot_exceptions --- Builds exception generation hardware for uncorrectable (fatal) errors detected on ICACHE.
--ic_prot_exceptions true
-
-
-######## Interrupt Controller --- com.arc.hardware.Interrupt_Controller.1_0 ########
-
-# Create Interrupt Controller
--create com.arc.hardware.Interrupt_Controller.1_0 "System.CPUisle.ARCv2EM.Interrupt Controller"
-
-# number_of_interrupts --- This is the total number of interrupts available to the core.  Some interrupts are allocated statically to a specific interrupt line (for example, timer interrupts).  For more information on Interrupt and register-file options, see DesignWare ARCv2 ISA Programmers Reference Manual.
--number_of_interrupts 96
-
-# number_of_levels --- Priority levels in the interrupt controller.
--number_of_levels 4
-
-# external_interrupts --- This is the total number of interrupt pins available for external system components.  This parameter must be less than the total number of interrupts.
--external_interrupts 77
-
-# firq_option --- This enables the fast-interrupts option, (priority level 0 interrupts), which uses an alternate register bank (if configured) instead of saving the context to memory.
--firq_option true
-
-
-######## JTAG Interface --- com.arc.hardware.JTAG_Interface.1_0 ########
-
-# Create JTAG Interface
--create com.arc.hardware.JTAG_Interface.1_0 "System.CPUisle.ARCv2EM.JTAG Interface"
-
-######## Timer 0 --- com.arc.hardware.Timer_0.1_0 ########
-
-# Create Timer 0
--create com.arc.hardware.Timer_0.1_0 "System.CPUisle.ARCv2EM.Timer 0"
-
-# timer_0_int_level --- This sets the interrupt level (and implicitly the priority: level 0 is highest) of timer 0.
--timer_0_int_level 1
-
-
-######## Watchdog Timer --- com.arc.hardware.Watchdog_Timer.1_0 ########
-
-# Create Watchdog Timer
--create com.arc.hardware.Watchdog_Timer.1_0 "System.CPUisle.ARCv2EM.Watchdog Timer"
-
-# watchdog_size --- Specifies the bit width of timer's internal counter.
--watchdog_size 32
-
-# watchdog_clk --- Specifies whether the timer should be driven from a separate clock.
--watchdog_clk false
-
-
-######## Real-time Counter --- com.arc.hardware.Real_time_Counter.1_0 ########
-
-# Create Real-time Counter
--create com.arc.hardware.Real_time_Counter.1_0 "System.CPUisle.ARCv2EM.Real-time Counter"
-
-######## SmaRT --- com.arc.hardware.SmaRT.1_0 ########
-
-# Create SmaRT
--create com.arc.hardware.SmaRT.1_0 System.CPUisle.ARCv2EM.SmaRT
-
-# smart_stack_entries --- This specifies the number of entries in the trace buffer.
--smart_stack_entries 8
-
-# smart_implementation --- Flip-flop = FF-based design.  Memory = memory-based design (provides better density for larger trace buffers).
--smart_implementation flip-flop
-
-
-######## XY --- com.arc.hardware.XY.1_0 ########
-
-# Create XY
--create com.arc.hardware.XY.1_0 System.CPUisle.ARCv2EM.XY
-
-# xy_config --- XY memory configuration:
-# One memory: DCCM only.
-# Two memories: DCCM + Y.
-# Three memories: DCCM + X + Y.
--xy_config dccm_x_y
-
-# xy_size --- Size of X and Y memories if included.
-# X and Y memories both have the same configured size.
--xy_size 16384
-
-# xy_interleave --- Split XY memories into odd/even instances to enable single cycle unaligned access.
--xy_interleave false
-
-# xy_x_base --- Base region for X memory. All accesses to this region will initiate a transfer on the X memory.
--xy_x_base 9
-
-# xy_y_base --- Base region for Y memory. All accesses to this region will initiate a transfer on the Y memory.
--xy_y_base 10
-
-
-######## AGU --- com.arc.hardware.AGU.1_0 ########
-
-# Create AGU
--create com.arc.hardware.AGU.1_0 System.CPUisle.ARCv2EM.AGU
-
-# agu_size --- Predefined configurations of modifiers, address 
-# pointers and offset registers                   
-# 
-# 
-#         address     address                     
-#         pointers    offset regs      modifiers  
-#        ----------- --------------- ------------ 
-# small:     4           2                 4      
-# medium:    8           4                 12     
-# large:     12          8                 24     
-# 

-# 
--agu_size small
-
-# agu_accord --- Enable the accordion stage if operating frequency is critical
--agu_accord true
-
-# agu_wb_depth --- Write buffer depth
--agu_wb_depth 4
-
-
-######## Actionpoints --- com.arc.hardware.Actionpoints.1_0 ########
-
-# Create Actionpoints
--create com.arc.hardware.Actionpoints.1_0 System.CPUisle.ARCv2EM.Actionpoints
-
-# num_actionpoints --- This is the number of trigger events available.
--num_actionpoints 8
-
-# aps_feature --- Selects Actionpoint feature set
--aps_feature min
-
-
-######## Bit stream --- com.arc.hardware.Bit_stream.1_0 ########
-
-# Create Bit stream
--create com.arc.hardware.Bit_stream.1_0 "System.CPUisle.ARCv2EM.Bit stream"
-
-######## Floating-point unit --- com.arc.hardware.Floating_point_unit.1_0 ########
-
-# Create Floating-point unit
--create com.arc.hardware.Floating_point_unit.1_0 "System.CPUisle.ARCv2EM.Floating-point unit"
-
-# fpu_dp_assist --- This enables double-precision acceleration instructions.
--fpu_dp_assist true
-
-# fpu_fma_option --- This enables the fused multiply-add & multiply-subtract instructions.
--fpu_fma_option true
-
-# fpu_mas_cycles --- Make mul/add/sub multicycle to achieve a higher clock speed.
--fpu_mas_cycles 2
-
-# fpu_pipe_impl --- FPU pipelined implementation
--fpu_pipe_impl true
-
-# fpu_div_option --- This enables divide & square-root acceleration
--fpu_div_option true
-
-# fpu_div_cycles --- Controls div/sqrt implementation.
--fpu_div_cycles 17
-
-
-######## Memory Protection Unit --- com.arc.hardware.Memory_Protection_Unit.1_0 ########
-
-# Create Memory Protection Unit
--create com.arc.hardware.Memory_Protection_Unit.1_0 "System.CPUisle.ARCv2EM.Memory Protection Unit"
-
-# mpu_num_regions --- Number of configured memory regions.
--mpu_num_regions 8
-
-# mpu_32b --- Set the minimal region size to be 32 byte instead of 2KB.
--mpu_32b false
-
-# mpu_sid_option --- It will enable SID support in Secure Shield
--mpu_sid_option false
-
-
-######## Real-time trace producer --- com.arc.hardware.Real_time_trace_producer.1_0 ########
-
-# Create Real-time trace producer
--create com.arc.hardware.Real_time_trace_producer.1_0 "System.CPUisle.ARCv2EM.Real-time trace producer"
-
-# rtt_feature_level --- 'small' means that program trace only is available.  `medium' adds data trace.  `full' adds core and aux register trace.
--rtt_feature_level small
-
-
-######## ARCv2EM CCT --- cct.1_0 ########
-
-# Create ARCv2EM CCT
--create cct.1_0 "System.ARCv2EM CCT"
-
-# cct --- 
-# 	Option used to add a CCT to the design for command-line builds
-# 	Without this architect can't add this component to a build
-# 	via a cmdline -create command.  
-# 	with old scripts.
-# 	
--cct true
-
-# no_hostlink --- 
-# This prevents the inclusion of the hostlink library when compiling
-# C or C++ programs.  The resultant executable, if it contains printfs,
-# will print to an internal fixed buffer __mwwrite_buf.  
-# Other hostlink operations that require debugger assistance, such as file
-# opens, will fail.
-# 
-# Hostlink references incur memory cycles at unpredictable times and 
-# so can perturb cycle-timing results.  Without hostlink,
-# the debugger will not in any way interfere with the target while it is running.  
-# Therefore this option is useful for simulation in which you want precisely the
-# same cycle timing to occur each time you run, or for accurate power consumption results.
-# 	
--cct_no_hostlink false
-
-# has_subsystem_cct_flow --- 
-# The above option will check for the presence of subsystem component in the build configuration and suitably modifies the Makefile for the sub-system environment.
-# 	
--has_subsystem_cct_flow false
-
-
-######## BusFabric --- com.arc.hardware.ARCv2MSS.BusFabric.1_0 ########
-
-# Create BusFabric
--create com.arc.hardware.ARCv2MSS.BusFabric.1_0 System.BusFabric
-
-######## ClkCtrl --- com.arc.hardware.ARCv2MSS.ClkCtrl.1_0 ########
-
-# Create ClkCtrl
--create com.arc.hardware.ARCv2MSS.ClkCtrl.1_0 System.ClkCtrl
-
-######## DSP Software --- com.arc.software.dfss.sw_dsp.1_0 ########
-
-# Create DSP Software
--create com.arc.software.dfss.sw_dsp.1_0 "System.DSP Software"
-
-# sw_dsp --- Command line option for Software element 'DSP Software'
--sw_dsp true
-
-
-######## EMSDP_BOARD --- com.arc.hardware.ARCv2MSS.EMSDP_BOARD.1_0 ########
-
-# Create EMSDP_BOARD
--create com.arc.hardware.ARCv2MSS.EMSDP_BOARD.1_0 System.EMSDP_BOARD
-
-# emsdp_sys_freq --- Select the core frequency.
--emsdp_sys_freq 40
-
-
-######## IO Software --- com.arc.software.dfss.sw_io.1_0 ########
-
-# Create IO Software
--create com.arc.software.dfss.sw_io.1_0 "System.IO Software"
-
-# sw_io --- Command line option for Software element 'IO Software'
--sw_io true
-
-
-######## Implementation --- com.arc.hardware.implementation.1_0 ########
-
-# Create Implementation
--create com.arc.hardware.implementation.1_0 System.Implementation
-
-# ClockSpeed --- Target clock speed of the system
--clock_speed 10
-
-# DDR2_clk_Ratio --- DDR2 Clock Vs System Clock Ratio
-# 2x
-# 3x
-# 4x
--ddr2_clk_ratio 3x
-
-# ClockSkew --- The clock skew for the system
--clock_skew 0.2
-
-# HoldMargin --- Margin for hold time checks
--hold_margin 0.05
-
-# Floorplan --- Floorplan definition for relative placement of  RAMs (at CPU-level) or the placement of the rams and CPU hard cores (at multicore level)
--floorplan em4_sensor
-
-# JTAGFrequency --- Select the frequency of the JTAG clock Tck (in MHz).
-# 
-# The JTAG clock speed has to be less than 1/2 of the cpu clock otherwise the signals on the BVCI interface are not guaranteed to be valid.
-# 
-# NOTE: The RTL simulations will work when the JTAG clock frequency is set to half the CPU clock, however this may not be the case when simulating at gate level due to delays on the IO pads.
-# 
-# The default is set to 10 MHz so that there is no conflict when simulating with an ARCangel3 at 30MHz. (30 > 10*2)
-# 
-# The speed of simulation can be greatly increased by using a faster JTAG clock, but a dependency will warn if it exceeds 1/2 of the cpu clock.
-# 
--jtag_tclk 4
-
-# execution_trace_level --- 
-# This traces committed instructions as they execute, and gathers statistics
-# visible in the debugger for counting instructions & cycle delays.
-# At the "stats" level ony the statistics are gathered and no trace is printed.
-# "file" is equivalent to "full", but the results go to a trace .txt file instead.
-# 
--execution_trace_level stats
-
-# tb_trace --- 
-# Enable instruction execution trace.
-# This is available to arc_dev licensees (internal developers) only.
-# 
--tb_trace false
-
-# zero_based_arcnum --- 
-# In a multicore build, number ARCs from 0.
-# If this is not selected, arcs are numbered from 1.
-# (This provides the initial value to the arcnum signal.)
-# 
--zero_based_arcnum true
-
-# generate_ipxact --- 
-# Generate ipxact.xml file describing the CPUisle or archipelago frontier
-# 
--generate_ipxact false
-
-# ipxact_relative_path_names --- 
-# Use relative path names for Verilog files in the ipxact.
-# Otherwise, absolute path names are used.
-# 
--ipxact_relative_path_names true
-
-# optional_encryption --- 
-# When selected, encrypted RTL output is generated.
-# 	
--optional_encryption false
-
-# ignore_encrypt_license --- 
-# When selected, pretend the encryption license is missing.  For testing.
-# 	
--ignore_encrypt_license false
-
-# ignore_clear_license --- 
-# When selected, pretend the cleartest license is missing.  For testing.
-# 	
--ignore_clear_license false
-
-# OPTION_require_archipelago --- 
-# When selected, force use of archipelago.  This is for testing purposes.
-# 	
--require_archipelago false
-
-
-######## Infrastructure Software --- com.arc.software.dfss.sw_infra.1_0 ########
-
-# Create Infrastructure Software
--create com.arc.software.dfss.sw_infra.1_0 "System.Infrastructure Software"
-
-# sw_infra --- Command line option for Software element 'Infrastructure Software'
--sw_infra true
-
-# templateName --- Template name
--template_name siss_combo_sensor_dsp
-
-
-######## subsys_infra --- com.arc.hardware.dfss.subsys_infra.1_0 ########
-
-# Create subsys_infra
--create com.arc.hardware.dfss.subsys_infra.1_0 System.subsys_infra
-
-# subsys_infra --- Command line option for EIA glue logic.
--subsys_infra true
-
-# internal_interrupt --- Connect the IO interrupts internally
--internal_interrupt true
-
-# internal_dma_handshake --- Connect the DMA handshake signals internally
--internal_dma_handshake true
-
-# spi_tb_sw_test_mode --- 
-# This is a secret option, not seen by customers.
-# If you check this, the SPI peripheral's testbenches will be set to SW test mode:
-# The serial interface of the first SPI master io_spi_mstN peripheral is connected to all SPI slave peripherals io_spi_slvN.
-# This is used for testing the SW drivers.
-# 	
--spi_tb_sw_test_mode false
-
-# i3c_tb_sw_test_mode --- 
-# This is a secret option, not seen by customers.
-# If you check this, the I3C peripheral's testbenches will be set to SW test mode:
-# The serial interface of the io_i3cN peripheral is connected to the I2C slave peripherals io_i2c_slv0.
-# This is used for testing the SW drivers.
-# 	
--i3c_tb_sw_test_mode false
-
-# subsys_apex_offset --- Subsystem APEX address offset in the AUX address space. The aperture used by the subsystem is fixed to 0x0010_0000. In general, the APEX address offset must be in the range from 0x0010_0000 to 0xFFF0_0000. However, if your design includes the "UAUX Interface" component, then the APEX address offset must be in the range from 0x0010_0000 to 0x7FF0_0000 to avoid address conflicts with any UAUX components.
--subsys_apex_offset 0x8000_0000
-
-# subsys_uaux_offset --- Subsystem UAUX address offset in the UAUX address space. The UAUX address offset must be an integer multiple of 0x0010_0000 in the range from 0x0000_0000 to 0x7FF0_0000. The aperture reserved for the subsystem is fixed to 0x0010_0000.
--subsys_uaux_offset 0x10_0000
-
-
-######## ARC_RTT --- com.arc.hardware.ARC_RTT.1_0 ########
-
-# Create ARC_RTT
--create com.arc.hardware.ARC_RTT.1_0 System.ARC_RTT
-
-# rtt_coresight_option --- Please select CoreSight ATB interface to offload the data from RTT 
--rtt_coresight_option false
-
-# rtt_num_filters --- Please select the Number of RTT Address Filters 
--rtt_num_filters 8
-
-# rtt_atb_ratio --- Sets the clock ratio for the ATB offload port
--rtt_atb_ratio 3
-
-# has_nexus_if --- Please select Nexus interface to offload the data from RTT 
--has_nexus_if true
-
-# has_on_chip_mem --- Please select the on-chip memory option to store the trace data in shared memory 
--has_on_chip_mem true
-
-# nexus_data_wdt --- Please select the Nexus Data Width to offload the data from RTT 
--nexus_data_wdt 16
-
-# internal_memory_size --- Please select internal memory size to capture the trace data 
--internal_memory_size 16k
-
-# ram_type --- Please select Types of internal memories to be inferred for the logic 
--ram_type 1_PORT
-
-# power_domains --- Adds isolation signal inputs/power switch controls for use in UPF flow when configuring power domains.
--rtt_power_domains false
-
-
-######## Tool Configuration --- cgen.1_0 ########
-
-# Create Tool Configuration
--create cgen.1_0 "System.Tool Configuration"
-
-# mwdt_version --- Selects the MetaWare version to be used with the TCF file.
-# Change from the default to an older or newer toolset version if you want the TCF file to be used with an older or newer version of the MetaWare tools.
--mwdt_version M-2017.03
-
-# code_base_addr --- 
-# The base address to assign to the executable code segment in the linker command file when there is no ICCM in the build.  This value is ignored when there is an ICCM.
-# 
--code_base_addr 0x0
-
-# data_base_addr --- 
-# The base address to assign to the data segment in the linker command file when the data is not being mapped to a DCCM.  This value is ignored when the data segment is mapped to a DCCM, as in that case the base address of the DCCM memory is used.
-# 
-# A value of 0xffffffff means that the data segment will not be mapped to any specific address.
-# 
--data_base_addr 0xffff_ffff
-
-# underscores_in_numbers --- Use underscores in hex numbers to improve readability.
--underscores_in_numbers false
-
-# tcf_rebrand --- Alternate branding of TCF (not used)
--rebrand false
-
-
-]]>
-  
-  
-    
-  
-  
-    
-  
-  
-    
-  
-  
-    
-  
-  
-     ICCM0
-
-    GROUP BLOCK(4): {
-	/* _SDA_BASE_ computed implicitly */
-        .sdata?: {}
-        .sbss?: {}
-        * (DATA): {}
-        * (BSS): {}
-       .stack ALIGN(4) SIZE(DEFINED _STACKSIZE?_STACKSIZE:65536): {}
-       .heap? ALIGN(4) SIZE(DEFINED _HEAPSIZE?_HEAPSIZE:0): {}
-	} > SYSTEM2
-    GROUP BLOCK(4): {
-        .Xdata? : {}
-        } > XCCM
-    GROUP BLOCK(4): {
-        .Ydata? : {}
-        } > YCCM
-    GROUP BLOCK(4) : {
-        .vectors (TEXT) SIZE(DEFINED _IVTSIZE?_IVTSIZE:756): {} = FILL(0xa5a5a5a5,4)
-        } > IVT
-    }
-
-]]>
-  
-  
-    
-  
-  
-     0x07, sub_opcode => 0x1E , latency_cycles => 8)
-
-// User extension instruction - dsp_sin
-extern long dsp_sin(long);
-#pragma intrinsic(dsp_sin, opcode => 0x07, sub_opcode => 0x1F , latency_cycles => 8)
-
-#define APEX_COM_ARC_HARDWARE_DFSS_DSP_SINCOS_PRESENT	1
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_GPIO0_PRESENT	1
-
-// User extension aux register io_gpio0_debounce
-#define AR_IO_GPIO0_DEBOUNCE 0x80017048
-#pragma Aux_register(0x80017048, name=>"io_gpio0_debounce")
-
-// User extension aux register io_gpio0_clken
-#define AR_IO_GPIO0_CLKEN 0x80017080
-#pragma Aux_register(0x80017080, name=>"io_gpio0_clken")
-
-// User extension aux register io_gpio0_swporta_dr
-#define AR_IO_GPIO0_SWPORTA_DR 0x80017000
-#pragma Aux_register(0x80017000, name=>"io_gpio0_swporta_dr")
-
-// User extension aux register io_gpio0_swporta_ddr
-#define AR_IO_GPIO0_SWPORTA_DDR 0x80017004
-#pragma Aux_register(0x80017004, name=>"io_gpio0_swporta_ddr")
-
-// User extension aux register io_gpio0_inten
-#define AR_IO_GPIO0_INTEN 0x80017030
-#pragma Aux_register(0x80017030, name=>"io_gpio0_inten")
-
-// User extension aux register io_gpio0_intmask
-#define AR_IO_GPIO0_INTMASK 0x80017034
-#pragma Aux_register(0x80017034, name=>"io_gpio0_intmask")
-
-// User extension aux register io_gpio0_inttype_level
-#define AR_IO_GPIO0_INTTYPE_LEVEL 0x80017038
-#pragma Aux_register(0x80017038, name=>"io_gpio0_inttype_level")
-
-// User extension aux register io_gpio0_int_polarity
-#define AR_IO_GPIO0_INT_POLARITY 0x8001703c
-#pragma Aux_register(0x8001703c, name=>"io_gpio0_int_polarity")
-
-// User extension aux register io_gpio0_intstatus
-#define AR_IO_GPIO0_INTSTATUS 0x80017040
-#pragma Aux_register(0x80017040, name=>"io_gpio0_intstatus")
-
-// User extension aux register io_gpio0_raw_intstatus
-#define AR_IO_GPIO0_RAW_INTSTATUS 0x80017044
-#pragma Aux_register(0x80017044, name=>"io_gpio0_raw_intstatus")
-
-// User extension aux register io_gpio0_porta_eoi
-#define AR_IO_GPIO0_PORTA_EOI 0x8001704c
-#pragma Aux_register(0x8001704c, name=>"io_gpio0_porta_eoi")
-
-// User extension aux register io_gpio0_ext_porta
-#define AR_IO_GPIO0_EXT_PORTA 0x80017050
-#pragma Aux_register(0x80017050, name=>"io_gpio0_ext_porta")
-
-// User extension aux register io_gpio0_ls_sync
-#define AR_IO_GPIO0_LS_SYNC 0x80017060
-#pragma Aux_register(0x80017060, name=>"io_gpio0_ls_sync")
-
-// User extension aux register io_gpio0_int_bothedge
-#define AR_IO_GPIO0_INT_BOTHEDGE 0x80017068
-#pragma Aux_register(0x80017068, name=>"io_gpio0_int_bothedge")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2C_MST0_PRESENT	1
-
-// User extension aux register io_i2c_mst0_clken
-#define AR_IO_I2C_MST0_CLKEN 0x800120c0
-#pragma Aux_register(0x800120c0, name=>"io_i2c_mst0_clken")
-
-// User extension aux register io_i2c_mst0_con
-#define AR_IO_I2C_MST0_CON 0x80012000
-#pragma Aux_register(0x80012000, name=>"io_i2c_mst0_con")
-
-// User extension aux register io_i2c_mst0_tar
-#define AR_IO_I2C_MST0_TAR 0x80012004
-#pragma Aux_register(0x80012004, name=>"io_i2c_mst0_tar")
-
-// User extension aux register io_i2c_mst0_data_cmd
-#define AR_IO_I2C_MST0_DATA_CMD 0x80012010
-#pragma Aux_register(0x80012010, name=>"io_i2c_mst0_data_cmd")
-
-// User extension aux register io_i2c_mst0_ss_scl_hcnt
-#define AR_IO_I2C_MST0_SS_SCL_HCNT 0x80012014
-#pragma Aux_register(0x80012014, name=>"io_i2c_mst0_ss_scl_hcnt")
-
-// User extension aux register io_i2c_mst0_ss_scl_lcnt
-#define AR_IO_I2C_MST0_SS_SCL_LCNT 0x80012018
-#pragma Aux_register(0x80012018, name=>"io_i2c_mst0_ss_scl_lcnt")
-
-// User extension aux register io_i2c_mst0_fs_scl_hcnt
-#define AR_IO_I2C_MST0_FS_SCL_HCNT 0x8001201c
-#pragma Aux_register(0x8001201c, name=>"io_i2c_mst0_fs_scl_hcnt")
-
-// User extension aux register io_i2c_mst0_fs_scl_lcnt
-#define AR_IO_I2C_MST0_FS_SCL_LCNT 0x80012020
-#pragma Aux_register(0x80012020, name=>"io_i2c_mst0_fs_scl_lcnt")
-
-// User extension aux register io_i2c_mst0_intr_stat
-#define AR_IO_I2C_MST0_INTR_STAT 0x8001202c
-#pragma Aux_register(0x8001202c, name=>"io_i2c_mst0_intr_stat")
-
-// User extension aux register io_i2c_mst0_intr_mask
-#define AR_IO_I2C_MST0_INTR_MASK 0x80012030
-#pragma Aux_register(0x80012030, name=>"io_i2c_mst0_intr_mask")
-
-// User extension aux register io_i2c_mst0_raw_intr_stat
-#define AR_IO_I2C_MST0_RAW_INTR_STAT 0x80012034
-#pragma Aux_register(0x80012034, name=>"io_i2c_mst0_raw_intr_stat")
-
-// User extension aux register io_i2c_mst0_rx_tl
-#define AR_IO_I2C_MST0_RX_TL 0x80012038
-#pragma Aux_register(0x80012038, name=>"io_i2c_mst0_rx_tl")
-
-// User extension aux register io_i2c_mst0_tx_tl
-#define AR_IO_I2C_MST0_TX_TL 0x8001203c
-#pragma Aux_register(0x8001203c, name=>"io_i2c_mst0_tx_tl")
-
-// User extension aux register io_i2c_mst0_clr_intr
-#define AR_IO_I2C_MST0_CLR_INTR 0x80012040
-#pragma Aux_register(0x80012040, name=>"io_i2c_mst0_clr_intr")
-
-// User extension aux register io_i2c_mst0_clr_rx_under
-#define AR_IO_I2C_MST0_CLR_RX_UNDER 0x80012044
-#pragma Aux_register(0x80012044, name=>"io_i2c_mst0_clr_rx_under")
-
-// User extension aux register io_i2c_mst0_clr_rx_over
-#define AR_IO_I2C_MST0_CLR_RX_OVER 0x80012048
-#pragma Aux_register(0x80012048, name=>"io_i2c_mst0_clr_rx_over")
-
-// User extension aux register io_i2c_mst0_clr_tx_over
-#define AR_IO_I2C_MST0_CLR_TX_OVER 0x8001204c
-#pragma Aux_register(0x8001204c, name=>"io_i2c_mst0_clr_tx_over")
-
-// User extension aux register io_i2c_mst0_clr_tx_abrt
-#define AR_IO_I2C_MST0_CLR_TX_ABRT 0x80012054
-#pragma Aux_register(0x80012054, name=>"io_i2c_mst0_clr_tx_abrt")
-
-// User extension aux register io_i2c_mst0_clr_activity
-#define AR_IO_I2C_MST0_CLR_ACTIVITY 0x8001205c
-#pragma Aux_register(0x8001205c, name=>"io_i2c_mst0_clr_activity")
-
-// User extension aux register io_i2c_mst0_clr_stop_det
-#define AR_IO_I2C_MST0_CLR_STOP_DET 0x80012060
-#pragma Aux_register(0x80012060, name=>"io_i2c_mst0_clr_stop_det")
-
-// User extension aux register io_i2c_mst0_clr_start_det
-#define AR_IO_I2C_MST0_CLR_START_DET 0x80012064
-#pragma Aux_register(0x80012064, name=>"io_i2c_mst0_clr_start_det")
-
-// User extension aux register io_i2c_mst0_enable
-#define AR_IO_I2C_MST0_ENABLE 0x8001206c
-#pragma Aux_register(0x8001206c, name=>"io_i2c_mst0_enable")
-
-// User extension aux register io_i2c_mst0_status
-#define AR_IO_I2C_MST0_STATUS 0x80012070
-#pragma Aux_register(0x80012070, name=>"io_i2c_mst0_status")
-
-// User extension aux register io_i2c_mst0_txflr
-#define AR_IO_I2C_MST0_TXFLR 0x80012074
-#pragma Aux_register(0x80012074, name=>"io_i2c_mst0_txflr")
-
-// User extension aux register io_i2c_mst0_rxflr
-#define AR_IO_I2C_MST0_RXFLR 0x80012078
-#pragma Aux_register(0x80012078, name=>"io_i2c_mst0_rxflr")
-
-// User extension aux register io_i2c_mst0_sda_hold
-#define AR_IO_I2C_MST0_SDA_HOLD 0x8001207c
-#pragma Aux_register(0x8001207c, name=>"io_i2c_mst0_sda_hold")
-
-// User extension aux register io_i2c_mst0_tx_abrt_source
-#define AR_IO_I2C_MST0_TX_ABRT_SOURCE 0x80012080
-#pragma Aux_register(0x80012080, name=>"io_i2c_mst0_tx_abrt_source")
-
-// User extension aux register io_i2c_mst0_enable_status
-#define AR_IO_I2C_MST0_ENABLE_STATUS 0x8001209c
-#pragma Aux_register(0x8001209c, name=>"io_i2c_mst0_enable_status")
-
-// User extension aux register io_i2c_mst0_fs_spklen
-#define AR_IO_I2C_MST0_FS_SPKLEN 0x800120a0
-#pragma Aux_register(0x800120a0, name=>"io_i2c_mst0_fs_spklen")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2C_SLV0_PRESENT	1
-
-// User extension aux register io_i2c_slv0_clken
-#define AR_IO_I2C_SLV0_CLKEN 0x800130c0
-#pragma Aux_register(0x800130c0, name=>"io_i2c_slv0_clken")
-
-// User extension aux register io_i2c_slv0_con
-#define AR_IO_I2C_SLV0_CON 0x80013000
-#pragma Aux_register(0x80013000, name=>"io_i2c_slv0_con")
-
-// User extension aux register io_i2c_slv0_sar
-#define AR_IO_I2C_SLV0_SAR 0x80013008
-#pragma Aux_register(0x80013008, name=>"io_i2c_slv0_sar")
-
-// User extension aux register io_i2c_slv0_data_cmd
-#define AR_IO_I2C_SLV0_DATA_CMD 0x80013010
-#pragma Aux_register(0x80013010, name=>"io_i2c_slv0_data_cmd")
-
-// User extension aux register io_i2c_slv0_intr_stat
-#define AR_IO_I2C_SLV0_INTR_STAT 0x8001302c
-#pragma Aux_register(0x8001302c, name=>"io_i2c_slv0_intr_stat")
-
-// User extension aux register io_i2c_slv0_intr_mask
-#define AR_IO_I2C_SLV0_INTR_MASK 0x80013030
-#pragma Aux_register(0x80013030, name=>"io_i2c_slv0_intr_mask")
-
-// User extension aux register io_i2c_slv0_raw_intr_stat
-#define AR_IO_I2C_SLV0_RAW_INTR_STAT 0x80013034
-#pragma Aux_register(0x80013034, name=>"io_i2c_slv0_raw_intr_stat")
-
-// User extension aux register io_i2c_slv0_rx_tl
-#define AR_IO_I2C_SLV0_RX_TL 0x80013038
-#pragma Aux_register(0x80013038, name=>"io_i2c_slv0_rx_tl")
-
-// User extension aux register io_i2c_slv0_tx_tl
-#define AR_IO_I2C_SLV0_TX_TL 0x8001303c
-#pragma Aux_register(0x8001303c, name=>"io_i2c_slv0_tx_tl")
-
-// User extension aux register io_i2c_slv0_clr_intr
-#define AR_IO_I2C_SLV0_CLR_INTR 0x80013040
-#pragma Aux_register(0x80013040, name=>"io_i2c_slv0_clr_intr")
-
-// User extension aux register io_i2c_slv0_clr_rx_under
-#define AR_IO_I2C_SLV0_CLR_RX_UNDER 0x80013044
-#pragma Aux_register(0x80013044, name=>"io_i2c_slv0_clr_rx_under")
-
-// User extension aux register io_i2c_slv0_clr_rx_over
-#define AR_IO_I2C_SLV0_CLR_RX_OVER 0x80013048
-#pragma Aux_register(0x80013048, name=>"io_i2c_slv0_clr_rx_over")
-
-// User extension aux register io_i2c_slv0_clr_tx_over
-#define AR_IO_I2C_SLV0_CLR_TX_OVER 0x8001304c
-#pragma Aux_register(0x8001304c, name=>"io_i2c_slv0_clr_tx_over")
-
-// User extension aux register io_i2c_slv0_clr_rd_req
-#define AR_IO_I2C_SLV0_CLR_RD_REQ 0x80013050
-#pragma Aux_register(0x80013050, name=>"io_i2c_slv0_clr_rd_req")
-
-// User extension aux register io_i2c_slv0_clr_tx_abrt
-#define AR_IO_I2C_SLV0_CLR_TX_ABRT 0x80013054
-#pragma Aux_register(0x80013054, name=>"io_i2c_slv0_clr_tx_abrt")
-
-// User extension aux register io_i2c_slv0_clr_rx_done
-#define AR_IO_I2C_SLV0_CLR_RX_DONE 0x80013058
-#pragma Aux_register(0x80013058, name=>"io_i2c_slv0_clr_rx_done")
-
-// User extension aux register io_i2c_slv0_clr_activity
-#define AR_IO_I2C_SLV0_CLR_ACTIVITY 0x8001305c
-#pragma Aux_register(0x8001305c, name=>"io_i2c_slv0_clr_activity")
-
-// User extension aux register io_i2c_slv0_clr_stop_det
-#define AR_IO_I2C_SLV0_CLR_STOP_DET 0x80013060
-#pragma Aux_register(0x80013060, name=>"io_i2c_slv0_clr_stop_det")
-
-// User extension aux register io_i2c_slv0_clr_start_det
-#define AR_IO_I2C_SLV0_CLR_START_DET 0x80013064
-#pragma Aux_register(0x80013064, name=>"io_i2c_slv0_clr_start_det")
-
-// User extension aux register io_i2c_slv0_enable
-#define AR_IO_I2C_SLV0_ENABLE 0x8001306c
-#pragma Aux_register(0x8001306c, name=>"io_i2c_slv0_enable")
-
-// User extension aux register io_i2c_slv0_status
-#define AR_IO_I2C_SLV0_STATUS 0x80013070
-#pragma Aux_register(0x80013070, name=>"io_i2c_slv0_status")
-
-// User extension aux register io_i2c_slv0_txflr
-#define AR_IO_I2C_SLV0_TXFLR 0x80013074
-#pragma Aux_register(0x80013074, name=>"io_i2c_slv0_txflr")
-
-// User extension aux register io_i2c_slv0_rxflr
-#define AR_IO_I2C_SLV0_RXFLR 0x80013078
-#pragma Aux_register(0x80013078, name=>"io_i2c_slv0_rxflr")
-
-// User extension aux register io_i2c_slv0_sda_hold
-#define AR_IO_I2C_SLV0_SDA_HOLD 0x8001307c
-#pragma Aux_register(0x8001307c, name=>"io_i2c_slv0_sda_hold")
-
-// User extension aux register io_i2c_slv0_tx_abrt_source
-#define AR_IO_I2C_SLV0_TX_ABRT_SOURCE 0x80013080
-#pragma Aux_register(0x80013080, name=>"io_i2c_slv0_tx_abrt_source")
-
-// User extension aux register io_i2c_slv0_sda_setup
-#define AR_IO_I2C_SLV0_SDA_SETUP 0x80013094
-#pragma Aux_register(0x80013094, name=>"io_i2c_slv0_sda_setup")
-
-// User extension aux register io_i2c_slv0_enable_status
-#define AR_IO_I2C_SLV0_ENABLE_STATUS 0x8001309c
-#pragma Aux_register(0x8001309c, name=>"io_i2c_slv0_enable_status")
-
-// User extension aux register io_i2c_slv0_fs_spklen
-#define AR_IO_I2C_SLV0_FS_SPKLEN 0x800130a0
-#pragma Aux_register(0x800130a0, name=>"io_i2c_slv0_fs_spklen")
-
-// User extension aux register io_i2c_slv0_clr_restart_det
-#define AR_IO_I2C_SLV0_CLR_RESTART_DET 0x800130a8
-#pragma Aux_register(0x800130a8, name=>"io_i2c_slv0_clr_restart_det")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_SPI_MST0_PRESENT	1
-
-// User extension aux register io_spi_mst0_ctrlr0
-#define AR_IO_SPI_MST0_CTRLR0 0x80010000
-#pragma Aux_register(0x80010000, name=>"io_spi_mst0_ctrlr0")
-
-// User extension aux register io_spi_mst0_ctrlr1
-#define AR_IO_SPI_MST0_CTRLR1 0x80010001
-#pragma Aux_register(0x80010001, name=>"io_spi_mst0_ctrlr1")
-
-// User extension aux register io_spi_mst0_spien
-#define AR_IO_SPI_MST0_SPIEN 0x80010002
-#pragma Aux_register(0x80010002, name=>"io_spi_mst0_spien")
-
-// User extension aux register io_spi_mst0_ser
-#define AR_IO_SPI_MST0_SER 0x80010004
-#pragma Aux_register(0x80010004, name=>"io_spi_mst0_ser")
-
-// User extension aux register io_spi_mst0_baudr
-#define AR_IO_SPI_MST0_BAUDR 0x80010005
-#pragma Aux_register(0x80010005, name=>"io_spi_mst0_baudr")
-
-// User extension aux register io_spi_mst0_txftlr
-#define AR_IO_SPI_MST0_TXFTLR 0x80010006
-#pragma Aux_register(0x80010006, name=>"io_spi_mst0_txftlr")
-
-// User extension aux register io_spi_mst0_rxftlr
-#define AR_IO_SPI_MST0_RXFTLR 0x80010007
-#pragma Aux_register(0x80010007, name=>"io_spi_mst0_rxftlr")
-
-// User extension aux register io_spi_mst0_txflr
-#define AR_IO_SPI_MST0_TXFLR 0x80010008
-#pragma Aux_register(0x80010008, name=>"io_spi_mst0_txflr")
-
-// User extension aux register io_spi_mst0_rxflr
-#define AR_IO_SPI_MST0_RXFLR 0x80010009
-#pragma Aux_register(0x80010009, name=>"io_spi_mst0_rxflr")
-
-// User extension aux register io_spi_mst0_sr
-#define AR_IO_SPI_MST0_SR 0x8001000a
-#pragma Aux_register(0x8001000a, name=>"io_spi_mst0_sr")
-
-// User extension aux register io_spi_mst0_imr
-#define AR_IO_SPI_MST0_IMR 0x8001000b
-#pragma Aux_register(0x8001000b, name=>"io_spi_mst0_imr")
-
-// User extension aux register io_spi_mst0_isr
-#define AR_IO_SPI_MST0_ISR 0x8001000c
-#pragma Aux_register(0x8001000c, name=>"io_spi_mst0_isr")
-
-// User extension aux register io_spi_mst0_risr
-#define AR_IO_SPI_MST0_RISR 0x8001000d
-#pragma Aux_register(0x8001000d, name=>"io_spi_mst0_risr")
-
-// User extension aux register io_spi_mst0_txoicr
-#define AR_IO_SPI_MST0_TXOICR 0x8001000e
-#pragma Aux_register(0x8001000e, name=>"io_spi_mst0_txoicr")
-
-// User extension aux register io_spi_mst0_rxoicr
-#define AR_IO_SPI_MST0_RXOICR 0x8001000f
-#pragma Aux_register(0x8001000f, name=>"io_spi_mst0_rxoicr")
-
-// User extension aux register io_spi_mst0_rxuicr
-#define AR_IO_SPI_MST0_RXUICR 0x80010010
-#pragma Aux_register(0x80010010, name=>"io_spi_mst0_rxuicr")
-
-// User extension aux register io_spi_mst0_icr
-#define AR_IO_SPI_MST0_ICR 0x80010012
-#pragma Aux_register(0x80010012, name=>"io_spi_mst0_icr")
-
-// User extension aux register io_spi_mst0_clken
-#define AR_IO_SPI_MST0_CLKEN 0x80010016
-#pragma Aux_register(0x80010016, name=>"io_spi_mst0_clken")
-
-// User extension aux register io_spi_mst0_dr
-#define AR_IO_SPI_MST0_DR 0x80010018
-#pragma Aux_register(0x80010018, name=>"io_spi_mst0_dr")
-
-// User extension aux register io_spi_mst0_rx_sample_dly
-#define AR_IO_SPI_MST0_RX_SAMPLE_DLY 0x8001003c
-#pragma Aux_register(0x8001003c, name=>"io_spi_mst0_rx_sample_dly")
-#define APEX_COM_ARC_HARDWARE_DFSS_SUBSYS_BCR_PRESENT	1
-
-// User extension aux register SUBSYS_BUILD
-#define AR_SUBSYS_BUILD 0xf0
-#pragma Aux_register(0xf0, name=>"SUBSYS_BUILD")
-
-// User extension aux register SUBSYS_DSP_0_BUILD
-#define AR_SUBSYS_DSP_0_BUILD 0xa00
-#pragma Aux_register(0xa00, name=>"SUBSYS_DSP_0_BUILD")
-
-// User extension aux register SUBSYS_DSP_0_CONFIG
-#define AR_SUBSYS_DSP_0_CONFIG 0xa02
-#pragma Aux_register(0xa02, name=>"SUBSYS_DSP_0_CONFIG")
-
-// User extension aux register SUBSYS_IO_0_BUILD
-#define AR_SUBSYS_IO_0_BUILD 0xa04
-#pragma Aux_register(0xa04, name=>"SUBSYS_IO_0_BUILD")
-
-// User extension aux register SUBSYS_IO_1_BUILD
-#define AR_SUBSYS_IO_1_BUILD 0xa05
-#pragma Aux_register(0xa05, name=>"SUBSYS_IO_1_BUILD")
-
-// User extension aux register SUBSYS_IO_2_BUILD
-#define AR_SUBSYS_IO_2_BUILD 0xa06
-#pragma Aux_register(0xa06, name=>"SUBSYS_IO_2_BUILD")
-
-// User extension aux register SUBSYS_UAUX_OFFSET
-#define AR_SUBSYS_UAUX_OFFSET 0xa1e
-#pragma Aux_register(0xa1e, name=>"SUBSYS_UAUX_OFFSET")
-
-// User extension aux register SUBSYS_APEX_OFFSET
-#define AR_SUBSYS_APEX_OFFSET 0xa1f
-#pragma Aux_register(0xa1f, name=>"SUBSYS_APEX_OFFSET")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_SPI_MST1_PRESENT	1
-
-// User extension aux register io_spi_mst1_ctrlr0
-#define AR_IO_SPI_MST1_CTRLR0 0x80010100
-#pragma Aux_register(0x80010100, name=>"io_spi_mst1_ctrlr0")
-
-// User extension aux register io_spi_mst1_ctrlr1
-#define AR_IO_SPI_MST1_CTRLR1 0x80010101
-#pragma Aux_register(0x80010101, name=>"io_spi_mst1_ctrlr1")
-
-// User extension aux register io_spi_mst1_spien
-#define AR_IO_SPI_MST1_SPIEN 0x80010102
-#pragma Aux_register(0x80010102, name=>"io_spi_mst1_spien")
-
-// User extension aux register io_spi_mst1_ser
-#define AR_IO_SPI_MST1_SER 0x80010104
-#pragma Aux_register(0x80010104, name=>"io_spi_mst1_ser")
-
-// User extension aux register io_spi_mst1_baudr
-#define AR_IO_SPI_MST1_BAUDR 0x80010105
-#pragma Aux_register(0x80010105, name=>"io_spi_mst1_baudr")
-
-// User extension aux register io_spi_mst1_txftlr
-#define AR_IO_SPI_MST1_TXFTLR 0x80010106
-#pragma Aux_register(0x80010106, name=>"io_spi_mst1_txftlr")
-
-// User extension aux register io_spi_mst1_rxftlr
-#define AR_IO_SPI_MST1_RXFTLR 0x80010107
-#pragma Aux_register(0x80010107, name=>"io_spi_mst1_rxftlr")
-
-// User extension aux register io_spi_mst1_txflr
-#define AR_IO_SPI_MST1_TXFLR 0x80010108
-#pragma Aux_register(0x80010108, name=>"io_spi_mst1_txflr")
-
-// User extension aux register io_spi_mst1_rxflr
-#define AR_IO_SPI_MST1_RXFLR 0x80010109
-#pragma Aux_register(0x80010109, name=>"io_spi_mst1_rxflr")
-
-// User extension aux register io_spi_mst1_sr
-#define AR_IO_SPI_MST1_SR 0x8001010a
-#pragma Aux_register(0x8001010a, name=>"io_spi_mst1_sr")
-
-// User extension aux register io_spi_mst1_imr
-#define AR_IO_SPI_MST1_IMR 0x8001010b
-#pragma Aux_register(0x8001010b, name=>"io_spi_mst1_imr")
-
-// User extension aux register io_spi_mst1_isr
-#define AR_IO_SPI_MST1_ISR 0x8001010c
-#pragma Aux_register(0x8001010c, name=>"io_spi_mst1_isr")
-
-// User extension aux register io_spi_mst1_risr
-#define AR_IO_SPI_MST1_RISR 0x8001010d
-#pragma Aux_register(0x8001010d, name=>"io_spi_mst1_risr")
-
-// User extension aux register io_spi_mst1_txoicr
-#define AR_IO_SPI_MST1_TXOICR 0x8001010e
-#pragma Aux_register(0x8001010e, name=>"io_spi_mst1_txoicr")
-
-// User extension aux register io_spi_mst1_rxoicr
-#define AR_IO_SPI_MST1_RXOICR 0x8001010f
-#pragma Aux_register(0x8001010f, name=>"io_spi_mst1_rxoicr")
-
-// User extension aux register io_spi_mst1_rxuicr
-#define AR_IO_SPI_MST1_RXUICR 0x80010110
-#pragma Aux_register(0x80010110, name=>"io_spi_mst1_rxuicr")
-
-// User extension aux register io_spi_mst1_icr
-#define AR_IO_SPI_MST1_ICR 0x80010112
-#pragma Aux_register(0x80010112, name=>"io_spi_mst1_icr")
-
-// User extension aux register io_spi_mst1_clken
-#define AR_IO_SPI_MST1_CLKEN 0x80010116
-#pragma Aux_register(0x80010116, name=>"io_spi_mst1_clken")
-
-// User extension aux register io_spi_mst1_dr
-#define AR_IO_SPI_MST1_DR 0x80010118
-#pragma Aux_register(0x80010118, name=>"io_spi_mst1_dr")
-
-// User extension aux register io_spi_mst1_rx_sample_dly
-#define AR_IO_SPI_MST1_RX_SAMPLE_DLY 0x8001013c
-#pragma Aux_register(0x8001013c, name=>"io_spi_mst1_rx_sample_dly")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_SPI_MST2_PRESENT	1
-
-// User extension aux register io_spi_mst2_ctrlr0
-#define AR_IO_SPI_MST2_CTRLR0 0x80010200
-#pragma Aux_register(0x80010200, name=>"io_spi_mst2_ctrlr0")
-
-// User extension aux register io_spi_mst2_ctrlr1
-#define AR_IO_SPI_MST2_CTRLR1 0x80010201
-#pragma Aux_register(0x80010201, name=>"io_spi_mst2_ctrlr1")
-
-// User extension aux register io_spi_mst2_spien
-#define AR_IO_SPI_MST2_SPIEN 0x80010202
-#pragma Aux_register(0x80010202, name=>"io_spi_mst2_spien")
-
-// User extension aux register io_spi_mst2_ser
-#define AR_IO_SPI_MST2_SER 0x80010204
-#pragma Aux_register(0x80010204, name=>"io_spi_mst2_ser")
-
-// User extension aux register io_spi_mst2_baudr
-#define AR_IO_SPI_MST2_BAUDR 0x80010205
-#pragma Aux_register(0x80010205, name=>"io_spi_mst2_baudr")
-
-// User extension aux register io_spi_mst2_txftlr
-#define AR_IO_SPI_MST2_TXFTLR 0x80010206
-#pragma Aux_register(0x80010206, name=>"io_spi_mst2_txftlr")
-
-// User extension aux register io_spi_mst2_rxftlr
-#define AR_IO_SPI_MST2_RXFTLR 0x80010207
-#pragma Aux_register(0x80010207, name=>"io_spi_mst2_rxftlr")
-
-// User extension aux register io_spi_mst2_txflr
-#define AR_IO_SPI_MST2_TXFLR 0x80010208
-#pragma Aux_register(0x80010208, name=>"io_spi_mst2_txflr")
-
-// User extension aux register io_spi_mst2_rxflr
-#define AR_IO_SPI_MST2_RXFLR 0x80010209
-#pragma Aux_register(0x80010209, name=>"io_spi_mst2_rxflr")
-
-// User extension aux register io_spi_mst2_sr
-#define AR_IO_SPI_MST2_SR 0x8001020a
-#pragma Aux_register(0x8001020a, name=>"io_spi_mst2_sr")
-
-// User extension aux register io_spi_mst2_imr
-#define AR_IO_SPI_MST2_IMR 0x8001020b
-#pragma Aux_register(0x8001020b, name=>"io_spi_mst2_imr")
-
-// User extension aux register io_spi_mst2_isr
-#define AR_IO_SPI_MST2_ISR 0x8001020c
-#pragma Aux_register(0x8001020c, name=>"io_spi_mst2_isr")
-
-// User extension aux register io_spi_mst2_risr
-#define AR_IO_SPI_MST2_RISR 0x8001020d
-#pragma Aux_register(0x8001020d, name=>"io_spi_mst2_risr")
-
-// User extension aux register io_spi_mst2_txoicr
-#define AR_IO_SPI_MST2_TXOICR 0x8001020e
-#pragma Aux_register(0x8001020e, name=>"io_spi_mst2_txoicr")
-
-// User extension aux register io_spi_mst2_rxoicr
-#define AR_IO_SPI_MST2_RXOICR 0x8001020f
-#pragma Aux_register(0x8001020f, name=>"io_spi_mst2_rxoicr")
-
-// User extension aux register io_spi_mst2_rxuicr
-#define AR_IO_SPI_MST2_RXUICR 0x80010210
-#pragma Aux_register(0x80010210, name=>"io_spi_mst2_rxuicr")
-
-// User extension aux register io_spi_mst2_icr
-#define AR_IO_SPI_MST2_ICR 0x80010212
-#pragma Aux_register(0x80010212, name=>"io_spi_mst2_icr")
-
-// User extension aux register io_spi_mst2_clken
-#define AR_IO_SPI_MST2_CLKEN 0x80010216
-#pragma Aux_register(0x80010216, name=>"io_spi_mst2_clken")
-
-// User extension aux register io_spi_mst2_dr
-#define AR_IO_SPI_MST2_DR 0x80010218
-#pragma Aux_register(0x80010218, name=>"io_spi_mst2_dr")
-
-// User extension aux register io_spi_mst2_rx_sample_dly
-#define AR_IO_SPI_MST2_RX_SAMPLE_DLY 0x8001023c
-#pragma Aux_register(0x8001023c, name=>"io_spi_mst2_rx_sample_dly")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_SPI_SLV0_PRESENT	1
-
-// User extension aux register io_spi_slv0_ctrlr0
-#define AR_IO_SPI_SLV0_CTRLR0 0x80011000
-#pragma Aux_register(0x80011000, name=>"io_spi_slv0_ctrlr0")
-
-// User extension aux register io_spi_slv0_spien
-#define AR_IO_SPI_SLV0_SPIEN 0x80011002
-#pragma Aux_register(0x80011002, name=>"io_spi_slv0_spien")
-
-// User extension aux register io_spi_slv0_txftlr
-#define AR_IO_SPI_SLV0_TXFTLR 0x80011006
-#pragma Aux_register(0x80011006, name=>"io_spi_slv0_txftlr")
-
-// User extension aux register io_spi_slv0_rxftlr
-#define AR_IO_SPI_SLV0_RXFTLR 0x80011007
-#pragma Aux_register(0x80011007, name=>"io_spi_slv0_rxftlr")
-
-// User extension aux register io_spi_slv0_txflr
-#define AR_IO_SPI_SLV0_TXFLR 0x80011008
-#pragma Aux_register(0x80011008, name=>"io_spi_slv0_txflr")
-
-// User extension aux register io_spi_slv0_rxflr
-#define AR_IO_SPI_SLV0_RXFLR 0x80011009
-#pragma Aux_register(0x80011009, name=>"io_spi_slv0_rxflr")
-
-// User extension aux register io_spi_slv0_sr
-#define AR_IO_SPI_SLV0_SR 0x8001100a
-#pragma Aux_register(0x8001100a, name=>"io_spi_slv0_sr")
-
-// User extension aux register io_spi_slv0_imr
-#define AR_IO_SPI_SLV0_IMR 0x8001100b
-#pragma Aux_register(0x8001100b, name=>"io_spi_slv0_imr")
-
-// User extension aux register io_spi_slv0_isr
-#define AR_IO_SPI_SLV0_ISR 0x8001100c
-#pragma Aux_register(0x8001100c, name=>"io_spi_slv0_isr")
-
-// User extension aux register io_spi_slv0_risr
-#define AR_IO_SPI_SLV0_RISR 0x8001100d
-#pragma Aux_register(0x8001100d, name=>"io_spi_slv0_risr")
-
-// User extension aux register io_spi_slv0_txoicr
-#define AR_IO_SPI_SLV0_TXOICR 0x8001100e
-#pragma Aux_register(0x8001100e, name=>"io_spi_slv0_txoicr")
-
-// User extension aux register io_spi_slv0_rxoicr
-#define AR_IO_SPI_SLV0_RXOICR 0x8001100f
-#pragma Aux_register(0x8001100f, name=>"io_spi_slv0_rxoicr")
-
-// User extension aux register io_spi_slv0_rxuicr
-#define AR_IO_SPI_SLV0_RXUICR 0x80011010
-#pragma Aux_register(0x80011010, name=>"io_spi_slv0_rxuicr")
-
-// User extension aux register io_spi_slv0_icr
-#define AR_IO_SPI_SLV0_ICR 0x80011012
-#pragma Aux_register(0x80011012, name=>"io_spi_slv0_icr")
-
-// User extension aux register io_spi_slv0_clken
-#define AR_IO_SPI_SLV0_CLKEN 0x80011016
-#pragma Aux_register(0x80011016, name=>"io_spi_slv0_clken")
-
-// User extension aux register io_spi_slv0_dr
-#define AR_IO_SPI_SLV0_DR 0x80011018
-#pragma Aux_register(0x80011018, name=>"io_spi_slv0_dr")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_GPIO1_PRESENT	1
-
-// User extension aux register io_gpio1_debounce
-#define AR_IO_GPIO1_DEBOUNCE 0x80017148
-#pragma Aux_register(0x80017148, name=>"io_gpio1_debounce")
-
-// User extension aux register io_gpio1_clken
-#define AR_IO_GPIO1_CLKEN 0x80017180
-#pragma Aux_register(0x80017180, name=>"io_gpio1_clken")
-
-// User extension aux register io_gpio1_swporta_dr
-#define AR_IO_GPIO1_SWPORTA_DR 0x80017100
-#pragma Aux_register(0x80017100, name=>"io_gpio1_swporta_dr")
-
-// User extension aux register io_gpio1_swporta_ddr
-#define AR_IO_GPIO1_SWPORTA_DDR 0x80017104
-#pragma Aux_register(0x80017104, name=>"io_gpio1_swporta_ddr")
-
-// User extension aux register io_gpio1_inten
-#define AR_IO_GPIO1_INTEN 0x80017130
-#pragma Aux_register(0x80017130, name=>"io_gpio1_inten")
-
-// User extension aux register io_gpio1_intmask
-#define AR_IO_GPIO1_INTMASK 0x80017134
-#pragma Aux_register(0x80017134, name=>"io_gpio1_intmask")
-
-// User extension aux register io_gpio1_inttype_level
-#define AR_IO_GPIO1_INTTYPE_LEVEL 0x80017138
-#pragma Aux_register(0x80017138, name=>"io_gpio1_inttype_level")
-
-// User extension aux register io_gpio1_int_polarity
-#define AR_IO_GPIO1_INT_POLARITY 0x8001713c
-#pragma Aux_register(0x8001713c, name=>"io_gpio1_int_polarity")
-
-// User extension aux register io_gpio1_intstatus
-#define AR_IO_GPIO1_INTSTATUS 0x80017140
-#pragma Aux_register(0x80017140, name=>"io_gpio1_intstatus")
-
-// User extension aux register io_gpio1_raw_intstatus
-#define AR_IO_GPIO1_RAW_INTSTATUS 0x80017144
-#pragma Aux_register(0x80017144, name=>"io_gpio1_raw_intstatus")
-
-// User extension aux register io_gpio1_porta_eoi
-#define AR_IO_GPIO1_PORTA_EOI 0x8001714c
-#pragma Aux_register(0x8001714c, name=>"io_gpio1_porta_eoi")
-
-// User extension aux register io_gpio1_ext_porta
-#define AR_IO_GPIO1_EXT_PORTA 0x80017150
-#pragma Aux_register(0x80017150, name=>"io_gpio1_ext_porta")
-
-// User extension aux register io_gpio1_ls_sync
-#define AR_IO_GPIO1_LS_SYNC 0x80017160
-#pragma Aux_register(0x80017160, name=>"io_gpio1_ls_sync")
-
-// User extension aux register io_gpio1_int_bothedge
-#define AR_IO_GPIO1_INT_BOTHEDGE 0x80017168
-#pragma Aux_register(0x80017168, name=>"io_gpio1_int_bothedge")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_GPIO2_PRESENT	1
-
-// User extension aux register io_gpio2_debounce
-#define AR_IO_GPIO2_DEBOUNCE 0x80017248
-#pragma Aux_register(0x80017248, name=>"io_gpio2_debounce")
-
-// User extension aux register io_gpio2_clken
-#define AR_IO_GPIO2_CLKEN 0x80017280
-#pragma Aux_register(0x80017280, name=>"io_gpio2_clken")
-
-// User extension aux register io_gpio2_swporta_dr
-#define AR_IO_GPIO2_SWPORTA_DR 0x80017200
-#pragma Aux_register(0x80017200, name=>"io_gpio2_swporta_dr")
-
-// User extension aux register io_gpio2_swporta_ddr
-#define AR_IO_GPIO2_SWPORTA_DDR 0x80017204
-#pragma Aux_register(0x80017204, name=>"io_gpio2_swporta_ddr")
-
-// User extension aux register io_gpio2_inten
-#define AR_IO_GPIO2_INTEN 0x80017230
-#pragma Aux_register(0x80017230, name=>"io_gpio2_inten")
-
-// User extension aux register io_gpio2_intmask
-#define AR_IO_GPIO2_INTMASK 0x80017234
-#pragma Aux_register(0x80017234, name=>"io_gpio2_intmask")
-
-// User extension aux register io_gpio2_inttype_level
-#define AR_IO_GPIO2_INTTYPE_LEVEL 0x80017238
-#pragma Aux_register(0x80017238, name=>"io_gpio2_inttype_level")
-
-// User extension aux register io_gpio2_int_polarity
-#define AR_IO_GPIO2_INT_POLARITY 0x8001723c
-#pragma Aux_register(0x8001723c, name=>"io_gpio2_int_polarity")
-
-// User extension aux register io_gpio2_intstatus
-#define AR_IO_GPIO2_INTSTATUS 0x80017240
-#pragma Aux_register(0x80017240, name=>"io_gpio2_intstatus")
-
-// User extension aux register io_gpio2_raw_intstatus
-#define AR_IO_GPIO2_RAW_INTSTATUS 0x80017244
-#pragma Aux_register(0x80017244, name=>"io_gpio2_raw_intstatus")
-
-// User extension aux register io_gpio2_porta_eoi
-#define AR_IO_GPIO2_PORTA_EOI 0x8001724c
-#pragma Aux_register(0x8001724c, name=>"io_gpio2_porta_eoi")
-
-// User extension aux register io_gpio2_ext_porta
-#define AR_IO_GPIO2_EXT_PORTA 0x80017250
-#pragma Aux_register(0x80017250, name=>"io_gpio2_ext_porta")
-
-// User extension aux register io_gpio2_ls_sync
-#define AR_IO_GPIO2_LS_SYNC 0x80017260
-#pragma Aux_register(0x80017260, name=>"io_gpio2_ls_sync")
-
-// User extension aux register io_gpio2_int_bothedge
-#define AR_IO_GPIO2_INT_BOTHEDGE 0x80017268
-#pragma Aux_register(0x80017268, name=>"io_gpio2_int_bothedge")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2C_MST1_PRESENT	1
-
-// User extension aux register io_i2c_mst1_clken
-#define AR_IO_I2C_MST1_CLKEN 0x800121c0
-#pragma Aux_register(0x800121c0, name=>"io_i2c_mst1_clken")
-
-// User extension aux register io_i2c_mst1_con
-#define AR_IO_I2C_MST1_CON 0x80012100
-#pragma Aux_register(0x80012100, name=>"io_i2c_mst1_con")
-
-// User extension aux register io_i2c_mst1_tar
-#define AR_IO_I2C_MST1_TAR 0x80012104
-#pragma Aux_register(0x80012104, name=>"io_i2c_mst1_tar")
-
-// User extension aux register io_i2c_mst1_data_cmd
-#define AR_IO_I2C_MST1_DATA_CMD 0x80012110
-#pragma Aux_register(0x80012110, name=>"io_i2c_mst1_data_cmd")
-
-// User extension aux register io_i2c_mst1_ss_scl_hcnt
-#define AR_IO_I2C_MST1_SS_SCL_HCNT 0x80012114
-#pragma Aux_register(0x80012114, name=>"io_i2c_mst1_ss_scl_hcnt")
-
-// User extension aux register io_i2c_mst1_ss_scl_lcnt
-#define AR_IO_I2C_MST1_SS_SCL_LCNT 0x80012118
-#pragma Aux_register(0x80012118, name=>"io_i2c_mst1_ss_scl_lcnt")
-
-// User extension aux register io_i2c_mst1_fs_scl_hcnt
-#define AR_IO_I2C_MST1_FS_SCL_HCNT 0x8001211c
-#pragma Aux_register(0x8001211c, name=>"io_i2c_mst1_fs_scl_hcnt")
-
-// User extension aux register io_i2c_mst1_fs_scl_lcnt
-#define AR_IO_I2C_MST1_FS_SCL_LCNT 0x80012120
-#pragma Aux_register(0x80012120, name=>"io_i2c_mst1_fs_scl_lcnt")
-
-// User extension aux register io_i2c_mst1_intr_stat
-#define AR_IO_I2C_MST1_INTR_STAT 0x8001212c
-#pragma Aux_register(0x8001212c, name=>"io_i2c_mst1_intr_stat")
-
-// User extension aux register io_i2c_mst1_intr_mask
-#define AR_IO_I2C_MST1_INTR_MASK 0x80012130
-#pragma Aux_register(0x80012130, name=>"io_i2c_mst1_intr_mask")
-
-// User extension aux register io_i2c_mst1_raw_intr_stat
-#define AR_IO_I2C_MST1_RAW_INTR_STAT 0x80012134
-#pragma Aux_register(0x80012134, name=>"io_i2c_mst1_raw_intr_stat")
-
-// User extension aux register io_i2c_mst1_rx_tl
-#define AR_IO_I2C_MST1_RX_TL 0x80012138
-#pragma Aux_register(0x80012138, name=>"io_i2c_mst1_rx_tl")
-
-// User extension aux register io_i2c_mst1_tx_tl
-#define AR_IO_I2C_MST1_TX_TL 0x8001213c
-#pragma Aux_register(0x8001213c, name=>"io_i2c_mst1_tx_tl")
-
-// User extension aux register io_i2c_mst1_clr_intr
-#define AR_IO_I2C_MST1_CLR_INTR 0x80012140
-#pragma Aux_register(0x80012140, name=>"io_i2c_mst1_clr_intr")
-
-// User extension aux register io_i2c_mst1_clr_rx_under
-#define AR_IO_I2C_MST1_CLR_RX_UNDER 0x80012144
-#pragma Aux_register(0x80012144, name=>"io_i2c_mst1_clr_rx_under")
-
-// User extension aux register io_i2c_mst1_clr_rx_over
-#define AR_IO_I2C_MST1_CLR_RX_OVER 0x80012148
-#pragma Aux_register(0x80012148, name=>"io_i2c_mst1_clr_rx_over")
-
-// User extension aux register io_i2c_mst1_clr_tx_over
-#define AR_IO_I2C_MST1_CLR_TX_OVER 0x8001214c
-#pragma Aux_register(0x8001214c, name=>"io_i2c_mst1_clr_tx_over")
-
-// User extension aux register io_i2c_mst1_clr_tx_abrt
-#define AR_IO_I2C_MST1_CLR_TX_ABRT 0x80012154
-#pragma Aux_register(0x80012154, name=>"io_i2c_mst1_clr_tx_abrt")
-
-// User extension aux register io_i2c_mst1_clr_activity
-#define AR_IO_I2C_MST1_CLR_ACTIVITY 0x8001215c
-#pragma Aux_register(0x8001215c, name=>"io_i2c_mst1_clr_activity")
-
-// User extension aux register io_i2c_mst1_clr_stop_det
-#define AR_IO_I2C_MST1_CLR_STOP_DET 0x80012160
-#pragma Aux_register(0x80012160, name=>"io_i2c_mst1_clr_stop_det")
-
-// User extension aux register io_i2c_mst1_clr_start_det
-#define AR_IO_I2C_MST1_CLR_START_DET 0x80012164
-#pragma Aux_register(0x80012164, name=>"io_i2c_mst1_clr_start_det")
-
-// User extension aux register io_i2c_mst1_enable
-#define AR_IO_I2C_MST1_ENABLE 0x8001216c
-#pragma Aux_register(0x8001216c, name=>"io_i2c_mst1_enable")
-
-// User extension aux register io_i2c_mst1_status
-#define AR_IO_I2C_MST1_STATUS 0x80012170
-#pragma Aux_register(0x80012170, name=>"io_i2c_mst1_status")
-
-// User extension aux register io_i2c_mst1_txflr
-#define AR_IO_I2C_MST1_TXFLR 0x80012174
-#pragma Aux_register(0x80012174, name=>"io_i2c_mst1_txflr")
-
-// User extension aux register io_i2c_mst1_rxflr
-#define AR_IO_I2C_MST1_RXFLR 0x80012178
-#pragma Aux_register(0x80012178, name=>"io_i2c_mst1_rxflr")
-
-// User extension aux register io_i2c_mst1_sda_hold
-#define AR_IO_I2C_MST1_SDA_HOLD 0x8001217c
-#pragma Aux_register(0x8001217c, name=>"io_i2c_mst1_sda_hold")
-
-// User extension aux register io_i2c_mst1_tx_abrt_source
-#define AR_IO_I2C_MST1_TX_ABRT_SOURCE 0x80012180
-#pragma Aux_register(0x80012180, name=>"io_i2c_mst1_tx_abrt_source")
-
-// User extension aux register io_i2c_mst1_enable_status
-#define AR_IO_I2C_MST1_ENABLE_STATUS 0x8001219c
-#pragma Aux_register(0x8001219c, name=>"io_i2c_mst1_enable_status")
-
-// User extension aux register io_i2c_mst1_fs_spklen
-#define AR_IO_I2C_MST1_FS_SPKLEN 0x800121a0
-#pragma Aux_register(0x800121a0, name=>"io_i2c_mst1_fs_spklen")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2C_MST2_PRESENT	1
-
-// User extension aux register io_i2c_mst2_clken
-#define AR_IO_I2C_MST2_CLKEN 0x800122c0
-#pragma Aux_register(0x800122c0, name=>"io_i2c_mst2_clken")
-
-// User extension aux register io_i2c_mst2_con
-#define AR_IO_I2C_MST2_CON 0x80012200
-#pragma Aux_register(0x80012200, name=>"io_i2c_mst2_con")
-
-// User extension aux register io_i2c_mst2_tar
-#define AR_IO_I2C_MST2_TAR 0x80012204
-#pragma Aux_register(0x80012204, name=>"io_i2c_mst2_tar")
-
-// User extension aux register io_i2c_mst2_data_cmd
-#define AR_IO_I2C_MST2_DATA_CMD 0x80012210
-#pragma Aux_register(0x80012210, name=>"io_i2c_mst2_data_cmd")
-
-// User extension aux register io_i2c_mst2_ss_scl_hcnt
-#define AR_IO_I2C_MST2_SS_SCL_HCNT 0x80012214
-#pragma Aux_register(0x80012214, name=>"io_i2c_mst2_ss_scl_hcnt")
-
-// User extension aux register io_i2c_mst2_ss_scl_lcnt
-#define AR_IO_I2C_MST2_SS_SCL_LCNT 0x80012218
-#pragma Aux_register(0x80012218, name=>"io_i2c_mst2_ss_scl_lcnt")
-
-// User extension aux register io_i2c_mst2_fs_scl_hcnt
-#define AR_IO_I2C_MST2_FS_SCL_HCNT 0x8001221c
-#pragma Aux_register(0x8001221c, name=>"io_i2c_mst2_fs_scl_hcnt")
-
-// User extension aux register io_i2c_mst2_fs_scl_lcnt
-#define AR_IO_I2C_MST2_FS_SCL_LCNT 0x80012220
-#pragma Aux_register(0x80012220, name=>"io_i2c_mst2_fs_scl_lcnt")
-
-// User extension aux register io_i2c_mst2_intr_stat
-#define AR_IO_I2C_MST2_INTR_STAT 0x8001222c
-#pragma Aux_register(0x8001222c, name=>"io_i2c_mst2_intr_stat")
-
-// User extension aux register io_i2c_mst2_intr_mask
-#define AR_IO_I2C_MST2_INTR_MASK 0x80012230
-#pragma Aux_register(0x80012230, name=>"io_i2c_mst2_intr_mask")
-
-// User extension aux register io_i2c_mst2_raw_intr_stat
-#define AR_IO_I2C_MST2_RAW_INTR_STAT 0x80012234
-#pragma Aux_register(0x80012234, name=>"io_i2c_mst2_raw_intr_stat")
-
-// User extension aux register io_i2c_mst2_rx_tl
-#define AR_IO_I2C_MST2_RX_TL 0x80012238
-#pragma Aux_register(0x80012238, name=>"io_i2c_mst2_rx_tl")
-
-// User extension aux register io_i2c_mst2_tx_tl
-#define AR_IO_I2C_MST2_TX_TL 0x8001223c
-#pragma Aux_register(0x8001223c, name=>"io_i2c_mst2_tx_tl")
-
-// User extension aux register io_i2c_mst2_clr_intr
-#define AR_IO_I2C_MST2_CLR_INTR 0x80012240
-#pragma Aux_register(0x80012240, name=>"io_i2c_mst2_clr_intr")
-
-// User extension aux register io_i2c_mst2_clr_rx_under
-#define AR_IO_I2C_MST2_CLR_RX_UNDER 0x80012244
-#pragma Aux_register(0x80012244, name=>"io_i2c_mst2_clr_rx_under")
-
-// User extension aux register io_i2c_mst2_clr_rx_over
-#define AR_IO_I2C_MST2_CLR_RX_OVER 0x80012248
-#pragma Aux_register(0x80012248, name=>"io_i2c_mst2_clr_rx_over")
-
-// User extension aux register io_i2c_mst2_clr_tx_over
-#define AR_IO_I2C_MST2_CLR_TX_OVER 0x8001224c
-#pragma Aux_register(0x8001224c, name=>"io_i2c_mst2_clr_tx_over")
-
-// User extension aux register io_i2c_mst2_clr_tx_abrt
-#define AR_IO_I2C_MST2_CLR_TX_ABRT 0x80012254
-#pragma Aux_register(0x80012254, name=>"io_i2c_mst2_clr_tx_abrt")
-
-// User extension aux register io_i2c_mst2_clr_activity
-#define AR_IO_I2C_MST2_CLR_ACTIVITY 0x8001225c
-#pragma Aux_register(0x8001225c, name=>"io_i2c_mst2_clr_activity")
-
-// User extension aux register io_i2c_mst2_clr_stop_det
-#define AR_IO_I2C_MST2_CLR_STOP_DET 0x80012260
-#pragma Aux_register(0x80012260, name=>"io_i2c_mst2_clr_stop_det")
-
-// User extension aux register io_i2c_mst2_clr_start_det
-#define AR_IO_I2C_MST2_CLR_START_DET 0x80012264
-#pragma Aux_register(0x80012264, name=>"io_i2c_mst2_clr_start_det")
-
-// User extension aux register io_i2c_mst2_enable
-#define AR_IO_I2C_MST2_ENABLE 0x8001226c
-#pragma Aux_register(0x8001226c, name=>"io_i2c_mst2_enable")
-
-// User extension aux register io_i2c_mst2_status
-#define AR_IO_I2C_MST2_STATUS 0x80012270
-#pragma Aux_register(0x80012270, name=>"io_i2c_mst2_status")
-
-// User extension aux register io_i2c_mst2_txflr
-#define AR_IO_I2C_MST2_TXFLR 0x80012274
-#pragma Aux_register(0x80012274, name=>"io_i2c_mst2_txflr")
-
-// User extension aux register io_i2c_mst2_rxflr
-#define AR_IO_I2C_MST2_RXFLR 0x80012278
-#pragma Aux_register(0x80012278, name=>"io_i2c_mst2_rxflr")
-
-// User extension aux register io_i2c_mst2_sda_hold
-#define AR_IO_I2C_MST2_SDA_HOLD 0x8001227c
-#pragma Aux_register(0x8001227c, name=>"io_i2c_mst2_sda_hold")
-
-// User extension aux register io_i2c_mst2_tx_abrt_source
-#define AR_IO_I2C_MST2_TX_ABRT_SOURCE 0x80012280
-#pragma Aux_register(0x80012280, name=>"io_i2c_mst2_tx_abrt_source")
-
-// User extension aux register io_i2c_mst2_enable_status
-#define AR_IO_I2C_MST2_ENABLE_STATUS 0x8001229c
-#pragma Aux_register(0x8001229c, name=>"io_i2c_mst2_enable_status")
-
-// User extension aux register io_i2c_mst2_fs_spklen
-#define AR_IO_I2C_MST2_FS_SPKLEN 0x800122a0
-#pragma Aux_register(0x800122a0, name=>"io_i2c_mst2_fs_spklen")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_UART0_PRESENT	1
-
-// User extension aux register io_uart0_clken
-#define AR_IO_UART0_CLKEN 0x800140c0
-#pragma Aux_register(0x800140c0, name=>"io_uart0_clken")
-
-// User extension aux register io_uart0_rbr_thr_dll
-#define AR_IO_UART0_RBR_THR_DLL 0x80014000
-#pragma Aux_register(0x80014000, name=>"io_uart0_rbr_thr_dll")
-
-// User extension aux register io_uart0_ier_dlh
-#define AR_IO_UART0_IER_DLH 0x80014004
-#pragma Aux_register(0x80014004, name=>"io_uart0_ier_dlh")
-
-// User extension aux register io_uart0_iir_fcr
-#define AR_IO_UART0_IIR_FCR 0x80014008
-#pragma Aux_register(0x80014008, name=>"io_uart0_iir_fcr")
-
-// User extension aux register io_uart0_lcr
-#define AR_IO_UART0_LCR 0x8001400c
-#pragma Aux_register(0x8001400c, name=>"io_uart0_lcr")
-
-// User extension aux register io_uart0_mcr
-#define AR_IO_UART0_MCR 0x80014010
-#pragma Aux_register(0x80014010, name=>"io_uart0_mcr")
-
-// User extension aux register io_uart0_lsr
-#define AR_IO_UART0_LSR 0x80014014
-#pragma Aux_register(0x80014014, name=>"io_uart0_lsr")
-
-// User extension aux register io_uart0_msr
-#define AR_IO_UART0_MSR 0x80014018
-#pragma Aux_register(0x80014018, name=>"io_uart0_msr")
-
-// User extension aux register io_uart0_usr
-#define AR_IO_UART0_USR 0x8001407c
-#pragma Aux_register(0x8001407c, name=>"io_uart0_usr")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_UART1_PRESENT	1
-
-// User extension aux register io_uart1_clken
-#define AR_IO_UART1_CLKEN 0x800141c0
-#pragma Aux_register(0x800141c0, name=>"io_uart1_clken")
-
-// User extension aux register io_uart1_rbr_thr_dll
-#define AR_IO_UART1_RBR_THR_DLL 0x80014100
-#pragma Aux_register(0x80014100, name=>"io_uart1_rbr_thr_dll")
-
-// User extension aux register io_uart1_ier_dlh
-#define AR_IO_UART1_IER_DLH 0x80014104
-#pragma Aux_register(0x80014104, name=>"io_uart1_ier_dlh")
-
-// User extension aux register io_uart1_iir_fcr
-#define AR_IO_UART1_IIR_FCR 0x80014108
-#pragma Aux_register(0x80014108, name=>"io_uart1_iir_fcr")
-
-// User extension aux register io_uart1_lcr
-#define AR_IO_UART1_LCR 0x8001410c
-#pragma Aux_register(0x8001410c, name=>"io_uart1_lcr")
-
-// User extension aux register io_uart1_mcr
-#define AR_IO_UART1_MCR 0x80014110
-#pragma Aux_register(0x80014110, name=>"io_uart1_mcr")
-
-// User extension aux register io_uart1_lsr
-#define AR_IO_UART1_LSR 0x80014114
-#pragma Aux_register(0x80014114, name=>"io_uart1_lsr")
-
-// User extension aux register io_uart1_msr
-#define AR_IO_UART1_MSR 0x80014118
-#pragma Aux_register(0x80014118, name=>"io_uart1_msr")
-
-// User extension aux register io_uart1_usr
-#define AR_IO_UART1_USR 0x8001417c
-#pragma Aux_register(0x8001417c, name=>"io_uart1_usr")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_UART2_PRESENT	1
-
-// User extension aux register io_uart2_clken
-#define AR_IO_UART2_CLKEN 0x800142c0
-#pragma Aux_register(0x800142c0, name=>"io_uart2_clken")
-
-// User extension aux register io_uart2_rbr_thr_dll
-#define AR_IO_UART2_RBR_THR_DLL 0x80014200
-#pragma Aux_register(0x80014200, name=>"io_uart2_rbr_thr_dll")
-
-// User extension aux register io_uart2_ier_dlh
-#define AR_IO_UART2_IER_DLH 0x80014204
-#pragma Aux_register(0x80014204, name=>"io_uart2_ier_dlh")
-
-// User extension aux register io_uart2_iir_fcr
-#define AR_IO_UART2_IIR_FCR 0x80014208
-#pragma Aux_register(0x80014208, name=>"io_uart2_iir_fcr")
-
-// User extension aux register io_uart2_lcr
-#define AR_IO_UART2_LCR 0x8001420c
-#pragma Aux_register(0x8001420c, name=>"io_uart2_lcr")
-
-// User extension aux register io_uart2_mcr
-#define AR_IO_UART2_MCR 0x80014210
-#pragma Aux_register(0x80014210, name=>"io_uart2_mcr")
-
-// User extension aux register io_uart2_lsr
-#define AR_IO_UART2_LSR 0x80014214
-#pragma Aux_register(0x80014214, name=>"io_uart2_lsr")
-
-// User extension aux register io_uart2_msr
-#define AR_IO_UART2_MSR 0x80014218
-#pragma Aux_register(0x80014218, name=>"io_uart2_msr")
-
-// User extension aux register io_uart2_usr
-#define AR_IO_UART2_USR 0x8001427c
-#pragma Aux_register(0x8001427c, name=>"io_uart2_usr")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_UART3_PRESENT	1
-
-// User extension aux register io_uart3_clken
-#define AR_IO_UART3_CLKEN 0x800143c0
-#pragma Aux_register(0x800143c0, name=>"io_uart3_clken")
-
-// User extension aux register io_uart3_rbr_thr_dll
-#define AR_IO_UART3_RBR_THR_DLL 0x80014300
-#pragma Aux_register(0x80014300, name=>"io_uart3_rbr_thr_dll")
-
-// User extension aux register io_uart3_ier_dlh
-#define AR_IO_UART3_IER_DLH 0x80014304
-#pragma Aux_register(0x80014304, name=>"io_uart3_ier_dlh")
-
-// User extension aux register io_uart3_iir_fcr
-#define AR_IO_UART3_IIR_FCR 0x80014308
-#pragma Aux_register(0x80014308, name=>"io_uart3_iir_fcr")
-
-// User extension aux register io_uart3_lcr
-#define AR_IO_UART3_LCR 0x8001430c
-#pragma Aux_register(0x8001430c, name=>"io_uart3_lcr")
-
-// User extension aux register io_uart3_mcr
-#define AR_IO_UART3_MCR 0x80014310
-#pragma Aux_register(0x80014310, name=>"io_uart3_mcr")
-
-// User extension aux register io_uart3_lsr
-#define AR_IO_UART3_LSR 0x80014314
-#pragma Aux_register(0x80014314, name=>"io_uart3_lsr")
-
-// User extension aux register io_uart3_msr
-#define AR_IO_UART3_MSR 0x80014318
-#pragma Aux_register(0x80014318, name=>"io_uart3_msr")
-
-// User extension aux register io_uart3_usr
-#define AR_IO_UART3_USR 0x8001437c
-#pragma Aux_register(0x8001437c, name=>"io_uart3_usr")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2S_RX_MST0_PRESENT	1
-
-// User extension aux register io_i2s_rx_mst0_ier
-#define AR_IO_I2S_RX_MST0_IER 0x8001a000
-#pragma Aux_register(0x8001a000, name=>"io_i2s_rx_mst0_ier")
-
-// User extension aux register io_i2s_rx_mst0_irer
-#define AR_IO_I2S_RX_MST0_IRER 0x8001a004
-#pragma Aux_register(0x8001a004, name=>"io_i2s_rx_mst0_irer")
-
-// User extension aux register io_i2s_rx_mst0_cer
-#define AR_IO_I2S_RX_MST0_CER 0x8001a00c
-#pragma Aux_register(0x8001a00c, name=>"io_i2s_rx_mst0_cer")
-
-// User extension aux register io_i2s_rx_mst0_ccr
-#define AR_IO_I2S_RX_MST0_CCR 0x8001a010
-#pragma Aux_register(0x8001a010, name=>"io_i2s_rx_mst0_ccr")
-
-// User extension aux register io_i2s_rx_mst0_rxffr
-#define AR_IO_I2S_RX_MST0_RXFFR 0x8001a014
-#pragma Aux_register(0x8001a014, name=>"io_i2s_rx_mst0_rxffr")
-
-// User extension aux register io_i2s_rx_mst0_lrbr
-#define AR_IO_I2S_RX_MST0_LRBR 0x8001a020
-#pragma Aux_register(0x8001a020, name=>"io_i2s_rx_mst0_lrbr")
-
-// User extension aux register io_i2s_rx_mst0_rrbr
-#define AR_IO_I2S_RX_MST0_RRBR 0x8001a024
-#pragma Aux_register(0x8001a024, name=>"io_i2s_rx_mst0_rrbr")
-
-// User extension aux register io_i2s_rx_mst0_rer
-#define AR_IO_I2S_RX_MST0_RER 0x8001a028
-#pragma Aux_register(0x8001a028, name=>"io_i2s_rx_mst0_rer")
-
-// User extension aux register io_i2s_rx_mst0_rcr
-#define AR_IO_I2S_RX_MST0_RCR 0x8001a030
-#pragma Aux_register(0x8001a030, name=>"io_i2s_rx_mst0_rcr")
-
-// User extension aux register io_i2s_rx_mst0_isr
-#define AR_IO_I2S_RX_MST0_ISR 0x8001a038
-#pragma Aux_register(0x8001a038, name=>"io_i2s_rx_mst0_isr")
-
-// User extension aux register io_i2s_rx_mst0_imr
-#define AR_IO_I2S_RX_MST0_IMR 0x8001a03c
-#pragma Aux_register(0x8001a03c, name=>"io_i2s_rx_mst0_imr")
-
-// User extension aux register io_i2s_rx_mst0_ror
-#define AR_IO_I2S_RX_MST0_ROR 0x8001a040
-#pragma Aux_register(0x8001a040, name=>"io_i2s_rx_mst0_ror")
-
-// User extension aux register io_i2s_rx_mst0_rfcr
-#define AR_IO_I2S_RX_MST0_RFCR 0x8001a048
-#pragma Aux_register(0x8001a048, name=>"io_i2s_rx_mst0_rfcr")
-
-// User extension aux register io_i2s_rx_mst0_rff
-#define AR_IO_I2S_RX_MST0_RFF 0x8001a050
-#pragma Aux_register(0x8001a050, name=>"io_i2s_rx_mst0_rff")
-
-// User extension aux register io_i2s_rx_mst0_rxdma
-#define AR_IO_I2S_RX_MST0_RXDMA 0x8001a1c0
-#pragma Aux_register(0x8001a1c0, name=>"io_i2s_rx_mst0_rxdma")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2S_TX_MST0_PRESENT	1
-
-// User extension aux register io_i2s_tx_mst0_ier
-#define AR_IO_I2S_TX_MST0_IER 0x80019000
-#pragma Aux_register(0x80019000, name=>"io_i2s_tx_mst0_ier")
-
-// User extension aux register io_i2s_tx_mst0_iter
-#define AR_IO_I2S_TX_MST0_ITER 0x80019008
-#pragma Aux_register(0x80019008, name=>"io_i2s_tx_mst0_iter")
-
-// User extension aux register io_i2s_tx_mst0_cer
-#define AR_IO_I2S_TX_MST0_CER 0x8001900c
-#pragma Aux_register(0x8001900c, name=>"io_i2s_tx_mst0_cer")
-
-// User extension aux register io_i2s_tx_mst0_ccr
-#define AR_IO_I2S_TX_MST0_CCR 0x80019010
-#pragma Aux_register(0x80019010, name=>"io_i2s_tx_mst0_ccr")
-
-// User extension aux register io_i2s_tx_mst0_txffr
-#define AR_IO_I2S_TX_MST0_TXFFR 0x80019018
-#pragma Aux_register(0x80019018, name=>"io_i2s_tx_mst0_txffr")
-
-// User extension aux register io_i2s_tx_mst0_lthr
-#define AR_IO_I2S_TX_MST0_LTHR 0x80019020
-#pragma Aux_register(0x80019020, name=>"io_i2s_tx_mst0_lthr")
-
-// User extension aux register io_i2s_tx_mst0_rthr
-#define AR_IO_I2S_TX_MST0_RTHR 0x80019024
-#pragma Aux_register(0x80019024, name=>"io_i2s_tx_mst0_rthr")
-
-// User extension aux register io_i2s_tx_mst0_ter
-#define AR_IO_I2S_TX_MST0_TER 0x8001902c
-#pragma Aux_register(0x8001902c, name=>"io_i2s_tx_mst0_ter")
-
-// User extension aux register io_i2s_tx_mst0_tcr
-#define AR_IO_I2S_TX_MST0_TCR 0x80019034
-#pragma Aux_register(0x80019034, name=>"io_i2s_tx_mst0_tcr")
-
-// User extension aux register io_i2s_tx_mst0_isr
-#define AR_IO_I2S_TX_MST0_ISR 0x80019038
-#pragma Aux_register(0x80019038, name=>"io_i2s_tx_mst0_isr")
-
-// User extension aux register io_i2s_tx_mst0_imr
-#define AR_IO_I2S_TX_MST0_IMR 0x8001903c
-#pragma Aux_register(0x8001903c, name=>"io_i2s_tx_mst0_imr")
-
-// User extension aux register io_i2s_tx_mst0_tor
-#define AR_IO_I2S_TX_MST0_TOR 0x80019044
-#pragma Aux_register(0x80019044, name=>"io_i2s_tx_mst0_tor")
-
-// User extension aux register io_i2s_tx_mst0_tfcr
-#define AR_IO_I2S_TX_MST0_TFCR 0x8001904c
-#pragma Aux_register(0x8001904c, name=>"io_i2s_tx_mst0_tfcr")
-
-// User extension aux register io_i2s_tx_mst0_tff
-#define AR_IO_I2S_TX_MST0_TFF 0x80019054
-#pragma Aux_register(0x80019054, name=>"io_i2s_tx_mst0_tff")
-
-// User extension aux register io_i2s_tx_mst0_txdma
-#define AR_IO_I2S_TX_MST0_TXDMA 0x800191c8
-#pragma Aux_register(0x800191c8, name=>"io_i2s_tx_mst0_txdma")
-#define APEX_COM_ARC_HARDWARE_DFSS_IO_PDM_RX0_PRESENT	1
-
-// User extension aux register io_pdm_rx0_pdm_en
-#define AR_IO_PDM_RX0_PDM_EN 0x8001b000
-#pragma Aux_register(0x8001b000, name=>"io_pdm_rx0_pdm_en")
-
-// User extension aux register io_pdm_rx0_pdm_ren
-#define AR_IO_PDM_RX0_PDM_REN 0x8001b004
-#pragma Aux_register(0x8001b004, name=>"io_pdm_rx0_pdm_ren")
-
-// User extension aux register io_pdm_rx0_cer
-#define AR_IO_PDM_RX0_CER 0x8001b00c
-#pragma Aux_register(0x8001b00c, name=>"io_pdm_rx0_cer")
-
-// User extension aux register io_pdm_rx0_rxffr
-#define AR_IO_PDM_RX0_RXFFR 0x8001b014
-#pragma Aux_register(0x8001b014, name=>"io_pdm_rx0_rxffr")
-
-// User extension aux register io_pdm_rx0_rer0
-#define AR_IO_PDM_RX0_RER0 0x8001b028
-#pragma Aux_register(0x8001b028, name=>"io_pdm_rx0_rer0")
-
-// User extension aux register io_pdm_rx0_isr
-#define AR_IO_PDM_RX0_ISR 0x8001b038
-#pragma Aux_register(0x8001b038, name=>"io_pdm_rx0_isr")
-
-// User extension aux register io_pdm_rx0_imr
-#define AR_IO_PDM_RX0_IMR 0x8001b03c
-#pragma Aux_register(0x8001b03c, name=>"io_pdm_rx0_imr")
-
-// User extension aux register io_pdm_rx0_ror
-#define AR_IO_PDM_RX0_ROR 0x8001b040
-#pragma Aux_register(0x8001b040, name=>"io_pdm_rx0_ror")
-
-// User extension aux register io_pdm_rx0_rfcr
-#define AR_IO_PDM_RX0_RFCR 0x8001b048
-#pragma Aux_register(0x8001b048, name=>"io_pdm_rx0_rfcr")
-
-// User extension aux register io_pdm_rx0_rxdma
-#define AR_IO_PDM_RX0_RXDMA 0x8001b1c0
-#pragma Aux_register(0x8001b1c0, name=>"io_pdm_rx0_rxdma")
-
-// User extension aux register io_pdm_rx0_pdm_rr
-#define AR_IO_PDM_RX0_PDM_RR 0x8001b1d0
-#pragma Aux_register(0x8001b1d0, name=>"io_pdm_rx0_pdm_rr")
-
-// User extension aux register io_pdm_rx0_cic_n
-#define AR_IO_PDM_RX0_CIC_N 0x8001b1d4
-#pragma Aux_register(0x8001b1d4, name=>"io_pdm_rx0_cic_n")
-
-// User extension aux register io_pdm_rx0_cic_d
-#define AR_IO_PDM_RX0_CIC_D 0x8001b1d8
-#pragma Aux_register(0x8001b1d8, name=>"io_pdm_rx0_cic_d")
-
-// User extension aux register io_pdm_rx0_dcrc
-#define AR_IO_PDM_RX0_DCRC 0x8001b1dc
-#pragma Aux_register(0x8001b1dc, name=>"io_pdm_rx0_dcrc")
-
-// User extension aux register io_pdm_rx0_brc_b0
-#define AR_IO_PDM_RX0_BRC_B0 0x8001b1e0
-#pragma Aux_register(0x8001b1e0, name=>"io_pdm_rx0_brc_b0")
-
-// User extension aux register io_pdm_rx0_brc_clp
-#define AR_IO_PDM_RX0_BRC_CLP 0x8001b1f0
-#pragma Aux_register(0x8001b1f0, name=>"io_pdm_rx0_brc_clp")
-#define APEX_COM_ARC_HARDWARE_FLOATING_POINT_UNIT_FPU_PRESENT	1
-
-// User extension aux register fpu_build
-#define AR_FPU_BUILD 0xc8
-#pragma Aux_register(0xc8, name=>"fpu_build")
-
-// User extension aux register fpu_ctrl
-#define AR_FPU_CTRL 0x300
-#pragma Aux_register(0x300, name=>"fpu_ctrl")
-
-// User extension aux register fpu_status
-#define AR_FPU_STATUS 0x301
-#pragma Aux_register(0x301, name=>"fpu_status")
-
-// User extension instruction fsmadd
-extern long fsmadd(long,long);
-#pragma intrinsic(fsmadd,opcode=>6,sub_opcode=>5, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fsmsub
-extern long fsmsub(long,long);
-#pragma intrinsic(fsmsub,opcode=>6,sub_opcode=>6, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fsmul
-extern long fsmul(long,long);
-#pragma intrinsic(fsmul,opcode=>6,sub_opcode=>0, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fsadd
-extern long fsadd(long,long);
-#pragma intrinsic(fsadd,opcode=>6,sub_opcode=>1, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fssub
-extern long fssub(long,long);
-#pragma intrinsic(fssub,opcode=>6,sub_opcode=>2, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fcvt32
-extern long fcvt32(long,long);
-#pragma intrinsic(fcvt32,opcode=>6,sub_opcode=>8, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fsdiv
-extern long fsdiv(long,long);
-#pragma intrinsic(fsdiv,opcode=>6,sub_opcode=>7, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fscmp
-extern long fscmp(long,long);
-#pragma intrinsic(fscmp,opcode=>6,sub_opcode=>3, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fscmp
-extern long fscmp_f(long,long);
-#pragma intrinsic(fscmp_f,opcode=>6,sub_opcode=>3, set_flags => 1, flags => "zncv", effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fscmpf
-extern long fscmpf(long,long);
-#pragma intrinsic(fscmpf,opcode=>6,sub_opcode=>4, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fscmpf
-extern long fscmpf_f(long,long);
-#pragma intrinsic(fscmpf_f,opcode=>6,sub_opcode=>4, set_flags => 1, flags => "zncv", effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fssqrt
-extern long fssqrt(long);
-#pragma intrinsic(fssqrt,opcode=>6,sub_opcode=>0, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-#define APEX_COM_ARC_HARDWARE_FLOATING_POINT_UNIT_FPU_DP_ASSIST_PRESENT	1
-
-// User extension aux register aux_dpfp1l
-#define AR_AUX_DPFP1L 0x302
-#pragma Aux_register(0x302, name=>"aux_dpfp1l")
-
-// User extension aux register aux_dpfp1h
-#define AR_AUX_DPFP1H 0x303
-#pragma Aux_register(0x303, name=>"aux_dpfp1h")
-
-// User extension aux register aux_dpfp2l
-#define AR_AUX_DPFP2L 0x304
-#pragma Aux_register(0x304, name=>"aux_dpfp2l")
-
-// User extension aux register aux_dpfp2h
-#define AR_AUX_DPFP2H 0x305
-#pragma Aux_register(0x305, name=>"aux_dpfp2h")
-
-// User extension instruction dmulh11
-extern long dmulh11(long,long);
-#pragma intrinsic(dmulh11,opcode=>6,sub_opcode=>48,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dmulh11
-extern long dmulh11_f(long,long);
-#pragma intrinsic(dmulh11_f,opcode=>6,sub_opcode=>48, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dmulh12
-extern long dmulh12(long,long);
-#pragma intrinsic(dmulh12,opcode=>6,sub_opcode=>49,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dmulh12
-extern long dmulh12_f(long,long);
-#pragma intrinsic(dmulh12_f,opcode=>6,sub_opcode=>49, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dmulh21
-extern long dmulh21(long,long);
-#pragma intrinsic(dmulh21,opcode=>6,sub_opcode=>50,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dmulh21
-extern long dmulh21_f(long,long);
-#pragma intrinsic(dmulh21_f,opcode=>6,sub_opcode=>50, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dmulh22
-extern long dmulh22(long,long);
-#pragma intrinsic(dmulh22,opcode=>6,sub_opcode=>51,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dmulh22
-extern long dmulh22_f(long,long);
-#pragma intrinsic(dmulh22_f,opcode=>6,sub_opcode=>51, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction daddh11
-extern long daddh11(long,long);
-#pragma intrinsic(daddh11,opcode=>6,sub_opcode=>52,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction daddh11
-extern long daddh11_f(long,long);
-#pragma intrinsic(daddh11_f,opcode=>6,sub_opcode=>52, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction daddh12
-extern long daddh12(long,long);
-#pragma intrinsic(daddh12,opcode=>6,sub_opcode=>53,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction daddh12
-extern long daddh12_f(long,long);
-#pragma intrinsic(daddh12_f,opcode=>6,sub_opcode=>53, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction daddh21
-extern long daddh21(long,long);
-#pragma intrinsic(daddh21,opcode=>6,sub_opcode=>54,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction daddh21
-extern long daddh21_f(long,long);
-#pragma intrinsic(daddh21_f,opcode=>6,sub_opcode=>54, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction daddh22
-extern long daddh22(long,long);
-#pragma intrinsic(daddh22,opcode=>6,sub_opcode=>55,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction daddh22
-extern long daddh22_f(long,long);
-#pragma intrinsic(daddh22_f,opcode=>6,sub_opcode=>55, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dsubh11
-extern long dsubh11(long,long);
-#pragma intrinsic(dsubh11,opcode=>6,sub_opcode=>56,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dsubh11
-extern long dsubh11_f(long,long);
-#pragma intrinsic(dsubh11_f,opcode=>6,sub_opcode=>56, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dsubh12
-extern long dsubh12(long,long);
-#pragma intrinsic(dsubh12,opcode=>6,sub_opcode=>57,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dsubh12
-extern long dsubh12_f(long,long);
-#pragma intrinsic(dsubh12_f,opcode=>6,sub_opcode=>57, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dsubh21
-extern long dsubh21(long,long);
-#pragma intrinsic(dsubh21,opcode=>6,sub_opcode=>58,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dsubh21
-extern long dsubh21_f(long,long);
-#pragma intrinsic(dsubh21_f,opcode=>6,sub_opcode=>58, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dsubh22
-extern long dsubh22(long,long);
-#pragma intrinsic(dsubh22,opcode=>6,sub_opcode=>59,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dsubh22
-extern long dsubh22_f(long,long);
-#pragma intrinsic(dsubh22_f,opcode=>6,sub_opcode=>59, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dexcl1
-extern long dexcl1(long,long);
-#pragma intrinsic(dexcl1,opcode=>6,sub_opcode=>60, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dexcl2
-extern long dexcl2(long,long);
-#pragma intrinsic(dexcl2,opcode=>6,sub_opcode=>61, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-
-#endif
-
-
-]]>
-  
-  
-    
-  
-
-
diff --git a/board/emsdp/rev1/configs/em6_scss/apexextensions.h b/board/emsdp/rev1/configs/em6_scss/apexextensions.h
deleted file mode 100644
index d9104c5e0..000000000
--- a/board/emsdp/rev1/configs/em6_scss/apexextensions.h
+++ /dev/null
@@ -1,1621 +0,0 @@
-
-/* **** DO NOT EDIT - this file is generated by ARChitect2 ****
- *
- * Description: Header file declaring the compiler extensions for apex components 
- */
-
-#ifndef _apexextensions_H_
-#define _apexextensions_H_
-
-// User extension instruction - dsp_abs_1d
-extern long dsp_abs_1d(long);
-#pragma intrinsic(dsp_abs_1d, opcode => 0x07, sub_opcode => 0x00 )
-
-// User extension instruction - dsp_add_1d
-extern long dsp_add_1d(long, long);
-#pragma intrinsic(dsp_add_1d, opcode => 0x07, sub_opcode => 0x03 )
-
-// User extension instruction - dsp_negate_1d
-extern long dsp_negate_1d(long);
-#pragma intrinsic(dsp_negate_1d, opcode => 0x07, sub_opcode => 0x0F )
-
-// User extension instruction - dsp_shift_1d
-extern long dsp_shift_1d(long, long);
-#pragma intrinsic(dsp_shift_1d, opcode => 0x07, sub_opcode => 0x18 )
-
-// User extension instruction - dsp_cos
-extern long dsp_cos(long);
-#pragma intrinsic(dsp_cos, opcode => 0x07, sub_opcode => 0x1E , latency_cycles => 8)
-
-// User extension instruction - dsp_sqrt
-extern long dsp_sqrt(long);
-#pragma intrinsic(dsp_sqrt, opcode => 0x07, sub_opcode => 0x20 , latency_cycles => 31)
-
-// User extension instruction - dsp_sub_1d
-extern long dsp_sub_1d(long, long);
-#pragma intrinsic(dsp_sub_1d, opcode => 0x07, sub_opcode => 0x06 )
-
-// User extension instruction - dsp_abs_2d
-extern long dsp_abs_2d(long);
-#pragma intrinsic(dsp_abs_2d, opcode => 0x07, sub_opcode => 0x01 )
-
-// User extension instruction - dsp_add_2d
-extern long dsp_add_2d(long, long);
-#pragma intrinsic(dsp_add_2d, opcode => 0x07, sub_opcode => 0x04 )
-
-// User extension instruction - dsp_mulv_2d
-extern long dsp_mulv_2d(long, long);
-#pragma intrinsic(dsp_mulv_2d, opcode => 0x07, sub_opcode => 0x1E )
-
-// User extension instruction - dsp_negate_2d
-extern long dsp_negate_2d(long);
-#pragma intrinsic(dsp_negate_2d, opcode => 0x07, sub_opcode => 0x10 )
-
-// User extension instruction - dsp_shift_2d
-extern long dsp_shift_2d(long, long);
-#pragma intrinsic(dsp_shift_2d, opcode => 0x07, sub_opcode => 0x19 )
-
-// User extension instruction - dsp_sin
-extern long dsp_sin(long);
-#pragma intrinsic(dsp_sin, opcode => 0x07, sub_opcode => 0x1F , latency_cycles => 8)
-
-// User extension instruction - dsp_sqrt15
-extern long dsp_sqrt15(long);
-#pragma intrinsic(dsp_sqrt15, opcode => 0x07, sub_opcode => 0x21 , latency_cycles => 15)
-
-// User extension instruction - dsp_sub_2d
-extern long dsp_sub_2d(long, long);
-#pragma intrinsic(dsp_sub_2d, opcode => 0x07, sub_opcode => 0x07 )
-
-// User extension instruction - dsp_abs_4d
-extern long dsp_abs_4d(long);
-#pragma intrinsic(dsp_abs_4d, opcode => 0x07, sub_opcode => 0x02 )
-
-// User extension instruction - dsp_add_4d
-extern long dsp_add_4d(long, long);
-#pragma intrinsic(dsp_add_4d, opcode => 0x07, sub_opcode => 0x05 )
-
-// User extension instruction - dsp_mulv_4d
-extern long dsp_mulv_4d(long, long);
-#pragma intrinsic(dsp_mulv_4d, opcode => 0x07, sub_opcode => 0x1F )
-
-// User extension instruction - dsp_negate_4d
-extern long dsp_negate_4d(long);
-#pragma intrinsic(dsp_negate_4d, opcode => 0x07, sub_opcode => 0x11 )
-
-// User extension instruction - dsp_shift_4d
-extern long dsp_shift_4d(long, long);
-#pragma intrinsic(dsp_shift_4d, opcode => 0x07, sub_opcode => 0x1A )
-
-// User extension instruction - dsp_sub_4d
-extern long dsp_sub_4d(long, long);
-#pragma intrinsic(dsp_sub_4d, opcode => 0x07, sub_opcode => 0x08 )
-
-#define APEX_COM_ARC_HARDWARE_SCSS_DSP_ABS_PRESENT	1
-#define APEX_COM_ARC_HARDWARE_SCSS_DSP_ACM_PRESENT	1
-
-// User extension core register dsp_acm_msbout
-#define CR_DSP_ACM_MSBOUT 54
-#pragma Core_register(54, name=>"dsp_acm_msbout", non_interlock_cycles=>"2", side_effects=>"rw")
-
-// User extension core register dsp_acm_lsbout
-#define CR_DSP_ACM_LSBOUT 53
-#pragma Core_register(53, name=>"dsp_acm_lsbout", non_interlock_cycles=>"2", side_effects=>"rw")
-
-// User extension instruction dsp_acm
-extern int dsp_acm(int,int);
-#pragma intrinsic(dsp_acm,opcode=>7,sub_opcode=>29, effects=>"dsp_acm_lsbout:is_read:is_written:is_read_cycle=0:is_written_cycle=0; dsp_acm_msbout:is_read:is_written:is_read_cycle=0:is_written_cycle=0")
-#define APEX_COM_ARC_HARDWARE_SCSS_DSP_ADD_PRESENT	1
-#define APEX_COM_ARC_HARDWARE_SCSS_DSP_MAC_PRESENT	1
-
-// User extension core register dsp_mac_lsbout
-#define CR_DSP_MAC_LSBOUT 56
-#pragma Core_register(56, name=>"dsp_mac_lsbout", non_interlock_cycles=>"2", side_effects=>"rw")
-
-// User extension core register dsp_mac_msbout
-#define CR_DSP_MAC_MSBOUT 57
-#pragma Core_register(57, name=>"dsp_mac_msbout", non_interlock_cycles=>"2", side_effects=>"rw")
-
-// User extension instruction dsp_mac
-extern int dsp_mac(int,int);
-#pragma intrinsic(dsp_mac,opcode=>7,sub_opcode=>27, effects=>"dsp_mac_lsbout:is_read:is_written:is_read_cycle=0:is_written_cycle=0; dsp_mac_msbout:is_read:is_written:is_read_cycle=0:is_written_cycle=0")
-
-// User extension instruction dsp_mult
-extern int dsp_mult(int,int);
-#pragma intrinsic(dsp_mult,opcode=>7,sub_opcode=>28, effects=>"dsp_mac_lsbout:is_read:is_written:is_read_cycle=0:is_written_cycle=0; dsp_mac_msbout:is_read:is_written:is_read_cycle=0:is_written_cycle=0")
-#define APEX_COM_ARC_HARDWARE_SCSS_DSP_MULT_PRESENT	1
-
-// User extension core register dsp_mult
-#define CR_DSP_MULT 55
-#pragma Core_register(55, name=>"dsp_mult", non_interlock_cycles=>"2")
-
-// User extension instruction dsp_mult_2d
-extern int dsp_mult_2d(int,int);
-#pragma intrinsic(dsp_mult_2d,opcode=>7,sub_opcode=>13, effects=>"dsp_mult:is_written:is_read_cycle=0:is_written_cycle=0")
-
-// User extension instruction dsp_mult_4d
-extern int dsp_mult_4d(int,int);
-#pragma intrinsic(dsp_mult_4d,opcode=>7,sub_opcode=>14, effects=>"dsp_mult:is_written:is_read_cycle=0:is_written_cycle=0")
-#define APEX_COM_ARC_HARDWARE_SCSS_DSP_MULV_PRESENT	1
-#define APEX_COM_ARC_HARDWARE_SCSS_DSP_NEGATE_PRESENT	1
-#define APEX_COM_ARC_HARDWARE_SCSS_DSP_SHIFT_PRESENT	1
-#define APEX_COM_ARC_HARDWARE_SCSS_DSP_SINCOS_PRESENT	1
-#define APEX_COM_ARC_HARDWARE_SCSS_DSP_SQRT_PRESENT	1
-#define APEX_COM_ARC_HARDWARE_SCSS_DSP_SUB_PRESENT	1
-#define APEX_COM_ARC_HARDWARE_SCSS_IO_GPIO0_PRESENT	1
-
-// User extension aux register io_gpio0_debounce
-#define AR_IO_GPIO0_DEBOUNCE 0x80017048
-#pragma Aux_register(0x80017048, name=>"io_gpio0_debounce")
-
-// User extension aux register io_gpio0_clken
-#define AR_IO_GPIO0_CLKEN 0x80017080
-#pragma Aux_register(0x80017080, name=>"io_gpio0_clken")
-
-// User extension aux register io_gpio0_swporta_dr
-#define AR_IO_GPIO0_SWPORTA_DR 0x80017000
-#pragma Aux_register(0x80017000, name=>"io_gpio0_swporta_dr")
-
-// User extension aux register io_gpio0_swporta_ddr
-#define AR_IO_GPIO0_SWPORTA_DDR 0x80017004
-#pragma Aux_register(0x80017004, name=>"io_gpio0_swporta_ddr")
-
-// User extension aux register io_gpio0_inten
-#define AR_IO_GPIO0_INTEN 0x80017030
-#pragma Aux_register(0x80017030, name=>"io_gpio0_inten")
-
-// User extension aux register io_gpio0_intmask
-#define AR_IO_GPIO0_INTMASK 0x80017034
-#pragma Aux_register(0x80017034, name=>"io_gpio0_intmask")
-
-// User extension aux register io_gpio0_inttype_level
-#define AR_IO_GPIO0_INTTYPE_LEVEL 0x80017038
-#pragma Aux_register(0x80017038, name=>"io_gpio0_inttype_level")
-
-// User extension aux register io_gpio0_int_polarity
-#define AR_IO_GPIO0_INT_POLARITY 0x8001703c
-#pragma Aux_register(0x8001703c, name=>"io_gpio0_int_polarity")
-
-// User extension aux register io_gpio0_intstatus
-#define AR_IO_GPIO0_INTSTATUS 0x80017040
-#pragma Aux_register(0x80017040, name=>"io_gpio0_intstatus")
-
-// User extension aux register io_gpio0_raw_intstatus
-#define AR_IO_GPIO0_RAW_INTSTATUS 0x80017044
-#pragma Aux_register(0x80017044, name=>"io_gpio0_raw_intstatus")
-
-// User extension aux register io_gpio0_porta_eoi
-#define AR_IO_GPIO0_PORTA_EOI 0x8001704c
-#pragma Aux_register(0x8001704c, name=>"io_gpio0_porta_eoi")
-
-// User extension aux register io_gpio0_ext_porta
-#define AR_IO_GPIO0_EXT_PORTA 0x80017050
-#pragma Aux_register(0x80017050, name=>"io_gpio0_ext_porta")
-
-// User extension aux register io_gpio0_ls_sync
-#define AR_IO_GPIO0_LS_SYNC 0x80017060
-#pragma Aux_register(0x80017060, name=>"io_gpio0_ls_sync")
-
-// User extension aux register io_gpio0_int_bothedge
-#define AR_IO_GPIO0_INT_BOTHEDGE 0x80017068
-#pragma Aux_register(0x80017068, name=>"io_gpio0_int_bothedge")
-#define APEX_COM_ARC_HARDWARE_SCSS_IO_GPIO1_PRESENT	1
-
-// User extension aux register io_gpio1_debounce
-#define AR_IO_GPIO1_DEBOUNCE 0x80017148
-#pragma Aux_register(0x80017148, name=>"io_gpio1_debounce")
-
-// User extension aux register io_gpio1_clken
-#define AR_IO_GPIO1_CLKEN 0x80017180
-#pragma Aux_register(0x80017180, name=>"io_gpio1_clken")
-
-// User extension aux register io_gpio1_swporta_dr
-#define AR_IO_GPIO1_SWPORTA_DR 0x80017100
-#pragma Aux_register(0x80017100, name=>"io_gpio1_swporta_dr")
-
-// User extension aux register io_gpio1_swporta_ddr
-#define AR_IO_GPIO1_SWPORTA_DDR 0x80017104
-#pragma Aux_register(0x80017104, name=>"io_gpio1_swporta_ddr")
-
-// User extension aux register io_gpio1_inten
-#define AR_IO_GPIO1_INTEN 0x80017130
-#pragma Aux_register(0x80017130, name=>"io_gpio1_inten")
-
-// User extension aux register io_gpio1_intmask
-#define AR_IO_GPIO1_INTMASK 0x80017134
-#pragma Aux_register(0x80017134, name=>"io_gpio1_intmask")
-
-// User extension aux register io_gpio1_inttype_level
-#define AR_IO_GPIO1_INTTYPE_LEVEL 0x80017138
-#pragma Aux_register(0x80017138, name=>"io_gpio1_inttype_level")
-
-// User extension aux register io_gpio1_int_polarity
-#define AR_IO_GPIO1_INT_POLARITY 0x8001713c
-#pragma Aux_register(0x8001713c, name=>"io_gpio1_int_polarity")
-
-// User extension aux register io_gpio1_intstatus
-#define AR_IO_GPIO1_INTSTATUS 0x80017140
-#pragma Aux_register(0x80017140, name=>"io_gpio1_intstatus")
-
-// User extension aux register io_gpio1_raw_intstatus
-#define AR_IO_GPIO1_RAW_INTSTATUS 0x80017144
-#pragma Aux_register(0x80017144, name=>"io_gpio1_raw_intstatus")
-
-// User extension aux register io_gpio1_porta_eoi
-#define AR_IO_GPIO1_PORTA_EOI 0x8001714c
-#pragma Aux_register(0x8001714c, name=>"io_gpio1_porta_eoi")
-
-// User extension aux register io_gpio1_ext_porta
-#define AR_IO_GPIO1_EXT_PORTA 0x80017150
-#pragma Aux_register(0x80017150, name=>"io_gpio1_ext_porta")
-
-// User extension aux register io_gpio1_ls_sync
-#define AR_IO_GPIO1_LS_SYNC 0x80017160
-#pragma Aux_register(0x80017160, name=>"io_gpio1_ls_sync")
-
-// User extension aux register io_gpio1_int_bothedge
-#define AR_IO_GPIO1_INT_BOTHEDGE 0x80017168
-#pragma Aux_register(0x80017168, name=>"io_gpio1_int_bothedge")
-#define APEX_COM_ARC_HARDWARE_SCSS_IO_GPIO2_PRESENT	1
-
-// User extension aux register io_gpio2_debounce
-#define AR_IO_GPIO2_DEBOUNCE 0x80017248
-#pragma Aux_register(0x80017248, name=>"io_gpio2_debounce")
-
-// User extension aux register io_gpio2_clken
-#define AR_IO_GPIO2_CLKEN 0x80017280
-#pragma Aux_register(0x80017280, name=>"io_gpio2_clken")
-
-// User extension aux register io_gpio2_swporta_dr
-#define AR_IO_GPIO2_SWPORTA_DR 0x80017200
-#pragma Aux_register(0x80017200, name=>"io_gpio2_swporta_dr")
-
-// User extension aux register io_gpio2_swporta_ddr
-#define AR_IO_GPIO2_SWPORTA_DDR 0x80017204
-#pragma Aux_register(0x80017204, name=>"io_gpio2_swporta_ddr")
-
-// User extension aux register io_gpio2_inten
-#define AR_IO_GPIO2_INTEN 0x80017230
-#pragma Aux_register(0x80017230, name=>"io_gpio2_inten")
-
-// User extension aux register io_gpio2_intmask
-#define AR_IO_GPIO2_INTMASK 0x80017234
-#pragma Aux_register(0x80017234, name=>"io_gpio2_intmask")
-
-// User extension aux register io_gpio2_inttype_level
-#define AR_IO_GPIO2_INTTYPE_LEVEL 0x80017238
-#pragma Aux_register(0x80017238, name=>"io_gpio2_inttype_level")
-
-// User extension aux register io_gpio2_int_polarity
-#define AR_IO_GPIO2_INT_POLARITY 0x8001723c
-#pragma Aux_register(0x8001723c, name=>"io_gpio2_int_polarity")
-
-// User extension aux register io_gpio2_intstatus
-#define AR_IO_GPIO2_INTSTATUS 0x80017240
-#pragma Aux_register(0x80017240, name=>"io_gpio2_intstatus")
-
-// User extension aux register io_gpio2_raw_intstatus
-#define AR_IO_GPIO2_RAW_INTSTATUS 0x80017244
-#pragma Aux_register(0x80017244, name=>"io_gpio2_raw_intstatus")
-
-// User extension aux register io_gpio2_porta_eoi
-#define AR_IO_GPIO2_PORTA_EOI 0x8001724c
-#pragma Aux_register(0x8001724c, name=>"io_gpio2_porta_eoi")
-
-// User extension aux register io_gpio2_ext_porta
-#define AR_IO_GPIO2_EXT_PORTA 0x80017250
-#pragma Aux_register(0x80017250, name=>"io_gpio2_ext_porta")
-
-// User extension aux register io_gpio2_ls_sync
-#define AR_IO_GPIO2_LS_SYNC 0x80017260
-#pragma Aux_register(0x80017260, name=>"io_gpio2_ls_sync")
-
-// User extension aux register io_gpio2_int_bothedge
-#define AR_IO_GPIO2_INT_BOTHEDGE 0x80017268
-#pragma Aux_register(0x80017268, name=>"io_gpio2_int_bothedge")
-#define APEX_COM_ARC_HARDWARE_SCSS_IO_I2C_MST0_PRESENT	1
-
-// User extension aux register io_i2c_mst0_clken
-#define AR_IO_I2C_MST0_CLKEN 0x800120c0
-#pragma Aux_register(0x800120c0, name=>"io_i2c_mst0_clken")
-
-// User extension aux register io_i2c_mst0_con
-#define AR_IO_I2C_MST0_CON 0x80012000
-#pragma Aux_register(0x80012000, name=>"io_i2c_mst0_con")
-
-// User extension aux register io_i2c_mst0_tar
-#define AR_IO_I2C_MST0_TAR 0x80012004
-#pragma Aux_register(0x80012004, name=>"io_i2c_mst0_tar")
-
-// User extension aux register io_i2c_mst0_data_cmd
-#define AR_IO_I2C_MST0_DATA_CMD 0x80012010
-#pragma Aux_register(0x80012010, name=>"io_i2c_mst0_data_cmd")
-
-// User extension aux register io_i2c_mst0_ss_scl_hcnt
-#define AR_IO_I2C_MST0_SS_SCL_HCNT 0x80012014
-#pragma Aux_register(0x80012014, name=>"io_i2c_mst0_ss_scl_hcnt")
-
-// User extension aux register io_i2c_mst0_ss_scl_lcnt
-#define AR_IO_I2C_MST0_SS_SCL_LCNT 0x80012018
-#pragma Aux_register(0x80012018, name=>"io_i2c_mst0_ss_scl_lcnt")
-
-// User extension aux register io_i2c_mst0_fs_scl_hcnt
-#define AR_IO_I2C_MST0_FS_SCL_HCNT 0x8001201c
-#pragma Aux_register(0x8001201c, name=>"io_i2c_mst0_fs_scl_hcnt")
-
-// User extension aux register io_i2c_mst0_fs_scl_lcnt
-#define AR_IO_I2C_MST0_FS_SCL_LCNT 0x80012020
-#pragma Aux_register(0x80012020, name=>"io_i2c_mst0_fs_scl_lcnt")
-
-// User extension aux register io_i2c_mst0_intr_stat
-#define AR_IO_I2C_MST0_INTR_STAT 0x8001202c
-#pragma Aux_register(0x8001202c, name=>"io_i2c_mst0_intr_stat")
-
-// User extension aux register io_i2c_mst0_intr_mask
-#define AR_IO_I2C_MST0_INTR_MASK 0x80012030
-#pragma Aux_register(0x80012030, name=>"io_i2c_mst0_intr_mask")
-
-// User extension aux register io_i2c_mst0_raw_intr_stat
-#define AR_IO_I2C_MST0_RAW_INTR_STAT 0x80012034
-#pragma Aux_register(0x80012034, name=>"io_i2c_mst0_raw_intr_stat")
-
-// User extension aux register io_i2c_mst0_rx_tl
-#define AR_IO_I2C_MST0_RX_TL 0x80012038
-#pragma Aux_register(0x80012038, name=>"io_i2c_mst0_rx_tl")
-
-// User extension aux register io_i2c_mst0_tx_tl
-#define AR_IO_I2C_MST0_TX_TL 0x8001203c
-#pragma Aux_register(0x8001203c, name=>"io_i2c_mst0_tx_tl")
-
-// User extension aux register io_i2c_mst0_clr_intr
-#define AR_IO_I2C_MST0_CLR_INTR 0x80012040
-#pragma Aux_register(0x80012040, name=>"io_i2c_mst0_clr_intr")
-
-// User extension aux register io_i2c_mst0_clr_rx_under
-#define AR_IO_I2C_MST0_CLR_RX_UNDER 0x80012044
-#pragma Aux_register(0x80012044, name=>"io_i2c_mst0_clr_rx_under")
-
-// User extension aux register io_i2c_mst0_clr_rx_over
-#define AR_IO_I2C_MST0_CLR_RX_OVER 0x80012048
-#pragma Aux_register(0x80012048, name=>"io_i2c_mst0_clr_rx_over")
-
-// User extension aux register io_i2c_mst0_clr_tx_over
-#define AR_IO_I2C_MST0_CLR_TX_OVER 0x8001204c
-#pragma Aux_register(0x8001204c, name=>"io_i2c_mst0_clr_tx_over")
-
-// User extension aux register io_i2c_mst0_clr_tx_abrt
-#define AR_IO_I2C_MST0_CLR_TX_ABRT 0x80012054
-#pragma Aux_register(0x80012054, name=>"io_i2c_mst0_clr_tx_abrt")
-
-// User extension aux register io_i2c_mst0_clr_activity
-#define AR_IO_I2C_MST0_CLR_ACTIVITY 0x8001205c
-#pragma Aux_register(0x8001205c, name=>"io_i2c_mst0_clr_activity")
-
-// User extension aux register io_i2c_mst0_clr_stop_det
-#define AR_IO_I2C_MST0_CLR_STOP_DET 0x80012060
-#pragma Aux_register(0x80012060, name=>"io_i2c_mst0_clr_stop_det")
-
-// User extension aux register io_i2c_mst0_clr_start_det
-#define AR_IO_I2C_MST0_CLR_START_DET 0x80012064
-#pragma Aux_register(0x80012064, name=>"io_i2c_mst0_clr_start_det")
-
-// User extension aux register io_i2c_mst0_enable
-#define AR_IO_I2C_MST0_ENABLE 0x8001206c
-#pragma Aux_register(0x8001206c, name=>"io_i2c_mst0_enable")
-
-// User extension aux register io_i2c_mst0_status
-#define AR_IO_I2C_MST0_STATUS 0x80012070
-#pragma Aux_register(0x80012070, name=>"io_i2c_mst0_status")
-
-// User extension aux register io_i2c_mst0_txflr
-#define AR_IO_I2C_MST0_TXFLR 0x80012074
-#pragma Aux_register(0x80012074, name=>"io_i2c_mst0_txflr")
-
-// User extension aux register io_i2c_mst0_rxflr
-#define AR_IO_I2C_MST0_RXFLR 0x80012078
-#pragma Aux_register(0x80012078, name=>"io_i2c_mst0_rxflr")
-
-// User extension aux register io_i2c_mst0_sda_hold
-#define AR_IO_I2C_MST0_SDA_HOLD 0x8001207c
-#pragma Aux_register(0x8001207c, name=>"io_i2c_mst0_sda_hold")
-
-// User extension aux register io_i2c_mst0_tx_abrt_source
-#define AR_IO_I2C_MST0_TX_ABRT_SOURCE 0x80012080
-#pragma Aux_register(0x80012080, name=>"io_i2c_mst0_tx_abrt_source")
-
-// User extension aux register io_i2c_mst0_enable_status
-#define AR_IO_I2C_MST0_ENABLE_STATUS 0x8001209c
-#pragma Aux_register(0x8001209c, name=>"io_i2c_mst0_enable_status")
-
-// User extension aux register io_i2c_mst0_fs_spklen
-#define AR_IO_I2C_MST0_FS_SPKLEN 0x800120a0
-#pragma Aux_register(0x800120a0, name=>"io_i2c_mst0_fs_spklen")
-#define APEX_COM_ARC_HARDWARE_SCSS_IO_I2C_MST1_PRESENT	1
-
-// User extension aux register io_i2c_mst1_clken
-#define AR_IO_I2C_MST1_CLKEN 0x800121c0
-#pragma Aux_register(0x800121c0, name=>"io_i2c_mst1_clken")
-
-// User extension aux register io_i2c_mst1_con
-#define AR_IO_I2C_MST1_CON 0x80012100
-#pragma Aux_register(0x80012100, name=>"io_i2c_mst1_con")
-
-// User extension aux register io_i2c_mst1_tar
-#define AR_IO_I2C_MST1_TAR 0x80012104
-#pragma Aux_register(0x80012104, name=>"io_i2c_mst1_tar")
-
-// User extension aux register io_i2c_mst1_data_cmd
-#define AR_IO_I2C_MST1_DATA_CMD 0x80012110
-#pragma Aux_register(0x80012110, name=>"io_i2c_mst1_data_cmd")
-
-// User extension aux register io_i2c_mst1_ss_scl_hcnt
-#define AR_IO_I2C_MST1_SS_SCL_HCNT 0x80012114
-#pragma Aux_register(0x80012114, name=>"io_i2c_mst1_ss_scl_hcnt")
-
-// User extension aux register io_i2c_mst1_ss_scl_lcnt
-#define AR_IO_I2C_MST1_SS_SCL_LCNT 0x80012118
-#pragma Aux_register(0x80012118, name=>"io_i2c_mst1_ss_scl_lcnt")
-
-// User extension aux register io_i2c_mst1_fs_scl_hcnt
-#define AR_IO_I2C_MST1_FS_SCL_HCNT 0x8001211c
-#pragma Aux_register(0x8001211c, name=>"io_i2c_mst1_fs_scl_hcnt")
-
-// User extension aux register io_i2c_mst1_fs_scl_lcnt
-#define AR_IO_I2C_MST1_FS_SCL_LCNT 0x80012120
-#pragma Aux_register(0x80012120, name=>"io_i2c_mst1_fs_scl_lcnt")
-
-// User extension aux register io_i2c_mst1_intr_stat
-#define AR_IO_I2C_MST1_INTR_STAT 0x8001212c
-#pragma Aux_register(0x8001212c, name=>"io_i2c_mst1_intr_stat")
-
-// User extension aux register io_i2c_mst1_intr_mask
-#define AR_IO_I2C_MST1_INTR_MASK 0x80012130
-#pragma Aux_register(0x80012130, name=>"io_i2c_mst1_intr_mask")
-
-// User extension aux register io_i2c_mst1_raw_intr_stat
-#define AR_IO_I2C_MST1_RAW_INTR_STAT 0x80012134
-#pragma Aux_register(0x80012134, name=>"io_i2c_mst1_raw_intr_stat")
-
-// User extension aux register io_i2c_mst1_rx_tl
-#define AR_IO_I2C_MST1_RX_TL 0x80012138
-#pragma Aux_register(0x80012138, name=>"io_i2c_mst1_rx_tl")
-
-// User extension aux register io_i2c_mst1_tx_tl
-#define AR_IO_I2C_MST1_TX_TL 0x8001213c
-#pragma Aux_register(0x8001213c, name=>"io_i2c_mst1_tx_tl")
-
-// User extension aux register io_i2c_mst1_clr_intr
-#define AR_IO_I2C_MST1_CLR_INTR 0x80012140
-#pragma Aux_register(0x80012140, name=>"io_i2c_mst1_clr_intr")
-
-// User extension aux register io_i2c_mst1_clr_rx_under
-#define AR_IO_I2C_MST1_CLR_RX_UNDER 0x80012144
-#pragma Aux_register(0x80012144, name=>"io_i2c_mst1_clr_rx_under")
-
-// User extension aux register io_i2c_mst1_clr_rx_over
-#define AR_IO_I2C_MST1_CLR_RX_OVER 0x80012148
-#pragma Aux_register(0x80012148, name=>"io_i2c_mst1_clr_rx_over")
-
-// User extension aux register io_i2c_mst1_clr_tx_over
-#define AR_IO_I2C_MST1_CLR_TX_OVER 0x8001214c
-#pragma Aux_register(0x8001214c, name=>"io_i2c_mst1_clr_tx_over")
-
-// User extension aux register io_i2c_mst1_clr_tx_abrt
-#define AR_IO_I2C_MST1_CLR_TX_ABRT 0x80012154
-#pragma Aux_register(0x80012154, name=>"io_i2c_mst1_clr_tx_abrt")
-
-// User extension aux register io_i2c_mst1_clr_activity
-#define AR_IO_I2C_MST1_CLR_ACTIVITY 0x8001215c
-#pragma Aux_register(0x8001215c, name=>"io_i2c_mst1_clr_activity")
-
-// User extension aux register io_i2c_mst1_clr_stop_det
-#define AR_IO_I2C_MST1_CLR_STOP_DET 0x80012160
-#pragma Aux_register(0x80012160, name=>"io_i2c_mst1_clr_stop_det")
-
-// User extension aux register io_i2c_mst1_clr_start_det
-#define AR_IO_I2C_MST1_CLR_START_DET 0x80012164
-#pragma Aux_register(0x80012164, name=>"io_i2c_mst1_clr_start_det")
-
-// User extension aux register io_i2c_mst1_enable
-#define AR_IO_I2C_MST1_ENABLE 0x8001216c
-#pragma Aux_register(0x8001216c, name=>"io_i2c_mst1_enable")
-
-// User extension aux register io_i2c_mst1_status
-#define AR_IO_I2C_MST1_STATUS 0x80012170
-#pragma Aux_register(0x80012170, name=>"io_i2c_mst1_status")
-
-// User extension aux register io_i2c_mst1_txflr
-#define AR_IO_I2C_MST1_TXFLR 0x80012174
-#pragma Aux_register(0x80012174, name=>"io_i2c_mst1_txflr")
-
-// User extension aux register io_i2c_mst1_rxflr
-#define AR_IO_I2C_MST1_RXFLR 0x80012178
-#pragma Aux_register(0x80012178, name=>"io_i2c_mst1_rxflr")
-
-// User extension aux register io_i2c_mst1_sda_hold
-#define AR_IO_I2C_MST1_SDA_HOLD 0x8001217c
-#pragma Aux_register(0x8001217c, name=>"io_i2c_mst1_sda_hold")
-
-// User extension aux register io_i2c_mst1_tx_abrt_source
-#define AR_IO_I2C_MST1_TX_ABRT_SOURCE 0x80012180
-#pragma Aux_register(0x80012180, name=>"io_i2c_mst1_tx_abrt_source")
-
-// User extension aux register io_i2c_mst1_enable_status
-#define AR_IO_I2C_MST1_ENABLE_STATUS 0x8001219c
-#pragma Aux_register(0x8001219c, name=>"io_i2c_mst1_enable_status")
-
-// User extension aux register io_i2c_mst1_fs_spklen
-#define AR_IO_I2C_MST1_FS_SPKLEN 0x800121a0
-#pragma Aux_register(0x800121a0, name=>"io_i2c_mst1_fs_spklen")
-#define APEX_COM_ARC_HARDWARE_SCSS_IO_I2C_MST2_PRESENT	1
-
-// User extension aux register io_i2c_mst2_clken
-#define AR_IO_I2C_MST2_CLKEN 0x800122c0
-#pragma Aux_register(0x800122c0, name=>"io_i2c_mst2_clken")
-
-// User extension aux register io_i2c_mst2_con
-#define AR_IO_I2C_MST2_CON 0x80012200
-#pragma Aux_register(0x80012200, name=>"io_i2c_mst2_con")
-
-// User extension aux register io_i2c_mst2_tar
-#define AR_IO_I2C_MST2_TAR 0x80012204
-#pragma Aux_register(0x80012204, name=>"io_i2c_mst2_tar")
-
-// User extension aux register io_i2c_mst2_data_cmd
-#define AR_IO_I2C_MST2_DATA_CMD 0x80012210
-#pragma Aux_register(0x80012210, name=>"io_i2c_mst2_data_cmd")
-
-// User extension aux register io_i2c_mst2_ss_scl_hcnt
-#define AR_IO_I2C_MST2_SS_SCL_HCNT 0x80012214
-#pragma Aux_register(0x80012214, name=>"io_i2c_mst2_ss_scl_hcnt")
-
-// User extension aux register io_i2c_mst2_ss_scl_lcnt
-#define AR_IO_I2C_MST2_SS_SCL_LCNT 0x80012218
-#pragma Aux_register(0x80012218, name=>"io_i2c_mst2_ss_scl_lcnt")
-
-// User extension aux register io_i2c_mst2_fs_scl_hcnt
-#define AR_IO_I2C_MST2_FS_SCL_HCNT 0x8001221c
-#pragma Aux_register(0x8001221c, name=>"io_i2c_mst2_fs_scl_hcnt")
-
-// User extension aux register io_i2c_mst2_fs_scl_lcnt
-#define AR_IO_I2C_MST2_FS_SCL_LCNT 0x80012220
-#pragma Aux_register(0x80012220, name=>"io_i2c_mst2_fs_scl_lcnt")
-
-// User extension aux register io_i2c_mst2_intr_stat
-#define AR_IO_I2C_MST2_INTR_STAT 0x8001222c
-#pragma Aux_register(0x8001222c, name=>"io_i2c_mst2_intr_stat")
-
-// User extension aux register io_i2c_mst2_intr_mask
-#define AR_IO_I2C_MST2_INTR_MASK 0x80012230
-#pragma Aux_register(0x80012230, name=>"io_i2c_mst2_intr_mask")
-
-// User extension aux register io_i2c_mst2_raw_intr_stat
-#define AR_IO_I2C_MST2_RAW_INTR_STAT 0x80012234
-#pragma Aux_register(0x80012234, name=>"io_i2c_mst2_raw_intr_stat")
-
-// User extension aux register io_i2c_mst2_rx_tl
-#define AR_IO_I2C_MST2_RX_TL 0x80012238
-#pragma Aux_register(0x80012238, name=>"io_i2c_mst2_rx_tl")
-
-// User extension aux register io_i2c_mst2_tx_tl
-#define AR_IO_I2C_MST2_TX_TL 0x8001223c
-#pragma Aux_register(0x8001223c, name=>"io_i2c_mst2_tx_tl")
-
-// User extension aux register io_i2c_mst2_clr_intr
-#define AR_IO_I2C_MST2_CLR_INTR 0x80012240
-#pragma Aux_register(0x80012240, name=>"io_i2c_mst2_clr_intr")
-
-// User extension aux register io_i2c_mst2_clr_rx_under
-#define AR_IO_I2C_MST2_CLR_RX_UNDER 0x80012244
-#pragma Aux_register(0x80012244, name=>"io_i2c_mst2_clr_rx_under")
-
-// User extension aux register io_i2c_mst2_clr_rx_over
-#define AR_IO_I2C_MST2_CLR_RX_OVER 0x80012248
-#pragma Aux_register(0x80012248, name=>"io_i2c_mst2_clr_rx_over")
-
-// User extension aux register io_i2c_mst2_clr_tx_over
-#define AR_IO_I2C_MST2_CLR_TX_OVER 0x8001224c
-#pragma Aux_register(0x8001224c, name=>"io_i2c_mst2_clr_tx_over")
-
-// User extension aux register io_i2c_mst2_clr_tx_abrt
-#define AR_IO_I2C_MST2_CLR_TX_ABRT 0x80012254
-#pragma Aux_register(0x80012254, name=>"io_i2c_mst2_clr_tx_abrt")
-
-// User extension aux register io_i2c_mst2_clr_activity
-#define AR_IO_I2C_MST2_CLR_ACTIVITY 0x8001225c
-#pragma Aux_register(0x8001225c, name=>"io_i2c_mst2_clr_activity")
-
-// User extension aux register io_i2c_mst2_clr_stop_det
-#define AR_IO_I2C_MST2_CLR_STOP_DET 0x80012260
-#pragma Aux_register(0x80012260, name=>"io_i2c_mst2_clr_stop_det")
-
-// User extension aux register io_i2c_mst2_clr_start_det
-#define AR_IO_I2C_MST2_CLR_START_DET 0x80012264
-#pragma Aux_register(0x80012264, name=>"io_i2c_mst2_clr_start_det")
-
-// User extension aux register io_i2c_mst2_enable
-#define AR_IO_I2C_MST2_ENABLE 0x8001226c
-#pragma Aux_register(0x8001226c, name=>"io_i2c_mst2_enable")
-
-// User extension aux register io_i2c_mst2_status
-#define AR_IO_I2C_MST2_STATUS 0x80012270
-#pragma Aux_register(0x80012270, name=>"io_i2c_mst2_status")
-
-// User extension aux register io_i2c_mst2_txflr
-#define AR_IO_I2C_MST2_TXFLR 0x80012274
-#pragma Aux_register(0x80012274, name=>"io_i2c_mst2_txflr")
-
-// User extension aux register io_i2c_mst2_rxflr
-#define AR_IO_I2C_MST2_RXFLR 0x80012278
-#pragma Aux_register(0x80012278, name=>"io_i2c_mst2_rxflr")
-
-// User extension aux register io_i2c_mst2_sda_hold
-#define AR_IO_I2C_MST2_SDA_HOLD 0x8001227c
-#pragma Aux_register(0x8001227c, name=>"io_i2c_mst2_sda_hold")
-
-// User extension aux register io_i2c_mst2_tx_abrt_source
-#define AR_IO_I2C_MST2_TX_ABRT_SOURCE 0x80012280
-#pragma Aux_register(0x80012280, name=>"io_i2c_mst2_tx_abrt_source")
-
-// User extension aux register io_i2c_mst2_enable_status
-#define AR_IO_I2C_MST2_ENABLE_STATUS 0x8001229c
-#pragma Aux_register(0x8001229c, name=>"io_i2c_mst2_enable_status")
-
-// User extension aux register io_i2c_mst2_fs_spklen
-#define AR_IO_I2C_MST2_FS_SPKLEN 0x800122a0
-#pragma Aux_register(0x800122a0, name=>"io_i2c_mst2_fs_spklen")
-#define APEX_COM_ARC_HARDWARE_SCSS_IO_I2C_SLV0_PRESENT	1
-
-// User extension aux register io_i2c_slv0_clken
-#define AR_IO_I2C_SLV0_CLKEN 0x800130c0
-#pragma Aux_register(0x800130c0, name=>"io_i2c_slv0_clken")
-
-// User extension aux register io_i2c_slv0_con
-#define AR_IO_I2C_SLV0_CON 0x80013000
-#pragma Aux_register(0x80013000, name=>"io_i2c_slv0_con")
-
-// User extension aux register io_i2c_slv0_sar
-#define AR_IO_I2C_SLV0_SAR 0x80013008
-#pragma Aux_register(0x80013008, name=>"io_i2c_slv0_sar")
-
-// User extension aux register io_i2c_slv0_data_cmd
-#define AR_IO_I2C_SLV0_DATA_CMD 0x80013010
-#pragma Aux_register(0x80013010, name=>"io_i2c_slv0_data_cmd")
-
-// User extension aux register io_i2c_slv0_intr_stat
-#define AR_IO_I2C_SLV0_INTR_STAT 0x8001302c
-#pragma Aux_register(0x8001302c, name=>"io_i2c_slv0_intr_stat")
-
-// User extension aux register io_i2c_slv0_intr_mask
-#define AR_IO_I2C_SLV0_INTR_MASK 0x80013030
-#pragma Aux_register(0x80013030, name=>"io_i2c_slv0_intr_mask")
-
-// User extension aux register io_i2c_slv0_raw_intr_stat
-#define AR_IO_I2C_SLV0_RAW_INTR_STAT 0x80013034
-#pragma Aux_register(0x80013034, name=>"io_i2c_slv0_raw_intr_stat")
-
-// User extension aux register io_i2c_slv0_rx_tl
-#define AR_IO_I2C_SLV0_RX_TL 0x80013038
-#pragma Aux_register(0x80013038, name=>"io_i2c_slv0_rx_tl")
-
-// User extension aux register io_i2c_slv0_tx_tl
-#define AR_IO_I2C_SLV0_TX_TL 0x8001303c
-#pragma Aux_register(0x8001303c, name=>"io_i2c_slv0_tx_tl")
-
-// User extension aux register io_i2c_slv0_clr_intr
-#define AR_IO_I2C_SLV0_CLR_INTR 0x80013040
-#pragma Aux_register(0x80013040, name=>"io_i2c_slv0_clr_intr")
-
-// User extension aux register io_i2c_slv0_clr_rx_under
-#define AR_IO_I2C_SLV0_CLR_RX_UNDER 0x80013044
-#pragma Aux_register(0x80013044, name=>"io_i2c_slv0_clr_rx_under")
-
-// User extension aux register io_i2c_slv0_clr_rx_over
-#define AR_IO_I2C_SLV0_CLR_RX_OVER 0x80013048
-#pragma Aux_register(0x80013048, name=>"io_i2c_slv0_clr_rx_over")
-
-// User extension aux register io_i2c_slv0_clr_tx_over
-#define AR_IO_I2C_SLV0_CLR_TX_OVER 0x8001304c
-#pragma Aux_register(0x8001304c, name=>"io_i2c_slv0_clr_tx_over")
-
-// User extension aux register io_i2c_slv0_clr_rd_req
-#define AR_IO_I2C_SLV0_CLR_RD_REQ 0x80013050
-#pragma Aux_register(0x80013050, name=>"io_i2c_slv0_clr_rd_req")
-
-// User extension aux register io_i2c_slv0_clr_tx_abrt
-#define AR_IO_I2C_SLV0_CLR_TX_ABRT 0x80013054
-#pragma Aux_register(0x80013054, name=>"io_i2c_slv0_clr_tx_abrt")
-
-// User extension aux register io_i2c_slv0_clr_rx_done
-#define AR_IO_I2C_SLV0_CLR_RX_DONE 0x80013058
-#pragma Aux_register(0x80013058, name=>"io_i2c_slv0_clr_rx_done")
-
-// User extension aux register io_i2c_slv0_clr_activity
-#define AR_IO_I2C_SLV0_CLR_ACTIVITY 0x8001305c
-#pragma Aux_register(0x8001305c, name=>"io_i2c_slv0_clr_activity")
-
-// User extension aux register io_i2c_slv0_clr_stop_det
-#define AR_IO_I2C_SLV0_CLR_STOP_DET 0x80013060
-#pragma Aux_register(0x80013060, name=>"io_i2c_slv0_clr_stop_det")
-
-// User extension aux register io_i2c_slv0_clr_start_det
-#define AR_IO_I2C_SLV0_CLR_START_DET 0x80013064
-#pragma Aux_register(0x80013064, name=>"io_i2c_slv0_clr_start_det")
-
-// User extension aux register io_i2c_slv0_enable
-#define AR_IO_I2C_SLV0_ENABLE 0x8001306c
-#pragma Aux_register(0x8001306c, name=>"io_i2c_slv0_enable")
-
-// User extension aux register io_i2c_slv0_status
-#define AR_IO_I2C_SLV0_STATUS 0x80013070
-#pragma Aux_register(0x80013070, name=>"io_i2c_slv0_status")
-
-// User extension aux register io_i2c_slv0_txflr
-#define AR_IO_I2C_SLV0_TXFLR 0x80013074
-#pragma Aux_register(0x80013074, name=>"io_i2c_slv0_txflr")
-
-// User extension aux register io_i2c_slv0_rxflr
-#define AR_IO_I2C_SLV0_RXFLR 0x80013078
-#pragma Aux_register(0x80013078, name=>"io_i2c_slv0_rxflr")
-
-// User extension aux register io_i2c_slv0_sda_hold
-#define AR_IO_I2C_SLV0_SDA_HOLD 0x8001307c
-#pragma Aux_register(0x8001307c, name=>"io_i2c_slv0_sda_hold")
-
-// User extension aux register io_i2c_slv0_tx_abrt_source
-#define AR_IO_I2C_SLV0_TX_ABRT_SOURCE 0x80013080
-#pragma Aux_register(0x80013080, name=>"io_i2c_slv0_tx_abrt_source")
-
-// User extension aux register io_i2c_slv0_sda_setup
-#define AR_IO_I2C_SLV0_SDA_SETUP 0x80013094
-#pragma Aux_register(0x80013094, name=>"io_i2c_slv0_sda_setup")
-
-// User extension aux register io_i2c_slv0_enable_status
-#define AR_IO_I2C_SLV0_ENABLE_STATUS 0x8001309c
-#pragma Aux_register(0x8001309c, name=>"io_i2c_slv0_enable_status")
-
-// User extension aux register io_i2c_slv0_fs_spklen
-#define AR_IO_I2C_SLV0_FS_SPKLEN 0x800130a0
-#pragma Aux_register(0x800130a0, name=>"io_i2c_slv0_fs_spklen")
-
-// User extension aux register io_i2c_slv0_clr_restart_det
-#define AR_IO_I2C_SLV0_CLR_RESTART_DET 0x800130a8
-#pragma Aux_register(0x800130a8, name=>"io_i2c_slv0_clr_restart_det")
-#define APEX_COM_ARC_HARDWARE_SCSS_IO_PWM0_PRESENT	1
-
-// User extension aux register io_pwm0_clken
-#define AR_IO_PWM0_CLKEN 0x8001d020
-#pragma Aux_register(0x8001d020, name=>"io_pwm0_clken")
-
-// User extension aux register io_pwm0_ctrl
-#define AR_IO_PWM0_CTRL 0x8001d000
-#pragma Aux_register(0x8001d000, name=>"io_pwm0_ctrl")
-
-// User extension aux register io_pwm0_chn_config
-#define AR_IO_PWM0_CHN_CONFIG 0x8001d001
-#pragma Aux_register(0x8001d001, name=>"io_pwm0_chn_config")
-
-// User extension aux register io_pwm0_trigger
-#define AR_IO_PWM0_TRIGGER 0x8001d002
-#pragma Aux_register(0x8001d002, name=>"io_pwm0_trigger")
-
-// User extension aux register io_pwm0_fault
-#define AR_IO_PWM0_FAULT 0x8001d003
-#pragma Aux_register(0x8001d003, name=>"io_pwm0_fault")
-
-// User extension aux register io_pwm0_events
-#define AR_IO_PWM0_EVENTS 0x8001d004
-#pragma Aux_register(0x8001d004, name=>"io_pwm0_events")
-
-// User extension aux register io_pwm0_intctrl
-#define AR_IO_PWM0_INTCTRL 0x8001d005
-#pragma Aux_register(0x8001d005, name=>"io_pwm0_intctrl")
-
-// User extension aux register io_pwm0_intstat
-#define AR_IO_PWM0_INTSTAT 0x8001d006
-#pragma Aux_register(0x8001d006, name=>"io_pwm0_intstat")
-
-// User extension aux register io_pwm0_intclr
-#define AR_IO_PWM0_INTCLR 0x8001d007
-#pragma Aux_register(0x8001d007, name=>"io_pwm0_intclr")
-
-// User extension aux register io_pwm0_threshold_01
-#define AR_IO_PWM0_THRESHOLD_01 0x8001d008
-#pragma Aux_register(0x8001d008, name=>"io_pwm0_threshold_01")
-
-// User extension aux register io_pwm0_threshold_23
-#define AR_IO_PWM0_THRESHOLD_23 0x8001d009
-#pragma Aux_register(0x8001d009, name=>"io_pwm0_threshold_23")
-
-// User extension aux register io_pwm0_threshold_45
-#define AR_IO_PWM0_THRESHOLD_45 0x8001d00a
-#pragma Aux_register(0x8001d00a, name=>"io_pwm0_threshold_45")
-
-// User extension aux register io_pwm0_threshold_67
-#define AR_IO_PWM0_THRESHOLD_67 0x8001d00b
-#pragma Aux_register(0x8001d00b, name=>"io_pwm0_threshold_67")
-
-// User extension aux register io_pwm0_deadzone_01
-#define AR_IO_PWM0_DEADZONE_01 0x8001d00c
-#pragma Aux_register(0x8001d00c, name=>"io_pwm0_deadzone_01")
-
-// User extension aux register io_pwm0_deadzone_23
-#define AR_IO_PWM0_DEADZONE_23 0x8001d00d
-#pragma Aux_register(0x8001d00d, name=>"io_pwm0_deadzone_23")
-
-// User extension aux register io_pwm0_deadzone_45
-#define AR_IO_PWM0_DEADZONE_45 0x8001d00e
-#pragma Aux_register(0x8001d00e, name=>"io_pwm0_deadzone_45")
-
-// User extension aux register io_pwm0_deadzone_67
-#define AR_IO_PWM0_DEADZONE_67 0x8001d00f
-#pragma Aux_register(0x8001d00f, name=>"io_pwm0_deadzone_67")
-
-// User extension aux register io_pwm0_timer_max
-#define AR_IO_PWM0_TIMER_MAX 0x8001d010
-#pragma Aux_register(0x8001d010, name=>"io_pwm0_timer_max")
-
-// User extension aux register io_pwm0_nperiods
-#define AR_IO_PWM0_NPERIODS 0x8001d011
-#pragma Aux_register(0x8001d011, name=>"io_pwm0_nperiods")
-
-// User extension aux register io_pwm0_clk_div
-#define AR_IO_PWM0_CLK_DIV 0x8001d012
-#pragma Aux_register(0x8001d012, name=>"io_pwm0_clk_div")
-#define APEX_COM_ARC_HARDWARE_SCSS_IO_PWM1_PRESENT	1
-
-// User extension aux register io_pwm1_clken
-#define AR_IO_PWM1_CLKEN 0x8001d120
-#pragma Aux_register(0x8001d120, name=>"io_pwm1_clken")
-
-// User extension aux register io_pwm1_ctrl
-#define AR_IO_PWM1_CTRL 0x8001d100
-#pragma Aux_register(0x8001d100, name=>"io_pwm1_ctrl")
-
-// User extension aux register io_pwm1_chn_config
-#define AR_IO_PWM1_CHN_CONFIG 0x8001d101
-#pragma Aux_register(0x8001d101, name=>"io_pwm1_chn_config")
-
-// User extension aux register io_pwm1_trigger
-#define AR_IO_PWM1_TRIGGER 0x8001d102
-#pragma Aux_register(0x8001d102, name=>"io_pwm1_trigger")
-
-// User extension aux register io_pwm1_fault
-#define AR_IO_PWM1_FAULT 0x8001d103
-#pragma Aux_register(0x8001d103, name=>"io_pwm1_fault")
-
-// User extension aux register io_pwm1_events
-#define AR_IO_PWM1_EVENTS 0x8001d104
-#pragma Aux_register(0x8001d104, name=>"io_pwm1_events")
-
-// User extension aux register io_pwm1_intctrl
-#define AR_IO_PWM1_INTCTRL 0x8001d105
-#pragma Aux_register(0x8001d105, name=>"io_pwm1_intctrl")
-
-// User extension aux register io_pwm1_intstat
-#define AR_IO_PWM1_INTSTAT 0x8001d106
-#pragma Aux_register(0x8001d106, name=>"io_pwm1_intstat")
-
-// User extension aux register io_pwm1_intclr
-#define AR_IO_PWM1_INTCLR 0x8001d107
-#pragma Aux_register(0x8001d107, name=>"io_pwm1_intclr")
-
-// User extension aux register io_pwm1_threshold_01
-#define AR_IO_PWM1_THRESHOLD_01 0x8001d108
-#pragma Aux_register(0x8001d108, name=>"io_pwm1_threshold_01")
-
-// User extension aux register io_pwm1_threshold_23
-#define AR_IO_PWM1_THRESHOLD_23 0x8001d109
-#pragma Aux_register(0x8001d109, name=>"io_pwm1_threshold_23")
-
-// User extension aux register io_pwm1_threshold_45
-#define AR_IO_PWM1_THRESHOLD_45 0x8001d10a
-#pragma Aux_register(0x8001d10a, name=>"io_pwm1_threshold_45")
-
-// User extension aux register io_pwm1_threshold_67
-#define AR_IO_PWM1_THRESHOLD_67 0x8001d10b
-#pragma Aux_register(0x8001d10b, name=>"io_pwm1_threshold_67")
-
-// User extension aux register io_pwm1_deadzone_01
-#define AR_IO_PWM1_DEADZONE_01 0x8001d10c
-#pragma Aux_register(0x8001d10c, name=>"io_pwm1_deadzone_01")
-
-// User extension aux register io_pwm1_deadzone_23
-#define AR_IO_PWM1_DEADZONE_23 0x8001d10d
-#pragma Aux_register(0x8001d10d, name=>"io_pwm1_deadzone_23")
-
-// User extension aux register io_pwm1_deadzone_45
-#define AR_IO_PWM1_DEADZONE_45 0x8001d10e
-#pragma Aux_register(0x8001d10e, name=>"io_pwm1_deadzone_45")
-
-// User extension aux register io_pwm1_deadzone_67
-#define AR_IO_PWM1_DEADZONE_67 0x8001d10f
-#pragma Aux_register(0x8001d10f, name=>"io_pwm1_deadzone_67")
-
-// User extension aux register io_pwm1_timer_max
-#define AR_IO_PWM1_TIMER_MAX 0x8001d110
-#pragma Aux_register(0x8001d110, name=>"io_pwm1_timer_max")
-
-// User extension aux register io_pwm1_nperiods
-#define AR_IO_PWM1_NPERIODS 0x8001d111
-#pragma Aux_register(0x8001d111, name=>"io_pwm1_nperiods")
-
-// User extension aux register io_pwm1_clk_div
-#define AR_IO_PWM1_CLK_DIV 0x8001d112
-#pragma Aux_register(0x8001d112, name=>"io_pwm1_clk_div")
-#define APEX_COM_ARC_HARDWARE_SCSS_IO_SPI_MST0_PRESENT	1
-
-// User extension aux register io_spi_mst0_ctrlr0
-#define AR_IO_SPI_MST0_CTRLR0 0x80010000
-#pragma Aux_register(0x80010000, name=>"io_spi_mst0_ctrlr0")
-
-// User extension aux register io_spi_mst0_ctrlr1
-#define AR_IO_SPI_MST0_CTRLR1 0x80010001
-#pragma Aux_register(0x80010001, name=>"io_spi_mst0_ctrlr1")
-
-// User extension aux register io_spi_mst0_spien
-#define AR_IO_SPI_MST0_SPIEN 0x80010002
-#pragma Aux_register(0x80010002, name=>"io_spi_mst0_spien")
-
-// User extension aux register io_spi_mst0_ser
-#define AR_IO_SPI_MST0_SER 0x80010004
-#pragma Aux_register(0x80010004, name=>"io_spi_mst0_ser")
-
-// User extension aux register io_spi_mst0_baudr
-#define AR_IO_SPI_MST0_BAUDR 0x80010005
-#pragma Aux_register(0x80010005, name=>"io_spi_mst0_baudr")
-
-// User extension aux register io_spi_mst0_txftlr
-#define AR_IO_SPI_MST0_TXFTLR 0x80010006
-#pragma Aux_register(0x80010006, name=>"io_spi_mst0_txftlr")
-
-// User extension aux register io_spi_mst0_rxftlr
-#define AR_IO_SPI_MST0_RXFTLR 0x80010007
-#pragma Aux_register(0x80010007, name=>"io_spi_mst0_rxftlr")
-
-// User extension aux register io_spi_mst0_txflr
-#define AR_IO_SPI_MST0_TXFLR 0x80010008
-#pragma Aux_register(0x80010008, name=>"io_spi_mst0_txflr")
-
-// User extension aux register io_spi_mst0_rxflr
-#define AR_IO_SPI_MST0_RXFLR 0x80010009
-#pragma Aux_register(0x80010009, name=>"io_spi_mst0_rxflr")
-
-// User extension aux register io_spi_mst0_sr
-#define AR_IO_SPI_MST0_SR 0x8001000a
-#pragma Aux_register(0x8001000a, name=>"io_spi_mst0_sr")
-
-// User extension aux register io_spi_mst0_imr
-#define AR_IO_SPI_MST0_IMR 0x8001000b
-#pragma Aux_register(0x8001000b, name=>"io_spi_mst0_imr")
-
-// User extension aux register io_spi_mst0_isr
-#define AR_IO_SPI_MST0_ISR 0x8001000c
-#pragma Aux_register(0x8001000c, name=>"io_spi_mst0_isr")
-
-// User extension aux register io_spi_mst0_risr
-#define AR_IO_SPI_MST0_RISR 0x8001000d
-#pragma Aux_register(0x8001000d, name=>"io_spi_mst0_risr")
-
-// User extension aux register io_spi_mst0_txoicr
-#define AR_IO_SPI_MST0_TXOICR 0x8001000e
-#pragma Aux_register(0x8001000e, name=>"io_spi_mst0_txoicr")
-
-// User extension aux register io_spi_mst0_rxoicr
-#define AR_IO_SPI_MST0_RXOICR 0x8001000f
-#pragma Aux_register(0x8001000f, name=>"io_spi_mst0_rxoicr")
-
-// User extension aux register io_spi_mst0_rxuicr
-#define AR_IO_SPI_MST0_RXUICR 0x80010010
-#pragma Aux_register(0x80010010, name=>"io_spi_mst0_rxuicr")
-
-// User extension aux register io_spi_mst0_icr
-#define AR_IO_SPI_MST0_ICR 0x80010012
-#pragma Aux_register(0x80010012, name=>"io_spi_mst0_icr")
-
-// User extension aux register io_spi_mst0_clken
-#define AR_IO_SPI_MST0_CLKEN 0x80010016
-#pragma Aux_register(0x80010016, name=>"io_spi_mst0_clken")
-
-// User extension aux register io_spi_mst0_dr
-#define AR_IO_SPI_MST0_DR 0x80010018
-#pragma Aux_register(0x80010018, name=>"io_spi_mst0_dr")
-
-// User extension aux register io_spi_mst0_rx_sample_dly
-#define AR_IO_SPI_MST0_RX_SAMPLE_DLY 0x8001003c
-#pragma Aux_register(0x8001003c, name=>"io_spi_mst0_rx_sample_dly")
-#define APEX_COM_ARC_HARDWARE_SCSS_IO_SPI_SLV0_PRESENT	1
-
-// User extension aux register io_spi_slv0_ctrlr0
-#define AR_IO_SPI_SLV0_CTRLR0 0x80011000
-#pragma Aux_register(0x80011000, name=>"io_spi_slv0_ctrlr0")
-
-// User extension aux register io_spi_slv0_spien
-#define AR_IO_SPI_SLV0_SPIEN 0x80011002
-#pragma Aux_register(0x80011002, name=>"io_spi_slv0_spien")
-
-// User extension aux register io_spi_slv0_txftlr
-#define AR_IO_SPI_SLV0_TXFTLR 0x80011006
-#pragma Aux_register(0x80011006, name=>"io_spi_slv0_txftlr")
-
-// User extension aux register io_spi_slv0_rxftlr
-#define AR_IO_SPI_SLV0_RXFTLR 0x80011007
-#pragma Aux_register(0x80011007, name=>"io_spi_slv0_rxftlr")
-
-// User extension aux register io_spi_slv0_txflr
-#define AR_IO_SPI_SLV0_TXFLR 0x80011008
-#pragma Aux_register(0x80011008, name=>"io_spi_slv0_txflr")
-
-// User extension aux register io_spi_slv0_rxflr
-#define AR_IO_SPI_SLV0_RXFLR 0x80011009
-#pragma Aux_register(0x80011009, name=>"io_spi_slv0_rxflr")
-
-// User extension aux register io_spi_slv0_sr
-#define AR_IO_SPI_SLV0_SR 0x8001100a
-#pragma Aux_register(0x8001100a, name=>"io_spi_slv0_sr")
-
-// User extension aux register io_spi_slv0_imr
-#define AR_IO_SPI_SLV0_IMR 0x8001100b
-#pragma Aux_register(0x8001100b, name=>"io_spi_slv0_imr")
-
-// User extension aux register io_spi_slv0_isr
-#define AR_IO_SPI_SLV0_ISR 0x8001100c
-#pragma Aux_register(0x8001100c, name=>"io_spi_slv0_isr")
-
-// User extension aux register io_spi_slv0_risr
-#define AR_IO_SPI_SLV0_RISR 0x8001100d
-#pragma Aux_register(0x8001100d, name=>"io_spi_slv0_risr")
-
-// User extension aux register io_spi_slv0_txoicr
-#define AR_IO_SPI_SLV0_TXOICR 0x8001100e
-#pragma Aux_register(0x8001100e, name=>"io_spi_slv0_txoicr")
-
-// User extension aux register io_spi_slv0_rxoicr
-#define AR_IO_SPI_SLV0_RXOICR 0x8001100f
-#pragma Aux_register(0x8001100f, name=>"io_spi_slv0_rxoicr")
-
-// User extension aux register io_spi_slv0_rxuicr
-#define AR_IO_SPI_SLV0_RXUICR 0x80011010
-#pragma Aux_register(0x80011010, name=>"io_spi_slv0_rxuicr")
-
-// User extension aux register io_spi_slv0_icr
-#define AR_IO_SPI_SLV0_ICR 0x80011012
-#pragma Aux_register(0x80011012, name=>"io_spi_slv0_icr")
-
-// User extension aux register io_spi_slv0_clken
-#define AR_IO_SPI_SLV0_CLKEN 0x80011016
-#pragma Aux_register(0x80011016, name=>"io_spi_slv0_clken")
-
-// User extension aux register io_spi_slv0_dr
-#define AR_IO_SPI_SLV0_DR 0x80011018
-#pragma Aux_register(0x80011018, name=>"io_spi_slv0_dr")
-#define APEX_COM_ARC_HARDWARE_SCSS_IO_UART0_PRESENT	1
-
-// User extension aux register io_uart0_clken
-#define AR_IO_UART0_CLKEN 0x800140c0
-#pragma Aux_register(0x800140c0, name=>"io_uart0_clken")
-
-// User extension aux register io_uart0_rbr_thr_dll
-#define AR_IO_UART0_RBR_THR_DLL 0x80014000
-#pragma Aux_register(0x80014000, name=>"io_uart0_rbr_thr_dll")
-
-// User extension aux register io_uart0_ier_dlh
-#define AR_IO_UART0_IER_DLH 0x80014004
-#pragma Aux_register(0x80014004, name=>"io_uart0_ier_dlh")
-
-// User extension aux register io_uart0_iir_fcr
-#define AR_IO_UART0_IIR_FCR 0x80014008
-#pragma Aux_register(0x80014008, name=>"io_uart0_iir_fcr")
-
-// User extension aux register io_uart0_lcr
-#define AR_IO_UART0_LCR 0x8001400c
-#pragma Aux_register(0x8001400c, name=>"io_uart0_lcr")
-
-// User extension aux register io_uart0_mcr
-#define AR_IO_UART0_MCR 0x80014010
-#pragma Aux_register(0x80014010, name=>"io_uart0_mcr")
-
-// User extension aux register io_uart0_lsr
-#define AR_IO_UART0_LSR 0x80014014
-#pragma Aux_register(0x80014014, name=>"io_uart0_lsr")
-
-// User extension aux register io_uart0_msr
-#define AR_IO_UART0_MSR 0x80014018
-#pragma Aux_register(0x80014018, name=>"io_uart0_msr")
-
-// User extension aux register io_uart0_usr
-#define AR_IO_UART0_USR 0x8001407c
-#pragma Aux_register(0x8001407c, name=>"io_uart0_usr")
-#define APEX_COM_ARC_HARDWARE_SCSS_IO_UART1_PRESENT	1
-
-// User extension aux register io_uart1_clken
-#define AR_IO_UART1_CLKEN 0x800141c0
-#pragma Aux_register(0x800141c0, name=>"io_uart1_clken")
-
-// User extension aux register io_uart1_rbr_thr_dll
-#define AR_IO_UART1_RBR_THR_DLL 0x80014100
-#pragma Aux_register(0x80014100, name=>"io_uart1_rbr_thr_dll")
-
-// User extension aux register io_uart1_ier_dlh
-#define AR_IO_UART1_IER_DLH 0x80014104
-#pragma Aux_register(0x80014104, name=>"io_uart1_ier_dlh")
-
-// User extension aux register io_uart1_iir_fcr
-#define AR_IO_UART1_IIR_FCR 0x80014108
-#pragma Aux_register(0x80014108, name=>"io_uart1_iir_fcr")
-
-// User extension aux register io_uart1_lcr
-#define AR_IO_UART1_LCR 0x8001410c
-#pragma Aux_register(0x8001410c, name=>"io_uart1_lcr")
-
-// User extension aux register io_uart1_mcr
-#define AR_IO_UART1_MCR 0x80014110
-#pragma Aux_register(0x80014110, name=>"io_uart1_mcr")
-
-// User extension aux register io_uart1_lsr
-#define AR_IO_UART1_LSR 0x80014114
-#pragma Aux_register(0x80014114, name=>"io_uart1_lsr")
-
-// User extension aux register io_uart1_msr
-#define AR_IO_UART1_MSR 0x80014118
-#pragma Aux_register(0x80014118, name=>"io_uart1_msr")
-
-// User extension aux register io_uart1_usr
-#define AR_IO_UART1_USR 0x8001417c
-#pragma Aux_register(0x8001417c, name=>"io_uart1_usr")
-#define APEX_COM_ARC_HARDWARE_SCSS_IO_UART2_PRESENT	1
-
-// User extension aux register io_uart2_clken
-#define AR_IO_UART2_CLKEN 0x800142c0
-#pragma Aux_register(0x800142c0, name=>"io_uart2_clken")
-
-// User extension aux register io_uart2_rbr_thr_dll
-#define AR_IO_UART2_RBR_THR_DLL 0x80014200
-#pragma Aux_register(0x80014200, name=>"io_uart2_rbr_thr_dll")
-
-// User extension aux register io_uart2_ier_dlh
-#define AR_IO_UART2_IER_DLH 0x80014204
-#pragma Aux_register(0x80014204, name=>"io_uart2_ier_dlh")
-
-// User extension aux register io_uart2_iir_fcr
-#define AR_IO_UART2_IIR_FCR 0x80014208
-#pragma Aux_register(0x80014208, name=>"io_uart2_iir_fcr")
-
-// User extension aux register io_uart2_lcr
-#define AR_IO_UART2_LCR 0x8001420c
-#pragma Aux_register(0x8001420c, name=>"io_uart2_lcr")
-
-// User extension aux register io_uart2_mcr
-#define AR_IO_UART2_MCR 0x80014210
-#pragma Aux_register(0x80014210, name=>"io_uart2_mcr")
-
-// User extension aux register io_uart2_lsr
-#define AR_IO_UART2_LSR 0x80014214
-#pragma Aux_register(0x80014214, name=>"io_uart2_lsr")
-
-// User extension aux register io_uart2_msr
-#define AR_IO_UART2_MSR 0x80014218
-#pragma Aux_register(0x80014218, name=>"io_uart2_msr")
-
-// User extension aux register io_uart2_usr
-#define AR_IO_UART2_USR 0x8001427c
-#pragma Aux_register(0x8001427c, name=>"io_uart2_usr")
-#define APEX_COM_ARC_HARDWARE_SCSS_IO_UART3_PRESENT	1
-
-// User extension aux register io_uart3_clken
-#define AR_IO_UART3_CLKEN 0x800143c0
-#pragma Aux_register(0x800143c0, name=>"io_uart3_clken")
-
-// User extension aux register io_uart3_rbr_thr_dll
-#define AR_IO_UART3_RBR_THR_DLL 0x80014300
-#pragma Aux_register(0x80014300, name=>"io_uart3_rbr_thr_dll")
-
-// User extension aux register io_uart3_ier_dlh
-#define AR_IO_UART3_IER_DLH 0x80014304
-#pragma Aux_register(0x80014304, name=>"io_uart3_ier_dlh")
-
-// User extension aux register io_uart3_iir_fcr
-#define AR_IO_UART3_IIR_FCR 0x80014308
-#pragma Aux_register(0x80014308, name=>"io_uart3_iir_fcr")
-
-// User extension aux register io_uart3_lcr
-#define AR_IO_UART3_LCR 0x8001430c
-#pragma Aux_register(0x8001430c, name=>"io_uart3_lcr")
-
-// User extension aux register io_uart3_mcr
-#define AR_IO_UART3_MCR 0x80014310
-#pragma Aux_register(0x80014310, name=>"io_uart3_mcr")
-
-// User extension aux register io_uart3_lsr
-#define AR_IO_UART3_LSR 0x80014314
-#pragma Aux_register(0x80014314, name=>"io_uart3_lsr")
-
-// User extension aux register io_uart3_msr
-#define AR_IO_UART3_MSR 0x80014318
-#pragma Aux_register(0x80014318, name=>"io_uart3_msr")
-
-// User extension aux register io_uart3_usr
-#define AR_IO_UART3_USR 0x8001437c
-#pragma Aux_register(0x8001437c, name=>"io_uart3_usr")
-#define APEX_COM_ARC_HARDWARE_SCSS_SUBSYS_BCR_PRESENT	1
-
-// User extension aux register SUBSYS_BUILD
-#define AR_SUBSYS_BUILD 0xf0
-#pragma Aux_register(0xf0, name=>"SUBSYS_BUILD")
-
-// User extension aux register SUBSYS_DSP_0_BUILD
-#define AR_SUBSYS_DSP_0_BUILD 0xa00
-#pragma Aux_register(0xa00, name=>"SUBSYS_DSP_0_BUILD")
-
-// User extension aux register SUBSYS_DSP_0_CONFIG
-#define AR_SUBSYS_DSP_0_CONFIG 0xa02
-#pragma Aux_register(0xa02, name=>"SUBSYS_DSP_0_CONFIG")
-
-// User extension aux register SUBSYS_IO_0_BUILD
-#define AR_SUBSYS_IO_0_BUILD 0xa04
-#pragma Aux_register(0xa04, name=>"SUBSYS_IO_0_BUILD")
-
-// User extension aux register SUBSYS_IO_1_BUILD
-#define AR_SUBSYS_IO_1_BUILD 0xa05
-#pragma Aux_register(0xa05, name=>"SUBSYS_IO_1_BUILD")
-
-// User extension aux register SUBSYS_IO_2_BUILD
-#define AR_SUBSYS_IO_2_BUILD 0xa06
-#pragma Aux_register(0xa06, name=>"SUBSYS_IO_2_BUILD")
-
-// User extension aux register SUBSYS_UAUX_OFFSET
-#define AR_SUBSYS_UAUX_OFFSET 0xa1e
-#pragma Aux_register(0xa1e, name=>"SUBSYS_UAUX_OFFSET")
-
-// User extension aux register SUBSYS_APEX_OFFSET
-#define AR_SUBSYS_APEX_OFFSET 0xa1f
-#pragma Aux_register(0xa1f, name=>"SUBSYS_APEX_OFFSET")
-#define APEX_COM_ARC_HARDWARE_SCSS_IO_SPI_MST1_PRESENT	1
-
-// User extension aux register io_spi_mst1_ctrlr0
-#define AR_IO_SPI_MST1_CTRLR0 0x80010100
-#pragma Aux_register(0x80010100, name=>"io_spi_mst1_ctrlr0")
-
-// User extension aux register io_spi_mst1_ctrlr1
-#define AR_IO_SPI_MST1_CTRLR1 0x80010101
-#pragma Aux_register(0x80010101, name=>"io_spi_mst1_ctrlr1")
-
-// User extension aux register io_spi_mst1_spien
-#define AR_IO_SPI_MST1_SPIEN 0x80010102
-#pragma Aux_register(0x80010102, name=>"io_spi_mst1_spien")
-
-// User extension aux register io_spi_mst1_ser
-#define AR_IO_SPI_MST1_SER 0x80010104
-#pragma Aux_register(0x80010104, name=>"io_spi_mst1_ser")
-
-// User extension aux register io_spi_mst1_baudr
-#define AR_IO_SPI_MST1_BAUDR 0x80010105
-#pragma Aux_register(0x80010105, name=>"io_spi_mst1_baudr")
-
-// User extension aux register io_spi_mst1_txftlr
-#define AR_IO_SPI_MST1_TXFTLR 0x80010106
-#pragma Aux_register(0x80010106, name=>"io_spi_mst1_txftlr")
-
-// User extension aux register io_spi_mst1_rxftlr
-#define AR_IO_SPI_MST1_RXFTLR 0x80010107
-#pragma Aux_register(0x80010107, name=>"io_spi_mst1_rxftlr")
-
-// User extension aux register io_spi_mst1_txflr
-#define AR_IO_SPI_MST1_TXFLR 0x80010108
-#pragma Aux_register(0x80010108, name=>"io_spi_mst1_txflr")
-
-// User extension aux register io_spi_mst1_rxflr
-#define AR_IO_SPI_MST1_RXFLR 0x80010109
-#pragma Aux_register(0x80010109, name=>"io_spi_mst1_rxflr")
-
-// User extension aux register io_spi_mst1_sr
-#define AR_IO_SPI_MST1_SR 0x8001010a
-#pragma Aux_register(0x8001010a, name=>"io_spi_mst1_sr")
-
-// User extension aux register io_spi_mst1_imr
-#define AR_IO_SPI_MST1_IMR 0x8001010b
-#pragma Aux_register(0x8001010b, name=>"io_spi_mst1_imr")
-
-// User extension aux register io_spi_mst1_isr
-#define AR_IO_SPI_MST1_ISR 0x8001010c
-#pragma Aux_register(0x8001010c, name=>"io_spi_mst1_isr")
-
-// User extension aux register io_spi_mst1_risr
-#define AR_IO_SPI_MST1_RISR 0x8001010d
-#pragma Aux_register(0x8001010d, name=>"io_spi_mst1_risr")
-
-// User extension aux register io_spi_mst1_txoicr
-#define AR_IO_SPI_MST1_TXOICR 0x8001010e
-#pragma Aux_register(0x8001010e, name=>"io_spi_mst1_txoicr")
-
-// User extension aux register io_spi_mst1_rxoicr
-#define AR_IO_SPI_MST1_RXOICR 0x8001010f
-#pragma Aux_register(0x8001010f, name=>"io_spi_mst1_rxoicr")
-
-// User extension aux register io_spi_mst1_rxuicr
-#define AR_IO_SPI_MST1_RXUICR 0x80010110
-#pragma Aux_register(0x80010110, name=>"io_spi_mst1_rxuicr")
-
-// User extension aux register io_spi_mst1_icr
-#define AR_IO_SPI_MST1_ICR 0x80010112
-#pragma Aux_register(0x80010112, name=>"io_spi_mst1_icr")
-
-// User extension aux register io_spi_mst1_clken
-#define AR_IO_SPI_MST1_CLKEN 0x80010116
-#pragma Aux_register(0x80010116, name=>"io_spi_mst1_clken")
-
-// User extension aux register io_spi_mst1_dr
-#define AR_IO_SPI_MST1_DR 0x80010118
-#pragma Aux_register(0x80010118, name=>"io_spi_mst1_dr")
-
-// User extension aux register io_spi_mst1_rx_sample_dly
-#define AR_IO_SPI_MST1_RX_SAMPLE_DLY 0x8001013c
-#pragma Aux_register(0x8001013c, name=>"io_spi_mst1_rx_sample_dly")
-#define APEX_COM_ARC_HARDWARE_SCSS_IO_SPI_MST2_PRESENT	1
-
-// User extension aux register io_spi_mst2_ctrlr0
-#define AR_IO_SPI_MST2_CTRLR0 0x80010200
-#pragma Aux_register(0x80010200, name=>"io_spi_mst2_ctrlr0")
-
-// User extension aux register io_spi_mst2_ctrlr1
-#define AR_IO_SPI_MST2_CTRLR1 0x80010201
-#pragma Aux_register(0x80010201, name=>"io_spi_mst2_ctrlr1")
-
-// User extension aux register io_spi_mst2_spien
-#define AR_IO_SPI_MST2_SPIEN 0x80010202
-#pragma Aux_register(0x80010202, name=>"io_spi_mst2_spien")
-
-// User extension aux register io_spi_mst2_ser
-#define AR_IO_SPI_MST2_SER 0x80010204
-#pragma Aux_register(0x80010204, name=>"io_spi_mst2_ser")
-
-// User extension aux register io_spi_mst2_baudr
-#define AR_IO_SPI_MST2_BAUDR 0x80010205
-#pragma Aux_register(0x80010205, name=>"io_spi_mst2_baudr")
-
-// User extension aux register io_spi_mst2_txftlr
-#define AR_IO_SPI_MST2_TXFTLR 0x80010206
-#pragma Aux_register(0x80010206, name=>"io_spi_mst2_txftlr")
-
-// User extension aux register io_spi_mst2_rxftlr
-#define AR_IO_SPI_MST2_RXFTLR 0x80010207
-#pragma Aux_register(0x80010207, name=>"io_spi_mst2_rxftlr")
-
-// User extension aux register io_spi_mst2_txflr
-#define AR_IO_SPI_MST2_TXFLR 0x80010208
-#pragma Aux_register(0x80010208, name=>"io_spi_mst2_txflr")
-
-// User extension aux register io_spi_mst2_rxflr
-#define AR_IO_SPI_MST2_RXFLR 0x80010209
-#pragma Aux_register(0x80010209, name=>"io_spi_mst2_rxflr")
-
-// User extension aux register io_spi_mst2_sr
-#define AR_IO_SPI_MST2_SR 0x8001020a
-#pragma Aux_register(0x8001020a, name=>"io_spi_mst2_sr")
-
-// User extension aux register io_spi_mst2_imr
-#define AR_IO_SPI_MST2_IMR 0x8001020b
-#pragma Aux_register(0x8001020b, name=>"io_spi_mst2_imr")
-
-// User extension aux register io_spi_mst2_isr
-#define AR_IO_SPI_MST2_ISR 0x8001020c
-#pragma Aux_register(0x8001020c, name=>"io_spi_mst2_isr")
-
-// User extension aux register io_spi_mst2_risr
-#define AR_IO_SPI_MST2_RISR 0x8001020d
-#pragma Aux_register(0x8001020d, name=>"io_spi_mst2_risr")
-
-// User extension aux register io_spi_mst2_txoicr
-#define AR_IO_SPI_MST2_TXOICR 0x8001020e
-#pragma Aux_register(0x8001020e, name=>"io_spi_mst2_txoicr")
-
-// User extension aux register io_spi_mst2_rxoicr
-#define AR_IO_SPI_MST2_RXOICR 0x8001020f
-#pragma Aux_register(0x8001020f, name=>"io_spi_mst2_rxoicr")
-
-// User extension aux register io_spi_mst2_rxuicr
-#define AR_IO_SPI_MST2_RXUICR 0x80010210
-#pragma Aux_register(0x80010210, name=>"io_spi_mst2_rxuicr")
-
-// User extension aux register io_spi_mst2_icr
-#define AR_IO_SPI_MST2_ICR 0x80010212
-#pragma Aux_register(0x80010212, name=>"io_spi_mst2_icr")
-
-// User extension aux register io_spi_mst2_clken
-#define AR_IO_SPI_MST2_CLKEN 0x80010216
-#pragma Aux_register(0x80010216, name=>"io_spi_mst2_clken")
-
-// User extension aux register io_spi_mst2_dr
-#define AR_IO_SPI_MST2_DR 0x80010218
-#pragma Aux_register(0x80010218, name=>"io_spi_mst2_dr")
-
-// User extension aux register io_spi_mst2_rx_sample_dly
-#define AR_IO_SPI_MST2_RX_SAMPLE_DLY 0x8001023c
-#pragma Aux_register(0x8001023c, name=>"io_spi_mst2_rx_sample_dly")
-#define APEX_COM_ARC_HARDWARE_FLOATING_POINT_UNIT_FPU_PRESENT	1
-
-// User extension aux register fpu_build
-#define AR_FPU_BUILD 0xc8
-#pragma Aux_register(0xc8, name=>"fpu_build")
-
-// User extension aux register fpu_ctrl
-#define AR_FPU_CTRL 0x300
-#pragma Aux_register(0x300, name=>"fpu_ctrl")
-
-// User extension aux register fpu_status
-#define AR_FPU_STATUS 0x301
-#pragma Aux_register(0x301, name=>"fpu_status")
-
-// User extension instruction fsmadd
-extern int fsmadd(int,int);
-#pragma intrinsic(fsmadd,opcode=>6,sub_opcode=>5, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fsmsub
-extern int fsmsub(int,int);
-#pragma intrinsic(fsmsub,opcode=>6,sub_opcode=>6, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fsmul
-extern int fsmul(int,int);
-#pragma intrinsic(fsmul,opcode=>6,sub_opcode=>0, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fsadd
-extern int fsadd(int,int);
-#pragma intrinsic(fsadd,opcode=>6,sub_opcode=>1, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fssub
-extern int fssub(int,int);
-#pragma intrinsic(fssub,opcode=>6,sub_opcode=>2, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fcvt32
-extern int fcvt32(int,int);
-#pragma intrinsic(fcvt32,opcode=>6,sub_opcode=>8, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fsdiv
-extern int fsdiv(int,int);
-#pragma intrinsic(fsdiv,opcode=>6,sub_opcode=>7, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fscmp
-extern int fscmp(int,int);
-#pragma intrinsic(fscmp,opcode=>6,sub_opcode=>3, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fscmp
-extern int fscmp_f(int,int);
-#pragma intrinsic(fscmp_f,opcode=>6,sub_opcode=>3, set_flags => 1, flags => "zncv", effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fscmpf
-extern int fscmpf(int,int);
-#pragma intrinsic(fscmpf,opcode=>6,sub_opcode=>4, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fscmpf
-extern int fscmpf_f(int,int);
-#pragma intrinsic(fscmpf_f,opcode=>6,sub_opcode=>4, set_flags => 1, flags => "zncv", effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-
-// User extension instruction fssqrt
-extern int fssqrt(int);
-#pragma intrinsic(fssqrt,opcode=>6,sub_opcode=>0, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written")
-#define APEX_COM_ARC_HARDWARE_FLOATING_POINT_UNIT_FPU_DP_ASSIST_PRESENT	1
-
-// User extension aux register aux_dpfp1l
-#define AR_AUX_DPFP1L 0x302
-#pragma Aux_register(0x302, name=>"aux_dpfp1l")
-
-// User extension aux register aux_dpfp1h
-#define AR_AUX_DPFP1H 0x303
-#pragma Aux_register(0x303, name=>"aux_dpfp1h")
-
-// User extension aux register aux_dpfp2l
-#define AR_AUX_DPFP2L 0x304
-#pragma Aux_register(0x304, name=>"aux_dpfp2l")
-
-// User extension aux register aux_dpfp2h
-#define AR_AUX_DPFP2H 0x305
-#pragma Aux_register(0x305, name=>"aux_dpfp2h")
-
-// User extension instruction dmulh11
-extern int dmulh11(int,int);
-#pragma intrinsic(dmulh11,opcode=>6,sub_opcode=>48,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dmulh11
-extern int dmulh11_f(int,int);
-#pragma intrinsic(dmulh11_f,opcode=>6,sub_opcode=>48, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dmulh12
-extern int dmulh12(int,int);
-#pragma intrinsic(dmulh12,opcode=>6,sub_opcode=>49,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dmulh12
-extern int dmulh12_f(int,int);
-#pragma intrinsic(dmulh12_f,opcode=>6,sub_opcode=>49, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dmulh21
-extern int dmulh21(int,int);
-#pragma intrinsic(dmulh21,opcode=>6,sub_opcode=>50,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dmulh21
-extern int dmulh21_f(int,int);
-#pragma intrinsic(dmulh21_f,opcode=>6,sub_opcode=>50, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dmulh22
-extern int dmulh22(int,int);
-#pragma intrinsic(dmulh22,opcode=>6,sub_opcode=>51,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dmulh22
-extern int dmulh22_f(int,int);
-#pragma intrinsic(dmulh22_f,opcode=>6,sub_opcode=>51, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction daddh11
-extern int daddh11(int,int);
-#pragma intrinsic(daddh11,opcode=>6,sub_opcode=>52,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction daddh11
-extern int daddh11_f(int,int);
-#pragma intrinsic(daddh11_f,opcode=>6,sub_opcode=>52, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction daddh12
-extern int daddh12(int,int);
-#pragma intrinsic(daddh12,opcode=>6,sub_opcode=>53,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction daddh12
-extern int daddh12_f(int,int);
-#pragma intrinsic(daddh12_f,opcode=>6,sub_opcode=>53, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction daddh21
-extern int daddh21(int,int);
-#pragma intrinsic(daddh21,opcode=>6,sub_opcode=>54,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction daddh21
-extern int daddh21_f(int,int);
-#pragma intrinsic(daddh21_f,opcode=>6,sub_opcode=>54, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction daddh22
-extern int daddh22(int,int);
-#pragma intrinsic(daddh22,opcode=>6,sub_opcode=>55,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction daddh22
-extern int daddh22_f(int,int);
-#pragma intrinsic(daddh22_f,opcode=>6,sub_opcode=>55, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dsubh11
-extern int dsubh11(int,int);
-#pragma intrinsic(dsubh11,opcode=>6,sub_opcode=>56,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dsubh11
-extern int dsubh11_f(int,int);
-#pragma intrinsic(dsubh11_f,opcode=>6,sub_opcode=>56, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dsubh12
-extern int dsubh12(int,int);
-#pragma intrinsic(dsubh12,opcode=>6,sub_opcode=>57,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dsubh12
-extern int dsubh12_f(int,int);
-#pragma intrinsic(dsubh12_f,opcode=>6,sub_opcode=>57, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dsubh21
-extern int dsubh21(int,int);
-#pragma intrinsic(dsubh21,opcode=>6,sub_opcode=>58,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dsubh21
-extern int dsubh21_f(int,int);
-#pragma intrinsic(dsubh21_f,opcode=>6,sub_opcode=>58, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dsubh22
-extern int dsubh22(int,int);
-#pragma intrinsic(dsubh22,opcode=>6,sub_opcode=>59,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dsubh22
-extern int dsubh22_f(int,int);
-#pragma intrinsic(dsubh22_f,opcode=>6,sub_opcode=>59, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dexcl1
-extern int dexcl1(int,int);
-#pragma intrinsic(dexcl1,opcode=>6,sub_opcode=>60, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-// User extension instruction dexcl2
-extern int dexcl2(int,int);
-#pragma intrinsic(dexcl2,opcode=>6,sub_opcode=>61, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written")
-
-
-#endif
-
-
diff --git a/board/emsdp/rev1/configs/em6_scss/core_hardware.h b/board/emsdp/rev1/configs/em6_scss/core_hardware.h
deleted file mode 100644
index 287716cb2..000000000
--- a/board/emsdp/rev1/configs/em6_scss/core_hardware.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/* ------------------------------------------
- * Copyright (c) 2018, Synopsys, Inc. All rights reserved.
-
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
-
- * 1) Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
-
- * 2) Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
-
- * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
- * be used to endorse or promote products derived from this software without
- * specific prior written permission.
-
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
---------------------------------------------- */
-#ifndef _CORE_HARDWARE_H_
-#define _CORE_HARDWARE_H_
-
-#define EMSDP_SPI0_INTR					(84)
-#define EMSDP_SPI1_INTR					(85)
-#define EMSDP_GPIO_INTR0				(86)
-#define EMSDP_GPIO_INTR1				(87)
-#define EMSDP_GPIO_INTR2				(88)
-#define EMSDP_GPIO_INTR3				(89)
-#define EMSDP_TIMER0_INTR0				(90)
-#define EMSDP_TIMER0_INTR1				(91)
-#define EMSDP_TIMER0_INTR2				(92)
-#define EMSDP_TIMER0_INTR3				(93)
-#define EMSDP_TIMER0_INTR4				(94)
-#define EMSDP_TIMER0_INTR5				(95)
-#define EMSDP_TIMER0_INTR6				(96)
-#define EMSDP_TIMER0_INTR7				(97)
-#define EMSDP_TIMER1_INTR0				(98)
-#define EMSDP_TIMER1_INTR1				(99)
-#define EMSDP_TIMER1_INTR2				(100)
-#define EMSDP_TIMER1_INTR3				(101)
-#define EMSDP_TIMER1_INTR4				(102)
-#define EMSDP_TIMER1_INTR5				(103)
-#define EMSDP_TIMER1_INTR6				(104)
-#define EMSDP_TIMER1_INTR7				(105)
-#define EMSDP_UART_INTR					(106)
-#define EMSDP_WDT_INTR					(107)
-#define EMSDP_DBG_UART_INTR				(108)
-#define EMSDP_SDIO_INTR					(109)
-#define EMSDP_REDPINE_SPI_INTR			(110)
-#define EMSDP_REDPINE_HOST_WAKEUP		(111)
-#define EMSDP_NIST_TRNG_INTR			(112)
-
-//EMSDP Peripheral Subsystem DMA assignments
-#define UART_DMA_TX					(10)
-#define UART_DMA_RX					(11)
-#define REDPINE_SPI_DMA_TX			(12)
-#define REDPINE_SPI_DMA_RX			(13)
-#define FLASH_SPI_DMA_TX			(14)
-#define FLASH_SPI_DMA_RX			(15)
-
-#endif /* _CORE_HARDWARE_H_ */
\ No newline at end of file
diff --git a/board/emsdp/rev1/configs/em6_scss/dsp_config.h b/board/emsdp/rev1/configs/em6_scss/dsp_config.h
deleted file mode 100644
index 3f7f2a312..000000000
--- a/board/emsdp/rev1/configs/em6_scss/dsp_config.h
+++ /dev/null
@@ -1,27 +0,0 @@
-
-/* **** DO NOT EDIT - this file is generated by ARChitect2 ****
- *
- * Description: Header file declaring the compiler extensions for eia components 
- */
-
-#ifndef _dsp_config_H_
-#define _dsp_config_H_
-
-
-#define DSP_MAC_PRESENT
-#define DSP_MAC_IO_FW (15)
-#define DSP_MAC_ACC_SIZE (min)
-#define DSP_MAC_Z_WRAP (floor)
-#define DSP_ABS_PRESENT
-#define DSP_ADD_PRESENT
-#define DSP_MULT_PRESENT
-#define DSP_MULV_PRESENT
-#define DSP_NEGATE_PRESENT
-#define DSP_SHIFT_PRESENT
-#define DSP_SINCOS_PRESENT
-#define DSP_SQRT_PRESENT
-#define DSP_SUB_PRESENT
-
-#endif
-
-
diff --git a/board/emsdp/rev1/configs/em6_scss/io_config.h b/board/emsdp/rev1/configs/em6_scss/io_config.h
deleted file mode 100644
index 068656a2e..000000000
--- a/board/emsdp/rev1/configs/em6_scss/io_config.h
+++ /dev/null
@@ -1,116 +0,0 @@
-
-/* **** DO NOT EDIT - this file is generated by ARChitect2 ****
- *
- * Description: Header file declaring the compiler extensions for eia components 
- */
-
-#ifndef _io_config_H_
-#define _io_config_H_
-
-
-#define DMAC_INT_BASE (20)
-#define DMAC_ERR_BASE (DMAC_INT_BASE + DMAC_CHAN_CNT)
-#define DMAC_CHAN_CNT (16)
-#define DMAC_MEM_CHAN_CNT (16)
-#define DMAC_AUX_CHAN_CNT (0)
-#define IO_I2C_SLV0_PRESENT
-#define IO_I2C_SLV0_FS (2)
-#define IO_I2C_SLV0_DMA_TX (2)
-#define IO_I2C_SLV0_DMA_RX (3)
-#define IO_I2C_SLV0_INT_ERR (50)
-#define IO_I2C_SLV0_INT_RX_AVAIL (51)
-#define IO_I2C_SLV0_INT_TX_REQ (52)
-#define IO_I2C_SLV0_INT_RD_REQ (53)
-#define IO_I2C_SLV0_INT_STOP_DET (54)
-#define IO_I2C_SLV0_INT_RESTART_DET (55)
-#define IO_SPI_MST0_PRESENT
-#define IO_SPI_MST0_FS (16)
-#define IO_SPI_MST0_MAX_XFER_SIZE (16)
-#define IO_SPI_MST0_DMA_TX (4)
-#define IO_SPI_MST0_DMA_RX (5)
-#define IO_SPI_MST0_INT_ERR (64)
-#define IO_SPI_MST0_INT_RX_AVAIL (65)
-#define IO_SPI_MST0_INT_TX_REQ (66)
-#define IO_SPI_MST0_INT_IDLE (67)
-#define IO_SPI_SLV0_PRESENT
-#define IO_SPI_SLV0_FS (2)
-#define IO_SPI_SLV0_MAX_XFER_SIZE (16)
-#define IO_SPI_SLV0_DMA_TX (8)
-#define IO_SPI_SLV0_DMA_RX (9)
-#define IO_SPI_SLV0_INT_ERR (76)
-#define IO_SPI_SLV0_INT_RX_AVAIL (77)
-#define IO_SPI_SLV0_INT_TX_REQ (78)
-#define IO_SPI_SLV0_INT_IDLE (79)
-#define IO_I2C_MST0_PRESENT
-#define IO_I2C_MST0_FS (16)
-#define IO_I2C_MST0_DMA_TX (0)
-#define IO_I2C_MST0_DMA_RX (1)
-#define IO_I2C_MST0_INT_ERR (38)
-#define IO_I2C_MST0_INT_RX_AVAIL (39)
-#define IO_I2C_MST0_INT_TX_REQ (40)
-#define IO_I2C_MST0_INT_STOP_DET (41)
-#define IO_GPIO0_PRESENT
-#define IO_GPIO0_INT_INTR_FLAG (17)
-#define IO_GPIO0_DEBOUNCE (1)
-#define IO_UART0_PRESENT
-#define IO_UART0_FS (0)
-#define IO_UART0_INTR (80)
-#define IO_PWM0_PRESENT
-#define IO_PWM0_COUNTER_WIDTH (16)
-#define IO_PWM0_INT_NEW_NPERIODS (56)
-#define IO_PWM0_INT_UPD_MISSED (57)
-#define IO_PWM0_INT_TRG (58)
-#define IO_PWM0_INT_FAULT (59)
-#define IO_SPI_MST1_PRESENT
-#define IO_SPI_MST1_FS (16)
-#define IO_SPI_MST1_MAX_XFER_SIZE (16)
-#define IO_SPI_MST1_DMA_TX (6)
-#define IO_SPI_MST1_DMA_RX (7)
-#define IO_SPI_MST1_INT_ERR (68)
-#define IO_SPI_MST1_INT_RX_AVAIL (69)
-#define IO_SPI_MST1_INT_TX_REQ (70)
-#define IO_SPI_MST1_INT_IDLE (71)
-#define IO_I2C_MST1_PRESENT
-#define IO_I2C_MST1_FS (16)
-#define IO_I2C_MST1_INT_ERR (42)
-#define IO_I2C_MST1_INT_RX_AVAIL (43)
-#define IO_I2C_MST1_INT_TX_REQ (44)
-#define IO_I2C_MST1_INT_STOP_DET (45)
-#define IO_GPIO1_PRESENT
-#define IO_GPIO1_INT_INTR_FLAG (19)
-#define IO_GPIO1_DEBOUNCE (1)
-#define IO_UART1_PRESENT
-#define IO_UART1_FS (0)
-#define IO_UART1_INTR (81)
-#define IO_PWM1_PRESENT
-#define IO_PWM1_COUNTER_WIDTH (16)
-#define IO_PWM1_INT_NEW_NPERIODS (60)
-#define IO_PWM1_INT_UPD_MISSED (61)
-#define IO_PWM1_INT_TRG (62)
-#define IO_PWM1_INT_FAULT (63)
-#define IO_SPI_MST2_PRESENT
-#define IO_SPI_MST2_FS (16)
-#define IO_SPI_MST2_MAX_XFER_SIZE (16)
-#define IO_SPI_MST2_INT_ERR (72)
-#define IO_SPI_MST2_INT_RX_AVAIL (73)
-#define IO_SPI_MST2_INT_TX_REQ (74)
-#define IO_SPI_MST2_INT_IDLE (75)
-#define IO_I2C_MST2_PRESENT
-#define IO_I2C_MST2_FS (16)
-#define IO_I2C_MST2_INT_ERR (46)
-#define IO_I2C_MST2_INT_RX_AVAIL (47)
-#define IO_I2C_MST2_INT_TX_REQ (48)
-#define IO_I2C_MST2_INT_STOP_DET (49)
-#define IO_GPIO2_PRESENT
-#define IO_GPIO2_INT_INTR_FLAG (37)
-#define IO_GPIO2_DEBOUNCE (1)
-#define IO_UART2_PRESENT
-#define IO_UART2_FS (0)
-#define IO_UART2_INTR (82)
-#define IO_UART3_PRESENT
-#define IO_UART3_FS (0)
-#define IO_UART3_INTR (83)
-
-#endif
-
-
diff --git a/board/emsdp/rev1/configs/em6_scss/tcf/em6_scss.tcf b/board/emsdp/rev1/configs/em6_scss/tcf/em6_scss.tcf
deleted file mode 100644
index 39aa15cab..000000000
--- a/board/emsdp/rev1/configs/em6_scss/tcf/em6_scss.tcf
+++ /dev/null
@@ -1,4775 +0,0 @@
-
-
-  
-  
-    
-  
-  
-    
-  
-  
-    
-  
-  
-    
-  
-  
-    
-  
-  
-    
-  
-  
-    
-# 
-# option  16/L32/U32  Instructions
-# ------  ----------  ---------------------
-#       
-# none	  -/-/-     None
-# wlh1	  1/1/1     MPYW/U, MPY/U, MPYH/U
-# wlh2	  2/2/2     MPYW/U, MPY/U, MPYH/U
-# wlh3	  2/3/3     MPYW/U, MPY/U, MPYH/U
-# wlh4	  2/4/5     MPYW/U, MPY/U, MPYH/U
-# wlh5	  5/9/9     MPYW/U, MPY/U, MPYH/U
-#
-# --mpy_option wlh2 - -# code_protection --- The ARC EM architecture divides the memory into 16 regions, which can be protected individually. This feature adds a 16-bit input to the processor core, one bit per region. When the protect bit is set, the processor disables any load or store to the corresponding region. An attempt to access a protected region raises an EV_ProtV exception. --code_protection false - -# stack_checking --- Stack checking is a mechanism for checking stack accesses and raising an exception when a stack overflow or underflow is detected. --stack_checking true - -# unaligned_option --- This enables unaligned loads and stores. --unaligned_option false - -# intvbase_preset --- This sets the interrupt vector base configuration register, VECBASE_AC_BUILD. The vector base address is aligned to a 1KB boundary, so the required address value should be divided by 1K (i.e. do not include the lower 10 bits). On reset, this register is loaded into the interrupt vector base address register, INT_VECTOR_BASE. --intvbase_preset 0x0 - -# intvbase_preset_s --- This sets the secure interrupt vector base configuration register, VECBASE_AC_BUILD. The vector base address is aligned to a 1KB boundary, so the required address value should be divided by 1K (i.e. do not include the lower 10 bits). On reset, this register is loaded into the interrupt vector base address register, INT_VECTOR_BASE_S.This is effective only when 2+2 mode is enabled. --intvbase_preset_s 0x0 - -# intvbase_ext --- Set this option to drive the upper 22 bits of the interrupt base vector externally, into signal intvbase_in. --intvbase_ext false - -# nmi_option --- add Non-maskable external exception support --nmi_option false - -# rgf_impl --- This defines whether the register file is implemented using flip-flops, or with a hard macro. --rgf_impl flip_flops - -# rgf_num_regs --- This defines the size (in 32b register) of the processor register file. --rgf_num_regs 32 - -# rgf_wr_ports --- This defines the number of write ports on the register file. --rgf_wr_ports 1 - -# rgf_num_banks --- Dual register banks are useful if Fast IRQ has been configured, but may be selected even if not. --rgf_num_banks 1 - -# rgf_banked_regs --- This selects the number of registers that are replicated in the second register-file bank. --rgf_banked_regs 32 - -# turbo_boost --- This enables the Turbo Boost synthesis option. By enabling this option, the achievable clock frequency is increased, but at the cost of an additional cycle latency on branch instructions. --turbo_boost true - -# infer_alu_adder --- infer: datapath is described as behavioral code: A + B -# instantiate: datapath is instantiated as a detailed multi-stage code of a carry-lookahead adder. It is generally preferable to use the infer option and add directives for your target synthesizer. --infer_alu_adder infer - -# infer_mpy_wtree --- infer: datapath is described as behavioral code: A * B (applies to only wlh3, wlh4 and wlh5 designs) -# instantiate: datapath is instantiated as a detailed multi-stage code of a Wallace Tree multiplier It is generally preferable to use the infer option and add directives for your target synthesizer. --infer_mpy_wtree instantiate - -# scantest_ram_bypass_mux --- This mux is used to make logic trapped between flops and memory (aka shadow logic) to be covered by scantest without requiring advanced sequential ATPG on the memory to be applied. Will add delay to functional access time --scantest_ram_bypass_mux false - -# logic_bist --- This option will OR LBIST_EN with test_mode --logic_bist false - -# power_domains --- Adds three separate power domains to the core, and propagates power-gate control signals to the top level of the core. Also generates UPF constraints and commands in the low-power scripts --power_domains false - -# dvfs --- Adds logic to the core to allow dynamic controlling of voltage and frequency and propagates the associated control signals to the top level of core --dvfs false - -# voltage_domains --- Creates a voltage domain split between RAM and std cell parts to support Ultra Low Voltage on cells and generates UPF constraints --voltage_domains false - -# mem_bus_option --- The core supports two bus protocols for accessing external memory: AHB & AHB-Lite. AHB-Lite-single means instruction fetch and data access share a single AHB-Lite port. AHB-Lite-dual means separate AHB-Lite port for each initiator if present. --mem_bus_option AHB - -# mem_bus_reg_interface --- Specifies whether the memory bus interface is registered. --mem_bus_reg_interface true - -# dmi_burst_option --- This will enable high-throughput burst support on the DMI slave interfaces. By enabling this option, the peak DMI read throughput goes from 1 word per 3 cycles to N words per N+2 cycles, in which N is the AHB burst lengthDMI write throughput goes from 1 word per 3 cycles to 1 word per cycle. --dmi_burst_option true - -# has_dmp_peripheral --- This option enables the redirection of load/store accesses to one segment (1/16) of the addressable space to a dedicated peripheral bus. This offers high system integration and reduces overall system cost. --has_dmp_peripheral true - -# per0_base --- This option specifies the memory region assignment for this peripheral aperture --per0_base 15 - -# per0_limit --- This option specifies the end of this peripheral aperture --per0_limit 0 - -# per_bus_option --- The core supports one bus protocol for accessing the peripheral space, when enabled: AHB-Lite. --per_bus_option AHB-Lite - -# per_bus_reg_interface --- Specifies whether the peripheral bus interface is registered. --per_bus_reg_interface true - -# clock_gating --- This enables the insertion of architectural clock gate elements in the design. By enabling this option, the clocks to various parts of the design will be disabled when the logic they drive is not in use to save power. --clock_gating false - -# back_compat --- This enables the addition of rst_a input in the clkgate module to support backward compatibility with the older EM and Subsystem releases. --back_compat true - -# byte_parity --- If parity protection on the CCMs is configured, this option is used to enable parity protection on a per-byte basis. Otherwise, parity will be per word basis --byte_parity false - -# prot_pipelined --- Check the box if CCM memories are configured for ECC, and you want single-bit errors to be corrected, written back to memory, and re-fetched. When unchecked, single bit errors are corrected when read from memory, but the offending memory location itself is not corrected with a writeback, no influence on Cache protection --prot_pipelined true - -# cct_test_ena --- When ECC is configured, this option enables single bit error injection in CCT RAM models to demonstrate ECC protection on the RAMs. When enabled, the RAM models can only be used in HDL CCT simulation (no xCAM support) and are not intended for use in SoC level integration. --cct_test_ena false - -# err_prot_ehce --- Enabled enhanced ECC architecture for CCM. Instruction fetch with single bit error is not replayed; ecc cac modules are shared to reduce area and timing opt. --err_prot_ehce false - - -######## Actionpoints --- com.arc.hardware.Actionpoints.1_0 ######## - -# Create Actionpoints --create com.arc.hardware.Actionpoints.1_0 System.CPUisle.ARCv2EM.Actionpoints - -# num_actionpoints --- This is the number of trigger events available. --num_actionpoints 8 - -# aps_feature --- Selects Actionpoint feature set --aps_feature min - - -######## DCCM --- com.arc.hardware.DCCM.1_0 ######## - -# Create DCCM --create com.arc.hardware.DCCM.1_0 System.CPUisle.ARCv2EM.DCCM - -# dccm_size --- This defines the size of the Data Closely Coupled Memory (DCCM) in bytes --dccm_size 131072 - -# dccm_base --- Sets the initial memory region assignment for DCCM --dccm_base 8 - -# dccm_interleave --- Split DCCM into even/odd memory banks. --dccm_interleave false - -# dccm_prot --- Specifies the type of protection built for the DCCM. --dccm_prot None - -# dccm_prot_level --- Specifies the level protection. --dccm_prot_level Data_Only - -# dccm_prot_exceptions --- When the core is configured with ECC or Parity, cause exception generation hardware to be created for uncorrectable errors detected on the DCCM --dccm_prot_exceptions true - -# dccm_sec_lvl --- Specifies the level of secure DCCM. --dccm_sec_lvl Non_Secure - -# dccm_dmi --- This enables external access through a DMI (direct memory interface) port. --dccm_dmi true - - -######## DMA Controller --- com.arc.hardware.DMA_Controller.1_0 ######## - -# Create DMA Controller --create com.arc.hardware.DMA_Controller.1_0 "System.CPUisle.ARCv2EM.DMA Controller" - -# dmac_channels --- This options specifies the number of DMA channels implemented in the DMA controller --dmac_channels 16 - -# dmac_fifo_depth --- This option specifies the DMA transfer FIFO depth in 32b words. --dmac_fifo_depth 2 - -# dmac_int_config --- None: the DMA controller cannot raise an interrupt -# Single-External: single done and single error interrupt signal for all DMA channels, and the interrupt signals are routed to a port at the top of the EM logical hierarchy -# Multiple-External: each DMA channel can be configured to raise separate (per-channel) done and error interrupts, and the interrupt signals are routed to ports at the top of the EM logical hierarchy -# Single-Internal: single done and single error interrupt signals for all DMA channels, and the interrupt signals are internal to the EM core -# Multiple-Internal: each DMA channel can be configured to raise separate (per-channel) done and error interrupts, and the interrupt signals are internal to the EM core --dmac_int_config Multiple-Internal - -# dmac_separate_error_interrupts --- This specifies whether there is a separate error interrupt per DMA channel, or just one. --dmac_separate_error_interrupts true - -# dmac_registers --- This option defines the number of DMA channels with their registers located in auxiliary space. --dmac_registers 0 - -# dmac_mem_if --- This option specifies whether the DMA controller system memory interface is integrated into the existing EM system memory interfaces or has its own interface. --dmac_mem_if integrated - -# dmac_per_if --- Internal vs DW peripheral interface. Specify (in hex) which channels have the DW interface, where bit 0 corresponds to DMA channel 0, bit 1 for DMA channel 1, etc. -# Example: 4 channel DMA controller where -dmac_per_if is set to 0x9 = DMA Channels 0 and 3 configured with the DW req interface, DMA Channels 1 and 2 configured with the internal req interface. --dmac_per_if 0xffff - - -######## Data Cache --- com.arc.hardware.Data_Cache.1_0 ######## - -# Create Data Cache --create com.arc.hardware.Data_Cache.1_0 "System.CPUisle.ARCv2EM.Data Cache" - -# dc_size --- This defines the total size of the Data Cache in bytes. --dc_size 16384 - -# dc_ways --- This defines the number of cache ways. --dc_ways 2 - -# dc_bsize --- This defines the cache line length in bytes. --dc_bsize 32 - -# dc_feature_level --- Feature Level, indicates locking and debug feature level 00 = Basic cache, with no locking or debug features 01 = Lock and flush features supported 10 = Lock, flush and advanced debug features supported 11 = Reserved --dc_feature_level 2 - -# dc_uncached_region --- Enable an uncached region defined by aux reg --dc_uncached_region false - -# dc_prot --- Specifies the type of protection built for DCACHE. --dc_prot None - -# dc_prot_level --- Specifies the level of protection. --dc_prot_level Data_Only - -# dc_prot_exceptions --- Builds exception generation hardware for uncorrectable (fatal) errors detected on DCACHE. --dc_prot_exceptions true - - -######## Debug Interface --- com.arc.hardware.Debug_Interface.1_0 ######## - -# Create Debug Interface --create com.arc.hardware.Debug_Interface.1_0 "System.CPUisle.ARCv2EM.Debug Interface" - -# dbg_en_option --- Adds an enable pin to the existing debug interface --dbg_en_option false - -# secure_debug --- This enables secure debug feature --secure_debug false - -# scdbg_aux_unlk --- An internal demo module will be included when enable --scdbg_aux_unlk false - -# dbg_apb_option --- Adds an additional APB debug port alongside the BVCI one --dbg_apb_option false - - -######## Floating-point unit --- com.arc.hardware.Floating_point_unit.1_0 ######## - -# Create Floating-point unit --create com.arc.hardware.Floating_point_unit.1_0 "System.CPUisle.ARCv2EM.Floating-point unit" - -# fpu_dp_assist --- This enables double-precision acceleration instructions. --fpu_dp_assist true - -# fpu_fma_option --- This enables the fused multiply-add & multiply-subtract instructions. --fpu_fma_option true - -# fpu_mas_cycles --- Make mul/add/sub multicycle to achieve a higher clock speed. --fpu_mas_cycles 2 - -# fpu_pipe_impl --- FPU pipelined implementation --fpu_pipe_impl false - -# fpu_div_option --- This enables divide & square-root acceleration --fpu_div_option true - -# fpu_div_cycles --- Controls div/sqrt implementation. --fpu_div_cycles 17 - - -######## ICCM0 --- com.arc.hardware.ICCM0.1_0 ######## - -# Create ICCM0 --create com.arc.hardware.ICCM0.1_0 System.CPUisle.ARCv2EM.ICCM0 - -# iccm0_size --- This defines the size of ICCM0 in bytes.This ICCM has 0 wait states. --iccm0_size 131072 - -# iccm0_base --- Sets the initial memory region assignment for ICCM0 --iccm0_base 6 - -# iccm0_wide --- Creates ICCM0 as 64b memory to reduce accesses. --iccm0_wide false - -# iccm0_prot --- Specifies the type of protection built for ICCM0. --iccm0_prot None - -# iccm0_prot_level --- Specifies the level of protection. --iccm0_prot_level Data_Only - -# iccm0_prot_exceptions --- When the core is configured with ECC or Parity, cause exception generation hardware to be created for uncorrectable errors detected on the ICCM0 --iccm0_prot_exceptions true - -# iccm0_sec_lvl --- Specifies the level of secure ICCM0. --iccm0_sec_lvl Non_Secure - -# iccm0_dmi --- This enables external access through a DMI (direct memory interface) port. --iccm0_dmi true - - -######## Instruction Cache --- com.arc.hardware.Instruction_Cache.1_0 ######## - -# Create Instruction Cache --create com.arc.hardware.Instruction_Cache.1_0 "System.CPUisle.ARCv2EM.Instruction Cache" - -# ic_size --- This defines the total size of the instruction cache in bytes. --ic_size 16384 - -# ic_ways --- This defines the number of cache ways --ic_ways 2 - -# ic_bsize --- This defines the cache line length in bytes. --ic_bsize 64 - -# ic_disable_on_reset --- The instruction cache may be enabled immediately after reset, depending on this option. If this option is enabled, the last cache operation is set to failed, and the direct cache-RAM access is enabled. Furthermore, the instruction cache is invalidated all cache lines are invalidated and unlocked, and the tag RAM is cleared. --ic_disable_on_reset false - -# ic_feature_level --- This defines the feature level of the cache. --ic_feature_level 1 - -# ic_pwr_opt_level --- This selects power-optimization options in the micro-architecture of the instruction cache. --ic_pwr_opt_level 0 - -# ic_prot --- Specifies the type of protection built for ICACHE. --ic_prot None - -# ic_prot_level --- Specifies the level of protection. --ic_prot_level Data_Only - -# ic_prot_exceptions --- Builds exception generation hardware for uncorrectable (fatal) errors detected on ICACHE. --ic_prot_exceptions true - - -######## Interrupt Controller --- com.arc.hardware.Interrupt_Controller.1_0 ######## - -# Create Interrupt Controller --create com.arc.hardware.Interrupt_Controller.1_0 "System.CPUisle.ARCv2EM.Interrupt Controller" - -# number_of_interrupts --- This is the total number of interrupts available to the core. Some interrupts are allocated statically to a specific interrupt line (for example, timer interrupts). For more information on Interrupt and register-file options, see DesignWare ARCv2 ISA Programmers Reference Manual. --number_of_interrupts 120 - -# number_of_levels --- Priority levels in the interrupt controller. --number_of_levels 4 - -# external_interrupts --- This is the total number of interrupt pins available for external system components. This parameter must be less than the total number of interrupts. --external_interrupts 80 - -# firq_option --- This enables the fast-interrupts option, (priority level 0 interrupts), which uses an alternate register bank (if configured) instead of saving the context to memory. --firq_option false - - -######## JTAG Interface --- com.arc.hardware.JTAG_Interface.1_0 ######## - -# Create JTAG Interface --create com.arc.hardware.JTAG_Interface.1_0 "System.CPUisle.ARCv2EM.JTAG Interface" - -######## Real-time Counter --- com.arc.hardware.Real_time_Counter.1_0 ######## - -# Create Real-time Counter --create com.arc.hardware.Real_time_Counter.1_0 "System.CPUisle.ARCv2EM.Real-time Counter" - -######## Real-time trace producer --- com.arc.hardware.Real_time_trace_producer.1_0 ######## - -# Create Real-time trace producer --create com.arc.hardware.Real_time_trace_producer.1_0 "System.CPUisle.ARCv2EM.Real-time trace producer" - -# rtt_feature_level --- 'small' means that program trace only is available. `medium' adds data trace. `full' adds core and aux register trace. --rtt_feature_level small - - -######## SmaRT --- com.arc.hardware.SmaRT.1_0 ######## - -# Create SmaRT --create com.arc.hardware.SmaRT.1_0 System.CPUisle.ARCv2EM.SmaRT - -# smart_stack_entries --- This specifies the number of entries in the trace buffer. --smart_stack_entries 8 - -# smart_implementation --- Flip-flop = FF-based design. Memory = memory-based design (provides better density for larger trace buffers). --smart_implementation flip-flop - - -######## Timer 0 --- com.arc.hardware.Timer_0.1_0 ######## - -# Create Timer 0 --create com.arc.hardware.Timer_0.1_0 "System.CPUisle.ARCv2EM.Timer 0" - -# timer_0_int_level --- This sets the interrupt level (and implicitly the priority: level 0 is highest) of timer 0. --timer_0_int_level 1 - - -######## dsp_abs --- com.arc.hardware.scss.dsp_abs.1_0 ######## - -# Create dsp_abs --create com.arc.hardware.scss.dsp_abs.1_0 System.CPUisle.ARCv2EM.dsp_abs - -# dsp_abs --- Command line option for EIA extension component 'dsp_abs'. --dsp_abs true - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## dsp_acm --- com.arc.hardware.scss.dsp_acm.1_0 ######## - -# Create dsp_acm --create com.arc.hardware.scss.dsp_acm.1_0 System.CPUisle.ARCv2EM.dsp_acm - -# io_fw --- Input and output fractional width -# - Q0.31 -# - Q0.15 -# - Q0.7 --dsp_acm_io_fw 31 - -# acc_size --- Accumulator size: -# - Min=Q0.(io_fw), -# - Max=Q(int(2*((64 - io_fw)/(2 + io_fw)-1))).(int(io_fw*(64 - io_fw)/(2 + io_fw))) -# -# Note that for io_fw=31, the acc_size is always q0.31 --dsp_acm_acc_size min - -# z_wrap --- Output wrapping method --dsp_acm_z_wrap floor - -# dsp_acm --- Command line option for EIA extension component 'dsp_acm'. --dsp_acm true - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## dsp_add --- com.arc.hardware.scss.dsp_add.1_0 ######## - -# Create dsp_add --create com.arc.hardware.scss.dsp_add.1_0 System.CPUisle.ARCv2EM.dsp_add - -# dsp_add --- Command line option for EIA extension component 'dsp_add'. --dsp_add true - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## dsp_mac --- com.arc.hardware.scss.dsp_mac.1_0 ######## - -# Create dsp_mac --create com.arc.hardware.scss.dsp_mac.1_0 System.CPUisle.ARCv2EM.dsp_mac - -# dsp_mac --- Command line option for EIA extension component 'dsp_mac'. --dsp_mac true - -# io_fw --- Input and output fractional width -# - Q0.31 -# - Q0.15 -# - Q0.7 --dsp_mac_io_fw 15 - -# acc_size --- Accumulator size: -# - Min=Q1.(2*io_fw), -# - Max=Q(63-(2*io_fw)).(2*io_fw) --dsp_mac_acc_size min - -# z_wrap --- Output wrapping method --dsp_mac_z_wrap floor - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## dsp_mult --- com.arc.hardware.scss.dsp_mult.1_0 ######## - -# Create dsp_mult --create com.arc.hardware.scss.dsp_mult.1_0 System.CPUisle.ARCv2EM.dsp_mult - -# dsp_mult --- Command line option for EIA extension component 'dsp_mult'. --dsp_mult true - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## dsp_mulv --- com.arc.hardware.scss.dsp_mulv.1_0 ######## - -# Create dsp_mulv --create com.arc.hardware.scss.dsp_mulv.1_0 System.CPUisle.ARCv2EM.dsp_mulv - -# dsp_mulv --- Command line option for APEX extension component 'dsp_mulv'. --dsp_mulv true - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## dsp_negate --- com.arc.hardware.scss.dsp_negate.1_0 ######## - -# Create dsp_negate --create com.arc.hardware.scss.dsp_negate.1_0 System.CPUisle.ARCv2EM.dsp_negate - -# dsp_negate --- Command line option for EIA extension component 'dsp_negate'. --dsp_negate true - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## dsp_shift --- com.arc.hardware.scss.dsp_shift.1_0 ######## - -# Create dsp_shift --create com.arc.hardware.scss.dsp_shift.1_0 System.CPUisle.ARCv2EM.dsp_shift - -# dsp_shift --- Command line option for EIA extension component 'dsp_shift'. --dsp_shift true - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## dsp_sincos --- com.arc.hardware.scss.dsp_sincos.1_0 ######## - -# Create dsp_sincos --create com.arc.hardware.scss.dsp_sincos.1_0 System.CPUisle.ARCv2EM.dsp_sincos - -# dsp_sincos --- Command line option for APEX extension component 'dsp_sincos'. --dsp_sincos true - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## dsp_sqrt --- com.arc.hardware.scss.dsp_sqrt.1_0 ######## - -# Create dsp_sqrt --create com.arc.hardware.scss.dsp_sqrt.1_0 System.CPUisle.ARCv2EM.dsp_sqrt - -# dsp_sqrt --- Command line option for APEX extension component 'dsp_sqrt'. --dsp_sqrt true - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## dsp_sub --- com.arc.hardware.scss.dsp_sub.1_0 ######## - -# Create dsp_sub --create com.arc.hardware.scss.dsp_sub.1_0 System.CPUisle.ARCv2EM.dsp_sub - -# dsp_sub --- Command line option for EIA extension component 'dsp_sub'. --dsp_sub true - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_gpio0 --- com.arc.hardware.scss.io_gpio0.1_0 ######## - -# Create io_gpio0 --create com.arc.hardware.scss.io_gpio0.1_0 System.CPUisle.ARCv2EM.io_gpio0 - -# io_gpio0 --- Command line option for EIA extension component 'io_gpio0'. --io_gpio0 true - -# io_gpio0_debounce --- Selects the inclusion of Debounce logic --io_gpio0_debounce 1 - -# io_gpio0_readback_sync --- Selects the inclusion of metastability registers on the read back path when reading the external 'ext_porta' signal --io_gpio0_readback_sync 1 - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_gpio1 --- com.arc.hardware.scss.io_gpio1.1_0 ######## - -# Create io_gpio1 --create com.arc.hardware.scss.io_gpio1.1_0 System.CPUisle.ARCv2EM.io_gpio1 - -# io_gpio1 --- Command line option for EIA extension component 'io_gpio1'. --io_gpio1 true - -# io_gpio1_debounce --- Selects the inclusion of Debounce logic --io_gpio1_debounce 1 - -# io_gpio1_readback_sync --- Selects the inclusion of metastability registers on the read back path when reading the external 'ext_porta' signal --io_gpio1_readback_sync 1 - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_gpio2 --- com.arc.hardware.scss.io_gpio2.1_0 ######## - -# Create io_gpio2 --create com.arc.hardware.scss.io_gpio2.1_0 System.CPUisle.ARCv2EM.io_gpio2 - -# io_gpio2 --- Command line option for EIA extension component 'io_gpio2'. --io_gpio2 true - -# io_gpio2_debounce --- Selects the inclusion of Debounce logic --io_gpio2_debounce 1 - -# io_gpio2_readback_sync --- Selects the inclusion of metastability registers on the read back path when reading the external 'ext_porta' signal --io_gpio2_readback_sync 1 - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_i2c_mst0 --- com.arc.hardware.scss.io_i2c_mst0.1_0 ######## - -# Create io_i2c_mst0 --create com.arc.hardware.scss.io_i2c_mst0.1_0 System.CPUisle.ARCv2EM.io_i2c_mst0 - -# io_i2c_mst0 --- Command line option for APEX extension component 'io_i2c_mst0'. --io_i2c_mst0 true - -# io_i2c_mst0_fs --- RX/TX FIFO size --io_i2c_mst0_fs 16 - -# io_i2c_mst0_dma_support --- Specifies whether the DMA handshake interface is included --io_i2c_mst0_dma_support Memory-Based - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_i2c_mst1 --- com.arc.hardware.scss.io_i2c_mst1.1_0 ######## - -# Create io_i2c_mst1 --create com.arc.hardware.scss.io_i2c_mst1.1_0 System.CPUisle.ARCv2EM.io_i2c_mst1 - -# io_i2c_mst1 --- Command line option for APEX extension component 'io_i2c_mst1'. --io_i2c_mst1 true - -# io_i2c_mst1_fs --- RX/TX FIFO size --io_i2c_mst1_fs 16 - -# io_i2c_mst1_dma_support --- Specifies whether the DMA handshake interface is included --io_i2c_mst1_dma_support None - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_i2c_mst2 --- com.arc.hardware.scss.io_i2c_mst2.1_0 ######## - -# Create io_i2c_mst2 --create com.arc.hardware.scss.io_i2c_mst2.1_0 System.CPUisle.ARCv2EM.io_i2c_mst2 - -# io_i2c_mst2 --- Command line option for APEX extension component 'io_i2c_mst2'. --io_i2c_mst2 true - -# io_i2c_mst2_fs --- RX/TX FIFO size --io_i2c_mst2_fs 16 - -# io_i2c_mst2_dma_support --- Specifies whether the DMA handshake interface is included --io_i2c_mst2_dma_support None - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_i2c_slv0 --- com.arc.hardware.scss.io_i2c_slv0.1_0 ######## - -# Create io_i2c_slv0 --create com.arc.hardware.scss.io_i2c_slv0.1_0 System.CPUisle.ARCv2EM.io_i2c_slv0 - -# io_i2c_slv0 --- Command line option for APEX extension component 'io_i2c_slv0'. --io_i2c_slv0 true - -# io_i2c_slv0_fs --- RX/TX FIFO size --io_i2c_slv0_fs 2 - -# io_i2c_slv0_dma_support --- Specifies whether the DMA handshake interface is included --io_i2c_slv0_dma_support Memory-Based - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_pwm0 --- com.arc.hardware.scss.io_pwm0.1_0 ######## - -# Create io_pwm0 --create com.arc.hardware.scss.io_pwm0.1_0 System.CPUisle.ARCv2EM.io_pwm0 - -# io_pwm0 --- Command line option for APEX extension component 'io_pwm0'. --io_pwm0 true - -# io_pwm0_counter_width --- PWM Timer(counter) width --io_pwm0_cw 16 - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_pwm1 --- com.arc.hardware.scss.io_pwm1.1_0 ######## - -# Create io_pwm1 --create com.arc.hardware.scss.io_pwm1.1_0 System.CPUisle.ARCv2EM.io_pwm1 - -# io_pwm1 --- Command line option for APEX extension component 'io_pwm1'. --io_pwm1 true - -# io_pwm1_counter_width --- PWM Timer(counter) width --io_pwm1_cw 16 - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_spi_mst0 --- com.arc.hardware.scss.io_spi_mst0.1_0 ######## - -# Create io_spi_mst0 --create com.arc.hardware.scss.io_spi_mst0.1_0 System.CPUisle.ARCv2EM.io_spi_mst0 - -# io_spi_mst0 --- Command line option for APEX extension component 'io_spi_mst0'. --io_spi_mst0 true - -# io_spi_mst0_fz --- RX/TX FIFO depth --io_spi_mst0_fs 16 - -# io_spi_mst0_max_xfer_size --- This defines the maximum number of bits per word at the serial data port, which determines the FIFO width. --io_spi_mst0_max_xfer_size 16 - -# io_spi_mst0_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_spi_mst0_dma_support Memory-Based - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_spi_slv0 --- com.arc.hardware.scss.io_spi_slv0.1_0 ######## - -# Create io_spi_slv0 --create com.arc.hardware.scss.io_spi_slv0.1_0 System.CPUisle.ARCv2EM.io_spi_slv0 - -# io_spi_slv0 --- Command line option for APEX extension component 'io_spi_slv0'. --io_spi_slv0 true - -# io_spi_slv0_fz --- RX/TX FIFO depth --io_spi_slv0_fs 2 - -# io_spi_slv0_max_xfer_size --- This defines the maximum number of bits per word at the serial data port, which determines the FIFO width. --io_spi_slv0_max_xfer_size 16 - -# io_spi_slv0_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_spi_slv0_dma_support Memory-Based - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_uart0 --- com.arc.hardware.scss.io_uart0.1_0 ######## - -# Create io_uart0 --create com.arc.hardware.scss.io_uart0.1_0 System.CPUisle.ARCv2EM.io_uart0 - -# io_uart0 --- Command line option for EIA extension component 'io_uart0'. --io_uart0 true - -# io_uart0_fifo_mode --- Set the UART FIFO mode --io_uart0_fifo_mode 0 - -# io_uart0_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_uart0_dma_support None - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_uart1 --- com.arc.hardware.scss.io_uart1.1_0 ######## - -# Create io_uart1 --create com.arc.hardware.scss.io_uart1.1_0 System.CPUisle.ARCv2EM.io_uart1 - -# io_uart1 --- Command line option for EIA extension component 'io_uart1'. --io_uart1 true - -# io_uart1_fifo_mode --- Set the UART FIFO mode --io_uart1_fifo_mode 0 - -# io_uart1_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_uart1_dma_support None - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_uart2 --- com.arc.hardware.scss.io_uart2.1_0 ######## - -# Create io_uart2 --create com.arc.hardware.scss.io_uart2.1_0 System.CPUisle.ARCv2EM.io_uart2 - -# io_uart2 --- Command line option for EIA extension component 'io_uart2'. --io_uart2 true - -# io_uart2_fifo_mode --- Set the UART FIFO mode --io_uart2_fifo_mode 0 - -# io_uart2_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_uart2_dma_support None - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_uart3 --- com.arc.hardware.scss.io_uart3.1_0 ######## - -# Create io_uart3 --create com.arc.hardware.scss.io_uart3.1_0 System.CPUisle.ARCv2EM.io_uart3 - -# io_uart3 --- Command line option for EIA extension component 'io_uart3'. --io_uart3 true - -# io_uart3_fifo_mode --- Set the UART FIFO mode --io_uart3_fifo_mode 0 - -# io_uart3_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_uart3_dma_support None - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## subsys_bcr --- com.arc.hardware.scss.subsys_bcr.1_0 ######## - -# Create subsys_bcr --create com.arc.hardware.scss.subsys_bcr.1_0 System.CPUisle.ARCv2EM.subsys_bcr - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_spi_mst1 --- com.arc.hardware.scss.io_spi_mst1.1_0 ######## - -# Create io_spi_mst1 --create com.arc.hardware.scss.io_spi_mst1.1_0 System.CPUisle.ARCv2EM.io_spi_mst1 - -# io_spi_mst1 --- Command line option for APEX extension component 'io_spi_mst1'. --io_spi_mst1 true - -# io_spi_mst1_fz --- RX/TX FIFO depth --io_spi_mst1_fs 16 - -# io_spi_mst1_max_xfer_size --- This defines the maximum number of bits per word at the serial data port, which determines the FIFO width. --io_spi_mst1_max_xfer_size 16 - -# io_spi_mst1_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_spi_mst1_dma_support Memory-Based - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_spi_mst2 --- com.arc.hardware.scss.io_spi_mst2.1_0 ######## - -# Create io_spi_mst2 --create com.arc.hardware.scss.io_spi_mst2.1_0 System.CPUisle.ARCv2EM.io_spi_mst2 - -# io_spi_mst2 --- Command line option for APEX extension component 'io_spi_mst2'. --io_spi_mst2 true - -# io_spi_mst2_fz --- RX/TX FIFO depth --io_spi_mst2_fs 16 - -# io_spi_mst2_max_xfer_size --- This defines the maximum number of bits per word at the serial data port, which determines the FIFO width. --io_spi_mst2_max_xfer_size 16 - -# io_spi_mst2_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_spi_mst2_dma_support None - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## Watchdog Timer --- com.arc.hardware.Watchdog_Timer.1_0 ######## - -# Create Watchdog Timer --create com.arc.hardware.Watchdog_Timer.1_0 "System.CPUisle.ARCv2EM.Watchdog Timer" - -# watchdog_size --- Specifies the bit width of timer's internal counter. --watchdog_size 32 - -# watchdog_clk --- Specifies whether the timer should be driven from a separate clock. --watchdog_clk false - - -######## ClkCtrl --- com.arc.hardware.ARCv2MSS.ClkCtrl.1_0 ######## - -# Create ClkCtrl --create com.arc.hardware.ARCv2MSS.ClkCtrl.1_0 System.ClkCtrl - -######## DSP Software --- com.arc.software.scss.sw_dsp.1_0 ######## - -# Create DSP Software --create com.arc.software.scss.sw_dsp.1_0 "System.DSP Software" - -# sw_dsp --- Command line option for Software element 'DSP Software' --sw_dsp true - - -######## EMDK_BOARD --- com.arc.hardware.ARCv2MSS.EMDK_BOARD.1_0 ######## - -# Create EMDK_BOARD --create com.arc.hardware.ARCv2MSS.EMDK_BOARD.1_0 System.EMDK_BOARD - -# emdk_sys_freq --- Select the core frequency. --emdk_sys_freq 50 - - -######## IO Software --- com.arc.software.scss.sw_io.1_0 ######## - -# Create IO Software --create com.arc.software.scss.sw_io.1_0 "System.IO Software" - -# sw_io --- Command line option for Software element 'IO Software' --sw_io true - - -######## Implementation --- com.arc.hardware.implementation.1_0 ######## - -# Create Implementation --create com.arc.hardware.implementation.1_0 System.Implementation - -# ClockSpeed --- Target clock speed of the system --clock_speed 10 - -# DDR2_clk_Ratio --- DDR2 Clock Vs System Clock Ratio -# 2x -# 3x -# 4x --ddr2_clk_ratio 3x - -# ClockSkew --- The clock skew for the system --clock_skew 0.2 - -# HoldMargin --- Margin for hold time checks --hold_margin 0.05 - -# Floorplan --- Floorplan definition for relative placement of RAMs (at CPU-level) or the placement of the rams and CPU hard cores (at multicore level) --floorplan em4_sensor - -# JTAGFrequency --- Select the frequency of the JTAG clock Tck (in MHz). -# -# The JTAG clock speed has to be less than 1/2 of the cpu clock otherwise the signals on the BVCI interface are not guaranteed to be valid. -# -# NOTE: The RTL simulations will work when the JTAG clock frequency is set to half the CPU clock, however this may not be the case when simulating at gate level due to delays on the IO pads. -# -# The default is set to 10 MHz so that there is no conflict when simulating with an ARCangel3 at 30MHz. (30 > 10*2) -# -# The speed of simulation can be greatly increased by using a faster JTAG clock, but a dependency will warn if it exceeds 1/2 of the cpu clock. -# --jtag_tclk 4 - -# execution_trace_level --- -# This traces committed instructions as they execute, and gathers statistics -# visible in the debugger for counting instructions & cycle delays. -# At the "stats" level ony the statistics are gathered and no trace is printed. -# "file" is equivalent to "full", but the results go to a trace .txt file instead. -# --execution_trace_level stats - -# tb_trace --- -# Enable instruction execution trace. -# This is available to arc_dev licensees (internal developers) only. -# --tb_trace false - -# zero_based_arcnum --- -# In a multicore build, number ARCs from 0. -# If this is not selected, arcs are numbered from 1. -# (This provides the initial value to the arcnum signal.) -# --zero_based_arcnum true - -# generate_ipxact --- -# Generate ipxact.xml file describing the CPUisle or archipelago frontier -# --generate_ipxact false - -# ipxact_relative_path_names --- -# Use relative path names for Verilog files in the ipxact. -# Otherwise, absolute path names are used. -# --ipxact_relative_path_names true - -# optional_encryption --- -# When selected, encrypted RTL output is generated. -# --optional_encryption false - -# ignore_encrypt_license --- -# When selected, pretend the encryption license is missing. For testing. -# --ignore_encrypt_license false - -# ignore_clear_license --- -# When selected, pretend the cleartest license is missing. For testing. -# --ignore_clear_license false - -# OPTION_require_archipelago --- -# When selected, force use of archipelago. This is for testing purposes. -# --require_archipelago false - - -######## Infrastructure Software --- com.arc.software.scss.sw_infra.1_0 ######## - -# Create Infrastructure Software --create com.arc.software.scss.sw_infra.1_0 "System.Infrastructure Software" - -# sw_infra --- Command line option for Software element 'Infrastructure Software' --sw_infra true - -# templateName --- Template name --template_name siss_combo_sensor - - -######## subsys_infra --- com.arc.hardware.scss.subsys_infra.1_0 ######## - -# Create subsys_infra --create com.arc.hardware.scss.subsys_infra.1_0 System.subsys_infra - -# subsys_infra --- Command line option for EIA glue logic. --subsys_infra true - -# internal_interrupt --- Connect the IO interrupts internally --internal_interrupt false - -# internal_dma_handshake --- Connect the DMA handshake signals internally --internal_dma_handshake false - -# spi_tb_sw_test_mode --- -# This is a secret option, not seen by customers. -# If you check this, the SPI peripheral's testbenches will be set to SW test mode: -# The serial interface of the first SPI master io_sps_mstN peripheral is connected to all SPI slave peripherals io_spi_slvN. -# This is used for testing the SW drivers. -# --spi_tb_sw_test_mode false - - -######## Tool Configuration --- cgen.1_0 ######## - -# Create Tool Configuration --create cgen.1_0 "System.Tool Configuration" - -# mwdt_version --- Selects the MetaWare version to be used with the TCF file. -# Change from the default to an older or newer toolset version if you want the TCF file to be used with an older or newer version of the MetaWare tools. --mwdt_version M-2017.06 - -# code_base_addr --- -# The base address to assign to the executable code segment in the linker command file when there is no ICCM in the build. This value is ignored when there is an ICCM. -# --code_base_addr 0x0 - -# data_base_addr --- -# The base address to assign to the data segment in the linker command file when the data is not being mapped to a DCCM. This value is ignored when the data segment is mapped to a DCCM, as in that case the base address of the DCCM memory is used. -# -# A value of 0xffffffff means that the data segment will not be mapped to any specific address. -# --data_base_addr 0xffff_ffff - -# underscores_in_numbers --- Use underscores in hex numbers to improve readability. --underscores_in_numbers false - -# tcf_rebrand --- Alternate branding of TCF (not used) --rebrand false - - -]]> - - - - - - - - - - - - - - - ICCM0 - - GROUP BLOCK(4): { - /* _SDA_BASE_ computed implicitly */ - .sdata?: {} - .sbss?: {} - * (DATA): {} - * (BSS): {} - .stack ALIGN(4) SIZE(DEFINED _STACKSIZE?_STACKSIZE:65536): {} - .heap? ALIGN(4) SIZE(DEFINED _HEAPSIZE?_HEAPSIZE:0): {} - } > SYSTEM2 - GROUP BLOCK(4) : { - .vectors (TEXT) SIZE(DEFINED _IVTSIZE?_IVTSIZE:864): {} = FILL(0xa5a5a5a5,4) - } > IVT - } - -]]> - - - - - - 0x07, sub_opcode => 0x00 ) - -// User extension instruction - dsp_add_1d -extern long dsp_add_1d(long, long); -#pragma intrinsic(dsp_add_1d, opcode => 0x07, sub_opcode => 0x03 ) - -// User extension instruction - dsp_negate_1d -extern long dsp_negate_1d(long); -#pragma intrinsic(dsp_negate_1d, opcode => 0x07, sub_opcode => 0x0F ) - -// User extension instruction - dsp_shift_1d -extern long dsp_shift_1d(long, long); -#pragma intrinsic(dsp_shift_1d, opcode => 0x07, sub_opcode => 0x18 ) - -// User extension instruction - dsp_cos -extern long dsp_cos(long); -#pragma intrinsic(dsp_cos, opcode => 0x07, sub_opcode => 0x1E , latency_cycles => 8) - -// User extension instruction - dsp_sqrt -extern long dsp_sqrt(long); -#pragma intrinsic(dsp_sqrt, opcode => 0x07, sub_opcode => 0x20 , latency_cycles => 31) - -// User extension instruction - dsp_sub_1d -extern long dsp_sub_1d(long, long); -#pragma intrinsic(dsp_sub_1d, opcode => 0x07, sub_opcode => 0x06 ) - -// User extension instruction - dsp_abs_2d -extern long dsp_abs_2d(long); -#pragma intrinsic(dsp_abs_2d, opcode => 0x07, sub_opcode => 0x01 ) - -// User extension instruction - dsp_add_2d -extern long dsp_add_2d(long, long); -#pragma intrinsic(dsp_add_2d, opcode => 0x07, sub_opcode => 0x04 ) - -// User extension instruction - dsp_mulv_2d -extern long dsp_mulv_2d(long, long); -#pragma intrinsic(dsp_mulv_2d, opcode => 0x07, sub_opcode => 0x1E ) - -// User extension instruction - dsp_negate_2d -extern long dsp_negate_2d(long); -#pragma intrinsic(dsp_negate_2d, opcode => 0x07, sub_opcode => 0x10 ) - -// User extension instruction - dsp_shift_2d -extern long dsp_shift_2d(long, long); -#pragma intrinsic(dsp_shift_2d, opcode => 0x07, sub_opcode => 0x19 ) - -// User extension instruction - dsp_sin -extern long dsp_sin(long); -#pragma intrinsic(dsp_sin, opcode => 0x07, sub_opcode => 0x1F , latency_cycles => 8) - -// User extension instruction - dsp_sqrt15 -extern long dsp_sqrt15(long); -#pragma intrinsic(dsp_sqrt15, opcode => 0x07, sub_opcode => 0x21 , latency_cycles => 15) - -// User extension instruction - dsp_sub_2d -extern long dsp_sub_2d(long, long); -#pragma intrinsic(dsp_sub_2d, opcode => 0x07, sub_opcode => 0x07 ) - -// User extension instruction - dsp_abs_4d -extern long dsp_abs_4d(long); -#pragma intrinsic(dsp_abs_4d, opcode => 0x07, sub_opcode => 0x02 ) - -// User extension instruction - dsp_add_4d -extern long dsp_add_4d(long, long); -#pragma intrinsic(dsp_add_4d, opcode => 0x07, sub_opcode => 0x05 ) - -// User extension instruction - dsp_mulv_4d -extern long dsp_mulv_4d(long, long); -#pragma intrinsic(dsp_mulv_4d, opcode => 0x07, sub_opcode => 0x1F ) - -// User extension instruction - dsp_negate_4d -extern long dsp_negate_4d(long); -#pragma intrinsic(dsp_negate_4d, opcode => 0x07, sub_opcode => 0x11 ) - -// User extension instruction - dsp_shift_4d -extern long dsp_shift_4d(long, long); -#pragma intrinsic(dsp_shift_4d, opcode => 0x07, sub_opcode => 0x1A ) - -// User extension instruction - dsp_sub_4d -extern long dsp_sub_4d(long, long); -#pragma intrinsic(dsp_sub_4d, opcode => 0x07, sub_opcode => 0x08 ) - -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_ABS_PRESENT 1 -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_ACM_PRESENT 1 - -// User extension core register dsp_acm_msbout -#define CR_DSP_ACM_MSBOUT 54 -#pragma Core_register(54, name=>"dsp_acm_msbout", non_interlock_cycles=>"2", side_effects=>"rw") - -// User extension core register dsp_acm_lsbout -#define CR_DSP_ACM_LSBOUT 53 -#pragma Core_register(53, name=>"dsp_acm_lsbout", non_interlock_cycles=>"2", side_effects=>"rw") - -// User extension instruction dsp_acm -extern long dsp_acm(long,long); -#pragma intrinsic(dsp_acm,opcode=>7,sub_opcode=>29, effects=>"53:is_read:is_written; 54:is_read:is_written") -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_ADD_PRESENT 1 -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_MAC_PRESENT 1 - -// User extension core register dsp_mac_lsbout -#define CR_DSP_MAC_LSBOUT 56 -#pragma Core_register(56, name=>"dsp_mac_lsbout", non_interlock_cycles=>"2", side_effects=>"rw") - -// User extension core register dsp_mac_msbout -#define CR_DSP_MAC_MSBOUT 57 -#pragma Core_register(57, name=>"dsp_mac_msbout", non_interlock_cycles=>"2", side_effects=>"rw") - -// User extension instruction dsp_mac -extern long dsp_mac(long,long); -#pragma intrinsic(dsp_mac,opcode=>7,sub_opcode=>27, effects=>"56:is_read:is_written; 57:is_read:is_written") - -// User extension instruction dsp_mult -extern long dsp_mult(long,long); -#pragma intrinsic(dsp_mult,opcode=>7,sub_opcode=>28, effects=>"56:is_written; 57:is_written") -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_MULT_PRESENT 1 - -// User extension core register dsp_mult -#define CR_DSP_MULT 55 -#pragma Core_register(55, name=>"dsp_mult", non_interlock_cycles=>"2") - -// User extension instruction dsp_mult_2d -extern long dsp_mult_2d(long,long); -#pragma intrinsic(dsp_mult_2d,opcode=>7,sub_opcode=>13, effects=>"55:is_written") - -// User extension instruction dsp_mult_4d -extern long dsp_mult_4d(long,long); -#pragma intrinsic(dsp_mult_4d,opcode=>7,sub_opcode=>14, effects=>"55:is_written") -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_MULV_PRESENT 1 -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_NEGATE_PRESENT 1 -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_SHIFT_PRESENT 1 -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_SINCOS_PRESENT 1 -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_SQRT_PRESENT 1 -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_SUB_PRESENT 1 -#define APEX_COM_ARC_HARDWARE_SCSS_IO_GPIO0_PRESENT 1 - -// User extension aux register io_gpio0_debounce -#define AR_IO_GPIO0_DEBOUNCE 0x80017048 -#pragma Aux_register(0x80017048, name=>"io_gpio0_debounce") - -// User extension aux register io_gpio0_clken -#define AR_IO_GPIO0_CLKEN 0x80017080 -#pragma Aux_register(0x80017080, name=>"io_gpio0_clken") - -// User extension aux register io_gpio0_swporta_dr -#define AR_IO_GPIO0_SWPORTA_DR 0x80017000 -#pragma Aux_register(0x80017000, name=>"io_gpio0_swporta_dr") - -// User extension aux register io_gpio0_swporta_ddr -#define AR_IO_GPIO0_SWPORTA_DDR 0x80017004 -#pragma Aux_register(0x80017004, name=>"io_gpio0_swporta_ddr") - -// User extension aux register io_gpio0_inten -#define AR_IO_GPIO0_INTEN 0x80017030 -#pragma Aux_register(0x80017030, name=>"io_gpio0_inten") - -// User extension aux register io_gpio0_intmask -#define AR_IO_GPIO0_INTMASK 0x80017034 -#pragma Aux_register(0x80017034, name=>"io_gpio0_intmask") - -// User extension aux register io_gpio0_inttype_level -#define AR_IO_GPIO0_INTTYPE_LEVEL 0x80017038 -#pragma Aux_register(0x80017038, name=>"io_gpio0_inttype_level") - -// User extension aux register io_gpio0_int_polarity -#define AR_IO_GPIO0_INT_POLARITY 0x8001703c -#pragma Aux_register(0x8001703c, name=>"io_gpio0_int_polarity") - -// User extension aux register io_gpio0_intstatus -#define AR_IO_GPIO0_INTSTATUS 0x80017040 -#pragma Aux_register(0x80017040, name=>"io_gpio0_intstatus") - -// User extension aux register io_gpio0_raw_intstatus -#define AR_IO_GPIO0_RAW_INTSTATUS 0x80017044 -#pragma Aux_register(0x80017044, name=>"io_gpio0_raw_intstatus") - -// User extension aux register io_gpio0_porta_eoi -#define AR_IO_GPIO0_PORTA_EOI 0x8001704c -#pragma Aux_register(0x8001704c, name=>"io_gpio0_porta_eoi") - -// User extension aux register io_gpio0_ext_porta -#define AR_IO_GPIO0_EXT_PORTA 0x80017050 -#pragma Aux_register(0x80017050, name=>"io_gpio0_ext_porta") - -// User extension aux register io_gpio0_ls_sync -#define AR_IO_GPIO0_LS_SYNC 0x80017060 -#pragma Aux_register(0x80017060, name=>"io_gpio0_ls_sync") - -// User extension aux register io_gpio0_int_bothedge -#define AR_IO_GPIO0_INT_BOTHEDGE 0x80017068 -#pragma Aux_register(0x80017068, name=>"io_gpio0_int_bothedge") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_GPIO1_PRESENT 1 - -// User extension aux register io_gpio1_debounce -#define AR_IO_GPIO1_DEBOUNCE 0x80017148 -#pragma Aux_register(0x80017148, name=>"io_gpio1_debounce") - -// User extension aux register io_gpio1_clken -#define AR_IO_GPIO1_CLKEN 0x80017180 -#pragma Aux_register(0x80017180, name=>"io_gpio1_clken") - -// User extension aux register io_gpio1_swporta_dr -#define AR_IO_GPIO1_SWPORTA_DR 0x80017100 -#pragma Aux_register(0x80017100, name=>"io_gpio1_swporta_dr") - -// User extension aux register io_gpio1_swporta_ddr -#define AR_IO_GPIO1_SWPORTA_DDR 0x80017104 -#pragma Aux_register(0x80017104, name=>"io_gpio1_swporta_ddr") - -// User extension aux register io_gpio1_inten -#define AR_IO_GPIO1_INTEN 0x80017130 -#pragma Aux_register(0x80017130, name=>"io_gpio1_inten") - -// User extension aux register io_gpio1_intmask -#define AR_IO_GPIO1_INTMASK 0x80017134 -#pragma Aux_register(0x80017134, name=>"io_gpio1_intmask") - -// User extension aux register io_gpio1_inttype_level -#define AR_IO_GPIO1_INTTYPE_LEVEL 0x80017138 -#pragma Aux_register(0x80017138, name=>"io_gpio1_inttype_level") - -// User extension aux register io_gpio1_int_polarity -#define AR_IO_GPIO1_INT_POLARITY 0x8001713c -#pragma Aux_register(0x8001713c, name=>"io_gpio1_int_polarity") - -// User extension aux register io_gpio1_intstatus -#define AR_IO_GPIO1_INTSTATUS 0x80017140 -#pragma Aux_register(0x80017140, name=>"io_gpio1_intstatus") - -// User extension aux register io_gpio1_raw_intstatus -#define AR_IO_GPIO1_RAW_INTSTATUS 0x80017144 -#pragma Aux_register(0x80017144, name=>"io_gpio1_raw_intstatus") - -// User extension aux register io_gpio1_porta_eoi -#define AR_IO_GPIO1_PORTA_EOI 0x8001714c -#pragma Aux_register(0x8001714c, name=>"io_gpio1_porta_eoi") - -// User extension aux register io_gpio1_ext_porta -#define AR_IO_GPIO1_EXT_PORTA 0x80017150 -#pragma Aux_register(0x80017150, name=>"io_gpio1_ext_porta") - -// User extension aux register io_gpio1_ls_sync -#define AR_IO_GPIO1_LS_SYNC 0x80017160 -#pragma Aux_register(0x80017160, name=>"io_gpio1_ls_sync") - -// User extension aux register io_gpio1_int_bothedge -#define AR_IO_GPIO1_INT_BOTHEDGE 0x80017168 -#pragma Aux_register(0x80017168, name=>"io_gpio1_int_bothedge") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_GPIO2_PRESENT 1 - -// User extension aux register io_gpio2_debounce -#define AR_IO_GPIO2_DEBOUNCE 0x80017248 -#pragma Aux_register(0x80017248, name=>"io_gpio2_debounce") - -// User extension aux register io_gpio2_clken -#define AR_IO_GPIO2_CLKEN 0x80017280 -#pragma Aux_register(0x80017280, name=>"io_gpio2_clken") - -// User extension aux register io_gpio2_swporta_dr -#define AR_IO_GPIO2_SWPORTA_DR 0x80017200 -#pragma Aux_register(0x80017200, name=>"io_gpio2_swporta_dr") - -// User extension aux register io_gpio2_swporta_ddr -#define AR_IO_GPIO2_SWPORTA_DDR 0x80017204 -#pragma Aux_register(0x80017204, name=>"io_gpio2_swporta_ddr") - -// User extension aux register io_gpio2_inten -#define AR_IO_GPIO2_INTEN 0x80017230 -#pragma Aux_register(0x80017230, name=>"io_gpio2_inten") - -// User extension aux register io_gpio2_intmask -#define AR_IO_GPIO2_INTMASK 0x80017234 -#pragma Aux_register(0x80017234, name=>"io_gpio2_intmask") - -// User extension aux register io_gpio2_inttype_level -#define AR_IO_GPIO2_INTTYPE_LEVEL 0x80017238 -#pragma Aux_register(0x80017238, name=>"io_gpio2_inttype_level") - -// User extension aux register io_gpio2_int_polarity -#define AR_IO_GPIO2_INT_POLARITY 0x8001723c -#pragma Aux_register(0x8001723c, name=>"io_gpio2_int_polarity") - -// User extension aux register io_gpio2_intstatus -#define AR_IO_GPIO2_INTSTATUS 0x80017240 -#pragma Aux_register(0x80017240, name=>"io_gpio2_intstatus") - -// User extension aux register io_gpio2_raw_intstatus -#define AR_IO_GPIO2_RAW_INTSTATUS 0x80017244 -#pragma Aux_register(0x80017244, name=>"io_gpio2_raw_intstatus") - -// User extension aux register io_gpio2_porta_eoi -#define AR_IO_GPIO2_PORTA_EOI 0x8001724c -#pragma Aux_register(0x8001724c, name=>"io_gpio2_porta_eoi") - -// User extension aux register io_gpio2_ext_porta -#define AR_IO_GPIO2_EXT_PORTA 0x80017250 -#pragma Aux_register(0x80017250, name=>"io_gpio2_ext_porta") - -// User extension aux register io_gpio2_ls_sync -#define AR_IO_GPIO2_LS_SYNC 0x80017260 -#pragma Aux_register(0x80017260, name=>"io_gpio2_ls_sync") - -// User extension aux register io_gpio2_int_bothedge -#define AR_IO_GPIO2_INT_BOTHEDGE 0x80017268 -#pragma Aux_register(0x80017268, name=>"io_gpio2_int_bothedge") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_I2C_MST0_PRESENT 1 - -// User extension aux register io_i2c_mst0_clken -#define AR_IO_I2C_MST0_CLKEN 0x800120c0 -#pragma Aux_register(0x800120c0, name=>"io_i2c_mst0_clken") - -// User extension aux register io_i2c_mst0_con -#define AR_IO_I2C_MST0_CON 0x80012000 -#pragma Aux_register(0x80012000, name=>"io_i2c_mst0_con") - -// User extension aux register io_i2c_mst0_tar -#define AR_IO_I2C_MST0_TAR 0x80012004 -#pragma Aux_register(0x80012004, name=>"io_i2c_mst0_tar") - -// User extension aux register io_i2c_mst0_data_cmd -#define AR_IO_I2C_MST0_DATA_CMD 0x80012010 -#pragma Aux_register(0x80012010, name=>"io_i2c_mst0_data_cmd") - -// User extension aux register io_i2c_mst0_ss_scl_hcnt -#define AR_IO_I2C_MST0_SS_SCL_HCNT 0x80012014 -#pragma Aux_register(0x80012014, name=>"io_i2c_mst0_ss_scl_hcnt") - -// User extension aux register io_i2c_mst0_ss_scl_lcnt -#define AR_IO_I2C_MST0_SS_SCL_LCNT 0x80012018 -#pragma Aux_register(0x80012018, name=>"io_i2c_mst0_ss_scl_lcnt") - -// User extension aux register io_i2c_mst0_fs_scl_hcnt -#define AR_IO_I2C_MST0_FS_SCL_HCNT 0x8001201c -#pragma Aux_register(0x8001201c, name=>"io_i2c_mst0_fs_scl_hcnt") - -// User extension aux register io_i2c_mst0_fs_scl_lcnt -#define AR_IO_I2C_MST0_FS_SCL_LCNT 0x80012020 -#pragma Aux_register(0x80012020, name=>"io_i2c_mst0_fs_scl_lcnt") - -// User extension aux register io_i2c_mst0_intr_stat -#define AR_IO_I2C_MST0_INTR_STAT 0x8001202c -#pragma Aux_register(0x8001202c, name=>"io_i2c_mst0_intr_stat") - -// User extension aux register io_i2c_mst0_intr_mask -#define AR_IO_I2C_MST0_INTR_MASK 0x80012030 -#pragma Aux_register(0x80012030, name=>"io_i2c_mst0_intr_mask") - -// User extension aux register io_i2c_mst0_raw_intr_stat -#define AR_IO_I2C_MST0_RAW_INTR_STAT 0x80012034 -#pragma Aux_register(0x80012034, name=>"io_i2c_mst0_raw_intr_stat") - -// User extension aux register io_i2c_mst0_rx_tl -#define AR_IO_I2C_MST0_RX_TL 0x80012038 -#pragma Aux_register(0x80012038, name=>"io_i2c_mst0_rx_tl") - -// User extension aux register io_i2c_mst0_tx_tl -#define AR_IO_I2C_MST0_TX_TL 0x8001203c -#pragma Aux_register(0x8001203c, name=>"io_i2c_mst0_tx_tl") - -// User extension aux register io_i2c_mst0_clr_intr -#define AR_IO_I2C_MST0_CLR_INTR 0x80012040 -#pragma Aux_register(0x80012040, name=>"io_i2c_mst0_clr_intr") - -// User extension aux register io_i2c_mst0_clr_rx_under -#define AR_IO_I2C_MST0_CLR_RX_UNDER 0x80012044 -#pragma Aux_register(0x80012044, name=>"io_i2c_mst0_clr_rx_under") - -// User extension aux register io_i2c_mst0_clr_rx_over -#define AR_IO_I2C_MST0_CLR_RX_OVER 0x80012048 -#pragma Aux_register(0x80012048, name=>"io_i2c_mst0_clr_rx_over") - -// User extension aux register io_i2c_mst0_clr_tx_over -#define AR_IO_I2C_MST0_CLR_TX_OVER 0x8001204c -#pragma Aux_register(0x8001204c, name=>"io_i2c_mst0_clr_tx_over") - -// User extension aux register io_i2c_mst0_clr_tx_abrt -#define AR_IO_I2C_MST0_CLR_TX_ABRT 0x80012054 -#pragma Aux_register(0x80012054, name=>"io_i2c_mst0_clr_tx_abrt") - -// User extension aux register io_i2c_mst0_clr_activity -#define AR_IO_I2C_MST0_CLR_ACTIVITY 0x8001205c -#pragma Aux_register(0x8001205c, name=>"io_i2c_mst0_clr_activity") - -// User extension aux register io_i2c_mst0_clr_stop_det -#define AR_IO_I2C_MST0_CLR_STOP_DET 0x80012060 -#pragma Aux_register(0x80012060, name=>"io_i2c_mst0_clr_stop_det") - -// User extension aux register io_i2c_mst0_clr_start_det -#define AR_IO_I2C_MST0_CLR_START_DET 0x80012064 -#pragma Aux_register(0x80012064, name=>"io_i2c_mst0_clr_start_det") - -// User extension aux register io_i2c_mst0_enable -#define AR_IO_I2C_MST0_ENABLE 0x8001206c -#pragma Aux_register(0x8001206c, name=>"io_i2c_mst0_enable") - -// User extension aux register io_i2c_mst0_status -#define AR_IO_I2C_MST0_STATUS 0x80012070 -#pragma Aux_register(0x80012070, name=>"io_i2c_mst0_status") - -// User extension aux register io_i2c_mst0_txflr -#define AR_IO_I2C_MST0_TXFLR 0x80012074 -#pragma Aux_register(0x80012074, name=>"io_i2c_mst0_txflr") - -// User extension aux register io_i2c_mst0_rxflr -#define AR_IO_I2C_MST0_RXFLR 0x80012078 -#pragma Aux_register(0x80012078, name=>"io_i2c_mst0_rxflr") - -// User extension aux register io_i2c_mst0_sda_hold -#define AR_IO_I2C_MST0_SDA_HOLD 0x8001207c -#pragma Aux_register(0x8001207c, name=>"io_i2c_mst0_sda_hold") - -// User extension aux register io_i2c_mst0_tx_abrt_source -#define AR_IO_I2C_MST0_TX_ABRT_SOURCE 0x80012080 -#pragma Aux_register(0x80012080, name=>"io_i2c_mst0_tx_abrt_source") - -// User extension aux register io_i2c_mst0_enable_status -#define AR_IO_I2C_MST0_ENABLE_STATUS 0x8001209c -#pragma Aux_register(0x8001209c, name=>"io_i2c_mst0_enable_status") - -// User extension aux register io_i2c_mst0_fs_spklen -#define AR_IO_I2C_MST0_FS_SPKLEN 0x800120a0 -#pragma Aux_register(0x800120a0, name=>"io_i2c_mst0_fs_spklen") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_I2C_MST1_PRESENT 1 - -// User extension aux register io_i2c_mst1_clken -#define AR_IO_I2C_MST1_CLKEN 0x800121c0 -#pragma Aux_register(0x800121c0, name=>"io_i2c_mst1_clken") - -// User extension aux register io_i2c_mst1_con -#define AR_IO_I2C_MST1_CON 0x80012100 -#pragma Aux_register(0x80012100, name=>"io_i2c_mst1_con") - -// User extension aux register io_i2c_mst1_tar -#define AR_IO_I2C_MST1_TAR 0x80012104 -#pragma Aux_register(0x80012104, name=>"io_i2c_mst1_tar") - -// User extension aux register io_i2c_mst1_data_cmd -#define AR_IO_I2C_MST1_DATA_CMD 0x80012110 -#pragma Aux_register(0x80012110, name=>"io_i2c_mst1_data_cmd") - -// User extension aux register io_i2c_mst1_ss_scl_hcnt -#define AR_IO_I2C_MST1_SS_SCL_HCNT 0x80012114 -#pragma Aux_register(0x80012114, name=>"io_i2c_mst1_ss_scl_hcnt") - -// User extension aux register io_i2c_mst1_ss_scl_lcnt -#define AR_IO_I2C_MST1_SS_SCL_LCNT 0x80012118 -#pragma Aux_register(0x80012118, name=>"io_i2c_mst1_ss_scl_lcnt") - -// User extension aux register io_i2c_mst1_fs_scl_hcnt -#define AR_IO_I2C_MST1_FS_SCL_HCNT 0x8001211c -#pragma Aux_register(0x8001211c, name=>"io_i2c_mst1_fs_scl_hcnt") - -// User extension aux register io_i2c_mst1_fs_scl_lcnt -#define AR_IO_I2C_MST1_FS_SCL_LCNT 0x80012120 -#pragma Aux_register(0x80012120, name=>"io_i2c_mst1_fs_scl_lcnt") - -// User extension aux register io_i2c_mst1_intr_stat -#define AR_IO_I2C_MST1_INTR_STAT 0x8001212c -#pragma Aux_register(0x8001212c, name=>"io_i2c_mst1_intr_stat") - -// User extension aux register io_i2c_mst1_intr_mask -#define AR_IO_I2C_MST1_INTR_MASK 0x80012130 -#pragma Aux_register(0x80012130, name=>"io_i2c_mst1_intr_mask") - -// User extension aux register io_i2c_mst1_raw_intr_stat -#define AR_IO_I2C_MST1_RAW_INTR_STAT 0x80012134 -#pragma Aux_register(0x80012134, name=>"io_i2c_mst1_raw_intr_stat") - -// User extension aux register io_i2c_mst1_rx_tl -#define AR_IO_I2C_MST1_RX_TL 0x80012138 -#pragma Aux_register(0x80012138, name=>"io_i2c_mst1_rx_tl") - -// User extension aux register io_i2c_mst1_tx_tl -#define AR_IO_I2C_MST1_TX_TL 0x8001213c -#pragma Aux_register(0x8001213c, name=>"io_i2c_mst1_tx_tl") - -// User extension aux register io_i2c_mst1_clr_intr -#define AR_IO_I2C_MST1_CLR_INTR 0x80012140 -#pragma Aux_register(0x80012140, name=>"io_i2c_mst1_clr_intr") - -// User extension aux register io_i2c_mst1_clr_rx_under -#define AR_IO_I2C_MST1_CLR_RX_UNDER 0x80012144 -#pragma Aux_register(0x80012144, name=>"io_i2c_mst1_clr_rx_under") - -// User extension aux register io_i2c_mst1_clr_rx_over -#define AR_IO_I2C_MST1_CLR_RX_OVER 0x80012148 -#pragma Aux_register(0x80012148, name=>"io_i2c_mst1_clr_rx_over") - -// User extension aux register io_i2c_mst1_clr_tx_over -#define AR_IO_I2C_MST1_CLR_TX_OVER 0x8001214c -#pragma Aux_register(0x8001214c, name=>"io_i2c_mst1_clr_tx_over") - -// User extension aux register io_i2c_mst1_clr_tx_abrt -#define AR_IO_I2C_MST1_CLR_TX_ABRT 0x80012154 -#pragma Aux_register(0x80012154, name=>"io_i2c_mst1_clr_tx_abrt") - -// User extension aux register io_i2c_mst1_clr_activity -#define AR_IO_I2C_MST1_CLR_ACTIVITY 0x8001215c -#pragma Aux_register(0x8001215c, name=>"io_i2c_mst1_clr_activity") - -// User extension aux register io_i2c_mst1_clr_stop_det -#define AR_IO_I2C_MST1_CLR_STOP_DET 0x80012160 -#pragma Aux_register(0x80012160, name=>"io_i2c_mst1_clr_stop_det") - -// User extension aux register io_i2c_mst1_clr_start_det -#define AR_IO_I2C_MST1_CLR_START_DET 0x80012164 -#pragma Aux_register(0x80012164, name=>"io_i2c_mst1_clr_start_det") - -// User extension aux register io_i2c_mst1_enable -#define AR_IO_I2C_MST1_ENABLE 0x8001216c -#pragma Aux_register(0x8001216c, name=>"io_i2c_mst1_enable") - -// User extension aux register io_i2c_mst1_status -#define AR_IO_I2C_MST1_STATUS 0x80012170 -#pragma Aux_register(0x80012170, name=>"io_i2c_mst1_status") - -// User extension aux register io_i2c_mst1_txflr -#define AR_IO_I2C_MST1_TXFLR 0x80012174 -#pragma Aux_register(0x80012174, name=>"io_i2c_mst1_txflr") - -// User extension aux register io_i2c_mst1_rxflr -#define AR_IO_I2C_MST1_RXFLR 0x80012178 -#pragma Aux_register(0x80012178, name=>"io_i2c_mst1_rxflr") - -// User extension aux register io_i2c_mst1_sda_hold -#define AR_IO_I2C_MST1_SDA_HOLD 0x8001217c -#pragma Aux_register(0x8001217c, name=>"io_i2c_mst1_sda_hold") - -// User extension aux register io_i2c_mst1_tx_abrt_source -#define AR_IO_I2C_MST1_TX_ABRT_SOURCE 0x80012180 -#pragma Aux_register(0x80012180, name=>"io_i2c_mst1_tx_abrt_source") - -// User extension aux register io_i2c_mst1_enable_status -#define AR_IO_I2C_MST1_ENABLE_STATUS 0x8001219c -#pragma Aux_register(0x8001219c, name=>"io_i2c_mst1_enable_status") - -// User extension aux register io_i2c_mst1_fs_spklen -#define AR_IO_I2C_MST1_FS_SPKLEN 0x800121a0 -#pragma Aux_register(0x800121a0, name=>"io_i2c_mst1_fs_spklen") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_I2C_MST2_PRESENT 1 - -// User extension aux register io_i2c_mst2_clken -#define AR_IO_I2C_MST2_CLKEN 0x800122c0 -#pragma Aux_register(0x800122c0, name=>"io_i2c_mst2_clken") - -// User extension aux register io_i2c_mst2_con -#define AR_IO_I2C_MST2_CON 0x80012200 -#pragma Aux_register(0x80012200, name=>"io_i2c_mst2_con") - -// User extension aux register io_i2c_mst2_tar -#define AR_IO_I2C_MST2_TAR 0x80012204 -#pragma Aux_register(0x80012204, name=>"io_i2c_mst2_tar") - -// User extension aux register io_i2c_mst2_data_cmd -#define AR_IO_I2C_MST2_DATA_CMD 0x80012210 -#pragma Aux_register(0x80012210, name=>"io_i2c_mst2_data_cmd") - -// User extension aux register io_i2c_mst2_ss_scl_hcnt -#define AR_IO_I2C_MST2_SS_SCL_HCNT 0x80012214 -#pragma Aux_register(0x80012214, name=>"io_i2c_mst2_ss_scl_hcnt") - -// User extension aux register io_i2c_mst2_ss_scl_lcnt -#define AR_IO_I2C_MST2_SS_SCL_LCNT 0x80012218 -#pragma Aux_register(0x80012218, name=>"io_i2c_mst2_ss_scl_lcnt") - -// User extension aux register io_i2c_mst2_fs_scl_hcnt -#define AR_IO_I2C_MST2_FS_SCL_HCNT 0x8001221c -#pragma Aux_register(0x8001221c, name=>"io_i2c_mst2_fs_scl_hcnt") - -// User extension aux register io_i2c_mst2_fs_scl_lcnt -#define AR_IO_I2C_MST2_FS_SCL_LCNT 0x80012220 -#pragma Aux_register(0x80012220, name=>"io_i2c_mst2_fs_scl_lcnt") - -// User extension aux register io_i2c_mst2_intr_stat -#define AR_IO_I2C_MST2_INTR_STAT 0x8001222c -#pragma Aux_register(0x8001222c, name=>"io_i2c_mst2_intr_stat") - -// User extension aux register io_i2c_mst2_intr_mask -#define AR_IO_I2C_MST2_INTR_MASK 0x80012230 -#pragma Aux_register(0x80012230, name=>"io_i2c_mst2_intr_mask") - -// User extension aux register io_i2c_mst2_raw_intr_stat -#define AR_IO_I2C_MST2_RAW_INTR_STAT 0x80012234 -#pragma Aux_register(0x80012234, name=>"io_i2c_mst2_raw_intr_stat") - -// User extension aux register io_i2c_mst2_rx_tl -#define AR_IO_I2C_MST2_RX_TL 0x80012238 -#pragma Aux_register(0x80012238, name=>"io_i2c_mst2_rx_tl") - -// User extension aux register io_i2c_mst2_tx_tl -#define AR_IO_I2C_MST2_TX_TL 0x8001223c -#pragma Aux_register(0x8001223c, name=>"io_i2c_mst2_tx_tl") - -// User extension aux register io_i2c_mst2_clr_intr -#define AR_IO_I2C_MST2_CLR_INTR 0x80012240 -#pragma Aux_register(0x80012240, name=>"io_i2c_mst2_clr_intr") - -// User extension aux register io_i2c_mst2_clr_rx_under -#define AR_IO_I2C_MST2_CLR_RX_UNDER 0x80012244 -#pragma Aux_register(0x80012244, name=>"io_i2c_mst2_clr_rx_under") - -// User extension aux register io_i2c_mst2_clr_rx_over -#define AR_IO_I2C_MST2_CLR_RX_OVER 0x80012248 -#pragma Aux_register(0x80012248, name=>"io_i2c_mst2_clr_rx_over") - -// User extension aux register io_i2c_mst2_clr_tx_over -#define AR_IO_I2C_MST2_CLR_TX_OVER 0x8001224c -#pragma Aux_register(0x8001224c, name=>"io_i2c_mst2_clr_tx_over") - -// User extension aux register io_i2c_mst2_clr_tx_abrt -#define AR_IO_I2C_MST2_CLR_TX_ABRT 0x80012254 -#pragma Aux_register(0x80012254, name=>"io_i2c_mst2_clr_tx_abrt") - -// User extension aux register io_i2c_mst2_clr_activity -#define AR_IO_I2C_MST2_CLR_ACTIVITY 0x8001225c -#pragma Aux_register(0x8001225c, name=>"io_i2c_mst2_clr_activity") - -// User extension aux register io_i2c_mst2_clr_stop_det -#define AR_IO_I2C_MST2_CLR_STOP_DET 0x80012260 -#pragma Aux_register(0x80012260, name=>"io_i2c_mst2_clr_stop_det") - -// User extension aux register io_i2c_mst2_clr_start_det -#define AR_IO_I2C_MST2_CLR_START_DET 0x80012264 -#pragma Aux_register(0x80012264, name=>"io_i2c_mst2_clr_start_det") - -// User extension aux register io_i2c_mst2_enable -#define AR_IO_I2C_MST2_ENABLE 0x8001226c -#pragma Aux_register(0x8001226c, name=>"io_i2c_mst2_enable") - -// User extension aux register io_i2c_mst2_status -#define AR_IO_I2C_MST2_STATUS 0x80012270 -#pragma Aux_register(0x80012270, name=>"io_i2c_mst2_status") - -// User extension aux register io_i2c_mst2_txflr -#define AR_IO_I2C_MST2_TXFLR 0x80012274 -#pragma Aux_register(0x80012274, name=>"io_i2c_mst2_txflr") - -// User extension aux register io_i2c_mst2_rxflr -#define AR_IO_I2C_MST2_RXFLR 0x80012278 -#pragma Aux_register(0x80012278, name=>"io_i2c_mst2_rxflr") - -// User extension aux register io_i2c_mst2_sda_hold -#define AR_IO_I2C_MST2_SDA_HOLD 0x8001227c -#pragma Aux_register(0x8001227c, name=>"io_i2c_mst2_sda_hold") - -// User extension aux register io_i2c_mst2_tx_abrt_source -#define AR_IO_I2C_MST2_TX_ABRT_SOURCE 0x80012280 -#pragma Aux_register(0x80012280, name=>"io_i2c_mst2_tx_abrt_source") - -// User extension aux register io_i2c_mst2_enable_status -#define AR_IO_I2C_MST2_ENABLE_STATUS 0x8001229c -#pragma Aux_register(0x8001229c, name=>"io_i2c_mst2_enable_status") - -// User extension aux register io_i2c_mst2_fs_spklen -#define AR_IO_I2C_MST2_FS_SPKLEN 0x800122a0 -#pragma Aux_register(0x800122a0, name=>"io_i2c_mst2_fs_spklen") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_I2C_SLV0_PRESENT 1 - -// User extension aux register io_i2c_slv0_clken -#define AR_IO_I2C_SLV0_CLKEN 0x800130c0 -#pragma Aux_register(0x800130c0, name=>"io_i2c_slv0_clken") - -// User extension aux register io_i2c_slv0_con -#define AR_IO_I2C_SLV0_CON 0x80013000 -#pragma Aux_register(0x80013000, name=>"io_i2c_slv0_con") - -// User extension aux register io_i2c_slv0_sar -#define AR_IO_I2C_SLV0_SAR 0x80013008 -#pragma Aux_register(0x80013008, name=>"io_i2c_slv0_sar") - -// User extension aux register io_i2c_slv0_data_cmd -#define AR_IO_I2C_SLV0_DATA_CMD 0x80013010 -#pragma Aux_register(0x80013010, name=>"io_i2c_slv0_data_cmd") - -// User extension aux register io_i2c_slv0_intr_stat -#define AR_IO_I2C_SLV0_INTR_STAT 0x8001302c -#pragma Aux_register(0x8001302c, name=>"io_i2c_slv0_intr_stat") - -// User extension aux register io_i2c_slv0_intr_mask -#define AR_IO_I2C_SLV0_INTR_MASK 0x80013030 -#pragma Aux_register(0x80013030, name=>"io_i2c_slv0_intr_mask") - -// User extension aux register io_i2c_slv0_raw_intr_stat -#define AR_IO_I2C_SLV0_RAW_INTR_STAT 0x80013034 -#pragma Aux_register(0x80013034, name=>"io_i2c_slv0_raw_intr_stat") - -// User extension aux register io_i2c_slv0_rx_tl -#define AR_IO_I2C_SLV0_RX_TL 0x80013038 -#pragma Aux_register(0x80013038, name=>"io_i2c_slv0_rx_tl") - -// User extension aux register io_i2c_slv0_tx_tl -#define AR_IO_I2C_SLV0_TX_TL 0x8001303c -#pragma Aux_register(0x8001303c, name=>"io_i2c_slv0_tx_tl") - -// User extension aux register io_i2c_slv0_clr_intr -#define AR_IO_I2C_SLV0_CLR_INTR 0x80013040 -#pragma Aux_register(0x80013040, name=>"io_i2c_slv0_clr_intr") - -// User extension aux register io_i2c_slv0_clr_rx_under -#define AR_IO_I2C_SLV0_CLR_RX_UNDER 0x80013044 -#pragma Aux_register(0x80013044, name=>"io_i2c_slv0_clr_rx_under") - -// User extension aux register io_i2c_slv0_clr_rx_over -#define AR_IO_I2C_SLV0_CLR_RX_OVER 0x80013048 -#pragma Aux_register(0x80013048, name=>"io_i2c_slv0_clr_rx_over") - -// User extension aux register io_i2c_slv0_clr_tx_over -#define AR_IO_I2C_SLV0_CLR_TX_OVER 0x8001304c -#pragma Aux_register(0x8001304c, name=>"io_i2c_slv0_clr_tx_over") - -// User extension aux register io_i2c_slv0_clr_rd_req -#define AR_IO_I2C_SLV0_CLR_RD_REQ 0x80013050 -#pragma Aux_register(0x80013050, name=>"io_i2c_slv0_clr_rd_req") - -// User extension aux register io_i2c_slv0_clr_tx_abrt -#define AR_IO_I2C_SLV0_CLR_TX_ABRT 0x80013054 -#pragma Aux_register(0x80013054, name=>"io_i2c_slv0_clr_tx_abrt") - -// User extension aux register io_i2c_slv0_clr_rx_done -#define AR_IO_I2C_SLV0_CLR_RX_DONE 0x80013058 -#pragma Aux_register(0x80013058, name=>"io_i2c_slv0_clr_rx_done") - -// User extension aux register io_i2c_slv0_clr_activity -#define AR_IO_I2C_SLV0_CLR_ACTIVITY 0x8001305c -#pragma Aux_register(0x8001305c, name=>"io_i2c_slv0_clr_activity") - -// User extension aux register io_i2c_slv0_clr_stop_det -#define AR_IO_I2C_SLV0_CLR_STOP_DET 0x80013060 -#pragma Aux_register(0x80013060, name=>"io_i2c_slv0_clr_stop_det") - -// User extension aux register io_i2c_slv0_clr_start_det -#define AR_IO_I2C_SLV0_CLR_START_DET 0x80013064 -#pragma Aux_register(0x80013064, name=>"io_i2c_slv0_clr_start_det") - -// User extension aux register io_i2c_slv0_enable -#define AR_IO_I2C_SLV0_ENABLE 0x8001306c -#pragma Aux_register(0x8001306c, name=>"io_i2c_slv0_enable") - -// User extension aux register io_i2c_slv0_status -#define AR_IO_I2C_SLV0_STATUS 0x80013070 -#pragma Aux_register(0x80013070, name=>"io_i2c_slv0_status") - -// User extension aux register io_i2c_slv0_txflr -#define AR_IO_I2C_SLV0_TXFLR 0x80013074 -#pragma Aux_register(0x80013074, name=>"io_i2c_slv0_txflr") - -// User extension aux register io_i2c_slv0_rxflr -#define AR_IO_I2C_SLV0_RXFLR 0x80013078 -#pragma Aux_register(0x80013078, name=>"io_i2c_slv0_rxflr") - -// User extension aux register io_i2c_slv0_sda_hold -#define AR_IO_I2C_SLV0_SDA_HOLD 0x8001307c -#pragma Aux_register(0x8001307c, name=>"io_i2c_slv0_sda_hold") - -// User extension aux register io_i2c_slv0_tx_abrt_source -#define AR_IO_I2C_SLV0_TX_ABRT_SOURCE 0x80013080 -#pragma Aux_register(0x80013080, name=>"io_i2c_slv0_tx_abrt_source") - -// User extension aux register io_i2c_slv0_sda_setup -#define AR_IO_I2C_SLV0_SDA_SETUP 0x80013094 -#pragma Aux_register(0x80013094, name=>"io_i2c_slv0_sda_setup") - -// User extension aux register io_i2c_slv0_enable_status -#define AR_IO_I2C_SLV0_ENABLE_STATUS 0x8001309c -#pragma Aux_register(0x8001309c, name=>"io_i2c_slv0_enable_status") - -// User extension aux register io_i2c_slv0_fs_spklen -#define AR_IO_I2C_SLV0_FS_SPKLEN 0x800130a0 -#pragma Aux_register(0x800130a0, name=>"io_i2c_slv0_fs_spklen") - -// User extension aux register io_i2c_slv0_clr_restart_det -#define AR_IO_I2C_SLV0_CLR_RESTART_DET 0x800130a8 -#pragma Aux_register(0x800130a8, name=>"io_i2c_slv0_clr_restart_det") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_PWM0_PRESENT 1 - -// User extension aux register io_pwm0_clken -#define AR_IO_PWM0_CLKEN 0x8001d020 -#pragma Aux_register(0x8001d020, name=>"io_pwm0_clken") - -// User extension aux register io_pwm0_ctrl -#define AR_IO_PWM0_CTRL 0x8001d000 -#pragma Aux_register(0x8001d000, name=>"io_pwm0_ctrl") - -// User extension aux register io_pwm0_chn_config -#define AR_IO_PWM0_CHN_CONFIG 0x8001d001 -#pragma Aux_register(0x8001d001, name=>"io_pwm0_chn_config") - -// User extension aux register io_pwm0_trigger -#define AR_IO_PWM0_TRIGGER 0x8001d002 -#pragma Aux_register(0x8001d002, name=>"io_pwm0_trigger") - -// User extension aux register io_pwm0_fault -#define AR_IO_PWM0_FAULT 0x8001d003 -#pragma Aux_register(0x8001d003, name=>"io_pwm0_fault") - -// User extension aux register io_pwm0_events -#define AR_IO_PWM0_EVENTS 0x8001d004 -#pragma Aux_register(0x8001d004, name=>"io_pwm0_events") - -// User extension aux register io_pwm0_intctrl -#define AR_IO_PWM0_INTCTRL 0x8001d005 -#pragma Aux_register(0x8001d005, name=>"io_pwm0_intctrl") - -// User extension aux register io_pwm0_intstat -#define AR_IO_PWM0_INTSTAT 0x8001d006 -#pragma Aux_register(0x8001d006, name=>"io_pwm0_intstat") - -// User extension aux register io_pwm0_intclr -#define AR_IO_PWM0_INTCLR 0x8001d007 -#pragma Aux_register(0x8001d007, name=>"io_pwm0_intclr") - -// User extension aux register io_pwm0_threshold_01 -#define AR_IO_PWM0_THRESHOLD_01 0x8001d008 -#pragma Aux_register(0x8001d008, name=>"io_pwm0_threshold_01") - -// User extension aux register io_pwm0_threshold_23 -#define AR_IO_PWM0_THRESHOLD_23 0x8001d009 -#pragma Aux_register(0x8001d009, name=>"io_pwm0_threshold_23") - -// User extension aux register io_pwm0_threshold_45 -#define AR_IO_PWM0_THRESHOLD_45 0x8001d00a -#pragma Aux_register(0x8001d00a, name=>"io_pwm0_threshold_45") - -// User extension aux register io_pwm0_threshold_67 -#define AR_IO_PWM0_THRESHOLD_67 0x8001d00b -#pragma Aux_register(0x8001d00b, name=>"io_pwm0_threshold_67") - -// User extension aux register io_pwm0_deadzone_01 -#define AR_IO_PWM0_DEADZONE_01 0x8001d00c -#pragma Aux_register(0x8001d00c, name=>"io_pwm0_deadzone_01") - -// User extension aux register io_pwm0_deadzone_23 -#define AR_IO_PWM0_DEADZONE_23 0x8001d00d -#pragma Aux_register(0x8001d00d, name=>"io_pwm0_deadzone_23") - -// User extension aux register io_pwm0_deadzone_45 -#define AR_IO_PWM0_DEADZONE_45 0x8001d00e -#pragma Aux_register(0x8001d00e, name=>"io_pwm0_deadzone_45") - -// User extension aux register io_pwm0_deadzone_67 -#define AR_IO_PWM0_DEADZONE_67 0x8001d00f -#pragma Aux_register(0x8001d00f, name=>"io_pwm0_deadzone_67") - -// User extension aux register io_pwm0_timer_max -#define AR_IO_PWM0_TIMER_MAX 0x8001d010 -#pragma Aux_register(0x8001d010, name=>"io_pwm0_timer_max") - -// User extension aux register io_pwm0_nperiods -#define AR_IO_PWM0_NPERIODS 0x8001d011 -#pragma Aux_register(0x8001d011, name=>"io_pwm0_nperiods") - -// User extension aux register io_pwm0_clk_div -#define AR_IO_PWM0_CLK_DIV 0x8001d012 -#pragma Aux_register(0x8001d012, name=>"io_pwm0_clk_div") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_PWM1_PRESENT 1 - -// User extension aux register io_pwm1_clken -#define AR_IO_PWM1_CLKEN 0x8001d120 -#pragma Aux_register(0x8001d120, name=>"io_pwm1_clken") - -// User extension aux register io_pwm1_ctrl -#define AR_IO_PWM1_CTRL 0x8001d100 -#pragma Aux_register(0x8001d100, name=>"io_pwm1_ctrl") - -// User extension aux register io_pwm1_chn_config -#define AR_IO_PWM1_CHN_CONFIG 0x8001d101 -#pragma Aux_register(0x8001d101, name=>"io_pwm1_chn_config") - -// User extension aux register io_pwm1_trigger -#define AR_IO_PWM1_TRIGGER 0x8001d102 -#pragma Aux_register(0x8001d102, name=>"io_pwm1_trigger") - -// User extension aux register io_pwm1_fault -#define AR_IO_PWM1_FAULT 0x8001d103 -#pragma Aux_register(0x8001d103, name=>"io_pwm1_fault") - -// User extension aux register io_pwm1_events -#define AR_IO_PWM1_EVENTS 0x8001d104 -#pragma Aux_register(0x8001d104, name=>"io_pwm1_events") - -// User extension aux register io_pwm1_intctrl -#define AR_IO_PWM1_INTCTRL 0x8001d105 -#pragma Aux_register(0x8001d105, name=>"io_pwm1_intctrl") - -// User extension aux register io_pwm1_intstat -#define AR_IO_PWM1_INTSTAT 0x8001d106 -#pragma Aux_register(0x8001d106, name=>"io_pwm1_intstat") - -// User extension aux register io_pwm1_intclr -#define AR_IO_PWM1_INTCLR 0x8001d107 -#pragma Aux_register(0x8001d107, name=>"io_pwm1_intclr") - -// User extension aux register io_pwm1_threshold_01 -#define AR_IO_PWM1_THRESHOLD_01 0x8001d108 -#pragma Aux_register(0x8001d108, name=>"io_pwm1_threshold_01") - -// User extension aux register io_pwm1_threshold_23 -#define AR_IO_PWM1_THRESHOLD_23 0x8001d109 -#pragma Aux_register(0x8001d109, name=>"io_pwm1_threshold_23") - -// User extension aux register io_pwm1_threshold_45 -#define AR_IO_PWM1_THRESHOLD_45 0x8001d10a -#pragma Aux_register(0x8001d10a, name=>"io_pwm1_threshold_45") - -// User extension aux register io_pwm1_threshold_67 -#define AR_IO_PWM1_THRESHOLD_67 0x8001d10b -#pragma Aux_register(0x8001d10b, name=>"io_pwm1_threshold_67") - -// User extension aux register io_pwm1_deadzone_01 -#define AR_IO_PWM1_DEADZONE_01 0x8001d10c -#pragma Aux_register(0x8001d10c, name=>"io_pwm1_deadzone_01") - -// User extension aux register io_pwm1_deadzone_23 -#define AR_IO_PWM1_DEADZONE_23 0x8001d10d -#pragma Aux_register(0x8001d10d, name=>"io_pwm1_deadzone_23") - -// User extension aux register io_pwm1_deadzone_45 -#define AR_IO_PWM1_DEADZONE_45 0x8001d10e -#pragma Aux_register(0x8001d10e, name=>"io_pwm1_deadzone_45") - -// User extension aux register io_pwm1_deadzone_67 -#define AR_IO_PWM1_DEADZONE_67 0x8001d10f -#pragma Aux_register(0x8001d10f, name=>"io_pwm1_deadzone_67") - -// User extension aux register io_pwm1_timer_max -#define AR_IO_PWM1_TIMER_MAX 0x8001d110 -#pragma Aux_register(0x8001d110, name=>"io_pwm1_timer_max") - -// User extension aux register io_pwm1_nperiods -#define AR_IO_PWM1_NPERIODS 0x8001d111 -#pragma Aux_register(0x8001d111, name=>"io_pwm1_nperiods") - -// User extension aux register io_pwm1_clk_div -#define AR_IO_PWM1_CLK_DIV 0x8001d112 -#pragma Aux_register(0x8001d112, name=>"io_pwm1_clk_div") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_SPI_MST0_PRESENT 1 - -// User extension aux register io_spi_mst0_ctrlr0 -#define AR_IO_SPI_MST0_CTRLR0 0x80010000 -#pragma Aux_register(0x80010000, name=>"io_spi_mst0_ctrlr0") - -// User extension aux register io_spi_mst0_ctrlr1 -#define AR_IO_SPI_MST0_CTRLR1 0x80010001 -#pragma Aux_register(0x80010001, name=>"io_spi_mst0_ctrlr1") - -// User extension aux register io_spi_mst0_spien -#define AR_IO_SPI_MST0_SPIEN 0x80010002 -#pragma Aux_register(0x80010002, name=>"io_spi_mst0_spien") - -// User extension aux register io_spi_mst0_ser -#define AR_IO_SPI_MST0_SER 0x80010004 -#pragma Aux_register(0x80010004, name=>"io_spi_mst0_ser") - -// User extension aux register io_spi_mst0_baudr -#define AR_IO_SPI_MST0_BAUDR 0x80010005 -#pragma Aux_register(0x80010005, name=>"io_spi_mst0_baudr") - -// User extension aux register io_spi_mst0_txftlr -#define AR_IO_SPI_MST0_TXFTLR 0x80010006 -#pragma Aux_register(0x80010006, name=>"io_spi_mst0_txftlr") - -// User extension aux register io_spi_mst0_rxftlr -#define AR_IO_SPI_MST0_RXFTLR 0x80010007 -#pragma Aux_register(0x80010007, name=>"io_spi_mst0_rxftlr") - -// User extension aux register io_spi_mst0_txflr -#define AR_IO_SPI_MST0_TXFLR 0x80010008 -#pragma Aux_register(0x80010008, name=>"io_spi_mst0_txflr") - -// User extension aux register io_spi_mst0_rxflr -#define AR_IO_SPI_MST0_RXFLR 0x80010009 -#pragma Aux_register(0x80010009, name=>"io_spi_mst0_rxflr") - -// User extension aux register io_spi_mst0_sr -#define AR_IO_SPI_MST0_SR 0x8001000a -#pragma Aux_register(0x8001000a, name=>"io_spi_mst0_sr") - -// User extension aux register io_spi_mst0_imr -#define AR_IO_SPI_MST0_IMR 0x8001000b -#pragma Aux_register(0x8001000b, name=>"io_spi_mst0_imr") - -// User extension aux register io_spi_mst0_isr -#define AR_IO_SPI_MST0_ISR 0x8001000c -#pragma Aux_register(0x8001000c, name=>"io_spi_mst0_isr") - -// User extension aux register io_spi_mst0_risr -#define AR_IO_SPI_MST0_RISR 0x8001000d -#pragma Aux_register(0x8001000d, name=>"io_spi_mst0_risr") - -// User extension aux register io_spi_mst0_txoicr -#define AR_IO_SPI_MST0_TXOICR 0x8001000e -#pragma Aux_register(0x8001000e, name=>"io_spi_mst0_txoicr") - -// User extension aux register io_spi_mst0_rxoicr -#define AR_IO_SPI_MST0_RXOICR 0x8001000f -#pragma Aux_register(0x8001000f, name=>"io_spi_mst0_rxoicr") - -// User extension aux register io_spi_mst0_rxuicr -#define AR_IO_SPI_MST0_RXUICR 0x80010010 -#pragma Aux_register(0x80010010, name=>"io_spi_mst0_rxuicr") - -// User extension aux register io_spi_mst0_icr -#define AR_IO_SPI_MST0_ICR 0x80010012 -#pragma Aux_register(0x80010012, name=>"io_spi_mst0_icr") - -// User extension aux register io_spi_mst0_clken -#define AR_IO_SPI_MST0_CLKEN 0x80010016 -#pragma Aux_register(0x80010016, name=>"io_spi_mst0_clken") - -// User extension aux register io_spi_mst0_dr -#define AR_IO_SPI_MST0_DR 0x80010018 -#pragma Aux_register(0x80010018, name=>"io_spi_mst0_dr") - -// User extension aux register io_spi_mst0_rx_sample_dly -#define AR_IO_SPI_MST0_RX_SAMPLE_DLY 0x8001003c -#pragma Aux_register(0x8001003c, name=>"io_spi_mst0_rx_sample_dly") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_SPI_SLV0_PRESENT 1 - -// User extension aux register io_spi_slv0_ctrlr0 -#define AR_IO_SPI_SLV0_CTRLR0 0x80011000 -#pragma Aux_register(0x80011000, name=>"io_spi_slv0_ctrlr0") - -// User extension aux register io_spi_slv0_spien -#define AR_IO_SPI_SLV0_SPIEN 0x80011002 -#pragma Aux_register(0x80011002, name=>"io_spi_slv0_spien") - -// User extension aux register io_spi_slv0_txftlr -#define AR_IO_SPI_SLV0_TXFTLR 0x80011006 -#pragma Aux_register(0x80011006, name=>"io_spi_slv0_txftlr") - -// User extension aux register io_spi_slv0_rxftlr -#define AR_IO_SPI_SLV0_RXFTLR 0x80011007 -#pragma Aux_register(0x80011007, name=>"io_spi_slv0_rxftlr") - -// User extension aux register io_spi_slv0_txflr -#define AR_IO_SPI_SLV0_TXFLR 0x80011008 -#pragma Aux_register(0x80011008, name=>"io_spi_slv0_txflr") - -// User extension aux register io_spi_slv0_rxflr -#define AR_IO_SPI_SLV0_RXFLR 0x80011009 -#pragma Aux_register(0x80011009, name=>"io_spi_slv0_rxflr") - -// User extension aux register io_spi_slv0_sr -#define AR_IO_SPI_SLV0_SR 0x8001100a -#pragma Aux_register(0x8001100a, name=>"io_spi_slv0_sr") - -// User extension aux register io_spi_slv0_imr -#define AR_IO_SPI_SLV0_IMR 0x8001100b -#pragma Aux_register(0x8001100b, name=>"io_spi_slv0_imr") - -// User extension aux register io_spi_slv0_isr -#define AR_IO_SPI_SLV0_ISR 0x8001100c -#pragma Aux_register(0x8001100c, name=>"io_spi_slv0_isr") - -// User extension aux register io_spi_slv0_risr -#define AR_IO_SPI_SLV0_RISR 0x8001100d -#pragma Aux_register(0x8001100d, name=>"io_spi_slv0_risr") - -// User extension aux register io_spi_slv0_txoicr -#define AR_IO_SPI_SLV0_TXOICR 0x8001100e -#pragma Aux_register(0x8001100e, name=>"io_spi_slv0_txoicr") - -// User extension aux register io_spi_slv0_rxoicr -#define AR_IO_SPI_SLV0_RXOICR 0x8001100f -#pragma Aux_register(0x8001100f, name=>"io_spi_slv0_rxoicr") - -// User extension aux register io_spi_slv0_rxuicr -#define AR_IO_SPI_SLV0_RXUICR 0x80011010 -#pragma Aux_register(0x80011010, name=>"io_spi_slv0_rxuicr") - -// User extension aux register io_spi_slv0_icr -#define AR_IO_SPI_SLV0_ICR 0x80011012 -#pragma Aux_register(0x80011012, name=>"io_spi_slv0_icr") - -// User extension aux register io_spi_slv0_clken -#define AR_IO_SPI_SLV0_CLKEN 0x80011016 -#pragma Aux_register(0x80011016, name=>"io_spi_slv0_clken") - -// User extension aux register io_spi_slv0_dr -#define AR_IO_SPI_SLV0_DR 0x80011018 -#pragma Aux_register(0x80011018, name=>"io_spi_slv0_dr") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_UART0_PRESENT 1 - -// User extension aux register io_uart0_clken -#define AR_IO_UART0_CLKEN 0x800140c0 -#pragma Aux_register(0x800140c0, name=>"io_uart0_clken") - -// User extension aux register io_uart0_rbr_thr_dll -#define AR_IO_UART0_RBR_THR_DLL 0x80014000 -#pragma Aux_register(0x80014000, name=>"io_uart0_rbr_thr_dll") - -// User extension aux register io_uart0_ier_dlh -#define AR_IO_UART0_IER_DLH 0x80014004 -#pragma Aux_register(0x80014004, name=>"io_uart0_ier_dlh") - -// User extension aux register io_uart0_iir_fcr -#define AR_IO_UART0_IIR_FCR 0x80014008 -#pragma Aux_register(0x80014008, name=>"io_uart0_iir_fcr") - -// User extension aux register io_uart0_lcr -#define AR_IO_UART0_LCR 0x8001400c -#pragma Aux_register(0x8001400c, name=>"io_uart0_lcr") - -// User extension aux register io_uart0_mcr -#define AR_IO_UART0_MCR 0x80014010 -#pragma Aux_register(0x80014010, name=>"io_uart0_mcr") - -// User extension aux register io_uart0_lsr -#define AR_IO_UART0_LSR 0x80014014 -#pragma Aux_register(0x80014014, name=>"io_uart0_lsr") - -// User extension aux register io_uart0_msr -#define AR_IO_UART0_MSR 0x80014018 -#pragma Aux_register(0x80014018, name=>"io_uart0_msr") - -// User extension aux register io_uart0_usr -#define AR_IO_UART0_USR 0x8001407c -#pragma Aux_register(0x8001407c, name=>"io_uart0_usr") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_UART1_PRESENT 1 - -// User extension aux register io_uart1_clken -#define AR_IO_UART1_CLKEN 0x800141c0 -#pragma Aux_register(0x800141c0, name=>"io_uart1_clken") - -// User extension aux register io_uart1_rbr_thr_dll -#define AR_IO_UART1_RBR_THR_DLL 0x80014100 -#pragma Aux_register(0x80014100, name=>"io_uart1_rbr_thr_dll") - -// User extension aux register io_uart1_ier_dlh -#define AR_IO_UART1_IER_DLH 0x80014104 -#pragma Aux_register(0x80014104, name=>"io_uart1_ier_dlh") - -// User extension aux register io_uart1_iir_fcr -#define AR_IO_UART1_IIR_FCR 0x80014108 -#pragma Aux_register(0x80014108, name=>"io_uart1_iir_fcr") - -// User extension aux register io_uart1_lcr -#define AR_IO_UART1_LCR 0x8001410c -#pragma Aux_register(0x8001410c, name=>"io_uart1_lcr") - -// User extension aux register io_uart1_mcr -#define AR_IO_UART1_MCR 0x80014110 -#pragma Aux_register(0x80014110, name=>"io_uart1_mcr") - -// User extension aux register io_uart1_lsr -#define AR_IO_UART1_LSR 0x80014114 -#pragma Aux_register(0x80014114, name=>"io_uart1_lsr") - -// User extension aux register io_uart1_msr -#define AR_IO_UART1_MSR 0x80014118 -#pragma Aux_register(0x80014118, name=>"io_uart1_msr") - -// User extension aux register io_uart1_usr -#define AR_IO_UART1_USR 0x8001417c -#pragma Aux_register(0x8001417c, name=>"io_uart1_usr") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_UART2_PRESENT 1 - -// User extension aux register io_uart2_clken -#define AR_IO_UART2_CLKEN 0x800142c0 -#pragma Aux_register(0x800142c0, name=>"io_uart2_clken") - -// User extension aux register io_uart2_rbr_thr_dll -#define AR_IO_UART2_RBR_THR_DLL 0x80014200 -#pragma Aux_register(0x80014200, name=>"io_uart2_rbr_thr_dll") - -// User extension aux register io_uart2_ier_dlh -#define AR_IO_UART2_IER_DLH 0x80014204 -#pragma Aux_register(0x80014204, name=>"io_uart2_ier_dlh") - -// User extension aux register io_uart2_iir_fcr -#define AR_IO_UART2_IIR_FCR 0x80014208 -#pragma Aux_register(0x80014208, name=>"io_uart2_iir_fcr") - -// User extension aux register io_uart2_lcr -#define AR_IO_UART2_LCR 0x8001420c -#pragma Aux_register(0x8001420c, name=>"io_uart2_lcr") - -// User extension aux register io_uart2_mcr -#define AR_IO_UART2_MCR 0x80014210 -#pragma Aux_register(0x80014210, name=>"io_uart2_mcr") - -// User extension aux register io_uart2_lsr -#define AR_IO_UART2_LSR 0x80014214 -#pragma Aux_register(0x80014214, name=>"io_uart2_lsr") - -// User extension aux register io_uart2_msr -#define AR_IO_UART2_MSR 0x80014218 -#pragma Aux_register(0x80014218, name=>"io_uart2_msr") - -// User extension aux register io_uart2_usr -#define AR_IO_UART2_USR 0x8001427c -#pragma Aux_register(0x8001427c, name=>"io_uart2_usr") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_UART3_PRESENT 1 - -// User extension aux register io_uart3_clken -#define AR_IO_UART3_CLKEN 0x800143c0 -#pragma Aux_register(0x800143c0, name=>"io_uart3_clken") - -// User extension aux register io_uart3_rbr_thr_dll -#define AR_IO_UART3_RBR_THR_DLL 0x80014300 -#pragma Aux_register(0x80014300, name=>"io_uart3_rbr_thr_dll") - -// User extension aux register io_uart3_ier_dlh -#define AR_IO_UART3_IER_DLH 0x80014304 -#pragma Aux_register(0x80014304, name=>"io_uart3_ier_dlh") - -// User extension aux register io_uart3_iir_fcr -#define AR_IO_UART3_IIR_FCR 0x80014308 -#pragma Aux_register(0x80014308, name=>"io_uart3_iir_fcr") - -// User extension aux register io_uart3_lcr -#define AR_IO_UART3_LCR 0x8001430c -#pragma Aux_register(0x8001430c, name=>"io_uart3_lcr") - -// User extension aux register io_uart3_mcr -#define AR_IO_UART3_MCR 0x80014310 -#pragma Aux_register(0x80014310, name=>"io_uart3_mcr") - -// User extension aux register io_uart3_lsr -#define AR_IO_UART3_LSR 0x80014314 -#pragma Aux_register(0x80014314, name=>"io_uart3_lsr") - -// User extension aux register io_uart3_msr -#define AR_IO_UART3_MSR 0x80014318 -#pragma Aux_register(0x80014318, name=>"io_uart3_msr") - -// User extension aux register io_uart3_usr -#define AR_IO_UART3_USR 0x8001437c -#pragma Aux_register(0x8001437c, name=>"io_uart3_usr") -#define APEX_COM_ARC_HARDWARE_SCSS_SUBSYS_BCR_PRESENT 1 - -// User extension aux register SUBSYS_BUILD -#define AR_SUBSYS_BUILD 0xf0 -#pragma Aux_register(0xf0, name=>"SUBSYS_BUILD") - -// User extension aux register SUBSYS_DSP_0_BUILD -#define AR_SUBSYS_DSP_0_BUILD 0xa00 -#pragma Aux_register(0xa00, name=>"SUBSYS_DSP_0_BUILD") - -// User extension aux register SUBSYS_DSP_0_CONFIG -#define AR_SUBSYS_DSP_0_CONFIG 0xa02 -#pragma Aux_register(0xa02, name=>"SUBSYS_DSP_0_CONFIG") - -// User extension aux register SUBSYS_IO_0_BUILD -#define AR_SUBSYS_IO_0_BUILD 0xa04 -#pragma Aux_register(0xa04, name=>"SUBSYS_IO_0_BUILD") - -// User extension aux register SUBSYS_IO_1_BUILD -#define AR_SUBSYS_IO_1_BUILD 0xa05 -#pragma Aux_register(0xa05, name=>"SUBSYS_IO_1_BUILD") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_SPI_MST1_PRESENT 1 - -// User extension aux register io_spi_mst1_ctrlr0 -#define AR_IO_SPI_MST1_CTRLR0 0x80010100 -#pragma Aux_register(0x80010100, name=>"io_spi_mst1_ctrlr0") - -// User extension aux register io_spi_mst1_ctrlr1 -#define AR_IO_SPI_MST1_CTRLR1 0x80010101 -#pragma Aux_register(0x80010101, name=>"io_spi_mst1_ctrlr1") - -// User extension aux register io_spi_mst1_spien -#define AR_IO_SPI_MST1_SPIEN 0x80010102 -#pragma Aux_register(0x80010102, name=>"io_spi_mst1_spien") - -// User extension aux register io_spi_mst1_ser -#define AR_IO_SPI_MST1_SER 0x80010104 -#pragma Aux_register(0x80010104, name=>"io_spi_mst1_ser") - -// User extension aux register io_spi_mst1_baudr -#define AR_IO_SPI_MST1_BAUDR 0x80010105 -#pragma Aux_register(0x80010105, name=>"io_spi_mst1_baudr") - -// User extension aux register io_spi_mst1_txftlr -#define AR_IO_SPI_MST1_TXFTLR 0x80010106 -#pragma Aux_register(0x80010106, name=>"io_spi_mst1_txftlr") - -// User extension aux register io_spi_mst1_rxftlr -#define AR_IO_SPI_MST1_RXFTLR 0x80010107 -#pragma Aux_register(0x80010107, name=>"io_spi_mst1_rxftlr") - -// User extension aux register io_spi_mst1_txflr -#define AR_IO_SPI_MST1_TXFLR 0x80010108 -#pragma Aux_register(0x80010108, name=>"io_spi_mst1_txflr") - -// User extension aux register io_spi_mst1_rxflr -#define AR_IO_SPI_MST1_RXFLR 0x80010109 -#pragma Aux_register(0x80010109, name=>"io_spi_mst1_rxflr") - -// User extension aux register io_spi_mst1_sr -#define AR_IO_SPI_MST1_SR 0x8001010a -#pragma Aux_register(0x8001010a, name=>"io_spi_mst1_sr") - -// User extension aux register io_spi_mst1_imr -#define AR_IO_SPI_MST1_IMR 0x8001010b -#pragma Aux_register(0x8001010b, name=>"io_spi_mst1_imr") - -// User extension aux register io_spi_mst1_isr -#define AR_IO_SPI_MST1_ISR 0x8001010c -#pragma Aux_register(0x8001010c, name=>"io_spi_mst1_isr") - -// User extension aux register io_spi_mst1_risr -#define AR_IO_SPI_MST1_RISR 0x8001010d -#pragma Aux_register(0x8001010d, name=>"io_spi_mst1_risr") - -// User extension aux register io_spi_mst1_txoicr -#define AR_IO_SPI_MST1_TXOICR 0x8001010e -#pragma Aux_register(0x8001010e, name=>"io_spi_mst1_txoicr") - -// User extension aux register io_spi_mst1_rxoicr -#define AR_IO_SPI_MST1_RXOICR 0x8001010f -#pragma Aux_register(0x8001010f, name=>"io_spi_mst1_rxoicr") - -// User extension aux register io_spi_mst1_rxuicr -#define AR_IO_SPI_MST1_RXUICR 0x80010110 -#pragma Aux_register(0x80010110, name=>"io_spi_mst1_rxuicr") - -// User extension aux register io_spi_mst1_icr -#define AR_IO_SPI_MST1_ICR 0x80010112 -#pragma Aux_register(0x80010112, name=>"io_spi_mst1_icr") - -// User extension aux register io_spi_mst1_clken -#define AR_IO_SPI_MST1_CLKEN 0x80010116 -#pragma Aux_register(0x80010116, name=>"io_spi_mst1_clken") - -// User extension aux register io_spi_mst1_dr -#define AR_IO_SPI_MST1_DR 0x80010118 -#pragma Aux_register(0x80010118, name=>"io_spi_mst1_dr") - -// User extension aux register io_spi_mst1_rx_sample_dly -#define AR_IO_SPI_MST1_RX_SAMPLE_DLY 0x8001013c -#pragma Aux_register(0x8001013c, name=>"io_spi_mst1_rx_sample_dly") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_SPI_MST2_PRESENT 1 - -// User extension aux register io_spi_mst2_ctrlr0 -#define AR_IO_SPI_MST2_CTRLR0 0x80010200 -#pragma Aux_register(0x80010200, name=>"io_spi_mst2_ctrlr0") - -// User extension aux register io_spi_mst2_ctrlr1 -#define AR_IO_SPI_MST2_CTRLR1 0x80010201 -#pragma Aux_register(0x80010201, name=>"io_spi_mst2_ctrlr1") - -// User extension aux register io_spi_mst2_spien -#define AR_IO_SPI_MST2_SPIEN 0x80010202 -#pragma Aux_register(0x80010202, name=>"io_spi_mst2_spien") - -// User extension aux register io_spi_mst2_ser -#define AR_IO_SPI_MST2_SER 0x80010204 -#pragma Aux_register(0x80010204, name=>"io_spi_mst2_ser") - -// User extension aux register io_spi_mst2_baudr -#define AR_IO_SPI_MST2_BAUDR 0x80010205 -#pragma Aux_register(0x80010205, name=>"io_spi_mst2_baudr") - -// User extension aux register io_spi_mst2_txftlr -#define AR_IO_SPI_MST2_TXFTLR 0x80010206 -#pragma Aux_register(0x80010206, name=>"io_spi_mst2_txftlr") - -// User extension aux register io_spi_mst2_rxftlr -#define AR_IO_SPI_MST2_RXFTLR 0x80010207 -#pragma Aux_register(0x80010207, name=>"io_spi_mst2_rxftlr") - -// User extension aux register io_spi_mst2_txflr -#define AR_IO_SPI_MST2_TXFLR 0x80010208 -#pragma Aux_register(0x80010208, name=>"io_spi_mst2_txflr") - -// User extension aux register io_spi_mst2_rxflr -#define AR_IO_SPI_MST2_RXFLR 0x80010209 -#pragma Aux_register(0x80010209, name=>"io_spi_mst2_rxflr") - -// User extension aux register io_spi_mst2_sr -#define AR_IO_SPI_MST2_SR 0x8001020a -#pragma Aux_register(0x8001020a, name=>"io_spi_mst2_sr") - -// User extension aux register io_spi_mst2_imr -#define AR_IO_SPI_MST2_IMR 0x8001020b -#pragma Aux_register(0x8001020b, name=>"io_spi_mst2_imr") - -// User extension aux register io_spi_mst2_isr -#define AR_IO_SPI_MST2_ISR 0x8001020c -#pragma Aux_register(0x8001020c, name=>"io_spi_mst2_isr") - -// User extension aux register io_spi_mst2_risr -#define AR_IO_SPI_MST2_RISR 0x8001020d -#pragma Aux_register(0x8001020d, name=>"io_spi_mst2_risr") - -// User extension aux register io_spi_mst2_txoicr -#define AR_IO_SPI_MST2_TXOICR 0x8001020e -#pragma Aux_register(0x8001020e, name=>"io_spi_mst2_txoicr") - -// User extension aux register io_spi_mst2_rxoicr -#define AR_IO_SPI_MST2_RXOICR 0x8001020f -#pragma Aux_register(0x8001020f, name=>"io_spi_mst2_rxoicr") - -// User extension aux register io_spi_mst2_rxuicr -#define AR_IO_SPI_MST2_RXUICR 0x80010210 -#pragma Aux_register(0x80010210, name=>"io_spi_mst2_rxuicr") - -// User extension aux register io_spi_mst2_icr -#define AR_IO_SPI_MST2_ICR 0x80010212 -#pragma Aux_register(0x80010212, name=>"io_spi_mst2_icr") - -// User extension aux register io_spi_mst2_clken -#define AR_IO_SPI_MST2_CLKEN 0x80010216 -#pragma Aux_register(0x80010216, name=>"io_spi_mst2_clken") - -// User extension aux register io_spi_mst2_dr -#define AR_IO_SPI_MST2_DR 0x80010218 -#pragma Aux_register(0x80010218, name=>"io_spi_mst2_dr") - -// User extension aux register io_spi_mst2_rx_sample_dly -#define AR_IO_SPI_MST2_RX_SAMPLE_DLY 0x8001023c -#pragma Aux_register(0x8001023c, name=>"io_spi_mst2_rx_sample_dly") -#define APEX_COM_ARC_HARDWARE_FLOATING_POINT_UNIT_FPU_PRESENT 1 - -// User extension aux register fpu_build -#define AR_FPU_BUILD 0xc8 -#pragma Aux_register(0xc8, name=>"fpu_build") - -// User extension aux register fpu_ctrl -#define AR_FPU_CTRL 0x300 -#pragma Aux_register(0x300, name=>"fpu_ctrl") - -// User extension aux register fpu_status -#define AR_FPU_STATUS 0x301 -#pragma Aux_register(0x301, name=>"fpu_status") - -// User extension instruction fsmadd -extern long fsmadd(long,long); -#pragma intrinsic(fsmadd,opcode=>6,sub_opcode=>5, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fsmsub -extern long fsmsub(long,long); -#pragma intrinsic(fsmsub,opcode=>6,sub_opcode=>6, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fsmul -extern long fsmul(long,long); -#pragma intrinsic(fsmul,opcode=>6,sub_opcode=>0, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fsadd -extern long fsadd(long,long); -#pragma intrinsic(fsadd,opcode=>6,sub_opcode=>1, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fssub -extern long fssub(long,long); -#pragma intrinsic(fssub,opcode=>6,sub_opcode=>2, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fcvt32 -extern long fcvt32(long,long); -#pragma intrinsic(fcvt32,opcode=>6,sub_opcode=>8, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fsdiv -extern long fsdiv(long,long); -#pragma intrinsic(fsdiv,opcode=>6,sub_opcode=>7, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fscmp -extern long fscmp(long,long); -#pragma intrinsic(fscmp,opcode=>6,sub_opcode=>3, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fscmp -extern long fscmp_f(long,long); -#pragma intrinsic(fscmp_f,opcode=>6,sub_opcode=>3, set_flags => 1, flags => "zncv", effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fscmpf -extern long fscmpf(long,long); -#pragma intrinsic(fscmpf,opcode=>6,sub_opcode=>4, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fscmpf -extern long fscmpf_f(long,long); -#pragma intrinsic(fscmpf_f,opcode=>6,sub_opcode=>4, set_flags => 1, flags => "zncv", effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fssqrt -extern long fssqrt(long); -#pragma intrinsic(fssqrt,opcode=>6,sub_opcode=>0, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") -#define APEX_COM_ARC_HARDWARE_FLOATING_POINT_UNIT_FPU_DP_ASSIST_PRESENT 1 - -// User extension aux register aux_dpfp1l -#define AR_AUX_DPFP1L 0x302 -#pragma Aux_register(0x302, name=>"aux_dpfp1l") - -// User extension aux register aux_dpfp1h -#define AR_AUX_DPFP1H 0x303 -#pragma Aux_register(0x303, name=>"aux_dpfp1h") - -// User extension aux register aux_dpfp2l -#define AR_AUX_DPFP2L 0x304 -#pragma Aux_register(0x304, name=>"aux_dpfp2l") - -// User extension aux register aux_dpfp2h -#define AR_AUX_DPFP2H 0x305 -#pragma Aux_register(0x305, name=>"aux_dpfp2h") - -// User extension instruction dmulh11 -extern long dmulh11(long,long); -#pragma intrinsic(dmulh11,opcode=>6,sub_opcode=>48,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh11 -extern long dmulh11_f(long,long); -#pragma intrinsic(dmulh11_f,opcode=>6,sub_opcode=>48, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh12 -extern long dmulh12(long,long); -#pragma intrinsic(dmulh12,opcode=>6,sub_opcode=>49,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh12 -extern long dmulh12_f(long,long); -#pragma intrinsic(dmulh12_f,opcode=>6,sub_opcode=>49, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh21 -extern long dmulh21(long,long); -#pragma intrinsic(dmulh21,opcode=>6,sub_opcode=>50,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh21 -extern long dmulh21_f(long,long); -#pragma intrinsic(dmulh21_f,opcode=>6,sub_opcode=>50, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh22 -extern long dmulh22(long,long); -#pragma intrinsic(dmulh22,opcode=>6,sub_opcode=>51,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh22 -extern long dmulh22_f(long,long); -#pragma intrinsic(dmulh22_f,opcode=>6,sub_opcode=>51, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh11 -extern long daddh11(long,long); -#pragma intrinsic(daddh11,opcode=>6,sub_opcode=>52,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh11 -extern long daddh11_f(long,long); -#pragma intrinsic(daddh11_f,opcode=>6,sub_opcode=>52, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh12 -extern long daddh12(long,long); -#pragma intrinsic(daddh12,opcode=>6,sub_opcode=>53,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh12 -extern long daddh12_f(long,long); -#pragma intrinsic(daddh12_f,opcode=>6,sub_opcode=>53, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh21 -extern long daddh21(long,long); -#pragma intrinsic(daddh21,opcode=>6,sub_opcode=>54,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh21 -extern long daddh21_f(long,long); -#pragma intrinsic(daddh21_f,opcode=>6,sub_opcode=>54, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh22 -extern long daddh22(long,long); -#pragma intrinsic(daddh22,opcode=>6,sub_opcode=>55,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh22 -extern long daddh22_f(long,long); -#pragma intrinsic(daddh22_f,opcode=>6,sub_opcode=>55, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh11 -extern long dsubh11(long,long); -#pragma intrinsic(dsubh11,opcode=>6,sub_opcode=>56,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh11 -extern long dsubh11_f(long,long); -#pragma intrinsic(dsubh11_f,opcode=>6,sub_opcode=>56, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh12 -extern long dsubh12(long,long); -#pragma intrinsic(dsubh12,opcode=>6,sub_opcode=>57,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh12 -extern long dsubh12_f(long,long); -#pragma intrinsic(dsubh12_f,opcode=>6,sub_opcode=>57, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh21 -extern long dsubh21(long,long); -#pragma intrinsic(dsubh21,opcode=>6,sub_opcode=>58,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh21 -extern long dsubh21_f(long,long); -#pragma intrinsic(dsubh21_f,opcode=>6,sub_opcode=>58, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh22 -extern long dsubh22(long,long); -#pragma intrinsic(dsubh22,opcode=>6,sub_opcode=>59,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh22 -extern long dsubh22_f(long,long); -#pragma intrinsic(dsubh22_f,opcode=>6,sub_opcode=>59, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dexcl1 -extern long dexcl1(long,long); -#pragma intrinsic(dexcl1,opcode=>6,sub_opcode=>60, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dexcl2 -extern long dexcl2(long,long); -#pragma intrinsic(dexcl2,opcode=>6,sub_opcode=>61, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - - -#endif - - -]]> - - - - - - diff --git a/board/emsdp/rev1/configs/em7d_esp_dfss/apexextensions.h b/board/emsdp/rev1/configs/em7d_esp_dfss/apexextensions.h deleted file mode 100644 index 943fecd72..000000000 --- a/board/emsdp/rev1/configs/em7d_esp_dfss/apexextensions.h +++ /dev/null @@ -1,1544 +0,0 @@ - -/* **** DO NOT EDIT - this file is generated by ARChitect2 **** - * - * Description: Header file declaring the compiler extensions for apex components - */ - -#ifndef _apexextensions_H_ -#define _apexextensions_H_ - -// User extension instruction - dsp_cos -extern long dsp_cos(long); -#pragma intrinsic(dsp_cos, opcode => 0x07, sub_opcode => 0x1E , latency_cycles => 8) - -// User extension instruction - dsp_sin -extern long dsp_sin(long); -#pragma intrinsic(dsp_sin, opcode => 0x07, sub_opcode => 0x1F , latency_cycles => 8) - -// User extension instruction - dsp_tan -extern long dsp_tan(long); -#pragma intrinsic(dsp_tan, opcode => 0x07, sub_opcode => 0x22 , latency_cycles => 11) - -// User extension instruction - dsp_acos -extern long dsp_acos(long); -#pragma intrinsic(dsp_acos, opcode => 0x07, sub_opcode => 0x23 , latency_cycles => 31) - -// User extension instruction - dsp_asin -extern long dsp_asin(long); -#pragma intrinsic(dsp_asin, opcode => 0x07, sub_opcode => 0x24 , latency_cycles => 31) - -// User extension instruction - dsp_atan -extern long dsp_atan(long); -#pragma intrinsic(dsp_atan, opcode => 0x07, sub_opcode => 0x25 , latency_cycles => 13) - -// User extension instruction - dsp_sqrt -extern long dsp_sqrt(long); -#pragma intrinsic(dsp_sqrt, opcode => 0x07, sub_opcode => 0x20 , latency_cycles => 31) - -// User extension instruction - dsp_sqrt15 -extern long dsp_sqrt15(long); -#pragma intrinsic(dsp_sqrt15, opcode => 0x07, sub_opcode => 0x21 , latency_cycles => 15) - -#define APEX_COM_ARC_HARDWARE_DFSS_DSP_TRIG_PRESENT 1 -#define APEX_COM_ARC_HARDWARE_DFSS_IO_GPIO0_PRESENT 1 - -// User extension aux register io_gpio0_debounce -#define AR_IO_GPIO0_DEBOUNCE 0x80017048 -#pragma Aux_register(0x80017048, name=>"io_gpio0_debounce") - -// User extension aux register io_gpio0_clken -#define AR_IO_GPIO0_CLKEN 0x80017080 -#pragma Aux_register(0x80017080, name=>"io_gpio0_clken") - -// User extension aux register io_gpio0_swporta_dr -#define AR_IO_GPIO0_SWPORTA_DR 0x80017000 -#pragma Aux_register(0x80017000, name=>"io_gpio0_swporta_dr") - -// User extension aux register io_gpio0_swporta_ddr -#define AR_IO_GPIO0_SWPORTA_DDR 0x80017004 -#pragma Aux_register(0x80017004, name=>"io_gpio0_swporta_ddr") - -// User extension aux register io_gpio0_inten -#define AR_IO_GPIO0_INTEN 0x80017030 -#pragma Aux_register(0x80017030, name=>"io_gpio0_inten") - -// User extension aux register io_gpio0_intmask -#define AR_IO_GPIO0_INTMASK 0x80017034 -#pragma Aux_register(0x80017034, name=>"io_gpio0_intmask") - -// User extension aux register io_gpio0_inttype_level -#define AR_IO_GPIO0_INTTYPE_LEVEL 0x80017038 -#pragma Aux_register(0x80017038, name=>"io_gpio0_inttype_level") - -// User extension aux register io_gpio0_int_polarity -#define AR_IO_GPIO0_INT_POLARITY 0x8001703c -#pragma Aux_register(0x8001703c, name=>"io_gpio0_int_polarity") - -// User extension aux register io_gpio0_intstatus -#define AR_IO_GPIO0_INTSTATUS 0x80017040 -#pragma Aux_register(0x80017040, name=>"io_gpio0_intstatus") - -// User extension aux register io_gpio0_raw_intstatus -#define AR_IO_GPIO0_RAW_INTSTATUS 0x80017044 -#pragma Aux_register(0x80017044, name=>"io_gpio0_raw_intstatus") - -// User extension aux register io_gpio0_porta_eoi -#define AR_IO_GPIO0_PORTA_EOI 0x8001704c -#pragma Aux_register(0x8001704c, name=>"io_gpio0_porta_eoi") - -// User extension aux register io_gpio0_ext_porta -#define AR_IO_GPIO0_EXT_PORTA 0x80017050 -#pragma Aux_register(0x80017050, name=>"io_gpio0_ext_porta") - -// User extension aux register io_gpio0_ls_sync -#define AR_IO_GPIO0_LS_SYNC 0x80017060 -#pragma Aux_register(0x80017060, name=>"io_gpio0_ls_sync") - -// User extension aux register io_gpio0_int_bothedge -#define AR_IO_GPIO0_INT_BOTHEDGE 0x80017068 -#pragma Aux_register(0x80017068, name=>"io_gpio0_int_bothedge") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2C_MST0_PRESENT 1 - -// User extension aux register io_i2c_mst0_clken -#define AR_IO_I2C_MST0_CLKEN 0x800120c0 -#pragma Aux_register(0x800120c0, name=>"io_i2c_mst0_clken") - -// User extension aux register io_i2c_mst0_con -#define AR_IO_I2C_MST0_CON 0x80012000 -#pragma Aux_register(0x80012000, name=>"io_i2c_mst0_con") - -// User extension aux register io_i2c_mst0_tar -#define AR_IO_I2C_MST0_TAR 0x80012004 -#pragma Aux_register(0x80012004, name=>"io_i2c_mst0_tar") - -// User extension aux register io_i2c_mst0_data_cmd -#define AR_IO_I2C_MST0_DATA_CMD 0x80012010 -#pragma Aux_register(0x80012010, name=>"io_i2c_mst0_data_cmd") - -// User extension aux register io_i2c_mst0_ss_scl_hcnt -#define AR_IO_I2C_MST0_SS_SCL_HCNT 0x80012014 -#pragma Aux_register(0x80012014, name=>"io_i2c_mst0_ss_scl_hcnt") - -// User extension aux register io_i2c_mst0_ss_scl_lcnt -#define AR_IO_I2C_MST0_SS_SCL_LCNT 0x80012018 -#pragma Aux_register(0x80012018, name=>"io_i2c_mst0_ss_scl_lcnt") - -// User extension aux register io_i2c_mst0_fs_scl_hcnt -#define AR_IO_I2C_MST0_FS_SCL_HCNT 0x8001201c -#pragma Aux_register(0x8001201c, name=>"io_i2c_mst0_fs_scl_hcnt") - -// User extension aux register io_i2c_mst0_fs_scl_lcnt -#define AR_IO_I2C_MST0_FS_SCL_LCNT 0x80012020 -#pragma Aux_register(0x80012020, name=>"io_i2c_mst0_fs_scl_lcnt") - -// User extension aux register io_i2c_mst0_intr_stat -#define AR_IO_I2C_MST0_INTR_STAT 0x8001202c -#pragma Aux_register(0x8001202c, name=>"io_i2c_mst0_intr_stat") - -// User extension aux register io_i2c_mst0_intr_mask -#define AR_IO_I2C_MST0_INTR_MASK 0x80012030 -#pragma Aux_register(0x80012030, name=>"io_i2c_mst0_intr_mask") - -// User extension aux register io_i2c_mst0_raw_intr_stat -#define AR_IO_I2C_MST0_RAW_INTR_STAT 0x80012034 -#pragma Aux_register(0x80012034, name=>"io_i2c_mst0_raw_intr_stat") - -// User extension aux register io_i2c_mst0_rx_tl -#define AR_IO_I2C_MST0_RX_TL 0x80012038 -#pragma Aux_register(0x80012038, name=>"io_i2c_mst0_rx_tl") - -// User extension aux register io_i2c_mst0_tx_tl -#define AR_IO_I2C_MST0_TX_TL 0x8001203c -#pragma Aux_register(0x8001203c, name=>"io_i2c_mst0_tx_tl") - -// User extension aux register io_i2c_mst0_clr_intr -#define AR_IO_I2C_MST0_CLR_INTR 0x80012040 -#pragma Aux_register(0x80012040, name=>"io_i2c_mst0_clr_intr") - -// User extension aux register io_i2c_mst0_clr_rx_under -#define AR_IO_I2C_MST0_CLR_RX_UNDER 0x80012044 -#pragma Aux_register(0x80012044, name=>"io_i2c_mst0_clr_rx_under") - -// User extension aux register io_i2c_mst0_clr_rx_over -#define AR_IO_I2C_MST0_CLR_RX_OVER 0x80012048 -#pragma Aux_register(0x80012048, name=>"io_i2c_mst0_clr_rx_over") - -// User extension aux register io_i2c_mst0_clr_tx_over -#define AR_IO_I2C_MST0_CLR_TX_OVER 0x8001204c -#pragma Aux_register(0x8001204c, name=>"io_i2c_mst0_clr_tx_over") - -// User extension aux register io_i2c_mst0_clr_tx_abrt -#define AR_IO_I2C_MST0_CLR_TX_ABRT 0x80012054 -#pragma Aux_register(0x80012054, name=>"io_i2c_mst0_clr_tx_abrt") - -// User extension aux register io_i2c_mst0_clr_activity -#define AR_IO_I2C_MST0_CLR_ACTIVITY 0x8001205c -#pragma Aux_register(0x8001205c, name=>"io_i2c_mst0_clr_activity") - -// User extension aux register io_i2c_mst0_clr_stop_det -#define AR_IO_I2C_MST0_CLR_STOP_DET 0x80012060 -#pragma Aux_register(0x80012060, name=>"io_i2c_mst0_clr_stop_det") - -// User extension aux register io_i2c_mst0_clr_start_det -#define AR_IO_I2C_MST0_CLR_START_DET 0x80012064 -#pragma Aux_register(0x80012064, name=>"io_i2c_mst0_clr_start_det") - -// User extension aux register io_i2c_mst0_enable -#define AR_IO_I2C_MST0_ENABLE 0x8001206c -#pragma Aux_register(0x8001206c, name=>"io_i2c_mst0_enable") - -// User extension aux register io_i2c_mst0_status -#define AR_IO_I2C_MST0_STATUS 0x80012070 -#pragma Aux_register(0x80012070, name=>"io_i2c_mst0_status") - -// User extension aux register io_i2c_mst0_txflr -#define AR_IO_I2C_MST0_TXFLR 0x80012074 -#pragma Aux_register(0x80012074, name=>"io_i2c_mst0_txflr") - -// User extension aux register io_i2c_mst0_rxflr -#define AR_IO_I2C_MST0_RXFLR 0x80012078 -#pragma Aux_register(0x80012078, name=>"io_i2c_mst0_rxflr") - -// User extension aux register io_i2c_mst0_sda_hold -#define AR_IO_I2C_MST0_SDA_HOLD 0x8001207c -#pragma Aux_register(0x8001207c, name=>"io_i2c_mst0_sda_hold") - -// User extension aux register io_i2c_mst0_tx_abrt_source -#define AR_IO_I2C_MST0_TX_ABRT_SOURCE 0x80012080 -#pragma Aux_register(0x80012080, name=>"io_i2c_mst0_tx_abrt_source") - -// User extension aux register io_i2c_mst0_enable_status -#define AR_IO_I2C_MST0_ENABLE_STATUS 0x8001209c -#pragma Aux_register(0x8001209c, name=>"io_i2c_mst0_enable_status") - -// User extension aux register io_i2c_mst0_fs_spklen -#define AR_IO_I2C_MST0_FS_SPKLEN 0x800120a0 -#pragma Aux_register(0x800120a0, name=>"io_i2c_mst0_fs_spklen") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2C_SLV0_PRESENT 1 - -// User extension aux register io_i2c_slv0_clken -#define AR_IO_I2C_SLV0_CLKEN 0x800130c0 -#pragma Aux_register(0x800130c0, name=>"io_i2c_slv0_clken") - -// User extension aux register io_i2c_slv0_con -#define AR_IO_I2C_SLV0_CON 0x80013000 -#pragma Aux_register(0x80013000, name=>"io_i2c_slv0_con") - -// User extension aux register io_i2c_slv0_sar -#define AR_IO_I2C_SLV0_SAR 0x80013008 -#pragma Aux_register(0x80013008, name=>"io_i2c_slv0_sar") - -// User extension aux register io_i2c_slv0_data_cmd -#define AR_IO_I2C_SLV0_DATA_CMD 0x80013010 -#pragma Aux_register(0x80013010, name=>"io_i2c_slv0_data_cmd") - -// User extension aux register io_i2c_slv0_intr_stat -#define AR_IO_I2C_SLV0_INTR_STAT 0x8001302c -#pragma Aux_register(0x8001302c, name=>"io_i2c_slv0_intr_stat") - -// User extension aux register io_i2c_slv0_intr_mask -#define AR_IO_I2C_SLV0_INTR_MASK 0x80013030 -#pragma Aux_register(0x80013030, name=>"io_i2c_slv0_intr_mask") - -// User extension aux register io_i2c_slv0_raw_intr_stat -#define AR_IO_I2C_SLV0_RAW_INTR_STAT 0x80013034 -#pragma Aux_register(0x80013034, name=>"io_i2c_slv0_raw_intr_stat") - -// User extension aux register io_i2c_slv0_rx_tl -#define AR_IO_I2C_SLV0_RX_TL 0x80013038 -#pragma Aux_register(0x80013038, name=>"io_i2c_slv0_rx_tl") - -// User extension aux register io_i2c_slv0_tx_tl -#define AR_IO_I2C_SLV0_TX_TL 0x8001303c -#pragma Aux_register(0x8001303c, name=>"io_i2c_slv0_tx_tl") - -// User extension aux register io_i2c_slv0_clr_intr -#define AR_IO_I2C_SLV0_CLR_INTR 0x80013040 -#pragma Aux_register(0x80013040, name=>"io_i2c_slv0_clr_intr") - -// User extension aux register io_i2c_slv0_clr_rx_under -#define AR_IO_I2C_SLV0_CLR_RX_UNDER 0x80013044 -#pragma Aux_register(0x80013044, name=>"io_i2c_slv0_clr_rx_under") - -// User extension aux register io_i2c_slv0_clr_rx_over -#define AR_IO_I2C_SLV0_CLR_RX_OVER 0x80013048 -#pragma Aux_register(0x80013048, name=>"io_i2c_slv0_clr_rx_over") - -// User extension aux register io_i2c_slv0_clr_tx_over -#define AR_IO_I2C_SLV0_CLR_TX_OVER 0x8001304c -#pragma Aux_register(0x8001304c, name=>"io_i2c_slv0_clr_tx_over") - -// User extension aux register io_i2c_slv0_clr_rd_req -#define AR_IO_I2C_SLV0_CLR_RD_REQ 0x80013050 -#pragma Aux_register(0x80013050, name=>"io_i2c_slv0_clr_rd_req") - -// User extension aux register io_i2c_slv0_clr_tx_abrt -#define AR_IO_I2C_SLV0_CLR_TX_ABRT 0x80013054 -#pragma Aux_register(0x80013054, name=>"io_i2c_slv0_clr_tx_abrt") - -// User extension aux register io_i2c_slv0_clr_rx_done -#define AR_IO_I2C_SLV0_CLR_RX_DONE 0x80013058 -#pragma Aux_register(0x80013058, name=>"io_i2c_slv0_clr_rx_done") - -// User extension aux register io_i2c_slv0_clr_activity -#define AR_IO_I2C_SLV0_CLR_ACTIVITY 0x8001305c -#pragma Aux_register(0x8001305c, name=>"io_i2c_slv0_clr_activity") - -// User extension aux register io_i2c_slv0_clr_stop_det -#define AR_IO_I2C_SLV0_CLR_STOP_DET 0x80013060 -#pragma Aux_register(0x80013060, name=>"io_i2c_slv0_clr_stop_det") - -// User extension aux register io_i2c_slv0_clr_start_det -#define AR_IO_I2C_SLV0_CLR_START_DET 0x80013064 -#pragma Aux_register(0x80013064, name=>"io_i2c_slv0_clr_start_det") - -// User extension aux register io_i2c_slv0_enable -#define AR_IO_I2C_SLV0_ENABLE 0x8001306c -#pragma Aux_register(0x8001306c, name=>"io_i2c_slv0_enable") - -// User extension aux register io_i2c_slv0_status -#define AR_IO_I2C_SLV0_STATUS 0x80013070 -#pragma Aux_register(0x80013070, name=>"io_i2c_slv0_status") - -// User extension aux register io_i2c_slv0_txflr -#define AR_IO_I2C_SLV0_TXFLR 0x80013074 -#pragma Aux_register(0x80013074, name=>"io_i2c_slv0_txflr") - -// User extension aux register io_i2c_slv0_rxflr -#define AR_IO_I2C_SLV0_RXFLR 0x80013078 -#pragma Aux_register(0x80013078, name=>"io_i2c_slv0_rxflr") - -// User extension aux register io_i2c_slv0_sda_hold -#define AR_IO_I2C_SLV0_SDA_HOLD 0x8001307c -#pragma Aux_register(0x8001307c, name=>"io_i2c_slv0_sda_hold") - -// User extension aux register io_i2c_slv0_tx_abrt_source -#define AR_IO_I2C_SLV0_TX_ABRT_SOURCE 0x80013080 -#pragma Aux_register(0x80013080, name=>"io_i2c_slv0_tx_abrt_source") - -// User extension aux register io_i2c_slv0_sda_setup -#define AR_IO_I2C_SLV0_SDA_SETUP 0x80013094 -#pragma Aux_register(0x80013094, name=>"io_i2c_slv0_sda_setup") - -// User extension aux register io_i2c_slv0_enable_status -#define AR_IO_I2C_SLV0_ENABLE_STATUS 0x8001309c -#pragma Aux_register(0x8001309c, name=>"io_i2c_slv0_enable_status") - -// User extension aux register io_i2c_slv0_fs_spklen -#define AR_IO_I2C_SLV0_FS_SPKLEN 0x800130a0 -#pragma Aux_register(0x800130a0, name=>"io_i2c_slv0_fs_spklen") - -// User extension aux register io_i2c_slv0_clr_restart_det -#define AR_IO_I2C_SLV0_CLR_RESTART_DET 0x800130a8 -#pragma Aux_register(0x800130a8, name=>"io_i2c_slv0_clr_restart_det") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_SPI_MST0_PRESENT 1 - -// User extension aux register io_spi_mst0_ctrlr0 -#define AR_IO_SPI_MST0_CTRLR0 0x80010000 -#pragma Aux_register(0x80010000, name=>"io_spi_mst0_ctrlr0") - -// User extension aux register io_spi_mst0_ctrlr1 -#define AR_IO_SPI_MST0_CTRLR1 0x80010001 -#pragma Aux_register(0x80010001, name=>"io_spi_mst0_ctrlr1") - -// User extension aux register io_spi_mst0_spien -#define AR_IO_SPI_MST0_SPIEN 0x80010002 -#pragma Aux_register(0x80010002, name=>"io_spi_mst0_spien") - -// User extension aux register io_spi_mst0_ser -#define AR_IO_SPI_MST0_SER 0x80010004 -#pragma Aux_register(0x80010004, name=>"io_spi_mst0_ser") - -// User extension aux register io_spi_mst0_baudr -#define AR_IO_SPI_MST0_BAUDR 0x80010005 -#pragma Aux_register(0x80010005, name=>"io_spi_mst0_baudr") - -// User extension aux register io_spi_mst0_txftlr -#define AR_IO_SPI_MST0_TXFTLR 0x80010006 -#pragma Aux_register(0x80010006, name=>"io_spi_mst0_txftlr") - -// User extension aux register io_spi_mst0_rxftlr -#define AR_IO_SPI_MST0_RXFTLR 0x80010007 -#pragma Aux_register(0x80010007, name=>"io_spi_mst0_rxftlr") - -// User extension aux register io_spi_mst0_txflr -#define AR_IO_SPI_MST0_TXFLR 0x80010008 -#pragma Aux_register(0x80010008, name=>"io_spi_mst0_txflr") - -// User extension aux register io_spi_mst0_rxflr -#define AR_IO_SPI_MST0_RXFLR 0x80010009 -#pragma Aux_register(0x80010009, name=>"io_spi_mst0_rxflr") - -// User extension aux register io_spi_mst0_sr -#define AR_IO_SPI_MST0_SR 0x8001000a -#pragma Aux_register(0x8001000a, name=>"io_spi_mst0_sr") - -// User extension aux register io_spi_mst0_imr -#define AR_IO_SPI_MST0_IMR 0x8001000b -#pragma Aux_register(0x8001000b, name=>"io_spi_mst0_imr") - -// User extension aux register io_spi_mst0_isr -#define AR_IO_SPI_MST0_ISR 0x8001000c -#pragma Aux_register(0x8001000c, name=>"io_spi_mst0_isr") - -// User extension aux register io_spi_mst0_risr -#define AR_IO_SPI_MST0_RISR 0x8001000d -#pragma Aux_register(0x8001000d, name=>"io_spi_mst0_risr") - -// User extension aux register io_spi_mst0_txoicr -#define AR_IO_SPI_MST0_TXOICR 0x8001000e -#pragma Aux_register(0x8001000e, name=>"io_spi_mst0_txoicr") - -// User extension aux register io_spi_mst0_rxoicr -#define AR_IO_SPI_MST0_RXOICR 0x8001000f -#pragma Aux_register(0x8001000f, name=>"io_spi_mst0_rxoicr") - -// User extension aux register io_spi_mst0_rxuicr -#define AR_IO_SPI_MST0_RXUICR 0x80010010 -#pragma Aux_register(0x80010010, name=>"io_spi_mst0_rxuicr") - -// User extension aux register io_spi_mst0_icr -#define AR_IO_SPI_MST0_ICR 0x80010012 -#pragma Aux_register(0x80010012, name=>"io_spi_mst0_icr") - -// User extension aux register io_spi_mst0_clken -#define AR_IO_SPI_MST0_CLKEN 0x80010016 -#pragma Aux_register(0x80010016, name=>"io_spi_mst0_clken") - -// User extension aux register io_spi_mst0_dr -#define AR_IO_SPI_MST0_DR 0x80010018 -#pragma Aux_register(0x80010018, name=>"io_spi_mst0_dr") - -// User extension aux register io_spi_mst0_rx_sample_dly -#define AR_IO_SPI_MST0_RX_SAMPLE_DLY 0x8001003c -#pragma Aux_register(0x8001003c, name=>"io_spi_mst0_rx_sample_dly") -#define APEX_COM_ARC_HARDWARE_DFSS_SUBSYS_BCR_PRESENT 1 - -// User extension aux register SUBSYS_BUILD -#define AR_SUBSYS_BUILD 0xf0 -#pragma Aux_register(0xf0, name=>"SUBSYS_BUILD") - -// User extension aux register SUBSYS_DSP_0_BUILD -#define AR_SUBSYS_DSP_0_BUILD 0xa00 -#pragma Aux_register(0xa00, name=>"SUBSYS_DSP_0_BUILD") - -// User extension aux register SUBSYS_DSP_0_CONFIG -#define AR_SUBSYS_DSP_0_CONFIG 0xa02 -#pragma Aux_register(0xa02, name=>"SUBSYS_DSP_0_CONFIG") - -// User extension aux register SUBSYS_IO_0_BUILD -#define AR_SUBSYS_IO_0_BUILD 0xa04 -#pragma Aux_register(0xa04, name=>"SUBSYS_IO_0_BUILD") - -// User extension aux register SUBSYS_IO_1_BUILD -#define AR_SUBSYS_IO_1_BUILD 0xa05 -#pragma Aux_register(0xa05, name=>"SUBSYS_IO_1_BUILD") - -// User extension aux register SUBSYS_IO_2_BUILD -#define AR_SUBSYS_IO_2_BUILD 0xa06 -#pragma Aux_register(0xa06, name=>"SUBSYS_IO_2_BUILD") - -// User extension aux register SUBSYS_UAUX_OFFSET -#define AR_SUBSYS_UAUX_OFFSET 0xa1e -#pragma Aux_register(0xa1e, name=>"SUBSYS_UAUX_OFFSET") - -// User extension aux register SUBSYS_APEX_OFFSET -#define AR_SUBSYS_APEX_OFFSET 0xa1f -#pragma Aux_register(0xa1f, name=>"SUBSYS_APEX_OFFSET") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_SPI_MST1_PRESENT 1 - -// User extension aux register io_spi_mst1_ctrlr0 -#define AR_IO_SPI_MST1_CTRLR0 0x80010100 -#pragma Aux_register(0x80010100, name=>"io_spi_mst1_ctrlr0") - -// User extension aux register io_spi_mst1_ctrlr1 -#define AR_IO_SPI_MST1_CTRLR1 0x80010101 -#pragma Aux_register(0x80010101, name=>"io_spi_mst1_ctrlr1") - -// User extension aux register io_spi_mst1_spien -#define AR_IO_SPI_MST1_SPIEN 0x80010102 -#pragma Aux_register(0x80010102, name=>"io_spi_mst1_spien") - -// User extension aux register io_spi_mst1_ser -#define AR_IO_SPI_MST1_SER 0x80010104 -#pragma Aux_register(0x80010104, name=>"io_spi_mst1_ser") - -// User extension aux register io_spi_mst1_baudr -#define AR_IO_SPI_MST1_BAUDR 0x80010105 -#pragma Aux_register(0x80010105, name=>"io_spi_mst1_baudr") - -// User extension aux register io_spi_mst1_txftlr -#define AR_IO_SPI_MST1_TXFTLR 0x80010106 -#pragma Aux_register(0x80010106, name=>"io_spi_mst1_txftlr") - -// User extension aux register io_spi_mst1_rxftlr -#define AR_IO_SPI_MST1_RXFTLR 0x80010107 -#pragma Aux_register(0x80010107, name=>"io_spi_mst1_rxftlr") - -// User extension aux register io_spi_mst1_txflr -#define AR_IO_SPI_MST1_TXFLR 0x80010108 -#pragma Aux_register(0x80010108, name=>"io_spi_mst1_txflr") - -// User extension aux register io_spi_mst1_rxflr -#define AR_IO_SPI_MST1_RXFLR 0x80010109 -#pragma Aux_register(0x80010109, name=>"io_spi_mst1_rxflr") - -// User extension aux register io_spi_mst1_sr -#define AR_IO_SPI_MST1_SR 0x8001010a -#pragma Aux_register(0x8001010a, name=>"io_spi_mst1_sr") - -// User extension aux register io_spi_mst1_imr -#define AR_IO_SPI_MST1_IMR 0x8001010b -#pragma Aux_register(0x8001010b, name=>"io_spi_mst1_imr") - -// User extension aux register io_spi_mst1_isr -#define AR_IO_SPI_MST1_ISR 0x8001010c -#pragma Aux_register(0x8001010c, name=>"io_spi_mst1_isr") - -// User extension aux register io_spi_mst1_risr -#define AR_IO_SPI_MST1_RISR 0x8001010d -#pragma Aux_register(0x8001010d, name=>"io_spi_mst1_risr") - -// User extension aux register io_spi_mst1_txoicr -#define AR_IO_SPI_MST1_TXOICR 0x8001010e -#pragma Aux_register(0x8001010e, name=>"io_spi_mst1_txoicr") - -// User extension aux register io_spi_mst1_rxoicr -#define AR_IO_SPI_MST1_RXOICR 0x8001010f -#pragma Aux_register(0x8001010f, name=>"io_spi_mst1_rxoicr") - -// User extension aux register io_spi_mst1_rxuicr -#define AR_IO_SPI_MST1_RXUICR 0x80010110 -#pragma Aux_register(0x80010110, name=>"io_spi_mst1_rxuicr") - -// User extension aux register io_spi_mst1_icr -#define AR_IO_SPI_MST1_ICR 0x80010112 -#pragma Aux_register(0x80010112, name=>"io_spi_mst1_icr") - -// User extension aux register io_spi_mst1_clken -#define AR_IO_SPI_MST1_CLKEN 0x80010116 -#pragma Aux_register(0x80010116, name=>"io_spi_mst1_clken") - -// User extension aux register io_spi_mst1_dr -#define AR_IO_SPI_MST1_DR 0x80010118 -#pragma Aux_register(0x80010118, name=>"io_spi_mst1_dr") - -// User extension aux register io_spi_mst1_rx_sample_dly -#define AR_IO_SPI_MST1_RX_SAMPLE_DLY 0x8001013c -#pragma Aux_register(0x8001013c, name=>"io_spi_mst1_rx_sample_dly") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_SPI_MST2_PRESENT 1 - -// User extension aux register io_spi_mst2_ctrlr0 -#define AR_IO_SPI_MST2_CTRLR0 0x80010200 -#pragma Aux_register(0x80010200, name=>"io_spi_mst2_ctrlr0") - -// User extension aux register io_spi_mst2_ctrlr1 -#define AR_IO_SPI_MST2_CTRLR1 0x80010201 -#pragma Aux_register(0x80010201, name=>"io_spi_mst2_ctrlr1") - -// User extension aux register io_spi_mst2_spien -#define AR_IO_SPI_MST2_SPIEN 0x80010202 -#pragma Aux_register(0x80010202, name=>"io_spi_mst2_spien") - -// User extension aux register io_spi_mst2_ser -#define AR_IO_SPI_MST2_SER 0x80010204 -#pragma Aux_register(0x80010204, name=>"io_spi_mst2_ser") - -// User extension aux register io_spi_mst2_baudr -#define AR_IO_SPI_MST2_BAUDR 0x80010205 -#pragma Aux_register(0x80010205, name=>"io_spi_mst2_baudr") - -// User extension aux register io_spi_mst2_txftlr -#define AR_IO_SPI_MST2_TXFTLR 0x80010206 -#pragma Aux_register(0x80010206, name=>"io_spi_mst2_txftlr") - -// User extension aux register io_spi_mst2_rxftlr -#define AR_IO_SPI_MST2_RXFTLR 0x80010207 -#pragma Aux_register(0x80010207, name=>"io_spi_mst2_rxftlr") - -// User extension aux register io_spi_mst2_txflr -#define AR_IO_SPI_MST2_TXFLR 0x80010208 -#pragma Aux_register(0x80010208, name=>"io_spi_mst2_txflr") - -// User extension aux register io_spi_mst2_rxflr -#define AR_IO_SPI_MST2_RXFLR 0x80010209 -#pragma Aux_register(0x80010209, name=>"io_spi_mst2_rxflr") - -// User extension aux register io_spi_mst2_sr -#define AR_IO_SPI_MST2_SR 0x8001020a -#pragma Aux_register(0x8001020a, name=>"io_spi_mst2_sr") - -// User extension aux register io_spi_mst2_imr -#define AR_IO_SPI_MST2_IMR 0x8001020b -#pragma Aux_register(0x8001020b, name=>"io_spi_mst2_imr") - -// User extension aux register io_spi_mst2_isr -#define AR_IO_SPI_MST2_ISR 0x8001020c -#pragma Aux_register(0x8001020c, name=>"io_spi_mst2_isr") - -// User extension aux register io_spi_mst2_risr -#define AR_IO_SPI_MST2_RISR 0x8001020d -#pragma Aux_register(0x8001020d, name=>"io_spi_mst2_risr") - -// User extension aux register io_spi_mst2_txoicr -#define AR_IO_SPI_MST2_TXOICR 0x8001020e -#pragma Aux_register(0x8001020e, name=>"io_spi_mst2_txoicr") - -// User extension aux register io_spi_mst2_rxoicr -#define AR_IO_SPI_MST2_RXOICR 0x8001020f -#pragma Aux_register(0x8001020f, name=>"io_spi_mst2_rxoicr") - -// User extension aux register io_spi_mst2_rxuicr -#define AR_IO_SPI_MST2_RXUICR 0x80010210 -#pragma Aux_register(0x80010210, name=>"io_spi_mst2_rxuicr") - -// User extension aux register io_spi_mst2_icr -#define AR_IO_SPI_MST2_ICR 0x80010212 -#pragma Aux_register(0x80010212, name=>"io_spi_mst2_icr") - -// User extension aux register io_spi_mst2_clken -#define AR_IO_SPI_MST2_CLKEN 0x80010216 -#pragma Aux_register(0x80010216, name=>"io_spi_mst2_clken") - -// User extension aux register io_spi_mst2_dr -#define AR_IO_SPI_MST2_DR 0x80010218 -#pragma Aux_register(0x80010218, name=>"io_spi_mst2_dr") - -// User extension aux register io_spi_mst2_rx_sample_dly -#define AR_IO_SPI_MST2_RX_SAMPLE_DLY 0x8001023c -#pragma Aux_register(0x8001023c, name=>"io_spi_mst2_rx_sample_dly") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_SPI_SLV0_PRESENT 1 - -// User extension aux register io_spi_slv0_ctrlr0 -#define AR_IO_SPI_SLV0_CTRLR0 0x80011000 -#pragma Aux_register(0x80011000, name=>"io_spi_slv0_ctrlr0") - -// User extension aux register io_spi_slv0_spien -#define AR_IO_SPI_SLV0_SPIEN 0x80011002 -#pragma Aux_register(0x80011002, name=>"io_spi_slv0_spien") - -// User extension aux register io_spi_slv0_txftlr -#define AR_IO_SPI_SLV0_TXFTLR 0x80011006 -#pragma Aux_register(0x80011006, name=>"io_spi_slv0_txftlr") - -// User extension aux register io_spi_slv0_rxftlr -#define AR_IO_SPI_SLV0_RXFTLR 0x80011007 -#pragma Aux_register(0x80011007, name=>"io_spi_slv0_rxftlr") - -// User extension aux register io_spi_slv0_txflr -#define AR_IO_SPI_SLV0_TXFLR 0x80011008 -#pragma Aux_register(0x80011008, name=>"io_spi_slv0_txflr") - -// User extension aux register io_spi_slv0_rxflr -#define AR_IO_SPI_SLV0_RXFLR 0x80011009 -#pragma Aux_register(0x80011009, name=>"io_spi_slv0_rxflr") - -// User extension aux register io_spi_slv0_sr -#define AR_IO_SPI_SLV0_SR 0x8001100a -#pragma Aux_register(0x8001100a, name=>"io_spi_slv0_sr") - -// User extension aux register io_spi_slv0_imr -#define AR_IO_SPI_SLV0_IMR 0x8001100b -#pragma Aux_register(0x8001100b, name=>"io_spi_slv0_imr") - -// User extension aux register io_spi_slv0_isr -#define AR_IO_SPI_SLV0_ISR 0x8001100c -#pragma Aux_register(0x8001100c, name=>"io_spi_slv0_isr") - -// User extension aux register io_spi_slv0_risr -#define AR_IO_SPI_SLV0_RISR 0x8001100d -#pragma Aux_register(0x8001100d, name=>"io_spi_slv0_risr") - -// User extension aux register io_spi_slv0_txoicr -#define AR_IO_SPI_SLV0_TXOICR 0x8001100e -#pragma Aux_register(0x8001100e, name=>"io_spi_slv0_txoicr") - -// User extension aux register io_spi_slv0_rxoicr -#define AR_IO_SPI_SLV0_RXOICR 0x8001100f -#pragma Aux_register(0x8001100f, name=>"io_spi_slv0_rxoicr") - -// User extension aux register io_spi_slv0_rxuicr -#define AR_IO_SPI_SLV0_RXUICR 0x80011010 -#pragma Aux_register(0x80011010, name=>"io_spi_slv0_rxuicr") - -// User extension aux register io_spi_slv0_icr -#define AR_IO_SPI_SLV0_ICR 0x80011012 -#pragma Aux_register(0x80011012, name=>"io_spi_slv0_icr") - -// User extension aux register io_spi_slv0_clken -#define AR_IO_SPI_SLV0_CLKEN 0x80011016 -#pragma Aux_register(0x80011016, name=>"io_spi_slv0_clken") - -// User extension aux register io_spi_slv0_dr -#define AR_IO_SPI_SLV0_DR 0x80011018 -#pragma Aux_register(0x80011018, name=>"io_spi_slv0_dr") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_GPIO1_PRESENT 1 - -// User extension aux register io_gpio1_debounce -#define AR_IO_GPIO1_DEBOUNCE 0x80017148 -#pragma Aux_register(0x80017148, name=>"io_gpio1_debounce") - -// User extension aux register io_gpio1_clken -#define AR_IO_GPIO1_CLKEN 0x80017180 -#pragma Aux_register(0x80017180, name=>"io_gpio1_clken") - -// User extension aux register io_gpio1_swporta_dr -#define AR_IO_GPIO1_SWPORTA_DR 0x80017100 -#pragma Aux_register(0x80017100, name=>"io_gpio1_swporta_dr") - -// User extension aux register io_gpio1_swporta_ddr -#define AR_IO_GPIO1_SWPORTA_DDR 0x80017104 -#pragma Aux_register(0x80017104, name=>"io_gpio1_swporta_ddr") - -// User extension aux register io_gpio1_inten -#define AR_IO_GPIO1_INTEN 0x80017130 -#pragma Aux_register(0x80017130, name=>"io_gpio1_inten") - -// User extension aux register io_gpio1_intmask -#define AR_IO_GPIO1_INTMASK 0x80017134 -#pragma Aux_register(0x80017134, name=>"io_gpio1_intmask") - -// User extension aux register io_gpio1_inttype_level -#define AR_IO_GPIO1_INTTYPE_LEVEL 0x80017138 -#pragma Aux_register(0x80017138, name=>"io_gpio1_inttype_level") - -// User extension aux register io_gpio1_int_polarity -#define AR_IO_GPIO1_INT_POLARITY 0x8001713c -#pragma Aux_register(0x8001713c, name=>"io_gpio1_int_polarity") - -// User extension aux register io_gpio1_intstatus -#define AR_IO_GPIO1_INTSTATUS 0x80017140 -#pragma Aux_register(0x80017140, name=>"io_gpio1_intstatus") - -// User extension aux register io_gpio1_raw_intstatus -#define AR_IO_GPIO1_RAW_INTSTATUS 0x80017144 -#pragma Aux_register(0x80017144, name=>"io_gpio1_raw_intstatus") - -// User extension aux register io_gpio1_porta_eoi -#define AR_IO_GPIO1_PORTA_EOI 0x8001714c -#pragma Aux_register(0x8001714c, name=>"io_gpio1_porta_eoi") - -// User extension aux register io_gpio1_ext_porta -#define AR_IO_GPIO1_EXT_PORTA 0x80017150 -#pragma Aux_register(0x80017150, name=>"io_gpio1_ext_porta") - -// User extension aux register io_gpio1_ls_sync -#define AR_IO_GPIO1_LS_SYNC 0x80017160 -#pragma Aux_register(0x80017160, name=>"io_gpio1_ls_sync") - -// User extension aux register io_gpio1_int_bothedge -#define AR_IO_GPIO1_INT_BOTHEDGE 0x80017168 -#pragma Aux_register(0x80017168, name=>"io_gpio1_int_bothedge") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_GPIO2_PRESENT 1 - -// User extension aux register io_gpio2_debounce -#define AR_IO_GPIO2_DEBOUNCE 0x80017248 -#pragma Aux_register(0x80017248, name=>"io_gpio2_debounce") - -// User extension aux register io_gpio2_clken -#define AR_IO_GPIO2_CLKEN 0x80017280 -#pragma Aux_register(0x80017280, name=>"io_gpio2_clken") - -// User extension aux register io_gpio2_swporta_dr -#define AR_IO_GPIO2_SWPORTA_DR 0x80017200 -#pragma Aux_register(0x80017200, name=>"io_gpio2_swporta_dr") - -// User extension aux register io_gpio2_swporta_ddr -#define AR_IO_GPIO2_SWPORTA_DDR 0x80017204 -#pragma Aux_register(0x80017204, name=>"io_gpio2_swporta_ddr") - -// User extension aux register io_gpio2_inten -#define AR_IO_GPIO2_INTEN 0x80017230 -#pragma Aux_register(0x80017230, name=>"io_gpio2_inten") - -// User extension aux register io_gpio2_intmask -#define AR_IO_GPIO2_INTMASK 0x80017234 -#pragma Aux_register(0x80017234, name=>"io_gpio2_intmask") - -// User extension aux register io_gpio2_inttype_level -#define AR_IO_GPIO2_INTTYPE_LEVEL 0x80017238 -#pragma Aux_register(0x80017238, name=>"io_gpio2_inttype_level") - -// User extension aux register io_gpio2_int_polarity -#define AR_IO_GPIO2_INT_POLARITY 0x8001723c -#pragma Aux_register(0x8001723c, name=>"io_gpio2_int_polarity") - -// User extension aux register io_gpio2_intstatus -#define AR_IO_GPIO2_INTSTATUS 0x80017240 -#pragma Aux_register(0x80017240, name=>"io_gpio2_intstatus") - -// User extension aux register io_gpio2_raw_intstatus -#define AR_IO_GPIO2_RAW_INTSTATUS 0x80017244 -#pragma Aux_register(0x80017244, name=>"io_gpio2_raw_intstatus") - -// User extension aux register io_gpio2_porta_eoi -#define AR_IO_GPIO2_PORTA_EOI 0x8001724c -#pragma Aux_register(0x8001724c, name=>"io_gpio2_porta_eoi") - -// User extension aux register io_gpio2_ext_porta -#define AR_IO_GPIO2_EXT_PORTA 0x80017250 -#pragma Aux_register(0x80017250, name=>"io_gpio2_ext_porta") - -// User extension aux register io_gpio2_ls_sync -#define AR_IO_GPIO2_LS_SYNC 0x80017260 -#pragma Aux_register(0x80017260, name=>"io_gpio2_ls_sync") - -// User extension aux register io_gpio2_int_bothedge -#define AR_IO_GPIO2_INT_BOTHEDGE 0x80017268 -#pragma Aux_register(0x80017268, name=>"io_gpio2_int_bothedge") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2C_MST1_PRESENT 1 - -// User extension aux register io_i2c_mst1_clken -#define AR_IO_I2C_MST1_CLKEN 0x800121c0 -#pragma Aux_register(0x800121c0, name=>"io_i2c_mst1_clken") - -// User extension aux register io_i2c_mst1_con -#define AR_IO_I2C_MST1_CON 0x80012100 -#pragma Aux_register(0x80012100, name=>"io_i2c_mst1_con") - -// User extension aux register io_i2c_mst1_tar -#define AR_IO_I2C_MST1_TAR 0x80012104 -#pragma Aux_register(0x80012104, name=>"io_i2c_mst1_tar") - -// User extension aux register io_i2c_mst1_data_cmd -#define AR_IO_I2C_MST1_DATA_CMD 0x80012110 -#pragma Aux_register(0x80012110, name=>"io_i2c_mst1_data_cmd") - -// User extension aux register io_i2c_mst1_ss_scl_hcnt -#define AR_IO_I2C_MST1_SS_SCL_HCNT 0x80012114 -#pragma Aux_register(0x80012114, name=>"io_i2c_mst1_ss_scl_hcnt") - -// User extension aux register io_i2c_mst1_ss_scl_lcnt -#define AR_IO_I2C_MST1_SS_SCL_LCNT 0x80012118 -#pragma Aux_register(0x80012118, name=>"io_i2c_mst1_ss_scl_lcnt") - -// User extension aux register io_i2c_mst1_fs_scl_hcnt -#define AR_IO_I2C_MST1_FS_SCL_HCNT 0x8001211c -#pragma Aux_register(0x8001211c, name=>"io_i2c_mst1_fs_scl_hcnt") - -// User extension aux register io_i2c_mst1_fs_scl_lcnt -#define AR_IO_I2C_MST1_FS_SCL_LCNT 0x80012120 -#pragma Aux_register(0x80012120, name=>"io_i2c_mst1_fs_scl_lcnt") - -// User extension aux register io_i2c_mst1_intr_stat -#define AR_IO_I2C_MST1_INTR_STAT 0x8001212c -#pragma Aux_register(0x8001212c, name=>"io_i2c_mst1_intr_stat") - -// User extension aux register io_i2c_mst1_intr_mask -#define AR_IO_I2C_MST1_INTR_MASK 0x80012130 -#pragma Aux_register(0x80012130, name=>"io_i2c_mst1_intr_mask") - -// User extension aux register io_i2c_mst1_raw_intr_stat -#define AR_IO_I2C_MST1_RAW_INTR_STAT 0x80012134 -#pragma Aux_register(0x80012134, name=>"io_i2c_mst1_raw_intr_stat") - -// User extension aux register io_i2c_mst1_rx_tl -#define AR_IO_I2C_MST1_RX_TL 0x80012138 -#pragma Aux_register(0x80012138, name=>"io_i2c_mst1_rx_tl") - -// User extension aux register io_i2c_mst1_tx_tl -#define AR_IO_I2C_MST1_TX_TL 0x8001213c -#pragma Aux_register(0x8001213c, name=>"io_i2c_mst1_tx_tl") - -// User extension aux register io_i2c_mst1_clr_intr -#define AR_IO_I2C_MST1_CLR_INTR 0x80012140 -#pragma Aux_register(0x80012140, name=>"io_i2c_mst1_clr_intr") - -// User extension aux register io_i2c_mst1_clr_rx_under -#define AR_IO_I2C_MST1_CLR_RX_UNDER 0x80012144 -#pragma Aux_register(0x80012144, name=>"io_i2c_mst1_clr_rx_under") - -// User extension aux register io_i2c_mst1_clr_rx_over -#define AR_IO_I2C_MST1_CLR_RX_OVER 0x80012148 -#pragma Aux_register(0x80012148, name=>"io_i2c_mst1_clr_rx_over") - -// User extension aux register io_i2c_mst1_clr_tx_over -#define AR_IO_I2C_MST1_CLR_TX_OVER 0x8001214c -#pragma Aux_register(0x8001214c, name=>"io_i2c_mst1_clr_tx_over") - -// User extension aux register io_i2c_mst1_clr_tx_abrt -#define AR_IO_I2C_MST1_CLR_TX_ABRT 0x80012154 -#pragma Aux_register(0x80012154, name=>"io_i2c_mst1_clr_tx_abrt") - -// User extension aux register io_i2c_mst1_clr_activity -#define AR_IO_I2C_MST1_CLR_ACTIVITY 0x8001215c -#pragma Aux_register(0x8001215c, name=>"io_i2c_mst1_clr_activity") - -// User extension aux register io_i2c_mst1_clr_stop_det -#define AR_IO_I2C_MST1_CLR_STOP_DET 0x80012160 -#pragma Aux_register(0x80012160, name=>"io_i2c_mst1_clr_stop_det") - -// User extension aux register io_i2c_mst1_clr_start_det -#define AR_IO_I2C_MST1_CLR_START_DET 0x80012164 -#pragma Aux_register(0x80012164, name=>"io_i2c_mst1_clr_start_det") - -// User extension aux register io_i2c_mst1_enable -#define AR_IO_I2C_MST1_ENABLE 0x8001216c -#pragma Aux_register(0x8001216c, name=>"io_i2c_mst1_enable") - -// User extension aux register io_i2c_mst1_status -#define AR_IO_I2C_MST1_STATUS 0x80012170 -#pragma Aux_register(0x80012170, name=>"io_i2c_mst1_status") - -// User extension aux register io_i2c_mst1_txflr -#define AR_IO_I2C_MST1_TXFLR 0x80012174 -#pragma Aux_register(0x80012174, name=>"io_i2c_mst1_txflr") - -// User extension aux register io_i2c_mst1_rxflr -#define AR_IO_I2C_MST1_RXFLR 0x80012178 -#pragma Aux_register(0x80012178, name=>"io_i2c_mst1_rxflr") - -// User extension aux register io_i2c_mst1_sda_hold -#define AR_IO_I2C_MST1_SDA_HOLD 0x8001217c -#pragma Aux_register(0x8001217c, name=>"io_i2c_mst1_sda_hold") - -// User extension aux register io_i2c_mst1_tx_abrt_source -#define AR_IO_I2C_MST1_TX_ABRT_SOURCE 0x80012180 -#pragma Aux_register(0x80012180, name=>"io_i2c_mst1_tx_abrt_source") - -// User extension aux register io_i2c_mst1_enable_status -#define AR_IO_I2C_MST1_ENABLE_STATUS 0x8001219c -#pragma Aux_register(0x8001219c, name=>"io_i2c_mst1_enable_status") - -// User extension aux register io_i2c_mst1_fs_spklen -#define AR_IO_I2C_MST1_FS_SPKLEN 0x800121a0 -#pragma Aux_register(0x800121a0, name=>"io_i2c_mst1_fs_spklen") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2C_MST2_PRESENT 1 - -// User extension aux register io_i2c_mst2_clken -#define AR_IO_I2C_MST2_CLKEN 0x800122c0 -#pragma Aux_register(0x800122c0, name=>"io_i2c_mst2_clken") - -// User extension aux register io_i2c_mst2_con -#define AR_IO_I2C_MST2_CON 0x80012200 -#pragma Aux_register(0x80012200, name=>"io_i2c_mst2_con") - -// User extension aux register io_i2c_mst2_tar -#define AR_IO_I2C_MST2_TAR 0x80012204 -#pragma Aux_register(0x80012204, name=>"io_i2c_mst2_tar") - -// User extension aux register io_i2c_mst2_data_cmd -#define AR_IO_I2C_MST2_DATA_CMD 0x80012210 -#pragma Aux_register(0x80012210, name=>"io_i2c_mst2_data_cmd") - -// User extension aux register io_i2c_mst2_ss_scl_hcnt -#define AR_IO_I2C_MST2_SS_SCL_HCNT 0x80012214 -#pragma Aux_register(0x80012214, name=>"io_i2c_mst2_ss_scl_hcnt") - -// User extension aux register io_i2c_mst2_ss_scl_lcnt -#define AR_IO_I2C_MST2_SS_SCL_LCNT 0x80012218 -#pragma Aux_register(0x80012218, name=>"io_i2c_mst2_ss_scl_lcnt") - -// User extension aux register io_i2c_mst2_fs_scl_hcnt -#define AR_IO_I2C_MST2_FS_SCL_HCNT 0x8001221c -#pragma Aux_register(0x8001221c, name=>"io_i2c_mst2_fs_scl_hcnt") - -// User extension aux register io_i2c_mst2_fs_scl_lcnt -#define AR_IO_I2C_MST2_FS_SCL_LCNT 0x80012220 -#pragma Aux_register(0x80012220, name=>"io_i2c_mst2_fs_scl_lcnt") - -// User extension aux register io_i2c_mst2_intr_stat -#define AR_IO_I2C_MST2_INTR_STAT 0x8001222c -#pragma Aux_register(0x8001222c, name=>"io_i2c_mst2_intr_stat") - -// User extension aux register io_i2c_mst2_intr_mask -#define AR_IO_I2C_MST2_INTR_MASK 0x80012230 -#pragma Aux_register(0x80012230, name=>"io_i2c_mst2_intr_mask") - -// User extension aux register io_i2c_mst2_raw_intr_stat -#define AR_IO_I2C_MST2_RAW_INTR_STAT 0x80012234 -#pragma Aux_register(0x80012234, name=>"io_i2c_mst2_raw_intr_stat") - -// User extension aux register io_i2c_mst2_rx_tl -#define AR_IO_I2C_MST2_RX_TL 0x80012238 -#pragma Aux_register(0x80012238, name=>"io_i2c_mst2_rx_tl") - -// User extension aux register io_i2c_mst2_tx_tl -#define AR_IO_I2C_MST2_TX_TL 0x8001223c -#pragma Aux_register(0x8001223c, name=>"io_i2c_mst2_tx_tl") - -// User extension aux register io_i2c_mst2_clr_intr -#define AR_IO_I2C_MST2_CLR_INTR 0x80012240 -#pragma Aux_register(0x80012240, name=>"io_i2c_mst2_clr_intr") - -// User extension aux register io_i2c_mst2_clr_rx_under -#define AR_IO_I2C_MST2_CLR_RX_UNDER 0x80012244 -#pragma Aux_register(0x80012244, name=>"io_i2c_mst2_clr_rx_under") - -// User extension aux register io_i2c_mst2_clr_rx_over -#define AR_IO_I2C_MST2_CLR_RX_OVER 0x80012248 -#pragma Aux_register(0x80012248, name=>"io_i2c_mst2_clr_rx_over") - -// User extension aux register io_i2c_mst2_clr_tx_over -#define AR_IO_I2C_MST2_CLR_TX_OVER 0x8001224c -#pragma Aux_register(0x8001224c, name=>"io_i2c_mst2_clr_tx_over") - -// User extension aux register io_i2c_mst2_clr_tx_abrt -#define AR_IO_I2C_MST2_CLR_TX_ABRT 0x80012254 -#pragma Aux_register(0x80012254, name=>"io_i2c_mst2_clr_tx_abrt") - -// User extension aux register io_i2c_mst2_clr_activity -#define AR_IO_I2C_MST2_CLR_ACTIVITY 0x8001225c -#pragma Aux_register(0x8001225c, name=>"io_i2c_mst2_clr_activity") - -// User extension aux register io_i2c_mst2_clr_stop_det -#define AR_IO_I2C_MST2_CLR_STOP_DET 0x80012260 -#pragma Aux_register(0x80012260, name=>"io_i2c_mst2_clr_stop_det") - -// User extension aux register io_i2c_mst2_clr_start_det -#define AR_IO_I2C_MST2_CLR_START_DET 0x80012264 -#pragma Aux_register(0x80012264, name=>"io_i2c_mst2_clr_start_det") - -// User extension aux register io_i2c_mst2_enable -#define AR_IO_I2C_MST2_ENABLE 0x8001226c -#pragma Aux_register(0x8001226c, name=>"io_i2c_mst2_enable") - -// User extension aux register io_i2c_mst2_status -#define AR_IO_I2C_MST2_STATUS 0x80012270 -#pragma Aux_register(0x80012270, name=>"io_i2c_mst2_status") - -// User extension aux register io_i2c_mst2_txflr -#define AR_IO_I2C_MST2_TXFLR 0x80012274 -#pragma Aux_register(0x80012274, name=>"io_i2c_mst2_txflr") - -// User extension aux register io_i2c_mst2_rxflr -#define AR_IO_I2C_MST2_RXFLR 0x80012278 -#pragma Aux_register(0x80012278, name=>"io_i2c_mst2_rxflr") - -// User extension aux register io_i2c_mst2_sda_hold -#define AR_IO_I2C_MST2_SDA_HOLD 0x8001227c -#pragma Aux_register(0x8001227c, name=>"io_i2c_mst2_sda_hold") - -// User extension aux register io_i2c_mst2_tx_abrt_source -#define AR_IO_I2C_MST2_TX_ABRT_SOURCE 0x80012280 -#pragma Aux_register(0x80012280, name=>"io_i2c_mst2_tx_abrt_source") - -// User extension aux register io_i2c_mst2_enable_status -#define AR_IO_I2C_MST2_ENABLE_STATUS 0x8001229c -#pragma Aux_register(0x8001229c, name=>"io_i2c_mst2_enable_status") - -// User extension aux register io_i2c_mst2_fs_spklen -#define AR_IO_I2C_MST2_FS_SPKLEN 0x800122a0 -#pragma Aux_register(0x800122a0, name=>"io_i2c_mst2_fs_spklen") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_UART0_PRESENT 1 - -// User extension aux register io_uart0_clken -#define AR_IO_UART0_CLKEN 0x800140c0 -#pragma Aux_register(0x800140c0, name=>"io_uart0_clken") - -// User extension aux register io_uart0_rbr_thr_dll -#define AR_IO_UART0_RBR_THR_DLL 0x80014000 -#pragma Aux_register(0x80014000, name=>"io_uart0_rbr_thr_dll") - -// User extension aux register io_uart0_ier_dlh -#define AR_IO_UART0_IER_DLH 0x80014004 -#pragma Aux_register(0x80014004, name=>"io_uart0_ier_dlh") - -// User extension aux register io_uart0_iir_fcr -#define AR_IO_UART0_IIR_FCR 0x80014008 -#pragma Aux_register(0x80014008, name=>"io_uart0_iir_fcr") - -// User extension aux register io_uart0_lcr -#define AR_IO_UART0_LCR 0x8001400c -#pragma Aux_register(0x8001400c, name=>"io_uart0_lcr") - -// User extension aux register io_uart0_mcr -#define AR_IO_UART0_MCR 0x80014010 -#pragma Aux_register(0x80014010, name=>"io_uart0_mcr") - -// User extension aux register io_uart0_lsr -#define AR_IO_UART0_LSR 0x80014014 -#pragma Aux_register(0x80014014, name=>"io_uart0_lsr") - -// User extension aux register io_uart0_msr -#define AR_IO_UART0_MSR 0x80014018 -#pragma Aux_register(0x80014018, name=>"io_uart0_msr") - -// User extension aux register io_uart0_usr -#define AR_IO_UART0_USR 0x8001407c -#pragma Aux_register(0x8001407c, name=>"io_uart0_usr") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_UART1_PRESENT 1 - -// User extension aux register io_uart1_clken -#define AR_IO_UART1_CLKEN 0x800141c0 -#pragma Aux_register(0x800141c0, name=>"io_uart1_clken") - -// User extension aux register io_uart1_rbr_thr_dll -#define AR_IO_UART1_RBR_THR_DLL 0x80014100 -#pragma Aux_register(0x80014100, name=>"io_uart1_rbr_thr_dll") - -// User extension aux register io_uart1_ier_dlh -#define AR_IO_UART1_IER_DLH 0x80014104 -#pragma Aux_register(0x80014104, name=>"io_uart1_ier_dlh") - -// User extension aux register io_uart1_iir_fcr -#define AR_IO_UART1_IIR_FCR 0x80014108 -#pragma Aux_register(0x80014108, name=>"io_uart1_iir_fcr") - -// User extension aux register io_uart1_lcr -#define AR_IO_UART1_LCR 0x8001410c -#pragma Aux_register(0x8001410c, name=>"io_uart1_lcr") - -// User extension aux register io_uart1_mcr -#define AR_IO_UART1_MCR 0x80014110 -#pragma Aux_register(0x80014110, name=>"io_uart1_mcr") - -// User extension aux register io_uart1_lsr -#define AR_IO_UART1_LSR 0x80014114 -#pragma Aux_register(0x80014114, name=>"io_uart1_lsr") - -// User extension aux register io_uart1_msr -#define AR_IO_UART1_MSR 0x80014118 -#pragma Aux_register(0x80014118, name=>"io_uart1_msr") - -// User extension aux register io_uart1_usr -#define AR_IO_UART1_USR 0x8001417c -#pragma Aux_register(0x8001417c, name=>"io_uart1_usr") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_UART2_PRESENT 1 - -// User extension aux register io_uart2_clken -#define AR_IO_UART2_CLKEN 0x800142c0 -#pragma Aux_register(0x800142c0, name=>"io_uart2_clken") - -// User extension aux register io_uart2_rbr_thr_dll -#define AR_IO_UART2_RBR_THR_DLL 0x80014200 -#pragma Aux_register(0x80014200, name=>"io_uart2_rbr_thr_dll") - -// User extension aux register io_uart2_ier_dlh -#define AR_IO_UART2_IER_DLH 0x80014204 -#pragma Aux_register(0x80014204, name=>"io_uart2_ier_dlh") - -// User extension aux register io_uart2_iir_fcr -#define AR_IO_UART2_IIR_FCR 0x80014208 -#pragma Aux_register(0x80014208, name=>"io_uart2_iir_fcr") - -// User extension aux register io_uart2_lcr -#define AR_IO_UART2_LCR 0x8001420c -#pragma Aux_register(0x8001420c, name=>"io_uart2_lcr") - -// User extension aux register io_uart2_mcr -#define AR_IO_UART2_MCR 0x80014210 -#pragma Aux_register(0x80014210, name=>"io_uart2_mcr") - -// User extension aux register io_uart2_lsr -#define AR_IO_UART2_LSR 0x80014214 -#pragma Aux_register(0x80014214, name=>"io_uart2_lsr") - -// User extension aux register io_uart2_msr -#define AR_IO_UART2_MSR 0x80014218 -#pragma Aux_register(0x80014218, name=>"io_uart2_msr") - -// User extension aux register io_uart2_usr -#define AR_IO_UART2_USR 0x8001427c -#pragma Aux_register(0x8001427c, name=>"io_uart2_usr") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_UART3_PRESENT 1 - -// User extension aux register io_uart3_clken -#define AR_IO_UART3_CLKEN 0x800143c0 -#pragma Aux_register(0x800143c0, name=>"io_uart3_clken") - -// User extension aux register io_uart3_rbr_thr_dll -#define AR_IO_UART3_RBR_THR_DLL 0x80014300 -#pragma Aux_register(0x80014300, name=>"io_uart3_rbr_thr_dll") - -// User extension aux register io_uart3_ier_dlh -#define AR_IO_UART3_IER_DLH 0x80014304 -#pragma Aux_register(0x80014304, name=>"io_uart3_ier_dlh") - -// User extension aux register io_uart3_iir_fcr -#define AR_IO_UART3_IIR_FCR 0x80014308 -#pragma Aux_register(0x80014308, name=>"io_uart3_iir_fcr") - -// User extension aux register io_uart3_lcr -#define AR_IO_UART3_LCR 0x8001430c -#pragma Aux_register(0x8001430c, name=>"io_uart3_lcr") - -// User extension aux register io_uart3_mcr -#define AR_IO_UART3_MCR 0x80014310 -#pragma Aux_register(0x80014310, name=>"io_uart3_mcr") - -// User extension aux register io_uart3_lsr -#define AR_IO_UART3_LSR 0x80014314 -#pragma Aux_register(0x80014314, name=>"io_uart3_lsr") - -// User extension aux register io_uart3_msr -#define AR_IO_UART3_MSR 0x80014318 -#pragma Aux_register(0x80014318, name=>"io_uart3_msr") - -// User extension aux register io_uart3_usr -#define AR_IO_UART3_USR 0x8001437c -#pragma Aux_register(0x8001437c, name=>"io_uart3_usr") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2S_RX_MST0_PRESENT 1 - -// User extension aux register io_i2s_rx_mst0_ier -#define AR_IO_I2S_RX_MST0_IER 0x8001a000 -#pragma Aux_register(0x8001a000, name=>"io_i2s_rx_mst0_ier") - -// User extension aux register io_i2s_rx_mst0_irer -#define AR_IO_I2S_RX_MST0_IRER 0x8001a004 -#pragma Aux_register(0x8001a004, name=>"io_i2s_rx_mst0_irer") - -// User extension aux register io_i2s_rx_mst0_cer -#define AR_IO_I2S_RX_MST0_CER 0x8001a00c -#pragma Aux_register(0x8001a00c, name=>"io_i2s_rx_mst0_cer") - -// User extension aux register io_i2s_rx_mst0_ccr -#define AR_IO_I2S_RX_MST0_CCR 0x8001a010 -#pragma Aux_register(0x8001a010, name=>"io_i2s_rx_mst0_ccr") - -// User extension aux register io_i2s_rx_mst0_rxffr -#define AR_IO_I2S_RX_MST0_RXFFR 0x8001a014 -#pragma Aux_register(0x8001a014, name=>"io_i2s_rx_mst0_rxffr") - -// User extension aux register io_i2s_rx_mst0_lrbr -#define AR_IO_I2S_RX_MST0_LRBR 0x8001a020 -#pragma Aux_register(0x8001a020, name=>"io_i2s_rx_mst0_lrbr") - -// User extension aux register io_i2s_rx_mst0_rrbr -#define AR_IO_I2S_RX_MST0_RRBR 0x8001a024 -#pragma Aux_register(0x8001a024, name=>"io_i2s_rx_mst0_rrbr") - -// User extension aux register io_i2s_rx_mst0_rer -#define AR_IO_I2S_RX_MST0_RER 0x8001a028 -#pragma Aux_register(0x8001a028, name=>"io_i2s_rx_mst0_rer") - -// User extension aux register io_i2s_rx_mst0_rcr -#define AR_IO_I2S_RX_MST0_RCR 0x8001a030 -#pragma Aux_register(0x8001a030, name=>"io_i2s_rx_mst0_rcr") - -// User extension aux register io_i2s_rx_mst0_isr -#define AR_IO_I2S_RX_MST0_ISR 0x8001a038 -#pragma Aux_register(0x8001a038, name=>"io_i2s_rx_mst0_isr") - -// User extension aux register io_i2s_rx_mst0_imr -#define AR_IO_I2S_RX_MST0_IMR 0x8001a03c -#pragma Aux_register(0x8001a03c, name=>"io_i2s_rx_mst0_imr") - -// User extension aux register io_i2s_rx_mst0_ror -#define AR_IO_I2S_RX_MST0_ROR 0x8001a040 -#pragma Aux_register(0x8001a040, name=>"io_i2s_rx_mst0_ror") - -// User extension aux register io_i2s_rx_mst0_rfcr -#define AR_IO_I2S_RX_MST0_RFCR 0x8001a048 -#pragma Aux_register(0x8001a048, name=>"io_i2s_rx_mst0_rfcr") - -// User extension aux register io_i2s_rx_mst0_rff -#define AR_IO_I2S_RX_MST0_RFF 0x8001a050 -#pragma Aux_register(0x8001a050, name=>"io_i2s_rx_mst0_rff") - -// User extension aux register io_i2s_rx_mst0_rxdma -#define AR_IO_I2S_RX_MST0_RXDMA 0x8001a1c0 -#pragma Aux_register(0x8001a1c0, name=>"io_i2s_rx_mst0_rxdma") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2S_TX_MST0_PRESENT 1 - -// User extension aux register io_i2s_tx_mst0_ier -#define AR_IO_I2S_TX_MST0_IER 0x80019000 -#pragma Aux_register(0x80019000, name=>"io_i2s_tx_mst0_ier") - -// User extension aux register io_i2s_tx_mst0_iter -#define AR_IO_I2S_TX_MST0_ITER 0x80019008 -#pragma Aux_register(0x80019008, name=>"io_i2s_tx_mst0_iter") - -// User extension aux register io_i2s_tx_mst0_cer -#define AR_IO_I2S_TX_MST0_CER 0x8001900c -#pragma Aux_register(0x8001900c, name=>"io_i2s_tx_mst0_cer") - -// User extension aux register io_i2s_tx_mst0_ccr -#define AR_IO_I2S_TX_MST0_CCR 0x80019010 -#pragma Aux_register(0x80019010, name=>"io_i2s_tx_mst0_ccr") - -// User extension aux register io_i2s_tx_mst0_txffr -#define AR_IO_I2S_TX_MST0_TXFFR 0x80019018 -#pragma Aux_register(0x80019018, name=>"io_i2s_tx_mst0_txffr") - -// User extension aux register io_i2s_tx_mst0_lthr -#define AR_IO_I2S_TX_MST0_LTHR 0x80019020 -#pragma Aux_register(0x80019020, name=>"io_i2s_tx_mst0_lthr") - -// User extension aux register io_i2s_tx_mst0_rthr -#define AR_IO_I2S_TX_MST0_RTHR 0x80019024 -#pragma Aux_register(0x80019024, name=>"io_i2s_tx_mst0_rthr") - -// User extension aux register io_i2s_tx_mst0_ter -#define AR_IO_I2S_TX_MST0_TER 0x8001902c -#pragma Aux_register(0x8001902c, name=>"io_i2s_tx_mst0_ter") - -// User extension aux register io_i2s_tx_mst0_tcr -#define AR_IO_I2S_TX_MST0_TCR 0x80019034 -#pragma Aux_register(0x80019034, name=>"io_i2s_tx_mst0_tcr") - -// User extension aux register io_i2s_tx_mst0_isr -#define AR_IO_I2S_TX_MST0_ISR 0x80019038 -#pragma Aux_register(0x80019038, name=>"io_i2s_tx_mst0_isr") - -// User extension aux register io_i2s_tx_mst0_imr -#define AR_IO_I2S_TX_MST0_IMR 0x8001903c -#pragma Aux_register(0x8001903c, name=>"io_i2s_tx_mst0_imr") - -// User extension aux register io_i2s_tx_mst0_tor -#define AR_IO_I2S_TX_MST0_TOR 0x80019044 -#pragma Aux_register(0x80019044, name=>"io_i2s_tx_mst0_tor") - -// User extension aux register io_i2s_tx_mst0_tfcr -#define AR_IO_I2S_TX_MST0_TFCR 0x8001904c -#pragma Aux_register(0x8001904c, name=>"io_i2s_tx_mst0_tfcr") - -// User extension aux register io_i2s_tx_mst0_tff -#define AR_IO_I2S_TX_MST0_TFF 0x80019054 -#pragma Aux_register(0x80019054, name=>"io_i2s_tx_mst0_tff") - -// User extension aux register io_i2s_tx_mst0_txdma -#define AR_IO_I2S_TX_MST0_TXDMA 0x800191c8 -#pragma Aux_register(0x800191c8, name=>"io_i2s_tx_mst0_txdma") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_PDM_RX0_PRESENT 1 - -// User extension aux register io_pdm_rx0_pdm_en -#define AR_IO_PDM_RX0_PDM_EN 0x8001b000 -#pragma Aux_register(0x8001b000, name=>"io_pdm_rx0_pdm_en") - -// User extension aux register io_pdm_rx0_pdm_ren -#define AR_IO_PDM_RX0_PDM_REN 0x8001b004 -#pragma Aux_register(0x8001b004, name=>"io_pdm_rx0_pdm_ren") - -// User extension aux register io_pdm_rx0_cer -#define AR_IO_PDM_RX0_CER 0x8001b00c -#pragma Aux_register(0x8001b00c, name=>"io_pdm_rx0_cer") - -// User extension aux register io_pdm_rx0_rxffr -#define AR_IO_PDM_RX0_RXFFR 0x8001b014 -#pragma Aux_register(0x8001b014, name=>"io_pdm_rx0_rxffr") - -// User extension aux register io_pdm_rx0_rer0 -#define AR_IO_PDM_RX0_RER0 0x8001b028 -#pragma Aux_register(0x8001b028, name=>"io_pdm_rx0_rer0") - -// User extension aux register io_pdm_rx0_isr -#define AR_IO_PDM_RX0_ISR 0x8001b038 -#pragma Aux_register(0x8001b038, name=>"io_pdm_rx0_isr") - -// User extension aux register io_pdm_rx0_imr -#define AR_IO_PDM_RX0_IMR 0x8001b03c -#pragma Aux_register(0x8001b03c, name=>"io_pdm_rx0_imr") - -// User extension aux register io_pdm_rx0_ror -#define AR_IO_PDM_RX0_ROR 0x8001b040 -#pragma Aux_register(0x8001b040, name=>"io_pdm_rx0_ror") - -// User extension aux register io_pdm_rx0_rfcr -#define AR_IO_PDM_RX0_RFCR 0x8001b048 -#pragma Aux_register(0x8001b048, name=>"io_pdm_rx0_rfcr") - -// User extension aux register io_pdm_rx0_rxdma -#define AR_IO_PDM_RX0_RXDMA 0x8001b1c0 -#pragma Aux_register(0x8001b1c0, name=>"io_pdm_rx0_rxdma") - -// User extension aux register io_pdm_rx0_pdm_rr -#define AR_IO_PDM_RX0_PDM_RR 0x8001b1d0 -#pragma Aux_register(0x8001b1d0, name=>"io_pdm_rx0_pdm_rr") - -// User extension aux register io_pdm_rx0_cic_n -#define AR_IO_PDM_RX0_CIC_N 0x8001b1d4 -#pragma Aux_register(0x8001b1d4, name=>"io_pdm_rx0_cic_n") - -// User extension aux register io_pdm_rx0_cic_d -#define AR_IO_PDM_RX0_CIC_D 0x8001b1d8 -#pragma Aux_register(0x8001b1d8, name=>"io_pdm_rx0_cic_d") - -// User extension aux register io_pdm_rx0_dcrc -#define AR_IO_PDM_RX0_DCRC 0x8001b1dc -#pragma Aux_register(0x8001b1dc, name=>"io_pdm_rx0_dcrc") - -// User extension aux register io_pdm_rx0_brc_b0 -#define AR_IO_PDM_RX0_BRC_B0 0x8001b1e0 -#pragma Aux_register(0x8001b1e0, name=>"io_pdm_rx0_brc_b0") - -// User extension aux register io_pdm_rx0_brc_clp -#define AR_IO_PDM_RX0_BRC_CLP 0x8001b1f0 -#pragma Aux_register(0x8001b1f0, name=>"io_pdm_rx0_brc_clp") -#define APEX_COM_ARC_HARDWARE_FLOATING_POINT_UNIT_FPU_PRESENT 1 - -// User extension aux register fpu_build -#define AR_FPU_BUILD 0xc8 -#pragma Aux_register(0xc8, name=>"fpu_build") - -// User extension aux register fpu_ctrl -#define AR_FPU_CTRL 0x300 -#pragma Aux_register(0x300, name=>"fpu_ctrl") - -// User extension aux register fpu_status -#define AR_FPU_STATUS 0x301 -#pragma Aux_register(0x301, name=>"fpu_status") - -// User extension instruction fsmadd -extern int fsmadd(int,int); -#pragma intrinsic(fsmadd,opcode=>6,sub_opcode=>5, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fsmsub -extern int fsmsub(int,int); -#pragma intrinsic(fsmsub,opcode=>6,sub_opcode=>6, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fsmul -extern int fsmul(int,int); -#pragma intrinsic(fsmul,opcode=>6,sub_opcode=>0, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fsadd -extern int fsadd(int,int); -#pragma intrinsic(fsadd,opcode=>6,sub_opcode=>1, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fssub -extern int fssub(int,int); -#pragma intrinsic(fssub,opcode=>6,sub_opcode=>2, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fcvt32 -extern int fcvt32(int,int); -#pragma intrinsic(fcvt32,opcode=>6,sub_opcode=>8, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fsdiv -extern int fsdiv(int,int); -#pragma intrinsic(fsdiv,opcode=>6,sub_opcode=>7, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fscmp -extern int fscmp(int,int); -#pragma intrinsic(fscmp,opcode=>6,sub_opcode=>3, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fscmp -extern int fscmp_f(int,int); -#pragma intrinsic(fscmp_f,opcode=>6,sub_opcode=>3, set_flags => 1, flags => "zncv", effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fscmpf -extern int fscmpf(int,int); -#pragma intrinsic(fscmpf,opcode=>6,sub_opcode=>4, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fscmpf -extern int fscmpf_f(int,int); -#pragma intrinsic(fscmpf_f,opcode=>6,sub_opcode=>4, set_flags => 1, flags => "zncv", effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fssqrt -extern int fssqrt(int); -#pragma intrinsic(fssqrt,opcode=>6,sub_opcode=>0, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") -#define APEX_COM_ARC_HARDWARE_FLOATING_POINT_UNIT_FPU_DP_ASSIST_PRESENT 1 - -// User extension aux register aux_dpfp1l -#define AR_AUX_DPFP1L 0x302 -#pragma Aux_register(0x302, name=>"aux_dpfp1l") - -// User extension aux register aux_dpfp1h -#define AR_AUX_DPFP1H 0x303 -#pragma Aux_register(0x303, name=>"aux_dpfp1h") - -// User extension aux register aux_dpfp2l -#define AR_AUX_DPFP2L 0x304 -#pragma Aux_register(0x304, name=>"aux_dpfp2l") - -// User extension aux register aux_dpfp2h -#define AR_AUX_DPFP2H 0x305 -#pragma Aux_register(0x305, name=>"aux_dpfp2h") - -// User extension instruction dmulh11 -extern int dmulh11(int,int); -#pragma intrinsic(dmulh11,opcode=>6,sub_opcode=>48,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh11 -extern int dmulh11_f(int,int); -#pragma intrinsic(dmulh11_f,opcode=>6,sub_opcode=>48, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh12 -extern int dmulh12(int,int); -#pragma intrinsic(dmulh12,opcode=>6,sub_opcode=>49,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh12 -extern int dmulh12_f(int,int); -#pragma intrinsic(dmulh12_f,opcode=>6,sub_opcode=>49, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh21 -extern int dmulh21(int,int); -#pragma intrinsic(dmulh21,opcode=>6,sub_opcode=>50,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh21 -extern int dmulh21_f(int,int); -#pragma intrinsic(dmulh21_f,opcode=>6,sub_opcode=>50, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh22 -extern int dmulh22(int,int); -#pragma intrinsic(dmulh22,opcode=>6,sub_opcode=>51,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh22 -extern int dmulh22_f(int,int); -#pragma intrinsic(dmulh22_f,opcode=>6,sub_opcode=>51, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh11 -extern int daddh11(int,int); -#pragma intrinsic(daddh11,opcode=>6,sub_opcode=>52,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh11 -extern int daddh11_f(int,int); -#pragma intrinsic(daddh11_f,opcode=>6,sub_opcode=>52, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh12 -extern int daddh12(int,int); -#pragma intrinsic(daddh12,opcode=>6,sub_opcode=>53,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh12 -extern int daddh12_f(int,int); -#pragma intrinsic(daddh12_f,opcode=>6,sub_opcode=>53, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh21 -extern int daddh21(int,int); -#pragma intrinsic(daddh21,opcode=>6,sub_opcode=>54,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh21 -extern int daddh21_f(int,int); -#pragma intrinsic(daddh21_f,opcode=>6,sub_opcode=>54, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh22 -extern int daddh22(int,int); -#pragma intrinsic(daddh22,opcode=>6,sub_opcode=>55,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh22 -extern int daddh22_f(int,int); -#pragma intrinsic(daddh22_f,opcode=>6,sub_opcode=>55, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh11 -extern int dsubh11(int,int); -#pragma intrinsic(dsubh11,opcode=>6,sub_opcode=>56,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh11 -extern int dsubh11_f(int,int); -#pragma intrinsic(dsubh11_f,opcode=>6,sub_opcode=>56, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh12 -extern int dsubh12(int,int); -#pragma intrinsic(dsubh12,opcode=>6,sub_opcode=>57,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh12 -extern int dsubh12_f(int,int); -#pragma intrinsic(dsubh12_f,opcode=>6,sub_opcode=>57, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh21 -extern int dsubh21(int,int); -#pragma intrinsic(dsubh21,opcode=>6,sub_opcode=>58,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh21 -extern int dsubh21_f(int,int); -#pragma intrinsic(dsubh21_f,opcode=>6,sub_opcode=>58, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh22 -extern int dsubh22(int,int); -#pragma intrinsic(dsubh22,opcode=>6,sub_opcode=>59,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh22 -extern int dsubh22_f(int,int); -#pragma intrinsic(dsubh22_f,opcode=>6,sub_opcode=>59, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dexcl1 -extern int dexcl1(int,int); -#pragma intrinsic(dexcl1,opcode=>6,sub_opcode=>60, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dexcl2 -extern int dexcl2(int,int); -#pragma intrinsic(dexcl2,opcode=>6,sub_opcode=>61, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - - -#endif - - diff --git a/board/emsdp/rev1/configs/em7d_esp_dfss/core_hardware.h b/board/emsdp/rev1/configs/em7d_esp_dfss/core_hardware.h deleted file mode 100644 index 6ab8701fa..000000000 --- a/board/emsdp/rev1/configs/em7d_esp_dfss/core_hardware.h +++ /dev/null @@ -1,71 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------- */ -#ifndef _CORE_HARDWARE_H_ -#define _CORE_HARDWARE_H_ - -#define EMSDP_SPI0_INTR (84) -#define EMSDP_SPI1_INTR (85) -#define EMSDP_GPIO_INTR0 (86) -#define EMSDP_GPIO_INTR1 (87) -#define EMSDP_GPIO_INTR2 (88) -#define EMSDP_GPIO_INTR3 (89) -#define EMSDP_TIMER0_INTR0 (90) -#define EMSDP_TIMER0_INTR1 (91) -#define EMSDP_TIMER0_INTR2 (92) -#define EMSDP_TIMER0_INTR3 (93) -#define EMSDP_TIMER0_INTR4 (94) -#define EMSDP_TIMER0_INTR5 (95) -#define EMSDP_TIMER0_INTR6 (96) -#define EMSDP_TIMER0_INTR7 (97) -#define EMSDP_TIMER1_INTR0 (98) -#define EMSDP_TIMER1_INTR1 (99) -#define EMSDP_TIMER1_INTR2 (100) -#define EMSDP_TIMER1_INTR3 (101) -#define EMSDP_TIMER1_INTR4 (102) -#define EMSDP_TIMER1_INTR5 (103) -#define EMSDP_TIMER1_INTR6 (104) -#define EMSDP_TIMER1_INTR7 (105) -#define EMSDP_UART_INTR (106) -#define EMSDP_WDT_INTR (107) -#define EMSDP_DBG_UART_INTR (108) -#define EMSDP_SDIO_INTR (109) -#define EMSDP_REDPINE_SPI_INTR (110) -#define EMSDP_REDPINE_HOST_WAKEUP (111) -#define EMSDP_NIST_TRNG_INTR (112) - -//EMSDP Peripheral Subsystem DMA assignments -#define UART_DMA_TX (9) -#define UART_DMA_RX (10) -#define REDPINE_SPI_DMA_TX (11) -#define REDPINE_SPI_DMA_RX (12) -#define FLASH_SPI_DMA_TX (13) -#define FLASH_SPI_DMA_RX (14) - -#endif /* _CORE_HARDWARE_H_ */ diff --git a/board/emsdp/rev1/configs/em7d_esp_dfss/dsp_config.h b/board/emsdp/rev1/configs/em7d_esp_dfss/dsp_config.h deleted file mode 100644 index 02a69fd24..000000000 --- a/board/emsdp/rev1/configs/em7d_esp_dfss/dsp_config.h +++ /dev/null @@ -1,15 +0,0 @@ - -/* **** DO NOT EDIT - this file is generated by ARChitect2 **** - * - * Description: Header file declaring the compiler extensions for eia components - */ - -#ifndef _dsp_config_H_ -#define _dsp_config_H_ - - -#define DSP_TRIG_PRESENT - -#endif - - diff --git a/board/emsdp/rev1/configs/em7d_esp_dfss/io_config.h b/board/emsdp/rev1/configs/em7d_esp_dfss/io_config.h deleted file mode 100644 index 5f55d3d9f..000000000 --- a/board/emsdp/rev1/configs/em7d_esp_dfss/io_config.h +++ /dev/null @@ -1,121 +0,0 @@ - -/* **** DO NOT EDIT - this file is generated by ARChitect2 **** - * - * Description: Header file declaring the compiler extensions for eia components - */ - -#ifndef _io_config_H_ -#define _io_config_H_ - - -#define DMAC_INT_BASE (20) -#define DMAC_ERR_BASE (DMAC_INT_BASE + DMAC_CHAN_CNT) -#define DMAC_CHAN_CNT (16) -#define DMAC_MEM_CHAN_CNT (16) -#define DMAC_AUX_CHAN_CNT (0) -#define IO_I2C_SLV0_PRESENT -#define IO_I2C_SLV0_FS (16) -#define IO_I2C_SLV0_INT_ERR (51) -#define IO_I2C_SLV0_INT_RX_AVAIL (52) -#define IO_I2C_SLV0_INT_TX_REQ (53) -#define IO_I2C_SLV0_INT_RD_REQ (54) -#define IO_I2C_SLV0_INT_STOP_DET (55) -#define IO_I2C_SLV0_INT_RESTART_DET (56) -#define IO_SPI_MST0_PRESENT -#define IO_SPI_MST0_FS (16) -#define IO_SPI_MST0_MAX_XFER_SIZE (16) -#define IO_SPI_MST0_DMA_TX (3) -#define IO_SPI_MST0_DMA_RX (4) -#define IO_SPI_MST0_INT_ERR (64) -#define IO_SPI_MST0_INT_RX_AVAIL (65) -#define IO_SPI_MST0_INT_TX_REQ (66) -#define IO_SPI_MST0_INT_IDLE (67) -#define IO_SPI_SLV0_PRESENT -#define IO_SPI_SLV0_FS (16) -#define IO_SPI_SLV0_MAX_XFER_SIZE (16) -#define IO_SPI_SLV0_DMA_TX (7) -#define IO_SPI_SLV0_DMA_RX (8) -#define IO_SPI_SLV0_INT_ERR (76) -#define IO_SPI_SLV0_INT_RX_AVAIL (77) -#define IO_SPI_SLV0_INT_TX_REQ (78) -#define IO_SPI_SLV0_INT_IDLE (79) -#define IO_I2C_MST0_PRESENT -#define IO_I2C_MST0_FS (16) -#define IO_I2C_MST0_INT_ERR (39) -#define IO_I2C_MST0_INT_RX_AVAIL (40) -#define IO_I2C_MST0_INT_TX_REQ (41) -#define IO_I2C_MST0_INT_STOP_DET (42) -#define IO_GPIO0_PRESENT -#define IO_GPIO0_INT_INTR_FLAG (17) -#define IO_GPIO0_DEBOUNCE (1) -#define IO_UART0_PRESENT -#define IO_UART0_FS (16) -#define IO_UART0_INTR (80) -#define IO_I2S_TX_MST0_PRESENT -#define IO_I2S_TX_MST0_FS (8) -#define IO_I2S_TX_MST0_FW (16) -#define IO_I2S_TX_MST0_INT_TX_REQ (59) -#define IO_I2S_TX_MST0_INT_ERR (60) -#define IO_I2S_TX_MST0_DMA (1) -#define IO_I2S_RX_MST0_PRESENT -#define IO_I2S_RX_MST0_FS (8) -#define IO_I2S_RX_MST0_FW (16) -#define IO_I2S_RX_MST0_INT_RX_AVAIL (57) -#define IO_I2S_RX_MST0_INT_ERR (58) -#define IO_I2S_RX_MST0_DMA (0) -#define IO_PDM_RX0_PRESENT -#define IO_PDM_RX0_CH (1) -#define IO_PDM_RX0_FS (16) -#define IO_PDM_RX0_NS (4) -#define IO_PDM_RX0_DS (2) -#define IO_PDM_RX0_INT_RX_AVAIL (61) -#define IO_PDM_RX0_INT_ERR (62) -#define IO_PDM_RX0_INT_CLP (63) -#define IO_PDM_RX0_DMA (2) -#define IO_SPI_MST1_PRESENT -#define IO_SPI_MST1_FS (16) -#define IO_SPI_MST1_MAX_XFER_SIZE (16) -#define IO_SPI_MST1_DMA_TX (5) -#define IO_SPI_MST1_DMA_RX (6) -#define IO_SPI_MST1_INT_ERR (68) -#define IO_SPI_MST1_INT_RX_AVAIL (69) -#define IO_SPI_MST1_INT_TX_REQ (70) -#define IO_SPI_MST1_INT_IDLE (71) -#define IO_I2C_MST1_PRESENT -#define IO_I2C_MST1_FS (16) -#define IO_I2C_MST1_INT_ERR (43) -#define IO_I2C_MST1_INT_RX_AVAIL (44) -#define IO_I2C_MST1_INT_TX_REQ (45) -#define IO_I2C_MST1_INT_STOP_DET (46) -#define IO_GPIO1_PRESENT -#define IO_GPIO1_INT_INTR_FLAG (19) -#define IO_GPIO1_DEBOUNCE (1) -#define IO_UART1_PRESENT -#define IO_UART1_FS (16) -#define IO_UART1_INTR (81) -#define IO_SPI_MST2_PRESENT -#define IO_SPI_MST2_FS (16) -#define IO_SPI_MST2_MAX_XFER_SIZE (16) -#define IO_SPI_MST2_INT_ERR (72) -#define IO_SPI_MST2_INT_RX_AVAIL (73) -#define IO_SPI_MST2_INT_TX_REQ (74) -#define IO_SPI_MST2_INT_IDLE (75) -#define IO_I2C_MST2_PRESENT -#define IO_I2C_MST2_FS (16) -#define IO_I2C_MST2_INT_ERR (47) -#define IO_I2C_MST2_INT_RX_AVAIL (48) -#define IO_I2C_MST2_INT_TX_REQ (49) -#define IO_I2C_MST2_INT_STOP_DET (50) -#define IO_GPIO2_PRESENT -#define IO_GPIO2_INT_INTR_FLAG (21) -#define IO_GPIO2_DEBOUNCE (1) -#define IO_UART2_PRESENT -#define IO_UART2_FS (16) -#define IO_UART2_INTR (82) -#define IO_UART3_PRESENT -#define IO_UART3_FS (16) -#define IO_UART3_INTR (83) - -#endif - - diff --git a/board/emsdp/rev1/configs/em7d_esp_dfss/tcf/em7d_esp_dfss.tcf b/board/emsdp/rev1/configs/em7d_esp_dfss/tcf/em7d_esp_dfss.tcf deleted file mode 100644 index 5d1ebc834..000000000 --- a/board/emsdp/rev1/configs/em7d_esp_dfss/tcf/em7d_esp_dfss.tcf +++ /dev/null @@ -1,4839 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - -# -# option 16/L32/U32 Instructions -# ------ ---------- --------------------- -# -# none -/-/- None -# wlh1 1/1/1 MPYW/U, MPY/U, MPYH/U -# wlh2 2/2/2 MPYW/U, MPY/U, MPYH/U -# wlh3 2/3/3 MPYW/U, MPY/U, MPYH/U -# wlh4 2/4/5 MPYW/U, MPY/U, MPYH/U -# wlh5 5/9/9 MPYW/U, MPY/U, MPYH/U -# -# --mpy_option none - -# code_protection --- The ARC EM architecture divides the memory into 16 regions, which can be protected individually. This feature adds a 16-bit input to the processor core, one bit per region. When the protect bit is set, the processor disables any load or store to the corresponding region. An attempt to access a protected region raises an EV_ProtV exception. --code_protection false - -# stack_checking --- Stack checking is a mechanism for checking stack accesses and raising an exception when a stack overflow or underflow is detected. --stack_checking true - -# unaligned_option --- This enables unaligned loads and stores. --unaligned_option false - -# intvbase_preset --- This sets the interrupt vector base configuration register, VECBASE_AC_BUILD. The vector base address is aligned to a 1KB boundary, so the required address value should be divided by 1K (i.e. do not include the lower 10 bits). On reset, this register is loaded into the interrupt vector base address register, INT_VECTOR_BASE. --intvbase_preset 0x1 - -# intvbase_preset_s --- This sets the secure interrupt vector base configuration register, VECBASE_AC_BUILD. The vector base address is aligned to a 1KB boundary, so the required address value should be divided by 1K (i.e. do not include the lower 10 bits). On reset, this register is loaded into the interrupt vector base address register, INT_VECTOR_BASE_S.This is effective only when 2+2 mode is enabled. --intvbase_preset_s 0x0 - -# intvbase_ext --- Set this option to drive the upper 22 bits of the interrupt base vector externally, into signal intvbase_in. --intvbase_ext false - -# nmi_option --- add Non-maskable external exception support --nmi_option false - -# rgf_impl --- This defines whether the register file is implemented using flip-flops, or with a hard macro. --rgf_impl flip_flops - -# rgf_num_regs --- This defines the size (in 32b register) of the processor register file. --rgf_num_regs 32 - -# rgf_wr_ports --- This defines the number of write ports on the register file. --rgf_wr_ports 1 - -# rgf_num_banks --- Dual register banks are useful if Fast IRQ has been configured, but may be selected even if not. --rgf_num_banks 1 - -# rgf_banked_regs --- This selects the number of registers that are replicated in the second register-file bank. --rgf_banked_regs 32 - -# turbo_boost --- This enables the Turbo Boost synthesis option. By enabling this option, the achievable clock frequency is increased, but at the cost of an additional cycle latency on branch instructions. --turbo_boost true - -# infer_alu_adder --- infer: datapath is described as behavioral code: A + B -# instantiate: datapath is instantiated as a detailed multi-stage code of a carry-lookahead adder. It is generally preferable to use the infer option and add directives for your target synthesizer. --infer_alu_adder infer - -# infer_mpy_wtree --- infer: datapath is described as behavioral code: A * B (applies to only wlh3, wlh4 and wlh5 designs) -# instantiate: datapath is instantiated as a detailed multi-stage code of a Wallace Tree multiplier It is generally preferable to use the infer option and add directives for your target synthesizer. --infer_mpy_wtree instantiate - -# scantest_ram_bypass_mux --- This mux is used to make logic trapped between flops and memory (aka shadow logic) to be covered by scantest without requiring advanced sequential ATPG on the memory to be applied. Will add delay to functional access time --scantest_ram_bypass_mux false - -# logic_bist --- This option will OR LBIST_EN with test_mode --logic_bist false - -# power_domains --- Adds three separate power domains to the core, and propagates power-gate control signals to the top level of the core. Also generates UPF constraints and commands in the low-power scripts --power_domains false - -# dvfs --- Adds logic to the core to allow dynamic controlling of voltage and frequency and propagates the associated control signals to the top level of core --dvfs false - -# voltage_domains --- Creates a voltage domain split between RAM and std cell parts to support Ultra Low Voltage on cells and generates UPF constraints --voltage_domains false - -# mem_bus_option --- The core supports two bus protocols for accessing external memory: AHB & AHB-Lite. AHB-Lite-single means instruction fetch and data access share a single AHB-Lite port. AHB-Lite-dual means separate AHB-Lite port for each initiator if present. --mem_bus_option AHB-Lite-dual - -# mem_bus_reg_interface --- Specifies whether the memory bus interface is registered. --mem_bus_reg_interface true - -# dmi_burst_option --- This will enable high-throughput burst support on the DMI slave interfaces. By enabling this option, the peak DMI read throughput goes from 1 word per 3 cycles to N words per N+2 cycles, in which N is the AHB burst lengthDMI write throughput goes from 1 word per 3 cycles to 1 word per cycle. --dmi_burst_option true - -# has_dmp_peripheral --- This option enables the redirection of load/store accesses to one segment (1/16) of the addressable space to a dedicated peripheral bus. This offers high system integration and reduces overall system cost. --has_dmp_peripheral true - -# per0_base --- This option specifies the memory region assignment for this peripheral aperture --per0_base 15 - -# per0_limit --- This option specifies the end of this peripheral aperture --per0_limit 0 - -# per_bus_option --- The core supports one bus protocol for accessing the peripheral space, when enabled: AHB-Lite. --per_bus_option AHB-Lite - -# per_bus_reg_interface --- Specifies whether the peripheral bus interface is registered. --per_bus_reg_interface true - -# clock_gating --- This enables the insertion of architectural clock gate elements in the design. By enabling this option, the clocks to various parts of the design will be disabled when the logic they drive is not in use to save power. --clock_gating false - -# back_compat --- This enables the addition of rst_a input in the clkgate module to support backward compatibility with the older EM and Subsystem releases. --back_compat true - -# byte_parity --- If parity protection on the CCMs is configured, this option is used to enable parity protection on a per-byte basis. Otherwise, parity will be per word basis --byte_parity false - -# prot_pipelined --- Check the box if CCM memories are configured for ECC, and you want single-bit errors to be corrected, written back to memory, and re-fetched. When unchecked, single bit errors are corrected when read from memory, but the offending memory location itself is not corrected with a writeback, no influence on Cache protection --prot_pipelined false - -# cct_test_ena --- When ECC is configured, this option enables single bit error injection in CCT RAM models to demonstrate ECC protection on the RAMs. When enabled, the RAM models can only be used in HDL CCT simulation (no xCAM support) and are not intended for use in SoC level integration. --cct_test_ena false - -# err_prot_ehce --- Enabled enhanced ECC architecture for CCM. Instruction fetch with single bit error is not replayed; ecc cac modules are shared to reduce area and timing opt. --err_prot_ehce false - - -######## dsp_sincos --- com.arc.hardware.dfss.dsp_sincos.1_0 ######## - -# Create dsp_sincos --create com.arc.hardware.dfss.dsp_sincos.1_0 System.CPUisle.ARCv2EM.dsp_sincos - -# dsp_sincos --- Command line option for APEX extension component 'dsp_sincos'. --dsp_sincos true - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_gpio0 --- com.arc.hardware.dfss.io_gpio0.1_0 ######## - -# Create io_gpio0 --create com.arc.hardware.dfss.io_gpio0.1_0 System.CPUisle.ARCv2EM.io_gpio0 - -# io_gpio0 --- Command line option for EIA extension component 'io_gpio0'. --io_gpio0 true - -# io_gpio0_debounce --- Selects the inclusion of Debounce logic --io_gpio0_debounce 1 - -# io_gpio0_readback_sync --- Selects the inclusion of metastability registers on the read back path when reading the external 'ext_porta' signal --io_gpio0_readback_sync 1 - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - -# io_gpio0_direction_rst_value --- Reset value of the SWPORTA_DDR register, which determines the direction (input/output) of the GPIO interface. 0: input, 1: output. --io_gpio0_direction_rst_value 0 - -# io_gpio0_output_rst_value --- Reset value of the SWPORTA_DR register, which determines the reset value of the GPIO output ports. Bits corresponding to input ports are ignored. --io_gpio0_output_rst_value 0x0 - - -######## io_i2c_mst0 --- com.arc.hardware.dfss.io_i2c_mst0.1_0 ######## - -# Create io_i2c_mst0 --create com.arc.hardware.dfss.io_i2c_mst0.1_0 System.CPUisle.ARCv2EM.io_i2c_mst0 - -# io_i2c_mst0 --- Command line option for APEX extension component 'io_i2c_mst0'. --io_i2c_mst0 true - -# io_i2c_mst0_fs --- RX/TX FIFO size --io_i2c_mst0_fs 16 - -# io_i2c_mst0_dma_support --- Specifies whether the DMA handshake interface is included --io_i2c_mst0_dma_support None - -# io_i2c_mst0_cdc_included --- Selects whether a clock-domain crossing (CDC) is included between the core clock and the serial clock. If no CDC is present, both clocks must be synchronous. Otherwise the core clock frequency may be higher than, lower than or equal to the serial clock frequency. --io_i2c_mst0_cdc_included 0 - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_i2c_slv0 --- com.arc.hardware.dfss.io_i2c_slv0.1_0 ######## - -# Create io_i2c_slv0 --create com.arc.hardware.dfss.io_i2c_slv0.1_0 System.CPUisle.ARCv2EM.io_i2c_slv0 - -# io_i2c_slv0 --- Command line option for APEX extension component 'io_i2c_slv0'. --io_i2c_slv0 true - -# io_i2c_slv0_fs --- RX/TX FIFO size --io_i2c_slv0_fs 16 - -# io_i2c_slv0_dma_support --- Specifies whether the DMA handshake interface is included --io_i2c_slv0_dma_support None - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_spi_mst0 --- com.arc.hardware.dfss.io_spi_mst0.1_0 ######## - -# Create io_spi_mst0 --create com.arc.hardware.dfss.io_spi_mst0.1_0 System.CPUisle.ARCv2EM.io_spi_mst0 - -# io_spi_mst0 --- Command line option for APEX extension component 'io_spi_mst0'. --io_spi_mst0 true - -# io_spi_mst0_fz --- RX/TX FIFO depth --io_spi_mst0_fs 16 - -# io_spi_mst0_max_xfer_size --- This defines the maximum number of bits per word at the serial data port, which determines the FIFO width. --io_spi_mst0_max_xfer_size 16 - -# io_spi_mst0_cdc_included --- Selects whether a clock-domain crossing (CDC) is included between the core clock and the peripheral clock. If no CDC is present, both clocks must be synchronous. Otherwise the core clock frequency may be higher than or equal to the peripheral clock frequency. --io_spi_mst0_cdc_included 0 - -# io_spi_mst0_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_spi_mst0_dma_support Memory-Based - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## subsys_bcr --- com.arc.hardware.dfss.subsys_bcr.1_0 ######## - -# Create subsys_bcr --create com.arc.hardware.dfss.subsys_bcr.1_0 System.CPUisle.ARCv2EM.subsys_bcr - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_spi_mst1 --- com.arc.hardware.dfss.io_spi_mst1.1_0 ######## - -# Create io_spi_mst1 --create com.arc.hardware.dfss.io_spi_mst1.1_0 System.CPUisle.ARCv2EM.io_spi_mst1 - -# io_spi_mst1 --- Command line option for APEX extension component 'io_spi_mst1'. --io_spi_mst1 true - -# io_spi_mst1_fz --- RX/TX FIFO depth --io_spi_mst1_fs 16 - -# io_spi_mst1_max_xfer_size --- This defines the maximum number of bits per word at the serial data port, which determines the FIFO width. --io_spi_mst1_max_xfer_size 16 - -# io_spi_mst1_cdc_included --- Selects whether a clock-domain crossing (CDC) is included between the core clock and the peripheral clock. If no CDC is present, both clocks must be synchronous. Otherwise the core clock frequency may be higher than or equal to the peripheral clock frequency. --io_spi_mst1_cdc_included 0 - -# io_spi_mst1_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_spi_mst1_dma_support Memory-Based - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_spi_mst2 --- com.arc.hardware.dfss.io_spi_mst2.1_0 ######## - -# Create io_spi_mst2 --create com.arc.hardware.dfss.io_spi_mst2.1_0 System.CPUisle.ARCv2EM.io_spi_mst2 - -# io_spi_mst2 --- Command line option for APEX extension component 'io_spi_mst2'. --io_spi_mst2 true - -# io_spi_mst2_fz --- RX/TX FIFO depth --io_spi_mst2_fs 16 - -# io_spi_mst2_max_xfer_size --- This defines the maximum number of bits per word at the serial data port, which determines the FIFO width. --io_spi_mst2_max_xfer_size 16 - -# io_spi_mst2_cdc_included --- Selects whether a clock-domain crossing (CDC) is included between the core clock and the peripheral clock. If no CDC is present, both clocks must be synchronous. Otherwise the core clock frequency may be higher than or equal to the peripheral clock frequency. --io_spi_mst2_cdc_included 0 - -# io_spi_mst2_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_spi_mst2_dma_support None - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_spi_slv0 --- com.arc.hardware.dfss.io_spi_slv0.1_0 ######## - -# Create io_spi_slv0 --create com.arc.hardware.dfss.io_spi_slv0.1_0 System.CPUisle.ARCv2EM.io_spi_slv0 - -# io_spi_slv0 --- Command line option for APEX extension component 'io_spi_slv0'. --io_spi_slv0 true - -# io_spi_slv0_fz --- RX/TX FIFO depth --io_spi_slv0_fs 16 - -# io_spi_slv0_max_xfer_size --- This defines the maximum number of bits per word at the serial data port, which determines the FIFO width. --io_spi_slv0_max_xfer_size 16 - -# io_spi_slv0_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_spi_slv0_dma_support Memory-Based - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_gpio1 --- com.arc.hardware.dfss.io_gpio1.1_0 ######## - -# Create io_gpio1 --create com.arc.hardware.dfss.io_gpio1.1_0 System.CPUisle.ARCv2EM.io_gpio1 - -# io_gpio1 --- Command line option for EIA extension component 'io_gpio1'. --io_gpio1 true - -# io_gpio1_debounce --- Selects the inclusion of Debounce logic --io_gpio1_debounce 1 - -# io_gpio1_readback_sync --- Selects the inclusion of metastability registers on the read back path when reading the external 'ext_porta' signal --io_gpio1_readback_sync 1 - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - -# io_gpio1_direction_rst_value --- Reset value of the SWPORTA_DDR register, which determines the direction (input/output) of the GPIO interface. 0: input, 1: output. --io_gpio1_direction_rst_value 0 - -# io_gpio1_output_rst_value --- Reset value of the SWPORTA_DR register, which determines the reset value of the GPIO output ports. Bits corresponding to input ports are ignored. --io_gpio1_output_rst_value 0x0 - - -######## io_gpio2 --- com.arc.hardware.dfss.io_gpio2.1_0 ######## - -# Create io_gpio2 --create com.arc.hardware.dfss.io_gpio2.1_0 System.CPUisle.ARCv2EM.io_gpio2 - -# io_gpio2 --- Command line option for EIA extension component 'io_gpio2'. --io_gpio2 true - -# io_gpio2_debounce --- Selects the inclusion of Debounce logic --io_gpio2_debounce 1 - -# io_gpio2_readback_sync --- Selects the inclusion of metastability registers on the read back path when reading the external 'ext_porta' signal --io_gpio2_readback_sync 1 - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - -# io_gpio2_direction_rst_value --- Reset value of the SWPORTA_DDR register, which determines the direction (input/output) of the GPIO interface. 0: input, 1: output. --io_gpio2_direction_rst_value 0 - -# io_gpio2_output_rst_value --- Reset value of the SWPORTA_DR register, which determines the reset value of the GPIO output ports. Bits corresponding to input ports are ignored. --io_gpio2_output_rst_value 0x0 - - -######## io_i2c_mst1 --- com.arc.hardware.dfss.io_i2c_mst1.1_0 ######## - -# Create io_i2c_mst1 --create com.arc.hardware.dfss.io_i2c_mst1.1_0 System.CPUisle.ARCv2EM.io_i2c_mst1 - -# io_i2c_mst1 --- Command line option for APEX extension component 'io_i2c_mst1'. --io_i2c_mst1 true - -# io_i2c_mst1_fs --- RX/TX FIFO size --io_i2c_mst1_fs 16 - -# io_i2c_mst1_dma_support --- Specifies whether the DMA handshake interface is included --io_i2c_mst1_dma_support None - -# io_i2c_mst1_cdc_included --- Selects whether a clock-domain crossing (CDC) is included between the core clock and the serial clock. If no CDC is present, both clocks must be synchronous. Otherwise the core clock frequency may be higher than, lower than or equal to the serial clock frequency. --io_i2c_mst1_cdc_included 0 - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_i2c_mst2 --- com.arc.hardware.dfss.io_i2c_mst2.1_0 ######## - -# Create io_i2c_mst2 --create com.arc.hardware.dfss.io_i2c_mst2.1_0 System.CPUisle.ARCv2EM.io_i2c_mst2 - -# io_i2c_mst2 --- Command line option for APEX extension component 'io_i2c_mst2'. --io_i2c_mst2 true - -# io_i2c_mst2_fs --- RX/TX FIFO size --io_i2c_mst2_fs 16 - -# io_i2c_mst2_dma_support --- Specifies whether the DMA handshake interface is included --io_i2c_mst2_dma_support None - -# io_i2c_mst2_cdc_included --- Selects whether a clock-domain crossing (CDC) is included between the core clock and the serial clock. If no CDC is present, both clocks must be synchronous. Otherwise the core clock frequency may be higher than, lower than or equal to the serial clock frequency. --io_i2c_mst2_cdc_included 0 - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_uart0 --- com.arc.hardware.dfss.io_uart0.1_0 ######## - -# Create io_uart0 --create com.arc.hardware.dfss.io_uart0.1_0 System.CPUisle.ARCv2EM.io_uart0 - -# io_uart0 --- Command line option for EIA extension component 'io_uart0'. --io_uart0 true - -# io_uart0_fifo_mode --- Set the UART FIFO mode --io_uart0_fifo_mode 16 - -# io_uart0_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_uart0_dma_support None - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_uart1 --- com.arc.hardware.dfss.io_uart1.1_0 ######## - -# Create io_uart1 --create com.arc.hardware.dfss.io_uart1.1_0 System.CPUisle.ARCv2EM.io_uart1 - -# io_uart1 --- Command line option for EIA extension component 'io_uart1'. --io_uart1 true - -# io_uart1_fifo_mode --- Set the UART FIFO mode --io_uart1_fifo_mode 16 - -# io_uart1_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_uart1_dma_support None - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_uart2 --- com.arc.hardware.dfss.io_uart2.1_0 ######## - -# Create io_uart2 --create com.arc.hardware.dfss.io_uart2.1_0 System.CPUisle.ARCv2EM.io_uart2 - -# io_uart2 --- Command line option for EIA extension component 'io_uart2'. --io_uart2 true - -# io_uart2_fifo_mode --- Set the UART FIFO mode --io_uart2_fifo_mode 16 - -# io_uart2_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_uart2_dma_support None - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_uart3 --- com.arc.hardware.dfss.io_uart3.1_0 ######## - -# Create io_uart3 --create com.arc.hardware.dfss.io_uart3.1_0 System.CPUisle.ARCv2EM.io_uart3 - -# io_uart3 --- Command line option for EIA extension component 'io_uart3'. --io_uart3 true - -# io_uart3_fifo_mode --- Set the UART FIFO mode --io_uart3_fifo_mode 16 - -# io_uart3_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_uart3_dma_support None - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_i2s_rx_mst0 --- com.arc.hardware.dfss.io_i2s_rx_mst0.1_0 ######## - -# Create io_i2s_rx_mst0 --create com.arc.hardware.dfss.io_i2s_rx_mst0.1_0 System.CPUisle.ARCv2EM.io_i2s_rx_mst0 - -# io_i2s_rx_mst0 --- Command line option for APEX extension component 'io_i2s_rx_mst0'. --io_i2s_rx_mst0 true - -# io_i2s_rx_mst0_fs --- RX FIFO size --io_i2s_rx_mst0_fs 8 - -# io_i2s_rx_mst0_fw --- RX FIFO width --io_i2s_rx_mst0_fw 16 - -# io_i2s_rx_mst0_dma_support --- Specifies whether the DMA handshake interface is included --io_i2s_rx_mst0_dma_support Memory-Based - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_i2s_tx_mst0 --- com.arc.hardware.dfss.io_i2s_tx_mst0.1_0 ######## - -# Create io_i2s_tx_mst0 --create com.arc.hardware.dfss.io_i2s_tx_mst0.1_0 System.CPUisle.ARCv2EM.io_i2s_tx_mst0 - -# io_i2s_tx_mst0 --- Command line option for APEX extension component 'io_i2s_tx_mst0'. --io_i2s_tx_mst0 true - -# io_i2s_tx_mst0_fs --- TX FIFO size --io_i2s_tx_mst0_fs 8 - -# io_i2s_tx_mst0_fw --- TX FIFO width --io_i2s_tx_mst0_fw 16 - -# io_i2s_tx_mst0_dma_support --- Specifies whether the DMA handshake interface is included --io_i2s_tx_mst0_dma_support Memory-Based - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_pdm_rx0 --- com.arc.hardware.dfss.io_pdm_rx0.1_0 ######## - -# Create io_pdm_rx0 --create com.arc.hardware.dfss.io_pdm_rx0.1_0 System.CPUisle.ARCv2EM.io_pdm_rx0 - -# io_pdm_rx0 --- Command line option for APEX extension component 'io_pdm_rx0'. --io_pdm_rx0 true - -# io_pdm_rx0_ch --- Number of Stereo Channels --io_pdm_rx0_ch 1 - -# io_pdm_rx0_fs --- RX FIFO size --io_pdm_rx0_fs 16 - -# io_pdm_rx0_ns --- Maximum number of CIC stages --io_pdm_rx0_ns 4 - -# io_pdm_rx0_ds --- Maximum delay in the COMB filter of the CIC filter --io_pdm_rx0_ds 2 - -# io_pdm_rx0_dma_support --- Specifies whether the DMA handshake interface is included --io_pdm_rx0_dma_support Memory-Based - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## DCCM --- com.arc.hardware.DCCM.1_0 ######## - -# Create DCCM --create com.arc.hardware.DCCM.1_0 System.CPUisle.ARCv2EM.DCCM - -# dccm_size --- This defines the size of the Data Closely Coupled Memory (DCCM) in bytes --dccm_size 131072 - -# dccm_base --- Sets the initial memory region assignment for DCCM --dccm_base 8 - -# dccm_interleave --- Split DCCM into even/odd memory banks. --dccm_interleave false - -# dccm_prot --- Specifies the type of protection built for the DCCM. --dccm_prot None - -# dccm_prot_level --- Specifies the level protection. --dccm_prot_level Data_Only - -# dccm_prot_exceptions --- When the core is configured with ECC or Parity, cause exception generation hardware to be created for uncorrectable errors detected on the DCCM --dccm_prot_exceptions true - -# dccm_sec_lvl --- Specifies the level of secure DCCM. --dccm_sec_lvl Non_Secure - -# dccm_dmi --- This enables external access through a DMI (direct memory interface) port. --dccm_dmi true - - -######## DMA Controller --- com.arc.hardware.DMA_Controller.1_0 ######## - -# Create DMA Controller --create com.arc.hardware.DMA_Controller.1_0 "System.CPUisle.ARCv2EM.DMA Controller" - -# dmac_channels --- This options specifies the number of DMA channels implemented in the DMA controller --dmac_channels 16 - -# dmac_fifo_depth --- This option specifies the DMA transfer FIFO depth in 32b words. --dmac_fifo_depth 2 - -# dmac_int_config --- None: the DMA controller cannot raise an interrupt -# Single-External: single done and single error interrupt signal for all DMA channels, and the interrupt signals are routed to a port at the top of the EM logical hierarchy -# Multiple-External: each DMA channel can be configured to raise separate (per-channel) done and error interrupts, and the interrupt signals are routed to ports at the top of the EM logical hierarchy -# Single-Internal: single done and single error interrupt signals for all DMA channels, and the interrupt signals are internal to the EM core -# Multiple-Internal: each DMA channel can be configured to raise separate (per-channel) done and error interrupts, and the interrupt signals are internal to the EM core --dmac_int_config Multiple-Internal - -# dmac_separate_error_interrupts --- This specifies whether there is a separate error interrupt per DMA channel, or just one. --dmac_separate_error_interrupts false - -# dmac_registers --- This option defines the number of DMA channels with their registers located in auxiliary space. --dmac_registers 0 - -# dmac_mem_if --- This option specifies whether the DMA controller system memory interface is integrated into the existing EM system memory interfaces or has its own interface. --dmac_mem_if integrated - -# dmac_per_if --- Internal vs DW peripheral interface. Specify (in hex) which channels have the DW interface, where bit 0 corresponds to DMA channel 0, bit 1 for DMA channel 1, etc. -# Example: 4 channel DMA controller where -dmac_per_if is set to 0x9 = DMA Channels 0 and 3 configured with the DW req interface, DMA Channels 1 and 2 configured with the internal req interface. --dmac_per_if 0x7e00 - - -######## DSP --- com.arc.hardware.DSP.1_0 ######## - -# Create DSP --create com.arc.hardware.DSP.1_0 System.CPUisle.ARCv2EM.DSP - -# dsp_complex --- Enable/disable support for single cycle 16b+16b complex instructions and butterfly operations, else 2-cycle complex instructions only without butterfly support --dsp_complex true - -# dsp_itu --- Enable/disable support for ITU bit-accurate 1 bit fractional shift before accumulation, else 1-bit fractional shift result after accumulation only --dsp_itu true - -# dsp_divsqrt --- Enable/disable support for divide and square root operations: DIV(U), REM(U), SQRT --dsp_divsqrt radix2 - -# dsp_accshift --- Select support for accumulator shift operations: no supported, limited shift support only or full shift support and convergent rounding --dsp_accshift full - -# dsp_impl --- The datapath components may be inferred from Verilog for better area or optimized using carry-save components for better timing --dsp_impl optimized - - -######## Data Cache --- com.arc.hardware.Data_Cache.1_0 ######## - -# Create Data Cache --create com.arc.hardware.Data_Cache.1_0 "System.CPUisle.ARCv2EM.Data Cache" - -# dc_size --- This defines the total size of the Data Cache in bytes. --dc_size 16384 - -# dc_ways --- This defines the number of cache ways. --dc_ways 2 - -# dc_bsize --- This defines the cache line length in bytes. --dc_bsize 32 - -# dc_feature_level --- Feature Level, indicates locking and debug feature level 00 = Basic cache, with no locking or debug features 01 = Lock and flush features supported 10 = Lock, flush and advanced debug features supported 11 = Reserved --dc_feature_level 2 - -# dc_uncached_region --- Enable an uncached region defined by aux reg --dc_uncached_region false - -# dc_prot --- Specifies the type of protection built for DCACHE. --dc_prot None - -# dc_prot_level --- Specifies the level of protection. --dc_prot_level Data_Only - -# dc_prot_exceptions --- Builds exception generation hardware for uncorrectable (fatal) errors detected on DCACHE. --dc_prot_exceptions true - - -######## Debug Interface --- com.arc.hardware.Debug_Interface.1_0 ######## - -# Create Debug Interface --create com.arc.hardware.Debug_Interface.1_0 "System.CPUisle.ARCv2EM.Debug Interface" - -# dbg_en_option --- Adds an enable pin to the existing debug interface --dbg_en_option false - -# secure_debug --- This enables secure debug feature --secure_debug true - -# scdbg_aux_unlk --- An internal demo module will be included when enable --scdbg_aux_unlk false - -# dbg_apb_option --- Adds an additional APB debug port alongside the BVCI one --dbg_apb_option false - - -######## ICCM0 --- com.arc.hardware.ICCM0.1_0 ######## - -# Create ICCM0 --create com.arc.hardware.ICCM0.1_0 System.CPUisle.ARCv2EM.ICCM0 - -# iccm0_size --- This defines the size of ICCM0 in bytes.This ICCM has 0 wait states. --iccm0_size 131072 - -# iccm0_base --- Sets the initial memory region assignment for ICCM0 --iccm0_base 6 - -# iccm0_wide --- Creates ICCM0 as 64b memory to reduce accesses. --iccm0_wide false - -# iccm0_prot --- Specifies the type of protection built for ICCM0. --iccm0_prot None - -# iccm0_prot_level --- Specifies the level of protection. --iccm0_prot_level Data_Only - -# iccm0_prot_exceptions --- When the core is configured with ECC or Parity, cause exception generation hardware to be created for uncorrectable errors detected on the ICCM0 --iccm0_prot_exceptions true - -# iccm0_sec_lvl --- Specifies the level of secure ICCM0. --iccm0_sec_lvl Non_Secure - -# iccm0_dmi --- This enables external access through a DMI (direct memory interface) port. --iccm0_dmi true - - -######## Instruction Cache --- com.arc.hardware.Instruction_Cache.1_0 ######## - -# Create Instruction Cache --create com.arc.hardware.Instruction_Cache.1_0 "System.CPUisle.ARCv2EM.Instruction Cache" - -# ic_size --- This defines the total size of the instruction cache in bytes. --ic_size 16384 - -# ic_ways --- This defines the number of cache ways --ic_ways 2 - -# ic_bsize --- This defines the cache line length in bytes. --ic_bsize 64 - -# ic_disable_on_reset --- The instruction cache may be enabled immediately after reset, depending on this option. If this option is enabled, the last cache operation is set to failed, and the direct cache-RAM access is enabled. Furthermore, the instruction cache is invalidated all cache lines are invalidated and unlocked, and the tag RAM is cleared. --ic_disable_on_reset false - -# ic_feature_level --- This defines the feature level of the cache. --ic_feature_level 1 - -# ic_pwr_opt_level --- This selects power-optimization options in the micro-architecture of the instruction cache. --ic_pwr_opt_level 0 - -# ic_prot --- Specifies the type of protection built for ICACHE. --ic_prot None - -# ic_prot_level --- Specifies the level of protection. --ic_prot_level Data_Only - -# ic_prot_exceptions --- Builds exception generation hardware for uncorrectable (fatal) errors detected on ICACHE. --ic_prot_exceptions true - - -######## Interrupt Controller --- com.arc.hardware.Interrupt_Controller.1_0 ######## - -# Create Interrupt Controller --create com.arc.hardware.Interrupt_Controller.1_0 "System.CPUisle.ARCv2EM.Interrupt Controller" - -# number_of_interrupts --- This is the total number of interrupts available to the core. Some interrupts are allocated statically to a specific interrupt line (for example, timer interrupts). For more information on Interrupt and register-file options, see DesignWare ARCv2 ISA Programmers Reference Manual. --number_of_interrupts 97 - -# number_of_levels --- Priority levels in the interrupt controller. --number_of_levels 4 - -# external_interrupts --- This is the total number of interrupt pins available for external system components. This parameter must be less than the total number of interrupts. --external_interrupts 77 - -# firq_option --- This enables the fast-interrupts option, (priority level 0 interrupts), which uses an alternate register bank (if configured) instead of saving the context to memory. --firq_option false - - -######## Performance Monitor --- com.arc.hardware.Performance_Monitor.1_0 ######## - -# Create Performance Monitor --create com.arc.hardware.Performance_Monitor.1_0 "System.CPUisle.ARCv2EM.Performance Monitor" - -# pct_counters --- Number of counters for performance monitoring. --pct_counters 8 - - -######## JTAG Interface --- com.arc.hardware.JTAG_Interface.1_0 ######## - -# Create JTAG Interface --create com.arc.hardware.JTAG_Interface.1_0 "System.CPUisle.ARCv2EM.JTAG Interface" - -######## Timer 0 --- com.arc.hardware.Timer_0.1_0 ######## - -# Create Timer 0 --create com.arc.hardware.Timer_0.1_0 "System.CPUisle.ARCv2EM.Timer 0" - -# timer_0_int_level --- This sets the interrupt level (and implicitly the priority: level 0 is highest) of timer 0. --timer_0_int_level 1 - - -######## Watchdog Timer --- com.arc.hardware.Watchdog_Timer.1_0 ######## - -# Create Watchdog Timer --create com.arc.hardware.Watchdog_Timer.1_0 "System.CPUisle.ARCv2EM.Watchdog Timer" - -# watchdog_size --- Specifies the bit width of timer's internal counter. --watchdog_size 32 - -# watchdog_clk --- Specifies whether the timer should be driven from a separate clock. --watchdog_clk false - - -######## Real-time Counter --- com.arc.hardware.Real_time_Counter.1_0 ######## - -# Create Real-time Counter --create com.arc.hardware.Real_time_Counter.1_0 "System.CPUisle.ARCv2EM.Real-time Counter" - -######## SmaRT --- com.arc.hardware.SmaRT.1_0 ######## - -# Create SmaRT --create com.arc.hardware.SmaRT.1_0 System.CPUisle.ARCv2EM.SmaRT - -# smart_stack_entries --- This specifies the number of entries in the trace buffer. --smart_stack_entries 8 - -# smart_implementation --- Flip-flop = FF-based design. Memory = memory-based design (provides better density for larger trace buffers). --smart_implementation flip-flop - - -######## Secure pipeline features --- com.arc.hardware.Secure_pipeline_features.1_0 ######## - -# Create Secure pipeline features --create com.arc.hardware.Secure_pipeline_features.1_0 "System.CPUisle.ARCv2EM.Secure pipeline features" - -# sec_scramble --- Enable insertion of scrambling modules on the address & data lines for embedded SRAMs and external memory interfaces. The gate count number in System/Gate Count tab does not include user defined logic. --sec_scramble false - -# sec_encrypt_i --- Add support for user defined instruction encryption. The gate count number in System/Gate Count tab does not include user defined logic. --sec_encrypt_i false - -# sec_encrypt_d --- Add support for user defined data encryption. The gate count number in System/Gate Count tab does not include user defined logic. --sec_encrypt_d false - -# err_prot_option --- Select the ECC mode for CCM/Cache ECC protection: false: detect & correct or true: detect & fail --err_prot_option true - -# pipe_prot_option --- Select to enable PC & Register File error protection --pipe_prot_option false - -# sec_modes_option --- Enable secure shield 2+2 mode --sec_modes_option true - -# sec_region_crypt --- If MPU is present, use region-based encryption user logic for CCT demo --sec_region_crypt false - - -######## Secure Timer 0 --- com.arc.hardware.Secure_Timer_0.1_0 ######## - -# Create Secure Timer 0 --create com.arc.hardware.Secure_Timer_0.1_0 "System.CPUisle.ARCv2EM.Secure Timer 0" - -# stimer_0_int_level --- This sets the interrupt level (and implicitly the priority: level 0 is highest) of secure timer 0. --stimer_0_int_level 1 - - -######## Actionpoints --- com.arc.hardware.Actionpoints.1_0 ######## - -# Create Actionpoints --create com.arc.hardware.Actionpoints.1_0 System.CPUisle.ARCv2EM.Actionpoints - -# num_actionpoints --- This is the number of trigger events available. --num_actionpoints 8 - -# aps_feature --- Selects Actionpoint feature set --aps_feature min - - -######## Floating-point unit --- com.arc.hardware.Floating_point_unit.1_0 ######## - -# Create Floating-point unit --create com.arc.hardware.Floating_point_unit.1_0 "System.CPUisle.ARCv2EM.Floating-point unit" - -# fpu_dp_assist --- This enables double-precision acceleration instructions. --fpu_dp_assist true - -# fpu_fma_option --- This enables the fused multiply-add & multiply-subtract instructions. --fpu_fma_option true - -# fpu_mas_cycles --- Make mul/add/sub multicycle to achieve a higher clock speed. --fpu_mas_cycles 2 - -# fpu_pipe_impl --- FPU pipelined implementation --fpu_pipe_impl false - -# fpu_div_option --- This enables divide & square-root acceleration --fpu_div_option true - -# fpu_div_cycles --- Controls div/sqrt implementation. --fpu_div_cycles 17 - - -######## Memory Protection Unit --- com.arc.hardware.Memory_Protection_Unit.1_0 ######## - -# Create Memory Protection Unit --create com.arc.hardware.Memory_Protection_Unit.1_0 "System.CPUisle.ARCv2EM.Memory Protection Unit" - -# mpu_num_regions --- Number of configured memory regions. --mpu_num_regions 8 - -# mpu_32b --- Set the minimal region size to be 32 byte instead of 2KB. --mpu_32b false - -# mpu_sid_option --- It will enable SID support in Secure Shield --mpu_sid_option true - - -######## Real-time trace producer --- com.arc.hardware.Real_time_trace_producer.1_0 ######## - -# Create Real-time trace producer --create com.arc.hardware.Real_time_trace_producer.1_0 "System.CPUisle.ARCv2EM.Real-time trace producer" - -# rtt_feature_level --- 'small' means that program trace only is available. `medium' adds data trace. `full' adds core and aux register trace. --rtt_feature_level small - - -######## ARCv2EM CCT --- cct.1_0 ######## - -# Create ARCv2EM CCT --create cct.1_0 "System.ARCv2EM CCT" - -# cct --- -# Option used to add a CCT to the design for command-line builds -# Without this architect can't add this component to a build -# via a cmdline -create command. -# with old scripts. -# --cct true - -# no_hostlink --- -# This prevents the inclusion of the hostlink library when compiling -# C or C++ programs. The resultant executable, if it contains printfs, -# will print to an internal fixed buffer __mwwrite_buf. -# Other hostlink operations that require debugger assistance, such as file -# opens, will fail. -# -# Hostlink references incur memory cycles at unpredictable times and -# so can perturb cycle-timing results. Without hostlink, -# the debugger will not in any way interfere with the target while it is running. -# Therefore this option is useful for simulation in which you want precisely the -# same cycle timing to occur each time you run, or for accurate power consumption results. -# --cct_no_hostlink false - -# has_subsystem_cct_flow --- -# The above option will check for the presence of subsystem component in the build configuration and suitably modifies the Makefile for the sub-system environment. -# --has_subsystem_cct_flow false - - -######## BusFabric --- com.arc.hardware.ARCv2MSS.BusFabric.1_0 ######## - -# Create BusFabric --create com.arc.hardware.ARCv2MSS.BusFabric.1_0 System.BusFabric - -######## ClkCtrl --- com.arc.hardware.ARCv2MSS.ClkCtrl.1_0 ######## - -# Create ClkCtrl --create com.arc.hardware.ARCv2MSS.ClkCtrl.1_0 System.ClkCtrl - -######## DSP Software --- com.arc.software.dfss.sw_dsp.1_0 ######## - -# Create DSP Software --create com.arc.software.dfss.sw_dsp.1_0 "System.DSP Software" - -# sw_dsp --- Command line option for Software element 'DSP Software' --sw_dsp true - - -######## EMDK_BOARD --- com.arc.hardware.ARCv2MSS.EMDK_BOARD.1_0 ######## - -# Create EMDK_BOARD --create com.arc.hardware.ARCv2MSS.EMDK_BOARD.1_0 System.EMDK_BOARD - -# emdk_sys_freq --- Select the core frequency. --emdk_sys_freq 50 - - -######## IO Software --- com.arc.software.dfss.sw_io.1_0 ######## - -# Create IO Software --create com.arc.software.dfss.sw_io.1_0 "System.IO Software" - -# sw_io --- Command line option for Software element 'IO Software' --sw_io true - - -######## Implementation --- com.arc.hardware.implementation.1_0 ######## - -# Create Implementation --create com.arc.hardware.implementation.1_0 System.Implementation - -# ClockSpeed --- Target clock speed of the system --clock_speed 10 - -# DDR2_clk_Ratio --- DDR2 Clock Vs System Clock Ratio -# 2x -# 3x -# 4x --ddr2_clk_ratio 3x - -# ClockSkew --- The clock skew for the system --clock_skew 0.2 - -# HoldMargin --- Margin for hold time checks --hold_margin 0.05 - -# Floorplan --- Floorplan definition for relative placement of RAMs (at CPU-level) or the placement of the rams and CPU hard cores (at multicore level) --floorplan em4_sensor - -# JTAGFrequency --- Select the frequency of the JTAG clock Tck (in MHz). -# -# The JTAG clock speed has to be less than 1/2 of the cpu clock otherwise the signals on the BVCI interface are not guaranteed to be valid. -# -# NOTE: The RTL simulations will work when the JTAG clock frequency is set to half the CPU clock, however this may not be the case when simulating at gate level due to delays on the IO pads. -# -# The default is set to 10 MHz so that there is no conflict when simulating with an ARCangel3 at 30MHz. (30 > 10*2) -# -# The speed of simulation can be greatly increased by using a faster JTAG clock, but a dependency will warn if it exceeds 1/2 of the cpu clock. -# --jtag_tclk 4 - -# execution_trace_level --- -# This traces committed instructions as they execute, and gathers statistics -# visible in the debugger for counting instructions & cycle delays. -# At the "stats" level ony the statistics are gathered and no trace is printed. -# "file" is equivalent to "full", but the results go to a trace .txt file instead. -# --execution_trace_level stats - -# tb_trace --- -# Enable instruction execution trace. -# This is available to arc_dev licensees (internal developers) only. -# --tb_trace false - -# zero_based_arcnum --- -# In a multicore build, number ARCs from 0. -# If this is not selected, arcs are numbered from 1. -# (This provides the initial value to the arcnum signal.) -# --zero_based_arcnum true - -# generate_ipxact --- -# Generate ipxact.xml file describing the CPUisle or archipelago frontier -# --generate_ipxact false - -# ipxact_relative_path_names --- -# Use relative path names for Verilog files in the ipxact. -# Otherwise, absolute path names are used. -# --ipxact_relative_path_names true - -# optional_encryption --- -# When selected, encrypted RTL output is generated. -# --optional_encryption false - -# ignore_encrypt_license --- -# When selected, pretend the encryption license is missing. For testing. -# --ignore_encrypt_license false - -# ignore_clear_license --- -# When selected, pretend the cleartest license is missing. For testing. -# --ignore_clear_license false - -# OPTION_require_archipelago --- -# When selected, force use of archipelago. This is for testing purposes. -# --require_archipelago false - - -######## Infrastructure Software --- com.arc.software.dfss.sw_infra.1_0 ######## - -# Create Infrastructure Software --create com.arc.software.dfss.sw_infra.1_0 "System.Infrastructure Software" - -# sw_infra --- Command line option for Software element 'Infrastructure Software' --sw_infra true - -# templateName --- Template name --template_name siss_combo_sensor_dsp - - -######## subsys_infra --- com.arc.hardware.dfss.subsys_infra.1_0 ######## - -# Create subsys_infra --create com.arc.hardware.dfss.subsys_infra.1_0 System.subsys_infra - -# subsys_infra --- Command line option for EIA glue logic. --subsys_infra true - -# internal_interrupt --- Connect the IO interrupts internally --internal_interrupt true - -# internal_dma_handshake --- Connect the DMA handshake signals internally --internal_dma_handshake true - -# spi_tb_sw_test_mode --- -# This is a secret option, not seen by customers. -# If you check this, the SPI peripheral's testbenches will be set to SW test mode: -# The serial interface of the first SPI master io_spi_mstN peripheral is connected to all SPI slave peripherals io_spi_slvN. -# This is used for testing the SW drivers. -# --spi_tb_sw_test_mode false - -# i3c_tb_sw_test_mode --- -# This is a secret option, not seen by customers. -# If you check this, the I3C peripheral's testbenches will be set to SW test mode: -# The serial interface of the io_i3cN peripheral is connected to the I2C slave peripherals io_i2c_slv0. -# This is used for testing the SW drivers. -# --i3c_tb_sw_test_mode false - -# subsys_apex_offset --- Subsystem APEX address offset in the AUX address space. The aperture used by the subsystem is fixed to 0x0010_0000. In general, the APEX address offset must be in the range from 0x0010_0000 to 0xFFF0_0000. However, if your design includes the "UAUX Interface" component, then the APEX address offset must be in the range from 0x0010_0000 to 0x7FF0_0000 to avoid address conflicts with any UAUX components. --subsys_apex_offset 0x8000_0000 - -# subsys_uaux_offset --- Subsystem UAUX address offset in the UAUX address space. The UAUX address offset must be an integer multiple of 0x0010_0000 in the range from 0x0000_0000 to 0x7FF0_0000. The aperture reserved for the subsystem is fixed to 0x0010_0000. --subsys_uaux_offset 0x10_0000 - - -######## ARC_RTT --- com.arc.hardware.ARC_RTT.1_0 ######## - -# Create ARC_RTT --create com.arc.hardware.ARC_RTT.1_0 System.ARC_RTT - -# rtt_coresight_option --- Please select CoreSight ATB interface to offload the data from RTT --rtt_coresight_option false - -# rtt_num_filters --- Please select the Number of RTT Address Filters --rtt_num_filters 8 - -# rtt_atb_ratio --- Sets the clock ratio for the ATB offload port --rtt_atb_ratio 3 - -# has_nexus_if --- Please select Nexus interface to offload the data from RTT --has_nexus_if true - -# has_on_chip_mem --- Please select the on-chip memory option to store the trace data in shared memory --has_on_chip_mem true - -# nexus_data_wdt --- Please select the Nexus Data Width to offload the data from RTT --nexus_data_wdt 16 - -# internal_memory_size --- Please select internal memory size to capture the trace data --internal_memory_size 16k - -# ram_type --- Please select Types of internal memories to be inferred for the logic --ram_type 1_PORT - -# power_domains --- Adds isolation signal inputs/power switch controls for use in UPF flow when configuring power domains. --rtt_power_domains false - - -######## Tool Configuration --- cgen.1_0 ######## - -# Create Tool Configuration --create cgen.1_0 "System.Tool Configuration" - -# mwdt_version --- Selects the MetaWare version to be used with the TCF file. -# Change from the default to an older or newer toolset version if you want the TCF file to be used with an older or newer version of the MetaWare tools. --mwdt_version M-2017.03 - -# code_base_addr --- -# The base address to assign to the executable code segment in the linker command file when there is no ICCM in the build. This value is ignored when there is an ICCM. -# --code_base_addr 0x0 - -# data_base_addr --- -# The base address to assign to the data segment in the linker command file when the data is not being mapped to a DCCM. This value is ignored when the data segment is mapped to a DCCM, as in that case the base address of the DCCM memory is used. -# -# A value of 0xffffffff means that the data segment will not be mapped to any specific address. -# --data_base_addr 0xffff_ffff - -# underscores_in_numbers --- Use underscores in hex numbers to improve readability. --underscores_in_numbers false - -# tcf_rebrand --- Alternate branding of TCF (not used) --rebrand false - - -]]> - - - - - - - - - - - - - - - ICCM0 - - GROUP BLOCK(4): { - /* _SDA_BASE_ computed implicitly */ - .sdata?: {} - .sbss?: {} - * (DATA): {} - * (BSS): {} - .stack ALIGN(4) SIZE(DEFINED _STACKSIZE?_STACKSIZE:65536): {} - .heap? ALIGN(4) SIZE(DEFINED _HEAPSIZE?_HEAPSIZE:0): {} - } > SYSTEM3 - GROUP BLOCK(4) : { - .vectors (TEXT) SIZE(DEFINED _IVTSIZE?_IVTSIZE:760): {} = FILL(0xa5a5a5a5,4) - } > IVT - GROUP BLOCK(4) : { - .nvectors (TEXT) SIZE(DEFINED _IVTSIZE?_IVTSIZE:760): {} = FILL(0xa5a5a5a5,4) - } > NIVT - } - -]]> - - - - - - 0x07, sub_opcode => 0x1E , latency_cycles => 8) - -// User extension instruction - dsp_sin -extern long dsp_sin(long); -#pragma intrinsic(dsp_sin, opcode => 0x07, sub_opcode => 0x1F , latency_cycles => 8) - -#define APEX_COM_ARC_HARDWARE_DFSS_DSP_SINCOS_PRESENT 1 -#define APEX_COM_ARC_HARDWARE_DFSS_IO_GPIO0_PRESENT 1 - -// User extension aux register io_gpio0_debounce -#define AR_IO_GPIO0_DEBOUNCE 0x80017048 -#pragma Aux_register(0x80017048, name=>"io_gpio0_debounce") - -// User extension aux register io_gpio0_clken -#define AR_IO_GPIO0_CLKEN 0x80017080 -#pragma Aux_register(0x80017080, name=>"io_gpio0_clken") - -// User extension aux register io_gpio0_swporta_dr -#define AR_IO_GPIO0_SWPORTA_DR 0x80017000 -#pragma Aux_register(0x80017000, name=>"io_gpio0_swporta_dr") - -// User extension aux register io_gpio0_swporta_ddr -#define AR_IO_GPIO0_SWPORTA_DDR 0x80017004 -#pragma Aux_register(0x80017004, name=>"io_gpio0_swporta_ddr") - -// User extension aux register io_gpio0_inten -#define AR_IO_GPIO0_INTEN 0x80017030 -#pragma Aux_register(0x80017030, name=>"io_gpio0_inten") - -// User extension aux register io_gpio0_intmask -#define AR_IO_GPIO0_INTMASK 0x80017034 -#pragma Aux_register(0x80017034, name=>"io_gpio0_intmask") - -// User extension aux register io_gpio0_inttype_level -#define AR_IO_GPIO0_INTTYPE_LEVEL 0x80017038 -#pragma Aux_register(0x80017038, name=>"io_gpio0_inttype_level") - -// User extension aux register io_gpio0_int_polarity -#define AR_IO_GPIO0_INT_POLARITY 0x8001703c -#pragma Aux_register(0x8001703c, name=>"io_gpio0_int_polarity") - -// User extension aux register io_gpio0_intstatus -#define AR_IO_GPIO0_INTSTATUS 0x80017040 -#pragma Aux_register(0x80017040, name=>"io_gpio0_intstatus") - -// User extension aux register io_gpio0_raw_intstatus -#define AR_IO_GPIO0_RAW_INTSTATUS 0x80017044 -#pragma Aux_register(0x80017044, name=>"io_gpio0_raw_intstatus") - -// User extension aux register io_gpio0_porta_eoi -#define AR_IO_GPIO0_PORTA_EOI 0x8001704c -#pragma Aux_register(0x8001704c, name=>"io_gpio0_porta_eoi") - -// User extension aux register io_gpio0_ext_porta -#define AR_IO_GPIO0_EXT_PORTA 0x80017050 -#pragma Aux_register(0x80017050, name=>"io_gpio0_ext_porta") - -// User extension aux register io_gpio0_ls_sync -#define AR_IO_GPIO0_LS_SYNC 0x80017060 -#pragma Aux_register(0x80017060, name=>"io_gpio0_ls_sync") - -// User extension aux register io_gpio0_int_bothedge -#define AR_IO_GPIO0_INT_BOTHEDGE 0x80017068 -#pragma Aux_register(0x80017068, name=>"io_gpio0_int_bothedge") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2C_MST0_PRESENT 1 - -// User extension aux register io_i2c_mst0_clken -#define AR_IO_I2C_MST0_CLKEN 0x800120c0 -#pragma Aux_register(0x800120c0, name=>"io_i2c_mst0_clken") - -// User extension aux register io_i2c_mst0_con -#define AR_IO_I2C_MST0_CON 0x80012000 -#pragma Aux_register(0x80012000, name=>"io_i2c_mst0_con") - -// User extension aux register io_i2c_mst0_tar -#define AR_IO_I2C_MST0_TAR 0x80012004 -#pragma Aux_register(0x80012004, name=>"io_i2c_mst0_tar") - -// User extension aux register io_i2c_mst0_data_cmd -#define AR_IO_I2C_MST0_DATA_CMD 0x80012010 -#pragma Aux_register(0x80012010, name=>"io_i2c_mst0_data_cmd") - -// User extension aux register io_i2c_mst0_ss_scl_hcnt -#define AR_IO_I2C_MST0_SS_SCL_HCNT 0x80012014 -#pragma Aux_register(0x80012014, name=>"io_i2c_mst0_ss_scl_hcnt") - -// User extension aux register io_i2c_mst0_ss_scl_lcnt -#define AR_IO_I2C_MST0_SS_SCL_LCNT 0x80012018 -#pragma Aux_register(0x80012018, name=>"io_i2c_mst0_ss_scl_lcnt") - -// User extension aux register io_i2c_mst0_fs_scl_hcnt -#define AR_IO_I2C_MST0_FS_SCL_HCNT 0x8001201c -#pragma Aux_register(0x8001201c, name=>"io_i2c_mst0_fs_scl_hcnt") - -// User extension aux register io_i2c_mst0_fs_scl_lcnt -#define AR_IO_I2C_MST0_FS_SCL_LCNT 0x80012020 -#pragma Aux_register(0x80012020, name=>"io_i2c_mst0_fs_scl_lcnt") - -// User extension aux register io_i2c_mst0_intr_stat -#define AR_IO_I2C_MST0_INTR_STAT 0x8001202c -#pragma Aux_register(0x8001202c, name=>"io_i2c_mst0_intr_stat") - -// User extension aux register io_i2c_mst0_intr_mask -#define AR_IO_I2C_MST0_INTR_MASK 0x80012030 -#pragma Aux_register(0x80012030, name=>"io_i2c_mst0_intr_mask") - -// User extension aux register io_i2c_mst0_raw_intr_stat -#define AR_IO_I2C_MST0_RAW_INTR_STAT 0x80012034 -#pragma Aux_register(0x80012034, name=>"io_i2c_mst0_raw_intr_stat") - -// User extension aux register io_i2c_mst0_rx_tl -#define AR_IO_I2C_MST0_RX_TL 0x80012038 -#pragma Aux_register(0x80012038, name=>"io_i2c_mst0_rx_tl") - -// User extension aux register io_i2c_mst0_tx_tl -#define AR_IO_I2C_MST0_TX_TL 0x8001203c -#pragma Aux_register(0x8001203c, name=>"io_i2c_mst0_tx_tl") - -// User extension aux register io_i2c_mst0_clr_intr -#define AR_IO_I2C_MST0_CLR_INTR 0x80012040 -#pragma Aux_register(0x80012040, name=>"io_i2c_mst0_clr_intr") - -// User extension aux register io_i2c_mst0_clr_rx_under -#define AR_IO_I2C_MST0_CLR_RX_UNDER 0x80012044 -#pragma Aux_register(0x80012044, name=>"io_i2c_mst0_clr_rx_under") - -// User extension aux register io_i2c_mst0_clr_rx_over -#define AR_IO_I2C_MST0_CLR_RX_OVER 0x80012048 -#pragma Aux_register(0x80012048, name=>"io_i2c_mst0_clr_rx_over") - -// User extension aux register io_i2c_mst0_clr_tx_over -#define AR_IO_I2C_MST0_CLR_TX_OVER 0x8001204c -#pragma Aux_register(0x8001204c, name=>"io_i2c_mst0_clr_tx_over") - -// User extension aux register io_i2c_mst0_clr_tx_abrt -#define AR_IO_I2C_MST0_CLR_TX_ABRT 0x80012054 -#pragma Aux_register(0x80012054, name=>"io_i2c_mst0_clr_tx_abrt") - -// User extension aux register io_i2c_mst0_clr_activity -#define AR_IO_I2C_MST0_CLR_ACTIVITY 0x8001205c -#pragma Aux_register(0x8001205c, name=>"io_i2c_mst0_clr_activity") - -// User extension aux register io_i2c_mst0_clr_stop_det -#define AR_IO_I2C_MST0_CLR_STOP_DET 0x80012060 -#pragma Aux_register(0x80012060, name=>"io_i2c_mst0_clr_stop_det") - -// User extension aux register io_i2c_mst0_clr_start_det -#define AR_IO_I2C_MST0_CLR_START_DET 0x80012064 -#pragma Aux_register(0x80012064, name=>"io_i2c_mst0_clr_start_det") - -// User extension aux register io_i2c_mst0_enable -#define AR_IO_I2C_MST0_ENABLE 0x8001206c -#pragma Aux_register(0x8001206c, name=>"io_i2c_mst0_enable") - -// User extension aux register io_i2c_mst0_status -#define AR_IO_I2C_MST0_STATUS 0x80012070 -#pragma Aux_register(0x80012070, name=>"io_i2c_mst0_status") - -// User extension aux register io_i2c_mst0_txflr -#define AR_IO_I2C_MST0_TXFLR 0x80012074 -#pragma Aux_register(0x80012074, name=>"io_i2c_mst0_txflr") - -// User extension aux register io_i2c_mst0_rxflr -#define AR_IO_I2C_MST0_RXFLR 0x80012078 -#pragma Aux_register(0x80012078, name=>"io_i2c_mst0_rxflr") - -// User extension aux register io_i2c_mst0_sda_hold -#define AR_IO_I2C_MST0_SDA_HOLD 0x8001207c -#pragma Aux_register(0x8001207c, name=>"io_i2c_mst0_sda_hold") - -// User extension aux register io_i2c_mst0_tx_abrt_source -#define AR_IO_I2C_MST0_TX_ABRT_SOURCE 0x80012080 -#pragma Aux_register(0x80012080, name=>"io_i2c_mst0_tx_abrt_source") - -// User extension aux register io_i2c_mst0_enable_status -#define AR_IO_I2C_MST0_ENABLE_STATUS 0x8001209c -#pragma Aux_register(0x8001209c, name=>"io_i2c_mst0_enable_status") - -// User extension aux register io_i2c_mst0_fs_spklen -#define AR_IO_I2C_MST0_FS_SPKLEN 0x800120a0 -#pragma Aux_register(0x800120a0, name=>"io_i2c_mst0_fs_spklen") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2C_SLV0_PRESENT 1 - -// User extension aux register io_i2c_slv0_clken -#define AR_IO_I2C_SLV0_CLKEN 0x800130c0 -#pragma Aux_register(0x800130c0, name=>"io_i2c_slv0_clken") - -// User extension aux register io_i2c_slv0_con -#define AR_IO_I2C_SLV0_CON 0x80013000 -#pragma Aux_register(0x80013000, name=>"io_i2c_slv0_con") - -// User extension aux register io_i2c_slv0_sar -#define AR_IO_I2C_SLV0_SAR 0x80013008 -#pragma Aux_register(0x80013008, name=>"io_i2c_slv0_sar") - -// User extension aux register io_i2c_slv0_data_cmd -#define AR_IO_I2C_SLV0_DATA_CMD 0x80013010 -#pragma Aux_register(0x80013010, name=>"io_i2c_slv0_data_cmd") - -// User extension aux register io_i2c_slv0_intr_stat -#define AR_IO_I2C_SLV0_INTR_STAT 0x8001302c -#pragma Aux_register(0x8001302c, name=>"io_i2c_slv0_intr_stat") - -// User extension aux register io_i2c_slv0_intr_mask -#define AR_IO_I2C_SLV0_INTR_MASK 0x80013030 -#pragma Aux_register(0x80013030, name=>"io_i2c_slv0_intr_mask") - -// User extension aux register io_i2c_slv0_raw_intr_stat -#define AR_IO_I2C_SLV0_RAW_INTR_STAT 0x80013034 -#pragma Aux_register(0x80013034, name=>"io_i2c_slv0_raw_intr_stat") - -// User extension aux register io_i2c_slv0_rx_tl -#define AR_IO_I2C_SLV0_RX_TL 0x80013038 -#pragma Aux_register(0x80013038, name=>"io_i2c_slv0_rx_tl") - -// User extension aux register io_i2c_slv0_tx_tl -#define AR_IO_I2C_SLV0_TX_TL 0x8001303c -#pragma Aux_register(0x8001303c, name=>"io_i2c_slv0_tx_tl") - -// User extension aux register io_i2c_slv0_clr_intr -#define AR_IO_I2C_SLV0_CLR_INTR 0x80013040 -#pragma Aux_register(0x80013040, name=>"io_i2c_slv0_clr_intr") - -// User extension aux register io_i2c_slv0_clr_rx_under -#define AR_IO_I2C_SLV0_CLR_RX_UNDER 0x80013044 -#pragma Aux_register(0x80013044, name=>"io_i2c_slv0_clr_rx_under") - -// User extension aux register io_i2c_slv0_clr_rx_over -#define AR_IO_I2C_SLV0_CLR_RX_OVER 0x80013048 -#pragma Aux_register(0x80013048, name=>"io_i2c_slv0_clr_rx_over") - -// User extension aux register io_i2c_slv0_clr_tx_over -#define AR_IO_I2C_SLV0_CLR_TX_OVER 0x8001304c -#pragma Aux_register(0x8001304c, name=>"io_i2c_slv0_clr_tx_over") - -// User extension aux register io_i2c_slv0_clr_rd_req -#define AR_IO_I2C_SLV0_CLR_RD_REQ 0x80013050 -#pragma Aux_register(0x80013050, name=>"io_i2c_slv0_clr_rd_req") - -// User extension aux register io_i2c_slv0_clr_tx_abrt -#define AR_IO_I2C_SLV0_CLR_TX_ABRT 0x80013054 -#pragma Aux_register(0x80013054, name=>"io_i2c_slv0_clr_tx_abrt") - -// User extension aux register io_i2c_slv0_clr_rx_done -#define AR_IO_I2C_SLV0_CLR_RX_DONE 0x80013058 -#pragma Aux_register(0x80013058, name=>"io_i2c_slv0_clr_rx_done") - -// User extension aux register io_i2c_slv0_clr_activity -#define AR_IO_I2C_SLV0_CLR_ACTIVITY 0x8001305c -#pragma Aux_register(0x8001305c, name=>"io_i2c_slv0_clr_activity") - -// User extension aux register io_i2c_slv0_clr_stop_det -#define AR_IO_I2C_SLV0_CLR_STOP_DET 0x80013060 -#pragma Aux_register(0x80013060, name=>"io_i2c_slv0_clr_stop_det") - -// User extension aux register io_i2c_slv0_clr_start_det -#define AR_IO_I2C_SLV0_CLR_START_DET 0x80013064 -#pragma Aux_register(0x80013064, name=>"io_i2c_slv0_clr_start_det") - -// User extension aux register io_i2c_slv0_enable -#define AR_IO_I2C_SLV0_ENABLE 0x8001306c -#pragma Aux_register(0x8001306c, name=>"io_i2c_slv0_enable") - -// User extension aux register io_i2c_slv0_status -#define AR_IO_I2C_SLV0_STATUS 0x80013070 -#pragma Aux_register(0x80013070, name=>"io_i2c_slv0_status") - -// User extension aux register io_i2c_slv0_txflr -#define AR_IO_I2C_SLV0_TXFLR 0x80013074 -#pragma Aux_register(0x80013074, name=>"io_i2c_slv0_txflr") - -// User extension aux register io_i2c_slv0_rxflr -#define AR_IO_I2C_SLV0_RXFLR 0x80013078 -#pragma Aux_register(0x80013078, name=>"io_i2c_slv0_rxflr") - -// User extension aux register io_i2c_slv0_sda_hold -#define AR_IO_I2C_SLV0_SDA_HOLD 0x8001307c -#pragma Aux_register(0x8001307c, name=>"io_i2c_slv0_sda_hold") - -// User extension aux register io_i2c_slv0_tx_abrt_source -#define AR_IO_I2C_SLV0_TX_ABRT_SOURCE 0x80013080 -#pragma Aux_register(0x80013080, name=>"io_i2c_slv0_tx_abrt_source") - -// User extension aux register io_i2c_slv0_sda_setup -#define AR_IO_I2C_SLV0_SDA_SETUP 0x80013094 -#pragma Aux_register(0x80013094, name=>"io_i2c_slv0_sda_setup") - -// User extension aux register io_i2c_slv0_enable_status -#define AR_IO_I2C_SLV0_ENABLE_STATUS 0x8001309c -#pragma Aux_register(0x8001309c, name=>"io_i2c_slv0_enable_status") - -// User extension aux register io_i2c_slv0_fs_spklen -#define AR_IO_I2C_SLV0_FS_SPKLEN 0x800130a0 -#pragma Aux_register(0x800130a0, name=>"io_i2c_slv0_fs_spklen") - -// User extension aux register io_i2c_slv0_clr_restart_det -#define AR_IO_I2C_SLV0_CLR_RESTART_DET 0x800130a8 -#pragma Aux_register(0x800130a8, name=>"io_i2c_slv0_clr_restart_det") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_SPI_MST0_PRESENT 1 - -// User extension aux register io_spi_mst0_ctrlr0 -#define AR_IO_SPI_MST0_CTRLR0 0x80010000 -#pragma Aux_register(0x80010000, name=>"io_spi_mst0_ctrlr0") - -// User extension aux register io_spi_mst0_ctrlr1 -#define AR_IO_SPI_MST0_CTRLR1 0x80010001 -#pragma Aux_register(0x80010001, name=>"io_spi_mst0_ctrlr1") - -// User extension aux register io_spi_mst0_spien -#define AR_IO_SPI_MST0_SPIEN 0x80010002 -#pragma Aux_register(0x80010002, name=>"io_spi_mst0_spien") - -// User extension aux register io_spi_mst0_ser -#define AR_IO_SPI_MST0_SER 0x80010004 -#pragma Aux_register(0x80010004, name=>"io_spi_mst0_ser") - -// User extension aux register io_spi_mst0_baudr -#define AR_IO_SPI_MST0_BAUDR 0x80010005 -#pragma Aux_register(0x80010005, name=>"io_spi_mst0_baudr") - -// User extension aux register io_spi_mst0_txftlr -#define AR_IO_SPI_MST0_TXFTLR 0x80010006 -#pragma Aux_register(0x80010006, name=>"io_spi_mst0_txftlr") - -// User extension aux register io_spi_mst0_rxftlr -#define AR_IO_SPI_MST0_RXFTLR 0x80010007 -#pragma Aux_register(0x80010007, name=>"io_spi_mst0_rxftlr") - -// User extension aux register io_spi_mst0_txflr -#define AR_IO_SPI_MST0_TXFLR 0x80010008 -#pragma Aux_register(0x80010008, name=>"io_spi_mst0_txflr") - -// User extension aux register io_spi_mst0_rxflr -#define AR_IO_SPI_MST0_RXFLR 0x80010009 -#pragma Aux_register(0x80010009, name=>"io_spi_mst0_rxflr") - -// User extension aux register io_spi_mst0_sr -#define AR_IO_SPI_MST0_SR 0x8001000a -#pragma Aux_register(0x8001000a, name=>"io_spi_mst0_sr") - -// User extension aux register io_spi_mst0_imr -#define AR_IO_SPI_MST0_IMR 0x8001000b -#pragma Aux_register(0x8001000b, name=>"io_spi_mst0_imr") - -// User extension aux register io_spi_mst0_isr -#define AR_IO_SPI_MST0_ISR 0x8001000c -#pragma Aux_register(0x8001000c, name=>"io_spi_mst0_isr") - -// User extension aux register io_spi_mst0_risr -#define AR_IO_SPI_MST0_RISR 0x8001000d -#pragma Aux_register(0x8001000d, name=>"io_spi_mst0_risr") - -// User extension aux register io_spi_mst0_txoicr -#define AR_IO_SPI_MST0_TXOICR 0x8001000e -#pragma Aux_register(0x8001000e, name=>"io_spi_mst0_txoicr") - -// User extension aux register io_spi_mst0_rxoicr -#define AR_IO_SPI_MST0_RXOICR 0x8001000f -#pragma Aux_register(0x8001000f, name=>"io_spi_mst0_rxoicr") - -// User extension aux register io_spi_mst0_rxuicr -#define AR_IO_SPI_MST0_RXUICR 0x80010010 -#pragma Aux_register(0x80010010, name=>"io_spi_mst0_rxuicr") - -// User extension aux register io_spi_mst0_icr -#define AR_IO_SPI_MST0_ICR 0x80010012 -#pragma Aux_register(0x80010012, name=>"io_spi_mst0_icr") - -// User extension aux register io_spi_mst0_clken -#define AR_IO_SPI_MST0_CLKEN 0x80010016 -#pragma Aux_register(0x80010016, name=>"io_spi_mst0_clken") - -// User extension aux register io_spi_mst0_dr -#define AR_IO_SPI_MST0_DR 0x80010018 -#pragma Aux_register(0x80010018, name=>"io_spi_mst0_dr") - -// User extension aux register io_spi_mst0_rx_sample_dly -#define AR_IO_SPI_MST0_RX_SAMPLE_DLY 0x8001003c -#pragma Aux_register(0x8001003c, name=>"io_spi_mst0_rx_sample_dly") -#define APEX_COM_ARC_HARDWARE_DFSS_SUBSYS_BCR_PRESENT 1 - -// User extension aux register SUBSYS_BUILD -#define AR_SUBSYS_BUILD 0xf0 -#pragma Aux_register(0xf0, name=>"SUBSYS_BUILD") - -// User extension aux register SUBSYS_DSP_0_BUILD -#define AR_SUBSYS_DSP_0_BUILD 0xa00 -#pragma Aux_register(0xa00, name=>"SUBSYS_DSP_0_BUILD") - -// User extension aux register SUBSYS_DSP_0_CONFIG -#define AR_SUBSYS_DSP_0_CONFIG 0xa02 -#pragma Aux_register(0xa02, name=>"SUBSYS_DSP_0_CONFIG") - -// User extension aux register SUBSYS_IO_0_BUILD -#define AR_SUBSYS_IO_0_BUILD 0xa04 -#pragma Aux_register(0xa04, name=>"SUBSYS_IO_0_BUILD") - -// User extension aux register SUBSYS_IO_1_BUILD -#define AR_SUBSYS_IO_1_BUILD 0xa05 -#pragma Aux_register(0xa05, name=>"SUBSYS_IO_1_BUILD") - -// User extension aux register SUBSYS_IO_2_BUILD -#define AR_SUBSYS_IO_2_BUILD 0xa06 -#pragma Aux_register(0xa06, name=>"SUBSYS_IO_2_BUILD") - -// User extension aux register SUBSYS_UAUX_OFFSET -#define AR_SUBSYS_UAUX_OFFSET 0xa1e -#pragma Aux_register(0xa1e, name=>"SUBSYS_UAUX_OFFSET") - -// User extension aux register SUBSYS_APEX_OFFSET -#define AR_SUBSYS_APEX_OFFSET 0xa1f -#pragma Aux_register(0xa1f, name=>"SUBSYS_APEX_OFFSET") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_SPI_MST1_PRESENT 1 - -// User extension aux register io_spi_mst1_ctrlr0 -#define AR_IO_SPI_MST1_CTRLR0 0x80010100 -#pragma Aux_register(0x80010100, name=>"io_spi_mst1_ctrlr0") - -// User extension aux register io_spi_mst1_ctrlr1 -#define AR_IO_SPI_MST1_CTRLR1 0x80010101 -#pragma Aux_register(0x80010101, name=>"io_spi_mst1_ctrlr1") - -// User extension aux register io_spi_mst1_spien -#define AR_IO_SPI_MST1_SPIEN 0x80010102 -#pragma Aux_register(0x80010102, name=>"io_spi_mst1_spien") - -// User extension aux register io_spi_mst1_ser -#define AR_IO_SPI_MST1_SER 0x80010104 -#pragma Aux_register(0x80010104, name=>"io_spi_mst1_ser") - -// User extension aux register io_spi_mst1_baudr -#define AR_IO_SPI_MST1_BAUDR 0x80010105 -#pragma Aux_register(0x80010105, name=>"io_spi_mst1_baudr") - -// User extension aux register io_spi_mst1_txftlr -#define AR_IO_SPI_MST1_TXFTLR 0x80010106 -#pragma Aux_register(0x80010106, name=>"io_spi_mst1_txftlr") - -// User extension aux register io_spi_mst1_rxftlr -#define AR_IO_SPI_MST1_RXFTLR 0x80010107 -#pragma Aux_register(0x80010107, name=>"io_spi_mst1_rxftlr") - -// User extension aux register io_spi_mst1_txflr -#define AR_IO_SPI_MST1_TXFLR 0x80010108 -#pragma Aux_register(0x80010108, name=>"io_spi_mst1_txflr") - -// User extension aux register io_spi_mst1_rxflr -#define AR_IO_SPI_MST1_RXFLR 0x80010109 -#pragma Aux_register(0x80010109, name=>"io_spi_mst1_rxflr") - -// User extension aux register io_spi_mst1_sr -#define AR_IO_SPI_MST1_SR 0x8001010a -#pragma Aux_register(0x8001010a, name=>"io_spi_mst1_sr") - -// User extension aux register io_spi_mst1_imr -#define AR_IO_SPI_MST1_IMR 0x8001010b -#pragma Aux_register(0x8001010b, name=>"io_spi_mst1_imr") - -// User extension aux register io_spi_mst1_isr -#define AR_IO_SPI_MST1_ISR 0x8001010c -#pragma Aux_register(0x8001010c, name=>"io_spi_mst1_isr") - -// User extension aux register io_spi_mst1_risr -#define AR_IO_SPI_MST1_RISR 0x8001010d -#pragma Aux_register(0x8001010d, name=>"io_spi_mst1_risr") - -// User extension aux register io_spi_mst1_txoicr -#define AR_IO_SPI_MST1_TXOICR 0x8001010e -#pragma Aux_register(0x8001010e, name=>"io_spi_mst1_txoicr") - -// User extension aux register io_spi_mst1_rxoicr -#define AR_IO_SPI_MST1_RXOICR 0x8001010f -#pragma Aux_register(0x8001010f, name=>"io_spi_mst1_rxoicr") - -// User extension aux register io_spi_mst1_rxuicr -#define AR_IO_SPI_MST1_RXUICR 0x80010110 -#pragma Aux_register(0x80010110, name=>"io_spi_mst1_rxuicr") - -// User extension aux register io_spi_mst1_icr -#define AR_IO_SPI_MST1_ICR 0x80010112 -#pragma Aux_register(0x80010112, name=>"io_spi_mst1_icr") - -// User extension aux register io_spi_mst1_clken -#define AR_IO_SPI_MST1_CLKEN 0x80010116 -#pragma Aux_register(0x80010116, name=>"io_spi_mst1_clken") - -// User extension aux register io_spi_mst1_dr -#define AR_IO_SPI_MST1_DR 0x80010118 -#pragma Aux_register(0x80010118, name=>"io_spi_mst1_dr") - -// User extension aux register io_spi_mst1_rx_sample_dly -#define AR_IO_SPI_MST1_RX_SAMPLE_DLY 0x8001013c -#pragma Aux_register(0x8001013c, name=>"io_spi_mst1_rx_sample_dly") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_SPI_MST2_PRESENT 1 - -// User extension aux register io_spi_mst2_ctrlr0 -#define AR_IO_SPI_MST2_CTRLR0 0x80010200 -#pragma Aux_register(0x80010200, name=>"io_spi_mst2_ctrlr0") - -// User extension aux register io_spi_mst2_ctrlr1 -#define AR_IO_SPI_MST2_CTRLR1 0x80010201 -#pragma Aux_register(0x80010201, name=>"io_spi_mst2_ctrlr1") - -// User extension aux register io_spi_mst2_spien -#define AR_IO_SPI_MST2_SPIEN 0x80010202 -#pragma Aux_register(0x80010202, name=>"io_spi_mst2_spien") - -// User extension aux register io_spi_mst2_ser -#define AR_IO_SPI_MST2_SER 0x80010204 -#pragma Aux_register(0x80010204, name=>"io_spi_mst2_ser") - -// User extension aux register io_spi_mst2_baudr -#define AR_IO_SPI_MST2_BAUDR 0x80010205 -#pragma Aux_register(0x80010205, name=>"io_spi_mst2_baudr") - -// User extension aux register io_spi_mst2_txftlr -#define AR_IO_SPI_MST2_TXFTLR 0x80010206 -#pragma Aux_register(0x80010206, name=>"io_spi_mst2_txftlr") - -// User extension aux register io_spi_mst2_rxftlr -#define AR_IO_SPI_MST2_RXFTLR 0x80010207 -#pragma Aux_register(0x80010207, name=>"io_spi_mst2_rxftlr") - -// User extension aux register io_spi_mst2_txflr -#define AR_IO_SPI_MST2_TXFLR 0x80010208 -#pragma Aux_register(0x80010208, name=>"io_spi_mst2_txflr") - -// User extension aux register io_spi_mst2_rxflr -#define AR_IO_SPI_MST2_RXFLR 0x80010209 -#pragma Aux_register(0x80010209, name=>"io_spi_mst2_rxflr") - -// User extension aux register io_spi_mst2_sr -#define AR_IO_SPI_MST2_SR 0x8001020a -#pragma Aux_register(0x8001020a, name=>"io_spi_mst2_sr") - -// User extension aux register io_spi_mst2_imr -#define AR_IO_SPI_MST2_IMR 0x8001020b -#pragma Aux_register(0x8001020b, name=>"io_spi_mst2_imr") - -// User extension aux register io_spi_mst2_isr -#define AR_IO_SPI_MST2_ISR 0x8001020c -#pragma Aux_register(0x8001020c, name=>"io_spi_mst2_isr") - -// User extension aux register io_spi_mst2_risr -#define AR_IO_SPI_MST2_RISR 0x8001020d -#pragma Aux_register(0x8001020d, name=>"io_spi_mst2_risr") - -// User extension aux register io_spi_mst2_txoicr -#define AR_IO_SPI_MST2_TXOICR 0x8001020e -#pragma Aux_register(0x8001020e, name=>"io_spi_mst2_txoicr") - -// User extension aux register io_spi_mst2_rxoicr -#define AR_IO_SPI_MST2_RXOICR 0x8001020f -#pragma Aux_register(0x8001020f, name=>"io_spi_mst2_rxoicr") - -// User extension aux register io_spi_mst2_rxuicr -#define AR_IO_SPI_MST2_RXUICR 0x80010210 -#pragma Aux_register(0x80010210, name=>"io_spi_mst2_rxuicr") - -// User extension aux register io_spi_mst2_icr -#define AR_IO_SPI_MST2_ICR 0x80010212 -#pragma Aux_register(0x80010212, name=>"io_spi_mst2_icr") - -// User extension aux register io_spi_mst2_clken -#define AR_IO_SPI_MST2_CLKEN 0x80010216 -#pragma Aux_register(0x80010216, name=>"io_spi_mst2_clken") - -// User extension aux register io_spi_mst2_dr -#define AR_IO_SPI_MST2_DR 0x80010218 -#pragma Aux_register(0x80010218, name=>"io_spi_mst2_dr") - -// User extension aux register io_spi_mst2_rx_sample_dly -#define AR_IO_SPI_MST2_RX_SAMPLE_DLY 0x8001023c -#pragma Aux_register(0x8001023c, name=>"io_spi_mst2_rx_sample_dly") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_SPI_SLV0_PRESENT 1 - -// User extension aux register io_spi_slv0_ctrlr0 -#define AR_IO_SPI_SLV0_CTRLR0 0x80011000 -#pragma Aux_register(0x80011000, name=>"io_spi_slv0_ctrlr0") - -// User extension aux register io_spi_slv0_spien -#define AR_IO_SPI_SLV0_SPIEN 0x80011002 -#pragma Aux_register(0x80011002, name=>"io_spi_slv0_spien") - -// User extension aux register io_spi_slv0_txftlr -#define AR_IO_SPI_SLV0_TXFTLR 0x80011006 -#pragma Aux_register(0x80011006, name=>"io_spi_slv0_txftlr") - -// User extension aux register io_spi_slv0_rxftlr -#define AR_IO_SPI_SLV0_RXFTLR 0x80011007 -#pragma Aux_register(0x80011007, name=>"io_spi_slv0_rxftlr") - -// User extension aux register io_spi_slv0_txflr -#define AR_IO_SPI_SLV0_TXFLR 0x80011008 -#pragma Aux_register(0x80011008, name=>"io_spi_slv0_txflr") - -// User extension aux register io_spi_slv0_rxflr -#define AR_IO_SPI_SLV0_RXFLR 0x80011009 -#pragma Aux_register(0x80011009, name=>"io_spi_slv0_rxflr") - -// User extension aux register io_spi_slv0_sr -#define AR_IO_SPI_SLV0_SR 0x8001100a -#pragma Aux_register(0x8001100a, name=>"io_spi_slv0_sr") - -// User extension aux register io_spi_slv0_imr -#define AR_IO_SPI_SLV0_IMR 0x8001100b -#pragma Aux_register(0x8001100b, name=>"io_spi_slv0_imr") - -// User extension aux register io_spi_slv0_isr -#define AR_IO_SPI_SLV0_ISR 0x8001100c -#pragma Aux_register(0x8001100c, name=>"io_spi_slv0_isr") - -// User extension aux register io_spi_slv0_risr -#define AR_IO_SPI_SLV0_RISR 0x8001100d -#pragma Aux_register(0x8001100d, name=>"io_spi_slv0_risr") - -// User extension aux register io_spi_slv0_txoicr -#define AR_IO_SPI_SLV0_TXOICR 0x8001100e -#pragma Aux_register(0x8001100e, name=>"io_spi_slv0_txoicr") - -// User extension aux register io_spi_slv0_rxoicr -#define AR_IO_SPI_SLV0_RXOICR 0x8001100f -#pragma Aux_register(0x8001100f, name=>"io_spi_slv0_rxoicr") - -// User extension aux register io_spi_slv0_rxuicr -#define AR_IO_SPI_SLV0_RXUICR 0x80011010 -#pragma Aux_register(0x80011010, name=>"io_spi_slv0_rxuicr") - -// User extension aux register io_spi_slv0_icr -#define AR_IO_SPI_SLV0_ICR 0x80011012 -#pragma Aux_register(0x80011012, name=>"io_spi_slv0_icr") - -// User extension aux register io_spi_slv0_clken -#define AR_IO_SPI_SLV0_CLKEN 0x80011016 -#pragma Aux_register(0x80011016, name=>"io_spi_slv0_clken") - -// User extension aux register io_spi_slv0_dr -#define AR_IO_SPI_SLV0_DR 0x80011018 -#pragma Aux_register(0x80011018, name=>"io_spi_slv0_dr") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_GPIO1_PRESENT 1 - -// User extension aux register io_gpio1_debounce -#define AR_IO_GPIO1_DEBOUNCE 0x80017148 -#pragma Aux_register(0x80017148, name=>"io_gpio1_debounce") - -// User extension aux register io_gpio1_clken -#define AR_IO_GPIO1_CLKEN 0x80017180 -#pragma Aux_register(0x80017180, name=>"io_gpio1_clken") - -// User extension aux register io_gpio1_swporta_dr -#define AR_IO_GPIO1_SWPORTA_DR 0x80017100 -#pragma Aux_register(0x80017100, name=>"io_gpio1_swporta_dr") - -// User extension aux register io_gpio1_swporta_ddr -#define AR_IO_GPIO1_SWPORTA_DDR 0x80017104 -#pragma Aux_register(0x80017104, name=>"io_gpio1_swporta_ddr") - -// User extension aux register io_gpio1_inten -#define AR_IO_GPIO1_INTEN 0x80017130 -#pragma Aux_register(0x80017130, name=>"io_gpio1_inten") - -// User extension aux register io_gpio1_intmask -#define AR_IO_GPIO1_INTMASK 0x80017134 -#pragma Aux_register(0x80017134, name=>"io_gpio1_intmask") - -// User extension aux register io_gpio1_inttype_level -#define AR_IO_GPIO1_INTTYPE_LEVEL 0x80017138 -#pragma Aux_register(0x80017138, name=>"io_gpio1_inttype_level") - -// User extension aux register io_gpio1_int_polarity -#define AR_IO_GPIO1_INT_POLARITY 0x8001713c -#pragma Aux_register(0x8001713c, name=>"io_gpio1_int_polarity") - -// User extension aux register io_gpio1_intstatus -#define AR_IO_GPIO1_INTSTATUS 0x80017140 -#pragma Aux_register(0x80017140, name=>"io_gpio1_intstatus") - -// User extension aux register io_gpio1_raw_intstatus -#define AR_IO_GPIO1_RAW_INTSTATUS 0x80017144 -#pragma Aux_register(0x80017144, name=>"io_gpio1_raw_intstatus") - -// User extension aux register io_gpio1_porta_eoi -#define AR_IO_GPIO1_PORTA_EOI 0x8001714c -#pragma Aux_register(0x8001714c, name=>"io_gpio1_porta_eoi") - -// User extension aux register io_gpio1_ext_porta -#define AR_IO_GPIO1_EXT_PORTA 0x80017150 -#pragma Aux_register(0x80017150, name=>"io_gpio1_ext_porta") - -// User extension aux register io_gpio1_ls_sync -#define AR_IO_GPIO1_LS_SYNC 0x80017160 -#pragma Aux_register(0x80017160, name=>"io_gpio1_ls_sync") - -// User extension aux register io_gpio1_int_bothedge -#define AR_IO_GPIO1_INT_BOTHEDGE 0x80017168 -#pragma Aux_register(0x80017168, name=>"io_gpio1_int_bothedge") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_GPIO2_PRESENT 1 - -// User extension aux register io_gpio2_debounce -#define AR_IO_GPIO2_DEBOUNCE 0x80017248 -#pragma Aux_register(0x80017248, name=>"io_gpio2_debounce") - -// User extension aux register io_gpio2_clken -#define AR_IO_GPIO2_CLKEN 0x80017280 -#pragma Aux_register(0x80017280, name=>"io_gpio2_clken") - -// User extension aux register io_gpio2_swporta_dr -#define AR_IO_GPIO2_SWPORTA_DR 0x80017200 -#pragma Aux_register(0x80017200, name=>"io_gpio2_swporta_dr") - -// User extension aux register io_gpio2_swporta_ddr -#define AR_IO_GPIO2_SWPORTA_DDR 0x80017204 -#pragma Aux_register(0x80017204, name=>"io_gpio2_swporta_ddr") - -// User extension aux register io_gpio2_inten -#define AR_IO_GPIO2_INTEN 0x80017230 -#pragma Aux_register(0x80017230, name=>"io_gpio2_inten") - -// User extension aux register io_gpio2_intmask -#define AR_IO_GPIO2_INTMASK 0x80017234 -#pragma Aux_register(0x80017234, name=>"io_gpio2_intmask") - -// User extension aux register io_gpio2_inttype_level -#define AR_IO_GPIO2_INTTYPE_LEVEL 0x80017238 -#pragma Aux_register(0x80017238, name=>"io_gpio2_inttype_level") - -// User extension aux register io_gpio2_int_polarity -#define AR_IO_GPIO2_INT_POLARITY 0x8001723c -#pragma Aux_register(0x8001723c, name=>"io_gpio2_int_polarity") - -// User extension aux register io_gpio2_intstatus -#define AR_IO_GPIO2_INTSTATUS 0x80017240 -#pragma Aux_register(0x80017240, name=>"io_gpio2_intstatus") - -// User extension aux register io_gpio2_raw_intstatus -#define AR_IO_GPIO2_RAW_INTSTATUS 0x80017244 -#pragma Aux_register(0x80017244, name=>"io_gpio2_raw_intstatus") - -// User extension aux register io_gpio2_porta_eoi -#define AR_IO_GPIO2_PORTA_EOI 0x8001724c -#pragma Aux_register(0x8001724c, name=>"io_gpio2_porta_eoi") - -// User extension aux register io_gpio2_ext_porta -#define AR_IO_GPIO2_EXT_PORTA 0x80017250 -#pragma Aux_register(0x80017250, name=>"io_gpio2_ext_porta") - -// User extension aux register io_gpio2_ls_sync -#define AR_IO_GPIO2_LS_SYNC 0x80017260 -#pragma Aux_register(0x80017260, name=>"io_gpio2_ls_sync") - -// User extension aux register io_gpio2_int_bothedge -#define AR_IO_GPIO2_INT_BOTHEDGE 0x80017268 -#pragma Aux_register(0x80017268, name=>"io_gpio2_int_bothedge") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2C_MST1_PRESENT 1 - -// User extension aux register io_i2c_mst1_clken -#define AR_IO_I2C_MST1_CLKEN 0x800121c0 -#pragma Aux_register(0x800121c0, name=>"io_i2c_mst1_clken") - -// User extension aux register io_i2c_mst1_con -#define AR_IO_I2C_MST1_CON 0x80012100 -#pragma Aux_register(0x80012100, name=>"io_i2c_mst1_con") - -// User extension aux register io_i2c_mst1_tar -#define AR_IO_I2C_MST1_TAR 0x80012104 -#pragma Aux_register(0x80012104, name=>"io_i2c_mst1_tar") - -// User extension aux register io_i2c_mst1_data_cmd -#define AR_IO_I2C_MST1_DATA_CMD 0x80012110 -#pragma Aux_register(0x80012110, name=>"io_i2c_mst1_data_cmd") - -// User extension aux register io_i2c_mst1_ss_scl_hcnt -#define AR_IO_I2C_MST1_SS_SCL_HCNT 0x80012114 -#pragma Aux_register(0x80012114, name=>"io_i2c_mst1_ss_scl_hcnt") - -// User extension aux register io_i2c_mst1_ss_scl_lcnt -#define AR_IO_I2C_MST1_SS_SCL_LCNT 0x80012118 -#pragma Aux_register(0x80012118, name=>"io_i2c_mst1_ss_scl_lcnt") - -// User extension aux register io_i2c_mst1_fs_scl_hcnt -#define AR_IO_I2C_MST1_FS_SCL_HCNT 0x8001211c -#pragma Aux_register(0x8001211c, name=>"io_i2c_mst1_fs_scl_hcnt") - -// User extension aux register io_i2c_mst1_fs_scl_lcnt -#define AR_IO_I2C_MST1_FS_SCL_LCNT 0x80012120 -#pragma Aux_register(0x80012120, name=>"io_i2c_mst1_fs_scl_lcnt") - -// User extension aux register io_i2c_mst1_intr_stat -#define AR_IO_I2C_MST1_INTR_STAT 0x8001212c -#pragma Aux_register(0x8001212c, name=>"io_i2c_mst1_intr_stat") - -// User extension aux register io_i2c_mst1_intr_mask -#define AR_IO_I2C_MST1_INTR_MASK 0x80012130 -#pragma Aux_register(0x80012130, name=>"io_i2c_mst1_intr_mask") - -// User extension aux register io_i2c_mst1_raw_intr_stat -#define AR_IO_I2C_MST1_RAW_INTR_STAT 0x80012134 -#pragma Aux_register(0x80012134, name=>"io_i2c_mst1_raw_intr_stat") - -// User extension aux register io_i2c_mst1_rx_tl -#define AR_IO_I2C_MST1_RX_TL 0x80012138 -#pragma Aux_register(0x80012138, name=>"io_i2c_mst1_rx_tl") - -// User extension aux register io_i2c_mst1_tx_tl -#define AR_IO_I2C_MST1_TX_TL 0x8001213c -#pragma Aux_register(0x8001213c, name=>"io_i2c_mst1_tx_tl") - -// User extension aux register io_i2c_mst1_clr_intr -#define AR_IO_I2C_MST1_CLR_INTR 0x80012140 -#pragma Aux_register(0x80012140, name=>"io_i2c_mst1_clr_intr") - -// User extension aux register io_i2c_mst1_clr_rx_under -#define AR_IO_I2C_MST1_CLR_RX_UNDER 0x80012144 -#pragma Aux_register(0x80012144, name=>"io_i2c_mst1_clr_rx_under") - -// User extension aux register io_i2c_mst1_clr_rx_over -#define AR_IO_I2C_MST1_CLR_RX_OVER 0x80012148 -#pragma Aux_register(0x80012148, name=>"io_i2c_mst1_clr_rx_over") - -// User extension aux register io_i2c_mst1_clr_tx_over -#define AR_IO_I2C_MST1_CLR_TX_OVER 0x8001214c -#pragma Aux_register(0x8001214c, name=>"io_i2c_mst1_clr_tx_over") - -// User extension aux register io_i2c_mst1_clr_tx_abrt -#define AR_IO_I2C_MST1_CLR_TX_ABRT 0x80012154 -#pragma Aux_register(0x80012154, name=>"io_i2c_mst1_clr_tx_abrt") - -// User extension aux register io_i2c_mst1_clr_activity -#define AR_IO_I2C_MST1_CLR_ACTIVITY 0x8001215c -#pragma Aux_register(0x8001215c, name=>"io_i2c_mst1_clr_activity") - -// User extension aux register io_i2c_mst1_clr_stop_det -#define AR_IO_I2C_MST1_CLR_STOP_DET 0x80012160 -#pragma Aux_register(0x80012160, name=>"io_i2c_mst1_clr_stop_det") - -// User extension aux register io_i2c_mst1_clr_start_det -#define AR_IO_I2C_MST1_CLR_START_DET 0x80012164 -#pragma Aux_register(0x80012164, name=>"io_i2c_mst1_clr_start_det") - -// User extension aux register io_i2c_mst1_enable -#define AR_IO_I2C_MST1_ENABLE 0x8001216c -#pragma Aux_register(0x8001216c, name=>"io_i2c_mst1_enable") - -// User extension aux register io_i2c_mst1_status -#define AR_IO_I2C_MST1_STATUS 0x80012170 -#pragma Aux_register(0x80012170, name=>"io_i2c_mst1_status") - -// User extension aux register io_i2c_mst1_txflr -#define AR_IO_I2C_MST1_TXFLR 0x80012174 -#pragma Aux_register(0x80012174, name=>"io_i2c_mst1_txflr") - -// User extension aux register io_i2c_mst1_rxflr -#define AR_IO_I2C_MST1_RXFLR 0x80012178 -#pragma Aux_register(0x80012178, name=>"io_i2c_mst1_rxflr") - -// User extension aux register io_i2c_mst1_sda_hold -#define AR_IO_I2C_MST1_SDA_HOLD 0x8001217c -#pragma Aux_register(0x8001217c, name=>"io_i2c_mst1_sda_hold") - -// User extension aux register io_i2c_mst1_tx_abrt_source -#define AR_IO_I2C_MST1_TX_ABRT_SOURCE 0x80012180 -#pragma Aux_register(0x80012180, name=>"io_i2c_mst1_tx_abrt_source") - -// User extension aux register io_i2c_mst1_enable_status -#define AR_IO_I2C_MST1_ENABLE_STATUS 0x8001219c -#pragma Aux_register(0x8001219c, name=>"io_i2c_mst1_enable_status") - -// User extension aux register io_i2c_mst1_fs_spklen -#define AR_IO_I2C_MST1_FS_SPKLEN 0x800121a0 -#pragma Aux_register(0x800121a0, name=>"io_i2c_mst1_fs_spklen") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2C_MST2_PRESENT 1 - -// User extension aux register io_i2c_mst2_clken -#define AR_IO_I2C_MST2_CLKEN 0x800122c0 -#pragma Aux_register(0x800122c0, name=>"io_i2c_mst2_clken") - -// User extension aux register io_i2c_mst2_con -#define AR_IO_I2C_MST2_CON 0x80012200 -#pragma Aux_register(0x80012200, name=>"io_i2c_mst2_con") - -// User extension aux register io_i2c_mst2_tar -#define AR_IO_I2C_MST2_TAR 0x80012204 -#pragma Aux_register(0x80012204, name=>"io_i2c_mst2_tar") - -// User extension aux register io_i2c_mst2_data_cmd -#define AR_IO_I2C_MST2_DATA_CMD 0x80012210 -#pragma Aux_register(0x80012210, name=>"io_i2c_mst2_data_cmd") - -// User extension aux register io_i2c_mst2_ss_scl_hcnt -#define AR_IO_I2C_MST2_SS_SCL_HCNT 0x80012214 -#pragma Aux_register(0x80012214, name=>"io_i2c_mst2_ss_scl_hcnt") - -// User extension aux register io_i2c_mst2_ss_scl_lcnt -#define AR_IO_I2C_MST2_SS_SCL_LCNT 0x80012218 -#pragma Aux_register(0x80012218, name=>"io_i2c_mst2_ss_scl_lcnt") - -// User extension aux register io_i2c_mst2_fs_scl_hcnt -#define AR_IO_I2C_MST2_FS_SCL_HCNT 0x8001221c -#pragma Aux_register(0x8001221c, name=>"io_i2c_mst2_fs_scl_hcnt") - -// User extension aux register io_i2c_mst2_fs_scl_lcnt -#define AR_IO_I2C_MST2_FS_SCL_LCNT 0x80012220 -#pragma Aux_register(0x80012220, name=>"io_i2c_mst2_fs_scl_lcnt") - -// User extension aux register io_i2c_mst2_intr_stat -#define AR_IO_I2C_MST2_INTR_STAT 0x8001222c -#pragma Aux_register(0x8001222c, name=>"io_i2c_mst2_intr_stat") - -// User extension aux register io_i2c_mst2_intr_mask -#define AR_IO_I2C_MST2_INTR_MASK 0x80012230 -#pragma Aux_register(0x80012230, name=>"io_i2c_mst2_intr_mask") - -// User extension aux register io_i2c_mst2_raw_intr_stat -#define AR_IO_I2C_MST2_RAW_INTR_STAT 0x80012234 -#pragma Aux_register(0x80012234, name=>"io_i2c_mst2_raw_intr_stat") - -// User extension aux register io_i2c_mst2_rx_tl -#define AR_IO_I2C_MST2_RX_TL 0x80012238 -#pragma Aux_register(0x80012238, name=>"io_i2c_mst2_rx_tl") - -// User extension aux register io_i2c_mst2_tx_tl -#define AR_IO_I2C_MST2_TX_TL 0x8001223c -#pragma Aux_register(0x8001223c, name=>"io_i2c_mst2_tx_tl") - -// User extension aux register io_i2c_mst2_clr_intr -#define AR_IO_I2C_MST2_CLR_INTR 0x80012240 -#pragma Aux_register(0x80012240, name=>"io_i2c_mst2_clr_intr") - -// User extension aux register io_i2c_mst2_clr_rx_under -#define AR_IO_I2C_MST2_CLR_RX_UNDER 0x80012244 -#pragma Aux_register(0x80012244, name=>"io_i2c_mst2_clr_rx_under") - -// User extension aux register io_i2c_mst2_clr_rx_over -#define AR_IO_I2C_MST2_CLR_RX_OVER 0x80012248 -#pragma Aux_register(0x80012248, name=>"io_i2c_mst2_clr_rx_over") - -// User extension aux register io_i2c_mst2_clr_tx_over -#define AR_IO_I2C_MST2_CLR_TX_OVER 0x8001224c -#pragma Aux_register(0x8001224c, name=>"io_i2c_mst2_clr_tx_over") - -// User extension aux register io_i2c_mst2_clr_tx_abrt -#define AR_IO_I2C_MST2_CLR_TX_ABRT 0x80012254 -#pragma Aux_register(0x80012254, name=>"io_i2c_mst2_clr_tx_abrt") - -// User extension aux register io_i2c_mst2_clr_activity -#define AR_IO_I2C_MST2_CLR_ACTIVITY 0x8001225c -#pragma Aux_register(0x8001225c, name=>"io_i2c_mst2_clr_activity") - -// User extension aux register io_i2c_mst2_clr_stop_det -#define AR_IO_I2C_MST2_CLR_STOP_DET 0x80012260 -#pragma Aux_register(0x80012260, name=>"io_i2c_mst2_clr_stop_det") - -// User extension aux register io_i2c_mst2_clr_start_det -#define AR_IO_I2C_MST2_CLR_START_DET 0x80012264 -#pragma Aux_register(0x80012264, name=>"io_i2c_mst2_clr_start_det") - -// User extension aux register io_i2c_mst2_enable -#define AR_IO_I2C_MST2_ENABLE 0x8001226c -#pragma Aux_register(0x8001226c, name=>"io_i2c_mst2_enable") - -// User extension aux register io_i2c_mst2_status -#define AR_IO_I2C_MST2_STATUS 0x80012270 -#pragma Aux_register(0x80012270, name=>"io_i2c_mst2_status") - -// User extension aux register io_i2c_mst2_txflr -#define AR_IO_I2C_MST2_TXFLR 0x80012274 -#pragma Aux_register(0x80012274, name=>"io_i2c_mst2_txflr") - -// User extension aux register io_i2c_mst2_rxflr -#define AR_IO_I2C_MST2_RXFLR 0x80012278 -#pragma Aux_register(0x80012278, name=>"io_i2c_mst2_rxflr") - -// User extension aux register io_i2c_mst2_sda_hold -#define AR_IO_I2C_MST2_SDA_HOLD 0x8001227c -#pragma Aux_register(0x8001227c, name=>"io_i2c_mst2_sda_hold") - -// User extension aux register io_i2c_mst2_tx_abrt_source -#define AR_IO_I2C_MST2_TX_ABRT_SOURCE 0x80012280 -#pragma Aux_register(0x80012280, name=>"io_i2c_mst2_tx_abrt_source") - -// User extension aux register io_i2c_mst2_enable_status -#define AR_IO_I2C_MST2_ENABLE_STATUS 0x8001229c -#pragma Aux_register(0x8001229c, name=>"io_i2c_mst2_enable_status") - -// User extension aux register io_i2c_mst2_fs_spklen -#define AR_IO_I2C_MST2_FS_SPKLEN 0x800122a0 -#pragma Aux_register(0x800122a0, name=>"io_i2c_mst2_fs_spklen") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_UART0_PRESENT 1 - -// User extension aux register io_uart0_clken -#define AR_IO_UART0_CLKEN 0x800140c0 -#pragma Aux_register(0x800140c0, name=>"io_uart0_clken") - -// User extension aux register io_uart0_rbr_thr_dll -#define AR_IO_UART0_RBR_THR_DLL 0x80014000 -#pragma Aux_register(0x80014000, name=>"io_uart0_rbr_thr_dll") - -// User extension aux register io_uart0_ier_dlh -#define AR_IO_UART0_IER_DLH 0x80014004 -#pragma Aux_register(0x80014004, name=>"io_uart0_ier_dlh") - -// User extension aux register io_uart0_iir_fcr -#define AR_IO_UART0_IIR_FCR 0x80014008 -#pragma Aux_register(0x80014008, name=>"io_uart0_iir_fcr") - -// User extension aux register io_uart0_lcr -#define AR_IO_UART0_LCR 0x8001400c -#pragma Aux_register(0x8001400c, name=>"io_uart0_lcr") - -// User extension aux register io_uart0_mcr -#define AR_IO_UART0_MCR 0x80014010 -#pragma Aux_register(0x80014010, name=>"io_uart0_mcr") - -// User extension aux register io_uart0_lsr -#define AR_IO_UART0_LSR 0x80014014 -#pragma Aux_register(0x80014014, name=>"io_uart0_lsr") - -// User extension aux register io_uart0_msr -#define AR_IO_UART0_MSR 0x80014018 -#pragma Aux_register(0x80014018, name=>"io_uart0_msr") - -// User extension aux register io_uart0_usr -#define AR_IO_UART0_USR 0x8001407c -#pragma Aux_register(0x8001407c, name=>"io_uart0_usr") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_UART1_PRESENT 1 - -// User extension aux register io_uart1_clken -#define AR_IO_UART1_CLKEN 0x800141c0 -#pragma Aux_register(0x800141c0, name=>"io_uart1_clken") - -// User extension aux register io_uart1_rbr_thr_dll -#define AR_IO_UART1_RBR_THR_DLL 0x80014100 -#pragma Aux_register(0x80014100, name=>"io_uart1_rbr_thr_dll") - -// User extension aux register io_uart1_ier_dlh -#define AR_IO_UART1_IER_DLH 0x80014104 -#pragma Aux_register(0x80014104, name=>"io_uart1_ier_dlh") - -// User extension aux register io_uart1_iir_fcr -#define AR_IO_UART1_IIR_FCR 0x80014108 -#pragma Aux_register(0x80014108, name=>"io_uart1_iir_fcr") - -// User extension aux register io_uart1_lcr -#define AR_IO_UART1_LCR 0x8001410c -#pragma Aux_register(0x8001410c, name=>"io_uart1_lcr") - -// User extension aux register io_uart1_mcr -#define AR_IO_UART1_MCR 0x80014110 -#pragma Aux_register(0x80014110, name=>"io_uart1_mcr") - -// User extension aux register io_uart1_lsr -#define AR_IO_UART1_LSR 0x80014114 -#pragma Aux_register(0x80014114, name=>"io_uart1_lsr") - -// User extension aux register io_uart1_msr -#define AR_IO_UART1_MSR 0x80014118 -#pragma Aux_register(0x80014118, name=>"io_uart1_msr") - -// User extension aux register io_uart1_usr -#define AR_IO_UART1_USR 0x8001417c -#pragma Aux_register(0x8001417c, name=>"io_uart1_usr") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_UART2_PRESENT 1 - -// User extension aux register io_uart2_clken -#define AR_IO_UART2_CLKEN 0x800142c0 -#pragma Aux_register(0x800142c0, name=>"io_uart2_clken") - -// User extension aux register io_uart2_rbr_thr_dll -#define AR_IO_UART2_RBR_THR_DLL 0x80014200 -#pragma Aux_register(0x80014200, name=>"io_uart2_rbr_thr_dll") - -// User extension aux register io_uart2_ier_dlh -#define AR_IO_UART2_IER_DLH 0x80014204 -#pragma Aux_register(0x80014204, name=>"io_uart2_ier_dlh") - -// User extension aux register io_uart2_iir_fcr -#define AR_IO_UART2_IIR_FCR 0x80014208 -#pragma Aux_register(0x80014208, name=>"io_uart2_iir_fcr") - -// User extension aux register io_uart2_lcr -#define AR_IO_UART2_LCR 0x8001420c -#pragma Aux_register(0x8001420c, name=>"io_uart2_lcr") - -// User extension aux register io_uart2_mcr -#define AR_IO_UART2_MCR 0x80014210 -#pragma Aux_register(0x80014210, name=>"io_uart2_mcr") - -// User extension aux register io_uart2_lsr -#define AR_IO_UART2_LSR 0x80014214 -#pragma Aux_register(0x80014214, name=>"io_uart2_lsr") - -// User extension aux register io_uart2_msr -#define AR_IO_UART2_MSR 0x80014218 -#pragma Aux_register(0x80014218, name=>"io_uart2_msr") - -// User extension aux register io_uart2_usr -#define AR_IO_UART2_USR 0x8001427c -#pragma Aux_register(0x8001427c, name=>"io_uart2_usr") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_UART3_PRESENT 1 - -// User extension aux register io_uart3_clken -#define AR_IO_UART3_CLKEN 0x800143c0 -#pragma Aux_register(0x800143c0, name=>"io_uart3_clken") - -// User extension aux register io_uart3_rbr_thr_dll -#define AR_IO_UART3_RBR_THR_DLL 0x80014300 -#pragma Aux_register(0x80014300, name=>"io_uart3_rbr_thr_dll") - -// User extension aux register io_uart3_ier_dlh -#define AR_IO_UART3_IER_DLH 0x80014304 -#pragma Aux_register(0x80014304, name=>"io_uart3_ier_dlh") - -// User extension aux register io_uart3_iir_fcr -#define AR_IO_UART3_IIR_FCR 0x80014308 -#pragma Aux_register(0x80014308, name=>"io_uart3_iir_fcr") - -// User extension aux register io_uart3_lcr -#define AR_IO_UART3_LCR 0x8001430c -#pragma Aux_register(0x8001430c, name=>"io_uart3_lcr") - -// User extension aux register io_uart3_mcr -#define AR_IO_UART3_MCR 0x80014310 -#pragma Aux_register(0x80014310, name=>"io_uart3_mcr") - -// User extension aux register io_uart3_lsr -#define AR_IO_UART3_LSR 0x80014314 -#pragma Aux_register(0x80014314, name=>"io_uart3_lsr") - -// User extension aux register io_uart3_msr -#define AR_IO_UART3_MSR 0x80014318 -#pragma Aux_register(0x80014318, name=>"io_uart3_msr") - -// User extension aux register io_uart3_usr -#define AR_IO_UART3_USR 0x8001437c -#pragma Aux_register(0x8001437c, name=>"io_uart3_usr") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2S_RX_MST0_PRESENT 1 - -// User extension aux register io_i2s_rx_mst0_ier -#define AR_IO_I2S_RX_MST0_IER 0x8001a000 -#pragma Aux_register(0x8001a000, name=>"io_i2s_rx_mst0_ier") - -// User extension aux register io_i2s_rx_mst0_irer -#define AR_IO_I2S_RX_MST0_IRER 0x8001a004 -#pragma Aux_register(0x8001a004, name=>"io_i2s_rx_mst0_irer") - -// User extension aux register io_i2s_rx_mst0_cer -#define AR_IO_I2S_RX_MST0_CER 0x8001a00c -#pragma Aux_register(0x8001a00c, name=>"io_i2s_rx_mst0_cer") - -// User extension aux register io_i2s_rx_mst0_ccr -#define AR_IO_I2S_RX_MST0_CCR 0x8001a010 -#pragma Aux_register(0x8001a010, name=>"io_i2s_rx_mst0_ccr") - -// User extension aux register io_i2s_rx_mst0_rxffr -#define AR_IO_I2S_RX_MST0_RXFFR 0x8001a014 -#pragma Aux_register(0x8001a014, name=>"io_i2s_rx_mst0_rxffr") - -// User extension aux register io_i2s_rx_mst0_lrbr -#define AR_IO_I2S_RX_MST0_LRBR 0x8001a020 -#pragma Aux_register(0x8001a020, name=>"io_i2s_rx_mst0_lrbr") - -// User extension aux register io_i2s_rx_mst0_rrbr -#define AR_IO_I2S_RX_MST0_RRBR 0x8001a024 -#pragma Aux_register(0x8001a024, name=>"io_i2s_rx_mst0_rrbr") - -// User extension aux register io_i2s_rx_mst0_rer -#define AR_IO_I2S_RX_MST0_RER 0x8001a028 -#pragma Aux_register(0x8001a028, name=>"io_i2s_rx_mst0_rer") - -// User extension aux register io_i2s_rx_mst0_rcr -#define AR_IO_I2S_RX_MST0_RCR 0x8001a030 -#pragma Aux_register(0x8001a030, name=>"io_i2s_rx_mst0_rcr") - -// User extension aux register io_i2s_rx_mst0_isr -#define AR_IO_I2S_RX_MST0_ISR 0x8001a038 -#pragma Aux_register(0x8001a038, name=>"io_i2s_rx_mst0_isr") - -// User extension aux register io_i2s_rx_mst0_imr -#define AR_IO_I2S_RX_MST0_IMR 0x8001a03c -#pragma Aux_register(0x8001a03c, name=>"io_i2s_rx_mst0_imr") - -// User extension aux register io_i2s_rx_mst0_ror -#define AR_IO_I2S_RX_MST0_ROR 0x8001a040 -#pragma Aux_register(0x8001a040, name=>"io_i2s_rx_mst0_ror") - -// User extension aux register io_i2s_rx_mst0_rfcr -#define AR_IO_I2S_RX_MST0_RFCR 0x8001a048 -#pragma Aux_register(0x8001a048, name=>"io_i2s_rx_mst0_rfcr") - -// User extension aux register io_i2s_rx_mst0_rff -#define AR_IO_I2S_RX_MST0_RFF 0x8001a050 -#pragma Aux_register(0x8001a050, name=>"io_i2s_rx_mst0_rff") - -// User extension aux register io_i2s_rx_mst0_rxdma -#define AR_IO_I2S_RX_MST0_RXDMA 0x8001a1c0 -#pragma Aux_register(0x8001a1c0, name=>"io_i2s_rx_mst0_rxdma") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2S_TX_MST0_PRESENT 1 - -// User extension aux register io_i2s_tx_mst0_ier -#define AR_IO_I2S_TX_MST0_IER 0x80019000 -#pragma Aux_register(0x80019000, name=>"io_i2s_tx_mst0_ier") - -// User extension aux register io_i2s_tx_mst0_iter -#define AR_IO_I2S_TX_MST0_ITER 0x80019008 -#pragma Aux_register(0x80019008, name=>"io_i2s_tx_mst0_iter") - -// User extension aux register io_i2s_tx_mst0_cer -#define AR_IO_I2S_TX_MST0_CER 0x8001900c -#pragma Aux_register(0x8001900c, name=>"io_i2s_tx_mst0_cer") - -// User extension aux register io_i2s_tx_mst0_ccr -#define AR_IO_I2S_TX_MST0_CCR 0x80019010 -#pragma Aux_register(0x80019010, name=>"io_i2s_tx_mst0_ccr") - -// User extension aux register io_i2s_tx_mst0_txffr -#define AR_IO_I2S_TX_MST0_TXFFR 0x80019018 -#pragma Aux_register(0x80019018, name=>"io_i2s_tx_mst0_txffr") - -// User extension aux register io_i2s_tx_mst0_lthr -#define AR_IO_I2S_TX_MST0_LTHR 0x80019020 -#pragma Aux_register(0x80019020, name=>"io_i2s_tx_mst0_lthr") - -// User extension aux register io_i2s_tx_mst0_rthr -#define AR_IO_I2S_TX_MST0_RTHR 0x80019024 -#pragma Aux_register(0x80019024, name=>"io_i2s_tx_mst0_rthr") - -// User extension aux register io_i2s_tx_mst0_ter -#define AR_IO_I2S_TX_MST0_TER 0x8001902c -#pragma Aux_register(0x8001902c, name=>"io_i2s_tx_mst0_ter") - -// User extension aux register io_i2s_tx_mst0_tcr -#define AR_IO_I2S_TX_MST0_TCR 0x80019034 -#pragma Aux_register(0x80019034, name=>"io_i2s_tx_mst0_tcr") - -// User extension aux register io_i2s_tx_mst0_isr -#define AR_IO_I2S_TX_MST0_ISR 0x80019038 -#pragma Aux_register(0x80019038, name=>"io_i2s_tx_mst0_isr") - -// User extension aux register io_i2s_tx_mst0_imr -#define AR_IO_I2S_TX_MST0_IMR 0x8001903c -#pragma Aux_register(0x8001903c, name=>"io_i2s_tx_mst0_imr") - -// User extension aux register io_i2s_tx_mst0_tor -#define AR_IO_I2S_TX_MST0_TOR 0x80019044 -#pragma Aux_register(0x80019044, name=>"io_i2s_tx_mst0_tor") - -// User extension aux register io_i2s_tx_mst0_tfcr -#define AR_IO_I2S_TX_MST0_TFCR 0x8001904c -#pragma Aux_register(0x8001904c, name=>"io_i2s_tx_mst0_tfcr") - -// User extension aux register io_i2s_tx_mst0_tff -#define AR_IO_I2S_TX_MST0_TFF 0x80019054 -#pragma Aux_register(0x80019054, name=>"io_i2s_tx_mst0_tff") - -// User extension aux register io_i2s_tx_mst0_txdma -#define AR_IO_I2S_TX_MST0_TXDMA 0x800191c8 -#pragma Aux_register(0x800191c8, name=>"io_i2s_tx_mst0_txdma") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_PDM_RX0_PRESENT 1 - -// User extension aux register io_pdm_rx0_pdm_en -#define AR_IO_PDM_RX0_PDM_EN 0x8001b000 -#pragma Aux_register(0x8001b000, name=>"io_pdm_rx0_pdm_en") - -// User extension aux register io_pdm_rx0_pdm_ren -#define AR_IO_PDM_RX0_PDM_REN 0x8001b004 -#pragma Aux_register(0x8001b004, name=>"io_pdm_rx0_pdm_ren") - -// User extension aux register io_pdm_rx0_cer -#define AR_IO_PDM_RX0_CER 0x8001b00c -#pragma Aux_register(0x8001b00c, name=>"io_pdm_rx0_cer") - -// User extension aux register io_pdm_rx0_rxffr -#define AR_IO_PDM_RX0_RXFFR 0x8001b014 -#pragma Aux_register(0x8001b014, name=>"io_pdm_rx0_rxffr") - -// User extension aux register io_pdm_rx0_rer0 -#define AR_IO_PDM_RX0_RER0 0x8001b028 -#pragma Aux_register(0x8001b028, name=>"io_pdm_rx0_rer0") - -// User extension aux register io_pdm_rx0_isr -#define AR_IO_PDM_RX0_ISR 0x8001b038 -#pragma Aux_register(0x8001b038, name=>"io_pdm_rx0_isr") - -// User extension aux register io_pdm_rx0_imr -#define AR_IO_PDM_RX0_IMR 0x8001b03c -#pragma Aux_register(0x8001b03c, name=>"io_pdm_rx0_imr") - -// User extension aux register io_pdm_rx0_ror -#define AR_IO_PDM_RX0_ROR 0x8001b040 -#pragma Aux_register(0x8001b040, name=>"io_pdm_rx0_ror") - -// User extension aux register io_pdm_rx0_rfcr -#define AR_IO_PDM_RX0_RFCR 0x8001b048 -#pragma Aux_register(0x8001b048, name=>"io_pdm_rx0_rfcr") - -// User extension aux register io_pdm_rx0_rxdma -#define AR_IO_PDM_RX0_RXDMA 0x8001b1c0 -#pragma Aux_register(0x8001b1c0, name=>"io_pdm_rx0_rxdma") - -// User extension aux register io_pdm_rx0_pdm_rr -#define AR_IO_PDM_RX0_PDM_RR 0x8001b1d0 -#pragma Aux_register(0x8001b1d0, name=>"io_pdm_rx0_pdm_rr") - -// User extension aux register io_pdm_rx0_cic_n -#define AR_IO_PDM_RX0_CIC_N 0x8001b1d4 -#pragma Aux_register(0x8001b1d4, name=>"io_pdm_rx0_cic_n") - -// User extension aux register io_pdm_rx0_cic_d -#define AR_IO_PDM_RX0_CIC_D 0x8001b1d8 -#pragma Aux_register(0x8001b1d8, name=>"io_pdm_rx0_cic_d") - -// User extension aux register io_pdm_rx0_dcrc -#define AR_IO_PDM_RX0_DCRC 0x8001b1dc -#pragma Aux_register(0x8001b1dc, name=>"io_pdm_rx0_dcrc") - -// User extension aux register io_pdm_rx0_brc_b0 -#define AR_IO_PDM_RX0_BRC_B0 0x8001b1e0 -#pragma Aux_register(0x8001b1e0, name=>"io_pdm_rx0_brc_b0") - -// User extension aux register io_pdm_rx0_brc_clp -#define AR_IO_PDM_RX0_BRC_CLP 0x8001b1f0 -#pragma Aux_register(0x8001b1f0, name=>"io_pdm_rx0_brc_clp") -#define APEX_COM_ARC_HARDWARE_FLOATING_POINT_UNIT_FPU_PRESENT 1 - -// User extension aux register fpu_build -#define AR_FPU_BUILD 0xc8 -#pragma Aux_register(0xc8, name=>"fpu_build") - -// User extension aux register fpu_ctrl -#define AR_FPU_CTRL 0x300 -#pragma Aux_register(0x300, name=>"fpu_ctrl") - -// User extension aux register fpu_status -#define AR_FPU_STATUS 0x301 -#pragma Aux_register(0x301, name=>"fpu_status") - -// User extension instruction fsmadd -extern long fsmadd(long,long); -#pragma intrinsic(fsmadd,opcode=>6,sub_opcode=>5, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fsmsub -extern long fsmsub(long,long); -#pragma intrinsic(fsmsub,opcode=>6,sub_opcode=>6, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fsmul -extern long fsmul(long,long); -#pragma intrinsic(fsmul,opcode=>6,sub_opcode=>0, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fsadd -extern long fsadd(long,long); -#pragma intrinsic(fsadd,opcode=>6,sub_opcode=>1, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fssub -extern long fssub(long,long); -#pragma intrinsic(fssub,opcode=>6,sub_opcode=>2, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fcvt32 -extern long fcvt32(long,long); -#pragma intrinsic(fcvt32,opcode=>6,sub_opcode=>8, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fsdiv -extern long fsdiv(long,long); -#pragma intrinsic(fsdiv,opcode=>6,sub_opcode=>7, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fscmp -extern long fscmp(long,long); -#pragma intrinsic(fscmp,opcode=>6,sub_opcode=>3, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fscmp -extern long fscmp_f(long,long); -#pragma intrinsic(fscmp_f,opcode=>6,sub_opcode=>3, set_flags => 1, flags => "zncv", effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fscmpf -extern long fscmpf(long,long); -#pragma intrinsic(fscmpf,opcode=>6,sub_opcode=>4, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fscmpf -extern long fscmpf_f(long,long); -#pragma intrinsic(fscmpf_f,opcode=>6,sub_opcode=>4, set_flags => 1, flags => "zncv", effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fssqrt -extern long fssqrt(long); -#pragma intrinsic(fssqrt,opcode=>6,sub_opcode=>0, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") -#define APEX_COM_ARC_HARDWARE_FLOATING_POINT_UNIT_FPU_DP_ASSIST_PRESENT 1 - -// User extension aux register aux_dpfp1l -#define AR_AUX_DPFP1L 0x302 -#pragma Aux_register(0x302, name=>"aux_dpfp1l") - -// User extension aux register aux_dpfp1h -#define AR_AUX_DPFP1H 0x303 -#pragma Aux_register(0x303, name=>"aux_dpfp1h") - -// User extension aux register aux_dpfp2l -#define AR_AUX_DPFP2L 0x304 -#pragma Aux_register(0x304, name=>"aux_dpfp2l") - -// User extension aux register aux_dpfp2h -#define AR_AUX_DPFP2H 0x305 -#pragma Aux_register(0x305, name=>"aux_dpfp2h") - -// User extension instruction dmulh11 -extern long dmulh11(long,long); -#pragma intrinsic(dmulh11,opcode=>6,sub_opcode=>48,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh11 -extern long dmulh11_f(long,long); -#pragma intrinsic(dmulh11_f,opcode=>6,sub_opcode=>48, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh12 -extern long dmulh12(long,long); -#pragma intrinsic(dmulh12,opcode=>6,sub_opcode=>49,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh12 -extern long dmulh12_f(long,long); -#pragma intrinsic(dmulh12_f,opcode=>6,sub_opcode=>49, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh21 -extern long dmulh21(long,long); -#pragma intrinsic(dmulh21,opcode=>6,sub_opcode=>50,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh21 -extern long dmulh21_f(long,long); -#pragma intrinsic(dmulh21_f,opcode=>6,sub_opcode=>50, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh22 -extern long dmulh22(long,long); -#pragma intrinsic(dmulh22,opcode=>6,sub_opcode=>51,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh22 -extern long dmulh22_f(long,long); -#pragma intrinsic(dmulh22_f,opcode=>6,sub_opcode=>51, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh11 -extern long daddh11(long,long); -#pragma intrinsic(daddh11,opcode=>6,sub_opcode=>52,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh11 -extern long daddh11_f(long,long); -#pragma intrinsic(daddh11_f,opcode=>6,sub_opcode=>52, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh12 -extern long daddh12(long,long); -#pragma intrinsic(daddh12,opcode=>6,sub_opcode=>53,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh12 -extern long daddh12_f(long,long); -#pragma intrinsic(daddh12_f,opcode=>6,sub_opcode=>53, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh21 -extern long daddh21(long,long); -#pragma intrinsic(daddh21,opcode=>6,sub_opcode=>54,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh21 -extern long daddh21_f(long,long); -#pragma intrinsic(daddh21_f,opcode=>6,sub_opcode=>54, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh22 -extern long daddh22(long,long); -#pragma intrinsic(daddh22,opcode=>6,sub_opcode=>55,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh22 -extern long daddh22_f(long,long); -#pragma intrinsic(daddh22_f,opcode=>6,sub_opcode=>55, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh11 -extern long dsubh11(long,long); -#pragma intrinsic(dsubh11,opcode=>6,sub_opcode=>56,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh11 -extern long dsubh11_f(long,long); -#pragma intrinsic(dsubh11_f,opcode=>6,sub_opcode=>56, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh12 -extern long dsubh12(long,long); -#pragma intrinsic(dsubh12,opcode=>6,sub_opcode=>57,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh12 -extern long dsubh12_f(long,long); -#pragma intrinsic(dsubh12_f,opcode=>6,sub_opcode=>57, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh21 -extern long dsubh21(long,long); -#pragma intrinsic(dsubh21,opcode=>6,sub_opcode=>58,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh21 -extern long dsubh21_f(long,long); -#pragma intrinsic(dsubh21_f,opcode=>6,sub_opcode=>58, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh22 -extern long dsubh22(long,long); -#pragma intrinsic(dsubh22,opcode=>6,sub_opcode=>59,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh22 -extern long dsubh22_f(long,long); -#pragma intrinsic(dsubh22_f,opcode=>6,sub_opcode=>59, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dexcl1 -extern long dexcl1(long,long); -#pragma intrinsic(dexcl1,opcode=>6,sub_opcode=>60, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dexcl2 -extern long dexcl2(long,long); -#pragma intrinsic(dexcl2,opcode=>6,sub_opcode=>61, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - - -#endif - - -]]> - - - - - - diff --git a/board/emsdp/rev1/configs/emsdp_hardware.h b/board/emsdp/rev1/configs/emsdp_hardware.h deleted file mode 100644 index f1eaa3498..000000000 --- a/board/emsdp/rev1/configs/emsdp_hardware.h +++ /dev/null @@ -1,103 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------- */ -#ifndef __EMSDP_HARDWARE_H__ -#define __EMSDP_HARDWARE_H__ - -#include "arc_feature_config.h" -#include "apexextensions.h" - -/** - * Clock Definitions - */ -#define EMSDP_REF_CLOCK (100000000U) - -#define EMSDP_UART_REF_CLOCK (100000000U) -#define EMSDP_AUDIO_REF_CLOCK (24576000U) -#define EMSDP_SPI_REF_CLOCK (20000000U) - -#if (defined(FAST_UART) ) - #define EMSDP_UART_BAUDRATE (6250000U) -#else - #define EMSDP_UART_BAUDRATE (115200) -#endif - -#define EMSDP_I2C_CLOCK (EMSDP_REF_CLOCK) -#define EMSDP_PWM_TIMER_CLOCK (EMSDP_REF_CLOCK) - -/** CPU Clock Frequency definition */ -#if defined(BOARD_CPU_FREQ) - /*!< Get cpu clock frequency definition from build system */ - #define CLK_CPU (BOARD_CPU_FREQ) -#elif defined(ARC_FEATURE_CPU_CLOCK_FREQ) - /*!< Get cpu clock frequency definition from tcf file */ - #define CLK_CPU (40000000U)//(ARC_FEATURE_CPU_CLOCK_FREQ) -#else - /*!< Default cpu clock frequency */ - #define CLK_CPU (50000000U) -#endif - -/** Peripheral Bus Reference Clock definition */ -#ifdef BOARD_DEV_FREQ - /*!< Get peripheral bus reference clock defintion from build system */ - #define CLK_BUS_APB (BOARD_DEV_FREQ) -#else - /*!< Default peripheral bus reference clock defintion */ - #define CLK_BUS_APB (100000000U) -#endif - -//APB Peripheral address map -#define EMSDP_CRU_BASE (0xF0000000U) -#define EMSDP_CREG_BASE (0xF0001000U) -#define EMSDP_GPIO_BASE (0xF0002000U) -#define EMSDP_TRNG_BASE (0xF0003000U) -#define EMSDP_DBG_UART_BASE (0xF0004000U) -#define EMSDP_WDT_BASE (0xF0005000U) -#define EMSDP_TIMERS0_BASE (0xF0006000U) -#define EMSDP_TIMERS1_BASE (0xF0007000U) -#define EMSDP_SPI_BASE (0xF0008000U) -#define EMSDP_UART_BASE (0xF0009000U) -#define EMSDP_SDIO_BASE (0xF0010000U) -#define EMSDP_FLASH_BASE (0xF1000000U) -#define EMSDP_EBI_BASE (0xF2000000U) -#define EMSDP_PSRAM_BASE (0xF2001000U) - -//CREG Control Register Map -#define EMSDP_CREG_BOOT_OFFSET (0x0000) -#define EMSDP_CREG_START_OFFSET (0x0010) -#define EMSDP_CREG_PMOD_MUX_OFFSET (0x0030) -#define EMSDP_CREG_ARDUINO_MUX_OFFSET (0x0034) -#define EMSDP_CREG_GENERIC_MUX_OFFSET (0x0038) -#define EMSDP_CREG_IP_SW_RESET_OFFSET (0x1FF0) -#define EMSDP_CREG_IP_VERSION_OFFSET (0x1FF8) -#define EMSDP_CREG_IP_TYPE_OFFSET (0x1FFC) - -#include "core_hardware.h" - -#endif //__EMSDP_HARDWARE_H__ diff --git a/board/emsdp/rev1/configs/target_mem_config.h b/board/emsdp/rev1/configs/target_mem_config.h deleted file mode 100644 index 6e42b6f18..000000000 --- a/board/emsdp/rev1/configs/target_mem_config.h +++ /dev/null @@ -1,150 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------- */ -#ifndef _TARGET_MEM_CONFIG_H_ -#define _TARGET_MEM_CONFIG_H_ - -#include "arc_feature_config.h" - -#ifdef USE_APPL_MEM_CONFIG -#include "appl_mem_config.h" -#endif - -/** - * The unit of XXXX_SIZE is Byte - * For REGION_ROM, ICCM, EXT_ROM and EXT_RAM are available - * For REGION_RAM, DCCM and EXT_RAM are available - */ -#ifdef ARC_FEATURE_ICCM_PRESENT -#ifndef ICCM_SIZE -#define ICCM_SIZE ARC_FEATURE_ICCM_SIZE -#endif -#ifndef ICCM_START -#define ICCM_START ARC_FEATURE_ICCM_BASE -#endif -#else -#ifndef ICCM_SIZE -#define ICCM_SIZE 0x20000 -#endif -#ifndef ICCM_START -#define ICCM_START 0x60000000 -#endif -#endif - -#ifdef ARC_FEATURE_DCCM_PRESENT -#ifndef DCCM_SIZE -#define DCCM_SIZE ARC_FEATURE_DCCM_SIZE -#endif -#ifndef DCCM_START -#define DCCM_START ARC_FEATURE_DCCM_BASE -#endif -#else -#ifndef DCCM_SIZE -#define DCCM_SIZE 0x20000 -#endif -#ifndef DCCM_START -#define DCCM_START 0x80000000 -#endif -#endif - -#ifndef EXT_ROM_START -#define EXT_ROM_START 0x00000000 -#endif - -#ifndef EXT_ROM_SIZE -#define EXT_ROM_SIZE 0x40000 -#endif - -#ifndef EXT_RAM_START -#define EXT_RAM_START 0x10000000 -#endif - -#ifndef EXT_RAM_SIZE -#define EXT_RAM_SIZE 0x1000000 -#endif - -/** - * The default regions assigned for application to use, - by default, each region will use all the space - of each memory device - * User can config the start address and the size of - the regions to limit the application using - */ -#ifndef REGION_ICCM_START -#define REGION_ICCM_START ICCM_START -#define REGION_ICCM_SIZE ICCM_SIZE -#endif - -#ifndef REGION_DCCM_START -#define REGION_DCCM_START DCCM_START -#define REGION_DCCM_SIZE DCCM_SIZE -#endif - -#ifndef REGION_EXT_RAM_START -#define REGION_EXT_RAM_START EXT_RAM_START -#define REGION_EXT_RAM_SIZE EXT_RAM_SIZE -#endif - -#ifdef LIB_MCUBOOT -#error "EMSDP doesnot support MCUBOOT now" - -#else /* !defined(LIB_MCUBOOT) */ - -#ifndef REGION_EXT_ROM_START -#define REGION_EXT_ROM_START EXT_ROM_START -#define REGION_EXT_ROM_SIZE EXT_ROM_SIZE -#endif - -#define IMAGE_HEAD_SIZE 0x0 -#endif /* LIB_MCUBOOT */ - - -/** - * The default regions used to generate link script - * User can select region by configuring REGION_ROM and REGION_RAM - * For REGION_ROM, REGION_ICCM, REGION_EXT_ROM are available - * For REGION_RAM, REGION_DCCM and REGION_EXT_RAM are available - */ -#ifndef REGION_ROM -#ifdef ARC_FEATURE_ICACHE_PRESENT -#define REGION_ROM REGION_EXT_RAM -#else -#define REGION_ROM REGION_ICCM -#endif -#endif - -#ifndef REGION_RAM -#ifdef ARC_FEATURE_DCACHE_PRESENT -#define REGION_RAM REGION_EXT_RAM -#else -#define REGION_RAM REGION_DCCM -#endif -#endif - -#endif /* _TARGET_MEM_CONFIG_H_ */ From c3f5a08b77d098f014b6c8afc6b1021cef3f6ccd Mon Sep 17 00:00:00 2001 From: Wayne Ren Date: Thu, 10 Jan 2019 14:04:02 +0800 Subject: [PATCH 13/28] board: emsdp: optimzie the structure of emsdp bsp user can directly copy or unzip the downloaded emsdp config package under the folder of configs to create a customizd core config Signed-off-by: Wayne Ren --- board/emsdp/emsdp.mk | 4 +- board/emsdp/rev2/configs/core_configs.mk | 6 +- .../rev2/configs/em11d_dfss/core_hardware.h | 71 - .../em11d_dfss/{ => include}/apexextensions.h | 0 .../configs/em11d_dfss/include/board_emsdp.h | 148 + .../configs/em11d_dfss/include/core_config.h | 300 + .../em11d_dfss/{ => include}/dsp_config.h | 0 .../em11d_dfss/{ => include}/io_config.h | 0 .../em11d_dfss.tcf => tool_config/arc.tcf} | 0 .../rev2/configs/em6_scss/apexextensions.h | 1621 ------ .../rev2/configs/em6_scss/core_hardware.h | 71 - .../emsdp/rev2/configs/em6_scss/dsp_config.h | 27 - board/emsdp/rev2/configs/em6_scss/io_config.h | 116 - .../rev2/configs/em6_scss/tcf/em6_scss.tcf | 4940 ----------------- .../configs/em7d_esp_dfss/apexextensions.h | 1544 ------ .../configs/em7d_esp_dfss/core_hardware.h | 71 - .../rev2/configs/em7d_esp_dfss/dsp_config.h | 15 - .../rev2/configs/em7d_esp_dfss/io_config.h | 121 - .../em7d_esp_dfss/tcf/em7d_esp_dfss.tcf | 4868 ---------------- board/emsdp/rev2/configs/emsdp_hardware.h | 46 +- 20 files changed, 470 insertions(+), 13499 deletions(-) delete mode 100644 board/emsdp/rev2/configs/em11d_dfss/core_hardware.h rename board/emsdp/rev2/configs/em11d_dfss/{ => include}/apexextensions.h (100%) create mode 100644 board/emsdp/rev2/configs/em11d_dfss/include/board_emsdp.h create mode 100644 board/emsdp/rev2/configs/em11d_dfss/include/core_config.h rename board/emsdp/rev2/configs/em11d_dfss/{ => include}/dsp_config.h (100%) rename board/emsdp/rev2/configs/em11d_dfss/{ => include}/io_config.h (100%) rename board/emsdp/rev2/configs/em11d_dfss/{tcf/em11d_dfss.tcf => tool_config/arc.tcf} (100%) delete mode 100644 board/emsdp/rev2/configs/em6_scss/apexextensions.h delete mode 100644 board/emsdp/rev2/configs/em6_scss/core_hardware.h delete mode 100644 board/emsdp/rev2/configs/em6_scss/dsp_config.h delete mode 100644 board/emsdp/rev2/configs/em6_scss/io_config.h delete mode 100644 board/emsdp/rev2/configs/em6_scss/tcf/em6_scss.tcf delete mode 100644 board/emsdp/rev2/configs/em7d_esp_dfss/apexextensions.h delete mode 100644 board/emsdp/rev2/configs/em7d_esp_dfss/core_hardware.h delete mode 100644 board/emsdp/rev2/configs/em7d_esp_dfss/dsp_config.h delete mode 100644 board/emsdp/rev2/configs/em7d_esp_dfss/io_config.h delete mode 100644 board/emsdp/rev2/configs/em7d_esp_dfss/tcf/em7d_esp_dfss.tcf diff --git a/board/emsdp/emsdp.mk b/board/emsdp/emsdp.mk index 65140857b..6726754a3 100644 --- a/board/emsdp/emsdp.mk +++ b/board/emsdp/emsdp.mk @@ -101,7 +101,9 @@ BOARD_EMSDP_CSRCDIR += $(BOARD_EMSDP_DIR)/drivers/pmwifi endif BOARD_EMSDP_ASMSRCDIR += $(BOARD_EMSDP_DEV_ASMSRCDIR) $(BOARD_CORE_DIR) -BOARD_EMSDP_INCDIR += $(BOARD_EMSDP_DEV_INCDIR) $(BOARD_CORE_DIR) $(BOARD_EMSDP_DIR)/$(VALID_BD_VER)/configs +BOARD_EMSDP_INCDIR += $(BOARD_EMSDP_DEV_INCDIR) \ + $(BOARD_EMSDP_DIR)/$(VALID_BD_VER)/configs \ + $(BOARD_CORE_DIR)/include # find all the source files in the target directories diff --git a/board/emsdp/rev2/configs/core_configs.mk b/board/emsdp/rev2/configs/core_configs.mk index f3762250a..a5c5d30c7 100644 --- a/board/emsdp/rev2/configs/core_configs.mk +++ b/board/emsdp/rev2/configs/core_configs.mk @@ -1,6 +1,6 @@ ## Current Supported Core Configurations -CORE_DIRS = $(sort $(dir $(wildcard $(BOARD_EMSDP_DIR)/$(VALID_BD_VER)/configs/*/core_hardware.h))) -SUPPORTED_CORES := $(patsubst $(BOARD_EMSDP_DIR)/$(VALID_BD_VER)/configs/%/, %,$(CORE_DIRS)) +CORE_DIRS = $(sort $(dir $(wildcard $(BOARD_EMSDP_DIR)/$(VALID_BD_VER)/configs/*/tool_config/arc.tcf))) +SUPPORTED_CORES := $(patsubst $(BOARD_EMSDP_DIR)/$(VALID_BD_VER)/configs/%/tool_config/, %,$(CORE_DIRS)) CUR_CORE ?= $(firstword $(SUPPORTED_CORES)) @@ -28,7 +28,7 @@ ONCHIP_IP_LIST ?= . designware/spi designware/uart designware/gpio \ ## Check TCF file existence ifneq ($(TCFFILE_IS_VALID),1) -TCF ?= $(wildcard $(BOARD_CORE_DIR)/*/*.tcf) +TCF ?= $(BOARD_CORE_DIR)/tool_config/arc.tcf endif ## If CUR_CORE is not in SUPPORT_CORES list, then force CUR_CORE and VALID_CUR_CORE to be TCF filename diff --git a/board/emsdp/rev2/configs/em11d_dfss/core_hardware.h b/board/emsdp/rev2/configs/em11d_dfss/core_hardware.h deleted file mode 100644 index 7922af9a5..000000000 --- a/board/emsdp/rev2/configs/em11d_dfss/core_hardware.h +++ /dev/null @@ -1,71 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------- */ -#ifndef _CORE_HARDWARE_H_ -#define _CORE_HARDWARE_H_ - -#define EMSDP_SPI0_INTR (83) -#define EMSDP_SPI1_INTR (84) -#define EMSDP_GPIO_INTR0 (85) -#define EMSDP_GPIO_INTR1 (86) -#define EMSDP_GPIO_INTR2 (87) -#define EMSDP_GPIO_INTR3 (88) -#define EMSDP_TIMER0_INTR0 (89) -#define EMSDP_TIMER0_INTR1 (90) -#define EMSDP_TIMER0_INTR2 (91) -#define EMSDP_TIMER0_INTR3 (92) -#define EMSDP_TIMER0_INTR4 (93) -#define EMSDP_TIMER0_INTR5 (94) -#define EMSDP_TIMER0_INTR6 (95) -#define EMSDP_TIMER0_INTR7 (96) -#define EMSDP_TIMER1_INTR0 (97) -#define EMSDP_TIMER1_INTR1 (98) -#define EMSDP_TIMER1_INTR2 (99) -#define EMSDP_TIMER1_INTR3 (100) -#define EMSDP_TIMER1_INTR4 (101) -#define EMSDP_TIMER1_INTR5 (102) -#define EMSDP_TIMER1_INTR6 (103) -#define EMSDP_TIMER1_INTR7 (104) -#define EMSDP_UART_INTR (105) -#define EMSDP_WDT_INTR (106) -#define EMSDP_DBG_UART_INTR (107) -#define EMSDP_SDIO_INTR (108) -#define EMSDP_REDPINE_SPI_INTR (109) -#define EMSDP_REDPINE_HOST_WAKEUP (110) -#define EMSDP_NIST_TRNG_INTR (111) - -//EMSDP Peripheral Subsystem DMA assignments -#define UART_DMA_TX (9) -#define UART_DMA_RX (10) -#define REDPINE_SPI_DMA_TX (11) -#define REDPINE_SPI_DMA_RX (12) -#define FLASH_SPI_DMA_TX (13) -#define FLASH_SPI_DMA_RX (14) - -#endif //_CORE_HARDWARE_H_ diff --git a/board/emsdp/rev2/configs/em11d_dfss/apexextensions.h b/board/emsdp/rev2/configs/em11d_dfss/include/apexextensions.h similarity index 100% rename from board/emsdp/rev2/configs/em11d_dfss/apexextensions.h rename to board/emsdp/rev2/configs/em11d_dfss/include/apexextensions.h diff --git a/board/emsdp/rev2/configs/em11d_dfss/include/board_emsdp.h b/board/emsdp/rev2/configs/em11d_dfss/include/board_emsdp.h new file mode 100644 index 000000000..54db57629 --- /dev/null +++ b/board/emsdp/rev2/configs/em11d_dfss/include/board_emsdp.h @@ -0,0 +1,148 @@ +/* ------------------------------------------ + * Copyright (c) 2018, Synopsys, Inc. All rights reserved. + + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + + * 1) Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + + * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +--------------------------------------------- */ +#ifndef __BOARD_EMSDP_H__ +#define __BOARD_EMSDP_H__ + +/** + * Clock + */ +#define EMSDP_REF_CLOCK (100000000) + +#define EMSDP_UART_REF_CLOCK (100000000) +#define EMSDP_AUDIO_REF_CLOCK (24576000) + +#if (defined(FAST_UART) ) + #define EMSDP_UART_BAUDRATE (6250000) +#else + #define EMSDP_UART_BAUDRATE (115200) +#endif + +#define EMSDP_I2C_CLOCK (EMSDP_REF_CLOCK) + +//APB Peripheral address map +#define EMSDP_CRU_BASE (0xF0000000U) +#define EMSDP_CREG_BASE (0xF0001000U) +#define EMSDP_GPIO_BASE (0xF0002000U) +#define EMSDP_TRNG_BASE (0xF0003000U) +#define EMSDP_DBG_UART_BASE (0xF0004000U) +#define EMSDP_WDT_BASE (0xF0005000U) +#define EMSDP_TIMERS0_BASE (0xF0006000U) +#define EMSDP_TIMERS1_BASE (0xF0007000U) +#define EMSDP_SPI_BASE (0xF0008000U) +#define EMSDP_UART_BASE (0xF0009000U) +#define EMSDP_SDIO_BASE (0xF0010000U) +#define EMSDP_FLASH_BASE (0xF1000000U) +#define EMSDP_EBI_BASE (0xF2000000U) +#define EMSDP_PSRAM_BASE (0xF2001000U) +/** +* Mapping of printf information +*/ +#define DBG_init dbg_init +#define DBG_print dbg_printf +#define DBG_getChar(x) \ +{ \ + DW_UART_STRUCT_PTR uart = (DW_UART_STRUCT_PTR) (DBG_PORT); \ + x = dw_uart_getChar(uart); \ +} +#define DBG_finish() +#define DBG_finish_with_error() +#define DBG_install(x) \ +{ \ + DW_UART_STRUCT_PTR uart = (DW_UART_STRUCT_PTR) (DBG_PORT); \ + uart->IER.DATA32 = DW_UART_IER_DATA_AVAIL; \ + board_installHandler(x, DBG_ISR); \ +} + + +//ARC Exceptions +#define EMSDP_RESET_EXCP (0) +#define EMSDP_MEMORY_ERROR_EXCP (1) +#define EMSDP_INSTRUCTION_ERROR_EXCP (2) +#define EMSDP_EVMACHINECHECK_EXCP (3) +#define EMSDP_EVITLBMISS_EXCP (4) +#define EMSDP_EVDTLBMISS_EXCP (5) +#define EMSDP_EVPROTV_EXCP (6) +#define EMSDP_EVPRIVILEGEV_EXCP (7) +#define EMSDP_EVSWI_EXCP (8) +#define EMSDP_EVTRAP_EXCP (9) +#define EMSDP_EVEXTENSION_EXCP (10) +#define EMSDP_EVDIVZERO_EXCP (11) +#define EMSDP_EVDCERROR_EXCP (12) +#define EMSDP_EVMALIGNED_EXCP (13) + +//ARC External private interrupts (low interrupts) +#define EMSDP_TIMER0_EXCP (16) +#define EMSDP_TIMER1_EXCP (17) + +#define EMSDP_MAX_NUM_EXCP (24) +#define EMSDP_MAX_NUM_ISR (80) + + +//EMSDP Peripheral Subsystem Interrupt assignments +#define EMSDP_SPI0_INTR (83) +#define EMSDP_SPI1_INTR (84) +#define EMSDP_GPIO_INTR0 (85) +#define EMSDP_GPIO_INTR1 (86) +#define EMSDP_GPIO_INTR2 (87) +#define EMSDP_GPIO_INTR3 (88) +#define EMSDP_TIMER0_INTR0 (89) +#define EMSDP_TIMER0_INTR1 (90) +#define EMSDP_TIMER0_INTR2 (91) +#define EMSDP_TIMER0_INTR3 (92) +#define EMSDP_TIMER0_INTR4 (93) +#define EMSDP_TIMER0_INTR5 (94) +#define EMSDP_TIMER0_INTR6 (95) +#define EMSDP_TIMER0_INTR7 (96) +#define EMSDP_TIMER1_INTR0 (97) +#define EMSDP_TIMER1_INTR1 (98) +#define EMSDP_TIMER1_INTR2 (99) +#define EMSDP_TIMER1_INTR3 (100) +#define EMSDP_TIMER1_INTR4 (101) +#define EMSDP_TIMER1_INTR5 (102) +#define EMSDP_TIMER1_INTR6 (103) +#define EMSDP_TIMER1_INTR7 (104) +#define EMSDP_UART_INTR (105) +#define EMSDP_WDT_INTR (106) +#define EMSDP_DBG_UART_INTR (107) +#define EMSDP_SDIO_INTR (108) +#define EMSDP_REDPINE_SPI_INTR (109) +#define EMSDP_REDPINE_HOST_WAKEUP (110) +#define EMSDP_NIST_TRNG_INTR (111) + + +//EMSDP Peripheral Subsystem DMA assignments +#define UART_DMA_TX (9) +#define UART_DMA_RX (10) +#define REDPINE_SPI_DMA_TX (11) +#define REDPINE_SPI_DMA_RX (12) +#define FLASH_SPI_DMA_TX (13) +#define FLASH_SPI_DMA_RX (14) + +#endif //__BOARD_EMSDP_H__ diff --git a/board/emsdp/rev2/configs/em11d_dfss/include/core_config.h b/board/emsdp/rev2/configs/em11d_dfss/include/core_config.h new file mode 100644 index 000000000..582f65a03 --- /dev/null +++ b/board/emsdp/rev2/configs/em11d_dfss/include/core_config.h @@ -0,0 +1,300 @@ +#ifndef __core_config_h + #define __core_config_h 1 + #define _TOOL_CONFIG_VER 10072 + #define core_config_cir_identity 0x00000044 + #define core_config_cir_identity_chipid 0 + #define core_config_cir_identity_arcnum 0 + #define core_config_cir_identity_arcver 68 + #define core_config_cir_identity_family 4 + #define core_config_cir_identity_corever 4 + #define core_config_cir_aux_dccm 0x80000000 + #define core_config_bcr_bcr_ver 0x00000002 + #define core_config_bcr_bcr_ver_version 2 + #define core_config_bcr_vecbase_ac_build 0x00000010 + #define core_config_bcr_vecbase_ac_build_version 4 + #define core_config_bcr_vecbase_ac_build_vector_config 0 + #define core_config_bcr_vecbase_ac_build_addr 0 + #define core_config_bcr_mpu_build 0x00001002 + #define core_config_bcr_mpu_build_i 0 + #define core_config_bcr_mpu_build_s 0 + #define core_config_bcr_mpu_build_regions 16 + #define core_config_bcr_mpu_build_version 2 + #define core_config_bcr_rf_build 0x0000c902 + #define core_config_bcr_rf_build_version 2 + #define core_config_bcr_rf_build_p 1 + #define core_config_bcr_rf_build_e 0 + #define core_config_bcr_rf_build_r 0 + #define core_config_bcr_rf_build_b 1 + #define core_config_bcr_rf_build_d 3 + #define core_config_bcr_d_cache_build 0x00215104 + #define core_config_bcr_d_cache_build_version 4 + #define core_config_bcr_d_cache_build_assoc 1 + #define core_config_bcr_d_cache_build_capacity 5 + #define core_config_bcr_d_cache_build_bsize 1 + #define core_config_bcr_d_cache_build_fl 2 + #define core_config_bcr_d_cache_build_ioc 0 + #define core_config_bcr_d_cache_build_cp 0 + #define core_config_bcr_d_cache_build_u 0 + #define core_config_bcr_d_cache_build_cycles 0 + #define core_config_bcr_dccm_build 0x00000904 + #define core_config_bcr_dccm_build_w 0 + #define core_config_bcr_dccm_build_cycles 0 + #define core_config_bcr_dccm_build_interleave 0 + #define core_config_bcr_dccm_build_size1 0 + #define core_config_bcr_dccm_build_size0 9 + #define core_config_bcr_dccm_build_version 4 + #define core_config_bcr_timer_build 0x00010504 + #define core_config_bcr_timer_build_sp1 0 + #define core_config_bcr_timer_build_sp0 0 + #define core_config_bcr_timer_build_p1 0 + #define core_config_bcr_timer_build_p0 1 + #define core_config_bcr_timer_build_st1 0 + #define core_config_bcr_timer_build_st0 0 + #define core_config_bcr_timer_build_rtc 1 + #define core_config_bcr_timer_build_rtsc_ver 1 + #define core_config_bcr_timer_build_rtsc 0 + #define core_config_bcr_timer_build_t0 1 + #define core_config_bcr_timer_build_t1 0 + #define core_config_bcr_timer_build_version 4 + #define core_config_bcr_ap_build 0x00000605 + #define core_config_bcr_ap_build_version 5 + #define core_config_bcr_ap_build_type 6 + #define core_config_bcr_i_cache_build 0x00135104 + #define core_config_bcr_i_cache_build_assoc 1 + #define core_config_bcr_i_cache_build_version 4 + #define core_config_bcr_i_cache_build_capacity 5 + #define core_config_bcr_i_cache_build_bsize 3 + #define core_config_bcr_i_cache_build_fl 1 + #define core_config_bcr_i_cache_build_d 0 + #define core_config_bcr_iccm_build 0x00000904 + #define core_config_bcr_iccm_build_w0 0 + #define core_config_bcr_iccm_build_iccm1_size1 0 + #define core_config_bcr_iccm_build_iccm0_size1 0 + #define core_config_bcr_iccm_build_iccm1_size0 0 + #define core_config_bcr_iccm_build_iccm0_size0 9 + #define core_config_bcr_iccm_build_version 4 + #define core_config_bcr_xy_build 0x00002220 + #define core_config_bcr_xy_build_memsize 2 + #define core_config_bcr_xy_build_interleaved 0 + #define core_config_bcr_xy_build_config 2 + #define core_config_bcr_xy_build_version 32 + #define core_config_bcr_dsp_build 0x00003521 + #define core_config_bcr_dsp_build_wide 0 + #define core_config_bcr_dsp_build_itu_pa 1 + #define core_config_bcr_dsp_build_acc_shift 2 + #define core_config_bcr_dsp_build_comp 1 + #define core_config_bcr_dsp_build_divsqrt 1 + #define core_config_bcr_dsp_build_version 33 + #define core_config_bcr_multiply_build 0x00022206 + #define core_config_bcr_multiply_build_version16x16 2 + #define core_config_bcr_multiply_build_dsp 2 + #define core_config_bcr_multiply_build_cyc 0 + #define core_config_bcr_multiply_build_type 2 + #define core_config_bcr_multiply_build_version32x32 6 + #define core_config_bcr_swap_build 0x00000003 + #define core_config_bcr_swap_build_version 3 + #define core_config_bcr_norm_build 0x00000003 + #define core_config_bcr_norm_build_version 3 + #define core_config_bcr_minmax_build 0x00000002 + #define core_config_bcr_minmax_build_version 2 + #define core_config_bcr_barrel_build 0x00000303 + #define core_config_bcr_barrel_build_version 3 + #define core_config_bcr_barrel_build_shift_option 3 + #define core_config_bcr_isa_config 0x12447402 + #define core_config_bcr_isa_config_res1 0 + #define core_config_bcr_isa_config_d 1 + #define core_config_bcr_isa_config_res2 0 + #define core_config_bcr_isa_config_f 0 + #define core_config_bcr_isa_config_c 2 + #define core_config_bcr_isa_config_l 0 + #define core_config_bcr_isa_config_n 1 + #define core_config_bcr_isa_config_a 0 + #define core_config_bcr_isa_config_b 0 + #define core_config_bcr_isa_config_addr_size 4 + #define core_config_bcr_isa_config_lpc_size 7 + #define core_config_bcr_isa_config_pc_size 4 + #define core_config_bcr_isa_config_version 2 + #define core_config_bcr_dmp_pp_build 0xf0000012 + #define core_config_bcr_stack_region_build 0x00000002 + #define core_config_bcr_erp_build 0x50000004 + #define core_config_bcr_erp_build_l 0 + #define core_config_bcr_erp_build_wd 2 + #define core_config_bcr_erp_build_c 1 + #define core_config_bcr_erp_build_mmu 0 + #define core_config_bcr_erp_build_rf 0 + #define core_config_bcr_erp_build_pc 0 + #define core_config_bcr_erp_build_ic 0 + #define core_config_bcr_erp_build_dc 0 + #define core_config_bcr_erp_build_ip 0 + #define core_config_bcr_erp_build_dp 0 + #define core_config_bcr_erp_build_version 4 + #define core_config_bcr_fpu_build 0x01004f03 + #define core_config_bcr_fpu_build_da 1 + #define core_config_bcr_fpu_build_dd 0 + #define core_config_bcr_fpu_build_dc 0 + #define core_config_bcr_fpu_build_df 0 + #define core_config_bcr_fpu_build_dp 0 + #define core_config_bcr_fpu_build_fd_v1 2 + #define core_config_bcr_fpu_build_pi 1 + #define core_config_bcr_fpu_build_fd 0 + #define core_config_bcr_fpu_build_fm 0 + #define core_config_bcr_fpu_build_sd 1 + #define core_config_bcr_fpu_build_sc 1 + #define core_config_bcr_fpu_build_sf 1 + #define core_config_bcr_fpu_build_sp 1 + #define core_config_bcr_fpu_build_version 3 + #define core_config_bcr_bs_build 0x00000002 + #define core_config_bcr_bs_build_version 2 + #define core_config_bcr_agu_build 0x01988c02 + #define core_config_bcr_agu_build_accordian 1 + #define core_config_bcr_agu_build_wb_size 4 + #define core_config_bcr_agu_build_num_modifier 24 + #define core_config_bcr_agu_build_num_offset 8 + #define core_config_bcr_agu_build_num_addr 12 + #define core_config_bcr_agu_build_version 2 + #define core_config_bcr_dmac_build 0x00120f02 + #define core_config_bcr_dmac_build_int_cfg 2 + #define core_config_bcr_dmac_build_fifo 1 + #define core_config_bcr_dmac_build_chan_mem 0 + #define core_config_bcr_dmac_build_channels 15 + #define core_config_bcr_dmac_build_version 2 + #define core_config_bcr_subsys_build 0x00101063 + #define core_config_bcr_subsys_build_version_major 0 + #define core_config_bcr_subsys_build_version_minor 2 + #define core_config_bcr_subsys_build_version_build 6 + #define core_config_bcr_subsys_build_type 3 + #define core_config_bcr_core_config 0x00000001 + #define core_config_bcr_core_config_turbo_boost 0 + #define core_config_bcr_core_config_version 1 + #define core_config_bcr_rtt_build 0x00000503 + #define core_config_bcr_rtt_build_prod_src_num 0 + #define core_config_bcr_rtt_build_fl 2 + #define core_config_bcr_rtt_build_pi 1 + #define core_config_bcr_rtt_build_version 3 + #define core_config_bcr_irq_build 0x134d6001 + #define core_config_bcr_irq_build_raz 0 + #define core_config_bcr_irq_build_nmi 0 + #define core_config_bcr_irq_build_f 1 + #define core_config_bcr_irq_build_p 3 + #define core_config_bcr_irq_build_exts 77 + #define core_config_bcr_irq_build_irqs 96 + #define core_config_bcr_irq_build_version 1 + #define core_config_bcr_pct_build 0x08080104 + #define core_config_bcr_pct_build_version 4 + #define core_config_bcr_pct_build_s 1 + #define core_config_bcr_pct_build_i 0 + #define core_config_bcr_pct_build_c 8 + #define core_config_bcr_cc_build 0x006f0004 + #define core_config_bcr_cc_build_version 4 + #define core_config_bcr_cc_build_cc 111 + #define core_config_bcr_smart_build 0x00002003 + #define core_config_bcr_smart_build_version 3 + #define core_config_bcr_smart_build_stack_size 8 + #define core_config_cir_aux_iccm 0x60000000 + #define core_config_cir_xccm_base 0x90000000 + #define core_config_cir_yccm_base 0xa0000000 + #define core_config_cir_subsys_dsp_0_build 0x00001000 + #define core_config_cir_subsys_io_0_build 0x171700f0 + #define core_config_cir_subsys_io_1_build 0x00000007 + #define core_config_cir_subsys_io_2_build 0x00000111 + #define core_config_cir_subsys_uaux_offset 0x00100000 + #define core_config_cir_subsys_apex_offset 0x80000000 + #define core_config_family 4 + #define core_config_core_version 4 + #define core_config_family_name "arcv2em" + #define core_config_rgf_num_banks 2 + #define core_config_rgf_banked_regs 32 + #define core_config_rgf_num_wr_ports 2 + #define core_config_endian "little" + #define core_config_endian_little 1 + #define core_config_endian_big 0 + #define core_config_lpc_size 32 + #define core_config_pc_size 32 + #define core_config_addr_size 32 + #define core_config_unaligned 1 + #define core_config_code_density 1 + #define core_config_div_rem "radix2" + #define core_config_div_rem_radix2 1 + #define core_config_swap 1 + #define core_config_bitscan 1 + #define core_config_mpy_option "mpyd" + #define core_config_mpy_option_num 8 + #define core_config_shift_assist 1 + #define core_config_barrel_shifter 1 + #define core_config_dsp 1 + #define core_config_dsp2 1 + #define core_config_dsp_complex 1 + #define core_config_dsp_divsqrt "radix2" + #define core_config_dsp_divsqrt_radix2 1 + #define core_config_dsp_itu 1 + #define core_config_dsp_accshift "full" + #define core_config_dsp_accshift_full 1 + #define core_config_agu_large 1 + #define core_config_agu_wb_depth 4 + #define core_config_agu_accord 1 + #define core_config_xy 1 + #define core_config_xy_config "dccm_x_y" + #define core_config_xy_config_dccm_x_y 1 + #define core_config_xy_size 16384 + #define core_config_xy_size_KM "16K" + #define core_config_xy_x_base 0x90000000 + #define core_config_xy_y_base 0xa0000000 + #define core_config_bitstream 1 + #define core_config_fpus_div 1 + #define core_config_fpu_mac 1 + #define core_config_fpuda 1 + #define core_config_fpus_mpy_slow 1 + #define core_config_fpus_div_slow 1 + #define core_config_fpu_pipe_impl 1 + #define core_config_timer0 1 + #define core_config_timer0_level 1 + #define core_config_timer0_vector 16 + #define core_config_rtc 1 + #define core_config_action_points 8 + #define core_config_stack_check 1 + #define core_config_smart_stack_entries 8 + #define core_config_mpu_present 1 + #define core_config_mpu 1 + #define core_config_mpu_regions 16 + #define core_config_interrupts_present 1 + #define core_config_interrupts_number 96 + #define core_config_interrupts_priorities 4 + #define core_config_interrupts_externals 77 + #define core_config_interrupts 96 + #define core_config_interrupt_priorities 4 + #define core_config_ext_interrupts 77 + #define core_config_interrupts_firq 1 + #define core_config_interrupts_base 0x0 + #define core_config_dcache_present 1 + #define core_config_dcache_size 16384 + #define core_config_dcache_line_size 32 + #define core_config_dcache_ways 2 + #define core_config_dcache_feature 2 + #define core_config_icache_present 1 + #define core_config_icache_size 16384 + #define core_config_icache_line_size 64 + #define core_config_icache_ways 2 + #define core_config_icache_feature 1 + #define core_config_dccm_present 1 + #define core_config_dccm_size 0x20000 + #define core_config_dccm_base 0x80000000 + #define core_config_iccm_present 1 + #define core_config_iccm0_present 1 + #define core_config_iccm_size 0x20000 + #define core_config_iccm0_size 0x20000 + #define core_config_iccm_base 0x60000000 + #define core_config_iccm0_base 0x60000000 + #define core_config_error_prot_ver 4 + #define core_config_ccm_prot_pipelined 1 + #define core_config_watchdog 1 + #define core_config_watchdog_size 32 + #define core_config_pct_counters 8 + #define core_config_dmac 1 + #define core_config_dmac_channels 16 + #define core_config_dmac_registers 0 + #define core_config_dmac_fifo_depth 2 + #define core_config_dmac_int_config "multiple_internal" + #define core_config_clock_speed 10 +#endif /* __core_config_h */ + + diff --git a/board/emsdp/rev2/configs/em11d_dfss/dsp_config.h b/board/emsdp/rev2/configs/em11d_dfss/include/dsp_config.h similarity index 100% rename from board/emsdp/rev2/configs/em11d_dfss/dsp_config.h rename to board/emsdp/rev2/configs/em11d_dfss/include/dsp_config.h diff --git a/board/emsdp/rev2/configs/em11d_dfss/io_config.h b/board/emsdp/rev2/configs/em11d_dfss/include/io_config.h similarity index 100% rename from board/emsdp/rev2/configs/em11d_dfss/io_config.h rename to board/emsdp/rev2/configs/em11d_dfss/include/io_config.h diff --git a/board/emsdp/rev2/configs/em11d_dfss/tcf/em11d_dfss.tcf b/board/emsdp/rev2/configs/em11d_dfss/tool_config/arc.tcf similarity index 100% rename from board/emsdp/rev2/configs/em11d_dfss/tcf/em11d_dfss.tcf rename to board/emsdp/rev2/configs/em11d_dfss/tool_config/arc.tcf diff --git a/board/emsdp/rev2/configs/em6_scss/apexextensions.h b/board/emsdp/rev2/configs/em6_scss/apexextensions.h deleted file mode 100644 index d9104c5e0..000000000 --- a/board/emsdp/rev2/configs/em6_scss/apexextensions.h +++ /dev/null @@ -1,1621 +0,0 @@ - -/* **** DO NOT EDIT - this file is generated by ARChitect2 **** - * - * Description: Header file declaring the compiler extensions for apex components - */ - -#ifndef _apexextensions_H_ -#define _apexextensions_H_ - -// User extension instruction - dsp_abs_1d -extern long dsp_abs_1d(long); -#pragma intrinsic(dsp_abs_1d, opcode => 0x07, sub_opcode => 0x00 ) - -// User extension instruction - dsp_add_1d -extern long dsp_add_1d(long, long); -#pragma intrinsic(dsp_add_1d, opcode => 0x07, sub_opcode => 0x03 ) - -// User extension instruction - dsp_negate_1d -extern long dsp_negate_1d(long); -#pragma intrinsic(dsp_negate_1d, opcode => 0x07, sub_opcode => 0x0F ) - -// User extension instruction - dsp_shift_1d -extern long dsp_shift_1d(long, long); -#pragma intrinsic(dsp_shift_1d, opcode => 0x07, sub_opcode => 0x18 ) - -// User extension instruction - dsp_cos -extern long dsp_cos(long); -#pragma intrinsic(dsp_cos, opcode => 0x07, sub_opcode => 0x1E , latency_cycles => 8) - -// User extension instruction - dsp_sqrt -extern long dsp_sqrt(long); -#pragma intrinsic(dsp_sqrt, opcode => 0x07, sub_opcode => 0x20 , latency_cycles => 31) - -// User extension instruction - dsp_sub_1d -extern long dsp_sub_1d(long, long); -#pragma intrinsic(dsp_sub_1d, opcode => 0x07, sub_opcode => 0x06 ) - -// User extension instruction - dsp_abs_2d -extern long dsp_abs_2d(long); -#pragma intrinsic(dsp_abs_2d, opcode => 0x07, sub_opcode => 0x01 ) - -// User extension instruction - dsp_add_2d -extern long dsp_add_2d(long, long); -#pragma intrinsic(dsp_add_2d, opcode => 0x07, sub_opcode => 0x04 ) - -// User extension instruction - dsp_mulv_2d -extern long dsp_mulv_2d(long, long); -#pragma intrinsic(dsp_mulv_2d, opcode => 0x07, sub_opcode => 0x1E ) - -// User extension instruction - dsp_negate_2d -extern long dsp_negate_2d(long); -#pragma intrinsic(dsp_negate_2d, opcode => 0x07, sub_opcode => 0x10 ) - -// User extension instruction - dsp_shift_2d -extern long dsp_shift_2d(long, long); -#pragma intrinsic(dsp_shift_2d, opcode => 0x07, sub_opcode => 0x19 ) - -// User extension instruction - dsp_sin -extern long dsp_sin(long); -#pragma intrinsic(dsp_sin, opcode => 0x07, sub_opcode => 0x1F , latency_cycles => 8) - -// User extension instruction - dsp_sqrt15 -extern long dsp_sqrt15(long); -#pragma intrinsic(dsp_sqrt15, opcode => 0x07, sub_opcode => 0x21 , latency_cycles => 15) - -// User extension instruction - dsp_sub_2d -extern long dsp_sub_2d(long, long); -#pragma intrinsic(dsp_sub_2d, opcode => 0x07, sub_opcode => 0x07 ) - -// User extension instruction - dsp_abs_4d -extern long dsp_abs_4d(long); -#pragma intrinsic(dsp_abs_4d, opcode => 0x07, sub_opcode => 0x02 ) - -// User extension instruction - dsp_add_4d -extern long dsp_add_4d(long, long); -#pragma intrinsic(dsp_add_4d, opcode => 0x07, sub_opcode => 0x05 ) - -// User extension instruction - dsp_mulv_4d -extern long dsp_mulv_4d(long, long); -#pragma intrinsic(dsp_mulv_4d, opcode => 0x07, sub_opcode => 0x1F ) - -// User extension instruction - dsp_negate_4d -extern long dsp_negate_4d(long); -#pragma intrinsic(dsp_negate_4d, opcode => 0x07, sub_opcode => 0x11 ) - -// User extension instruction - dsp_shift_4d -extern long dsp_shift_4d(long, long); -#pragma intrinsic(dsp_shift_4d, opcode => 0x07, sub_opcode => 0x1A ) - -// User extension instruction - dsp_sub_4d -extern long dsp_sub_4d(long, long); -#pragma intrinsic(dsp_sub_4d, opcode => 0x07, sub_opcode => 0x08 ) - -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_ABS_PRESENT 1 -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_ACM_PRESENT 1 - -// User extension core register dsp_acm_msbout -#define CR_DSP_ACM_MSBOUT 54 -#pragma Core_register(54, name=>"dsp_acm_msbout", non_interlock_cycles=>"2", side_effects=>"rw") - -// User extension core register dsp_acm_lsbout -#define CR_DSP_ACM_LSBOUT 53 -#pragma Core_register(53, name=>"dsp_acm_lsbout", non_interlock_cycles=>"2", side_effects=>"rw") - -// User extension instruction dsp_acm -extern int dsp_acm(int,int); -#pragma intrinsic(dsp_acm,opcode=>7,sub_opcode=>29, effects=>"dsp_acm_lsbout:is_read:is_written:is_read_cycle=0:is_written_cycle=0; dsp_acm_msbout:is_read:is_written:is_read_cycle=0:is_written_cycle=0") -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_ADD_PRESENT 1 -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_MAC_PRESENT 1 - -// User extension core register dsp_mac_lsbout -#define CR_DSP_MAC_LSBOUT 56 -#pragma Core_register(56, name=>"dsp_mac_lsbout", non_interlock_cycles=>"2", side_effects=>"rw") - -// User extension core register dsp_mac_msbout -#define CR_DSP_MAC_MSBOUT 57 -#pragma Core_register(57, name=>"dsp_mac_msbout", non_interlock_cycles=>"2", side_effects=>"rw") - -// User extension instruction dsp_mac -extern int dsp_mac(int,int); -#pragma intrinsic(dsp_mac,opcode=>7,sub_opcode=>27, effects=>"dsp_mac_lsbout:is_read:is_written:is_read_cycle=0:is_written_cycle=0; dsp_mac_msbout:is_read:is_written:is_read_cycle=0:is_written_cycle=0") - -// User extension instruction dsp_mult -extern int dsp_mult(int,int); -#pragma intrinsic(dsp_mult,opcode=>7,sub_opcode=>28, effects=>"dsp_mac_lsbout:is_read:is_written:is_read_cycle=0:is_written_cycle=0; dsp_mac_msbout:is_read:is_written:is_read_cycle=0:is_written_cycle=0") -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_MULT_PRESENT 1 - -// User extension core register dsp_mult -#define CR_DSP_MULT 55 -#pragma Core_register(55, name=>"dsp_mult", non_interlock_cycles=>"2") - -// User extension instruction dsp_mult_2d -extern int dsp_mult_2d(int,int); -#pragma intrinsic(dsp_mult_2d,opcode=>7,sub_opcode=>13, effects=>"dsp_mult:is_written:is_read_cycle=0:is_written_cycle=0") - -// User extension instruction dsp_mult_4d -extern int dsp_mult_4d(int,int); -#pragma intrinsic(dsp_mult_4d,opcode=>7,sub_opcode=>14, effects=>"dsp_mult:is_written:is_read_cycle=0:is_written_cycle=0") -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_MULV_PRESENT 1 -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_NEGATE_PRESENT 1 -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_SHIFT_PRESENT 1 -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_SINCOS_PRESENT 1 -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_SQRT_PRESENT 1 -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_SUB_PRESENT 1 -#define APEX_COM_ARC_HARDWARE_SCSS_IO_GPIO0_PRESENT 1 - -// User extension aux register io_gpio0_debounce -#define AR_IO_GPIO0_DEBOUNCE 0x80017048 -#pragma Aux_register(0x80017048, name=>"io_gpio0_debounce") - -// User extension aux register io_gpio0_clken -#define AR_IO_GPIO0_CLKEN 0x80017080 -#pragma Aux_register(0x80017080, name=>"io_gpio0_clken") - -// User extension aux register io_gpio0_swporta_dr -#define AR_IO_GPIO0_SWPORTA_DR 0x80017000 -#pragma Aux_register(0x80017000, name=>"io_gpio0_swporta_dr") - -// User extension aux register io_gpio0_swporta_ddr -#define AR_IO_GPIO0_SWPORTA_DDR 0x80017004 -#pragma Aux_register(0x80017004, name=>"io_gpio0_swporta_ddr") - -// User extension aux register io_gpio0_inten -#define AR_IO_GPIO0_INTEN 0x80017030 -#pragma Aux_register(0x80017030, name=>"io_gpio0_inten") - -// User extension aux register io_gpio0_intmask -#define AR_IO_GPIO0_INTMASK 0x80017034 -#pragma Aux_register(0x80017034, name=>"io_gpio0_intmask") - -// User extension aux register io_gpio0_inttype_level -#define AR_IO_GPIO0_INTTYPE_LEVEL 0x80017038 -#pragma Aux_register(0x80017038, name=>"io_gpio0_inttype_level") - -// User extension aux register io_gpio0_int_polarity -#define AR_IO_GPIO0_INT_POLARITY 0x8001703c -#pragma Aux_register(0x8001703c, name=>"io_gpio0_int_polarity") - -// User extension aux register io_gpio0_intstatus -#define AR_IO_GPIO0_INTSTATUS 0x80017040 -#pragma Aux_register(0x80017040, name=>"io_gpio0_intstatus") - -// User extension aux register io_gpio0_raw_intstatus -#define AR_IO_GPIO0_RAW_INTSTATUS 0x80017044 -#pragma Aux_register(0x80017044, name=>"io_gpio0_raw_intstatus") - -// User extension aux register io_gpio0_porta_eoi -#define AR_IO_GPIO0_PORTA_EOI 0x8001704c -#pragma Aux_register(0x8001704c, name=>"io_gpio0_porta_eoi") - -// User extension aux register io_gpio0_ext_porta -#define AR_IO_GPIO0_EXT_PORTA 0x80017050 -#pragma Aux_register(0x80017050, name=>"io_gpio0_ext_porta") - -// User extension aux register io_gpio0_ls_sync -#define AR_IO_GPIO0_LS_SYNC 0x80017060 -#pragma Aux_register(0x80017060, name=>"io_gpio0_ls_sync") - -// User extension aux register io_gpio0_int_bothedge -#define AR_IO_GPIO0_INT_BOTHEDGE 0x80017068 -#pragma Aux_register(0x80017068, name=>"io_gpio0_int_bothedge") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_GPIO1_PRESENT 1 - -// User extension aux register io_gpio1_debounce -#define AR_IO_GPIO1_DEBOUNCE 0x80017148 -#pragma Aux_register(0x80017148, name=>"io_gpio1_debounce") - -// User extension aux register io_gpio1_clken -#define AR_IO_GPIO1_CLKEN 0x80017180 -#pragma Aux_register(0x80017180, name=>"io_gpio1_clken") - -// User extension aux register io_gpio1_swporta_dr -#define AR_IO_GPIO1_SWPORTA_DR 0x80017100 -#pragma Aux_register(0x80017100, name=>"io_gpio1_swporta_dr") - -// User extension aux register io_gpio1_swporta_ddr -#define AR_IO_GPIO1_SWPORTA_DDR 0x80017104 -#pragma Aux_register(0x80017104, name=>"io_gpio1_swporta_ddr") - -// User extension aux register io_gpio1_inten -#define AR_IO_GPIO1_INTEN 0x80017130 -#pragma Aux_register(0x80017130, name=>"io_gpio1_inten") - -// User extension aux register io_gpio1_intmask -#define AR_IO_GPIO1_INTMASK 0x80017134 -#pragma Aux_register(0x80017134, name=>"io_gpio1_intmask") - -// User extension aux register io_gpio1_inttype_level -#define AR_IO_GPIO1_INTTYPE_LEVEL 0x80017138 -#pragma Aux_register(0x80017138, name=>"io_gpio1_inttype_level") - -// User extension aux register io_gpio1_int_polarity -#define AR_IO_GPIO1_INT_POLARITY 0x8001713c -#pragma Aux_register(0x8001713c, name=>"io_gpio1_int_polarity") - -// User extension aux register io_gpio1_intstatus -#define AR_IO_GPIO1_INTSTATUS 0x80017140 -#pragma Aux_register(0x80017140, name=>"io_gpio1_intstatus") - -// User extension aux register io_gpio1_raw_intstatus -#define AR_IO_GPIO1_RAW_INTSTATUS 0x80017144 -#pragma Aux_register(0x80017144, name=>"io_gpio1_raw_intstatus") - -// User extension aux register io_gpio1_porta_eoi -#define AR_IO_GPIO1_PORTA_EOI 0x8001714c -#pragma Aux_register(0x8001714c, name=>"io_gpio1_porta_eoi") - -// User extension aux register io_gpio1_ext_porta -#define AR_IO_GPIO1_EXT_PORTA 0x80017150 -#pragma Aux_register(0x80017150, name=>"io_gpio1_ext_porta") - -// User extension aux register io_gpio1_ls_sync -#define AR_IO_GPIO1_LS_SYNC 0x80017160 -#pragma Aux_register(0x80017160, name=>"io_gpio1_ls_sync") - -// User extension aux register io_gpio1_int_bothedge -#define AR_IO_GPIO1_INT_BOTHEDGE 0x80017168 -#pragma Aux_register(0x80017168, name=>"io_gpio1_int_bothedge") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_GPIO2_PRESENT 1 - -// User extension aux register io_gpio2_debounce -#define AR_IO_GPIO2_DEBOUNCE 0x80017248 -#pragma Aux_register(0x80017248, name=>"io_gpio2_debounce") - -// User extension aux register io_gpio2_clken -#define AR_IO_GPIO2_CLKEN 0x80017280 -#pragma Aux_register(0x80017280, name=>"io_gpio2_clken") - -// User extension aux register io_gpio2_swporta_dr -#define AR_IO_GPIO2_SWPORTA_DR 0x80017200 -#pragma Aux_register(0x80017200, name=>"io_gpio2_swporta_dr") - -// User extension aux register io_gpio2_swporta_ddr -#define AR_IO_GPIO2_SWPORTA_DDR 0x80017204 -#pragma Aux_register(0x80017204, name=>"io_gpio2_swporta_ddr") - -// User extension aux register io_gpio2_inten -#define AR_IO_GPIO2_INTEN 0x80017230 -#pragma Aux_register(0x80017230, name=>"io_gpio2_inten") - -// User extension aux register io_gpio2_intmask -#define AR_IO_GPIO2_INTMASK 0x80017234 -#pragma Aux_register(0x80017234, name=>"io_gpio2_intmask") - -// User extension aux register io_gpio2_inttype_level -#define AR_IO_GPIO2_INTTYPE_LEVEL 0x80017238 -#pragma Aux_register(0x80017238, name=>"io_gpio2_inttype_level") - -// User extension aux register io_gpio2_int_polarity -#define AR_IO_GPIO2_INT_POLARITY 0x8001723c -#pragma Aux_register(0x8001723c, name=>"io_gpio2_int_polarity") - -// User extension aux register io_gpio2_intstatus -#define AR_IO_GPIO2_INTSTATUS 0x80017240 -#pragma Aux_register(0x80017240, name=>"io_gpio2_intstatus") - -// User extension aux register io_gpio2_raw_intstatus -#define AR_IO_GPIO2_RAW_INTSTATUS 0x80017244 -#pragma Aux_register(0x80017244, name=>"io_gpio2_raw_intstatus") - -// User extension aux register io_gpio2_porta_eoi -#define AR_IO_GPIO2_PORTA_EOI 0x8001724c -#pragma Aux_register(0x8001724c, name=>"io_gpio2_porta_eoi") - -// User extension aux register io_gpio2_ext_porta -#define AR_IO_GPIO2_EXT_PORTA 0x80017250 -#pragma Aux_register(0x80017250, name=>"io_gpio2_ext_porta") - -// User extension aux register io_gpio2_ls_sync -#define AR_IO_GPIO2_LS_SYNC 0x80017260 -#pragma Aux_register(0x80017260, name=>"io_gpio2_ls_sync") - -// User extension aux register io_gpio2_int_bothedge -#define AR_IO_GPIO2_INT_BOTHEDGE 0x80017268 -#pragma Aux_register(0x80017268, name=>"io_gpio2_int_bothedge") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_I2C_MST0_PRESENT 1 - -// User extension aux register io_i2c_mst0_clken -#define AR_IO_I2C_MST0_CLKEN 0x800120c0 -#pragma Aux_register(0x800120c0, name=>"io_i2c_mst0_clken") - -// User extension aux register io_i2c_mst0_con -#define AR_IO_I2C_MST0_CON 0x80012000 -#pragma Aux_register(0x80012000, name=>"io_i2c_mst0_con") - -// User extension aux register io_i2c_mst0_tar -#define AR_IO_I2C_MST0_TAR 0x80012004 -#pragma Aux_register(0x80012004, name=>"io_i2c_mst0_tar") - -// User extension aux register io_i2c_mst0_data_cmd -#define AR_IO_I2C_MST0_DATA_CMD 0x80012010 -#pragma Aux_register(0x80012010, name=>"io_i2c_mst0_data_cmd") - -// User extension aux register io_i2c_mst0_ss_scl_hcnt -#define AR_IO_I2C_MST0_SS_SCL_HCNT 0x80012014 -#pragma Aux_register(0x80012014, name=>"io_i2c_mst0_ss_scl_hcnt") - -// User extension aux register io_i2c_mst0_ss_scl_lcnt -#define AR_IO_I2C_MST0_SS_SCL_LCNT 0x80012018 -#pragma Aux_register(0x80012018, name=>"io_i2c_mst0_ss_scl_lcnt") - -// User extension aux register io_i2c_mst0_fs_scl_hcnt -#define AR_IO_I2C_MST0_FS_SCL_HCNT 0x8001201c -#pragma Aux_register(0x8001201c, name=>"io_i2c_mst0_fs_scl_hcnt") - -// User extension aux register io_i2c_mst0_fs_scl_lcnt -#define AR_IO_I2C_MST0_FS_SCL_LCNT 0x80012020 -#pragma Aux_register(0x80012020, name=>"io_i2c_mst0_fs_scl_lcnt") - -// User extension aux register io_i2c_mst0_intr_stat -#define AR_IO_I2C_MST0_INTR_STAT 0x8001202c -#pragma Aux_register(0x8001202c, name=>"io_i2c_mst0_intr_stat") - -// User extension aux register io_i2c_mst0_intr_mask -#define AR_IO_I2C_MST0_INTR_MASK 0x80012030 -#pragma Aux_register(0x80012030, name=>"io_i2c_mst0_intr_mask") - -// User extension aux register io_i2c_mst0_raw_intr_stat -#define AR_IO_I2C_MST0_RAW_INTR_STAT 0x80012034 -#pragma Aux_register(0x80012034, name=>"io_i2c_mst0_raw_intr_stat") - -// User extension aux register io_i2c_mst0_rx_tl -#define AR_IO_I2C_MST0_RX_TL 0x80012038 -#pragma Aux_register(0x80012038, name=>"io_i2c_mst0_rx_tl") - -// User extension aux register io_i2c_mst0_tx_tl -#define AR_IO_I2C_MST0_TX_TL 0x8001203c -#pragma Aux_register(0x8001203c, name=>"io_i2c_mst0_tx_tl") - -// User extension aux register io_i2c_mst0_clr_intr -#define AR_IO_I2C_MST0_CLR_INTR 0x80012040 -#pragma Aux_register(0x80012040, name=>"io_i2c_mst0_clr_intr") - -// User extension aux register io_i2c_mst0_clr_rx_under -#define AR_IO_I2C_MST0_CLR_RX_UNDER 0x80012044 -#pragma Aux_register(0x80012044, name=>"io_i2c_mst0_clr_rx_under") - -// User extension aux register io_i2c_mst0_clr_rx_over -#define AR_IO_I2C_MST0_CLR_RX_OVER 0x80012048 -#pragma Aux_register(0x80012048, name=>"io_i2c_mst0_clr_rx_over") - -// User extension aux register io_i2c_mst0_clr_tx_over -#define AR_IO_I2C_MST0_CLR_TX_OVER 0x8001204c -#pragma Aux_register(0x8001204c, name=>"io_i2c_mst0_clr_tx_over") - -// User extension aux register io_i2c_mst0_clr_tx_abrt -#define AR_IO_I2C_MST0_CLR_TX_ABRT 0x80012054 -#pragma Aux_register(0x80012054, name=>"io_i2c_mst0_clr_tx_abrt") - -// User extension aux register io_i2c_mst0_clr_activity -#define AR_IO_I2C_MST0_CLR_ACTIVITY 0x8001205c -#pragma Aux_register(0x8001205c, name=>"io_i2c_mst0_clr_activity") - -// User extension aux register io_i2c_mst0_clr_stop_det -#define AR_IO_I2C_MST0_CLR_STOP_DET 0x80012060 -#pragma Aux_register(0x80012060, name=>"io_i2c_mst0_clr_stop_det") - -// User extension aux register io_i2c_mst0_clr_start_det -#define AR_IO_I2C_MST0_CLR_START_DET 0x80012064 -#pragma Aux_register(0x80012064, name=>"io_i2c_mst0_clr_start_det") - -// User extension aux register io_i2c_mst0_enable -#define AR_IO_I2C_MST0_ENABLE 0x8001206c -#pragma Aux_register(0x8001206c, name=>"io_i2c_mst0_enable") - -// User extension aux register io_i2c_mst0_status -#define AR_IO_I2C_MST0_STATUS 0x80012070 -#pragma Aux_register(0x80012070, name=>"io_i2c_mst0_status") - -// User extension aux register io_i2c_mst0_txflr -#define AR_IO_I2C_MST0_TXFLR 0x80012074 -#pragma Aux_register(0x80012074, name=>"io_i2c_mst0_txflr") - -// User extension aux register io_i2c_mst0_rxflr -#define AR_IO_I2C_MST0_RXFLR 0x80012078 -#pragma Aux_register(0x80012078, name=>"io_i2c_mst0_rxflr") - -// User extension aux register io_i2c_mst0_sda_hold -#define AR_IO_I2C_MST0_SDA_HOLD 0x8001207c -#pragma Aux_register(0x8001207c, name=>"io_i2c_mst0_sda_hold") - -// User extension aux register io_i2c_mst0_tx_abrt_source -#define AR_IO_I2C_MST0_TX_ABRT_SOURCE 0x80012080 -#pragma Aux_register(0x80012080, name=>"io_i2c_mst0_tx_abrt_source") - -// User extension aux register io_i2c_mst0_enable_status -#define AR_IO_I2C_MST0_ENABLE_STATUS 0x8001209c -#pragma Aux_register(0x8001209c, name=>"io_i2c_mst0_enable_status") - -// User extension aux register io_i2c_mst0_fs_spklen -#define AR_IO_I2C_MST0_FS_SPKLEN 0x800120a0 -#pragma Aux_register(0x800120a0, name=>"io_i2c_mst0_fs_spklen") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_I2C_MST1_PRESENT 1 - -// User extension aux register io_i2c_mst1_clken -#define AR_IO_I2C_MST1_CLKEN 0x800121c0 -#pragma Aux_register(0x800121c0, name=>"io_i2c_mst1_clken") - -// User extension aux register io_i2c_mst1_con -#define AR_IO_I2C_MST1_CON 0x80012100 -#pragma Aux_register(0x80012100, name=>"io_i2c_mst1_con") - -// User extension aux register io_i2c_mst1_tar -#define AR_IO_I2C_MST1_TAR 0x80012104 -#pragma Aux_register(0x80012104, name=>"io_i2c_mst1_tar") - -// User extension aux register io_i2c_mst1_data_cmd -#define AR_IO_I2C_MST1_DATA_CMD 0x80012110 -#pragma Aux_register(0x80012110, name=>"io_i2c_mst1_data_cmd") - -// User extension aux register io_i2c_mst1_ss_scl_hcnt -#define AR_IO_I2C_MST1_SS_SCL_HCNT 0x80012114 -#pragma Aux_register(0x80012114, name=>"io_i2c_mst1_ss_scl_hcnt") - -// User extension aux register io_i2c_mst1_ss_scl_lcnt -#define AR_IO_I2C_MST1_SS_SCL_LCNT 0x80012118 -#pragma Aux_register(0x80012118, name=>"io_i2c_mst1_ss_scl_lcnt") - -// User extension aux register io_i2c_mst1_fs_scl_hcnt -#define AR_IO_I2C_MST1_FS_SCL_HCNT 0x8001211c -#pragma Aux_register(0x8001211c, name=>"io_i2c_mst1_fs_scl_hcnt") - -// User extension aux register io_i2c_mst1_fs_scl_lcnt -#define AR_IO_I2C_MST1_FS_SCL_LCNT 0x80012120 -#pragma Aux_register(0x80012120, name=>"io_i2c_mst1_fs_scl_lcnt") - -// User extension aux register io_i2c_mst1_intr_stat -#define AR_IO_I2C_MST1_INTR_STAT 0x8001212c -#pragma Aux_register(0x8001212c, name=>"io_i2c_mst1_intr_stat") - -// User extension aux register io_i2c_mst1_intr_mask -#define AR_IO_I2C_MST1_INTR_MASK 0x80012130 -#pragma Aux_register(0x80012130, name=>"io_i2c_mst1_intr_mask") - -// User extension aux register io_i2c_mst1_raw_intr_stat -#define AR_IO_I2C_MST1_RAW_INTR_STAT 0x80012134 -#pragma Aux_register(0x80012134, name=>"io_i2c_mst1_raw_intr_stat") - -// User extension aux register io_i2c_mst1_rx_tl -#define AR_IO_I2C_MST1_RX_TL 0x80012138 -#pragma Aux_register(0x80012138, name=>"io_i2c_mst1_rx_tl") - -// User extension aux register io_i2c_mst1_tx_tl -#define AR_IO_I2C_MST1_TX_TL 0x8001213c -#pragma Aux_register(0x8001213c, name=>"io_i2c_mst1_tx_tl") - -// User extension aux register io_i2c_mst1_clr_intr -#define AR_IO_I2C_MST1_CLR_INTR 0x80012140 -#pragma Aux_register(0x80012140, name=>"io_i2c_mst1_clr_intr") - -// User extension aux register io_i2c_mst1_clr_rx_under -#define AR_IO_I2C_MST1_CLR_RX_UNDER 0x80012144 -#pragma Aux_register(0x80012144, name=>"io_i2c_mst1_clr_rx_under") - -// User extension aux register io_i2c_mst1_clr_rx_over -#define AR_IO_I2C_MST1_CLR_RX_OVER 0x80012148 -#pragma Aux_register(0x80012148, name=>"io_i2c_mst1_clr_rx_over") - -// User extension aux register io_i2c_mst1_clr_tx_over -#define AR_IO_I2C_MST1_CLR_TX_OVER 0x8001214c -#pragma Aux_register(0x8001214c, name=>"io_i2c_mst1_clr_tx_over") - -// User extension aux register io_i2c_mst1_clr_tx_abrt -#define AR_IO_I2C_MST1_CLR_TX_ABRT 0x80012154 -#pragma Aux_register(0x80012154, name=>"io_i2c_mst1_clr_tx_abrt") - -// User extension aux register io_i2c_mst1_clr_activity -#define AR_IO_I2C_MST1_CLR_ACTIVITY 0x8001215c -#pragma Aux_register(0x8001215c, name=>"io_i2c_mst1_clr_activity") - -// User extension aux register io_i2c_mst1_clr_stop_det -#define AR_IO_I2C_MST1_CLR_STOP_DET 0x80012160 -#pragma Aux_register(0x80012160, name=>"io_i2c_mst1_clr_stop_det") - -// User extension aux register io_i2c_mst1_clr_start_det -#define AR_IO_I2C_MST1_CLR_START_DET 0x80012164 -#pragma Aux_register(0x80012164, name=>"io_i2c_mst1_clr_start_det") - -// User extension aux register io_i2c_mst1_enable -#define AR_IO_I2C_MST1_ENABLE 0x8001216c -#pragma Aux_register(0x8001216c, name=>"io_i2c_mst1_enable") - -// User extension aux register io_i2c_mst1_status -#define AR_IO_I2C_MST1_STATUS 0x80012170 -#pragma Aux_register(0x80012170, name=>"io_i2c_mst1_status") - -// User extension aux register io_i2c_mst1_txflr -#define AR_IO_I2C_MST1_TXFLR 0x80012174 -#pragma Aux_register(0x80012174, name=>"io_i2c_mst1_txflr") - -// User extension aux register io_i2c_mst1_rxflr -#define AR_IO_I2C_MST1_RXFLR 0x80012178 -#pragma Aux_register(0x80012178, name=>"io_i2c_mst1_rxflr") - -// User extension aux register io_i2c_mst1_sda_hold -#define AR_IO_I2C_MST1_SDA_HOLD 0x8001217c -#pragma Aux_register(0x8001217c, name=>"io_i2c_mst1_sda_hold") - -// User extension aux register io_i2c_mst1_tx_abrt_source -#define AR_IO_I2C_MST1_TX_ABRT_SOURCE 0x80012180 -#pragma Aux_register(0x80012180, name=>"io_i2c_mst1_tx_abrt_source") - -// User extension aux register io_i2c_mst1_enable_status -#define AR_IO_I2C_MST1_ENABLE_STATUS 0x8001219c -#pragma Aux_register(0x8001219c, name=>"io_i2c_mst1_enable_status") - -// User extension aux register io_i2c_mst1_fs_spklen -#define AR_IO_I2C_MST1_FS_SPKLEN 0x800121a0 -#pragma Aux_register(0x800121a0, name=>"io_i2c_mst1_fs_spklen") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_I2C_MST2_PRESENT 1 - -// User extension aux register io_i2c_mst2_clken -#define AR_IO_I2C_MST2_CLKEN 0x800122c0 -#pragma Aux_register(0x800122c0, name=>"io_i2c_mst2_clken") - -// User extension aux register io_i2c_mst2_con -#define AR_IO_I2C_MST2_CON 0x80012200 -#pragma Aux_register(0x80012200, name=>"io_i2c_mst2_con") - -// User extension aux register io_i2c_mst2_tar -#define AR_IO_I2C_MST2_TAR 0x80012204 -#pragma Aux_register(0x80012204, name=>"io_i2c_mst2_tar") - -// User extension aux register io_i2c_mst2_data_cmd -#define AR_IO_I2C_MST2_DATA_CMD 0x80012210 -#pragma Aux_register(0x80012210, name=>"io_i2c_mst2_data_cmd") - -// User extension aux register io_i2c_mst2_ss_scl_hcnt -#define AR_IO_I2C_MST2_SS_SCL_HCNT 0x80012214 -#pragma Aux_register(0x80012214, name=>"io_i2c_mst2_ss_scl_hcnt") - -// User extension aux register io_i2c_mst2_ss_scl_lcnt -#define AR_IO_I2C_MST2_SS_SCL_LCNT 0x80012218 -#pragma Aux_register(0x80012218, name=>"io_i2c_mst2_ss_scl_lcnt") - -// User extension aux register io_i2c_mst2_fs_scl_hcnt -#define AR_IO_I2C_MST2_FS_SCL_HCNT 0x8001221c -#pragma Aux_register(0x8001221c, name=>"io_i2c_mst2_fs_scl_hcnt") - -// User extension aux register io_i2c_mst2_fs_scl_lcnt -#define AR_IO_I2C_MST2_FS_SCL_LCNT 0x80012220 -#pragma Aux_register(0x80012220, name=>"io_i2c_mst2_fs_scl_lcnt") - -// User extension aux register io_i2c_mst2_intr_stat -#define AR_IO_I2C_MST2_INTR_STAT 0x8001222c -#pragma Aux_register(0x8001222c, name=>"io_i2c_mst2_intr_stat") - -// User extension aux register io_i2c_mst2_intr_mask -#define AR_IO_I2C_MST2_INTR_MASK 0x80012230 -#pragma Aux_register(0x80012230, name=>"io_i2c_mst2_intr_mask") - -// User extension aux register io_i2c_mst2_raw_intr_stat -#define AR_IO_I2C_MST2_RAW_INTR_STAT 0x80012234 -#pragma Aux_register(0x80012234, name=>"io_i2c_mst2_raw_intr_stat") - -// User extension aux register io_i2c_mst2_rx_tl -#define AR_IO_I2C_MST2_RX_TL 0x80012238 -#pragma Aux_register(0x80012238, name=>"io_i2c_mst2_rx_tl") - -// User extension aux register io_i2c_mst2_tx_tl -#define AR_IO_I2C_MST2_TX_TL 0x8001223c -#pragma Aux_register(0x8001223c, name=>"io_i2c_mst2_tx_tl") - -// User extension aux register io_i2c_mst2_clr_intr -#define AR_IO_I2C_MST2_CLR_INTR 0x80012240 -#pragma Aux_register(0x80012240, name=>"io_i2c_mst2_clr_intr") - -// User extension aux register io_i2c_mst2_clr_rx_under -#define AR_IO_I2C_MST2_CLR_RX_UNDER 0x80012244 -#pragma Aux_register(0x80012244, name=>"io_i2c_mst2_clr_rx_under") - -// User extension aux register io_i2c_mst2_clr_rx_over -#define AR_IO_I2C_MST2_CLR_RX_OVER 0x80012248 -#pragma Aux_register(0x80012248, name=>"io_i2c_mst2_clr_rx_over") - -// User extension aux register io_i2c_mst2_clr_tx_over -#define AR_IO_I2C_MST2_CLR_TX_OVER 0x8001224c -#pragma Aux_register(0x8001224c, name=>"io_i2c_mst2_clr_tx_over") - -// User extension aux register io_i2c_mst2_clr_tx_abrt -#define AR_IO_I2C_MST2_CLR_TX_ABRT 0x80012254 -#pragma Aux_register(0x80012254, name=>"io_i2c_mst2_clr_tx_abrt") - -// User extension aux register io_i2c_mst2_clr_activity -#define AR_IO_I2C_MST2_CLR_ACTIVITY 0x8001225c -#pragma Aux_register(0x8001225c, name=>"io_i2c_mst2_clr_activity") - -// User extension aux register io_i2c_mst2_clr_stop_det -#define AR_IO_I2C_MST2_CLR_STOP_DET 0x80012260 -#pragma Aux_register(0x80012260, name=>"io_i2c_mst2_clr_stop_det") - -// User extension aux register io_i2c_mst2_clr_start_det -#define AR_IO_I2C_MST2_CLR_START_DET 0x80012264 -#pragma Aux_register(0x80012264, name=>"io_i2c_mst2_clr_start_det") - -// User extension aux register io_i2c_mst2_enable -#define AR_IO_I2C_MST2_ENABLE 0x8001226c -#pragma Aux_register(0x8001226c, name=>"io_i2c_mst2_enable") - -// User extension aux register io_i2c_mst2_status -#define AR_IO_I2C_MST2_STATUS 0x80012270 -#pragma Aux_register(0x80012270, name=>"io_i2c_mst2_status") - -// User extension aux register io_i2c_mst2_txflr -#define AR_IO_I2C_MST2_TXFLR 0x80012274 -#pragma Aux_register(0x80012274, name=>"io_i2c_mst2_txflr") - -// User extension aux register io_i2c_mst2_rxflr -#define AR_IO_I2C_MST2_RXFLR 0x80012278 -#pragma Aux_register(0x80012278, name=>"io_i2c_mst2_rxflr") - -// User extension aux register io_i2c_mst2_sda_hold -#define AR_IO_I2C_MST2_SDA_HOLD 0x8001227c -#pragma Aux_register(0x8001227c, name=>"io_i2c_mst2_sda_hold") - -// User extension aux register io_i2c_mst2_tx_abrt_source -#define AR_IO_I2C_MST2_TX_ABRT_SOURCE 0x80012280 -#pragma Aux_register(0x80012280, name=>"io_i2c_mst2_tx_abrt_source") - -// User extension aux register io_i2c_mst2_enable_status -#define AR_IO_I2C_MST2_ENABLE_STATUS 0x8001229c -#pragma Aux_register(0x8001229c, name=>"io_i2c_mst2_enable_status") - -// User extension aux register io_i2c_mst2_fs_spklen -#define AR_IO_I2C_MST2_FS_SPKLEN 0x800122a0 -#pragma Aux_register(0x800122a0, name=>"io_i2c_mst2_fs_spklen") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_I2C_SLV0_PRESENT 1 - -// User extension aux register io_i2c_slv0_clken -#define AR_IO_I2C_SLV0_CLKEN 0x800130c0 -#pragma Aux_register(0x800130c0, name=>"io_i2c_slv0_clken") - -// User extension aux register io_i2c_slv0_con -#define AR_IO_I2C_SLV0_CON 0x80013000 -#pragma Aux_register(0x80013000, name=>"io_i2c_slv0_con") - -// User extension aux register io_i2c_slv0_sar -#define AR_IO_I2C_SLV0_SAR 0x80013008 -#pragma Aux_register(0x80013008, name=>"io_i2c_slv0_sar") - -// User extension aux register io_i2c_slv0_data_cmd -#define AR_IO_I2C_SLV0_DATA_CMD 0x80013010 -#pragma Aux_register(0x80013010, name=>"io_i2c_slv0_data_cmd") - -// User extension aux register io_i2c_slv0_intr_stat -#define AR_IO_I2C_SLV0_INTR_STAT 0x8001302c -#pragma Aux_register(0x8001302c, name=>"io_i2c_slv0_intr_stat") - -// User extension aux register io_i2c_slv0_intr_mask -#define AR_IO_I2C_SLV0_INTR_MASK 0x80013030 -#pragma Aux_register(0x80013030, name=>"io_i2c_slv0_intr_mask") - -// User extension aux register io_i2c_slv0_raw_intr_stat -#define AR_IO_I2C_SLV0_RAW_INTR_STAT 0x80013034 -#pragma Aux_register(0x80013034, name=>"io_i2c_slv0_raw_intr_stat") - -// User extension aux register io_i2c_slv0_rx_tl -#define AR_IO_I2C_SLV0_RX_TL 0x80013038 -#pragma Aux_register(0x80013038, name=>"io_i2c_slv0_rx_tl") - -// User extension aux register io_i2c_slv0_tx_tl -#define AR_IO_I2C_SLV0_TX_TL 0x8001303c -#pragma Aux_register(0x8001303c, name=>"io_i2c_slv0_tx_tl") - -// User extension aux register io_i2c_slv0_clr_intr -#define AR_IO_I2C_SLV0_CLR_INTR 0x80013040 -#pragma Aux_register(0x80013040, name=>"io_i2c_slv0_clr_intr") - -// User extension aux register io_i2c_slv0_clr_rx_under -#define AR_IO_I2C_SLV0_CLR_RX_UNDER 0x80013044 -#pragma Aux_register(0x80013044, name=>"io_i2c_slv0_clr_rx_under") - -// User extension aux register io_i2c_slv0_clr_rx_over -#define AR_IO_I2C_SLV0_CLR_RX_OVER 0x80013048 -#pragma Aux_register(0x80013048, name=>"io_i2c_slv0_clr_rx_over") - -// User extension aux register io_i2c_slv0_clr_tx_over -#define AR_IO_I2C_SLV0_CLR_TX_OVER 0x8001304c -#pragma Aux_register(0x8001304c, name=>"io_i2c_slv0_clr_tx_over") - -// User extension aux register io_i2c_slv0_clr_rd_req -#define AR_IO_I2C_SLV0_CLR_RD_REQ 0x80013050 -#pragma Aux_register(0x80013050, name=>"io_i2c_slv0_clr_rd_req") - -// User extension aux register io_i2c_slv0_clr_tx_abrt -#define AR_IO_I2C_SLV0_CLR_TX_ABRT 0x80013054 -#pragma Aux_register(0x80013054, name=>"io_i2c_slv0_clr_tx_abrt") - -// User extension aux register io_i2c_slv0_clr_rx_done -#define AR_IO_I2C_SLV0_CLR_RX_DONE 0x80013058 -#pragma Aux_register(0x80013058, name=>"io_i2c_slv0_clr_rx_done") - -// User extension aux register io_i2c_slv0_clr_activity -#define AR_IO_I2C_SLV0_CLR_ACTIVITY 0x8001305c -#pragma Aux_register(0x8001305c, name=>"io_i2c_slv0_clr_activity") - -// User extension aux register io_i2c_slv0_clr_stop_det -#define AR_IO_I2C_SLV0_CLR_STOP_DET 0x80013060 -#pragma Aux_register(0x80013060, name=>"io_i2c_slv0_clr_stop_det") - -// User extension aux register io_i2c_slv0_clr_start_det -#define AR_IO_I2C_SLV0_CLR_START_DET 0x80013064 -#pragma Aux_register(0x80013064, name=>"io_i2c_slv0_clr_start_det") - -// User extension aux register io_i2c_slv0_enable -#define AR_IO_I2C_SLV0_ENABLE 0x8001306c -#pragma Aux_register(0x8001306c, name=>"io_i2c_slv0_enable") - -// User extension aux register io_i2c_slv0_status -#define AR_IO_I2C_SLV0_STATUS 0x80013070 -#pragma Aux_register(0x80013070, name=>"io_i2c_slv0_status") - -// User extension aux register io_i2c_slv0_txflr -#define AR_IO_I2C_SLV0_TXFLR 0x80013074 -#pragma Aux_register(0x80013074, name=>"io_i2c_slv0_txflr") - -// User extension aux register io_i2c_slv0_rxflr -#define AR_IO_I2C_SLV0_RXFLR 0x80013078 -#pragma Aux_register(0x80013078, name=>"io_i2c_slv0_rxflr") - -// User extension aux register io_i2c_slv0_sda_hold -#define AR_IO_I2C_SLV0_SDA_HOLD 0x8001307c -#pragma Aux_register(0x8001307c, name=>"io_i2c_slv0_sda_hold") - -// User extension aux register io_i2c_slv0_tx_abrt_source -#define AR_IO_I2C_SLV0_TX_ABRT_SOURCE 0x80013080 -#pragma Aux_register(0x80013080, name=>"io_i2c_slv0_tx_abrt_source") - -// User extension aux register io_i2c_slv0_sda_setup -#define AR_IO_I2C_SLV0_SDA_SETUP 0x80013094 -#pragma Aux_register(0x80013094, name=>"io_i2c_slv0_sda_setup") - -// User extension aux register io_i2c_slv0_enable_status -#define AR_IO_I2C_SLV0_ENABLE_STATUS 0x8001309c -#pragma Aux_register(0x8001309c, name=>"io_i2c_slv0_enable_status") - -// User extension aux register io_i2c_slv0_fs_spklen -#define AR_IO_I2C_SLV0_FS_SPKLEN 0x800130a0 -#pragma Aux_register(0x800130a0, name=>"io_i2c_slv0_fs_spklen") - -// User extension aux register io_i2c_slv0_clr_restart_det -#define AR_IO_I2C_SLV0_CLR_RESTART_DET 0x800130a8 -#pragma Aux_register(0x800130a8, name=>"io_i2c_slv0_clr_restart_det") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_PWM0_PRESENT 1 - -// User extension aux register io_pwm0_clken -#define AR_IO_PWM0_CLKEN 0x8001d020 -#pragma Aux_register(0x8001d020, name=>"io_pwm0_clken") - -// User extension aux register io_pwm0_ctrl -#define AR_IO_PWM0_CTRL 0x8001d000 -#pragma Aux_register(0x8001d000, name=>"io_pwm0_ctrl") - -// User extension aux register io_pwm0_chn_config -#define AR_IO_PWM0_CHN_CONFIG 0x8001d001 -#pragma Aux_register(0x8001d001, name=>"io_pwm0_chn_config") - -// User extension aux register io_pwm0_trigger -#define AR_IO_PWM0_TRIGGER 0x8001d002 -#pragma Aux_register(0x8001d002, name=>"io_pwm0_trigger") - -// User extension aux register io_pwm0_fault -#define AR_IO_PWM0_FAULT 0x8001d003 -#pragma Aux_register(0x8001d003, name=>"io_pwm0_fault") - -// User extension aux register io_pwm0_events -#define AR_IO_PWM0_EVENTS 0x8001d004 -#pragma Aux_register(0x8001d004, name=>"io_pwm0_events") - -// User extension aux register io_pwm0_intctrl -#define AR_IO_PWM0_INTCTRL 0x8001d005 -#pragma Aux_register(0x8001d005, name=>"io_pwm0_intctrl") - -// User extension aux register io_pwm0_intstat -#define AR_IO_PWM0_INTSTAT 0x8001d006 -#pragma Aux_register(0x8001d006, name=>"io_pwm0_intstat") - -// User extension aux register io_pwm0_intclr -#define AR_IO_PWM0_INTCLR 0x8001d007 -#pragma Aux_register(0x8001d007, name=>"io_pwm0_intclr") - -// User extension aux register io_pwm0_threshold_01 -#define AR_IO_PWM0_THRESHOLD_01 0x8001d008 -#pragma Aux_register(0x8001d008, name=>"io_pwm0_threshold_01") - -// User extension aux register io_pwm0_threshold_23 -#define AR_IO_PWM0_THRESHOLD_23 0x8001d009 -#pragma Aux_register(0x8001d009, name=>"io_pwm0_threshold_23") - -// User extension aux register io_pwm0_threshold_45 -#define AR_IO_PWM0_THRESHOLD_45 0x8001d00a -#pragma Aux_register(0x8001d00a, name=>"io_pwm0_threshold_45") - -// User extension aux register io_pwm0_threshold_67 -#define AR_IO_PWM0_THRESHOLD_67 0x8001d00b -#pragma Aux_register(0x8001d00b, name=>"io_pwm0_threshold_67") - -// User extension aux register io_pwm0_deadzone_01 -#define AR_IO_PWM0_DEADZONE_01 0x8001d00c -#pragma Aux_register(0x8001d00c, name=>"io_pwm0_deadzone_01") - -// User extension aux register io_pwm0_deadzone_23 -#define AR_IO_PWM0_DEADZONE_23 0x8001d00d -#pragma Aux_register(0x8001d00d, name=>"io_pwm0_deadzone_23") - -// User extension aux register io_pwm0_deadzone_45 -#define AR_IO_PWM0_DEADZONE_45 0x8001d00e -#pragma Aux_register(0x8001d00e, name=>"io_pwm0_deadzone_45") - -// User extension aux register io_pwm0_deadzone_67 -#define AR_IO_PWM0_DEADZONE_67 0x8001d00f -#pragma Aux_register(0x8001d00f, name=>"io_pwm0_deadzone_67") - -// User extension aux register io_pwm0_timer_max -#define AR_IO_PWM0_TIMER_MAX 0x8001d010 -#pragma Aux_register(0x8001d010, name=>"io_pwm0_timer_max") - -// User extension aux register io_pwm0_nperiods -#define AR_IO_PWM0_NPERIODS 0x8001d011 -#pragma Aux_register(0x8001d011, name=>"io_pwm0_nperiods") - -// User extension aux register io_pwm0_clk_div -#define AR_IO_PWM0_CLK_DIV 0x8001d012 -#pragma Aux_register(0x8001d012, name=>"io_pwm0_clk_div") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_PWM1_PRESENT 1 - -// User extension aux register io_pwm1_clken -#define AR_IO_PWM1_CLKEN 0x8001d120 -#pragma Aux_register(0x8001d120, name=>"io_pwm1_clken") - -// User extension aux register io_pwm1_ctrl -#define AR_IO_PWM1_CTRL 0x8001d100 -#pragma Aux_register(0x8001d100, name=>"io_pwm1_ctrl") - -// User extension aux register io_pwm1_chn_config -#define AR_IO_PWM1_CHN_CONFIG 0x8001d101 -#pragma Aux_register(0x8001d101, name=>"io_pwm1_chn_config") - -// User extension aux register io_pwm1_trigger -#define AR_IO_PWM1_TRIGGER 0x8001d102 -#pragma Aux_register(0x8001d102, name=>"io_pwm1_trigger") - -// User extension aux register io_pwm1_fault -#define AR_IO_PWM1_FAULT 0x8001d103 -#pragma Aux_register(0x8001d103, name=>"io_pwm1_fault") - -// User extension aux register io_pwm1_events -#define AR_IO_PWM1_EVENTS 0x8001d104 -#pragma Aux_register(0x8001d104, name=>"io_pwm1_events") - -// User extension aux register io_pwm1_intctrl -#define AR_IO_PWM1_INTCTRL 0x8001d105 -#pragma Aux_register(0x8001d105, name=>"io_pwm1_intctrl") - -// User extension aux register io_pwm1_intstat -#define AR_IO_PWM1_INTSTAT 0x8001d106 -#pragma Aux_register(0x8001d106, name=>"io_pwm1_intstat") - -// User extension aux register io_pwm1_intclr -#define AR_IO_PWM1_INTCLR 0x8001d107 -#pragma Aux_register(0x8001d107, name=>"io_pwm1_intclr") - -// User extension aux register io_pwm1_threshold_01 -#define AR_IO_PWM1_THRESHOLD_01 0x8001d108 -#pragma Aux_register(0x8001d108, name=>"io_pwm1_threshold_01") - -// User extension aux register io_pwm1_threshold_23 -#define AR_IO_PWM1_THRESHOLD_23 0x8001d109 -#pragma Aux_register(0x8001d109, name=>"io_pwm1_threshold_23") - -// User extension aux register io_pwm1_threshold_45 -#define AR_IO_PWM1_THRESHOLD_45 0x8001d10a -#pragma Aux_register(0x8001d10a, name=>"io_pwm1_threshold_45") - -// User extension aux register io_pwm1_threshold_67 -#define AR_IO_PWM1_THRESHOLD_67 0x8001d10b -#pragma Aux_register(0x8001d10b, name=>"io_pwm1_threshold_67") - -// User extension aux register io_pwm1_deadzone_01 -#define AR_IO_PWM1_DEADZONE_01 0x8001d10c -#pragma Aux_register(0x8001d10c, name=>"io_pwm1_deadzone_01") - -// User extension aux register io_pwm1_deadzone_23 -#define AR_IO_PWM1_DEADZONE_23 0x8001d10d -#pragma Aux_register(0x8001d10d, name=>"io_pwm1_deadzone_23") - -// User extension aux register io_pwm1_deadzone_45 -#define AR_IO_PWM1_DEADZONE_45 0x8001d10e -#pragma Aux_register(0x8001d10e, name=>"io_pwm1_deadzone_45") - -// User extension aux register io_pwm1_deadzone_67 -#define AR_IO_PWM1_DEADZONE_67 0x8001d10f -#pragma Aux_register(0x8001d10f, name=>"io_pwm1_deadzone_67") - -// User extension aux register io_pwm1_timer_max -#define AR_IO_PWM1_TIMER_MAX 0x8001d110 -#pragma Aux_register(0x8001d110, name=>"io_pwm1_timer_max") - -// User extension aux register io_pwm1_nperiods -#define AR_IO_PWM1_NPERIODS 0x8001d111 -#pragma Aux_register(0x8001d111, name=>"io_pwm1_nperiods") - -// User extension aux register io_pwm1_clk_div -#define AR_IO_PWM1_CLK_DIV 0x8001d112 -#pragma Aux_register(0x8001d112, name=>"io_pwm1_clk_div") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_SPI_MST0_PRESENT 1 - -// User extension aux register io_spi_mst0_ctrlr0 -#define AR_IO_SPI_MST0_CTRLR0 0x80010000 -#pragma Aux_register(0x80010000, name=>"io_spi_mst0_ctrlr0") - -// User extension aux register io_spi_mst0_ctrlr1 -#define AR_IO_SPI_MST0_CTRLR1 0x80010001 -#pragma Aux_register(0x80010001, name=>"io_spi_mst0_ctrlr1") - -// User extension aux register io_spi_mst0_spien -#define AR_IO_SPI_MST0_SPIEN 0x80010002 -#pragma Aux_register(0x80010002, name=>"io_spi_mst0_spien") - -// User extension aux register io_spi_mst0_ser -#define AR_IO_SPI_MST0_SER 0x80010004 -#pragma Aux_register(0x80010004, name=>"io_spi_mst0_ser") - -// User extension aux register io_spi_mst0_baudr -#define AR_IO_SPI_MST0_BAUDR 0x80010005 -#pragma Aux_register(0x80010005, name=>"io_spi_mst0_baudr") - -// User extension aux register io_spi_mst0_txftlr -#define AR_IO_SPI_MST0_TXFTLR 0x80010006 -#pragma Aux_register(0x80010006, name=>"io_spi_mst0_txftlr") - -// User extension aux register io_spi_mst0_rxftlr -#define AR_IO_SPI_MST0_RXFTLR 0x80010007 -#pragma Aux_register(0x80010007, name=>"io_spi_mst0_rxftlr") - -// User extension aux register io_spi_mst0_txflr -#define AR_IO_SPI_MST0_TXFLR 0x80010008 -#pragma Aux_register(0x80010008, name=>"io_spi_mst0_txflr") - -// User extension aux register io_spi_mst0_rxflr -#define AR_IO_SPI_MST0_RXFLR 0x80010009 -#pragma Aux_register(0x80010009, name=>"io_spi_mst0_rxflr") - -// User extension aux register io_spi_mst0_sr -#define AR_IO_SPI_MST0_SR 0x8001000a -#pragma Aux_register(0x8001000a, name=>"io_spi_mst0_sr") - -// User extension aux register io_spi_mst0_imr -#define AR_IO_SPI_MST0_IMR 0x8001000b -#pragma Aux_register(0x8001000b, name=>"io_spi_mst0_imr") - -// User extension aux register io_spi_mst0_isr -#define AR_IO_SPI_MST0_ISR 0x8001000c -#pragma Aux_register(0x8001000c, name=>"io_spi_mst0_isr") - -// User extension aux register io_spi_mst0_risr -#define AR_IO_SPI_MST0_RISR 0x8001000d -#pragma Aux_register(0x8001000d, name=>"io_spi_mst0_risr") - -// User extension aux register io_spi_mst0_txoicr -#define AR_IO_SPI_MST0_TXOICR 0x8001000e -#pragma Aux_register(0x8001000e, name=>"io_spi_mst0_txoicr") - -// User extension aux register io_spi_mst0_rxoicr -#define AR_IO_SPI_MST0_RXOICR 0x8001000f -#pragma Aux_register(0x8001000f, name=>"io_spi_mst0_rxoicr") - -// User extension aux register io_spi_mst0_rxuicr -#define AR_IO_SPI_MST0_RXUICR 0x80010010 -#pragma Aux_register(0x80010010, name=>"io_spi_mst0_rxuicr") - -// User extension aux register io_spi_mst0_icr -#define AR_IO_SPI_MST0_ICR 0x80010012 -#pragma Aux_register(0x80010012, name=>"io_spi_mst0_icr") - -// User extension aux register io_spi_mst0_clken -#define AR_IO_SPI_MST0_CLKEN 0x80010016 -#pragma Aux_register(0x80010016, name=>"io_spi_mst0_clken") - -// User extension aux register io_spi_mst0_dr -#define AR_IO_SPI_MST0_DR 0x80010018 -#pragma Aux_register(0x80010018, name=>"io_spi_mst0_dr") - -// User extension aux register io_spi_mst0_rx_sample_dly -#define AR_IO_SPI_MST0_RX_SAMPLE_DLY 0x8001003c -#pragma Aux_register(0x8001003c, name=>"io_spi_mst0_rx_sample_dly") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_SPI_SLV0_PRESENT 1 - -// User extension aux register io_spi_slv0_ctrlr0 -#define AR_IO_SPI_SLV0_CTRLR0 0x80011000 -#pragma Aux_register(0x80011000, name=>"io_spi_slv0_ctrlr0") - -// User extension aux register io_spi_slv0_spien -#define AR_IO_SPI_SLV0_SPIEN 0x80011002 -#pragma Aux_register(0x80011002, name=>"io_spi_slv0_spien") - -// User extension aux register io_spi_slv0_txftlr -#define AR_IO_SPI_SLV0_TXFTLR 0x80011006 -#pragma Aux_register(0x80011006, name=>"io_spi_slv0_txftlr") - -// User extension aux register io_spi_slv0_rxftlr -#define AR_IO_SPI_SLV0_RXFTLR 0x80011007 -#pragma Aux_register(0x80011007, name=>"io_spi_slv0_rxftlr") - -// User extension aux register io_spi_slv0_txflr -#define AR_IO_SPI_SLV0_TXFLR 0x80011008 -#pragma Aux_register(0x80011008, name=>"io_spi_slv0_txflr") - -// User extension aux register io_spi_slv0_rxflr -#define AR_IO_SPI_SLV0_RXFLR 0x80011009 -#pragma Aux_register(0x80011009, name=>"io_spi_slv0_rxflr") - -// User extension aux register io_spi_slv0_sr -#define AR_IO_SPI_SLV0_SR 0x8001100a -#pragma Aux_register(0x8001100a, name=>"io_spi_slv0_sr") - -// User extension aux register io_spi_slv0_imr -#define AR_IO_SPI_SLV0_IMR 0x8001100b -#pragma Aux_register(0x8001100b, name=>"io_spi_slv0_imr") - -// User extension aux register io_spi_slv0_isr -#define AR_IO_SPI_SLV0_ISR 0x8001100c -#pragma Aux_register(0x8001100c, name=>"io_spi_slv0_isr") - -// User extension aux register io_spi_slv0_risr -#define AR_IO_SPI_SLV0_RISR 0x8001100d -#pragma Aux_register(0x8001100d, name=>"io_spi_slv0_risr") - -// User extension aux register io_spi_slv0_txoicr -#define AR_IO_SPI_SLV0_TXOICR 0x8001100e -#pragma Aux_register(0x8001100e, name=>"io_spi_slv0_txoicr") - -// User extension aux register io_spi_slv0_rxoicr -#define AR_IO_SPI_SLV0_RXOICR 0x8001100f -#pragma Aux_register(0x8001100f, name=>"io_spi_slv0_rxoicr") - -// User extension aux register io_spi_slv0_rxuicr -#define AR_IO_SPI_SLV0_RXUICR 0x80011010 -#pragma Aux_register(0x80011010, name=>"io_spi_slv0_rxuicr") - -// User extension aux register io_spi_slv0_icr -#define AR_IO_SPI_SLV0_ICR 0x80011012 -#pragma Aux_register(0x80011012, name=>"io_spi_slv0_icr") - -// User extension aux register io_spi_slv0_clken -#define AR_IO_SPI_SLV0_CLKEN 0x80011016 -#pragma Aux_register(0x80011016, name=>"io_spi_slv0_clken") - -// User extension aux register io_spi_slv0_dr -#define AR_IO_SPI_SLV0_DR 0x80011018 -#pragma Aux_register(0x80011018, name=>"io_spi_slv0_dr") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_UART0_PRESENT 1 - -// User extension aux register io_uart0_clken -#define AR_IO_UART0_CLKEN 0x800140c0 -#pragma Aux_register(0x800140c0, name=>"io_uart0_clken") - -// User extension aux register io_uart0_rbr_thr_dll -#define AR_IO_UART0_RBR_THR_DLL 0x80014000 -#pragma Aux_register(0x80014000, name=>"io_uart0_rbr_thr_dll") - -// User extension aux register io_uart0_ier_dlh -#define AR_IO_UART0_IER_DLH 0x80014004 -#pragma Aux_register(0x80014004, name=>"io_uart0_ier_dlh") - -// User extension aux register io_uart0_iir_fcr -#define AR_IO_UART0_IIR_FCR 0x80014008 -#pragma Aux_register(0x80014008, name=>"io_uart0_iir_fcr") - -// User extension aux register io_uart0_lcr -#define AR_IO_UART0_LCR 0x8001400c -#pragma Aux_register(0x8001400c, name=>"io_uart0_lcr") - -// User extension aux register io_uart0_mcr -#define AR_IO_UART0_MCR 0x80014010 -#pragma Aux_register(0x80014010, name=>"io_uart0_mcr") - -// User extension aux register io_uart0_lsr -#define AR_IO_UART0_LSR 0x80014014 -#pragma Aux_register(0x80014014, name=>"io_uart0_lsr") - -// User extension aux register io_uart0_msr -#define AR_IO_UART0_MSR 0x80014018 -#pragma Aux_register(0x80014018, name=>"io_uart0_msr") - -// User extension aux register io_uart0_usr -#define AR_IO_UART0_USR 0x8001407c -#pragma Aux_register(0x8001407c, name=>"io_uart0_usr") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_UART1_PRESENT 1 - -// User extension aux register io_uart1_clken -#define AR_IO_UART1_CLKEN 0x800141c0 -#pragma Aux_register(0x800141c0, name=>"io_uart1_clken") - -// User extension aux register io_uart1_rbr_thr_dll -#define AR_IO_UART1_RBR_THR_DLL 0x80014100 -#pragma Aux_register(0x80014100, name=>"io_uart1_rbr_thr_dll") - -// User extension aux register io_uart1_ier_dlh -#define AR_IO_UART1_IER_DLH 0x80014104 -#pragma Aux_register(0x80014104, name=>"io_uart1_ier_dlh") - -// User extension aux register io_uart1_iir_fcr -#define AR_IO_UART1_IIR_FCR 0x80014108 -#pragma Aux_register(0x80014108, name=>"io_uart1_iir_fcr") - -// User extension aux register io_uart1_lcr -#define AR_IO_UART1_LCR 0x8001410c -#pragma Aux_register(0x8001410c, name=>"io_uart1_lcr") - -// User extension aux register io_uart1_mcr -#define AR_IO_UART1_MCR 0x80014110 -#pragma Aux_register(0x80014110, name=>"io_uart1_mcr") - -// User extension aux register io_uart1_lsr -#define AR_IO_UART1_LSR 0x80014114 -#pragma Aux_register(0x80014114, name=>"io_uart1_lsr") - -// User extension aux register io_uart1_msr -#define AR_IO_UART1_MSR 0x80014118 -#pragma Aux_register(0x80014118, name=>"io_uart1_msr") - -// User extension aux register io_uart1_usr -#define AR_IO_UART1_USR 0x8001417c -#pragma Aux_register(0x8001417c, name=>"io_uart1_usr") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_UART2_PRESENT 1 - -// User extension aux register io_uart2_clken -#define AR_IO_UART2_CLKEN 0x800142c0 -#pragma Aux_register(0x800142c0, name=>"io_uart2_clken") - -// User extension aux register io_uart2_rbr_thr_dll -#define AR_IO_UART2_RBR_THR_DLL 0x80014200 -#pragma Aux_register(0x80014200, name=>"io_uart2_rbr_thr_dll") - -// User extension aux register io_uart2_ier_dlh -#define AR_IO_UART2_IER_DLH 0x80014204 -#pragma Aux_register(0x80014204, name=>"io_uart2_ier_dlh") - -// User extension aux register io_uart2_iir_fcr -#define AR_IO_UART2_IIR_FCR 0x80014208 -#pragma Aux_register(0x80014208, name=>"io_uart2_iir_fcr") - -// User extension aux register io_uart2_lcr -#define AR_IO_UART2_LCR 0x8001420c -#pragma Aux_register(0x8001420c, name=>"io_uart2_lcr") - -// User extension aux register io_uart2_mcr -#define AR_IO_UART2_MCR 0x80014210 -#pragma Aux_register(0x80014210, name=>"io_uart2_mcr") - -// User extension aux register io_uart2_lsr -#define AR_IO_UART2_LSR 0x80014214 -#pragma Aux_register(0x80014214, name=>"io_uart2_lsr") - -// User extension aux register io_uart2_msr -#define AR_IO_UART2_MSR 0x80014218 -#pragma Aux_register(0x80014218, name=>"io_uart2_msr") - -// User extension aux register io_uart2_usr -#define AR_IO_UART2_USR 0x8001427c -#pragma Aux_register(0x8001427c, name=>"io_uart2_usr") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_UART3_PRESENT 1 - -// User extension aux register io_uart3_clken -#define AR_IO_UART3_CLKEN 0x800143c0 -#pragma Aux_register(0x800143c0, name=>"io_uart3_clken") - -// User extension aux register io_uart3_rbr_thr_dll -#define AR_IO_UART3_RBR_THR_DLL 0x80014300 -#pragma Aux_register(0x80014300, name=>"io_uart3_rbr_thr_dll") - -// User extension aux register io_uart3_ier_dlh -#define AR_IO_UART3_IER_DLH 0x80014304 -#pragma Aux_register(0x80014304, name=>"io_uart3_ier_dlh") - -// User extension aux register io_uart3_iir_fcr -#define AR_IO_UART3_IIR_FCR 0x80014308 -#pragma Aux_register(0x80014308, name=>"io_uart3_iir_fcr") - -// User extension aux register io_uart3_lcr -#define AR_IO_UART3_LCR 0x8001430c -#pragma Aux_register(0x8001430c, name=>"io_uart3_lcr") - -// User extension aux register io_uart3_mcr -#define AR_IO_UART3_MCR 0x80014310 -#pragma Aux_register(0x80014310, name=>"io_uart3_mcr") - -// User extension aux register io_uart3_lsr -#define AR_IO_UART3_LSR 0x80014314 -#pragma Aux_register(0x80014314, name=>"io_uart3_lsr") - -// User extension aux register io_uart3_msr -#define AR_IO_UART3_MSR 0x80014318 -#pragma Aux_register(0x80014318, name=>"io_uart3_msr") - -// User extension aux register io_uart3_usr -#define AR_IO_UART3_USR 0x8001437c -#pragma Aux_register(0x8001437c, name=>"io_uart3_usr") -#define APEX_COM_ARC_HARDWARE_SCSS_SUBSYS_BCR_PRESENT 1 - -// User extension aux register SUBSYS_BUILD -#define AR_SUBSYS_BUILD 0xf0 -#pragma Aux_register(0xf0, name=>"SUBSYS_BUILD") - -// User extension aux register SUBSYS_DSP_0_BUILD -#define AR_SUBSYS_DSP_0_BUILD 0xa00 -#pragma Aux_register(0xa00, name=>"SUBSYS_DSP_0_BUILD") - -// User extension aux register SUBSYS_DSP_0_CONFIG -#define AR_SUBSYS_DSP_0_CONFIG 0xa02 -#pragma Aux_register(0xa02, name=>"SUBSYS_DSP_0_CONFIG") - -// User extension aux register SUBSYS_IO_0_BUILD -#define AR_SUBSYS_IO_0_BUILD 0xa04 -#pragma Aux_register(0xa04, name=>"SUBSYS_IO_0_BUILD") - -// User extension aux register SUBSYS_IO_1_BUILD -#define AR_SUBSYS_IO_1_BUILD 0xa05 -#pragma Aux_register(0xa05, name=>"SUBSYS_IO_1_BUILD") - -// User extension aux register SUBSYS_IO_2_BUILD -#define AR_SUBSYS_IO_2_BUILD 0xa06 -#pragma Aux_register(0xa06, name=>"SUBSYS_IO_2_BUILD") - -// User extension aux register SUBSYS_UAUX_OFFSET -#define AR_SUBSYS_UAUX_OFFSET 0xa1e -#pragma Aux_register(0xa1e, name=>"SUBSYS_UAUX_OFFSET") - -// User extension aux register SUBSYS_APEX_OFFSET -#define AR_SUBSYS_APEX_OFFSET 0xa1f -#pragma Aux_register(0xa1f, name=>"SUBSYS_APEX_OFFSET") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_SPI_MST1_PRESENT 1 - -// User extension aux register io_spi_mst1_ctrlr0 -#define AR_IO_SPI_MST1_CTRLR0 0x80010100 -#pragma Aux_register(0x80010100, name=>"io_spi_mst1_ctrlr0") - -// User extension aux register io_spi_mst1_ctrlr1 -#define AR_IO_SPI_MST1_CTRLR1 0x80010101 -#pragma Aux_register(0x80010101, name=>"io_spi_mst1_ctrlr1") - -// User extension aux register io_spi_mst1_spien -#define AR_IO_SPI_MST1_SPIEN 0x80010102 -#pragma Aux_register(0x80010102, name=>"io_spi_mst1_spien") - -// User extension aux register io_spi_mst1_ser -#define AR_IO_SPI_MST1_SER 0x80010104 -#pragma Aux_register(0x80010104, name=>"io_spi_mst1_ser") - -// User extension aux register io_spi_mst1_baudr -#define AR_IO_SPI_MST1_BAUDR 0x80010105 -#pragma Aux_register(0x80010105, name=>"io_spi_mst1_baudr") - -// User extension aux register io_spi_mst1_txftlr -#define AR_IO_SPI_MST1_TXFTLR 0x80010106 -#pragma Aux_register(0x80010106, name=>"io_spi_mst1_txftlr") - -// User extension aux register io_spi_mst1_rxftlr -#define AR_IO_SPI_MST1_RXFTLR 0x80010107 -#pragma Aux_register(0x80010107, name=>"io_spi_mst1_rxftlr") - -// User extension aux register io_spi_mst1_txflr -#define AR_IO_SPI_MST1_TXFLR 0x80010108 -#pragma Aux_register(0x80010108, name=>"io_spi_mst1_txflr") - -// User extension aux register io_spi_mst1_rxflr -#define AR_IO_SPI_MST1_RXFLR 0x80010109 -#pragma Aux_register(0x80010109, name=>"io_spi_mst1_rxflr") - -// User extension aux register io_spi_mst1_sr -#define AR_IO_SPI_MST1_SR 0x8001010a -#pragma Aux_register(0x8001010a, name=>"io_spi_mst1_sr") - -// User extension aux register io_spi_mst1_imr -#define AR_IO_SPI_MST1_IMR 0x8001010b -#pragma Aux_register(0x8001010b, name=>"io_spi_mst1_imr") - -// User extension aux register io_spi_mst1_isr -#define AR_IO_SPI_MST1_ISR 0x8001010c -#pragma Aux_register(0x8001010c, name=>"io_spi_mst1_isr") - -// User extension aux register io_spi_mst1_risr -#define AR_IO_SPI_MST1_RISR 0x8001010d -#pragma Aux_register(0x8001010d, name=>"io_spi_mst1_risr") - -// User extension aux register io_spi_mst1_txoicr -#define AR_IO_SPI_MST1_TXOICR 0x8001010e -#pragma Aux_register(0x8001010e, name=>"io_spi_mst1_txoicr") - -// User extension aux register io_spi_mst1_rxoicr -#define AR_IO_SPI_MST1_RXOICR 0x8001010f -#pragma Aux_register(0x8001010f, name=>"io_spi_mst1_rxoicr") - -// User extension aux register io_spi_mst1_rxuicr -#define AR_IO_SPI_MST1_RXUICR 0x80010110 -#pragma Aux_register(0x80010110, name=>"io_spi_mst1_rxuicr") - -// User extension aux register io_spi_mst1_icr -#define AR_IO_SPI_MST1_ICR 0x80010112 -#pragma Aux_register(0x80010112, name=>"io_spi_mst1_icr") - -// User extension aux register io_spi_mst1_clken -#define AR_IO_SPI_MST1_CLKEN 0x80010116 -#pragma Aux_register(0x80010116, name=>"io_spi_mst1_clken") - -// User extension aux register io_spi_mst1_dr -#define AR_IO_SPI_MST1_DR 0x80010118 -#pragma Aux_register(0x80010118, name=>"io_spi_mst1_dr") - -// User extension aux register io_spi_mst1_rx_sample_dly -#define AR_IO_SPI_MST1_RX_SAMPLE_DLY 0x8001013c -#pragma Aux_register(0x8001013c, name=>"io_spi_mst1_rx_sample_dly") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_SPI_MST2_PRESENT 1 - -// User extension aux register io_spi_mst2_ctrlr0 -#define AR_IO_SPI_MST2_CTRLR0 0x80010200 -#pragma Aux_register(0x80010200, name=>"io_spi_mst2_ctrlr0") - -// User extension aux register io_spi_mst2_ctrlr1 -#define AR_IO_SPI_MST2_CTRLR1 0x80010201 -#pragma Aux_register(0x80010201, name=>"io_spi_mst2_ctrlr1") - -// User extension aux register io_spi_mst2_spien -#define AR_IO_SPI_MST2_SPIEN 0x80010202 -#pragma Aux_register(0x80010202, name=>"io_spi_mst2_spien") - -// User extension aux register io_spi_mst2_ser -#define AR_IO_SPI_MST2_SER 0x80010204 -#pragma Aux_register(0x80010204, name=>"io_spi_mst2_ser") - -// User extension aux register io_spi_mst2_baudr -#define AR_IO_SPI_MST2_BAUDR 0x80010205 -#pragma Aux_register(0x80010205, name=>"io_spi_mst2_baudr") - -// User extension aux register io_spi_mst2_txftlr -#define AR_IO_SPI_MST2_TXFTLR 0x80010206 -#pragma Aux_register(0x80010206, name=>"io_spi_mst2_txftlr") - -// User extension aux register io_spi_mst2_rxftlr -#define AR_IO_SPI_MST2_RXFTLR 0x80010207 -#pragma Aux_register(0x80010207, name=>"io_spi_mst2_rxftlr") - -// User extension aux register io_spi_mst2_txflr -#define AR_IO_SPI_MST2_TXFLR 0x80010208 -#pragma Aux_register(0x80010208, name=>"io_spi_mst2_txflr") - -// User extension aux register io_spi_mst2_rxflr -#define AR_IO_SPI_MST2_RXFLR 0x80010209 -#pragma Aux_register(0x80010209, name=>"io_spi_mst2_rxflr") - -// User extension aux register io_spi_mst2_sr -#define AR_IO_SPI_MST2_SR 0x8001020a -#pragma Aux_register(0x8001020a, name=>"io_spi_mst2_sr") - -// User extension aux register io_spi_mst2_imr -#define AR_IO_SPI_MST2_IMR 0x8001020b -#pragma Aux_register(0x8001020b, name=>"io_spi_mst2_imr") - -// User extension aux register io_spi_mst2_isr -#define AR_IO_SPI_MST2_ISR 0x8001020c -#pragma Aux_register(0x8001020c, name=>"io_spi_mst2_isr") - -// User extension aux register io_spi_mst2_risr -#define AR_IO_SPI_MST2_RISR 0x8001020d -#pragma Aux_register(0x8001020d, name=>"io_spi_mst2_risr") - -// User extension aux register io_spi_mst2_txoicr -#define AR_IO_SPI_MST2_TXOICR 0x8001020e -#pragma Aux_register(0x8001020e, name=>"io_spi_mst2_txoicr") - -// User extension aux register io_spi_mst2_rxoicr -#define AR_IO_SPI_MST2_RXOICR 0x8001020f -#pragma Aux_register(0x8001020f, name=>"io_spi_mst2_rxoicr") - -// User extension aux register io_spi_mst2_rxuicr -#define AR_IO_SPI_MST2_RXUICR 0x80010210 -#pragma Aux_register(0x80010210, name=>"io_spi_mst2_rxuicr") - -// User extension aux register io_spi_mst2_icr -#define AR_IO_SPI_MST2_ICR 0x80010212 -#pragma Aux_register(0x80010212, name=>"io_spi_mst2_icr") - -// User extension aux register io_spi_mst2_clken -#define AR_IO_SPI_MST2_CLKEN 0x80010216 -#pragma Aux_register(0x80010216, name=>"io_spi_mst2_clken") - -// User extension aux register io_spi_mst2_dr -#define AR_IO_SPI_MST2_DR 0x80010218 -#pragma Aux_register(0x80010218, name=>"io_spi_mst2_dr") - -// User extension aux register io_spi_mst2_rx_sample_dly -#define AR_IO_SPI_MST2_RX_SAMPLE_DLY 0x8001023c -#pragma Aux_register(0x8001023c, name=>"io_spi_mst2_rx_sample_dly") -#define APEX_COM_ARC_HARDWARE_FLOATING_POINT_UNIT_FPU_PRESENT 1 - -// User extension aux register fpu_build -#define AR_FPU_BUILD 0xc8 -#pragma Aux_register(0xc8, name=>"fpu_build") - -// User extension aux register fpu_ctrl -#define AR_FPU_CTRL 0x300 -#pragma Aux_register(0x300, name=>"fpu_ctrl") - -// User extension aux register fpu_status -#define AR_FPU_STATUS 0x301 -#pragma Aux_register(0x301, name=>"fpu_status") - -// User extension instruction fsmadd -extern int fsmadd(int,int); -#pragma intrinsic(fsmadd,opcode=>6,sub_opcode=>5, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fsmsub -extern int fsmsub(int,int); -#pragma intrinsic(fsmsub,opcode=>6,sub_opcode=>6, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fsmul -extern int fsmul(int,int); -#pragma intrinsic(fsmul,opcode=>6,sub_opcode=>0, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fsadd -extern int fsadd(int,int); -#pragma intrinsic(fsadd,opcode=>6,sub_opcode=>1, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fssub -extern int fssub(int,int); -#pragma intrinsic(fssub,opcode=>6,sub_opcode=>2, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fcvt32 -extern int fcvt32(int,int); -#pragma intrinsic(fcvt32,opcode=>6,sub_opcode=>8, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fsdiv -extern int fsdiv(int,int); -#pragma intrinsic(fsdiv,opcode=>6,sub_opcode=>7, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fscmp -extern int fscmp(int,int); -#pragma intrinsic(fscmp,opcode=>6,sub_opcode=>3, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fscmp -extern int fscmp_f(int,int); -#pragma intrinsic(fscmp_f,opcode=>6,sub_opcode=>3, set_flags => 1, flags => "zncv", effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fscmpf -extern int fscmpf(int,int); -#pragma intrinsic(fscmpf,opcode=>6,sub_opcode=>4, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fscmpf -extern int fscmpf_f(int,int); -#pragma intrinsic(fscmpf_f,opcode=>6,sub_opcode=>4, set_flags => 1, flags => "zncv", effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fssqrt -extern int fssqrt(int); -#pragma intrinsic(fssqrt,opcode=>6,sub_opcode=>0, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") -#define APEX_COM_ARC_HARDWARE_FLOATING_POINT_UNIT_FPU_DP_ASSIST_PRESENT 1 - -// User extension aux register aux_dpfp1l -#define AR_AUX_DPFP1L 0x302 -#pragma Aux_register(0x302, name=>"aux_dpfp1l") - -// User extension aux register aux_dpfp1h -#define AR_AUX_DPFP1H 0x303 -#pragma Aux_register(0x303, name=>"aux_dpfp1h") - -// User extension aux register aux_dpfp2l -#define AR_AUX_DPFP2L 0x304 -#pragma Aux_register(0x304, name=>"aux_dpfp2l") - -// User extension aux register aux_dpfp2h -#define AR_AUX_DPFP2H 0x305 -#pragma Aux_register(0x305, name=>"aux_dpfp2h") - -// User extension instruction dmulh11 -extern int dmulh11(int,int); -#pragma intrinsic(dmulh11,opcode=>6,sub_opcode=>48,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh11 -extern int dmulh11_f(int,int); -#pragma intrinsic(dmulh11_f,opcode=>6,sub_opcode=>48, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh12 -extern int dmulh12(int,int); -#pragma intrinsic(dmulh12,opcode=>6,sub_opcode=>49,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh12 -extern int dmulh12_f(int,int); -#pragma intrinsic(dmulh12_f,opcode=>6,sub_opcode=>49, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh21 -extern int dmulh21(int,int); -#pragma intrinsic(dmulh21,opcode=>6,sub_opcode=>50,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh21 -extern int dmulh21_f(int,int); -#pragma intrinsic(dmulh21_f,opcode=>6,sub_opcode=>50, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh22 -extern int dmulh22(int,int); -#pragma intrinsic(dmulh22,opcode=>6,sub_opcode=>51,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh22 -extern int dmulh22_f(int,int); -#pragma intrinsic(dmulh22_f,opcode=>6,sub_opcode=>51, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh11 -extern int daddh11(int,int); -#pragma intrinsic(daddh11,opcode=>6,sub_opcode=>52,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh11 -extern int daddh11_f(int,int); -#pragma intrinsic(daddh11_f,opcode=>6,sub_opcode=>52, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh12 -extern int daddh12(int,int); -#pragma intrinsic(daddh12,opcode=>6,sub_opcode=>53,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh12 -extern int daddh12_f(int,int); -#pragma intrinsic(daddh12_f,opcode=>6,sub_opcode=>53, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh21 -extern int daddh21(int,int); -#pragma intrinsic(daddh21,opcode=>6,sub_opcode=>54,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh21 -extern int daddh21_f(int,int); -#pragma intrinsic(daddh21_f,opcode=>6,sub_opcode=>54, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh22 -extern int daddh22(int,int); -#pragma intrinsic(daddh22,opcode=>6,sub_opcode=>55,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh22 -extern int daddh22_f(int,int); -#pragma intrinsic(daddh22_f,opcode=>6,sub_opcode=>55, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh11 -extern int dsubh11(int,int); -#pragma intrinsic(dsubh11,opcode=>6,sub_opcode=>56,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh11 -extern int dsubh11_f(int,int); -#pragma intrinsic(dsubh11_f,opcode=>6,sub_opcode=>56, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh12 -extern int dsubh12(int,int); -#pragma intrinsic(dsubh12,opcode=>6,sub_opcode=>57,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh12 -extern int dsubh12_f(int,int); -#pragma intrinsic(dsubh12_f,opcode=>6,sub_opcode=>57, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh21 -extern int dsubh21(int,int); -#pragma intrinsic(dsubh21,opcode=>6,sub_opcode=>58,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh21 -extern int dsubh21_f(int,int); -#pragma intrinsic(dsubh21_f,opcode=>6,sub_opcode=>58, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh22 -extern int dsubh22(int,int); -#pragma intrinsic(dsubh22,opcode=>6,sub_opcode=>59,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh22 -extern int dsubh22_f(int,int); -#pragma intrinsic(dsubh22_f,opcode=>6,sub_opcode=>59, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dexcl1 -extern int dexcl1(int,int); -#pragma intrinsic(dexcl1,opcode=>6,sub_opcode=>60, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dexcl2 -extern int dexcl2(int,int); -#pragma intrinsic(dexcl2,opcode=>6,sub_opcode=>61, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - - -#endif - - diff --git a/board/emsdp/rev2/configs/em6_scss/core_hardware.h b/board/emsdp/rev2/configs/em6_scss/core_hardware.h deleted file mode 100644 index 287716cb2..000000000 --- a/board/emsdp/rev2/configs/em6_scss/core_hardware.h +++ /dev/null @@ -1,71 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------- */ -#ifndef _CORE_HARDWARE_H_ -#define _CORE_HARDWARE_H_ - -#define EMSDP_SPI0_INTR (84) -#define EMSDP_SPI1_INTR (85) -#define EMSDP_GPIO_INTR0 (86) -#define EMSDP_GPIO_INTR1 (87) -#define EMSDP_GPIO_INTR2 (88) -#define EMSDP_GPIO_INTR3 (89) -#define EMSDP_TIMER0_INTR0 (90) -#define EMSDP_TIMER0_INTR1 (91) -#define EMSDP_TIMER0_INTR2 (92) -#define EMSDP_TIMER0_INTR3 (93) -#define EMSDP_TIMER0_INTR4 (94) -#define EMSDP_TIMER0_INTR5 (95) -#define EMSDP_TIMER0_INTR6 (96) -#define EMSDP_TIMER0_INTR7 (97) -#define EMSDP_TIMER1_INTR0 (98) -#define EMSDP_TIMER1_INTR1 (99) -#define EMSDP_TIMER1_INTR2 (100) -#define EMSDP_TIMER1_INTR3 (101) -#define EMSDP_TIMER1_INTR4 (102) -#define EMSDP_TIMER1_INTR5 (103) -#define EMSDP_TIMER1_INTR6 (104) -#define EMSDP_TIMER1_INTR7 (105) -#define EMSDP_UART_INTR (106) -#define EMSDP_WDT_INTR (107) -#define EMSDP_DBG_UART_INTR (108) -#define EMSDP_SDIO_INTR (109) -#define EMSDP_REDPINE_SPI_INTR (110) -#define EMSDP_REDPINE_HOST_WAKEUP (111) -#define EMSDP_NIST_TRNG_INTR (112) - -//EMSDP Peripheral Subsystem DMA assignments -#define UART_DMA_TX (10) -#define UART_DMA_RX (11) -#define REDPINE_SPI_DMA_TX (12) -#define REDPINE_SPI_DMA_RX (13) -#define FLASH_SPI_DMA_TX (14) -#define FLASH_SPI_DMA_RX (15) - -#endif /* _CORE_HARDWARE_H_ */ \ No newline at end of file diff --git a/board/emsdp/rev2/configs/em6_scss/dsp_config.h b/board/emsdp/rev2/configs/em6_scss/dsp_config.h deleted file mode 100644 index 3f7f2a312..000000000 --- a/board/emsdp/rev2/configs/em6_scss/dsp_config.h +++ /dev/null @@ -1,27 +0,0 @@ - -/* **** DO NOT EDIT - this file is generated by ARChitect2 **** - * - * Description: Header file declaring the compiler extensions for eia components - */ - -#ifndef _dsp_config_H_ -#define _dsp_config_H_ - - -#define DSP_MAC_PRESENT -#define DSP_MAC_IO_FW (15) -#define DSP_MAC_ACC_SIZE (min) -#define DSP_MAC_Z_WRAP (floor) -#define DSP_ABS_PRESENT -#define DSP_ADD_PRESENT -#define DSP_MULT_PRESENT -#define DSP_MULV_PRESENT -#define DSP_NEGATE_PRESENT -#define DSP_SHIFT_PRESENT -#define DSP_SINCOS_PRESENT -#define DSP_SQRT_PRESENT -#define DSP_SUB_PRESENT - -#endif - - diff --git a/board/emsdp/rev2/configs/em6_scss/io_config.h b/board/emsdp/rev2/configs/em6_scss/io_config.h deleted file mode 100644 index 068656a2e..000000000 --- a/board/emsdp/rev2/configs/em6_scss/io_config.h +++ /dev/null @@ -1,116 +0,0 @@ - -/* **** DO NOT EDIT - this file is generated by ARChitect2 **** - * - * Description: Header file declaring the compiler extensions for eia components - */ - -#ifndef _io_config_H_ -#define _io_config_H_ - - -#define DMAC_INT_BASE (20) -#define DMAC_ERR_BASE (DMAC_INT_BASE + DMAC_CHAN_CNT) -#define DMAC_CHAN_CNT (16) -#define DMAC_MEM_CHAN_CNT (16) -#define DMAC_AUX_CHAN_CNT (0) -#define IO_I2C_SLV0_PRESENT -#define IO_I2C_SLV0_FS (2) -#define IO_I2C_SLV0_DMA_TX (2) -#define IO_I2C_SLV0_DMA_RX (3) -#define IO_I2C_SLV0_INT_ERR (50) -#define IO_I2C_SLV0_INT_RX_AVAIL (51) -#define IO_I2C_SLV0_INT_TX_REQ (52) -#define IO_I2C_SLV0_INT_RD_REQ (53) -#define IO_I2C_SLV0_INT_STOP_DET (54) -#define IO_I2C_SLV0_INT_RESTART_DET (55) -#define IO_SPI_MST0_PRESENT -#define IO_SPI_MST0_FS (16) -#define IO_SPI_MST0_MAX_XFER_SIZE (16) -#define IO_SPI_MST0_DMA_TX (4) -#define IO_SPI_MST0_DMA_RX (5) -#define IO_SPI_MST0_INT_ERR (64) -#define IO_SPI_MST0_INT_RX_AVAIL (65) -#define IO_SPI_MST0_INT_TX_REQ (66) -#define IO_SPI_MST0_INT_IDLE (67) -#define IO_SPI_SLV0_PRESENT -#define IO_SPI_SLV0_FS (2) -#define IO_SPI_SLV0_MAX_XFER_SIZE (16) -#define IO_SPI_SLV0_DMA_TX (8) -#define IO_SPI_SLV0_DMA_RX (9) -#define IO_SPI_SLV0_INT_ERR (76) -#define IO_SPI_SLV0_INT_RX_AVAIL (77) -#define IO_SPI_SLV0_INT_TX_REQ (78) -#define IO_SPI_SLV0_INT_IDLE (79) -#define IO_I2C_MST0_PRESENT -#define IO_I2C_MST0_FS (16) -#define IO_I2C_MST0_DMA_TX (0) -#define IO_I2C_MST0_DMA_RX (1) -#define IO_I2C_MST0_INT_ERR (38) -#define IO_I2C_MST0_INT_RX_AVAIL (39) -#define IO_I2C_MST0_INT_TX_REQ (40) -#define IO_I2C_MST0_INT_STOP_DET (41) -#define IO_GPIO0_PRESENT -#define IO_GPIO0_INT_INTR_FLAG (17) -#define IO_GPIO0_DEBOUNCE (1) -#define IO_UART0_PRESENT -#define IO_UART0_FS (0) -#define IO_UART0_INTR (80) -#define IO_PWM0_PRESENT -#define IO_PWM0_COUNTER_WIDTH (16) -#define IO_PWM0_INT_NEW_NPERIODS (56) -#define IO_PWM0_INT_UPD_MISSED (57) -#define IO_PWM0_INT_TRG (58) -#define IO_PWM0_INT_FAULT (59) -#define IO_SPI_MST1_PRESENT -#define IO_SPI_MST1_FS (16) -#define IO_SPI_MST1_MAX_XFER_SIZE (16) -#define IO_SPI_MST1_DMA_TX (6) -#define IO_SPI_MST1_DMA_RX (7) -#define IO_SPI_MST1_INT_ERR (68) -#define IO_SPI_MST1_INT_RX_AVAIL (69) -#define IO_SPI_MST1_INT_TX_REQ (70) -#define IO_SPI_MST1_INT_IDLE (71) -#define IO_I2C_MST1_PRESENT -#define IO_I2C_MST1_FS (16) -#define IO_I2C_MST1_INT_ERR (42) -#define IO_I2C_MST1_INT_RX_AVAIL (43) -#define IO_I2C_MST1_INT_TX_REQ (44) -#define IO_I2C_MST1_INT_STOP_DET (45) -#define IO_GPIO1_PRESENT -#define IO_GPIO1_INT_INTR_FLAG (19) -#define IO_GPIO1_DEBOUNCE (1) -#define IO_UART1_PRESENT -#define IO_UART1_FS (0) -#define IO_UART1_INTR (81) -#define IO_PWM1_PRESENT -#define IO_PWM1_COUNTER_WIDTH (16) -#define IO_PWM1_INT_NEW_NPERIODS (60) -#define IO_PWM1_INT_UPD_MISSED (61) -#define IO_PWM1_INT_TRG (62) -#define IO_PWM1_INT_FAULT (63) -#define IO_SPI_MST2_PRESENT -#define IO_SPI_MST2_FS (16) -#define IO_SPI_MST2_MAX_XFER_SIZE (16) -#define IO_SPI_MST2_INT_ERR (72) -#define IO_SPI_MST2_INT_RX_AVAIL (73) -#define IO_SPI_MST2_INT_TX_REQ (74) -#define IO_SPI_MST2_INT_IDLE (75) -#define IO_I2C_MST2_PRESENT -#define IO_I2C_MST2_FS (16) -#define IO_I2C_MST2_INT_ERR (46) -#define IO_I2C_MST2_INT_RX_AVAIL (47) -#define IO_I2C_MST2_INT_TX_REQ (48) -#define IO_I2C_MST2_INT_STOP_DET (49) -#define IO_GPIO2_PRESENT -#define IO_GPIO2_INT_INTR_FLAG (37) -#define IO_GPIO2_DEBOUNCE (1) -#define IO_UART2_PRESENT -#define IO_UART2_FS (0) -#define IO_UART2_INTR (82) -#define IO_UART3_PRESENT -#define IO_UART3_FS (0) -#define IO_UART3_INTR (83) - -#endif - - diff --git a/board/emsdp/rev2/configs/em6_scss/tcf/em6_scss.tcf b/board/emsdp/rev2/configs/em6_scss/tcf/em6_scss.tcf deleted file mode 100644 index 4364cad15..000000000 --- a/board/emsdp/rev2/configs/em6_scss/tcf/em6_scss.tcf +++ /dev/null @@ -1,4940 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - -# -# option 16/L32/U32 Instructions -# ------ ---------- --------------------- -# -# none -/-/- None -# wlh1 1/1/1 MPYW/U, MPY/U, MPYH/U -# wlh2 2/2/2 MPYW/U, MPY/U, MPYH/U -# wlh3 2/3/3 MPYW/U, MPY/U, MPYH/U -# wlh4 2/4/5 MPYW/U, MPY/U, MPYH/U -# wlh5 5/9/9 MPYW/U, MPY/U, MPYH/U -# -# --mpy_option wlh2 - -# code_protection --- The ARC EM architecture divides the memory into 16 regions, which can be protected individually. This feature adds a 16-bit input to the processor core, one bit per region. When the protect bit is set, the processor disables any load or store to the corresponding region. An attempt to access a protected region raises an EV_ProtV exception. --code_protection false - -# stack_checking --- Stack checking is a mechanism for checking stack accesses and raising an exception when a stack overflow or underflow is detected. --stack_checking true - -# unaligned_option --- This enables unaligned loads and stores. --unaligned_option true - -# intvbase_preset --- This sets the interrupt vector base configuration register, VECBASE_AC_BUILD. The vector base address is aligned to a 1KB boundary, so the required address value should be divided by 1K (i.e. do not include the lower 10 bits). On reset, this register is loaded into the interrupt vector base address register, INT_VECTOR_BASE. --intvbase_preset 0x0 - -# intvbase_preset_s --- This sets the secure interrupt vector base configuration register, VECBASE_AC_BUILD. The vector base address is aligned to a 1KB boundary, so the required address value should be divided by 1K (i.e. do not include the lower 10 bits). On reset, this register is loaded into the interrupt vector base address register, INT_VECTOR_BASE_S.This is effective only when 2+2 mode is enabled. --intvbase_preset_s 0x0 - -# intvbase_ext --- Set this option to drive the upper 22 bits of the interrupt base vector externally, into signal intvbase_in. --intvbase_ext false - -# nmi_option --- add Non-maskable external exception support --nmi_option false - -# rgf_impl --- This defines whether the register file is implemented using flip-flops, or with a hard macro. --rgf_impl flip_flops - -# rgf_num_regs --- This defines the size (in 32b register) of the processor register file. --rgf_num_regs 32 - -# rgf_wr_ports --- This defines the number of write ports on the register file. --rgf_wr_ports 2 - -# rgf_num_banks --- Dual register banks are useful if Fast IRQ has been configured, but may be selected even if not. --rgf_num_banks 2 - -# rgf_banked_regs --- This selects the number of registers that are replicated in the second register-file bank. --rgf_banked_regs 32 - -# turbo_boost --- This enables the Turbo Boost synthesis option. By enabling this option, the achievable clock frequency is increased, but at the cost of an additional cycle latency on branch instructions. --turbo_boost true - -# infer_alu_adder --- infer: datapath is described as behavioral code: A + B -# instantiate: datapath is instantiated as a detailed multi-stage code of a carry-lookahead adder. It is generally preferable to use the infer option and add directives for your target synthesizer. --infer_alu_adder infer - -# infer_mpy_wtree --- infer: datapath is described as behavioral code: A * B (applies to only wlh3, wlh4 and wlh5 designs) -# instantiate: datapath is instantiated as a detailed multi-stage code of a Wallace Tree multiplier It is generally preferable to use the infer option and add directives for your target synthesizer. --infer_mpy_wtree instantiate - -# scantest_ram_bypass_mux --- This mux is used to make logic trapped between flops and memory (aka shadow logic) to be covered by scantest without requiring advanced sequential ATPG on the memory to be applied. Will add delay to functional access time --scantest_ram_bypass_mux false - -# logic_bist --- This option will OR LBIST_EN with test_mode --logic_bist false - -# power_domains --- Adds three separate power domains to the core, and propagates power-gate control signals to the top level of the core. Also generates UPF constraints and commands in the low-power scripts --power_domains false - -# dvfs --- Adds logic to the core to allow dynamic controlling of voltage and frequency and propagates the associated control signals to the top level of core --dvfs false - -# voltage_domains --- Creates a voltage domain split between RAM and std cell parts to support Ultra Low Voltage on cells and generates UPF constraints --voltage_domains false - -# mem_bus_option --- The core supports two bus protocols for accessing external memory: AHB & AHB-Lite. AHB-Lite-single means instruction fetch and data access share a single AHB-Lite port. AHB-Lite-dual means separate AHB-Lite port for each initiator if present. --mem_bus_option AHB - -# mem_bus_reg_interface --- Specifies whether the memory bus interface is registered. --mem_bus_reg_interface true - -# dmi_burst_option --- This will enable high-throughput burst support on the DMI slave interfaces. By enabling this option, the peak DMI read throughput goes from 1 word per 3 cycles to N words per N+2 cycles, in which N is the AHB burst lengthDMI write throughput goes from 1 word per 3 cycles to 1 word per cycle. --dmi_burst_option true - -# has_dmp_peripheral --- This option enables the redirection of load/store accesses to one segment (1/16) of the addressable space to a dedicated peripheral bus. This offers high system integration and reduces overall system cost. --has_dmp_peripheral true - -# per0_base --- This option specifies the memory region assignment for this peripheral aperture --per0_base 15 - -# per0_limit --- This option specifies the end of this peripheral aperture --per0_limit 0 - -# per_bus_option --- The core supports one bus protocol for accessing the peripheral space, when enabled: AHB-Lite. --per_bus_option AHB-Lite - -# per_bus_reg_interface --- Specifies whether the peripheral bus interface is registered. --per_bus_reg_interface true - -# clock_gating --- This enables the insertion of architectural clock gate elements in the design. By enabling this option, the clocks to various parts of the design will be disabled when the logic they drive is not in use to save power. --clock_gating false - -# back_compat --- This enables the addition of rst_a input in the clkgate module to support backward compatibility with the older EM and Subsystem releases. --back_compat true - -# byte_parity --- If parity protection on the CCMs or Cache is configured, this option enables parity protection on a per-byte basis. Otherwise, parity is per word basis --byte_parity false - -# prot_pipelined --- Check the box if CCM memories are configured for ECC, and you want single-bit errors to be corrected, written back to memory, and re-fetched. When unchecked, single bit errors are corrected when read from memory, but the offending memory location itself is not corrected with a writeback, no influence on Cache protection --prot_pipelined true - -# cct_test_ena --- When ECC is configured, this option enables single bit error injection in CCT RAM models to demonstrate ECC protection on the RAMs. When enabled, the RAM models can only be used in HDL CCT simulation (no xCAM support) and are not intended for use in SoC level integration. --cct_test_ena false - -# err_prot_ehce --- Enabled enhanced ECC architecture for CCM. Instruction fetch with single bit error is not replayed; ecc cac modules are shared to reduce area and timing opt. --err_prot_ehce false - - -######## Actionpoints --- com.arc.hardware.Actionpoints.1_0 ######## - -# Create Actionpoints --create com.arc.hardware.Actionpoints.1_0 System.CPUisle.ARCv2EM.Actionpoints - -# num_actionpoints --- This is the number of trigger events available. --num_actionpoints 8 - -# aps_feature --- Selects Actionpoint feature set --aps_feature min - - -######## DCCM --- com.arc.hardware.DCCM.1_0 ######## - -# Create DCCM --create com.arc.hardware.DCCM.1_0 System.CPUisle.ARCv2EM.DCCM - -# dccm_size --- This defines the size of the Data Closely Coupled Memory (DCCM) in bytes --dccm_size 131072 - -# dccm_base --- Sets the initial memory region assignment for DCCM --dccm_base 8 - -# dccm_interleave --- Split DCCM into even/odd memory banks. --dccm_interleave false - -# dccm_prot --- Specifies the type of protection built for the DCCM. --dccm_prot None - -# dccm_prot_level --- Specifies the level protection. --dccm_prot_level Data_Only - -# dccm_prot_exceptions --- When the core is configured with ECC or Parity, cause exception generation hardware to be created for uncorrectable errors detected on the DCCM --dccm_prot_exceptions true - -# dccm_sec_lvl --- Specifies the level of secure DCCM. --dccm_sec_lvl Non_Secure - -# dccm_dmi --- This enables external access through a DMI (direct memory interface) port. --dccm_dmi true - - -######## DMA Controller --- com.arc.hardware.DMA_Controller.1_0 ######## - -# Create DMA Controller --create com.arc.hardware.DMA_Controller.1_0 "System.CPUisle.ARCv2EM.DMA Controller" - -# dmac_channels --- This options specifies the number of DMA channels implemented in the DMA controller --dmac_channels 16 - -# dmac_fifo_depth --- This option specifies the DMA transfer FIFO depth in 32b words. --dmac_fifo_depth 2 - -# dmac_int_config --- None: the DMA controller cannot raise an interrupt -# Single-External: single done and single error interrupt signal for all DMA channels, and the interrupt signals are routed to a port at the top of the EM logical hierarchy -# Multiple-External: each DMA channel can be configured to raise separate (per-channel) done and error interrupts, and the interrupt signals are routed to ports at the top of the EM logical hierarchy -# Single-Internal: single done and single error interrupt signals for all DMA channels, and the interrupt signals are internal to the EM core -# Multiple-Internal: each DMA channel can be configured to raise separate (per-channel) done and error interrupts, and the interrupt signals are internal to the EM core --dmac_int_config Multiple-Internal - -# dmac_separate_error_interrupts --- This specifies whether there is a separate error interrupt per DMA channel, or just one. --dmac_separate_error_interrupts false - -# dmac_registers --- This option defines the number of DMA channels with their registers located in auxiliary space. --dmac_registers 0 - -# dmac_mem_if --- This option specifies whether the DMA controller system memory interface is integrated into the existing EM system memory interfaces or has its own interface. --dmac_mem_if integrated - -# dmac_per_if --- Internal vs DW peripheral interface. Specify (in hex) which channels have the DW interface, where bit 0 corresponds to DMA channel 0, bit 1 for DMA channel 1, etc. -# Example: 4 channel DMA controller where -dmac_per_if is set to 0x9 = DMA Channels 0 and 3 configured with the DW req interface, DMA Channels 1 and 2 configured with the internal req interface. --dmac_per_if 0xfc00 - - -######## Data Cache --- com.arc.hardware.Data_Cache.1_0 ######## - -# Create Data Cache --create com.arc.hardware.Data_Cache.1_0 "System.CPUisle.ARCv2EM.Data Cache" - -# dc_size --- This defines the total size of the Data Cache in bytes. --dc_size 16384 - -# dc_ways --- This defines the number of cache ways. --dc_ways 2 - -# dc_bsize --- This defines the cache line length in bytes. --dc_bsize 32 - -# dc_feature_level --- Feature Level, indicates locking and debug feature level 00 = Basic cache, with no locking or debug features 01 = Lock and flush features supported 10 = Lock, flush and advanced debug features supported 11 = Reserved --dc_feature_level 2 - -# dc_uncached_region --- Enable an uncached region defined by aux reg --dc_uncached_region false - -# dc_prot --- Specifies the type of protection built for DCACHE. --dc_prot None - -# dc_prot_level --- Specifies the level of protection. --dc_prot_level Data_Only - -# dc_prot_exceptions --- Builds exception generation hardware for uncorrectable (fatal) errors detected on DCACHE. --dc_prot_exceptions true - - -######## Debug Interface --- com.arc.hardware.Debug_Interface.1_0 ######## - -# Create Debug Interface --create com.arc.hardware.Debug_Interface.1_0 "System.CPUisle.ARCv2EM.Debug Interface" - -# dbg_en_option --- Adds an enable pin to the existing debug interface --dbg_en_option false - -# secure_debug --- This enables secure debug feature --secure_debug false - -# scdbg_aux_unlk --- An internal demo module will be included when enable --scdbg_aux_unlk false - -# dbg_apb_option --- Adds an additional APB debug port alongside the BVCI one --dbg_apb_option false - - -######## Floating-point unit --- com.arc.hardware.Floating_point_unit.1_0 ######## - -# Create Floating-point unit --create com.arc.hardware.Floating_point_unit.1_0 "System.CPUisle.ARCv2EM.Floating-point unit" - -# fpu_dp_assist --- This enables double-precision acceleration instructions. --fpu_dp_assist true - -# fpu_fma_option --- This enables the fused multiply-add & multiply-subtract instructions. --fpu_fma_option true - -# fpu_mas_cycles --- Make mul/add/sub multicycle to achieve a higher clock speed. --fpu_mas_cycles 2 - -# fpu_pipe_impl --- FPU pipelined implementation --fpu_pipe_impl true - -# fpu_div_option --- This enables divide & square-root acceleration --fpu_div_option true - -# fpu_div_cycles --- Controls div/sqrt implementation. --fpu_div_cycles 17 - - -######## Memory Protection Unit --- com.arc.hardware.Memory_Protection_Unit.1_0 ######## - -# Create Memory Protection Unit --create com.arc.hardware.Memory_Protection_Unit.1_0 "System.CPUisle.ARCv2EM.Memory Protection Unit" - -# mpu_num_regions --- Number of configured memory regions. --mpu_num_regions 16 - -# mpu_32b --- Set the minimal region size to be 32 byte instead of 2KB. --mpu_32b false - -# mpu_sid_option --- It will enable SID support in Secure Shield --mpu_sid_option false - - -######## ICCM0 --- com.arc.hardware.ICCM0.1_0 ######## - -# Create ICCM0 --create com.arc.hardware.ICCM0.1_0 System.CPUisle.ARCv2EM.ICCM0 - -# iccm0_size --- This defines the size of ICCM0 in bytes.This ICCM has 0 wait states. --iccm0_size 131072 - -# iccm0_base --- Sets the initial memory region assignment for ICCM0 --iccm0_base 6 - -# iccm0_wide --- Creates ICCM0 as 64b memory to reduce accesses. --iccm0_wide false - -# iccm0_prot --- Specifies the type of protection built for ICCM0. --iccm0_prot None - -# iccm0_prot_level --- Specifies the level of protection. --iccm0_prot_level Data_Only - -# iccm0_prot_exceptions --- When the core is configured with ECC or Parity, cause exception generation hardware to be created for uncorrectable errors detected on the ICCM0 --iccm0_prot_exceptions true - -# iccm0_sec_lvl --- Specifies the level of secure ICCM0. --iccm0_sec_lvl Non_Secure - -# iccm0_dmi --- This enables external access through a DMI (direct memory interface) port. --iccm0_dmi true - - -######## Instruction Cache --- com.arc.hardware.Instruction_Cache.1_0 ######## - -# Create Instruction Cache --create com.arc.hardware.Instruction_Cache.1_0 "System.CPUisle.ARCv2EM.Instruction Cache" - -# ic_size --- This defines the total size of the instruction cache in bytes. --ic_size 16384 - -# ic_ways --- This defines the number of cache ways --ic_ways 2 - -# ic_bsize --- This defines the cache line length in bytes. --ic_bsize 64 - -# ic_disable_on_reset --- The instruction cache may be enabled immediately after reset, depending on this option. If this option is enabled, the last cache operation is set to failed, and the direct cache-RAM access is enabled. Furthermore, the instruction cache is invalidated all cache lines are invalidated and unlocked, and the tag RAM is cleared. --ic_disable_on_reset false - -# ic_feature_level --- This defines the feature level of the cache. --ic_feature_level 1 - -# ic_pwr_opt_level --- This selects power-optimization options in the micro-architecture of the instruction cache. --ic_pwr_opt_level 0 - -# ic_prot --- Specifies the type of protection built for ICACHE. --ic_prot None - -# ic_prot_level --- Specifies the level of protection. --ic_prot_level Data_Only - -# ic_prot_exceptions --- Builds exception generation hardware for uncorrectable (fatal) errors detected on ICACHE. --ic_prot_exceptions true - - -######## Interrupt Controller --- com.arc.hardware.Interrupt_Controller.1_0 ######## - -# Create Interrupt Controller --create com.arc.hardware.Interrupt_Controller.1_0 "System.CPUisle.ARCv2EM.Interrupt Controller" - -# number_of_interrupts --- This is the total number of interrupts available to the core. Some interrupts are allocated statically to a specific interrupt line (for example, timer interrupts). For more information on Interrupt and register-file options, see DesignWare ARCv2 ISA Programmers Reference Manual. --number_of_interrupts 98 - -# number_of_levels --- Priority levels in the interrupt controller. --number_of_levels 4 - -# external_interrupts --- This is the total number of interrupt pins available for external system components. This parameter must be less than the total number of interrupts. --external_interrupts 78 - -# firq_option --- This enables the fast-interrupts option, (priority level 0 interrupts), which uses an alternate register bank (if configured) instead of saving the context to memory. --firq_option true - - -######## JTAG Interface --- com.arc.hardware.JTAG_Interface.1_0 ######## - -# Create JTAG Interface --create com.arc.hardware.JTAG_Interface.1_0 "System.CPUisle.ARCv2EM.JTAG Interface" - -######## Real-time Counter --- com.arc.hardware.Real_time_Counter.1_0 ######## - -# Create Real-time Counter --create com.arc.hardware.Real_time_Counter.1_0 "System.CPUisle.ARCv2EM.Real-time Counter" - -######## Performance Monitor --- com.arc.hardware.Performance_Monitor.1_0 ######## - -# Create Performance Monitor --create com.arc.hardware.Performance_Monitor.1_0 "System.CPUisle.ARCv2EM.Performance Monitor" - -# pct_counters --- Number of counters for performance monitoring. --pct_counters 8 - - -######## Real-time trace producer --- com.arc.hardware.Real_time_trace_producer.1_0 ######## - -# Create Real-time trace producer --create com.arc.hardware.Real_time_trace_producer.1_0 "System.CPUisle.ARCv2EM.Real-time trace producer" - -# rtt_feature_level --- 'small' means that program trace only is available. `medium' adds data trace. `full' adds core and aux register trace. --rtt_feature_level full - - -######## SmaRT --- com.arc.hardware.SmaRT.1_0 ######## - -# Create SmaRT --create com.arc.hardware.SmaRT.1_0 System.CPUisle.ARCv2EM.SmaRT - -# smart_stack_entries --- This specifies the number of entries in the trace buffer. --smart_stack_entries 8 - -# smart_implementation --- Flip-flop = FF-based design. Memory = memory-based design (provides better density for larger trace buffers). --smart_implementation flip-flop - - -######## Timer 0 --- com.arc.hardware.Timer_0.1_0 ######## - -# Create Timer 0 --create com.arc.hardware.Timer_0.1_0 "System.CPUisle.ARCv2EM.Timer 0" - -# timer_0_int_level --- This sets the interrupt level (and implicitly the priority: level 0 is highest) of timer 0. --timer_0_int_level 1 - - -######## dsp_abs --- com.arc.hardware.scss.dsp_abs.1_0 ######## - -# Create dsp_abs --create com.arc.hardware.scss.dsp_abs.1_0 System.CPUisle.ARCv2EM.dsp_abs - -# dsp_abs --- Command line option for EIA extension component 'dsp_abs'. --dsp_abs true - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## dsp_acm --- com.arc.hardware.scss.dsp_acm.1_0 ######## - -# Create dsp_acm --create com.arc.hardware.scss.dsp_acm.1_0 System.CPUisle.ARCv2EM.dsp_acm - -# io_fw --- Input and output fractional width -# - Q0.31 -# - Q0.15 -# - Q0.7 --dsp_acm_io_fw 31 - -# acc_size --- Accumulator size: -# - Min=Q0.(io_fw), -# - Max=Q(int(2*((64 - io_fw)/(2 + io_fw)-1))).(int(io_fw*(64 - io_fw)/(2 + io_fw))) -# -# Note that for io_fw=31, the acc_size is always q0.31 --dsp_acm_acc_size min - -# z_wrap --- Output wrapping method --dsp_acm_z_wrap floor - -# dsp_acm --- Command line option for EIA extension component 'dsp_acm'. --dsp_acm true - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## dsp_add --- com.arc.hardware.scss.dsp_add.1_0 ######## - -# Create dsp_add --create com.arc.hardware.scss.dsp_add.1_0 System.CPUisle.ARCv2EM.dsp_add - -# dsp_add --- Command line option for EIA extension component 'dsp_add'. --dsp_add true - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## dsp_mac --- com.arc.hardware.scss.dsp_mac.1_0 ######## - -# Create dsp_mac --create com.arc.hardware.scss.dsp_mac.1_0 System.CPUisle.ARCv2EM.dsp_mac - -# dsp_mac --- Command line option for EIA extension component 'dsp_mac'. --dsp_mac true - -# io_fw --- Input and output fractional width -# - Q0.31 -# - Q0.15 -# - Q0.7 --dsp_mac_io_fw 15 - -# acc_size --- Accumulator size: -# - Min=Q1.(2*io_fw), -# - Max=Q(63-(2*io_fw)).(2*io_fw) --dsp_mac_acc_size min - -# z_wrap --- Output wrapping method --dsp_mac_z_wrap floor - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## dsp_mult --- com.arc.hardware.scss.dsp_mult.1_0 ######## - -# Create dsp_mult --create com.arc.hardware.scss.dsp_mult.1_0 System.CPUisle.ARCv2EM.dsp_mult - -# dsp_mult --- Command line option for EIA extension component 'dsp_mult'. --dsp_mult true - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## dsp_mulv --- com.arc.hardware.scss.dsp_mulv.1_0 ######## - -# Create dsp_mulv --create com.arc.hardware.scss.dsp_mulv.1_0 System.CPUisle.ARCv2EM.dsp_mulv - -# dsp_mulv --- Command line option for APEX extension component 'dsp_mulv'. --dsp_mulv true - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## dsp_negate --- com.arc.hardware.scss.dsp_negate.1_0 ######## - -# Create dsp_negate --create com.arc.hardware.scss.dsp_negate.1_0 System.CPUisle.ARCv2EM.dsp_negate - -# dsp_negate --- Command line option for EIA extension component 'dsp_negate'. --dsp_negate true - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## dsp_shift --- com.arc.hardware.scss.dsp_shift.1_0 ######## - -# Create dsp_shift --create com.arc.hardware.scss.dsp_shift.1_0 System.CPUisle.ARCv2EM.dsp_shift - -# dsp_shift --- Command line option for EIA extension component 'dsp_shift'. --dsp_shift true - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## dsp_sincos --- com.arc.hardware.scss.dsp_sincos.1_0 ######## - -# Create dsp_sincos --create com.arc.hardware.scss.dsp_sincos.1_0 System.CPUisle.ARCv2EM.dsp_sincos - -# dsp_sincos --- Command line option for APEX extension component 'dsp_sincos'. --dsp_sincos true - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## dsp_sqrt --- com.arc.hardware.scss.dsp_sqrt.1_0 ######## - -# Create dsp_sqrt --create com.arc.hardware.scss.dsp_sqrt.1_0 System.CPUisle.ARCv2EM.dsp_sqrt - -# dsp_sqrt --- Command line option for APEX extension component 'dsp_sqrt'. --dsp_sqrt true - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## dsp_sub --- com.arc.hardware.scss.dsp_sub.1_0 ######## - -# Create dsp_sub --create com.arc.hardware.scss.dsp_sub.1_0 System.CPUisle.ARCv2EM.dsp_sub - -# dsp_sub --- Command line option for EIA extension component 'dsp_sub'. --dsp_sub true - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_gpio0 --- com.arc.hardware.scss.io_gpio0.1_0 ######## - -# Create io_gpio0 --create com.arc.hardware.scss.io_gpio0.1_0 System.CPUisle.ARCv2EM.io_gpio0 - -# io_gpio0 --- Command line option for EIA extension component 'io_gpio0'. --io_gpio0 true - -# io_gpio0_debounce --- Selects the inclusion of Debounce logic --io_gpio0_debounce 1 - -# io_gpio0_readback_sync --- Selects the inclusion of metastability registers on the read back path when reading the external 'ext_porta' signal --io_gpio0_readback_sync 1 - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - -# io_gpio0_direction_rst_value --- Reset value of the SWPORTA_DDR register, which determines the direction (input/output) of the GPIO interface. 0: input, 1: output. --io_gpio0_direction_rst_value 0 - -# io_gpio0_output_rst_value --- Reset value of the SWPORTA_DR register, which determines the reset value of the GPIO output ports. Bits corresponding to input ports are ignored. --io_gpio0_output_rst_value 0x0 - - -######## io_gpio1 --- com.arc.hardware.scss.io_gpio1.1_0 ######## - -# Create io_gpio1 --create com.arc.hardware.scss.io_gpio1.1_0 System.CPUisle.ARCv2EM.io_gpio1 - -# io_gpio1 --- Command line option for EIA extension component 'io_gpio1'. --io_gpio1 true - -# io_gpio1_debounce --- Selects the inclusion of Debounce logic --io_gpio1_debounce 1 - -# io_gpio1_readback_sync --- Selects the inclusion of metastability registers on the read back path when reading the external 'ext_porta' signal --io_gpio1_readback_sync 1 - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - -# io_gpio1_direction_rst_value --- Reset value of the SWPORTA_DDR register, which determines the direction (input/output) of the GPIO interface. 0: input, 1: output. --io_gpio1_direction_rst_value 0 - -# io_gpio1_output_rst_value --- Reset value of the SWPORTA_DR register, which determines the reset value of the GPIO output ports. Bits corresponding to input ports are ignored. --io_gpio1_output_rst_value 0x0 - - -######## io_gpio2 --- com.arc.hardware.scss.io_gpio2.1_0 ######## - -# Create io_gpio2 --create com.arc.hardware.scss.io_gpio2.1_0 System.CPUisle.ARCv2EM.io_gpio2 - -# io_gpio2 --- Command line option for EIA extension component 'io_gpio2'. --io_gpio2 true - -# io_gpio2_debounce --- Selects the inclusion of Debounce logic --io_gpio2_debounce 1 - -# io_gpio2_readback_sync --- Selects the inclusion of metastability registers on the read back path when reading the external 'ext_porta' signal --io_gpio2_readback_sync 1 - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - -# io_gpio2_direction_rst_value --- Reset value of the SWPORTA_DDR register, which determines the direction (input/output) of the GPIO interface. 0: input, 1: output. --io_gpio2_direction_rst_value 0 - -# io_gpio2_output_rst_value --- Reset value of the SWPORTA_DR register, which determines the reset value of the GPIO output ports. Bits corresponding to input ports are ignored. --io_gpio2_output_rst_value 0x0 - - -######## io_i2c_mst0 --- com.arc.hardware.scss.io_i2c_mst0.1_0 ######## - -# Create io_i2c_mst0 --create com.arc.hardware.scss.io_i2c_mst0.1_0 System.CPUisle.ARCv2EM.io_i2c_mst0 - -# io_i2c_mst0 --- Command line option for APEX extension component 'io_i2c_mst0'. --io_i2c_mst0 true - -# io_i2c_mst0_fs --- RX/TX FIFO size --io_i2c_mst0_fs 16 - -# io_i2c_mst0_dma_support --- Specifies whether the DMA handshake interface is included --io_i2c_mst0_dma_support Memory-Based - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_i2c_mst1 --- com.arc.hardware.scss.io_i2c_mst1.1_0 ######## - -# Create io_i2c_mst1 --create com.arc.hardware.scss.io_i2c_mst1.1_0 System.CPUisle.ARCv2EM.io_i2c_mst1 - -# io_i2c_mst1 --- Command line option for APEX extension component 'io_i2c_mst1'. --io_i2c_mst1 true - -# io_i2c_mst1_fs --- RX/TX FIFO size --io_i2c_mst1_fs 16 - -# io_i2c_mst1_dma_support --- Specifies whether the DMA handshake interface is included --io_i2c_mst1_dma_support None - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_i2c_mst2 --- com.arc.hardware.scss.io_i2c_mst2.1_0 ######## - -# Create io_i2c_mst2 --create com.arc.hardware.scss.io_i2c_mst2.1_0 System.CPUisle.ARCv2EM.io_i2c_mst2 - -# io_i2c_mst2 --- Command line option for APEX extension component 'io_i2c_mst2'. --io_i2c_mst2 true - -# io_i2c_mst2_fs --- RX/TX FIFO size --io_i2c_mst2_fs 16 - -# io_i2c_mst2_dma_support --- Specifies whether the DMA handshake interface is included --io_i2c_mst2_dma_support None - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_i2c_slv0 --- com.arc.hardware.scss.io_i2c_slv0.1_0 ######## - -# Create io_i2c_slv0 --create com.arc.hardware.scss.io_i2c_slv0.1_0 System.CPUisle.ARCv2EM.io_i2c_slv0 - -# io_i2c_slv0 --- Command line option for APEX extension component 'io_i2c_slv0'. --io_i2c_slv0 true - -# io_i2c_slv0_fs --- RX/TX FIFO size --io_i2c_slv0_fs 2 - -# io_i2c_slv0_dma_support --- Specifies whether the DMA handshake interface is included --io_i2c_slv0_dma_support Memory-Based - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_pwm0 --- com.arc.hardware.scss.io_pwm0.1_0 ######## - -# Create io_pwm0 --create com.arc.hardware.scss.io_pwm0.1_0 System.CPUisle.ARCv2EM.io_pwm0 - -# io_pwm0 --- Command line option for APEX extension component 'io_pwm0'. --io_pwm0 true - -# io_pwm0_counter_width --- PWM Timer(counter) width --io_pwm0_cw 16 - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_pwm1 --- com.arc.hardware.scss.io_pwm1.1_0 ######## - -# Create io_pwm1 --create com.arc.hardware.scss.io_pwm1.1_0 System.CPUisle.ARCv2EM.io_pwm1 - -# io_pwm1 --- Command line option for APEX extension component 'io_pwm1'. --io_pwm1 true - -# io_pwm1_counter_width --- PWM Timer(counter) width --io_pwm1_cw 16 - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_spi_mst0 --- com.arc.hardware.scss.io_spi_mst0.1_0 ######## - -# Create io_spi_mst0 --create com.arc.hardware.scss.io_spi_mst0.1_0 System.CPUisle.ARCv2EM.io_spi_mst0 - -# io_spi_mst0 --- Command line option for APEX extension component 'io_spi_mst0'. --io_spi_mst0 true - -# io_spi_mst0_fz --- RX/TX FIFO depth --io_spi_mst0_fs 16 - -# io_spi_mst0_max_xfer_size --- This defines the maximum number of bits per word at the serial data port, which determines the FIFO width. --io_spi_mst0_max_xfer_size 16 - -# io_spi_mst0_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_spi_mst0_dma_support Memory-Based - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_spi_slv0 --- com.arc.hardware.scss.io_spi_slv0.1_0 ######## - -# Create io_spi_slv0 --create com.arc.hardware.scss.io_spi_slv0.1_0 System.CPUisle.ARCv2EM.io_spi_slv0 - -# io_spi_slv0 --- Command line option for APEX extension component 'io_spi_slv0'. --io_spi_slv0 true - -# io_spi_slv0_fz --- RX/TX FIFO depth --io_spi_slv0_fs 2 - -# io_spi_slv0_max_xfer_size --- This defines the maximum number of bits per word at the serial data port, which determines the FIFO width. --io_spi_slv0_max_xfer_size 16 - -# io_spi_slv0_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_spi_slv0_dma_support Memory-Based - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_uart0 --- com.arc.hardware.scss.io_uart0.1_0 ######## - -# Create io_uart0 --create com.arc.hardware.scss.io_uart0.1_0 System.CPUisle.ARCv2EM.io_uart0 - -# io_uart0 --- Command line option for EIA extension component 'io_uart0'. --io_uart0 true - -# io_uart0_fifo_mode --- Set the UART FIFO mode --io_uart0_fifo_mode 0 - -# io_uart0_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_uart0_dma_support None - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_uart1 --- com.arc.hardware.scss.io_uart1.1_0 ######## - -# Create io_uart1 --create com.arc.hardware.scss.io_uart1.1_0 System.CPUisle.ARCv2EM.io_uart1 - -# io_uart1 --- Command line option for EIA extension component 'io_uart1'. --io_uart1 true - -# io_uart1_fifo_mode --- Set the UART FIFO mode --io_uart1_fifo_mode 0 - -# io_uart1_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_uart1_dma_support None - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_uart2 --- com.arc.hardware.scss.io_uart2.1_0 ######## - -# Create io_uart2 --create com.arc.hardware.scss.io_uart2.1_0 System.CPUisle.ARCv2EM.io_uart2 - -# io_uart2 --- Command line option for EIA extension component 'io_uart2'. --io_uart2 true - -# io_uart2_fifo_mode --- Set the UART FIFO mode --io_uart2_fifo_mode 0 - -# io_uart2_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_uart2_dma_support None - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_uart3 --- com.arc.hardware.scss.io_uart3.1_0 ######## - -# Create io_uart3 --create com.arc.hardware.scss.io_uart3.1_0 System.CPUisle.ARCv2EM.io_uart3 - -# io_uart3 --- Command line option for EIA extension component 'io_uart3'. --io_uart3 true - -# io_uart3_fifo_mode --- Set the UART FIFO mode --io_uart3_fifo_mode 0 - -# io_uart3_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_uart3_dma_support None - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## subsys_bcr --- com.arc.hardware.scss.subsys_bcr.1_0 ######## - -# Create subsys_bcr --create com.arc.hardware.scss.subsys_bcr.1_0 System.CPUisle.ARCv2EM.subsys_bcr - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_spi_mst1 --- com.arc.hardware.scss.io_spi_mst1.1_0 ######## - -# Create io_spi_mst1 --create com.arc.hardware.scss.io_spi_mst1.1_0 System.CPUisle.ARCv2EM.io_spi_mst1 - -# io_spi_mst1 --- Command line option for APEX extension component 'io_spi_mst1'. --io_spi_mst1 true - -# io_spi_mst1_fz --- RX/TX FIFO depth --io_spi_mst1_fs 16 - -# io_spi_mst1_max_xfer_size --- This defines the maximum number of bits per word at the serial data port, which determines the FIFO width. --io_spi_mst1_max_xfer_size 16 - -# io_spi_mst1_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_spi_mst1_dma_support Memory-Based - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_spi_mst2 --- com.arc.hardware.scss.io_spi_mst2.1_0 ######## - -# Create io_spi_mst2 --create com.arc.hardware.scss.io_spi_mst2.1_0 System.CPUisle.ARCv2EM.io_spi_mst2 - -# io_spi_mst2 --- Command line option for APEX extension component 'io_spi_mst2'. --io_spi_mst2 true - -# io_spi_mst2_fz --- RX/TX FIFO depth --io_spi_mst2_fs 16 - -# io_spi_mst2_max_xfer_size --- This defines the maximum number of bits per word at the serial data port, which determines the FIFO width. --io_spi_mst2_max_xfer_size 16 - -# io_spi_mst2_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_spi_mst2_dma_support None - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## Watchdog Timer --- com.arc.hardware.Watchdog_Timer.1_0 ######## - -# Create Watchdog Timer --create com.arc.hardware.Watchdog_Timer.1_0 "System.CPUisle.ARCv2EM.Watchdog Timer" - -# watchdog_size --- Specifies the bit width of timer's internal counter. --watchdog_size 32 - -# watchdog_clk --- Specifies whether the timer should be driven from a separate clock. --watchdog_clk false - - -######## ClkCtrl --- com.arc.hardware.ARCv2MSS.ClkCtrl.1_0 ######## - -# Create ClkCtrl --create com.arc.hardware.ARCv2MSS.ClkCtrl.1_0 System.ClkCtrl - -######## DSP Software --- com.arc.software.scss.sw_dsp.1_0 ######## - -# Create DSP Software --create com.arc.software.scss.sw_dsp.1_0 "System.DSP Software" - -# sw_dsp --- Command line option for Software element 'DSP Software' --sw_dsp true - - -######## EMSDP_BOARD --- com.arc.hardware.ARCv2MSS.EMSDP_BOARD.1_0 ######## - -# Create EMSDP_BOARD --create com.arc.hardware.ARCv2MSS.EMSDP_BOARD.1_0 System.EMSDP_BOARD - -# emsdp_sys_freq --- Select the core frequency. --emsdp_sys_freq 50 - - -######## IO Software --- com.arc.software.scss.sw_io.1_0 ######## - -# Create IO Software --create com.arc.software.scss.sw_io.1_0 "System.IO Software" - -# sw_io --- Command line option for Software element 'IO Software' --sw_io true - - -######## Implementation --- com.arc.hardware.implementation.1_0 ######## - -# Create Implementation --create com.arc.hardware.implementation.1_0 System.Implementation - -# ClockSpeed --- Target clock speed of the system --clock_speed 10 - -# DDR2_clk_Ratio --- DDR2 Clock Vs System Clock Ratio -# 2x -# 3x -# 4x --ddr2_clk_ratio 3x - -# ClockSkew --- The clock skew for the system --clock_skew 0.2 - -# HoldMargin --- Margin for hold time checks --hold_margin 0.05 - -# Floorplan --- Floorplan definition for relative placement of RAMs (at CPU-level) or the placement of the rams and CPU hard cores (at multicore level) --floorplan em4_sensor - -# JTAGFrequency --- Select the frequency of the JTAG clock Tck (in MHz). -# -# The JTAG clock speed has to be less than 1/2 of the cpu clock otherwise the signals on the BVCI interface are not guaranteed to be valid. -# -# NOTE: The RTL simulations will work when the JTAG clock frequency is set to half the CPU clock, however this may not be the case when simulating at gate level due to delays on the IO pads. -# -# The default is set to 10 MHz so that there is no conflict when simulating with an ARCangel3 at 30MHz. (30 > 10*2) -# -# The speed of simulation can be greatly increased by using a faster JTAG clock, but a dependency will warn if it exceeds 1/2 of the cpu clock. -# --jtag_tclk 4 - -# execution_trace_level --- -# This traces committed instructions as they execute, and gathers statistics -# visible in the debugger for counting instructions & cycle delays. -# At the "stats" level ony the statistics are gathered and no trace is printed. -# "file" is equivalent to "full", but the results go to a trace .txt file instead. -# --execution_trace_level stats - -# tb_trace --- -# Enable instruction execution trace. -# This is available to arc_dev licensees (internal developers) only. -# --tb_trace false - -# zero_based_arcnum --- -# In a multicore build, number ARCs from 0. -# If this is not selected, arcs are numbered from 1. -# (This provides the initial value to the arcnum signal.) -# --zero_based_arcnum true - -# generate_ipxact --- -# Generate ipxact.xml file describing the CPUisle or archipelago frontier -# --generate_ipxact false - -# ipxact_relative_path_names --- -# Use relative path names for Verilog files in the ipxact. -# Otherwise, absolute path names are used. -# --ipxact_relative_path_names true - -# optional_encryption --- -# When selected, encrypted RTL output is generated. -# --optional_encryption false - -# ignore_encrypt_license --- -# When selected, pretend the encryption license is missing. For testing. -# --ignore_encrypt_license false - -# ignore_clear_license --- -# When selected, pretend the cleartest license is missing. For testing. -# --ignore_clear_license false - -# OPTION_require_archipelago --- -# When selected, force use of archipelago. This is for testing purposes. -# --require_archipelago false - - -######## Infrastructure Software --- com.arc.software.scss.sw_infra.1_0 ######## - -# Create Infrastructure Software --create com.arc.software.scss.sw_infra.1_0 "System.Infrastructure Software" - -# sw_infra --- Command line option for Software element 'Infrastructure Software' --sw_infra true - -# templateName --- Template name --template_name siss_combo_sensor - - -######## subsys_infra --- com.arc.hardware.scss.subsys_infra.1_0 ######## - -# Create subsys_infra --create com.arc.hardware.scss.subsys_infra.1_0 System.subsys_infra - -# subsys_infra --- Command line option for EIA glue logic. --subsys_infra true - -# internal_interrupt --- Connect the IO interrupts internally --internal_interrupt false - -# internal_dma_handshake --- Connect the DMA handshake signals internally --internal_dma_handshake false - -# spi_tb_sw_test_mode --- -# This is a secret option, not seen by customers. -# If you check this, the SPI peripheral's testbenches will be set to SW test mode: -# The serial interface of the first SPI master io_spi_mstN peripheral is connected to all SPI slave peripherals io_spi_slvN. -# This is used for testing the SW drivers. -# --spi_tb_sw_test_mode false - -# i3c_tb_sw_test_mode --- -# This is a secret option, not seen by customers. -# If you check this, the I3C peripheral's testbenches will be set to SW test mode: -# The serial interface of the io_i3cN peripheral is connected to the I2C slave peripherals io_i2c_slv0. -# This is used for testing the SW drivers. -# --i3c_tb_sw_test_mode false - -# subsys_apex_offset --- Subsystem APEX address offset in the AUX address space. The aperture used by the subsystem is fixed to 0x0010_0000. In general, the APEX address offset must be in the range from 0x0010_0000 to 0xFFF0_0000. However, if your design includes the "UAUX Interface" component, then the APEX address offset must be in the range from 0x0010_0000 to 0x7FF0_0000 to avoid address conflicts with any UAUX components. --subsys_apex_offset 0x8000_0000 - -# subsys_uaux_offset --- Subsystem UAUX address offset in the UAUX address space. The UAUX address offset must be an integer multiple of 0x0010_0000 in the range from 0x0000_0000 to 0x7FF0_0000. The aperture reserved for the subsystem is fixed to 0x0010_0000. --subsys_uaux_offset 0x10_0000 - - -######## Tool Configuration --- cgen.1_0 ######## - -# Create Tool Configuration --create cgen.1_0 "System.Tool Configuration" - -# mwdt_version --- Selects the MetaWare version to be used with the TCF file. -# Change from the default to an older or newer toolset version if you want the TCF file to be used with an older or newer version of the MetaWare tools. --mwdt_version O-2018.09 - -# code_base_addr --- -# The base address to assign to the executable code segment in the linker command file when there is no ICCM in the build. This value is ignored when there is an ICCM. -# --code_base_addr 0x0 - -# data_base_addr --- -# The base address to assign to the data segment in the linker command file when the data is not being mapped to a DCCM. This value is ignored when the data segment is mapped to a DCCM, as in that case the base address of the DCCM memory is used. -# -# A value of 0xffffffff means that the data segment will not be mapped to any specific address. -# --data_base_addr 0xffff_ffff - -# underscores_in_numbers --- Use underscores in hex numbers to improve readability. --underscores_in_numbers false - -# tcf_rebrand --- Alternate branding of TCF (not used) --rebrand false - - -]]> - - - - - - - - - - - - - - - ICCM0 - - GROUP BLOCK(4): { - /* _SDA_BASE_ computed implicitly */ - .sdata?: {} - .sbss?: {} - * (DATA): {} - * (BSS): {} - .stack ALIGN(4) SIZE(DEFINED _STACKSIZE?_STACKSIZE:65536): {} - .heap? ALIGN(4) SIZE(DEFINED _HEAPSIZE?_HEAPSIZE:0): {} - } > SYSTEM2 - GROUP BLOCK(4) : { - .vectors (TEXT) SIZE(DEFINED _IVTSIZE?_IVTSIZE:768): {} = FILL(0xa5a5a5a5,4) - } > IVT - } - -]]> - - - - - - 0x07, sub_opcode => 0x00 ) - -// User extension instruction - dsp_add_1d -extern long dsp_add_1d(long, long); -#pragma intrinsic(dsp_add_1d, opcode => 0x07, sub_opcode => 0x03 ) - -// User extension instruction - dsp_negate_1d -extern long dsp_negate_1d(long); -#pragma intrinsic(dsp_negate_1d, opcode => 0x07, sub_opcode => 0x0F ) - -// User extension instruction - dsp_shift_1d -extern long dsp_shift_1d(long, long); -#pragma intrinsic(dsp_shift_1d, opcode => 0x07, sub_opcode => 0x18 ) - -// User extension instruction - dsp_cos -extern long dsp_cos(long); -#pragma intrinsic(dsp_cos, opcode => 0x07, sub_opcode => 0x1E , latency_cycles => 8) - -// User extension instruction - dsp_sqrt -extern long dsp_sqrt(long); -#pragma intrinsic(dsp_sqrt, opcode => 0x07, sub_opcode => 0x20 , latency_cycles => 31) - -// User extension instruction - dsp_sub_1d -extern long dsp_sub_1d(long, long); -#pragma intrinsic(dsp_sub_1d, opcode => 0x07, sub_opcode => 0x06 ) - -// User extension instruction - dsp_abs_2d -extern long dsp_abs_2d(long); -#pragma intrinsic(dsp_abs_2d, opcode => 0x07, sub_opcode => 0x01 ) - -// User extension instruction - dsp_add_2d -extern long dsp_add_2d(long, long); -#pragma intrinsic(dsp_add_2d, opcode => 0x07, sub_opcode => 0x04 ) - -// User extension instruction - dsp_mulv_2d -extern long dsp_mulv_2d(long, long); -#pragma intrinsic(dsp_mulv_2d, opcode => 0x07, sub_opcode => 0x1E ) - -// User extension instruction - dsp_negate_2d -extern long dsp_negate_2d(long); -#pragma intrinsic(dsp_negate_2d, opcode => 0x07, sub_opcode => 0x10 ) - -// User extension instruction - dsp_shift_2d -extern long dsp_shift_2d(long, long); -#pragma intrinsic(dsp_shift_2d, opcode => 0x07, sub_opcode => 0x19 ) - -// User extension instruction - dsp_sin -extern long dsp_sin(long); -#pragma intrinsic(dsp_sin, opcode => 0x07, sub_opcode => 0x1F , latency_cycles => 8) - -// User extension instruction - dsp_sqrt15 -extern long dsp_sqrt15(long); -#pragma intrinsic(dsp_sqrt15, opcode => 0x07, sub_opcode => 0x21 , latency_cycles => 15) - -// User extension instruction - dsp_sub_2d -extern long dsp_sub_2d(long, long); -#pragma intrinsic(dsp_sub_2d, opcode => 0x07, sub_opcode => 0x07 ) - -// User extension instruction - dsp_abs_4d -extern long dsp_abs_4d(long); -#pragma intrinsic(dsp_abs_4d, opcode => 0x07, sub_opcode => 0x02 ) - -// User extension instruction - dsp_add_4d -extern long dsp_add_4d(long, long); -#pragma intrinsic(dsp_add_4d, opcode => 0x07, sub_opcode => 0x05 ) - -// User extension instruction - dsp_mulv_4d -extern long dsp_mulv_4d(long, long); -#pragma intrinsic(dsp_mulv_4d, opcode => 0x07, sub_opcode => 0x1F ) - -// User extension instruction - dsp_negate_4d -extern long dsp_negate_4d(long); -#pragma intrinsic(dsp_negate_4d, opcode => 0x07, sub_opcode => 0x11 ) - -// User extension instruction - dsp_shift_4d -extern long dsp_shift_4d(long, long); -#pragma intrinsic(dsp_shift_4d, opcode => 0x07, sub_opcode => 0x1A ) - -// User extension instruction - dsp_sub_4d -extern long dsp_sub_4d(long, long); -#pragma intrinsic(dsp_sub_4d, opcode => 0x07, sub_opcode => 0x08 ) - -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_ABS_PRESENT 1 -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_ACM_PRESENT 1 - -// User extension core register dsp_acm_msbout -#define CR_DSP_ACM_MSBOUT 54 -#pragma Core_register(54, name=>"dsp_acm_msbout", non_interlock_cycles=>"2", side_effects=>"rw") - -// User extension core register dsp_acm_lsbout -#define CR_DSP_ACM_LSBOUT 53 -#pragma Core_register(53, name=>"dsp_acm_lsbout", non_interlock_cycles=>"2", side_effects=>"rw") - -// User extension instruction dsp_acm -extern int dsp_acm(int,int); -#pragma intrinsic(dsp_acm,opcode=>7,sub_opcode=>29, effects=>"dsp_acm_lsbout:is_read:is_written:is_read_cycle=0:is_written_cycle=0; dsp_acm_msbout:is_read:is_written:is_read_cycle=0:is_written_cycle=0") -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_ADD_PRESENT 1 -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_MAC_PRESENT 1 - -// User extension core register dsp_mac_lsbout -#define CR_DSP_MAC_LSBOUT 56 -#pragma Core_register(56, name=>"dsp_mac_lsbout", non_interlock_cycles=>"2", side_effects=>"rw") - -// User extension core register dsp_mac_msbout -#define CR_DSP_MAC_MSBOUT 57 -#pragma Core_register(57, name=>"dsp_mac_msbout", non_interlock_cycles=>"2", side_effects=>"rw") - -// User extension instruction dsp_mac -extern int dsp_mac(int,int); -#pragma intrinsic(dsp_mac,opcode=>7,sub_opcode=>27, effects=>"dsp_mac_lsbout:is_read:is_written:is_read_cycle=0:is_written_cycle=0; dsp_mac_msbout:is_read:is_written:is_read_cycle=0:is_written_cycle=0") - -// User extension instruction dsp_mult -extern int dsp_mult(int,int); -#pragma intrinsic(dsp_mult,opcode=>7,sub_opcode=>28, effects=>"dsp_mac_lsbout:is_read:is_written:is_read_cycle=0:is_written_cycle=0; dsp_mac_msbout:is_read:is_written:is_read_cycle=0:is_written_cycle=0") -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_MULT_PRESENT 1 - -// User extension core register dsp_mult -#define CR_DSP_MULT 55 -#pragma Core_register(55, name=>"dsp_mult", non_interlock_cycles=>"2") - -// User extension instruction dsp_mult_2d -extern int dsp_mult_2d(int,int); -#pragma intrinsic(dsp_mult_2d,opcode=>7,sub_opcode=>13, effects=>"dsp_mult:is_written:is_read_cycle=0:is_written_cycle=0") - -// User extension instruction dsp_mult_4d -extern int dsp_mult_4d(int,int); -#pragma intrinsic(dsp_mult_4d,opcode=>7,sub_opcode=>14, effects=>"dsp_mult:is_written:is_read_cycle=0:is_written_cycle=0") -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_MULV_PRESENT 1 -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_NEGATE_PRESENT 1 -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_SHIFT_PRESENT 1 -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_SINCOS_PRESENT 1 -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_SQRT_PRESENT 1 -#define APEX_COM_ARC_HARDWARE_SCSS_DSP_SUB_PRESENT 1 -#define APEX_COM_ARC_HARDWARE_SCSS_IO_GPIO0_PRESENT 1 - -// User extension aux register io_gpio0_debounce -#define AR_IO_GPIO0_DEBOUNCE 0x80017048 -#pragma Aux_register(0x80017048, name=>"io_gpio0_debounce") - -// User extension aux register io_gpio0_clken -#define AR_IO_GPIO0_CLKEN 0x80017080 -#pragma Aux_register(0x80017080, name=>"io_gpio0_clken") - -// User extension aux register io_gpio0_swporta_dr -#define AR_IO_GPIO0_SWPORTA_DR 0x80017000 -#pragma Aux_register(0x80017000, name=>"io_gpio0_swporta_dr") - -// User extension aux register io_gpio0_swporta_ddr -#define AR_IO_GPIO0_SWPORTA_DDR 0x80017004 -#pragma Aux_register(0x80017004, name=>"io_gpio0_swporta_ddr") - -// User extension aux register io_gpio0_inten -#define AR_IO_GPIO0_INTEN 0x80017030 -#pragma Aux_register(0x80017030, name=>"io_gpio0_inten") - -// User extension aux register io_gpio0_intmask -#define AR_IO_GPIO0_INTMASK 0x80017034 -#pragma Aux_register(0x80017034, name=>"io_gpio0_intmask") - -// User extension aux register io_gpio0_inttype_level -#define AR_IO_GPIO0_INTTYPE_LEVEL 0x80017038 -#pragma Aux_register(0x80017038, name=>"io_gpio0_inttype_level") - -// User extension aux register io_gpio0_int_polarity -#define AR_IO_GPIO0_INT_POLARITY 0x8001703c -#pragma Aux_register(0x8001703c, name=>"io_gpio0_int_polarity") - -// User extension aux register io_gpio0_intstatus -#define AR_IO_GPIO0_INTSTATUS 0x80017040 -#pragma Aux_register(0x80017040, name=>"io_gpio0_intstatus") - -// User extension aux register io_gpio0_raw_intstatus -#define AR_IO_GPIO0_RAW_INTSTATUS 0x80017044 -#pragma Aux_register(0x80017044, name=>"io_gpio0_raw_intstatus") - -// User extension aux register io_gpio0_porta_eoi -#define AR_IO_GPIO0_PORTA_EOI 0x8001704c -#pragma Aux_register(0x8001704c, name=>"io_gpio0_porta_eoi") - -// User extension aux register io_gpio0_ext_porta -#define AR_IO_GPIO0_EXT_PORTA 0x80017050 -#pragma Aux_register(0x80017050, name=>"io_gpio0_ext_porta") - -// User extension aux register io_gpio0_ls_sync -#define AR_IO_GPIO0_LS_SYNC 0x80017060 -#pragma Aux_register(0x80017060, name=>"io_gpio0_ls_sync") - -// User extension aux register io_gpio0_int_bothedge -#define AR_IO_GPIO0_INT_BOTHEDGE 0x80017068 -#pragma Aux_register(0x80017068, name=>"io_gpio0_int_bothedge") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_GPIO1_PRESENT 1 - -// User extension aux register io_gpio1_debounce -#define AR_IO_GPIO1_DEBOUNCE 0x80017148 -#pragma Aux_register(0x80017148, name=>"io_gpio1_debounce") - -// User extension aux register io_gpio1_clken -#define AR_IO_GPIO1_CLKEN 0x80017180 -#pragma Aux_register(0x80017180, name=>"io_gpio1_clken") - -// User extension aux register io_gpio1_swporta_dr -#define AR_IO_GPIO1_SWPORTA_DR 0x80017100 -#pragma Aux_register(0x80017100, name=>"io_gpio1_swporta_dr") - -// User extension aux register io_gpio1_swporta_ddr -#define AR_IO_GPIO1_SWPORTA_DDR 0x80017104 -#pragma Aux_register(0x80017104, name=>"io_gpio1_swporta_ddr") - -// User extension aux register io_gpio1_inten -#define AR_IO_GPIO1_INTEN 0x80017130 -#pragma Aux_register(0x80017130, name=>"io_gpio1_inten") - -// User extension aux register io_gpio1_intmask -#define AR_IO_GPIO1_INTMASK 0x80017134 -#pragma Aux_register(0x80017134, name=>"io_gpio1_intmask") - -// User extension aux register io_gpio1_inttype_level -#define AR_IO_GPIO1_INTTYPE_LEVEL 0x80017138 -#pragma Aux_register(0x80017138, name=>"io_gpio1_inttype_level") - -// User extension aux register io_gpio1_int_polarity -#define AR_IO_GPIO1_INT_POLARITY 0x8001713c -#pragma Aux_register(0x8001713c, name=>"io_gpio1_int_polarity") - -// User extension aux register io_gpio1_intstatus -#define AR_IO_GPIO1_INTSTATUS 0x80017140 -#pragma Aux_register(0x80017140, name=>"io_gpio1_intstatus") - -// User extension aux register io_gpio1_raw_intstatus -#define AR_IO_GPIO1_RAW_INTSTATUS 0x80017144 -#pragma Aux_register(0x80017144, name=>"io_gpio1_raw_intstatus") - -// User extension aux register io_gpio1_porta_eoi -#define AR_IO_GPIO1_PORTA_EOI 0x8001714c -#pragma Aux_register(0x8001714c, name=>"io_gpio1_porta_eoi") - -// User extension aux register io_gpio1_ext_porta -#define AR_IO_GPIO1_EXT_PORTA 0x80017150 -#pragma Aux_register(0x80017150, name=>"io_gpio1_ext_porta") - -// User extension aux register io_gpio1_ls_sync -#define AR_IO_GPIO1_LS_SYNC 0x80017160 -#pragma Aux_register(0x80017160, name=>"io_gpio1_ls_sync") - -// User extension aux register io_gpio1_int_bothedge -#define AR_IO_GPIO1_INT_BOTHEDGE 0x80017168 -#pragma Aux_register(0x80017168, name=>"io_gpio1_int_bothedge") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_GPIO2_PRESENT 1 - -// User extension aux register io_gpio2_debounce -#define AR_IO_GPIO2_DEBOUNCE 0x80017248 -#pragma Aux_register(0x80017248, name=>"io_gpio2_debounce") - -// User extension aux register io_gpio2_clken -#define AR_IO_GPIO2_CLKEN 0x80017280 -#pragma Aux_register(0x80017280, name=>"io_gpio2_clken") - -// User extension aux register io_gpio2_swporta_dr -#define AR_IO_GPIO2_SWPORTA_DR 0x80017200 -#pragma Aux_register(0x80017200, name=>"io_gpio2_swporta_dr") - -// User extension aux register io_gpio2_swporta_ddr -#define AR_IO_GPIO2_SWPORTA_DDR 0x80017204 -#pragma Aux_register(0x80017204, name=>"io_gpio2_swporta_ddr") - -// User extension aux register io_gpio2_inten -#define AR_IO_GPIO2_INTEN 0x80017230 -#pragma Aux_register(0x80017230, name=>"io_gpio2_inten") - -// User extension aux register io_gpio2_intmask -#define AR_IO_GPIO2_INTMASK 0x80017234 -#pragma Aux_register(0x80017234, name=>"io_gpio2_intmask") - -// User extension aux register io_gpio2_inttype_level -#define AR_IO_GPIO2_INTTYPE_LEVEL 0x80017238 -#pragma Aux_register(0x80017238, name=>"io_gpio2_inttype_level") - -// User extension aux register io_gpio2_int_polarity -#define AR_IO_GPIO2_INT_POLARITY 0x8001723c -#pragma Aux_register(0x8001723c, name=>"io_gpio2_int_polarity") - -// User extension aux register io_gpio2_intstatus -#define AR_IO_GPIO2_INTSTATUS 0x80017240 -#pragma Aux_register(0x80017240, name=>"io_gpio2_intstatus") - -// User extension aux register io_gpio2_raw_intstatus -#define AR_IO_GPIO2_RAW_INTSTATUS 0x80017244 -#pragma Aux_register(0x80017244, name=>"io_gpio2_raw_intstatus") - -// User extension aux register io_gpio2_porta_eoi -#define AR_IO_GPIO2_PORTA_EOI 0x8001724c -#pragma Aux_register(0x8001724c, name=>"io_gpio2_porta_eoi") - -// User extension aux register io_gpio2_ext_porta -#define AR_IO_GPIO2_EXT_PORTA 0x80017250 -#pragma Aux_register(0x80017250, name=>"io_gpio2_ext_porta") - -// User extension aux register io_gpio2_ls_sync -#define AR_IO_GPIO2_LS_SYNC 0x80017260 -#pragma Aux_register(0x80017260, name=>"io_gpio2_ls_sync") - -// User extension aux register io_gpio2_int_bothedge -#define AR_IO_GPIO2_INT_BOTHEDGE 0x80017268 -#pragma Aux_register(0x80017268, name=>"io_gpio2_int_bothedge") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_I2C_MST0_PRESENT 1 - -// User extension aux register io_i2c_mst0_clken -#define AR_IO_I2C_MST0_CLKEN 0x800120c0 -#pragma Aux_register(0x800120c0, name=>"io_i2c_mst0_clken") - -// User extension aux register io_i2c_mst0_con -#define AR_IO_I2C_MST0_CON 0x80012000 -#pragma Aux_register(0x80012000, name=>"io_i2c_mst0_con") - -// User extension aux register io_i2c_mst0_tar -#define AR_IO_I2C_MST0_TAR 0x80012004 -#pragma Aux_register(0x80012004, name=>"io_i2c_mst0_tar") - -// User extension aux register io_i2c_mst0_data_cmd -#define AR_IO_I2C_MST0_DATA_CMD 0x80012010 -#pragma Aux_register(0x80012010, name=>"io_i2c_mst0_data_cmd") - -// User extension aux register io_i2c_mst0_ss_scl_hcnt -#define AR_IO_I2C_MST0_SS_SCL_HCNT 0x80012014 -#pragma Aux_register(0x80012014, name=>"io_i2c_mst0_ss_scl_hcnt") - -// User extension aux register io_i2c_mst0_ss_scl_lcnt -#define AR_IO_I2C_MST0_SS_SCL_LCNT 0x80012018 -#pragma Aux_register(0x80012018, name=>"io_i2c_mst0_ss_scl_lcnt") - -// User extension aux register io_i2c_mst0_fs_scl_hcnt -#define AR_IO_I2C_MST0_FS_SCL_HCNT 0x8001201c -#pragma Aux_register(0x8001201c, name=>"io_i2c_mst0_fs_scl_hcnt") - -// User extension aux register io_i2c_mst0_fs_scl_lcnt -#define AR_IO_I2C_MST0_FS_SCL_LCNT 0x80012020 -#pragma Aux_register(0x80012020, name=>"io_i2c_mst0_fs_scl_lcnt") - -// User extension aux register io_i2c_mst0_intr_stat -#define AR_IO_I2C_MST0_INTR_STAT 0x8001202c -#pragma Aux_register(0x8001202c, name=>"io_i2c_mst0_intr_stat") - -// User extension aux register io_i2c_mst0_intr_mask -#define AR_IO_I2C_MST0_INTR_MASK 0x80012030 -#pragma Aux_register(0x80012030, name=>"io_i2c_mst0_intr_mask") - -// User extension aux register io_i2c_mst0_raw_intr_stat -#define AR_IO_I2C_MST0_RAW_INTR_STAT 0x80012034 -#pragma Aux_register(0x80012034, name=>"io_i2c_mst0_raw_intr_stat") - -// User extension aux register io_i2c_mst0_rx_tl -#define AR_IO_I2C_MST0_RX_TL 0x80012038 -#pragma Aux_register(0x80012038, name=>"io_i2c_mst0_rx_tl") - -// User extension aux register io_i2c_mst0_tx_tl -#define AR_IO_I2C_MST0_TX_TL 0x8001203c -#pragma Aux_register(0x8001203c, name=>"io_i2c_mst0_tx_tl") - -// User extension aux register io_i2c_mst0_clr_intr -#define AR_IO_I2C_MST0_CLR_INTR 0x80012040 -#pragma Aux_register(0x80012040, name=>"io_i2c_mst0_clr_intr") - -// User extension aux register io_i2c_mst0_clr_rx_under -#define AR_IO_I2C_MST0_CLR_RX_UNDER 0x80012044 -#pragma Aux_register(0x80012044, name=>"io_i2c_mst0_clr_rx_under") - -// User extension aux register io_i2c_mst0_clr_rx_over -#define AR_IO_I2C_MST0_CLR_RX_OVER 0x80012048 -#pragma Aux_register(0x80012048, name=>"io_i2c_mst0_clr_rx_over") - -// User extension aux register io_i2c_mst0_clr_tx_over -#define AR_IO_I2C_MST0_CLR_TX_OVER 0x8001204c -#pragma Aux_register(0x8001204c, name=>"io_i2c_mst0_clr_tx_over") - -// User extension aux register io_i2c_mst0_clr_tx_abrt -#define AR_IO_I2C_MST0_CLR_TX_ABRT 0x80012054 -#pragma Aux_register(0x80012054, name=>"io_i2c_mst0_clr_tx_abrt") - -// User extension aux register io_i2c_mst0_clr_activity -#define AR_IO_I2C_MST0_CLR_ACTIVITY 0x8001205c -#pragma Aux_register(0x8001205c, name=>"io_i2c_mst0_clr_activity") - -// User extension aux register io_i2c_mst0_clr_stop_det -#define AR_IO_I2C_MST0_CLR_STOP_DET 0x80012060 -#pragma Aux_register(0x80012060, name=>"io_i2c_mst0_clr_stop_det") - -// User extension aux register io_i2c_mst0_clr_start_det -#define AR_IO_I2C_MST0_CLR_START_DET 0x80012064 -#pragma Aux_register(0x80012064, name=>"io_i2c_mst0_clr_start_det") - -// User extension aux register io_i2c_mst0_enable -#define AR_IO_I2C_MST0_ENABLE 0x8001206c -#pragma Aux_register(0x8001206c, name=>"io_i2c_mst0_enable") - -// User extension aux register io_i2c_mst0_status -#define AR_IO_I2C_MST0_STATUS 0x80012070 -#pragma Aux_register(0x80012070, name=>"io_i2c_mst0_status") - -// User extension aux register io_i2c_mst0_txflr -#define AR_IO_I2C_MST0_TXFLR 0x80012074 -#pragma Aux_register(0x80012074, name=>"io_i2c_mst0_txflr") - -// User extension aux register io_i2c_mst0_rxflr -#define AR_IO_I2C_MST0_RXFLR 0x80012078 -#pragma Aux_register(0x80012078, name=>"io_i2c_mst0_rxflr") - -// User extension aux register io_i2c_mst0_sda_hold -#define AR_IO_I2C_MST0_SDA_HOLD 0x8001207c -#pragma Aux_register(0x8001207c, name=>"io_i2c_mst0_sda_hold") - -// User extension aux register io_i2c_mst0_tx_abrt_source -#define AR_IO_I2C_MST0_TX_ABRT_SOURCE 0x80012080 -#pragma Aux_register(0x80012080, name=>"io_i2c_mst0_tx_abrt_source") - -// User extension aux register io_i2c_mst0_enable_status -#define AR_IO_I2C_MST0_ENABLE_STATUS 0x8001209c -#pragma Aux_register(0x8001209c, name=>"io_i2c_mst0_enable_status") - -// User extension aux register io_i2c_mst0_fs_spklen -#define AR_IO_I2C_MST0_FS_SPKLEN 0x800120a0 -#pragma Aux_register(0x800120a0, name=>"io_i2c_mst0_fs_spklen") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_I2C_MST1_PRESENT 1 - -// User extension aux register io_i2c_mst1_clken -#define AR_IO_I2C_MST1_CLKEN 0x800121c0 -#pragma Aux_register(0x800121c0, name=>"io_i2c_mst1_clken") - -// User extension aux register io_i2c_mst1_con -#define AR_IO_I2C_MST1_CON 0x80012100 -#pragma Aux_register(0x80012100, name=>"io_i2c_mst1_con") - -// User extension aux register io_i2c_mst1_tar -#define AR_IO_I2C_MST1_TAR 0x80012104 -#pragma Aux_register(0x80012104, name=>"io_i2c_mst1_tar") - -// User extension aux register io_i2c_mst1_data_cmd -#define AR_IO_I2C_MST1_DATA_CMD 0x80012110 -#pragma Aux_register(0x80012110, name=>"io_i2c_mst1_data_cmd") - -// User extension aux register io_i2c_mst1_ss_scl_hcnt -#define AR_IO_I2C_MST1_SS_SCL_HCNT 0x80012114 -#pragma Aux_register(0x80012114, name=>"io_i2c_mst1_ss_scl_hcnt") - -// User extension aux register io_i2c_mst1_ss_scl_lcnt -#define AR_IO_I2C_MST1_SS_SCL_LCNT 0x80012118 -#pragma Aux_register(0x80012118, name=>"io_i2c_mst1_ss_scl_lcnt") - -// User extension aux register io_i2c_mst1_fs_scl_hcnt -#define AR_IO_I2C_MST1_FS_SCL_HCNT 0x8001211c -#pragma Aux_register(0x8001211c, name=>"io_i2c_mst1_fs_scl_hcnt") - -// User extension aux register io_i2c_mst1_fs_scl_lcnt -#define AR_IO_I2C_MST1_FS_SCL_LCNT 0x80012120 -#pragma Aux_register(0x80012120, name=>"io_i2c_mst1_fs_scl_lcnt") - -// User extension aux register io_i2c_mst1_intr_stat -#define AR_IO_I2C_MST1_INTR_STAT 0x8001212c -#pragma Aux_register(0x8001212c, name=>"io_i2c_mst1_intr_stat") - -// User extension aux register io_i2c_mst1_intr_mask -#define AR_IO_I2C_MST1_INTR_MASK 0x80012130 -#pragma Aux_register(0x80012130, name=>"io_i2c_mst1_intr_mask") - -// User extension aux register io_i2c_mst1_raw_intr_stat -#define AR_IO_I2C_MST1_RAW_INTR_STAT 0x80012134 -#pragma Aux_register(0x80012134, name=>"io_i2c_mst1_raw_intr_stat") - -// User extension aux register io_i2c_mst1_rx_tl -#define AR_IO_I2C_MST1_RX_TL 0x80012138 -#pragma Aux_register(0x80012138, name=>"io_i2c_mst1_rx_tl") - -// User extension aux register io_i2c_mst1_tx_tl -#define AR_IO_I2C_MST1_TX_TL 0x8001213c -#pragma Aux_register(0x8001213c, name=>"io_i2c_mst1_tx_tl") - -// User extension aux register io_i2c_mst1_clr_intr -#define AR_IO_I2C_MST1_CLR_INTR 0x80012140 -#pragma Aux_register(0x80012140, name=>"io_i2c_mst1_clr_intr") - -// User extension aux register io_i2c_mst1_clr_rx_under -#define AR_IO_I2C_MST1_CLR_RX_UNDER 0x80012144 -#pragma Aux_register(0x80012144, name=>"io_i2c_mst1_clr_rx_under") - -// User extension aux register io_i2c_mst1_clr_rx_over -#define AR_IO_I2C_MST1_CLR_RX_OVER 0x80012148 -#pragma Aux_register(0x80012148, name=>"io_i2c_mst1_clr_rx_over") - -// User extension aux register io_i2c_mst1_clr_tx_over -#define AR_IO_I2C_MST1_CLR_TX_OVER 0x8001214c -#pragma Aux_register(0x8001214c, name=>"io_i2c_mst1_clr_tx_over") - -// User extension aux register io_i2c_mst1_clr_tx_abrt -#define AR_IO_I2C_MST1_CLR_TX_ABRT 0x80012154 -#pragma Aux_register(0x80012154, name=>"io_i2c_mst1_clr_tx_abrt") - -// User extension aux register io_i2c_mst1_clr_activity -#define AR_IO_I2C_MST1_CLR_ACTIVITY 0x8001215c -#pragma Aux_register(0x8001215c, name=>"io_i2c_mst1_clr_activity") - -// User extension aux register io_i2c_mst1_clr_stop_det -#define AR_IO_I2C_MST1_CLR_STOP_DET 0x80012160 -#pragma Aux_register(0x80012160, name=>"io_i2c_mst1_clr_stop_det") - -// User extension aux register io_i2c_mst1_clr_start_det -#define AR_IO_I2C_MST1_CLR_START_DET 0x80012164 -#pragma Aux_register(0x80012164, name=>"io_i2c_mst1_clr_start_det") - -// User extension aux register io_i2c_mst1_enable -#define AR_IO_I2C_MST1_ENABLE 0x8001216c -#pragma Aux_register(0x8001216c, name=>"io_i2c_mst1_enable") - -// User extension aux register io_i2c_mst1_status -#define AR_IO_I2C_MST1_STATUS 0x80012170 -#pragma Aux_register(0x80012170, name=>"io_i2c_mst1_status") - -// User extension aux register io_i2c_mst1_txflr -#define AR_IO_I2C_MST1_TXFLR 0x80012174 -#pragma Aux_register(0x80012174, name=>"io_i2c_mst1_txflr") - -// User extension aux register io_i2c_mst1_rxflr -#define AR_IO_I2C_MST1_RXFLR 0x80012178 -#pragma Aux_register(0x80012178, name=>"io_i2c_mst1_rxflr") - -// User extension aux register io_i2c_mst1_sda_hold -#define AR_IO_I2C_MST1_SDA_HOLD 0x8001217c -#pragma Aux_register(0x8001217c, name=>"io_i2c_mst1_sda_hold") - -// User extension aux register io_i2c_mst1_tx_abrt_source -#define AR_IO_I2C_MST1_TX_ABRT_SOURCE 0x80012180 -#pragma Aux_register(0x80012180, name=>"io_i2c_mst1_tx_abrt_source") - -// User extension aux register io_i2c_mst1_enable_status -#define AR_IO_I2C_MST1_ENABLE_STATUS 0x8001219c -#pragma Aux_register(0x8001219c, name=>"io_i2c_mst1_enable_status") - -// User extension aux register io_i2c_mst1_fs_spklen -#define AR_IO_I2C_MST1_FS_SPKLEN 0x800121a0 -#pragma Aux_register(0x800121a0, name=>"io_i2c_mst1_fs_spklen") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_I2C_MST2_PRESENT 1 - -// User extension aux register io_i2c_mst2_clken -#define AR_IO_I2C_MST2_CLKEN 0x800122c0 -#pragma Aux_register(0x800122c0, name=>"io_i2c_mst2_clken") - -// User extension aux register io_i2c_mst2_con -#define AR_IO_I2C_MST2_CON 0x80012200 -#pragma Aux_register(0x80012200, name=>"io_i2c_mst2_con") - -// User extension aux register io_i2c_mst2_tar -#define AR_IO_I2C_MST2_TAR 0x80012204 -#pragma Aux_register(0x80012204, name=>"io_i2c_mst2_tar") - -// User extension aux register io_i2c_mst2_data_cmd -#define AR_IO_I2C_MST2_DATA_CMD 0x80012210 -#pragma Aux_register(0x80012210, name=>"io_i2c_mst2_data_cmd") - -// User extension aux register io_i2c_mst2_ss_scl_hcnt -#define AR_IO_I2C_MST2_SS_SCL_HCNT 0x80012214 -#pragma Aux_register(0x80012214, name=>"io_i2c_mst2_ss_scl_hcnt") - -// User extension aux register io_i2c_mst2_ss_scl_lcnt -#define AR_IO_I2C_MST2_SS_SCL_LCNT 0x80012218 -#pragma Aux_register(0x80012218, name=>"io_i2c_mst2_ss_scl_lcnt") - -// User extension aux register io_i2c_mst2_fs_scl_hcnt -#define AR_IO_I2C_MST2_FS_SCL_HCNT 0x8001221c -#pragma Aux_register(0x8001221c, name=>"io_i2c_mst2_fs_scl_hcnt") - -// User extension aux register io_i2c_mst2_fs_scl_lcnt -#define AR_IO_I2C_MST2_FS_SCL_LCNT 0x80012220 -#pragma Aux_register(0x80012220, name=>"io_i2c_mst2_fs_scl_lcnt") - -// User extension aux register io_i2c_mst2_intr_stat -#define AR_IO_I2C_MST2_INTR_STAT 0x8001222c -#pragma Aux_register(0x8001222c, name=>"io_i2c_mst2_intr_stat") - -// User extension aux register io_i2c_mst2_intr_mask -#define AR_IO_I2C_MST2_INTR_MASK 0x80012230 -#pragma Aux_register(0x80012230, name=>"io_i2c_mst2_intr_mask") - -// User extension aux register io_i2c_mst2_raw_intr_stat -#define AR_IO_I2C_MST2_RAW_INTR_STAT 0x80012234 -#pragma Aux_register(0x80012234, name=>"io_i2c_mst2_raw_intr_stat") - -// User extension aux register io_i2c_mst2_rx_tl -#define AR_IO_I2C_MST2_RX_TL 0x80012238 -#pragma Aux_register(0x80012238, name=>"io_i2c_mst2_rx_tl") - -// User extension aux register io_i2c_mst2_tx_tl -#define AR_IO_I2C_MST2_TX_TL 0x8001223c -#pragma Aux_register(0x8001223c, name=>"io_i2c_mst2_tx_tl") - -// User extension aux register io_i2c_mst2_clr_intr -#define AR_IO_I2C_MST2_CLR_INTR 0x80012240 -#pragma Aux_register(0x80012240, name=>"io_i2c_mst2_clr_intr") - -// User extension aux register io_i2c_mst2_clr_rx_under -#define AR_IO_I2C_MST2_CLR_RX_UNDER 0x80012244 -#pragma Aux_register(0x80012244, name=>"io_i2c_mst2_clr_rx_under") - -// User extension aux register io_i2c_mst2_clr_rx_over -#define AR_IO_I2C_MST2_CLR_RX_OVER 0x80012248 -#pragma Aux_register(0x80012248, name=>"io_i2c_mst2_clr_rx_over") - -// User extension aux register io_i2c_mst2_clr_tx_over -#define AR_IO_I2C_MST2_CLR_TX_OVER 0x8001224c -#pragma Aux_register(0x8001224c, name=>"io_i2c_mst2_clr_tx_over") - -// User extension aux register io_i2c_mst2_clr_tx_abrt -#define AR_IO_I2C_MST2_CLR_TX_ABRT 0x80012254 -#pragma Aux_register(0x80012254, name=>"io_i2c_mst2_clr_tx_abrt") - -// User extension aux register io_i2c_mst2_clr_activity -#define AR_IO_I2C_MST2_CLR_ACTIVITY 0x8001225c -#pragma Aux_register(0x8001225c, name=>"io_i2c_mst2_clr_activity") - -// User extension aux register io_i2c_mst2_clr_stop_det -#define AR_IO_I2C_MST2_CLR_STOP_DET 0x80012260 -#pragma Aux_register(0x80012260, name=>"io_i2c_mst2_clr_stop_det") - -// User extension aux register io_i2c_mst2_clr_start_det -#define AR_IO_I2C_MST2_CLR_START_DET 0x80012264 -#pragma Aux_register(0x80012264, name=>"io_i2c_mst2_clr_start_det") - -// User extension aux register io_i2c_mst2_enable -#define AR_IO_I2C_MST2_ENABLE 0x8001226c -#pragma Aux_register(0x8001226c, name=>"io_i2c_mst2_enable") - -// User extension aux register io_i2c_mst2_status -#define AR_IO_I2C_MST2_STATUS 0x80012270 -#pragma Aux_register(0x80012270, name=>"io_i2c_mst2_status") - -// User extension aux register io_i2c_mst2_txflr -#define AR_IO_I2C_MST2_TXFLR 0x80012274 -#pragma Aux_register(0x80012274, name=>"io_i2c_mst2_txflr") - -// User extension aux register io_i2c_mst2_rxflr -#define AR_IO_I2C_MST2_RXFLR 0x80012278 -#pragma Aux_register(0x80012278, name=>"io_i2c_mst2_rxflr") - -// User extension aux register io_i2c_mst2_sda_hold -#define AR_IO_I2C_MST2_SDA_HOLD 0x8001227c -#pragma Aux_register(0x8001227c, name=>"io_i2c_mst2_sda_hold") - -// User extension aux register io_i2c_mst2_tx_abrt_source -#define AR_IO_I2C_MST2_TX_ABRT_SOURCE 0x80012280 -#pragma Aux_register(0x80012280, name=>"io_i2c_mst2_tx_abrt_source") - -// User extension aux register io_i2c_mst2_enable_status -#define AR_IO_I2C_MST2_ENABLE_STATUS 0x8001229c -#pragma Aux_register(0x8001229c, name=>"io_i2c_mst2_enable_status") - -// User extension aux register io_i2c_mst2_fs_spklen -#define AR_IO_I2C_MST2_FS_SPKLEN 0x800122a0 -#pragma Aux_register(0x800122a0, name=>"io_i2c_mst2_fs_spklen") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_I2C_SLV0_PRESENT 1 - -// User extension aux register io_i2c_slv0_clken -#define AR_IO_I2C_SLV0_CLKEN 0x800130c0 -#pragma Aux_register(0x800130c0, name=>"io_i2c_slv0_clken") - -// User extension aux register io_i2c_slv0_con -#define AR_IO_I2C_SLV0_CON 0x80013000 -#pragma Aux_register(0x80013000, name=>"io_i2c_slv0_con") - -// User extension aux register io_i2c_slv0_sar -#define AR_IO_I2C_SLV0_SAR 0x80013008 -#pragma Aux_register(0x80013008, name=>"io_i2c_slv0_sar") - -// User extension aux register io_i2c_slv0_data_cmd -#define AR_IO_I2C_SLV0_DATA_CMD 0x80013010 -#pragma Aux_register(0x80013010, name=>"io_i2c_slv0_data_cmd") - -// User extension aux register io_i2c_slv0_intr_stat -#define AR_IO_I2C_SLV0_INTR_STAT 0x8001302c -#pragma Aux_register(0x8001302c, name=>"io_i2c_slv0_intr_stat") - -// User extension aux register io_i2c_slv0_intr_mask -#define AR_IO_I2C_SLV0_INTR_MASK 0x80013030 -#pragma Aux_register(0x80013030, name=>"io_i2c_slv0_intr_mask") - -// User extension aux register io_i2c_slv0_raw_intr_stat -#define AR_IO_I2C_SLV0_RAW_INTR_STAT 0x80013034 -#pragma Aux_register(0x80013034, name=>"io_i2c_slv0_raw_intr_stat") - -// User extension aux register io_i2c_slv0_rx_tl -#define AR_IO_I2C_SLV0_RX_TL 0x80013038 -#pragma Aux_register(0x80013038, name=>"io_i2c_slv0_rx_tl") - -// User extension aux register io_i2c_slv0_tx_tl -#define AR_IO_I2C_SLV0_TX_TL 0x8001303c -#pragma Aux_register(0x8001303c, name=>"io_i2c_slv0_tx_tl") - -// User extension aux register io_i2c_slv0_clr_intr -#define AR_IO_I2C_SLV0_CLR_INTR 0x80013040 -#pragma Aux_register(0x80013040, name=>"io_i2c_slv0_clr_intr") - -// User extension aux register io_i2c_slv0_clr_rx_under -#define AR_IO_I2C_SLV0_CLR_RX_UNDER 0x80013044 -#pragma Aux_register(0x80013044, name=>"io_i2c_slv0_clr_rx_under") - -// User extension aux register io_i2c_slv0_clr_rx_over -#define AR_IO_I2C_SLV0_CLR_RX_OVER 0x80013048 -#pragma Aux_register(0x80013048, name=>"io_i2c_slv0_clr_rx_over") - -// User extension aux register io_i2c_slv0_clr_tx_over -#define AR_IO_I2C_SLV0_CLR_TX_OVER 0x8001304c -#pragma Aux_register(0x8001304c, name=>"io_i2c_slv0_clr_tx_over") - -// User extension aux register io_i2c_slv0_clr_rd_req -#define AR_IO_I2C_SLV0_CLR_RD_REQ 0x80013050 -#pragma Aux_register(0x80013050, name=>"io_i2c_slv0_clr_rd_req") - -// User extension aux register io_i2c_slv0_clr_tx_abrt -#define AR_IO_I2C_SLV0_CLR_TX_ABRT 0x80013054 -#pragma Aux_register(0x80013054, name=>"io_i2c_slv0_clr_tx_abrt") - -// User extension aux register io_i2c_slv0_clr_rx_done -#define AR_IO_I2C_SLV0_CLR_RX_DONE 0x80013058 -#pragma Aux_register(0x80013058, name=>"io_i2c_slv0_clr_rx_done") - -// User extension aux register io_i2c_slv0_clr_activity -#define AR_IO_I2C_SLV0_CLR_ACTIVITY 0x8001305c -#pragma Aux_register(0x8001305c, name=>"io_i2c_slv0_clr_activity") - -// User extension aux register io_i2c_slv0_clr_stop_det -#define AR_IO_I2C_SLV0_CLR_STOP_DET 0x80013060 -#pragma Aux_register(0x80013060, name=>"io_i2c_slv0_clr_stop_det") - -// User extension aux register io_i2c_slv0_clr_start_det -#define AR_IO_I2C_SLV0_CLR_START_DET 0x80013064 -#pragma Aux_register(0x80013064, name=>"io_i2c_slv0_clr_start_det") - -// User extension aux register io_i2c_slv0_enable -#define AR_IO_I2C_SLV0_ENABLE 0x8001306c -#pragma Aux_register(0x8001306c, name=>"io_i2c_slv0_enable") - -// User extension aux register io_i2c_slv0_status -#define AR_IO_I2C_SLV0_STATUS 0x80013070 -#pragma Aux_register(0x80013070, name=>"io_i2c_slv0_status") - -// User extension aux register io_i2c_slv0_txflr -#define AR_IO_I2C_SLV0_TXFLR 0x80013074 -#pragma Aux_register(0x80013074, name=>"io_i2c_slv0_txflr") - -// User extension aux register io_i2c_slv0_rxflr -#define AR_IO_I2C_SLV0_RXFLR 0x80013078 -#pragma Aux_register(0x80013078, name=>"io_i2c_slv0_rxflr") - -// User extension aux register io_i2c_slv0_sda_hold -#define AR_IO_I2C_SLV0_SDA_HOLD 0x8001307c -#pragma Aux_register(0x8001307c, name=>"io_i2c_slv0_sda_hold") - -// User extension aux register io_i2c_slv0_tx_abrt_source -#define AR_IO_I2C_SLV0_TX_ABRT_SOURCE 0x80013080 -#pragma Aux_register(0x80013080, name=>"io_i2c_slv0_tx_abrt_source") - -// User extension aux register io_i2c_slv0_sda_setup -#define AR_IO_I2C_SLV0_SDA_SETUP 0x80013094 -#pragma Aux_register(0x80013094, name=>"io_i2c_slv0_sda_setup") - -// User extension aux register io_i2c_slv0_enable_status -#define AR_IO_I2C_SLV0_ENABLE_STATUS 0x8001309c -#pragma Aux_register(0x8001309c, name=>"io_i2c_slv0_enable_status") - -// User extension aux register io_i2c_slv0_fs_spklen -#define AR_IO_I2C_SLV0_FS_SPKLEN 0x800130a0 -#pragma Aux_register(0x800130a0, name=>"io_i2c_slv0_fs_spklen") - -// User extension aux register io_i2c_slv0_clr_restart_det -#define AR_IO_I2C_SLV0_CLR_RESTART_DET 0x800130a8 -#pragma Aux_register(0x800130a8, name=>"io_i2c_slv0_clr_restart_det") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_PWM0_PRESENT 1 - -// User extension aux register io_pwm0_clken -#define AR_IO_PWM0_CLKEN 0x8001d020 -#pragma Aux_register(0x8001d020, name=>"io_pwm0_clken") - -// User extension aux register io_pwm0_ctrl -#define AR_IO_PWM0_CTRL 0x8001d000 -#pragma Aux_register(0x8001d000, name=>"io_pwm0_ctrl") - -// User extension aux register io_pwm0_chn_config -#define AR_IO_PWM0_CHN_CONFIG 0x8001d001 -#pragma Aux_register(0x8001d001, name=>"io_pwm0_chn_config") - -// User extension aux register io_pwm0_trigger -#define AR_IO_PWM0_TRIGGER 0x8001d002 -#pragma Aux_register(0x8001d002, name=>"io_pwm0_trigger") - -// User extension aux register io_pwm0_fault -#define AR_IO_PWM0_FAULT 0x8001d003 -#pragma Aux_register(0x8001d003, name=>"io_pwm0_fault") - -// User extension aux register io_pwm0_events -#define AR_IO_PWM0_EVENTS 0x8001d004 -#pragma Aux_register(0x8001d004, name=>"io_pwm0_events") - -// User extension aux register io_pwm0_intctrl -#define AR_IO_PWM0_INTCTRL 0x8001d005 -#pragma Aux_register(0x8001d005, name=>"io_pwm0_intctrl") - -// User extension aux register io_pwm0_intstat -#define AR_IO_PWM0_INTSTAT 0x8001d006 -#pragma Aux_register(0x8001d006, name=>"io_pwm0_intstat") - -// User extension aux register io_pwm0_intclr -#define AR_IO_PWM0_INTCLR 0x8001d007 -#pragma Aux_register(0x8001d007, name=>"io_pwm0_intclr") - -// User extension aux register io_pwm0_threshold_01 -#define AR_IO_PWM0_THRESHOLD_01 0x8001d008 -#pragma Aux_register(0x8001d008, name=>"io_pwm0_threshold_01") - -// User extension aux register io_pwm0_threshold_23 -#define AR_IO_PWM0_THRESHOLD_23 0x8001d009 -#pragma Aux_register(0x8001d009, name=>"io_pwm0_threshold_23") - -// User extension aux register io_pwm0_threshold_45 -#define AR_IO_PWM0_THRESHOLD_45 0x8001d00a -#pragma Aux_register(0x8001d00a, name=>"io_pwm0_threshold_45") - -// User extension aux register io_pwm0_threshold_67 -#define AR_IO_PWM0_THRESHOLD_67 0x8001d00b -#pragma Aux_register(0x8001d00b, name=>"io_pwm0_threshold_67") - -// User extension aux register io_pwm0_deadzone_01 -#define AR_IO_PWM0_DEADZONE_01 0x8001d00c -#pragma Aux_register(0x8001d00c, name=>"io_pwm0_deadzone_01") - -// User extension aux register io_pwm0_deadzone_23 -#define AR_IO_PWM0_DEADZONE_23 0x8001d00d -#pragma Aux_register(0x8001d00d, name=>"io_pwm0_deadzone_23") - -// User extension aux register io_pwm0_deadzone_45 -#define AR_IO_PWM0_DEADZONE_45 0x8001d00e -#pragma Aux_register(0x8001d00e, name=>"io_pwm0_deadzone_45") - -// User extension aux register io_pwm0_deadzone_67 -#define AR_IO_PWM0_DEADZONE_67 0x8001d00f -#pragma Aux_register(0x8001d00f, name=>"io_pwm0_deadzone_67") - -// User extension aux register io_pwm0_timer_max -#define AR_IO_PWM0_TIMER_MAX 0x8001d010 -#pragma Aux_register(0x8001d010, name=>"io_pwm0_timer_max") - -// User extension aux register io_pwm0_nperiods -#define AR_IO_PWM0_NPERIODS 0x8001d011 -#pragma Aux_register(0x8001d011, name=>"io_pwm0_nperiods") - -// User extension aux register io_pwm0_clk_div -#define AR_IO_PWM0_CLK_DIV 0x8001d012 -#pragma Aux_register(0x8001d012, name=>"io_pwm0_clk_div") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_PWM1_PRESENT 1 - -// User extension aux register io_pwm1_clken -#define AR_IO_PWM1_CLKEN 0x8001d120 -#pragma Aux_register(0x8001d120, name=>"io_pwm1_clken") - -// User extension aux register io_pwm1_ctrl -#define AR_IO_PWM1_CTRL 0x8001d100 -#pragma Aux_register(0x8001d100, name=>"io_pwm1_ctrl") - -// User extension aux register io_pwm1_chn_config -#define AR_IO_PWM1_CHN_CONFIG 0x8001d101 -#pragma Aux_register(0x8001d101, name=>"io_pwm1_chn_config") - -// User extension aux register io_pwm1_trigger -#define AR_IO_PWM1_TRIGGER 0x8001d102 -#pragma Aux_register(0x8001d102, name=>"io_pwm1_trigger") - -// User extension aux register io_pwm1_fault -#define AR_IO_PWM1_FAULT 0x8001d103 -#pragma Aux_register(0x8001d103, name=>"io_pwm1_fault") - -// User extension aux register io_pwm1_events -#define AR_IO_PWM1_EVENTS 0x8001d104 -#pragma Aux_register(0x8001d104, name=>"io_pwm1_events") - -// User extension aux register io_pwm1_intctrl -#define AR_IO_PWM1_INTCTRL 0x8001d105 -#pragma Aux_register(0x8001d105, name=>"io_pwm1_intctrl") - -// User extension aux register io_pwm1_intstat -#define AR_IO_PWM1_INTSTAT 0x8001d106 -#pragma Aux_register(0x8001d106, name=>"io_pwm1_intstat") - -// User extension aux register io_pwm1_intclr -#define AR_IO_PWM1_INTCLR 0x8001d107 -#pragma Aux_register(0x8001d107, name=>"io_pwm1_intclr") - -// User extension aux register io_pwm1_threshold_01 -#define AR_IO_PWM1_THRESHOLD_01 0x8001d108 -#pragma Aux_register(0x8001d108, name=>"io_pwm1_threshold_01") - -// User extension aux register io_pwm1_threshold_23 -#define AR_IO_PWM1_THRESHOLD_23 0x8001d109 -#pragma Aux_register(0x8001d109, name=>"io_pwm1_threshold_23") - -// User extension aux register io_pwm1_threshold_45 -#define AR_IO_PWM1_THRESHOLD_45 0x8001d10a -#pragma Aux_register(0x8001d10a, name=>"io_pwm1_threshold_45") - -// User extension aux register io_pwm1_threshold_67 -#define AR_IO_PWM1_THRESHOLD_67 0x8001d10b -#pragma Aux_register(0x8001d10b, name=>"io_pwm1_threshold_67") - -// User extension aux register io_pwm1_deadzone_01 -#define AR_IO_PWM1_DEADZONE_01 0x8001d10c -#pragma Aux_register(0x8001d10c, name=>"io_pwm1_deadzone_01") - -// User extension aux register io_pwm1_deadzone_23 -#define AR_IO_PWM1_DEADZONE_23 0x8001d10d -#pragma Aux_register(0x8001d10d, name=>"io_pwm1_deadzone_23") - -// User extension aux register io_pwm1_deadzone_45 -#define AR_IO_PWM1_DEADZONE_45 0x8001d10e -#pragma Aux_register(0x8001d10e, name=>"io_pwm1_deadzone_45") - -// User extension aux register io_pwm1_deadzone_67 -#define AR_IO_PWM1_DEADZONE_67 0x8001d10f -#pragma Aux_register(0x8001d10f, name=>"io_pwm1_deadzone_67") - -// User extension aux register io_pwm1_timer_max -#define AR_IO_PWM1_TIMER_MAX 0x8001d110 -#pragma Aux_register(0x8001d110, name=>"io_pwm1_timer_max") - -// User extension aux register io_pwm1_nperiods -#define AR_IO_PWM1_NPERIODS 0x8001d111 -#pragma Aux_register(0x8001d111, name=>"io_pwm1_nperiods") - -// User extension aux register io_pwm1_clk_div -#define AR_IO_PWM1_CLK_DIV 0x8001d112 -#pragma Aux_register(0x8001d112, name=>"io_pwm1_clk_div") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_SPI_MST0_PRESENT 1 - -// User extension aux register io_spi_mst0_ctrlr0 -#define AR_IO_SPI_MST0_CTRLR0 0x80010000 -#pragma Aux_register(0x80010000, name=>"io_spi_mst0_ctrlr0") - -// User extension aux register io_spi_mst0_ctrlr1 -#define AR_IO_SPI_MST0_CTRLR1 0x80010001 -#pragma Aux_register(0x80010001, name=>"io_spi_mst0_ctrlr1") - -// User extension aux register io_spi_mst0_spien -#define AR_IO_SPI_MST0_SPIEN 0x80010002 -#pragma Aux_register(0x80010002, name=>"io_spi_mst0_spien") - -// User extension aux register io_spi_mst0_ser -#define AR_IO_SPI_MST0_SER 0x80010004 -#pragma Aux_register(0x80010004, name=>"io_spi_mst0_ser") - -// User extension aux register io_spi_mst0_baudr -#define AR_IO_SPI_MST0_BAUDR 0x80010005 -#pragma Aux_register(0x80010005, name=>"io_spi_mst0_baudr") - -// User extension aux register io_spi_mst0_txftlr -#define AR_IO_SPI_MST0_TXFTLR 0x80010006 -#pragma Aux_register(0x80010006, name=>"io_spi_mst0_txftlr") - -// User extension aux register io_spi_mst0_rxftlr -#define AR_IO_SPI_MST0_RXFTLR 0x80010007 -#pragma Aux_register(0x80010007, name=>"io_spi_mst0_rxftlr") - -// User extension aux register io_spi_mst0_txflr -#define AR_IO_SPI_MST0_TXFLR 0x80010008 -#pragma Aux_register(0x80010008, name=>"io_spi_mst0_txflr") - -// User extension aux register io_spi_mst0_rxflr -#define AR_IO_SPI_MST0_RXFLR 0x80010009 -#pragma Aux_register(0x80010009, name=>"io_spi_mst0_rxflr") - -// User extension aux register io_spi_mst0_sr -#define AR_IO_SPI_MST0_SR 0x8001000a -#pragma Aux_register(0x8001000a, name=>"io_spi_mst0_sr") - -// User extension aux register io_spi_mst0_imr -#define AR_IO_SPI_MST0_IMR 0x8001000b -#pragma Aux_register(0x8001000b, name=>"io_spi_mst0_imr") - -// User extension aux register io_spi_mst0_isr -#define AR_IO_SPI_MST0_ISR 0x8001000c -#pragma Aux_register(0x8001000c, name=>"io_spi_mst0_isr") - -// User extension aux register io_spi_mst0_risr -#define AR_IO_SPI_MST0_RISR 0x8001000d -#pragma Aux_register(0x8001000d, name=>"io_spi_mst0_risr") - -// User extension aux register io_spi_mst0_txoicr -#define AR_IO_SPI_MST0_TXOICR 0x8001000e -#pragma Aux_register(0x8001000e, name=>"io_spi_mst0_txoicr") - -// User extension aux register io_spi_mst0_rxoicr -#define AR_IO_SPI_MST0_RXOICR 0x8001000f -#pragma Aux_register(0x8001000f, name=>"io_spi_mst0_rxoicr") - -// User extension aux register io_spi_mst0_rxuicr -#define AR_IO_SPI_MST0_RXUICR 0x80010010 -#pragma Aux_register(0x80010010, name=>"io_spi_mst0_rxuicr") - -// User extension aux register io_spi_mst0_icr -#define AR_IO_SPI_MST0_ICR 0x80010012 -#pragma Aux_register(0x80010012, name=>"io_spi_mst0_icr") - -// User extension aux register io_spi_mst0_clken -#define AR_IO_SPI_MST0_CLKEN 0x80010016 -#pragma Aux_register(0x80010016, name=>"io_spi_mst0_clken") - -// User extension aux register io_spi_mst0_dr -#define AR_IO_SPI_MST0_DR 0x80010018 -#pragma Aux_register(0x80010018, name=>"io_spi_mst0_dr") - -// User extension aux register io_spi_mst0_rx_sample_dly -#define AR_IO_SPI_MST0_RX_SAMPLE_DLY 0x8001003c -#pragma Aux_register(0x8001003c, name=>"io_spi_mst0_rx_sample_dly") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_SPI_SLV0_PRESENT 1 - -// User extension aux register io_spi_slv0_ctrlr0 -#define AR_IO_SPI_SLV0_CTRLR0 0x80011000 -#pragma Aux_register(0x80011000, name=>"io_spi_slv0_ctrlr0") - -// User extension aux register io_spi_slv0_spien -#define AR_IO_SPI_SLV0_SPIEN 0x80011002 -#pragma Aux_register(0x80011002, name=>"io_spi_slv0_spien") - -// User extension aux register io_spi_slv0_txftlr -#define AR_IO_SPI_SLV0_TXFTLR 0x80011006 -#pragma Aux_register(0x80011006, name=>"io_spi_slv0_txftlr") - -// User extension aux register io_spi_slv0_rxftlr -#define AR_IO_SPI_SLV0_RXFTLR 0x80011007 -#pragma Aux_register(0x80011007, name=>"io_spi_slv0_rxftlr") - -// User extension aux register io_spi_slv0_txflr -#define AR_IO_SPI_SLV0_TXFLR 0x80011008 -#pragma Aux_register(0x80011008, name=>"io_spi_slv0_txflr") - -// User extension aux register io_spi_slv0_rxflr -#define AR_IO_SPI_SLV0_RXFLR 0x80011009 -#pragma Aux_register(0x80011009, name=>"io_spi_slv0_rxflr") - -// User extension aux register io_spi_slv0_sr -#define AR_IO_SPI_SLV0_SR 0x8001100a -#pragma Aux_register(0x8001100a, name=>"io_spi_slv0_sr") - -// User extension aux register io_spi_slv0_imr -#define AR_IO_SPI_SLV0_IMR 0x8001100b -#pragma Aux_register(0x8001100b, name=>"io_spi_slv0_imr") - -// User extension aux register io_spi_slv0_isr -#define AR_IO_SPI_SLV0_ISR 0x8001100c -#pragma Aux_register(0x8001100c, name=>"io_spi_slv0_isr") - -// User extension aux register io_spi_slv0_risr -#define AR_IO_SPI_SLV0_RISR 0x8001100d -#pragma Aux_register(0x8001100d, name=>"io_spi_slv0_risr") - -// User extension aux register io_spi_slv0_txoicr -#define AR_IO_SPI_SLV0_TXOICR 0x8001100e -#pragma Aux_register(0x8001100e, name=>"io_spi_slv0_txoicr") - -// User extension aux register io_spi_slv0_rxoicr -#define AR_IO_SPI_SLV0_RXOICR 0x8001100f -#pragma Aux_register(0x8001100f, name=>"io_spi_slv0_rxoicr") - -// User extension aux register io_spi_slv0_rxuicr -#define AR_IO_SPI_SLV0_RXUICR 0x80011010 -#pragma Aux_register(0x80011010, name=>"io_spi_slv0_rxuicr") - -// User extension aux register io_spi_slv0_icr -#define AR_IO_SPI_SLV0_ICR 0x80011012 -#pragma Aux_register(0x80011012, name=>"io_spi_slv0_icr") - -// User extension aux register io_spi_slv0_clken -#define AR_IO_SPI_SLV0_CLKEN 0x80011016 -#pragma Aux_register(0x80011016, name=>"io_spi_slv0_clken") - -// User extension aux register io_spi_slv0_dr -#define AR_IO_SPI_SLV0_DR 0x80011018 -#pragma Aux_register(0x80011018, name=>"io_spi_slv0_dr") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_UART0_PRESENT 1 - -// User extension aux register io_uart0_clken -#define AR_IO_UART0_CLKEN 0x800140c0 -#pragma Aux_register(0x800140c0, name=>"io_uart0_clken") - -// User extension aux register io_uart0_rbr_thr_dll -#define AR_IO_UART0_RBR_THR_DLL 0x80014000 -#pragma Aux_register(0x80014000, name=>"io_uart0_rbr_thr_dll") - -// User extension aux register io_uart0_ier_dlh -#define AR_IO_UART0_IER_DLH 0x80014004 -#pragma Aux_register(0x80014004, name=>"io_uart0_ier_dlh") - -// User extension aux register io_uart0_iir_fcr -#define AR_IO_UART0_IIR_FCR 0x80014008 -#pragma Aux_register(0x80014008, name=>"io_uart0_iir_fcr") - -// User extension aux register io_uart0_lcr -#define AR_IO_UART0_LCR 0x8001400c -#pragma Aux_register(0x8001400c, name=>"io_uart0_lcr") - -// User extension aux register io_uart0_mcr -#define AR_IO_UART0_MCR 0x80014010 -#pragma Aux_register(0x80014010, name=>"io_uart0_mcr") - -// User extension aux register io_uart0_lsr -#define AR_IO_UART0_LSR 0x80014014 -#pragma Aux_register(0x80014014, name=>"io_uart0_lsr") - -// User extension aux register io_uart0_msr -#define AR_IO_UART0_MSR 0x80014018 -#pragma Aux_register(0x80014018, name=>"io_uart0_msr") - -// User extension aux register io_uart0_usr -#define AR_IO_UART0_USR 0x8001407c -#pragma Aux_register(0x8001407c, name=>"io_uart0_usr") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_UART1_PRESENT 1 - -// User extension aux register io_uart1_clken -#define AR_IO_UART1_CLKEN 0x800141c0 -#pragma Aux_register(0x800141c0, name=>"io_uart1_clken") - -// User extension aux register io_uart1_rbr_thr_dll -#define AR_IO_UART1_RBR_THR_DLL 0x80014100 -#pragma Aux_register(0x80014100, name=>"io_uart1_rbr_thr_dll") - -// User extension aux register io_uart1_ier_dlh -#define AR_IO_UART1_IER_DLH 0x80014104 -#pragma Aux_register(0x80014104, name=>"io_uart1_ier_dlh") - -// User extension aux register io_uart1_iir_fcr -#define AR_IO_UART1_IIR_FCR 0x80014108 -#pragma Aux_register(0x80014108, name=>"io_uart1_iir_fcr") - -// User extension aux register io_uart1_lcr -#define AR_IO_UART1_LCR 0x8001410c -#pragma Aux_register(0x8001410c, name=>"io_uart1_lcr") - -// User extension aux register io_uart1_mcr -#define AR_IO_UART1_MCR 0x80014110 -#pragma Aux_register(0x80014110, name=>"io_uart1_mcr") - -// User extension aux register io_uart1_lsr -#define AR_IO_UART1_LSR 0x80014114 -#pragma Aux_register(0x80014114, name=>"io_uart1_lsr") - -// User extension aux register io_uart1_msr -#define AR_IO_UART1_MSR 0x80014118 -#pragma Aux_register(0x80014118, name=>"io_uart1_msr") - -// User extension aux register io_uart1_usr -#define AR_IO_UART1_USR 0x8001417c -#pragma Aux_register(0x8001417c, name=>"io_uart1_usr") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_UART2_PRESENT 1 - -// User extension aux register io_uart2_clken -#define AR_IO_UART2_CLKEN 0x800142c0 -#pragma Aux_register(0x800142c0, name=>"io_uart2_clken") - -// User extension aux register io_uart2_rbr_thr_dll -#define AR_IO_UART2_RBR_THR_DLL 0x80014200 -#pragma Aux_register(0x80014200, name=>"io_uart2_rbr_thr_dll") - -// User extension aux register io_uart2_ier_dlh -#define AR_IO_UART2_IER_DLH 0x80014204 -#pragma Aux_register(0x80014204, name=>"io_uart2_ier_dlh") - -// User extension aux register io_uart2_iir_fcr -#define AR_IO_UART2_IIR_FCR 0x80014208 -#pragma Aux_register(0x80014208, name=>"io_uart2_iir_fcr") - -// User extension aux register io_uart2_lcr -#define AR_IO_UART2_LCR 0x8001420c -#pragma Aux_register(0x8001420c, name=>"io_uart2_lcr") - -// User extension aux register io_uart2_mcr -#define AR_IO_UART2_MCR 0x80014210 -#pragma Aux_register(0x80014210, name=>"io_uart2_mcr") - -// User extension aux register io_uart2_lsr -#define AR_IO_UART2_LSR 0x80014214 -#pragma Aux_register(0x80014214, name=>"io_uart2_lsr") - -// User extension aux register io_uart2_msr -#define AR_IO_UART2_MSR 0x80014218 -#pragma Aux_register(0x80014218, name=>"io_uart2_msr") - -// User extension aux register io_uart2_usr -#define AR_IO_UART2_USR 0x8001427c -#pragma Aux_register(0x8001427c, name=>"io_uart2_usr") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_UART3_PRESENT 1 - -// User extension aux register io_uart3_clken -#define AR_IO_UART3_CLKEN 0x800143c0 -#pragma Aux_register(0x800143c0, name=>"io_uart3_clken") - -// User extension aux register io_uart3_rbr_thr_dll -#define AR_IO_UART3_RBR_THR_DLL 0x80014300 -#pragma Aux_register(0x80014300, name=>"io_uart3_rbr_thr_dll") - -// User extension aux register io_uart3_ier_dlh -#define AR_IO_UART3_IER_DLH 0x80014304 -#pragma Aux_register(0x80014304, name=>"io_uart3_ier_dlh") - -// User extension aux register io_uart3_iir_fcr -#define AR_IO_UART3_IIR_FCR 0x80014308 -#pragma Aux_register(0x80014308, name=>"io_uart3_iir_fcr") - -// User extension aux register io_uart3_lcr -#define AR_IO_UART3_LCR 0x8001430c -#pragma Aux_register(0x8001430c, name=>"io_uart3_lcr") - -// User extension aux register io_uart3_mcr -#define AR_IO_UART3_MCR 0x80014310 -#pragma Aux_register(0x80014310, name=>"io_uart3_mcr") - -// User extension aux register io_uart3_lsr -#define AR_IO_UART3_LSR 0x80014314 -#pragma Aux_register(0x80014314, name=>"io_uart3_lsr") - -// User extension aux register io_uart3_msr -#define AR_IO_UART3_MSR 0x80014318 -#pragma Aux_register(0x80014318, name=>"io_uart3_msr") - -// User extension aux register io_uart3_usr -#define AR_IO_UART3_USR 0x8001437c -#pragma Aux_register(0x8001437c, name=>"io_uart3_usr") -#define APEX_COM_ARC_HARDWARE_SCSS_SUBSYS_BCR_PRESENT 1 - -// User extension aux register SUBSYS_BUILD -#define AR_SUBSYS_BUILD 0xf0 -#pragma Aux_register(0xf0, name=>"SUBSYS_BUILD") - -// User extension aux register SUBSYS_DSP_0_BUILD -#define AR_SUBSYS_DSP_0_BUILD 0xa00 -#pragma Aux_register(0xa00, name=>"SUBSYS_DSP_0_BUILD") - -// User extension aux register SUBSYS_DSP_0_CONFIG -#define AR_SUBSYS_DSP_0_CONFIG 0xa02 -#pragma Aux_register(0xa02, name=>"SUBSYS_DSP_0_CONFIG") - -// User extension aux register SUBSYS_IO_0_BUILD -#define AR_SUBSYS_IO_0_BUILD 0xa04 -#pragma Aux_register(0xa04, name=>"SUBSYS_IO_0_BUILD") - -// User extension aux register SUBSYS_IO_1_BUILD -#define AR_SUBSYS_IO_1_BUILD 0xa05 -#pragma Aux_register(0xa05, name=>"SUBSYS_IO_1_BUILD") - -// User extension aux register SUBSYS_IO_2_BUILD -#define AR_SUBSYS_IO_2_BUILD 0xa06 -#pragma Aux_register(0xa06, name=>"SUBSYS_IO_2_BUILD") - -// User extension aux register SUBSYS_UAUX_OFFSET -#define AR_SUBSYS_UAUX_OFFSET 0xa1e -#pragma Aux_register(0xa1e, name=>"SUBSYS_UAUX_OFFSET") - -// User extension aux register SUBSYS_APEX_OFFSET -#define AR_SUBSYS_APEX_OFFSET 0xa1f -#pragma Aux_register(0xa1f, name=>"SUBSYS_APEX_OFFSET") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_SPI_MST1_PRESENT 1 - -// User extension aux register io_spi_mst1_ctrlr0 -#define AR_IO_SPI_MST1_CTRLR0 0x80010100 -#pragma Aux_register(0x80010100, name=>"io_spi_mst1_ctrlr0") - -// User extension aux register io_spi_mst1_ctrlr1 -#define AR_IO_SPI_MST1_CTRLR1 0x80010101 -#pragma Aux_register(0x80010101, name=>"io_spi_mst1_ctrlr1") - -// User extension aux register io_spi_mst1_spien -#define AR_IO_SPI_MST1_SPIEN 0x80010102 -#pragma Aux_register(0x80010102, name=>"io_spi_mst1_spien") - -// User extension aux register io_spi_mst1_ser -#define AR_IO_SPI_MST1_SER 0x80010104 -#pragma Aux_register(0x80010104, name=>"io_spi_mst1_ser") - -// User extension aux register io_spi_mst1_baudr -#define AR_IO_SPI_MST1_BAUDR 0x80010105 -#pragma Aux_register(0x80010105, name=>"io_spi_mst1_baudr") - -// User extension aux register io_spi_mst1_txftlr -#define AR_IO_SPI_MST1_TXFTLR 0x80010106 -#pragma Aux_register(0x80010106, name=>"io_spi_mst1_txftlr") - -// User extension aux register io_spi_mst1_rxftlr -#define AR_IO_SPI_MST1_RXFTLR 0x80010107 -#pragma Aux_register(0x80010107, name=>"io_spi_mst1_rxftlr") - -// User extension aux register io_spi_mst1_txflr -#define AR_IO_SPI_MST1_TXFLR 0x80010108 -#pragma Aux_register(0x80010108, name=>"io_spi_mst1_txflr") - -// User extension aux register io_spi_mst1_rxflr -#define AR_IO_SPI_MST1_RXFLR 0x80010109 -#pragma Aux_register(0x80010109, name=>"io_spi_mst1_rxflr") - -// User extension aux register io_spi_mst1_sr -#define AR_IO_SPI_MST1_SR 0x8001010a -#pragma Aux_register(0x8001010a, name=>"io_spi_mst1_sr") - -// User extension aux register io_spi_mst1_imr -#define AR_IO_SPI_MST1_IMR 0x8001010b -#pragma Aux_register(0x8001010b, name=>"io_spi_mst1_imr") - -// User extension aux register io_spi_mst1_isr -#define AR_IO_SPI_MST1_ISR 0x8001010c -#pragma Aux_register(0x8001010c, name=>"io_spi_mst1_isr") - -// User extension aux register io_spi_mst1_risr -#define AR_IO_SPI_MST1_RISR 0x8001010d -#pragma Aux_register(0x8001010d, name=>"io_spi_mst1_risr") - -// User extension aux register io_spi_mst1_txoicr -#define AR_IO_SPI_MST1_TXOICR 0x8001010e -#pragma Aux_register(0x8001010e, name=>"io_spi_mst1_txoicr") - -// User extension aux register io_spi_mst1_rxoicr -#define AR_IO_SPI_MST1_RXOICR 0x8001010f -#pragma Aux_register(0x8001010f, name=>"io_spi_mst1_rxoicr") - -// User extension aux register io_spi_mst1_rxuicr -#define AR_IO_SPI_MST1_RXUICR 0x80010110 -#pragma Aux_register(0x80010110, name=>"io_spi_mst1_rxuicr") - -// User extension aux register io_spi_mst1_icr -#define AR_IO_SPI_MST1_ICR 0x80010112 -#pragma Aux_register(0x80010112, name=>"io_spi_mst1_icr") - -// User extension aux register io_spi_mst1_clken -#define AR_IO_SPI_MST1_CLKEN 0x80010116 -#pragma Aux_register(0x80010116, name=>"io_spi_mst1_clken") - -// User extension aux register io_spi_mst1_dr -#define AR_IO_SPI_MST1_DR 0x80010118 -#pragma Aux_register(0x80010118, name=>"io_spi_mst1_dr") - -// User extension aux register io_spi_mst1_rx_sample_dly -#define AR_IO_SPI_MST1_RX_SAMPLE_DLY 0x8001013c -#pragma Aux_register(0x8001013c, name=>"io_spi_mst1_rx_sample_dly") -#define APEX_COM_ARC_HARDWARE_SCSS_IO_SPI_MST2_PRESENT 1 - -// User extension aux register io_spi_mst2_ctrlr0 -#define AR_IO_SPI_MST2_CTRLR0 0x80010200 -#pragma Aux_register(0x80010200, name=>"io_spi_mst2_ctrlr0") - -// User extension aux register io_spi_mst2_ctrlr1 -#define AR_IO_SPI_MST2_CTRLR1 0x80010201 -#pragma Aux_register(0x80010201, name=>"io_spi_mst2_ctrlr1") - -// User extension aux register io_spi_mst2_spien -#define AR_IO_SPI_MST2_SPIEN 0x80010202 -#pragma Aux_register(0x80010202, name=>"io_spi_mst2_spien") - -// User extension aux register io_spi_mst2_ser -#define AR_IO_SPI_MST2_SER 0x80010204 -#pragma Aux_register(0x80010204, name=>"io_spi_mst2_ser") - -// User extension aux register io_spi_mst2_baudr -#define AR_IO_SPI_MST2_BAUDR 0x80010205 -#pragma Aux_register(0x80010205, name=>"io_spi_mst2_baudr") - -// User extension aux register io_spi_mst2_txftlr -#define AR_IO_SPI_MST2_TXFTLR 0x80010206 -#pragma Aux_register(0x80010206, name=>"io_spi_mst2_txftlr") - -// User extension aux register io_spi_mst2_rxftlr -#define AR_IO_SPI_MST2_RXFTLR 0x80010207 -#pragma Aux_register(0x80010207, name=>"io_spi_mst2_rxftlr") - -// User extension aux register io_spi_mst2_txflr -#define AR_IO_SPI_MST2_TXFLR 0x80010208 -#pragma Aux_register(0x80010208, name=>"io_spi_mst2_txflr") - -// User extension aux register io_spi_mst2_rxflr -#define AR_IO_SPI_MST2_RXFLR 0x80010209 -#pragma Aux_register(0x80010209, name=>"io_spi_mst2_rxflr") - -// User extension aux register io_spi_mst2_sr -#define AR_IO_SPI_MST2_SR 0x8001020a -#pragma Aux_register(0x8001020a, name=>"io_spi_mst2_sr") - -// User extension aux register io_spi_mst2_imr -#define AR_IO_SPI_MST2_IMR 0x8001020b -#pragma Aux_register(0x8001020b, name=>"io_spi_mst2_imr") - -// User extension aux register io_spi_mst2_isr -#define AR_IO_SPI_MST2_ISR 0x8001020c -#pragma Aux_register(0x8001020c, name=>"io_spi_mst2_isr") - -// User extension aux register io_spi_mst2_risr -#define AR_IO_SPI_MST2_RISR 0x8001020d -#pragma Aux_register(0x8001020d, name=>"io_spi_mst2_risr") - -// User extension aux register io_spi_mst2_txoicr -#define AR_IO_SPI_MST2_TXOICR 0x8001020e -#pragma Aux_register(0x8001020e, name=>"io_spi_mst2_txoicr") - -// User extension aux register io_spi_mst2_rxoicr -#define AR_IO_SPI_MST2_RXOICR 0x8001020f -#pragma Aux_register(0x8001020f, name=>"io_spi_mst2_rxoicr") - -// User extension aux register io_spi_mst2_rxuicr -#define AR_IO_SPI_MST2_RXUICR 0x80010210 -#pragma Aux_register(0x80010210, name=>"io_spi_mst2_rxuicr") - -// User extension aux register io_spi_mst2_icr -#define AR_IO_SPI_MST2_ICR 0x80010212 -#pragma Aux_register(0x80010212, name=>"io_spi_mst2_icr") - -// User extension aux register io_spi_mst2_clken -#define AR_IO_SPI_MST2_CLKEN 0x80010216 -#pragma Aux_register(0x80010216, name=>"io_spi_mst2_clken") - -// User extension aux register io_spi_mst2_dr -#define AR_IO_SPI_MST2_DR 0x80010218 -#pragma Aux_register(0x80010218, name=>"io_spi_mst2_dr") - -// User extension aux register io_spi_mst2_rx_sample_dly -#define AR_IO_SPI_MST2_RX_SAMPLE_DLY 0x8001023c -#pragma Aux_register(0x8001023c, name=>"io_spi_mst2_rx_sample_dly") -#define APEX_COM_ARC_HARDWARE_FLOATING_POINT_UNIT_FPU_PRESENT 1 - -// User extension aux register fpu_build -#define AR_FPU_BUILD 0xc8 -#pragma Aux_register(0xc8, name=>"fpu_build") - -// User extension aux register fpu_ctrl -#define AR_FPU_CTRL 0x300 -#pragma Aux_register(0x300, name=>"fpu_ctrl") - -// User extension aux register fpu_status -#define AR_FPU_STATUS 0x301 -#pragma Aux_register(0x301, name=>"fpu_status") - -// User extension instruction fsmadd -extern int fsmadd(int,int); -#pragma intrinsic(fsmadd,opcode=>6,sub_opcode=>5, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fsmsub -extern int fsmsub(int,int); -#pragma intrinsic(fsmsub,opcode=>6,sub_opcode=>6, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fsmul -extern int fsmul(int,int); -#pragma intrinsic(fsmul,opcode=>6,sub_opcode=>0, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fsadd -extern int fsadd(int,int); -#pragma intrinsic(fsadd,opcode=>6,sub_opcode=>1, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fssub -extern int fssub(int,int); -#pragma intrinsic(fssub,opcode=>6,sub_opcode=>2, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fcvt32 -extern int fcvt32(int,int); -#pragma intrinsic(fcvt32,opcode=>6,sub_opcode=>8, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fsdiv -extern int fsdiv(int,int); -#pragma intrinsic(fsdiv,opcode=>6,sub_opcode=>7, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fscmp -extern int fscmp(int,int); -#pragma intrinsic(fscmp,opcode=>6,sub_opcode=>3, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fscmp -extern int fscmp_f(int,int); -#pragma intrinsic(fscmp_f,opcode=>6,sub_opcode=>3, set_flags => 1, flags => "zncv", effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fscmpf -extern int fscmpf(int,int); -#pragma intrinsic(fscmpf,opcode=>6,sub_opcode=>4, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fscmpf -extern int fscmpf_f(int,int); -#pragma intrinsic(fscmpf_f,opcode=>6,sub_opcode=>4, set_flags => 1, flags => "zncv", effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fssqrt -extern int fssqrt(int); -#pragma intrinsic(fssqrt,opcode=>6,sub_opcode=>0, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") -#define APEX_COM_ARC_HARDWARE_FLOATING_POINT_UNIT_FPU_DP_ASSIST_PRESENT 1 - -// User extension aux register aux_dpfp1l -#define AR_AUX_DPFP1L 0x302 -#pragma Aux_register(0x302, name=>"aux_dpfp1l") - -// User extension aux register aux_dpfp1h -#define AR_AUX_DPFP1H 0x303 -#pragma Aux_register(0x303, name=>"aux_dpfp1h") - -// User extension aux register aux_dpfp2l -#define AR_AUX_DPFP2L 0x304 -#pragma Aux_register(0x304, name=>"aux_dpfp2l") - -// User extension aux register aux_dpfp2h -#define AR_AUX_DPFP2H 0x305 -#pragma Aux_register(0x305, name=>"aux_dpfp2h") - -// User extension instruction dmulh11 -extern int dmulh11(int,int); -#pragma intrinsic(dmulh11,opcode=>6,sub_opcode=>48,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh11 -extern int dmulh11_f(int,int); -#pragma intrinsic(dmulh11_f,opcode=>6,sub_opcode=>48, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh12 -extern int dmulh12(int,int); -#pragma intrinsic(dmulh12,opcode=>6,sub_opcode=>49,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh12 -extern int dmulh12_f(int,int); -#pragma intrinsic(dmulh12_f,opcode=>6,sub_opcode=>49, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh21 -extern int dmulh21(int,int); -#pragma intrinsic(dmulh21,opcode=>6,sub_opcode=>50,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh21 -extern int dmulh21_f(int,int); -#pragma intrinsic(dmulh21_f,opcode=>6,sub_opcode=>50, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh22 -extern int dmulh22(int,int); -#pragma intrinsic(dmulh22,opcode=>6,sub_opcode=>51,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh22 -extern int dmulh22_f(int,int); -#pragma intrinsic(dmulh22_f,opcode=>6,sub_opcode=>51, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh11 -extern int daddh11(int,int); -#pragma intrinsic(daddh11,opcode=>6,sub_opcode=>52,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh11 -extern int daddh11_f(int,int); -#pragma intrinsic(daddh11_f,opcode=>6,sub_opcode=>52, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh12 -extern int daddh12(int,int); -#pragma intrinsic(daddh12,opcode=>6,sub_opcode=>53,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh12 -extern int daddh12_f(int,int); -#pragma intrinsic(daddh12_f,opcode=>6,sub_opcode=>53, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh21 -extern int daddh21(int,int); -#pragma intrinsic(daddh21,opcode=>6,sub_opcode=>54,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh21 -extern int daddh21_f(int,int); -#pragma intrinsic(daddh21_f,opcode=>6,sub_opcode=>54, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh22 -extern int daddh22(int,int); -#pragma intrinsic(daddh22,opcode=>6,sub_opcode=>55,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh22 -extern int daddh22_f(int,int); -#pragma intrinsic(daddh22_f,opcode=>6,sub_opcode=>55, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh11 -extern int dsubh11(int,int); -#pragma intrinsic(dsubh11,opcode=>6,sub_opcode=>56,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh11 -extern int dsubh11_f(int,int); -#pragma intrinsic(dsubh11_f,opcode=>6,sub_opcode=>56, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh12 -extern int dsubh12(int,int); -#pragma intrinsic(dsubh12,opcode=>6,sub_opcode=>57,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh12 -extern int dsubh12_f(int,int); -#pragma intrinsic(dsubh12_f,opcode=>6,sub_opcode=>57, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh21 -extern int dsubh21(int,int); -#pragma intrinsic(dsubh21,opcode=>6,sub_opcode=>58,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh21 -extern int dsubh21_f(int,int); -#pragma intrinsic(dsubh21_f,opcode=>6,sub_opcode=>58, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh22 -extern int dsubh22(int,int); -#pragma intrinsic(dsubh22,opcode=>6,sub_opcode=>59,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh22 -extern int dsubh22_f(int,int); -#pragma intrinsic(dsubh22_f,opcode=>6,sub_opcode=>59, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dexcl1 -extern int dexcl1(int,int); -#pragma intrinsic(dexcl1,opcode=>6,sub_opcode=>60, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dexcl2 -extern int dexcl2(int,int); -#pragma intrinsic(dexcl2,opcode=>6,sub_opcode=>61, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - - -#endif - - -]]> - - - - - - diff --git a/board/emsdp/rev2/configs/em7d_esp_dfss/apexextensions.h b/board/emsdp/rev2/configs/em7d_esp_dfss/apexextensions.h deleted file mode 100644 index 943fecd72..000000000 --- a/board/emsdp/rev2/configs/em7d_esp_dfss/apexextensions.h +++ /dev/null @@ -1,1544 +0,0 @@ - -/* **** DO NOT EDIT - this file is generated by ARChitect2 **** - * - * Description: Header file declaring the compiler extensions for apex components - */ - -#ifndef _apexextensions_H_ -#define _apexextensions_H_ - -// User extension instruction - dsp_cos -extern long dsp_cos(long); -#pragma intrinsic(dsp_cos, opcode => 0x07, sub_opcode => 0x1E , latency_cycles => 8) - -// User extension instruction - dsp_sin -extern long dsp_sin(long); -#pragma intrinsic(dsp_sin, opcode => 0x07, sub_opcode => 0x1F , latency_cycles => 8) - -// User extension instruction - dsp_tan -extern long dsp_tan(long); -#pragma intrinsic(dsp_tan, opcode => 0x07, sub_opcode => 0x22 , latency_cycles => 11) - -// User extension instruction - dsp_acos -extern long dsp_acos(long); -#pragma intrinsic(dsp_acos, opcode => 0x07, sub_opcode => 0x23 , latency_cycles => 31) - -// User extension instruction - dsp_asin -extern long dsp_asin(long); -#pragma intrinsic(dsp_asin, opcode => 0x07, sub_opcode => 0x24 , latency_cycles => 31) - -// User extension instruction - dsp_atan -extern long dsp_atan(long); -#pragma intrinsic(dsp_atan, opcode => 0x07, sub_opcode => 0x25 , latency_cycles => 13) - -// User extension instruction - dsp_sqrt -extern long dsp_sqrt(long); -#pragma intrinsic(dsp_sqrt, opcode => 0x07, sub_opcode => 0x20 , latency_cycles => 31) - -// User extension instruction - dsp_sqrt15 -extern long dsp_sqrt15(long); -#pragma intrinsic(dsp_sqrt15, opcode => 0x07, sub_opcode => 0x21 , latency_cycles => 15) - -#define APEX_COM_ARC_HARDWARE_DFSS_DSP_TRIG_PRESENT 1 -#define APEX_COM_ARC_HARDWARE_DFSS_IO_GPIO0_PRESENT 1 - -// User extension aux register io_gpio0_debounce -#define AR_IO_GPIO0_DEBOUNCE 0x80017048 -#pragma Aux_register(0x80017048, name=>"io_gpio0_debounce") - -// User extension aux register io_gpio0_clken -#define AR_IO_GPIO0_CLKEN 0x80017080 -#pragma Aux_register(0x80017080, name=>"io_gpio0_clken") - -// User extension aux register io_gpio0_swporta_dr -#define AR_IO_GPIO0_SWPORTA_DR 0x80017000 -#pragma Aux_register(0x80017000, name=>"io_gpio0_swporta_dr") - -// User extension aux register io_gpio0_swporta_ddr -#define AR_IO_GPIO0_SWPORTA_DDR 0x80017004 -#pragma Aux_register(0x80017004, name=>"io_gpio0_swporta_ddr") - -// User extension aux register io_gpio0_inten -#define AR_IO_GPIO0_INTEN 0x80017030 -#pragma Aux_register(0x80017030, name=>"io_gpio0_inten") - -// User extension aux register io_gpio0_intmask -#define AR_IO_GPIO0_INTMASK 0x80017034 -#pragma Aux_register(0x80017034, name=>"io_gpio0_intmask") - -// User extension aux register io_gpio0_inttype_level -#define AR_IO_GPIO0_INTTYPE_LEVEL 0x80017038 -#pragma Aux_register(0x80017038, name=>"io_gpio0_inttype_level") - -// User extension aux register io_gpio0_int_polarity -#define AR_IO_GPIO0_INT_POLARITY 0x8001703c -#pragma Aux_register(0x8001703c, name=>"io_gpio0_int_polarity") - -// User extension aux register io_gpio0_intstatus -#define AR_IO_GPIO0_INTSTATUS 0x80017040 -#pragma Aux_register(0x80017040, name=>"io_gpio0_intstatus") - -// User extension aux register io_gpio0_raw_intstatus -#define AR_IO_GPIO0_RAW_INTSTATUS 0x80017044 -#pragma Aux_register(0x80017044, name=>"io_gpio0_raw_intstatus") - -// User extension aux register io_gpio0_porta_eoi -#define AR_IO_GPIO0_PORTA_EOI 0x8001704c -#pragma Aux_register(0x8001704c, name=>"io_gpio0_porta_eoi") - -// User extension aux register io_gpio0_ext_porta -#define AR_IO_GPIO0_EXT_PORTA 0x80017050 -#pragma Aux_register(0x80017050, name=>"io_gpio0_ext_porta") - -// User extension aux register io_gpio0_ls_sync -#define AR_IO_GPIO0_LS_SYNC 0x80017060 -#pragma Aux_register(0x80017060, name=>"io_gpio0_ls_sync") - -// User extension aux register io_gpio0_int_bothedge -#define AR_IO_GPIO0_INT_BOTHEDGE 0x80017068 -#pragma Aux_register(0x80017068, name=>"io_gpio0_int_bothedge") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2C_MST0_PRESENT 1 - -// User extension aux register io_i2c_mst0_clken -#define AR_IO_I2C_MST0_CLKEN 0x800120c0 -#pragma Aux_register(0x800120c0, name=>"io_i2c_mst0_clken") - -// User extension aux register io_i2c_mst0_con -#define AR_IO_I2C_MST0_CON 0x80012000 -#pragma Aux_register(0x80012000, name=>"io_i2c_mst0_con") - -// User extension aux register io_i2c_mst0_tar -#define AR_IO_I2C_MST0_TAR 0x80012004 -#pragma Aux_register(0x80012004, name=>"io_i2c_mst0_tar") - -// User extension aux register io_i2c_mst0_data_cmd -#define AR_IO_I2C_MST0_DATA_CMD 0x80012010 -#pragma Aux_register(0x80012010, name=>"io_i2c_mst0_data_cmd") - -// User extension aux register io_i2c_mst0_ss_scl_hcnt -#define AR_IO_I2C_MST0_SS_SCL_HCNT 0x80012014 -#pragma Aux_register(0x80012014, name=>"io_i2c_mst0_ss_scl_hcnt") - -// User extension aux register io_i2c_mst0_ss_scl_lcnt -#define AR_IO_I2C_MST0_SS_SCL_LCNT 0x80012018 -#pragma Aux_register(0x80012018, name=>"io_i2c_mst0_ss_scl_lcnt") - -// User extension aux register io_i2c_mst0_fs_scl_hcnt -#define AR_IO_I2C_MST0_FS_SCL_HCNT 0x8001201c -#pragma Aux_register(0x8001201c, name=>"io_i2c_mst0_fs_scl_hcnt") - -// User extension aux register io_i2c_mst0_fs_scl_lcnt -#define AR_IO_I2C_MST0_FS_SCL_LCNT 0x80012020 -#pragma Aux_register(0x80012020, name=>"io_i2c_mst0_fs_scl_lcnt") - -// User extension aux register io_i2c_mst0_intr_stat -#define AR_IO_I2C_MST0_INTR_STAT 0x8001202c -#pragma Aux_register(0x8001202c, name=>"io_i2c_mst0_intr_stat") - -// User extension aux register io_i2c_mst0_intr_mask -#define AR_IO_I2C_MST0_INTR_MASK 0x80012030 -#pragma Aux_register(0x80012030, name=>"io_i2c_mst0_intr_mask") - -// User extension aux register io_i2c_mst0_raw_intr_stat -#define AR_IO_I2C_MST0_RAW_INTR_STAT 0x80012034 -#pragma Aux_register(0x80012034, name=>"io_i2c_mst0_raw_intr_stat") - -// User extension aux register io_i2c_mst0_rx_tl -#define AR_IO_I2C_MST0_RX_TL 0x80012038 -#pragma Aux_register(0x80012038, name=>"io_i2c_mst0_rx_tl") - -// User extension aux register io_i2c_mst0_tx_tl -#define AR_IO_I2C_MST0_TX_TL 0x8001203c -#pragma Aux_register(0x8001203c, name=>"io_i2c_mst0_tx_tl") - -// User extension aux register io_i2c_mst0_clr_intr -#define AR_IO_I2C_MST0_CLR_INTR 0x80012040 -#pragma Aux_register(0x80012040, name=>"io_i2c_mst0_clr_intr") - -// User extension aux register io_i2c_mst0_clr_rx_under -#define AR_IO_I2C_MST0_CLR_RX_UNDER 0x80012044 -#pragma Aux_register(0x80012044, name=>"io_i2c_mst0_clr_rx_under") - -// User extension aux register io_i2c_mst0_clr_rx_over -#define AR_IO_I2C_MST0_CLR_RX_OVER 0x80012048 -#pragma Aux_register(0x80012048, name=>"io_i2c_mst0_clr_rx_over") - -// User extension aux register io_i2c_mst0_clr_tx_over -#define AR_IO_I2C_MST0_CLR_TX_OVER 0x8001204c -#pragma Aux_register(0x8001204c, name=>"io_i2c_mst0_clr_tx_over") - -// User extension aux register io_i2c_mst0_clr_tx_abrt -#define AR_IO_I2C_MST0_CLR_TX_ABRT 0x80012054 -#pragma Aux_register(0x80012054, name=>"io_i2c_mst0_clr_tx_abrt") - -// User extension aux register io_i2c_mst0_clr_activity -#define AR_IO_I2C_MST0_CLR_ACTIVITY 0x8001205c -#pragma Aux_register(0x8001205c, name=>"io_i2c_mst0_clr_activity") - -// User extension aux register io_i2c_mst0_clr_stop_det -#define AR_IO_I2C_MST0_CLR_STOP_DET 0x80012060 -#pragma Aux_register(0x80012060, name=>"io_i2c_mst0_clr_stop_det") - -// User extension aux register io_i2c_mst0_clr_start_det -#define AR_IO_I2C_MST0_CLR_START_DET 0x80012064 -#pragma Aux_register(0x80012064, name=>"io_i2c_mst0_clr_start_det") - -// User extension aux register io_i2c_mst0_enable -#define AR_IO_I2C_MST0_ENABLE 0x8001206c -#pragma Aux_register(0x8001206c, name=>"io_i2c_mst0_enable") - -// User extension aux register io_i2c_mst0_status -#define AR_IO_I2C_MST0_STATUS 0x80012070 -#pragma Aux_register(0x80012070, name=>"io_i2c_mst0_status") - -// User extension aux register io_i2c_mst0_txflr -#define AR_IO_I2C_MST0_TXFLR 0x80012074 -#pragma Aux_register(0x80012074, name=>"io_i2c_mst0_txflr") - -// User extension aux register io_i2c_mst0_rxflr -#define AR_IO_I2C_MST0_RXFLR 0x80012078 -#pragma Aux_register(0x80012078, name=>"io_i2c_mst0_rxflr") - -// User extension aux register io_i2c_mst0_sda_hold -#define AR_IO_I2C_MST0_SDA_HOLD 0x8001207c -#pragma Aux_register(0x8001207c, name=>"io_i2c_mst0_sda_hold") - -// User extension aux register io_i2c_mst0_tx_abrt_source -#define AR_IO_I2C_MST0_TX_ABRT_SOURCE 0x80012080 -#pragma Aux_register(0x80012080, name=>"io_i2c_mst0_tx_abrt_source") - -// User extension aux register io_i2c_mst0_enable_status -#define AR_IO_I2C_MST0_ENABLE_STATUS 0x8001209c -#pragma Aux_register(0x8001209c, name=>"io_i2c_mst0_enable_status") - -// User extension aux register io_i2c_mst0_fs_spklen -#define AR_IO_I2C_MST0_FS_SPKLEN 0x800120a0 -#pragma Aux_register(0x800120a0, name=>"io_i2c_mst0_fs_spklen") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2C_SLV0_PRESENT 1 - -// User extension aux register io_i2c_slv0_clken -#define AR_IO_I2C_SLV0_CLKEN 0x800130c0 -#pragma Aux_register(0x800130c0, name=>"io_i2c_slv0_clken") - -// User extension aux register io_i2c_slv0_con -#define AR_IO_I2C_SLV0_CON 0x80013000 -#pragma Aux_register(0x80013000, name=>"io_i2c_slv0_con") - -// User extension aux register io_i2c_slv0_sar -#define AR_IO_I2C_SLV0_SAR 0x80013008 -#pragma Aux_register(0x80013008, name=>"io_i2c_slv0_sar") - -// User extension aux register io_i2c_slv0_data_cmd -#define AR_IO_I2C_SLV0_DATA_CMD 0x80013010 -#pragma Aux_register(0x80013010, name=>"io_i2c_slv0_data_cmd") - -// User extension aux register io_i2c_slv0_intr_stat -#define AR_IO_I2C_SLV0_INTR_STAT 0x8001302c -#pragma Aux_register(0x8001302c, name=>"io_i2c_slv0_intr_stat") - -// User extension aux register io_i2c_slv0_intr_mask -#define AR_IO_I2C_SLV0_INTR_MASK 0x80013030 -#pragma Aux_register(0x80013030, name=>"io_i2c_slv0_intr_mask") - -// User extension aux register io_i2c_slv0_raw_intr_stat -#define AR_IO_I2C_SLV0_RAW_INTR_STAT 0x80013034 -#pragma Aux_register(0x80013034, name=>"io_i2c_slv0_raw_intr_stat") - -// User extension aux register io_i2c_slv0_rx_tl -#define AR_IO_I2C_SLV0_RX_TL 0x80013038 -#pragma Aux_register(0x80013038, name=>"io_i2c_slv0_rx_tl") - -// User extension aux register io_i2c_slv0_tx_tl -#define AR_IO_I2C_SLV0_TX_TL 0x8001303c -#pragma Aux_register(0x8001303c, name=>"io_i2c_slv0_tx_tl") - -// User extension aux register io_i2c_slv0_clr_intr -#define AR_IO_I2C_SLV0_CLR_INTR 0x80013040 -#pragma Aux_register(0x80013040, name=>"io_i2c_slv0_clr_intr") - -// User extension aux register io_i2c_slv0_clr_rx_under -#define AR_IO_I2C_SLV0_CLR_RX_UNDER 0x80013044 -#pragma Aux_register(0x80013044, name=>"io_i2c_slv0_clr_rx_under") - -// User extension aux register io_i2c_slv0_clr_rx_over -#define AR_IO_I2C_SLV0_CLR_RX_OVER 0x80013048 -#pragma Aux_register(0x80013048, name=>"io_i2c_slv0_clr_rx_over") - -// User extension aux register io_i2c_slv0_clr_tx_over -#define AR_IO_I2C_SLV0_CLR_TX_OVER 0x8001304c -#pragma Aux_register(0x8001304c, name=>"io_i2c_slv0_clr_tx_over") - -// User extension aux register io_i2c_slv0_clr_rd_req -#define AR_IO_I2C_SLV0_CLR_RD_REQ 0x80013050 -#pragma Aux_register(0x80013050, name=>"io_i2c_slv0_clr_rd_req") - -// User extension aux register io_i2c_slv0_clr_tx_abrt -#define AR_IO_I2C_SLV0_CLR_TX_ABRT 0x80013054 -#pragma Aux_register(0x80013054, name=>"io_i2c_slv0_clr_tx_abrt") - -// User extension aux register io_i2c_slv0_clr_rx_done -#define AR_IO_I2C_SLV0_CLR_RX_DONE 0x80013058 -#pragma Aux_register(0x80013058, name=>"io_i2c_slv0_clr_rx_done") - -// User extension aux register io_i2c_slv0_clr_activity -#define AR_IO_I2C_SLV0_CLR_ACTIVITY 0x8001305c -#pragma Aux_register(0x8001305c, name=>"io_i2c_slv0_clr_activity") - -// User extension aux register io_i2c_slv0_clr_stop_det -#define AR_IO_I2C_SLV0_CLR_STOP_DET 0x80013060 -#pragma Aux_register(0x80013060, name=>"io_i2c_slv0_clr_stop_det") - -// User extension aux register io_i2c_slv0_clr_start_det -#define AR_IO_I2C_SLV0_CLR_START_DET 0x80013064 -#pragma Aux_register(0x80013064, name=>"io_i2c_slv0_clr_start_det") - -// User extension aux register io_i2c_slv0_enable -#define AR_IO_I2C_SLV0_ENABLE 0x8001306c -#pragma Aux_register(0x8001306c, name=>"io_i2c_slv0_enable") - -// User extension aux register io_i2c_slv0_status -#define AR_IO_I2C_SLV0_STATUS 0x80013070 -#pragma Aux_register(0x80013070, name=>"io_i2c_slv0_status") - -// User extension aux register io_i2c_slv0_txflr -#define AR_IO_I2C_SLV0_TXFLR 0x80013074 -#pragma Aux_register(0x80013074, name=>"io_i2c_slv0_txflr") - -// User extension aux register io_i2c_slv0_rxflr -#define AR_IO_I2C_SLV0_RXFLR 0x80013078 -#pragma Aux_register(0x80013078, name=>"io_i2c_slv0_rxflr") - -// User extension aux register io_i2c_slv0_sda_hold -#define AR_IO_I2C_SLV0_SDA_HOLD 0x8001307c -#pragma Aux_register(0x8001307c, name=>"io_i2c_slv0_sda_hold") - -// User extension aux register io_i2c_slv0_tx_abrt_source -#define AR_IO_I2C_SLV0_TX_ABRT_SOURCE 0x80013080 -#pragma Aux_register(0x80013080, name=>"io_i2c_slv0_tx_abrt_source") - -// User extension aux register io_i2c_slv0_sda_setup -#define AR_IO_I2C_SLV0_SDA_SETUP 0x80013094 -#pragma Aux_register(0x80013094, name=>"io_i2c_slv0_sda_setup") - -// User extension aux register io_i2c_slv0_enable_status -#define AR_IO_I2C_SLV0_ENABLE_STATUS 0x8001309c -#pragma Aux_register(0x8001309c, name=>"io_i2c_slv0_enable_status") - -// User extension aux register io_i2c_slv0_fs_spklen -#define AR_IO_I2C_SLV0_FS_SPKLEN 0x800130a0 -#pragma Aux_register(0x800130a0, name=>"io_i2c_slv0_fs_spklen") - -// User extension aux register io_i2c_slv0_clr_restart_det -#define AR_IO_I2C_SLV0_CLR_RESTART_DET 0x800130a8 -#pragma Aux_register(0x800130a8, name=>"io_i2c_slv0_clr_restart_det") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_SPI_MST0_PRESENT 1 - -// User extension aux register io_spi_mst0_ctrlr0 -#define AR_IO_SPI_MST0_CTRLR0 0x80010000 -#pragma Aux_register(0x80010000, name=>"io_spi_mst0_ctrlr0") - -// User extension aux register io_spi_mst0_ctrlr1 -#define AR_IO_SPI_MST0_CTRLR1 0x80010001 -#pragma Aux_register(0x80010001, name=>"io_spi_mst0_ctrlr1") - -// User extension aux register io_spi_mst0_spien -#define AR_IO_SPI_MST0_SPIEN 0x80010002 -#pragma Aux_register(0x80010002, name=>"io_spi_mst0_spien") - -// User extension aux register io_spi_mst0_ser -#define AR_IO_SPI_MST0_SER 0x80010004 -#pragma Aux_register(0x80010004, name=>"io_spi_mst0_ser") - -// User extension aux register io_spi_mst0_baudr -#define AR_IO_SPI_MST0_BAUDR 0x80010005 -#pragma Aux_register(0x80010005, name=>"io_spi_mst0_baudr") - -// User extension aux register io_spi_mst0_txftlr -#define AR_IO_SPI_MST0_TXFTLR 0x80010006 -#pragma Aux_register(0x80010006, name=>"io_spi_mst0_txftlr") - -// User extension aux register io_spi_mst0_rxftlr -#define AR_IO_SPI_MST0_RXFTLR 0x80010007 -#pragma Aux_register(0x80010007, name=>"io_spi_mst0_rxftlr") - -// User extension aux register io_spi_mst0_txflr -#define AR_IO_SPI_MST0_TXFLR 0x80010008 -#pragma Aux_register(0x80010008, name=>"io_spi_mst0_txflr") - -// User extension aux register io_spi_mst0_rxflr -#define AR_IO_SPI_MST0_RXFLR 0x80010009 -#pragma Aux_register(0x80010009, name=>"io_spi_mst0_rxflr") - -// User extension aux register io_spi_mst0_sr -#define AR_IO_SPI_MST0_SR 0x8001000a -#pragma Aux_register(0x8001000a, name=>"io_spi_mst0_sr") - -// User extension aux register io_spi_mst0_imr -#define AR_IO_SPI_MST0_IMR 0x8001000b -#pragma Aux_register(0x8001000b, name=>"io_spi_mst0_imr") - -// User extension aux register io_spi_mst0_isr -#define AR_IO_SPI_MST0_ISR 0x8001000c -#pragma Aux_register(0x8001000c, name=>"io_spi_mst0_isr") - -// User extension aux register io_spi_mst0_risr -#define AR_IO_SPI_MST0_RISR 0x8001000d -#pragma Aux_register(0x8001000d, name=>"io_spi_mst0_risr") - -// User extension aux register io_spi_mst0_txoicr -#define AR_IO_SPI_MST0_TXOICR 0x8001000e -#pragma Aux_register(0x8001000e, name=>"io_spi_mst0_txoicr") - -// User extension aux register io_spi_mst0_rxoicr -#define AR_IO_SPI_MST0_RXOICR 0x8001000f -#pragma Aux_register(0x8001000f, name=>"io_spi_mst0_rxoicr") - -// User extension aux register io_spi_mst0_rxuicr -#define AR_IO_SPI_MST0_RXUICR 0x80010010 -#pragma Aux_register(0x80010010, name=>"io_spi_mst0_rxuicr") - -// User extension aux register io_spi_mst0_icr -#define AR_IO_SPI_MST0_ICR 0x80010012 -#pragma Aux_register(0x80010012, name=>"io_spi_mst0_icr") - -// User extension aux register io_spi_mst0_clken -#define AR_IO_SPI_MST0_CLKEN 0x80010016 -#pragma Aux_register(0x80010016, name=>"io_spi_mst0_clken") - -// User extension aux register io_spi_mst0_dr -#define AR_IO_SPI_MST0_DR 0x80010018 -#pragma Aux_register(0x80010018, name=>"io_spi_mst0_dr") - -// User extension aux register io_spi_mst0_rx_sample_dly -#define AR_IO_SPI_MST0_RX_SAMPLE_DLY 0x8001003c -#pragma Aux_register(0x8001003c, name=>"io_spi_mst0_rx_sample_dly") -#define APEX_COM_ARC_HARDWARE_DFSS_SUBSYS_BCR_PRESENT 1 - -// User extension aux register SUBSYS_BUILD -#define AR_SUBSYS_BUILD 0xf0 -#pragma Aux_register(0xf0, name=>"SUBSYS_BUILD") - -// User extension aux register SUBSYS_DSP_0_BUILD -#define AR_SUBSYS_DSP_0_BUILD 0xa00 -#pragma Aux_register(0xa00, name=>"SUBSYS_DSP_0_BUILD") - -// User extension aux register SUBSYS_DSP_0_CONFIG -#define AR_SUBSYS_DSP_0_CONFIG 0xa02 -#pragma Aux_register(0xa02, name=>"SUBSYS_DSP_0_CONFIG") - -// User extension aux register SUBSYS_IO_0_BUILD -#define AR_SUBSYS_IO_0_BUILD 0xa04 -#pragma Aux_register(0xa04, name=>"SUBSYS_IO_0_BUILD") - -// User extension aux register SUBSYS_IO_1_BUILD -#define AR_SUBSYS_IO_1_BUILD 0xa05 -#pragma Aux_register(0xa05, name=>"SUBSYS_IO_1_BUILD") - -// User extension aux register SUBSYS_IO_2_BUILD -#define AR_SUBSYS_IO_2_BUILD 0xa06 -#pragma Aux_register(0xa06, name=>"SUBSYS_IO_2_BUILD") - -// User extension aux register SUBSYS_UAUX_OFFSET -#define AR_SUBSYS_UAUX_OFFSET 0xa1e -#pragma Aux_register(0xa1e, name=>"SUBSYS_UAUX_OFFSET") - -// User extension aux register SUBSYS_APEX_OFFSET -#define AR_SUBSYS_APEX_OFFSET 0xa1f -#pragma Aux_register(0xa1f, name=>"SUBSYS_APEX_OFFSET") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_SPI_MST1_PRESENT 1 - -// User extension aux register io_spi_mst1_ctrlr0 -#define AR_IO_SPI_MST1_CTRLR0 0x80010100 -#pragma Aux_register(0x80010100, name=>"io_spi_mst1_ctrlr0") - -// User extension aux register io_spi_mst1_ctrlr1 -#define AR_IO_SPI_MST1_CTRLR1 0x80010101 -#pragma Aux_register(0x80010101, name=>"io_spi_mst1_ctrlr1") - -// User extension aux register io_spi_mst1_spien -#define AR_IO_SPI_MST1_SPIEN 0x80010102 -#pragma Aux_register(0x80010102, name=>"io_spi_mst1_spien") - -// User extension aux register io_spi_mst1_ser -#define AR_IO_SPI_MST1_SER 0x80010104 -#pragma Aux_register(0x80010104, name=>"io_spi_mst1_ser") - -// User extension aux register io_spi_mst1_baudr -#define AR_IO_SPI_MST1_BAUDR 0x80010105 -#pragma Aux_register(0x80010105, name=>"io_spi_mst1_baudr") - -// User extension aux register io_spi_mst1_txftlr -#define AR_IO_SPI_MST1_TXFTLR 0x80010106 -#pragma Aux_register(0x80010106, name=>"io_spi_mst1_txftlr") - -// User extension aux register io_spi_mst1_rxftlr -#define AR_IO_SPI_MST1_RXFTLR 0x80010107 -#pragma Aux_register(0x80010107, name=>"io_spi_mst1_rxftlr") - -// User extension aux register io_spi_mst1_txflr -#define AR_IO_SPI_MST1_TXFLR 0x80010108 -#pragma Aux_register(0x80010108, name=>"io_spi_mst1_txflr") - -// User extension aux register io_spi_mst1_rxflr -#define AR_IO_SPI_MST1_RXFLR 0x80010109 -#pragma Aux_register(0x80010109, name=>"io_spi_mst1_rxflr") - -// User extension aux register io_spi_mst1_sr -#define AR_IO_SPI_MST1_SR 0x8001010a -#pragma Aux_register(0x8001010a, name=>"io_spi_mst1_sr") - -// User extension aux register io_spi_mst1_imr -#define AR_IO_SPI_MST1_IMR 0x8001010b -#pragma Aux_register(0x8001010b, name=>"io_spi_mst1_imr") - -// User extension aux register io_spi_mst1_isr -#define AR_IO_SPI_MST1_ISR 0x8001010c -#pragma Aux_register(0x8001010c, name=>"io_spi_mst1_isr") - -// User extension aux register io_spi_mst1_risr -#define AR_IO_SPI_MST1_RISR 0x8001010d -#pragma Aux_register(0x8001010d, name=>"io_spi_mst1_risr") - -// User extension aux register io_spi_mst1_txoicr -#define AR_IO_SPI_MST1_TXOICR 0x8001010e -#pragma Aux_register(0x8001010e, name=>"io_spi_mst1_txoicr") - -// User extension aux register io_spi_mst1_rxoicr -#define AR_IO_SPI_MST1_RXOICR 0x8001010f -#pragma Aux_register(0x8001010f, name=>"io_spi_mst1_rxoicr") - -// User extension aux register io_spi_mst1_rxuicr -#define AR_IO_SPI_MST1_RXUICR 0x80010110 -#pragma Aux_register(0x80010110, name=>"io_spi_mst1_rxuicr") - -// User extension aux register io_spi_mst1_icr -#define AR_IO_SPI_MST1_ICR 0x80010112 -#pragma Aux_register(0x80010112, name=>"io_spi_mst1_icr") - -// User extension aux register io_spi_mst1_clken -#define AR_IO_SPI_MST1_CLKEN 0x80010116 -#pragma Aux_register(0x80010116, name=>"io_spi_mst1_clken") - -// User extension aux register io_spi_mst1_dr -#define AR_IO_SPI_MST1_DR 0x80010118 -#pragma Aux_register(0x80010118, name=>"io_spi_mst1_dr") - -// User extension aux register io_spi_mst1_rx_sample_dly -#define AR_IO_SPI_MST1_RX_SAMPLE_DLY 0x8001013c -#pragma Aux_register(0x8001013c, name=>"io_spi_mst1_rx_sample_dly") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_SPI_MST2_PRESENT 1 - -// User extension aux register io_spi_mst2_ctrlr0 -#define AR_IO_SPI_MST2_CTRLR0 0x80010200 -#pragma Aux_register(0x80010200, name=>"io_spi_mst2_ctrlr0") - -// User extension aux register io_spi_mst2_ctrlr1 -#define AR_IO_SPI_MST2_CTRLR1 0x80010201 -#pragma Aux_register(0x80010201, name=>"io_spi_mst2_ctrlr1") - -// User extension aux register io_spi_mst2_spien -#define AR_IO_SPI_MST2_SPIEN 0x80010202 -#pragma Aux_register(0x80010202, name=>"io_spi_mst2_spien") - -// User extension aux register io_spi_mst2_ser -#define AR_IO_SPI_MST2_SER 0x80010204 -#pragma Aux_register(0x80010204, name=>"io_spi_mst2_ser") - -// User extension aux register io_spi_mst2_baudr -#define AR_IO_SPI_MST2_BAUDR 0x80010205 -#pragma Aux_register(0x80010205, name=>"io_spi_mst2_baudr") - -// User extension aux register io_spi_mst2_txftlr -#define AR_IO_SPI_MST2_TXFTLR 0x80010206 -#pragma Aux_register(0x80010206, name=>"io_spi_mst2_txftlr") - -// User extension aux register io_spi_mst2_rxftlr -#define AR_IO_SPI_MST2_RXFTLR 0x80010207 -#pragma Aux_register(0x80010207, name=>"io_spi_mst2_rxftlr") - -// User extension aux register io_spi_mst2_txflr -#define AR_IO_SPI_MST2_TXFLR 0x80010208 -#pragma Aux_register(0x80010208, name=>"io_spi_mst2_txflr") - -// User extension aux register io_spi_mst2_rxflr -#define AR_IO_SPI_MST2_RXFLR 0x80010209 -#pragma Aux_register(0x80010209, name=>"io_spi_mst2_rxflr") - -// User extension aux register io_spi_mst2_sr -#define AR_IO_SPI_MST2_SR 0x8001020a -#pragma Aux_register(0x8001020a, name=>"io_spi_mst2_sr") - -// User extension aux register io_spi_mst2_imr -#define AR_IO_SPI_MST2_IMR 0x8001020b -#pragma Aux_register(0x8001020b, name=>"io_spi_mst2_imr") - -// User extension aux register io_spi_mst2_isr -#define AR_IO_SPI_MST2_ISR 0x8001020c -#pragma Aux_register(0x8001020c, name=>"io_spi_mst2_isr") - -// User extension aux register io_spi_mst2_risr -#define AR_IO_SPI_MST2_RISR 0x8001020d -#pragma Aux_register(0x8001020d, name=>"io_spi_mst2_risr") - -// User extension aux register io_spi_mst2_txoicr -#define AR_IO_SPI_MST2_TXOICR 0x8001020e -#pragma Aux_register(0x8001020e, name=>"io_spi_mst2_txoicr") - -// User extension aux register io_spi_mst2_rxoicr -#define AR_IO_SPI_MST2_RXOICR 0x8001020f -#pragma Aux_register(0x8001020f, name=>"io_spi_mst2_rxoicr") - -// User extension aux register io_spi_mst2_rxuicr -#define AR_IO_SPI_MST2_RXUICR 0x80010210 -#pragma Aux_register(0x80010210, name=>"io_spi_mst2_rxuicr") - -// User extension aux register io_spi_mst2_icr -#define AR_IO_SPI_MST2_ICR 0x80010212 -#pragma Aux_register(0x80010212, name=>"io_spi_mst2_icr") - -// User extension aux register io_spi_mst2_clken -#define AR_IO_SPI_MST2_CLKEN 0x80010216 -#pragma Aux_register(0x80010216, name=>"io_spi_mst2_clken") - -// User extension aux register io_spi_mst2_dr -#define AR_IO_SPI_MST2_DR 0x80010218 -#pragma Aux_register(0x80010218, name=>"io_spi_mst2_dr") - -// User extension aux register io_spi_mst2_rx_sample_dly -#define AR_IO_SPI_MST2_RX_SAMPLE_DLY 0x8001023c -#pragma Aux_register(0x8001023c, name=>"io_spi_mst2_rx_sample_dly") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_SPI_SLV0_PRESENT 1 - -// User extension aux register io_spi_slv0_ctrlr0 -#define AR_IO_SPI_SLV0_CTRLR0 0x80011000 -#pragma Aux_register(0x80011000, name=>"io_spi_slv0_ctrlr0") - -// User extension aux register io_spi_slv0_spien -#define AR_IO_SPI_SLV0_SPIEN 0x80011002 -#pragma Aux_register(0x80011002, name=>"io_spi_slv0_spien") - -// User extension aux register io_spi_slv0_txftlr -#define AR_IO_SPI_SLV0_TXFTLR 0x80011006 -#pragma Aux_register(0x80011006, name=>"io_spi_slv0_txftlr") - -// User extension aux register io_spi_slv0_rxftlr -#define AR_IO_SPI_SLV0_RXFTLR 0x80011007 -#pragma Aux_register(0x80011007, name=>"io_spi_slv0_rxftlr") - -// User extension aux register io_spi_slv0_txflr -#define AR_IO_SPI_SLV0_TXFLR 0x80011008 -#pragma Aux_register(0x80011008, name=>"io_spi_slv0_txflr") - -// User extension aux register io_spi_slv0_rxflr -#define AR_IO_SPI_SLV0_RXFLR 0x80011009 -#pragma Aux_register(0x80011009, name=>"io_spi_slv0_rxflr") - -// User extension aux register io_spi_slv0_sr -#define AR_IO_SPI_SLV0_SR 0x8001100a -#pragma Aux_register(0x8001100a, name=>"io_spi_slv0_sr") - -// User extension aux register io_spi_slv0_imr -#define AR_IO_SPI_SLV0_IMR 0x8001100b -#pragma Aux_register(0x8001100b, name=>"io_spi_slv0_imr") - -// User extension aux register io_spi_slv0_isr -#define AR_IO_SPI_SLV0_ISR 0x8001100c -#pragma Aux_register(0x8001100c, name=>"io_spi_slv0_isr") - -// User extension aux register io_spi_slv0_risr -#define AR_IO_SPI_SLV0_RISR 0x8001100d -#pragma Aux_register(0x8001100d, name=>"io_spi_slv0_risr") - -// User extension aux register io_spi_slv0_txoicr -#define AR_IO_SPI_SLV0_TXOICR 0x8001100e -#pragma Aux_register(0x8001100e, name=>"io_spi_slv0_txoicr") - -// User extension aux register io_spi_slv0_rxoicr -#define AR_IO_SPI_SLV0_RXOICR 0x8001100f -#pragma Aux_register(0x8001100f, name=>"io_spi_slv0_rxoicr") - -// User extension aux register io_spi_slv0_rxuicr -#define AR_IO_SPI_SLV0_RXUICR 0x80011010 -#pragma Aux_register(0x80011010, name=>"io_spi_slv0_rxuicr") - -// User extension aux register io_spi_slv0_icr -#define AR_IO_SPI_SLV0_ICR 0x80011012 -#pragma Aux_register(0x80011012, name=>"io_spi_slv0_icr") - -// User extension aux register io_spi_slv0_clken -#define AR_IO_SPI_SLV0_CLKEN 0x80011016 -#pragma Aux_register(0x80011016, name=>"io_spi_slv0_clken") - -// User extension aux register io_spi_slv0_dr -#define AR_IO_SPI_SLV0_DR 0x80011018 -#pragma Aux_register(0x80011018, name=>"io_spi_slv0_dr") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_GPIO1_PRESENT 1 - -// User extension aux register io_gpio1_debounce -#define AR_IO_GPIO1_DEBOUNCE 0x80017148 -#pragma Aux_register(0x80017148, name=>"io_gpio1_debounce") - -// User extension aux register io_gpio1_clken -#define AR_IO_GPIO1_CLKEN 0x80017180 -#pragma Aux_register(0x80017180, name=>"io_gpio1_clken") - -// User extension aux register io_gpio1_swporta_dr -#define AR_IO_GPIO1_SWPORTA_DR 0x80017100 -#pragma Aux_register(0x80017100, name=>"io_gpio1_swporta_dr") - -// User extension aux register io_gpio1_swporta_ddr -#define AR_IO_GPIO1_SWPORTA_DDR 0x80017104 -#pragma Aux_register(0x80017104, name=>"io_gpio1_swporta_ddr") - -// User extension aux register io_gpio1_inten -#define AR_IO_GPIO1_INTEN 0x80017130 -#pragma Aux_register(0x80017130, name=>"io_gpio1_inten") - -// User extension aux register io_gpio1_intmask -#define AR_IO_GPIO1_INTMASK 0x80017134 -#pragma Aux_register(0x80017134, name=>"io_gpio1_intmask") - -// User extension aux register io_gpio1_inttype_level -#define AR_IO_GPIO1_INTTYPE_LEVEL 0x80017138 -#pragma Aux_register(0x80017138, name=>"io_gpio1_inttype_level") - -// User extension aux register io_gpio1_int_polarity -#define AR_IO_GPIO1_INT_POLARITY 0x8001713c -#pragma Aux_register(0x8001713c, name=>"io_gpio1_int_polarity") - -// User extension aux register io_gpio1_intstatus -#define AR_IO_GPIO1_INTSTATUS 0x80017140 -#pragma Aux_register(0x80017140, name=>"io_gpio1_intstatus") - -// User extension aux register io_gpio1_raw_intstatus -#define AR_IO_GPIO1_RAW_INTSTATUS 0x80017144 -#pragma Aux_register(0x80017144, name=>"io_gpio1_raw_intstatus") - -// User extension aux register io_gpio1_porta_eoi -#define AR_IO_GPIO1_PORTA_EOI 0x8001714c -#pragma Aux_register(0x8001714c, name=>"io_gpio1_porta_eoi") - -// User extension aux register io_gpio1_ext_porta -#define AR_IO_GPIO1_EXT_PORTA 0x80017150 -#pragma Aux_register(0x80017150, name=>"io_gpio1_ext_porta") - -// User extension aux register io_gpio1_ls_sync -#define AR_IO_GPIO1_LS_SYNC 0x80017160 -#pragma Aux_register(0x80017160, name=>"io_gpio1_ls_sync") - -// User extension aux register io_gpio1_int_bothedge -#define AR_IO_GPIO1_INT_BOTHEDGE 0x80017168 -#pragma Aux_register(0x80017168, name=>"io_gpio1_int_bothedge") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_GPIO2_PRESENT 1 - -// User extension aux register io_gpio2_debounce -#define AR_IO_GPIO2_DEBOUNCE 0x80017248 -#pragma Aux_register(0x80017248, name=>"io_gpio2_debounce") - -// User extension aux register io_gpio2_clken -#define AR_IO_GPIO2_CLKEN 0x80017280 -#pragma Aux_register(0x80017280, name=>"io_gpio2_clken") - -// User extension aux register io_gpio2_swporta_dr -#define AR_IO_GPIO2_SWPORTA_DR 0x80017200 -#pragma Aux_register(0x80017200, name=>"io_gpio2_swporta_dr") - -// User extension aux register io_gpio2_swporta_ddr -#define AR_IO_GPIO2_SWPORTA_DDR 0x80017204 -#pragma Aux_register(0x80017204, name=>"io_gpio2_swporta_ddr") - -// User extension aux register io_gpio2_inten -#define AR_IO_GPIO2_INTEN 0x80017230 -#pragma Aux_register(0x80017230, name=>"io_gpio2_inten") - -// User extension aux register io_gpio2_intmask -#define AR_IO_GPIO2_INTMASK 0x80017234 -#pragma Aux_register(0x80017234, name=>"io_gpio2_intmask") - -// User extension aux register io_gpio2_inttype_level -#define AR_IO_GPIO2_INTTYPE_LEVEL 0x80017238 -#pragma Aux_register(0x80017238, name=>"io_gpio2_inttype_level") - -// User extension aux register io_gpio2_int_polarity -#define AR_IO_GPIO2_INT_POLARITY 0x8001723c -#pragma Aux_register(0x8001723c, name=>"io_gpio2_int_polarity") - -// User extension aux register io_gpio2_intstatus -#define AR_IO_GPIO2_INTSTATUS 0x80017240 -#pragma Aux_register(0x80017240, name=>"io_gpio2_intstatus") - -// User extension aux register io_gpio2_raw_intstatus -#define AR_IO_GPIO2_RAW_INTSTATUS 0x80017244 -#pragma Aux_register(0x80017244, name=>"io_gpio2_raw_intstatus") - -// User extension aux register io_gpio2_porta_eoi -#define AR_IO_GPIO2_PORTA_EOI 0x8001724c -#pragma Aux_register(0x8001724c, name=>"io_gpio2_porta_eoi") - -// User extension aux register io_gpio2_ext_porta -#define AR_IO_GPIO2_EXT_PORTA 0x80017250 -#pragma Aux_register(0x80017250, name=>"io_gpio2_ext_porta") - -// User extension aux register io_gpio2_ls_sync -#define AR_IO_GPIO2_LS_SYNC 0x80017260 -#pragma Aux_register(0x80017260, name=>"io_gpio2_ls_sync") - -// User extension aux register io_gpio2_int_bothedge -#define AR_IO_GPIO2_INT_BOTHEDGE 0x80017268 -#pragma Aux_register(0x80017268, name=>"io_gpio2_int_bothedge") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2C_MST1_PRESENT 1 - -// User extension aux register io_i2c_mst1_clken -#define AR_IO_I2C_MST1_CLKEN 0x800121c0 -#pragma Aux_register(0x800121c0, name=>"io_i2c_mst1_clken") - -// User extension aux register io_i2c_mst1_con -#define AR_IO_I2C_MST1_CON 0x80012100 -#pragma Aux_register(0x80012100, name=>"io_i2c_mst1_con") - -// User extension aux register io_i2c_mst1_tar -#define AR_IO_I2C_MST1_TAR 0x80012104 -#pragma Aux_register(0x80012104, name=>"io_i2c_mst1_tar") - -// User extension aux register io_i2c_mst1_data_cmd -#define AR_IO_I2C_MST1_DATA_CMD 0x80012110 -#pragma Aux_register(0x80012110, name=>"io_i2c_mst1_data_cmd") - -// User extension aux register io_i2c_mst1_ss_scl_hcnt -#define AR_IO_I2C_MST1_SS_SCL_HCNT 0x80012114 -#pragma Aux_register(0x80012114, name=>"io_i2c_mst1_ss_scl_hcnt") - -// User extension aux register io_i2c_mst1_ss_scl_lcnt -#define AR_IO_I2C_MST1_SS_SCL_LCNT 0x80012118 -#pragma Aux_register(0x80012118, name=>"io_i2c_mst1_ss_scl_lcnt") - -// User extension aux register io_i2c_mst1_fs_scl_hcnt -#define AR_IO_I2C_MST1_FS_SCL_HCNT 0x8001211c -#pragma Aux_register(0x8001211c, name=>"io_i2c_mst1_fs_scl_hcnt") - -// User extension aux register io_i2c_mst1_fs_scl_lcnt -#define AR_IO_I2C_MST1_FS_SCL_LCNT 0x80012120 -#pragma Aux_register(0x80012120, name=>"io_i2c_mst1_fs_scl_lcnt") - -// User extension aux register io_i2c_mst1_intr_stat -#define AR_IO_I2C_MST1_INTR_STAT 0x8001212c -#pragma Aux_register(0x8001212c, name=>"io_i2c_mst1_intr_stat") - -// User extension aux register io_i2c_mst1_intr_mask -#define AR_IO_I2C_MST1_INTR_MASK 0x80012130 -#pragma Aux_register(0x80012130, name=>"io_i2c_mst1_intr_mask") - -// User extension aux register io_i2c_mst1_raw_intr_stat -#define AR_IO_I2C_MST1_RAW_INTR_STAT 0x80012134 -#pragma Aux_register(0x80012134, name=>"io_i2c_mst1_raw_intr_stat") - -// User extension aux register io_i2c_mst1_rx_tl -#define AR_IO_I2C_MST1_RX_TL 0x80012138 -#pragma Aux_register(0x80012138, name=>"io_i2c_mst1_rx_tl") - -// User extension aux register io_i2c_mst1_tx_tl -#define AR_IO_I2C_MST1_TX_TL 0x8001213c -#pragma Aux_register(0x8001213c, name=>"io_i2c_mst1_tx_tl") - -// User extension aux register io_i2c_mst1_clr_intr -#define AR_IO_I2C_MST1_CLR_INTR 0x80012140 -#pragma Aux_register(0x80012140, name=>"io_i2c_mst1_clr_intr") - -// User extension aux register io_i2c_mst1_clr_rx_under -#define AR_IO_I2C_MST1_CLR_RX_UNDER 0x80012144 -#pragma Aux_register(0x80012144, name=>"io_i2c_mst1_clr_rx_under") - -// User extension aux register io_i2c_mst1_clr_rx_over -#define AR_IO_I2C_MST1_CLR_RX_OVER 0x80012148 -#pragma Aux_register(0x80012148, name=>"io_i2c_mst1_clr_rx_over") - -// User extension aux register io_i2c_mst1_clr_tx_over -#define AR_IO_I2C_MST1_CLR_TX_OVER 0x8001214c -#pragma Aux_register(0x8001214c, name=>"io_i2c_mst1_clr_tx_over") - -// User extension aux register io_i2c_mst1_clr_tx_abrt -#define AR_IO_I2C_MST1_CLR_TX_ABRT 0x80012154 -#pragma Aux_register(0x80012154, name=>"io_i2c_mst1_clr_tx_abrt") - -// User extension aux register io_i2c_mst1_clr_activity -#define AR_IO_I2C_MST1_CLR_ACTIVITY 0x8001215c -#pragma Aux_register(0x8001215c, name=>"io_i2c_mst1_clr_activity") - -// User extension aux register io_i2c_mst1_clr_stop_det -#define AR_IO_I2C_MST1_CLR_STOP_DET 0x80012160 -#pragma Aux_register(0x80012160, name=>"io_i2c_mst1_clr_stop_det") - -// User extension aux register io_i2c_mst1_clr_start_det -#define AR_IO_I2C_MST1_CLR_START_DET 0x80012164 -#pragma Aux_register(0x80012164, name=>"io_i2c_mst1_clr_start_det") - -// User extension aux register io_i2c_mst1_enable -#define AR_IO_I2C_MST1_ENABLE 0x8001216c -#pragma Aux_register(0x8001216c, name=>"io_i2c_mst1_enable") - -// User extension aux register io_i2c_mst1_status -#define AR_IO_I2C_MST1_STATUS 0x80012170 -#pragma Aux_register(0x80012170, name=>"io_i2c_mst1_status") - -// User extension aux register io_i2c_mst1_txflr -#define AR_IO_I2C_MST1_TXFLR 0x80012174 -#pragma Aux_register(0x80012174, name=>"io_i2c_mst1_txflr") - -// User extension aux register io_i2c_mst1_rxflr -#define AR_IO_I2C_MST1_RXFLR 0x80012178 -#pragma Aux_register(0x80012178, name=>"io_i2c_mst1_rxflr") - -// User extension aux register io_i2c_mst1_sda_hold -#define AR_IO_I2C_MST1_SDA_HOLD 0x8001217c -#pragma Aux_register(0x8001217c, name=>"io_i2c_mst1_sda_hold") - -// User extension aux register io_i2c_mst1_tx_abrt_source -#define AR_IO_I2C_MST1_TX_ABRT_SOURCE 0x80012180 -#pragma Aux_register(0x80012180, name=>"io_i2c_mst1_tx_abrt_source") - -// User extension aux register io_i2c_mst1_enable_status -#define AR_IO_I2C_MST1_ENABLE_STATUS 0x8001219c -#pragma Aux_register(0x8001219c, name=>"io_i2c_mst1_enable_status") - -// User extension aux register io_i2c_mst1_fs_spklen -#define AR_IO_I2C_MST1_FS_SPKLEN 0x800121a0 -#pragma Aux_register(0x800121a0, name=>"io_i2c_mst1_fs_spklen") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2C_MST2_PRESENT 1 - -// User extension aux register io_i2c_mst2_clken -#define AR_IO_I2C_MST2_CLKEN 0x800122c0 -#pragma Aux_register(0x800122c0, name=>"io_i2c_mst2_clken") - -// User extension aux register io_i2c_mst2_con -#define AR_IO_I2C_MST2_CON 0x80012200 -#pragma Aux_register(0x80012200, name=>"io_i2c_mst2_con") - -// User extension aux register io_i2c_mst2_tar -#define AR_IO_I2C_MST2_TAR 0x80012204 -#pragma Aux_register(0x80012204, name=>"io_i2c_mst2_tar") - -// User extension aux register io_i2c_mst2_data_cmd -#define AR_IO_I2C_MST2_DATA_CMD 0x80012210 -#pragma Aux_register(0x80012210, name=>"io_i2c_mst2_data_cmd") - -// User extension aux register io_i2c_mst2_ss_scl_hcnt -#define AR_IO_I2C_MST2_SS_SCL_HCNT 0x80012214 -#pragma Aux_register(0x80012214, name=>"io_i2c_mst2_ss_scl_hcnt") - -// User extension aux register io_i2c_mst2_ss_scl_lcnt -#define AR_IO_I2C_MST2_SS_SCL_LCNT 0x80012218 -#pragma Aux_register(0x80012218, name=>"io_i2c_mst2_ss_scl_lcnt") - -// User extension aux register io_i2c_mst2_fs_scl_hcnt -#define AR_IO_I2C_MST2_FS_SCL_HCNT 0x8001221c -#pragma Aux_register(0x8001221c, name=>"io_i2c_mst2_fs_scl_hcnt") - -// User extension aux register io_i2c_mst2_fs_scl_lcnt -#define AR_IO_I2C_MST2_FS_SCL_LCNT 0x80012220 -#pragma Aux_register(0x80012220, name=>"io_i2c_mst2_fs_scl_lcnt") - -// User extension aux register io_i2c_mst2_intr_stat -#define AR_IO_I2C_MST2_INTR_STAT 0x8001222c -#pragma Aux_register(0x8001222c, name=>"io_i2c_mst2_intr_stat") - -// User extension aux register io_i2c_mst2_intr_mask -#define AR_IO_I2C_MST2_INTR_MASK 0x80012230 -#pragma Aux_register(0x80012230, name=>"io_i2c_mst2_intr_mask") - -// User extension aux register io_i2c_mst2_raw_intr_stat -#define AR_IO_I2C_MST2_RAW_INTR_STAT 0x80012234 -#pragma Aux_register(0x80012234, name=>"io_i2c_mst2_raw_intr_stat") - -// User extension aux register io_i2c_mst2_rx_tl -#define AR_IO_I2C_MST2_RX_TL 0x80012238 -#pragma Aux_register(0x80012238, name=>"io_i2c_mst2_rx_tl") - -// User extension aux register io_i2c_mst2_tx_tl -#define AR_IO_I2C_MST2_TX_TL 0x8001223c -#pragma Aux_register(0x8001223c, name=>"io_i2c_mst2_tx_tl") - -// User extension aux register io_i2c_mst2_clr_intr -#define AR_IO_I2C_MST2_CLR_INTR 0x80012240 -#pragma Aux_register(0x80012240, name=>"io_i2c_mst2_clr_intr") - -// User extension aux register io_i2c_mst2_clr_rx_under -#define AR_IO_I2C_MST2_CLR_RX_UNDER 0x80012244 -#pragma Aux_register(0x80012244, name=>"io_i2c_mst2_clr_rx_under") - -// User extension aux register io_i2c_mst2_clr_rx_over -#define AR_IO_I2C_MST2_CLR_RX_OVER 0x80012248 -#pragma Aux_register(0x80012248, name=>"io_i2c_mst2_clr_rx_over") - -// User extension aux register io_i2c_mst2_clr_tx_over -#define AR_IO_I2C_MST2_CLR_TX_OVER 0x8001224c -#pragma Aux_register(0x8001224c, name=>"io_i2c_mst2_clr_tx_over") - -// User extension aux register io_i2c_mst2_clr_tx_abrt -#define AR_IO_I2C_MST2_CLR_TX_ABRT 0x80012254 -#pragma Aux_register(0x80012254, name=>"io_i2c_mst2_clr_tx_abrt") - -// User extension aux register io_i2c_mst2_clr_activity -#define AR_IO_I2C_MST2_CLR_ACTIVITY 0x8001225c -#pragma Aux_register(0x8001225c, name=>"io_i2c_mst2_clr_activity") - -// User extension aux register io_i2c_mst2_clr_stop_det -#define AR_IO_I2C_MST2_CLR_STOP_DET 0x80012260 -#pragma Aux_register(0x80012260, name=>"io_i2c_mst2_clr_stop_det") - -// User extension aux register io_i2c_mst2_clr_start_det -#define AR_IO_I2C_MST2_CLR_START_DET 0x80012264 -#pragma Aux_register(0x80012264, name=>"io_i2c_mst2_clr_start_det") - -// User extension aux register io_i2c_mst2_enable -#define AR_IO_I2C_MST2_ENABLE 0x8001226c -#pragma Aux_register(0x8001226c, name=>"io_i2c_mst2_enable") - -// User extension aux register io_i2c_mst2_status -#define AR_IO_I2C_MST2_STATUS 0x80012270 -#pragma Aux_register(0x80012270, name=>"io_i2c_mst2_status") - -// User extension aux register io_i2c_mst2_txflr -#define AR_IO_I2C_MST2_TXFLR 0x80012274 -#pragma Aux_register(0x80012274, name=>"io_i2c_mst2_txflr") - -// User extension aux register io_i2c_mst2_rxflr -#define AR_IO_I2C_MST2_RXFLR 0x80012278 -#pragma Aux_register(0x80012278, name=>"io_i2c_mst2_rxflr") - -// User extension aux register io_i2c_mst2_sda_hold -#define AR_IO_I2C_MST2_SDA_HOLD 0x8001227c -#pragma Aux_register(0x8001227c, name=>"io_i2c_mst2_sda_hold") - -// User extension aux register io_i2c_mst2_tx_abrt_source -#define AR_IO_I2C_MST2_TX_ABRT_SOURCE 0x80012280 -#pragma Aux_register(0x80012280, name=>"io_i2c_mst2_tx_abrt_source") - -// User extension aux register io_i2c_mst2_enable_status -#define AR_IO_I2C_MST2_ENABLE_STATUS 0x8001229c -#pragma Aux_register(0x8001229c, name=>"io_i2c_mst2_enable_status") - -// User extension aux register io_i2c_mst2_fs_spklen -#define AR_IO_I2C_MST2_FS_SPKLEN 0x800122a0 -#pragma Aux_register(0x800122a0, name=>"io_i2c_mst2_fs_spklen") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_UART0_PRESENT 1 - -// User extension aux register io_uart0_clken -#define AR_IO_UART0_CLKEN 0x800140c0 -#pragma Aux_register(0x800140c0, name=>"io_uart0_clken") - -// User extension aux register io_uart0_rbr_thr_dll -#define AR_IO_UART0_RBR_THR_DLL 0x80014000 -#pragma Aux_register(0x80014000, name=>"io_uart0_rbr_thr_dll") - -// User extension aux register io_uart0_ier_dlh -#define AR_IO_UART0_IER_DLH 0x80014004 -#pragma Aux_register(0x80014004, name=>"io_uart0_ier_dlh") - -// User extension aux register io_uart0_iir_fcr -#define AR_IO_UART0_IIR_FCR 0x80014008 -#pragma Aux_register(0x80014008, name=>"io_uart0_iir_fcr") - -// User extension aux register io_uart0_lcr -#define AR_IO_UART0_LCR 0x8001400c -#pragma Aux_register(0x8001400c, name=>"io_uart0_lcr") - -// User extension aux register io_uart0_mcr -#define AR_IO_UART0_MCR 0x80014010 -#pragma Aux_register(0x80014010, name=>"io_uart0_mcr") - -// User extension aux register io_uart0_lsr -#define AR_IO_UART0_LSR 0x80014014 -#pragma Aux_register(0x80014014, name=>"io_uart0_lsr") - -// User extension aux register io_uart0_msr -#define AR_IO_UART0_MSR 0x80014018 -#pragma Aux_register(0x80014018, name=>"io_uart0_msr") - -// User extension aux register io_uart0_usr -#define AR_IO_UART0_USR 0x8001407c -#pragma Aux_register(0x8001407c, name=>"io_uart0_usr") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_UART1_PRESENT 1 - -// User extension aux register io_uart1_clken -#define AR_IO_UART1_CLKEN 0x800141c0 -#pragma Aux_register(0x800141c0, name=>"io_uart1_clken") - -// User extension aux register io_uart1_rbr_thr_dll -#define AR_IO_UART1_RBR_THR_DLL 0x80014100 -#pragma Aux_register(0x80014100, name=>"io_uart1_rbr_thr_dll") - -// User extension aux register io_uart1_ier_dlh -#define AR_IO_UART1_IER_DLH 0x80014104 -#pragma Aux_register(0x80014104, name=>"io_uart1_ier_dlh") - -// User extension aux register io_uart1_iir_fcr -#define AR_IO_UART1_IIR_FCR 0x80014108 -#pragma Aux_register(0x80014108, name=>"io_uart1_iir_fcr") - -// User extension aux register io_uart1_lcr -#define AR_IO_UART1_LCR 0x8001410c -#pragma Aux_register(0x8001410c, name=>"io_uart1_lcr") - -// User extension aux register io_uart1_mcr -#define AR_IO_UART1_MCR 0x80014110 -#pragma Aux_register(0x80014110, name=>"io_uart1_mcr") - -// User extension aux register io_uart1_lsr -#define AR_IO_UART1_LSR 0x80014114 -#pragma Aux_register(0x80014114, name=>"io_uart1_lsr") - -// User extension aux register io_uart1_msr -#define AR_IO_UART1_MSR 0x80014118 -#pragma Aux_register(0x80014118, name=>"io_uart1_msr") - -// User extension aux register io_uart1_usr -#define AR_IO_UART1_USR 0x8001417c -#pragma Aux_register(0x8001417c, name=>"io_uart1_usr") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_UART2_PRESENT 1 - -// User extension aux register io_uart2_clken -#define AR_IO_UART2_CLKEN 0x800142c0 -#pragma Aux_register(0x800142c0, name=>"io_uart2_clken") - -// User extension aux register io_uart2_rbr_thr_dll -#define AR_IO_UART2_RBR_THR_DLL 0x80014200 -#pragma Aux_register(0x80014200, name=>"io_uart2_rbr_thr_dll") - -// User extension aux register io_uart2_ier_dlh -#define AR_IO_UART2_IER_DLH 0x80014204 -#pragma Aux_register(0x80014204, name=>"io_uart2_ier_dlh") - -// User extension aux register io_uart2_iir_fcr -#define AR_IO_UART2_IIR_FCR 0x80014208 -#pragma Aux_register(0x80014208, name=>"io_uart2_iir_fcr") - -// User extension aux register io_uart2_lcr -#define AR_IO_UART2_LCR 0x8001420c -#pragma Aux_register(0x8001420c, name=>"io_uart2_lcr") - -// User extension aux register io_uart2_mcr -#define AR_IO_UART2_MCR 0x80014210 -#pragma Aux_register(0x80014210, name=>"io_uart2_mcr") - -// User extension aux register io_uart2_lsr -#define AR_IO_UART2_LSR 0x80014214 -#pragma Aux_register(0x80014214, name=>"io_uart2_lsr") - -// User extension aux register io_uart2_msr -#define AR_IO_UART2_MSR 0x80014218 -#pragma Aux_register(0x80014218, name=>"io_uart2_msr") - -// User extension aux register io_uart2_usr -#define AR_IO_UART2_USR 0x8001427c -#pragma Aux_register(0x8001427c, name=>"io_uart2_usr") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_UART3_PRESENT 1 - -// User extension aux register io_uart3_clken -#define AR_IO_UART3_CLKEN 0x800143c0 -#pragma Aux_register(0x800143c0, name=>"io_uart3_clken") - -// User extension aux register io_uart3_rbr_thr_dll -#define AR_IO_UART3_RBR_THR_DLL 0x80014300 -#pragma Aux_register(0x80014300, name=>"io_uart3_rbr_thr_dll") - -// User extension aux register io_uart3_ier_dlh -#define AR_IO_UART3_IER_DLH 0x80014304 -#pragma Aux_register(0x80014304, name=>"io_uart3_ier_dlh") - -// User extension aux register io_uart3_iir_fcr -#define AR_IO_UART3_IIR_FCR 0x80014308 -#pragma Aux_register(0x80014308, name=>"io_uart3_iir_fcr") - -// User extension aux register io_uart3_lcr -#define AR_IO_UART3_LCR 0x8001430c -#pragma Aux_register(0x8001430c, name=>"io_uart3_lcr") - -// User extension aux register io_uart3_mcr -#define AR_IO_UART3_MCR 0x80014310 -#pragma Aux_register(0x80014310, name=>"io_uart3_mcr") - -// User extension aux register io_uart3_lsr -#define AR_IO_UART3_LSR 0x80014314 -#pragma Aux_register(0x80014314, name=>"io_uart3_lsr") - -// User extension aux register io_uart3_msr -#define AR_IO_UART3_MSR 0x80014318 -#pragma Aux_register(0x80014318, name=>"io_uart3_msr") - -// User extension aux register io_uart3_usr -#define AR_IO_UART3_USR 0x8001437c -#pragma Aux_register(0x8001437c, name=>"io_uart3_usr") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2S_RX_MST0_PRESENT 1 - -// User extension aux register io_i2s_rx_mst0_ier -#define AR_IO_I2S_RX_MST0_IER 0x8001a000 -#pragma Aux_register(0x8001a000, name=>"io_i2s_rx_mst0_ier") - -// User extension aux register io_i2s_rx_mst0_irer -#define AR_IO_I2S_RX_MST0_IRER 0x8001a004 -#pragma Aux_register(0x8001a004, name=>"io_i2s_rx_mst0_irer") - -// User extension aux register io_i2s_rx_mst0_cer -#define AR_IO_I2S_RX_MST0_CER 0x8001a00c -#pragma Aux_register(0x8001a00c, name=>"io_i2s_rx_mst0_cer") - -// User extension aux register io_i2s_rx_mst0_ccr -#define AR_IO_I2S_RX_MST0_CCR 0x8001a010 -#pragma Aux_register(0x8001a010, name=>"io_i2s_rx_mst0_ccr") - -// User extension aux register io_i2s_rx_mst0_rxffr -#define AR_IO_I2S_RX_MST0_RXFFR 0x8001a014 -#pragma Aux_register(0x8001a014, name=>"io_i2s_rx_mst0_rxffr") - -// User extension aux register io_i2s_rx_mst0_lrbr -#define AR_IO_I2S_RX_MST0_LRBR 0x8001a020 -#pragma Aux_register(0x8001a020, name=>"io_i2s_rx_mst0_lrbr") - -// User extension aux register io_i2s_rx_mst0_rrbr -#define AR_IO_I2S_RX_MST0_RRBR 0x8001a024 -#pragma Aux_register(0x8001a024, name=>"io_i2s_rx_mst0_rrbr") - -// User extension aux register io_i2s_rx_mst0_rer -#define AR_IO_I2S_RX_MST0_RER 0x8001a028 -#pragma Aux_register(0x8001a028, name=>"io_i2s_rx_mst0_rer") - -// User extension aux register io_i2s_rx_mst0_rcr -#define AR_IO_I2S_RX_MST0_RCR 0x8001a030 -#pragma Aux_register(0x8001a030, name=>"io_i2s_rx_mst0_rcr") - -// User extension aux register io_i2s_rx_mst0_isr -#define AR_IO_I2S_RX_MST0_ISR 0x8001a038 -#pragma Aux_register(0x8001a038, name=>"io_i2s_rx_mst0_isr") - -// User extension aux register io_i2s_rx_mst0_imr -#define AR_IO_I2S_RX_MST0_IMR 0x8001a03c -#pragma Aux_register(0x8001a03c, name=>"io_i2s_rx_mst0_imr") - -// User extension aux register io_i2s_rx_mst0_ror -#define AR_IO_I2S_RX_MST0_ROR 0x8001a040 -#pragma Aux_register(0x8001a040, name=>"io_i2s_rx_mst0_ror") - -// User extension aux register io_i2s_rx_mst0_rfcr -#define AR_IO_I2S_RX_MST0_RFCR 0x8001a048 -#pragma Aux_register(0x8001a048, name=>"io_i2s_rx_mst0_rfcr") - -// User extension aux register io_i2s_rx_mst0_rff -#define AR_IO_I2S_RX_MST0_RFF 0x8001a050 -#pragma Aux_register(0x8001a050, name=>"io_i2s_rx_mst0_rff") - -// User extension aux register io_i2s_rx_mst0_rxdma -#define AR_IO_I2S_RX_MST0_RXDMA 0x8001a1c0 -#pragma Aux_register(0x8001a1c0, name=>"io_i2s_rx_mst0_rxdma") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2S_TX_MST0_PRESENT 1 - -// User extension aux register io_i2s_tx_mst0_ier -#define AR_IO_I2S_TX_MST0_IER 0x80019000 -#pragma Aux_register(0x80019000, name=>"io_i2s_tx_mst0_ier") - -// User extension aux register io_i2s_tx_mst0_iter -#define AR_IO_I2S_TX_MST0_ITER 0x80019008 -#pragma Aux_register(0x80019008, name=>"io_i2s_tx_mst0_iter") - -// User extension aux register io_i2s_tx_mst0_cer -#define AR_IO_I2S_TX_MST0_CER 0x8001900c -#pragma Aux_register(0x8001900c, name=>"io_i2s_tx_mst0_cer") - -// User extension aux register io_i2s_tx_mst0_ccr -#define AR_IO_I2S_TX_MST0_CCR 0x80019010 -#pragma Aux_register(0x80019010, name=>"io_i2s_tx_mst0_ccr") - -// User extension aux register io_i2s_tx_mst0_txffr -#define AR_IO_I2S_TX_MST0_TXFFR 0x80019018 -#pragma Aux_register(0x80019018, name=>"io_i2s_tx_mst0_txffr") - -// User extension aux register io_i2s_tx_mst0_lthr -#define AR_IO_I2S_TX_MST0_LTHR 0x80019020 -#pragma Aux_register(0x80019020, name=>"io_i2s_tx_mst0_lthr") - -// User extension aux register io_i2s_tx_mst0_rthr -#define AR_IO_I2S_TX_MST0_RTHR 0x80019024 -#pragma Aux_register(0x80019024, name=>"io_i2s_tx_mst0_rthr") - -// User extension aux register io_i2s_tx_mst0_ter -#define AR_IO_I2S_TX_MST0_TER 0x8001902c -#pragma Aux_register(0x8001902c, name=>"io_i2s_tx_mst0_ter") - -// User extension aux register io_i2s_tx_mst0_tcr -#define AR_IO_I2S_TX_MST0_TCR 0x80019034 -#pragma Aux_register(0x80019034, name=>"io_i2s_tx_mst0_tcr") - -// User extension aux register io_i2s_tx_mst0_isr -#define AR_IO_I2S_TX_MST0_ISR 0x80019038 -#pragma Aux_register(0x80019038, name=>"io_i2s_tx_mst0_isr") - -// User extension aux register io_i2s_tx_mst0_imr -#define AR_IO_I2S_TX_MST0_IMR 0x8001903c -#pragma Aux_register(0x8001903c, name=>"io_i2s_tx_mst0_imr") - -// User extension aux register io_i2s_tx_mst0_tor -#define AR_IO_I2S_TX_MST0_TOR 0x80019044 -#pragma Aux_register(0x80019044, name=>"io_i2s_tx_mst0_tor") - -// User extension aux register io_i2s_tx_mst0_tfcr -#define AR_IO_I2S_TX_MST0_TFCR 0x8001904c -#pragma Aux_register(0x8001904c, name=>"io_i2s_tx_mst0_tfcr") - -// User extension aux register io_i2s_tx_mst0_tff -#define AR_IO_I2S_TX_MST0_TFF 0x80019054 -#pragma Aux_register(0x80019054, name=>"io_i2s_tx_mst0_tff") - -// User extension aux register io_i2s_tx_mst0_txdma -#define AR_IO_I2S_TX_MST0_TXDMA 0x800191c8 -#pragma Aux_register(0x800191c8, name=>"io_i2s_tx_mst0_txdma") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_PDM_RX0_PRESENT 1 - -// User extension aux register io_pdm_rx0_pdm_en -#define AR_IO_PDM_RX0_PDM_EN 0x8001b000 -#pragma Aux_register(0x8001b000, name=>"io_pdm_rx0_pdm_en") - -// User extension aux register io_pdm_rx0_pdm_ren -#define AR_IO_PDM_RX0_PDM_REN 0x8001b004 -#pragma Aux_register(0x8001b004, name=>"io_pdm_rx0_pdm_ren") - -// User extension aux register io_pdm_rx0_cer -#define AR_IO_PDM_RX0_CER 0x8001b00c -#pragma Aux_register(0x8001b00c, name=>"io_pdm_rx0_cer") - -// User extension aux register io_pdm_rx0_rxffr -#define AR_IO_PDM_RX0_RXFFR 0x8001b014 -#pragma Aux_register(0x8001b014, name=>"io_pdm_rx0_rxffr") - -// User extension aux register io_pdm_rx0_rer0 -#define AR_IO_PDM_RX0_RER0 0x8001b028 -#pragma Aux_register(0x8001b028, name=>"io_pdm_rx0_rer0") - -// User extension aux register io_pdm_rx0_isr -#define AR_IO_PDM_RX0_ISR 0x8001b038 -#pragma Aux_register(0x8001b038, name=>"io_pdm_rx0_isr") - -// User extension aux register io_pdm_rx0_imr -#define AR_IO_PDM_RX0_IMR 0x8001b03c -#pragma Aux_register(0x8001b03c, name=>"io_pdm_rx0_imr") - -// User extension aux register io_pdm_rx0_ror -#define AR_IO_PDM_RX0_ROR 0x8001b040 -#pragma Aux_register(0x8001b040, name=>"io_pdm_rx0_ror") - -// User extension aux register io_pdm_rx0_rfcr -#define AR_IO_PDM_RX0_RFCR 0x8001b048 -#pragma Aux_register(0x8001b048, name=>"io_pdm_rx0_rfcr") - -// User extension aux register io_pdm_rx0_rxdma -#define AR_IO_PDM_RX0_RXDMA 0x8001b1c0 -#pragma Aux_register(0x8001b1c0, name=>"io_pdm_rx0_rxdma") - -// User extension aux register io_pdm_rx0_pdm_rr -#define AR_IO_PDM_RX0_PDM_RR 0x8001b1d0 -#pragma Aux_register(0x8001b1d0, name=>"io_pdm_rx0_pdm_rr") - -// User extension aux register io_pdm_rx0_cic_n -#define AR_IO_PDM_RX0_CIC_N 0x8001b1d4 -#pragma Aux_register(0x8001b1d4, name=>"io_pdm_rx0_cic_n") - -// User extension aux register io_pdm_rx0_cic_d -#define AR_IO_PDM_RX0_CIC_D 0x8001b1d8 -#pragma Aux_register(0x8001b1d8, name=>"io_pdm_rx0_cic_d") - -// User extension aux register io_pdm_rx0_dcrc -#define AR_IO_PDM_RX0_DCRC 0x8001b1dc -#pragma Aux_register(0x8001b1dc, name=>"io_pdm_rx0_dcrc") - -// User extension aux register io_pdm_rx0_brc_b0 -#define AR_IO_PDM_RX0_BRC_B0 0x8001b1e0 -#pragma Aux_register(0x8001b1e0, name=>"io_pdm_rx0_brc_b0") - -// User extension aux register io_pdm_rx0_brc_clp -#define AR_IO_PDM_RX0_BRC_CLP 0x8001b1f0 -#pragma Aux_register(0x8001b1f0, name=>"io_pdm_rx0_brc_clp") -#define APEX_COM_ARC_HARDWARE_FLOATING_POINT_UNIT_FPU_PRESENT 1 - -// User extension aux register fpu_build -#define AR_FPU_BUILD 0xc8 -#pragma Aux_register(0xc8, name=>"fpu_build") - -// User extension aux register fpu_ctrl -#define AR_FPU_CTRL 0x300 -#pragma Aux_register(0x300, name=>"fpu_ctrl") - -// User extension aux register fpu_status -#define AR_FPU_STATUS 0x301 -#pragma Aux_register(0x301, name=>"fpu_status") - -// User extension instruction fsmadd -extern int fsmadd(int,int); -#pragma intrinsic(fsmadd,opcode=>6,sub_opcode=>5, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fsmsub -extern int fsmsub(int,int); -#pragma intrinsic(fsmsub,opcode=>6,sub_opcode=>6, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fsmul -extern int fsmul(int,int); -#pragma intrinsic(fsmul,opcode=>6,sub_opcode=>0, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fsadd -extern int fsadd(int,int); -#pragma intrinsic(fsadd,opcode=>6,sub_opcode=>1, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fssub -extern int fssub(int,int); -#pragma intrinsic(fssub,opcode=>6,sub_opcode=>2, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fcvt32 -extern int fcvt32(int,int); -#pragma intrinsic(fcvt32,opcode=>6,sub_opcode=>8, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fsdiv -extern int fsdiv(int,int); -#pragma intrinsic(fsdiv,opcode=>6,sub_opcode=>7, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fscmp -extern int fscmp(int,int); -#pragma intrinsic(fscmp,opcode=>6,sub_opcode=>3, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fscmp -extern int fscmp_f(int,int); -#pragma intrinsic(fscmp_f,opcode=>6,sub_opcode=>3, set_flags => 1, flags => "zncv", effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fscmpf -extern int fscmpf(int,int); -#pragma intrinsic(fscmpf,opcode=>6,sub_opcode=>4, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fscmpf -extern int fscmpf_f(int,int); -#pragma intrinsic(fscmpf_f,opcode=>6,sub_opcode=>4, set_flags => 1, flags => "zncv", effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fssqrt -extern int fssqrt(int); -#pragma intrinsic(fssqrt,opcode=>6,sub_opcode=>0, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") -#define APEX_COM_ARC_HARDWARE_FLOATING_POINT_UNIT_FPU_DP_ASSIST_PRESENT 1 - -// User extension aux register aux_dpfp1l -#define AR_AUX_DPFP1L 0x302 -#pragma Aux_register(0x302, name=>"aux_dpfp1l") - -// User extension aux register aux_dpfp1h -#define AR_AUX_DPFP1H 0x303 -#pragma Aux_register(0x303, name=>"aux_dpfp1h") - -// User extension aux register aux_dpfp2l -#define AR_AUX_DPFP2L 0x304 -#pragma Aux_register(0x304, name=>"aux_dpfp2l") - -// User extension aux register aux_dpfp2h -#define AR_AUX_DPFP2H 0x305 -#pragma Aux_register(0x305, name=>"aux_dpfp2h") - -// User extension instruction dmulh11 -extern int dmulh11(int,int); -#pragma intrinsic(dmulh11,opcode=>6,sub_opcode=>48,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh11 -extern int dmulh11_f(int,int); -#pragma intrinsic(dmulh11_f,opcode=>6,sub_opcode=>48, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh12 -extern int dmulh12(int,int); -#pragma intrinsic(dmulh12,opcode=>6,sub_opcode=>49,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh12 -extern int dmulh12_f(int,int); -#pragma intrinsic(dmulh12_f,opcode=>6,sub_opcode=>49, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh21 -extern int dmulh21(int,int); -#pragma intrinsic(dmulh21,opcode=>6,sub_opcode=>50,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh21 -extern int dmulh21_f(int,int); -#pragma intrinsic(dmulh21_f,opcode=>6,sub_opcode=>50, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh22 -extern int dmulh22(int,int); -#pragma intrinsic(dmulh22,opcode=>6,sub_opcode=>51,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh22 -extern int dmulh22_f(int,int); -#pragma intrinsic(dmulh22_f,opcode=>6,sub_opcode=>51, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh11 -extern int daddh11(int,int); -#pragma intrinsic(daddh11,opcode=>6,sub_opcode=>52,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh11 -extern int daddh11_f(int,int); -#pragma intrinsic(daddh11_f,opcode=>6,sub_opcode=>52, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh12 -extern int daddh12(int,int); -#pragma intrinsic(daddh12,opcode=>6,sub_opcode=>53,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh12 -extern int daddh12_f(int,int); -#pragma intrinsic(daddh12_f,opcode=>6,sub_opcode=>53, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh21 -extern int daddh21(int,int); -#pragma intrinsic(daddh21,opcode=>6,sub_opcode=>54,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh21 -extern int daddh21_f(int,int); -#pragma intrinsic(daddh21_f,opcode=>6,sub_opcode=>54, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh22 -extern int daddh22(int,int); -#pragma intrinsic(daddh22,opcode=>6,sub_opcode=>55,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh22 -extern int daddh22_f(int,int); -#pragma intrinsic(daddh22_f,opcode=>6,sub_opcode=>55, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh11 -extern int dsubh11(int,int); -#pragma intrinsic(dsubh11,opcode=>6,sub_opcode=>56,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh11 -extern int dsubh11_f(int,int); -#pragma intrinsic(dsubh11_f,opcode=>6,sub_opcode=>56, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh12 -extern int dsubh12(int,int); -#pragma intrinsic(dsubh12,opcode=>6,sub_opcode=>57,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh12 -extern int dsubh12_f(int,int); -#pragma intrinsic(dsubh12_f,opcode=>6,sub_opcode=>57, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh21 -extern int dsubh21(int,int); -#pragma intrinsic(dsubh21,opcode=>6,sub_opcode=>58,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh21 -extern int dsubh21_f(int,int); -#pragma intrinsic(dsubh21_f,opcode=>6,sub_opcode=>58, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh22 -extern int dsubh22(int,int); -#pragma intrinsic(dsubh22,opcode=>6,sub_opcode=>59,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh22 -extern int dsubh22_f(int,int); -#pragma intrinsic(dsubh22_f,opcode=>6,sub_opcode=>59, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dexcl1 -extern int dexcl1(int,int); -#pragma intrinsic(dexcl1,opcode=>6,sub_opcode=>60, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dexcl2 -extern int dexcl2(int,int); -#pragma intrinsic(dexcl2,opcode=>6,sub_opcode=>61, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - - -#endif - - diff --git a/board/emsdp/rev2/configs/em7d_esp_dfss/core_hardware.h b/board/emsdp/rev2/configs/em7d_esp_dfss/core_hardware.h deleted file mode 100644 index 6ab8701fa..000000000 --- a/board/emsdp/rev2/configs/em7d_esp_dfss/core_hardware.h +++ /dev/null @@ -1,71 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------- */ -#ifndef _CORE_HARDWARE_H_ -#define _CORE_HARDWARE_H_ - -#define EMSDP_SPI0_INTR (84) -#define EMSDP_SPI1_INTR (85) -#define EMSDP_GPIO_INTR0 (86) -#define EMSDP_GPIO_INTR1 (87) -#define EMSDP_GPIO_INTR2 (88) -#define EMSDP_GPIO_INTR3 (89) -#define EMSDP_TIMER0_INTR0 (90) -#define EMSDP_TIMER0_INTR1 (91) -#define EMSDP_TIMER0_INTR2 (92) -#define EMSDP_TIMER0_INTR3 (93) -#define EMSDP_TIMER0_INTR4 (94) -#define EMSDP_TIMER0_INTR5 (95) -#define EMSDP_TIMER0_INTR6 (96) -#define EMSDP_TIMER0_INTR7 (97) -#define EMSDP_TIMER1_INTR0 (98) -#define EMSDP_TIMER1_INTR1 (99) -#define EMSDP_TIMER1_INTR2 (100) -#define EMSDP_TIMER1_INTR3 (101) -#define EMSDP_TIMER1_INTR4 (102) -#define EMSDP_TIMER1_INTR5 (103) -#define EMSDP_TIMER1_INTR6 (104) -#define EMSDP_TIMER1_INTR7 (105) -#define EMSDP_UART_INTR (106) -#define EMSDP_WDT_INTR (107) -#define EMSDP_DBG_UART_INTR (108) -#define EMSDP_SDIO_INTR (109) -#define EMSDP_REDPINE_SPI_INTR (110) -#define EMSDP_REDPINE_HOST_WAKEUP (111) -#define EMSDP_NIST_TRNG_INTR (112) - -//EMSDP Peripheral Subsystem DMA assignments -#define UART_DMA_TX (9) -#define UART_DMA_RX (10) -#define REDPINE_SPI_DMA_TX (11) -#define REDPINE_SPI_DMA_RX (12) -#define FLASH_SPI_DMA_TX (13) -#define FLASH_SPI_DMA_RX (14) - -#endif /* _CORE_HARDWARE_H_ */ diff --git a/board/emsdp/rev2/configs/em7d_esp_dfss/dsp_config.h b/board/emsdp/rev2/configs/em7d_esp_dfss/dsp_config.h deleted file mode 100644 index 02a69fd24..000000000 --- a/board/emsdp/rev2/configs/em7d_esp_dfss/dsp_config.h +++ /dev/null @@ -1,15 +0,0 @@ - -/* **** DO NOT EDIT - this file is generated by ARChitect2 **** - * - * Description: Header file declaring the compiler extensions for eia components - */ - -#ifndef _dsp_config_H_ -#define _dsp_config_H_ - - -#define DSP_TRIG_PRESENT - -#endif - - diff --git a/board/emsdp/rev2/configs/em7d_esp_dfss/io_config.h b/board/emsdp/rev2/configs/em7d_esp_dfss/io_config.h deleted file mode 100644 index 5f55d3d9f..000000000 --- a/board/emsdp/rev2/configs/em7d_esp_dfss/io_config.h +++ /dev/null @@ -1,121 +0,0 @@ - -/* **** DO NOT EDIT - this file is generated by ARChitect2 **** - * - * Description: Header file declaring the compiler extensions for eia components - */ - -#ifndef _io_config_H_ -#define _io_config_H_ - - -#define DMAC_INT_BASE (20) -#define DMAC_ERR_BASE (DMAC_INT_BASE + DMAC_CHAN_CNT) -#define DMAC_CHAN_CNT (16) -#define DMAC_MEM_CHAN_CNT (16) -#define DMAC_AUX_CHAN_CNT (0) -#define IO_I2C_SLV0_PRESENT -#define IO_I2C_SLV0_FS (16) -#define IO_I2C_SLV0_INT_ERR (51) -#define IO_I2C_SLV0_INT_RX_AVAIL (52) -#define IO_I2C_SLV0_INT_TX_REQ (53) -#define IO_I2C_SLV0_INT_RD_REQ (54) -#define IO_I2C_SLV0_INT_STOP_DET (55) -#define IO_I2C_SLV0_INT_RESTART_DET (56) -#define IO_SPI_MST0_PRESENT -#define IO_SPI_MST0_FS (16) -#define IO_SPI_MST0_MAX_XFER_SIZE (16) -#define IO_SPI_MST0_DMA_TX (3) -#define IO_SPI_MST0_DMA_RX (4) -#define IO_SPI_MST0_INT_ERR (64) -#define IO_SPI_MST0_INT_RX_AVAIL (65) -#define IO_SPI_MST0_INT_TX_REQ (66) -#define IO_SPI_MST0_INT_IDLE (67) -#define IO_SPI_SLV0_PRESENT -#define IO_SPI_SLV0_FS (16) -#define IO_SPI_SLV0_MAX_XFER_SIZE (16) -#define IO_SPI_SLV0_DMA_TX (7) -#define IO_SPI_SLV0_DMA_RX (8) -#define IO_SPI_SLV0_INT_ERR (76) -#define IO_SPI_SLV0_INT_RX_AVAIL (77) -#define IO_SPI_SLV0_INT_TX_REQ (78) -#define IO_SPI_SLV0_INT_IDLE (79) -#define IO_I2C_MST0_PRESENT -#define IO_I2C_MST0_FS (16) -#define IO_I2C_MST0_INT_ERR (39) -#define IO_I2C_MST0_INT_RX_AVAIL (40) -#define IO_I2C_MST0_INT_TX_REQ (41) -#define IO_I2C_MST0_INT_STOP_DET (42) -#define IO_GPIO0_PRESENT -#define IO_GPIO0_INT_INTR_FLAG (17) -#define IO_GPIO0_DEBOUNCE (1) -#define IO_UART0_PRESENT -#define IO_UART0_FS (16) -#define IO_UART0_INTR (80) -#define IO_I2S_TX_MST0_PRESENT -#define IO_I2S_TX_MST0_FS (8) -#define IO_I2S_TX_MST0_FW (16) -#define IO_I2S_TX_MST0_INT_TX_REQ (59) -#define IO_I2S_TX_MST0_INT_ERR (60) -#define IO_I2S_TX_MST0_DMA (1) -#define IO_I2S_RX_MST0_PRESENT -#define IO_I2S_RX_MST0_FS (8) -#define IO_I2S_RX_MST0_FW (16) -#define IO_I2S_RX_MST0_INT_RX_AVAIL (57) -#define IO_I2S_RX_MST0_INT_ERR (58) -#define IO_I2S_RX_MST0_DMA (0) -#define IO_PDM_RX0_PRESENT -#define IO_PDM_RX0_CH (1) -#define IO_PDM_RX0_FS (16) -#define IO_PDM_RX0_NS (4) -#define IO_PDM_RX0_DS (2) -#define IO_PDM_RX0_INT_RX_AVAIL (61) -#define IO_PDM_RX0_INT_ERR (62) -#define IO_PDM_RX0_INT_CLP (63) -#define IO_PDM_RX0_DMA (2) -#define IO_SPI_MST1_PRESENT -#define IO_SPI_MST1_FS (16) -#define IO_SPI_MST1_MAX_XFER_SIZE (16) -#define IO_SPI_MST1_DMA_TX (5) -#define IO_SPI_MST1_DMA_RX (6) -#define IO_SPI_MST1_INT_ERR (68) -#define IO_SPI_MST1_INT_RX_AVAIL (69) -#define IO_SPI_MST1_INT_TX_REQ (70) -#define IO_SPI_MST1_INT_IDLE (71) -#define IO_I2C_MST1_PRESENT -#define IO_I2C_MST1_FS (16) -#define IO_I2C_MST1_INT_ERR (43) -#define IO_I2C_MST1_INT_RX_AVAIL (44) -#define IO_I2C_MST1_INT_TX_REQ (45) -#define IO_I2C_MST1_INT_STOP_DET (46) -#define IO_GPIO1_PRESENT -#define IO_GPIO1_INT_INTR_FLAG (19) -#define IO_GPIO1_DEBOUNCE (1) -#define IO_UART1_PRESENT -#define IO_UART1_FS (16) -#define IO_UART1_INTR (81) -#define IO_SPI_MST2_PRESENT -#define IO_SPI_MST2_FS (16) -#define IO_SPI_MST2_MAX_XFER_SIZE (16) -#define IO_SPI_MST2_INT_ERR (72) -#define IO_SPI_MST2_INT_RX_AVAIL (73) -#define IO_SPI_MST2_INT_TX_REQ (74) -#define IO_SPI_MST2_INT_IDLE (75) -#define IO_I2C_MST2_PRESENT -#define IO_I2C_MST2_FS (16) -#define IO_I2C_MST2_INT_ERR (47) -#define IO_I2C_MST2_INT_RX_AVAIL (48) -#define IO_I2C_MST2_INT_TX_REQ (49) -#define IO_I2C_MST2_INT_STOP_DET (50) -#define IO_GPIO2_PRESENT -#define IO_GPIO2_INT_INTR_FLAG (21) -#define IO_GPIO2_DEBOUNCE (1) -#define IO_UART2_PRESENT -#define IO_UART2_FS (16) -#define IO_UART2_INTR (82) -#define IO_UART3_PRESENT -#define IO_UART3_FS (16) -#define IO_UART3_INTR (83) - -#endif - - diff --git a/board/emsdp/rev2/configs/em7d_esp_dfss/tcf/em7d_esp_dfss.tcf b/board/emsdp/rev2/configs/em7d_esp_dfss/tcf/em7d_esp_dfss.tcf deleted file mode 100644 index ec704759e..000000000 --- a/board/emsdp/rev2/configs/em7d_esp_dfss/tcf/em7d_esp_dfss.tcf +++ /dev/null @@ -1,4868 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - -# -# option 16/L32/U32 Instructions -# ------ ---------- --------------------- -# -# none -/-/- None -# wlh1 1/1/1 MPYW/U, MPY/U, MPYH/U -# wlh2 2/2/2 MPYW/U, MPY/U, MPYH/U -# wlh3 2/3/3 MPYW/U, MPY/U, MPYH/U -# wlh4 2/4/5 MPYW/U, MPY/U, MPYH/U -# wlh5 5/9/9 MPYW/U, MPY/U, MPYH/U -# -# --mpy_option none - -# code_protection --- The ARC EM architecture divides the memory into 16 regions, which can be protected individually. This feature adds a 16-bit input to the processor core, one bit per region. When the protect bit is set, the processor disables any load or store to the corresponding region. An attempt to access a protected region raises an EV_ProtV exception. --code_protection false - -# stack_checking --- Stack checking is a mechanism for checking stack accesses and raising an exception when a stack overflow or underflow is detected. --stack_checking true - -# unaligned_option --- This enables unaligned loads and stores. --unaligned_option false - -# intvbase_preset --- This sets the interrupt vector base configuration register, VECBASE_AC_BUILD. The vector base address is aligned to a 1KB boundary, so the required address value should be divided by 1K (i.e. do not include the lower 10 bits). On reset, this register is loaded into the interrupt vector base address register, INT_VECTOR_BASE. --intvbase_preset 0x1 - -# intvbase_preset_s --- This sets the secure interrupt vector base configuration register, VECBASE_AC_BUILD. The vector base address is aligned to a 1KB boundary, so the required address value should be divided by 1K (i.e. do not include the lower 10 bits). On reset, this register is loaded into the interrupt vector base address register, INT_VECTOR_BASE_S.This is effective only when 2+2 mode is enabled. --intvbase_preset_s 0x0 - -# intvbase_ext --- Set this option to drive the upper 22 bits of the interrupt base vector externally, into signal intvbase_in. --intvbase_ext false - -# nmi_option --- add Non-maskable external exception support --nmi_option false - -# rgf_impl --- This defines whether the register file is implemented using flip-flops, or with a hard macro. --rgf_impl flip_flops - -# rgf_num_regs --- This defines the size (in 32b register) of the processor register file. --rgf_num_regs 32 - -# rgf_wr_ports --- This defines the number of write ports on the register file. --rgf_wr_ports 1 - -# rgf_num_banks --- Dual register banks are useful if Fast IRQ has been configured, but may be selected even if not. --rgf_num_banks 1 - -# rgf_banked_regs --- This selects the number of registers that are replicated in the second register-file bank. --rgf_banked_regs 32 - -# turbo_boost --- This enables the Turbo Boost synthesis option. By enabling this option, the achievable clock frequency is increased, but at the cost of an additional cycle latency on branch instructions. --turbo_boost true - -# infer_alu_adder --- infer: datapath is described as behavioral code: A + B -# instantiate: datapath is instantiated as a detailed multi-stage code of a carry-lookahead adder. It is generally preferable to use the infer option and add directives for your target synthesizer. --infer_alu_adder infer - -# infer_mpy_wtree --- infer: datapath is described as behavioral code: A * B (applies to only wlh3, wlh4 and wlh5 designs) -# instantiate: datapath is instantiated as a detailed multi-stage code of a Wallace Tree multiplier It is generally preferable to use the infer option and add directives for your target synthesizer. --infer_mpy_wtree instantiate - -# scantest_ram_bypass_mux --- This mux is used to make logic trapped between flops and memory (aka shadow logic) to be covered by scantest without requiring advanced sequential ATPG on the memory to be applied. Will add delay to functional access time --scantest_ram_bypass_mux false - -# logic_bist --- This option will OR LBIST_EN with test_mode --logic_bist false - -# power_domains --- Adds three separate power domains to the core, and propagates power-gate control signals to the top level of the core. Also generates UPF constraints and commands in the low-power scripts --power_domains false - -# dvfs --- Adds logic to the core to allow dynamic controlling of voltage and frequency and propagates the associated control signals to the top level of core --dvfs false - -# voltage_domains --- Creates a voltage domain split between RAM and std cell parts to support Ultra Low Voltage on cells and generates UPF constraints --voltage_domains false - -# mem_bus_option --- The core supports two bus protocols for accessing external memory: AHB & AHB-Lite. AHB-Lite-single means instruction fetch and data access share a single AHB-Lite port. AHB-Lite-dual means separate AHB-Lite port for each initiator if present. --mem_bus_option AHB-Lite-dual - -# mem_bus_reg_interface --- Specifies whether the memory bus interface is registered. --mem_bus_reg_interface true - -# dmi_burst_option --- This will enable high-throughput burst support on the DMI slave interfaces. By enabling this option, the peak DMI read throughput goes from 1 word per 3 cycles to N words per N+2 cycles, in which N is the AHB burst lengthDMI write throughput goes from 1 word per 3 cycles to 1 word per cycle. --dmi_burst_option true - -# has_dmp_peripheral --- This option enables the redirection of load/store accesses to one segment (1/16) of the addressable space to a dedicated peripheral bus. This offers high system integration and reduces overall system cost. --has_dmp_peripheral true - -# per0_base --- This option specifies the memory region assignment for this peripheral aperture --per0_base 15 - -# per0_limit --- This option specifies the end of this peripheral aperture --per0_limit 0 - -# per_bus_option --- The core supports one bus protocol for accessing the peripheral space, when enabled: AHB-Lite. --per_bus_option AHB-Lite - -# per_bus_reg_interface --- Specifies whether the peripheral bus interface is registered. --per_bus_reg_interface true - -# clock_gating --- This enables the insertion of architectural clock gate elements in the design. By enabling this option, the clocks to various parts of the design will be disabled when the logic they drive is not in use to save power. --clock_gating false - -# back_compat --- This enables the addition of rst_a input in the clkgate module to support backward compatibility with the older EM and Subsystem releases. --back_compat true - -# byte_parity --- If parity protection on the CCMs or Cache is configured, this option enables parity protection on a per-byte basis. Otherwise, parity is per word basis --byte_parity false - -# prot_pipelined --- Check the box if CCM memories are configured for ECC, and you want single-bit errors to be corrected, written back to memory, and re-fetched. When unchecked, single bit errors are corrected when read from memory, but the offending memory location itself is not corrected with a writeback, no influence on Cache protection --prot_pipelined false - -# cct_test_ena --- When ECC is configured, this option enables single bit error injection in CCT RAM models to demonstrate ECC protection on the RAMs. When enabled, the RAM models can only be used in HDL CCT simulation (no xCAM support) and are not intended for use in SoC level integration. --cct_test_ena false - -# err_prot_ehce --- Enabled enhanced ECC architecture for CCM. Instruction fetch with single bit error is not replayed; ecc cac modules are shared to reduce area and timing opt. --err_prot_ehce false - - -######## dsp_trig --- com.arc.hardware.dfss.dsp_trig.1_0 ######## - -# Create dsp_trig --create com.arc.hardware.dfss.dsp_trig.1_0 System.CPUisle.ARCv2EM.dsp_trig - -# dsp_trig --- Command line option for EIA extension component 'dsp_trig'. --dsp_trig true - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_gpio0 --- com.arc.hardware.dfss.io_gpio0.1_0 ######## - -# Create io_gpio0 --create com.arc.hardware.dfss.io_gpio0.1_0 System.CPUisle.ARCv2EM.io_gpio0 - -# io_gpio0 --- Command line option for EIA extension component 'io_gpio0'. --io_gpio0 true - -# io_gpio0_debounce --- Selects the inclusion of Debounce logic --io_gpio0_debounce 1 - -# io_gpio0_readback_sync --- Selects the inclusion of metastability registers on the read back path when reading the external 'ext_porta' signal --io_gpio0_readback_sync 1 - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - -# io_gpio0_direction_rst_value --- Reset value of the SWPORTA_DDR register, which determines the direction (input/output) of the GPIO interface. 0: input, 1: output. --io_gpio0_direction_rst_value 0 - -# io_gpio0_output_rst_value --- Reset value of the SWPORTA_DR register, which determines the reset value of the GPIO output ports. Bits corresponding to input ports are ignored. --io_gpio0_output_rst_value 0x0 - - -######## io_i2c_mst0 --- com.arc.hardware.dfss.io_i2c_mst0.1_0 ######## - -# Create io_i2c_mst0 --create com.arc.hardware.dfss.io_i2c_mst0.1_0 System.CPUisle.ARCv2EM.io_i2c_mst0 - -# io_i2c_mst0 --- Command line option for APEX extension component 'io_i2c_mst0'. --io_i2c_mst0 true - -# io_i2c_mst0_fs --- RX/TX FIFO size --io_i2c_mst0_fs 16 - -# io_i2c_mst0_dma_support --- Specifies whether the DMA handshake interface is included --io_i2c_mst0_dma_support None - -# io_i2c_mst0_cdc_included --- Selects whether a clock-domain crossing (CDC) is included between the core clock and the serial clock. If no CDC is present, both clocks must be synchronous. Otherwise the core clock frequency may be higher than, lower than or equal to the serial clock frequency. --io_i2c_mst0_cdc_included 0 - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_i2c_slv0 --- com.arc.hardware.dfss.io_i2c_slv0.1_0 ######## - -# Create io_i2c_slv0 --create com.arc.hardware.dfss.io_i2c_slv0.1_0 System.CPUisle.ARCv2EM.io_i2c_slv0 - -# io_i2c_slv0 --- Command line option for APEX extension component 'io_i2c_slv0'. --io_i2c_slv0 true - -# io_i2c_slv0_fs --- RX/TX FIFO size --io_i2c_slv0_fs 16 - -# io_i2c_slv0_dma_support --- Specifies whether the DMA handshake interface is included --io_i2c_slv0_dma_support None - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_spi_mst0 --- com.arc.hardware.dfss.io_spi_mst0.1_0 ######## - -# Create io_spi_mst0 --create com.arc.hardware.dfss.io_spi_mst0.1_0 System.CPUisle.ARCv2EM.io_spi_mst0 - -# io_spi_mst0 --- Command line option for APEX extension component 'io_spi_mst0'. --io_spi_mst0 true - -# io_spi_mst0_fz --- RX/TX FIFO depth --io_spi_mst0_fs 16 - -# io_spi_mst0_max_xfer_size --- This defines the maximum number of bits per word at the serial data port, which determines the FIFO width. --io_spi_mst0_max_xfer_size 16 - -# io_spi_mst0_cdc_included --- Selects whether a clock-domain crossing (CDC) is included between the core clock and the peripheral clock. If no CDC is present, both clocks must be synchronous. Otherwise the core clock frequency may be higher than or equal to the peripheral clock frequency. --io_spi_mst0_cdc_included 0 - -# io_spi_mst0_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_spi_mst0_dma_support Memory-Based - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## subsys_bcr --- com.arc.hardware.dfss.subsys_bcr.1_0 ######## - -# Create subsys_bcr --create com.arc.hardware.dfss.subsys_bcr.1_0 System.CPUisle.ARCv2EM.subsys_bcr - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_spi_mst1 --- com.arc.hardware.dfss.io_spi_mst1.1_0 ######## - -# Create io_spi_mst1 --create com.arc.hardware.dfss.io_spi_mst1.1_0 System.CPUisle.ARCv2EM.io_spi_mst1 - -# io_spi_mst1 --- Command line option for APEX extension component 'io_spi_mst1'. --io_spi_mst1 true - -# io_spi_mst1_fz --- RX/TX FIFO depth --io_spi_mst1_fs 16 - -# io_spi_mst1_max_xfer_size --- This defines the maximum number of bits per word at the serial data port, which determines the FIFO width. --io_spi_mst1_max_xfer_size 16 - -# io_spi_mst1_cdc_included --- Selects whether a clock-domain crossing (CDC) is included between the core clock and the peripheral clock. If no CDC is present, both clocks must be synchronous. Otherwise the core clock frequency may be higher than or equal to the peripheral clock frequency. --io_spi_mst1_cdc_included 0 - -# io_spi_mst1_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_spi_mst1_dma_support Memory-Based - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_spi_mst2 --- com.arc.hardware.dfss.io_spi_mst2.1_0 ######## - -# Create io_spi_mst2 --create com.arc.hardware.dfss.io_spi_mst2.1_0 System.CPUisle.ARCv2EM.io_spi_mst2 - -# io_spi_mst2 --- Command line option for APEX extension component 'io_spi_mst2'. --io_spi_mst2 true - -# io_spi_mst2_fz --- RX/TX FIFO depth --io_spi_mst2_fs 16 - -# io_spi_mst2_max_xfer_size --- This defines the maximum number of bits per word at the serial data port, which determines the FIFO width. --io_spi_mst2_max_xfer_size 16 - -# io_spi_mst2_cdc_included --- Selects whether a clock-domain crossing (CDC) is included between the core clock and the peripheral clock. If no CDC is present, both clocks must be synchronous. Otherwise the core clock frequency may be higher than or equal to the peripheral clock frequency. --io_spi_mst2_cdc_included 0 - -# io_spi_mst2_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_spi_mst2_dma_support None - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_spi_slv0 --- com.arc.hardware.dfss.io_spi_slv0.1_0 ######## - -# Create io_spi_slv0 --create com.arc.hardware.dfss.io_spi_slv0.1_0 System.CPUisle.ARCv2EM.io_spi_slv0 - -# io_spi_slv0 --- Command line option for APEX extension component 'io_spi_slv0'. --io_spi_slv0 true - -# io_spi_slv0_fz --- RX/TX FIFO depth --io_spi_slv0_fs 16 - -# io_spi_slv0_max_xfer_size --- This defines the maximum number of bits per word at the serial data port, which determines the FIFO width. --io_spi_slv0_max_xfer_size 16 - -# io_spi_slv0_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_spi_slv0_dma_support Memory-Based - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_gpio1 --- com.arc.hardware.dfss.io_gpio1.1_0 ######## - -# Create io_gpio1 --create com.arc.hardware.dfss.io_gpio1.1_0 System.CPUisle.ARCv2EM.io_gpio1 - -# io_gpio1 --- Command line option for EIA extension component 'io_gpio1'. --io_gpio1 true - -# io_gpio1_debounce --- Selects the inclusion of Debounce logic --io_gpio1_debounce 1 - -# io_gpio1_readback_sync --- Selects the inclusion of metastability registers on the read back path when reading the external 'ext_porta' signal --io_gpio1_readback_sync 1 - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - -# io_gpio1_direction_rst_value --- Reset value of the SWPORTA_DDR register, which determines the direction (input/output) of the GPIO interface. 0: input, 1: output. --io_gpio1_direction_rst_value 0 - -# io_gpio1_output_rst_value --- Reset value of the SWPORTA_DR register, which determines the reset value of the GPIO output ports. Bits corresponding to input ports are ignored. --io_gpio1_output_rst_value 0x0 - - -######## io_gpio2 --- com.arc.hardware.dfss.io_gpio2.1_0 ######## - -# Create io_gpio2 --create com.arc.hardware.dfss.io_gpio2.1_0 System.CPUisle.ARCv2EM.io_gpio2 - -# io_gpio2 --- Command line option for EIA extension component 'io_gpio2'. --io_gpio2 true - -# io_gpio2_debounce --- Selects the inclusion of Debounce logic --io_gpio2_debounce 1 - -# io_gpio2_readback_sync --- Selects the inclusion of metastability registers on the read back path when reading the external 'ext_porta' signal --io_gpio2_readback_sync 1 - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - -# io_gpio2_direction_rst_value --- Reset value of the SWPORTA_DDR register, which determines the direction (input/output) of the GPIO interface. 0: input, 1: output. --io_gpio2_direction_rst_value 0 - -# io_gpio2_output_rst_value --- Reset value of the SWPORTA_DR register, which determines the reset value of the GPIO output ports. Bits corresponding to input ports are ignored. --io_gpio2_output_rst_value 0x0 - - -######## io_i2c_mst1 --- com.arc.hardware.dfss.io_i2c_mst1.1_0 ######## - -# Create io_i2c_mst1 --create com.arc.hardware.dfss.io_i2c_mst1.1_0 System.CPUisle.ARCv2EM.io_i2c_mst1 - -# io_i2c_mst1 --- Command line option for APEX extension component 'io_i2c_mst1'. --io_i2c_mst1 true - -# io_i2c_mst1_fs --- RX/TX FIFO size --io_i2c_mst1_fs 16 - -# io_i2c_mst1_dma_support --- Specifies whether the DMA handshake interface is included --io_i2c_mst1_dma_support None - -# io_i2c_mst1_cdc_included --- Selects whether a clock-domain crossing (CDC) is included between the core clock and the serial clock. If no CDC is present, both clocks must be synchronous. Otherwise the core clock frequency may be higher than, lower than or equal to the serial clock frequency. --io_i2c_mst1_cdc_included 0 - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_i2c_mst2 --- com.arc.hardware.dfss.io_i2c_mst2.1_0 ######## - -# Create io_i2c_mst2 --create com.arc.hardware.dfss.io_i2c_mst2.1_0 System.CPUisle.ARCv2EM.io_i2c_mst2 - -# io_i2c_mst2 --- Command line option for APEX extension component 'io_i2c_mst2'. --io_i2c_mst2 true - -# io_i2c_mst2_fs --- RX/TX FIFO size --io_i2c_mst2_fs 16 - -# io_i2c_mst2_dma_support --- Specifies whether the DMA handshake interface is included --io_i2c_mst2_dma_support None - -# io_i2c_mst2_cdc_included --- Selects whether a clock-domain crossing (CDC) is included between the core clock and the serial clock. If no CDC is present, both clocks must be synchronous. Otherwise the core clock frequency may be higher than, lower than or equal to the serial clock frequency. --io_i2c_mst2_cdc_included 0 - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_uart0 --- com.arc.hardware.dfss.io_uart0.1_0 ######## - -# Create io_uart0 --create com.arc.hardware.dfss.io_uart0.1_0 System.CPUisle.ARCv2EM.io_uart0 - -# io_uart0 --- Command line option for EIA extension component 'io_uart0'. --io_uart0 true - -# io_uart0_fifo_mode --- Set the UART FIFO mode --io_uart0_fifo_mode 16 - -# io_uart0_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_uart0_dma_support None - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_uart1 --- com.arc.hardware.dfss.io_uart1.1_0 ######## - -# Create io_uart1 --create com.arc.hardware.dfss.io_uart1.1_0 System.CPUisle.ARCv2EM.io_uart1 - -# io_uart1 --- Command line option for EIA extension component 'io_uart1'. --io_uart1 true - -# io_uart1_fifo_mode --- Set the UART FIFO mode --io_uart1_fifo_mode 16 - -# io_uart1_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_uart1_dma_support None - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_uart2 --- com.arc.hardware.dfss.io_uart2.1_0 ######## - -# Create io_uart2 --create com.arc.hardware.dfss.io_uart2.1_0 System.CPUisle.ARCv2EM.io_uart2 - -# io_uart2 --- Command line option for EIA extension component 'io_uart2'. --io_uart2 true - -# io_uart2_fifo_mode --- Set the UART FIFO mode --io_uart2_fifo_mode 16 - -# io_uart2_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_uart2_dma_support None - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_uart3 --- com.arc.hardware.dfss.io_uart3.1_0 ######## - -# Create io_uart3 --create com.arc.hardware.dfss.io_uart3.1_0 System.CPUisle.ARCv2EM.io_uart3 - -# io_uart3 --- Command line option for EIA extension component 'io_uart3'. --io_uart3 true - -# io_uart3_fifo_mode --- Set the UART FIFO mode --io_uart3_fifo_mode 16 - -# io_uart3_dma_support --- Selects whether support for the ARC EM DMA is included and whether the handshake interface should be connected to a memory-based or to an Aux-based DMA channel. --io_uart3_dma_support None - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_i2s_rx_mst0 --- com.arc.hardware.dfss.io_i2s_rx_mst0.1_0 ######## - -# Create io_i2s_rx_mst0 --create com.arc.hardware.dfss.io_i2s_rx_mst0.1_0 System.CPUisle.ARCv2EM.io_i2s_rx_mst0 - -# io_i2s_rx_mst0 --- Command line option for APEX extension component 'io_i2s_rx_mst0'. --io_i2s_rx_mst0 true - -# io_i2s_rx_mst0_fs --- RX FIFO size --io_i2s_rx_mst0_fs 8 - -# io_i2s_rx_mst0_fw --- RX FIFO width --io_i2s_rx_mst0_fw 16 - -# io_i2s_rx_mst0_dma_support --- Specifies whether the DMA handshake interface is included --io_i2s_rx_mst0_dma_support Memory-Based - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_i2s_tx_mst0 --- com.arc.hardware.dfss.io_i2s_tx_mst0.1_0 ######## - -# Create io_i2s_tx_mst0 --create com.arc.hardware.dfss.io_i2s_tx_mst0.1_0 System.CPUisle.ARCv2EM.io_i2s_tx_mst0 - -# io_i2s_tx_mst0 --- Command line option for APEX extension component 'io_i2s_tx_mst0'. --io_i2s_tx_mst0 true - -# io_i2s_tx_mst0_fs --- TX FIFO size --io_i2s_tx_mst0_fs 8 - -# io_i2s_tx_mst0_fw --- TX FIFO width --io_i2s_tx_mst0_fw 16 - -# io_i2s_tx_mst0_dma_support --- Specifies whether the DMA handshake interface is included --io_i2s_tx_mst0_dma_support Memory-Based - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## io_pdm_rx0 --- com.arc.hardware.dfss.io_pdm_rx0.1_0 ######## - -# Create io_pdm_rx0 --create com.arc.hardware.dfss.io_pdm_rx0.1_0 System.CPUisle.ARCv2EM.io_pdm_rx0 - -# io_pdm_rx0 --- Command line option for APEX extension component 'io_pdm_rx0'. --io_pdm_rx0 true - -# io_pdm_rx0_ch --- Number of Stereo Channels --io_pdm_rx0_ch 1 - -# io_pdm_rx0_fs --- RX FIFO size --io_pdm_rx0_fs 16 - -# io_pdm_rx0_ns --- Maximum number of CIC stages --io_pdm_rx0_ns 4 - -# io_pdm_rx0_ds --- Maximum delay in the COMB filter of the CIC filter --io_pdm_rx0_ds 2 - -# io_pdm_rx0_dma_support --- Specifies whether the DMA handshake interface is included --io_pdm_rx0_dma_support Memory-Based - -# assign_xpubit --- -# -# The User Mode Extension Enable register (XPU) controls user-mode access to extension instructions and state. Each extension group is assigned a bit within the XPU register, and this bit may be programmed to enable or disable user-mode access to the extensions within that group. -#

-# By default an extension is not assigned a bit in this register. This means the extension is always available. -#

-# If you wish to assign an XPU bit number, select this option. -# -# --assign_xpubit false - -# xpubit --- -# The XPU bit number for this extension. -# --xpubit 0 - - -######## DCCM --- com.arc.hardware.DCCM.1_0 ######## - -# Create DCCM --create com.arc.hardware.DCCM.1_0 System.CPUisle.ARCv2EM.DCCM - -# dccm_size --- This defines the size of the Data Closely Coupled Memory (DCCM) in bytes --dccm_size 131072 - -# dccm_base --- Sets the initial memory region assignment for DCCM --dccm_base 8 - -# dccm_interleave --- Split DCCM into even/odd memory banks. --dccm_interleave false - -# dccm_prot --- Specifies the type of protection built for the DCCM. --dccm_prot None - -# dccm_prot_level --- Specifies the level protection. --dccm_prot_level Data_Only - -# dccm_prot_exceptions --- When the core is configured with ECC or Parity, cause exception generation hardware to be created for uncorrectable errors detected on the DCCM --dccm_prot_exceptions true - -# dccm_sec_lvl --- Specifies the level of secure DCCM. --dccm_sec_lvl Non_Secure - -# dccm_dmi --- This enables external access through a DMI (direct memory interface) port. --dccm_dmi true - - -######## DMA Controller --- com.arc.hardware.DMA_Controller.1_0 ######## - -# Create DMA Controller --create com.arc.hardware.DMA_Controller.1_0 "System.CPUisle.ARCv2EM.DMA Controller" - -# dmac_channels --- This options specifies the number of DMA channels implemented in the DMA controller --dmac_channels 16 - -# dmac_fifo_depth --- This option specifies the DMA transfer FIFO depth in 32b words. --dmac_fifo_depth 2 - -# dmac_int_config --- None: the DMA controller cannot raise an interrupt -# Single-External: single done and single error interrupt signal for all DMA channels, and the interrupt signals are routed to a port at the top of the EM logical hierarchy -# Multiple-External: each DMA channel can be configured to raise separate (per-channel) done and error interrupts, and the interrupt signals are routed to ports at the top of the EM logical hierarchy -# Single-Internal: single done and single error interrupt signals for all DMA channels, and the interrupt signals are internal to the EM core -# Multiple-Internal: each DMA channel can be configured to raise separate (per-channel) done and error interrupts, and the interrupt signals are internal to the EM core --dmac_int_config Multiple-Internal - -# dmac_separate_error_interrupts --- This specifies whether there is a separate error interrupt per DMA channel, or just one. --dmac_separate_error_interrupts false - -# dmac_registers --- This option defines the number of DMA channels with their registers located in auxiliary space. --dmac_registers 0 - -# dmac_mem_if --- This option specifies whether the DMA controller system memory interface is integrated into the existing EM system memory interfaces or has its own interface. --dmac_mem_if integrated - -# dmac_per_if --- Internal vs DW peripheral interface. Specify (in hex) which channels have the DW interface, where bit 0 corresponds to DMA channel 0, bit 1 for DMA channel 1, etc. -# Example: 4 channel DMA controller where -dmac_per_if is set to 0x9 = DMA Channels 0 and 3 configured with the DW req interface, DMA Channels 1 and 2 configured with the internal req interface. --dmac_per_if 0x7e00 - - -######## DSP --- com.arc.hardware.DSP.1_0 ######## - -# Create DSP --create com.arc.hardware.DSP.1_0 System.CPUisle.ARCv2EM.DSP - -# dsp_complex --- Enable/disable support for single cycle 16b+16b complex instructions and butterfly operations, else 2-cycle complex instructions only without butterfly support --dsp_complex true - -# dsp_itu --- Enable/disable support for ITU bit-accurate 1 bit fractional shift before accumulation, else 1-bit fractional shift result after accumulation only --dsp_itu true - -# dsp_divsqrt --- Enable/disable support for divide and square root operations: DIV(U), REM(U), SQRT --dsp_divsqrt radix2 - -# dsp_accshift --- Select support for accumulator shift operations: no supported, limited shift support only or full shift support and convergent rounding --dsp_accshift full - -# dsp_impl --- The datapath components may be inferred from Verilog for better area or optimized using carry-save components for better timing --dsp_impl optimized - - -######## Data Cache --- com.arc.hardware.Data_Cache.1_0 ######## - -# Create Data Cache --create com.arc.hardware.Data_Cache.1_0 "System.CPUisle.ARCv2EM.Data Cache" - -# dc_size --- This defines the total size of the Data Cache in bytes. --dc_size 16384 - -# dc_ways --- This defines the number of cache ways. --dc_ways 2 - -# dc_bsize --- This defines the cache line length in bytes. --dc_bsize 32 - -# dc_feature_level --- Feature Level, indicates locking and debug feature level 00 = Basic cache, with no locking or debug features 01 = Lock and flush features supported 10 = Lock, flush and advanced debug features supported 11 = Reserved --dc_feature_level 2 - -# dc_uncached_region --- Enable an uncached region defined by aux reg --dc_uncached_region false - -# dc_prot --- Specifies the type of protection built for DCACHE. --dc_prot None - -# dc_prot_level --- Specifies the level of protection. --dc_prot_level Data_Only - -# dc_prot_exceptions --- Builds exception generation hardware for uncorrectable (fatal) errors detected on DCACHE. --dc_prot_exceptions true - - -######## Debug Interface --- com.arc.hardware.Debug_Interface.1_0 ######## - -# Create Debug Interface --create com.arc.hardware.Debug_Interface.1_0 "System.CPUisle.ARCv2EM.Debug Interface" - -# dbg_en_option --- Adds an enable pin to the existing debug interface --dbg_en_option false - -# secure_debug --- This enables secure debug feature --secure_debug true - -# scdbg_aux_unlk --- An internal demo module will be included when enable --scdbg_aux_unlk false - -# dbg_apb_option --- Adds an additional APB debug port alongside the BVCI one --dbg_apb_option false - - -######## ICCM0 --- com.arc.hardware.ICCM0.1_0 ######## - -# Create ICCM0 --create com.arc.hardware.ICCM0.1_0 System.CPUisle.ARCv2EM.ICCM0 - -# iccm0_size --- This defines the size of ICCM0 in bytes.This ICCM has 0 wait states. --iccm0_size 131072 - -# iccm0_base --- Sets the initial memory region assignment for ICCM0 --iccm0_base 6 - -# iccm0_wide --- Creates ICCM0 as 64b memory to reduce accesses. --iccm0_wide false - -# iccm0_prot --- Specifies the type of protection built for ICCM0. --iccm0_prot None - -# iccm0_prot_level --- Specifies the level of protection. --iccm0_prot_level Data_Only - -# iccm0_prot_exceptions --- When the core is configured with ECC or Parity, cause exception generation hardware to be created for uncorrectable errors detected on the ICCM0 --iccm0_prot_exceptions true - -# iccm0_sec_lvl --- Specifies the level of secure ICCM0. --iccm0_sec_lvl Non_Secure - -# iccm0_dmi --- This enables external access through a DMI (direct memory interface) port. --iccm0_dmi true - - -######## Instruction Cache --- com.arc.hardware.Instruction_Cache.1_0 ######## - -# Create Instruction Cache --create com.arc.hardware.Instruction_Cache.1_0 "System.CPUisle.ARCv2EM.Instruction Cache" - -# ic_size --- This defines the total size of the instruction cache in bytes. --ic_size 16384 - -# ic_ways --- This defines the number of cache ways --ic_ways 2 - -# ic_bsize --- This defines the cache line length in bytes. --ic_bsize 64 - -# ic_disable_on_reset --- The instruction cache may be enabled immediately after reset, depending on this option. If this option is enabled, the last cache operation is set to failed, and the direct cache-RAM access is enabled. Furthermore, the instruction cache is invalidated all cache lines are invalidated and unlocked, and the tag RAM is cleared. --ic_disable_on_reset false - -# ic_feature_level --- This defines the feature level of the cache. --ic_feature_level 1 - -# ic_pwr_opt_level --- This selects power-optimization options in the micro-architecture of the instruction cache. --ic_pwr_opt_level 0 - -# ic_prot --- Specifies the type of protection built for ICACHE. --ic_prot None - -# ic_prot_level --- Specifies the level of protection. --ic_prot_level Data_Only - -# ic_prot_exceptions --- Builds exception generation hardware for uncorrectable (fatal) errors detected on ICACHE. --ic_prot_exceptions true - - -######## Interrupt Controller --- com.arc.hardware.Interrupt_Controller.1_0 ######## - -# Create Interrupt Controller --create com.arc.hardware.Interrupt_Controller.1_0 "System.CPUisle.ARCv2EM.Interrupt Controller" - -# number_of_interrupts --- This is the total number of interrupts available to the core. Some interrupts are allocated statically to a specific interrupt line (for example, timer interrupts). For more information on Interrupt and register-file options, see DesignWare ARCv2 ISA Programmers Reference Manual. --number_of_interrupts 97 - -# number_of_levels --- Priority levels in the interrupt controller. --number_of_levels 4 - -# external_interrupts --- This is the total number of interrupt pins available for external system components. This parameter must be less than the total number of interrupts. --external_interrupts 77 - -# firq_option --- This enables the fast-interrupts option, (priority level 0 interrupts), which uses an alternate register bank (if configured) instead of saving the context to memory. --firq_option false - - -######## Performance Monitor --- com.arc.hardware.Performance_Monitor.1_0 ######## - -# Create Performance Monitor --create com.arc.hardware.Performance_Monitor.1_0 "System.CPUisle.ARCv2EM.Performance Monitor" - -# pct_counters --- Number of counters for performance monitoring. --pct_counters 8 - - -######## JTAG Interface --- com.arc.hardware.JTAG_Interface.1_0 ######## - -# Create JTAG Interface --create com.arc.hardware.JTAG_Interface.1_0 "System.CPUisle.ARCv2EM.JTAG Interface" - -######## Timer 0 --- com.arc.hardware.Timer_0.1_0 ######## - -# Create Timer 0 --create com.arc.hardware.Timer_0.1_0 "System.CPUisle.ARCv2EM.Timer 0" - -# timer_0_int_level --- This sets the interrupt level (and implicitly the priority: level 0 is highest) of timer 0. --timer_0_int_level 1 - - -######## Watchdog Timer --- com.arc.hardware.Watchdog_Timer.1_0 ######## - -# Create Watchdog Timer --create com.arc.hardware.Watchdog_Timer.1_0 "System.CPUisle.ARCv2EM.Watchdog Timer" - -# watchdog_size --- Specifies the bit width of timer's internal counter. --watchdog_size 32 - -# watchdog_clk --- Specifies whether the timer should be driven from a separate clock. --watchdog_clk false - - -######## Real-time Counter --- com.arc.hardware.Real_time_Counter.1_0 ######## - -# Create Real-time Counter --create com.arc.hardware.Real_time_Counter.1_0 "System.CPUisle.ARCv2EM.Real-time Counter" - -######## SmaRT --- com.arc.hardware.SmaRT.1_0 ######## - -# Create SmaRT --create com.arc.hardware.SmaRT.1_0 System.CPUisle.ARCv2EM.SmaRT - -# smart_stack_entries --- This specifies the number of entries in the trace buffer. --smart_stack_entries 8 - -# smart_implementation --- Flip-flop = FF-based design. Memory = memory-based design (provides better density for larger trace buffers). --smart_implementation flip-flop - - -######## Secure pipeline features --- com.arc.hardware.Secure_pipeline_features.1_0 ######## - -# Create Secure pipeline features --create com.arc.hardware.Secure_pipeline_features.1_0 "System.CPUisle.ARCv2EM.Secure pipeline features" - -# sec_scramble --- Enable insertion of scrambling modules on the address & data lines for embedded SRAMs and external memory interfaces. The gate count number in System/Gate Count tab does not include user defined logic. --sec_scramble false - -# sec_encrypt_i --- Add support for user defined instruction encryption. The gate count number in System/Gate Count tab does not include user defined logic. --sec_encrypt_i false - -# sec_encrypt_d --- Add support for user defined data encryption. The gate count number in System/Gate Count tab does not include user defined logic. --sec_encrypt_d false - -# err_prot_option --- Select the ECC mode for CCM/Cache ECC protection: false: detect & correct or true: detect & fail --err_prot_option true - -# pipe_prot_option --- Select to enable PC & Register File error protection --pipe_prot_option false - -# sec_modes_option --- Enable secure shield 2+2 mode --sec_modes_option true - -# sec_region_crypt --- If MPU is present, use region-based encryption user logic for CCT demo --sec_region_crypt false - - -######## Secure Timer 0 --- com.arc.hardware.Secure_Timer_0.1_0 ######## - -# Create Secure Timer 0 --create com.arc.hardware.Secure_Timer_0.1_0 "System.CPUisle.ARCv2EM.Secure Timer 0" - -# stimer_0_int_level --- This sets the interrupt level (and implicitly the priority: level 0 is highest) of secure timer 0. --stimer_0_int_level 1 - - -######## Actionpoints --- com.arc.hardware.Actionpoints.1_0 ######## - -# Create Actionpoints --create com.arc.hardware.Actionpoints.1_0 System.CPUisle.ARCv2EM.Actionpoints - -# num_actionpoints --- This is the number of trigger events available. --num_actionpoints 8 - -# aps_feature --- Selects Actionpoint feature set --aps_feature min - - -######## Floating-point unit --- com.arc.hardware.Floating_point_unit.1_0 ######## - -# Create Floating-point unit --create com.arc.hardware.Floating_point_unit.1_0 "System.CPUisle.ARCv2EM.Floating-point unit" - -# fpu_dp_assist --- This enables double-precision acceleration instructions. --fpu_dp_assist true - -# fpu_fma_option --- This enables the fused multiply-add & multiply-subtract instructions. --fpu_fma_option true - -# fpu_mas_cycles --- Make mul/add/sub multicycle to achieve a higher clock speed. --fpu_mas_cycles 2 - -# fpu_pipe_impl --- FPU pipelined implementation --fpu_pipe_impl true - -# fpu_div_option --- This enables divide & square-root acceleration --fpu_div_option true - -# fpu_div_cycles --- Controls div/sqrt implementation. --fpu_div_cycles 17 - - -######## Memory Protection Unit --- com.arc.hardware.Memory_Protection_Unit.1_0 ######## - -# Create Memory Protection Unit --create com.arc.hardware.Memory_Protection_Unit.1_0 "System.CPUisle.ARCv2EM.Memory Protection Unit" - -# mpu_num_regions --- Number of configured memory regions. --mpu_num_regions 16 - -# mpu_32b --- Set the minimal region size to be 32 byte instead of 2KB. --mpu_32b false - -# mpu_sid_option --- It will enable SID support in Secure Shield --mpu_sid_option true - - -######## Real-time trace producer --- com.arc.hardware.Real_time_trace_producer.1_0 ######## - -# Create Real-time trace producer --create com.arc.hardware.Real_time_trace_producer.1_0 "System.CPUisle.ARCv2EM.Real-time trace producer" - -# rtt_feature_level --- 'small' means that program trace only is available. `medium' adds data trace. `full' adds core and aux register trace. --rtt_feature_level full - - -######## ARCv2EM CCT --- cct.1_0 ######## - -# Create ARCv2EM CCT --create cct.1_0 "System.ARCv2EM CCT" - -# cct --- -# Option used to add a CCT to the design for command-line builds -# Without this architect can't add this component to a build -# via a cmdline -create command. -# with old scripts. -# --cct true - -# no_hostlink --- -# This prevents the inclusion of the hostlink library when compiling -# C or C++ programs. The resultant executable, if it contains printfs, -# will print to an internal fixed buffer __mwwrite_buf. -# Other hostlink operations that require debugger assistance, such as file -# opens, will fail. -# -# Hostlink references incur memory cycles at unpredictable times and -# so can perturb cycle-timing results. Without hostlink, -# the debugger will not in any way interfere with the target while it is running. -# Therefore this option is useful for simulation in which you want precisely the -# same cycle timing to occur each time you run, or for accurate power consumption results. -# --cct_no_hostlink false - -# has_subsystem_cct_flow --- -# The above option will check for the presence of subsystem component in the build configuration and suitably modifies the Makefile for the sub-system environment. -# --has_subsystem_cct_flow false - - -######## BusFabric --- com.arc.hardware.ARCv2MSS.BusFabric.1_0 ######## - -# Create BusFabric --create com.arc.hardware.ARCv2MSS.BusFabric.1_0 System.BusFabric - -######## ClkCtrl --- com.arc.hardware.ARCv2MSS.ClkCtrl.1_0 ######## - -# Create ClkCtrl --create com.arc.hardware.ARCv2MSS.ClkCtrl.1_0 System.ClkCtrl - -######## DSP Software --- com.arc.software.dfss.sw_dsp.1_0 ######## - -# Create DSP Software --create com.arc.software.dfss.sw_dsp.1_0 "System.DSP Software" - -# sw_dsp --- Command line option for Software element 'DSP Software' --sw_dsp true - - -######## EMSDP_BOARD --- com.arc.hardware.ARCv2MSS.EMSDP_BOARD.1_0 ######## - -# Create EMSDP_BOARD --create com.arc.hardware.ARCv2MSS.EMSDP_BOARD.1_0 System.EMSDP_BOARD - -# emsdp_sys_freq --- Select the core frequency. --emsdp_sys_freq 50 - - -######## IO Software --- com.arc.software.dfss.sw_io.1_0 ######## - -# Create IO Software --create com.arc.software.dfss.sw_io.1_0 "System.IO Software" - -# sw_io --- Command line option for Software element 'IO Software' --sw_io true - - -######## Implementation --- com.arc.hardware.implementation.1_0 ######## - -# Create Implementation --create com.arc.hardware.implementation.1_0 System.Implementation - -# ClockSpeed --- Target clock speed of the system --clock_speed 10 - -# DDR2_clk_Ratio --- DDR2 Clock Vs System Clock Ratio -# 2x -# 3x -# 4x --ddr2_clk_ratio 3x - -# ClockSkew --- The clock skew for the system --clock_skew 0.2 - -# HoldMargin --- Margin for hold time checks --hold_margin 0.05 - -# Floorplan --- Floorplan definition for relative placement of RAMs (at CPU-level) or the placement of the rams and CPU hard cores (at multicore level) --floorplan em4_sensor - -# JTAGFrequency --- Select the frequency of the JTAG clock Tck (in MHz). -# -# The JTAG clock speed has to be less than 1/2 of the cpu clock otherwise the signals on the BVCI interface are not guaranteed to be valid. -# -# NOTE: The RTL simulations will work when the JTAG clock frequency is set to half the CPU clock, however this may not be the case when simulating at gate level due to delays on the IO pads. -# -# The default is set to 10 MHz so that there is no conflict when simulating with an ARCangel3 at 30MHz. (30 > 10*2) -# -# The speed of simulation can be greatly increased by using a faster JTAG clock, but a dependency will warn if it exceeds 1/2 of the cpu clock. -# --jtag_tclk 4 - -# execution_trace_level --- -# This traces committed instructions as they execute, and gathers statistics -# visible in the debugger for counting instructions & cycle delays. -# At the "stats" level ony the statistics are gathered and no trace is printed. -# "file" is equivalent to "full", but the results go to a trace .txt file instead. -# --execution_trace_level stats - -# tb_trace --- -# Enable instruction execution trace. -# This is available to arc_dev licensees (internal developers) only. -# --tb_trace false - -# zero_based_arcnum --- -# In a multicore build, number ARCs from 0. -# If this is not selected, arcs are numbered from 1. -# (This provides the initial value to the arcnum signal.) -# --zero_based_arcnum true - -# generate_ipxact --- -# Generate ipxact.xml file describing the CPUisle or archipelago frontier -# --generate_ipxact false - -# ipxact_relative_path_names --- -# Use relative path names for Verilog files in the ipxact. -# Otherwise, absolute path names are used. -# --ipxact_relative_path_names true - -# optional_encryption --- -# When selected, encrypted RTL output is generated. -# --optional_encryption false - -# ignore_encrypt_license --- -# When selected, pretend the encryption license is missing. For testing. -# --ignore_encrypt_license false - -# ignore_clear_license --- -# When selected, pretend the cleartest license is missing. For testing. -# --ignore_clear_license false - -# OPTION_require_archipelago --- -# When selected, force use of archipelago. This is for testing purposes. -# --require_archipelago false - - -######## Infrastructure Software --- com.arc.software.dfss.sw_infra.1_0 ######## - -# Create Infrastructure Software --create com.arc.software.dfss.sw_infra.1_0 "System.Infrastructure Software" - -# sw_infra --- Command line option for Software element 'Infrastructure Software' --sw_infra true - -# templateName --- Template name --template_name siss_combo_sensor_dsp - - -######## subsys_infra --- com.arc.hardware.dfss.subsys_infra.1_0 ######## - -# Create subsys_infra --create com.arc.hardware.dfss.subsys_infra.1_0 System.subsys_infra - -# subsys_infra --- Command line option for EIA glue logic. --subsys_infra true - -# internal_interrupt --- Connect the IO interrupts internally --internal_interrupt true - -# internal_dma_handshake --- Connect the DMA handshake signals internally --internal_dma_handshake true - -# spi_tb_sw_test_mode --- -# This is a secret option, not seen by customers. -# If you check this, the SPI peripheral's testbenches will be set to SW test mode: -# The serial interface of the first SPI master io_spi_mstN peripheral is connected to all SPI slave peripherals io_spi_slvN. -# This is used for testing the SW drivers. -# --spi_tb_sw_test_mode false - -# i3c_tb_sw_test_mode --- -# This is a secret option, not seen by customers. -# If you check this, the I3C peripheral's testbenches will be set to SW test mode: -# The serial interface of the io_i3cN peripheral is connected to the I2C slave peripherals io_i2c_slv0. -# This is used for testing the SW drivers. -# --i3c_tb_sw_test_mode false - -# subsys_apex_offset --- Subsystem APEX address offset in the AUX address space. The aperture used by the subsystem is fixed to 0x0010_0000. In general, the APEX address offset must be in the range from 0x0010_0000 to 0xFFF0_0000. However, if your design includes the "UAUX Interface" component, then the APEX address offset must be in the range from 0x0010_0000 to 0x7FF0_0000 to avoid address conflicts with any UAUX components. --subsys_apex_offset 0x8000_0000 - -# subsys_uaux_offset --- Subsystem UAUX address offset in the UAUX address space. The UAUX address offset must be an integer multiple of 0x0010_0000 in the range from 0x0000_0000 to 0x7FF0_0000. The aperture reserved for the subsystem is fixed to 0x0010_0000. --subsys_uaux_offset 0x10_0000 - - -######## ARC_RTT --- com.arc.hardware.ARC_RTT.1_0 ######## - -# Create ARC_RTT --create com.arc.hardware.ARC_RTT.1_0 System.ARC_RTT - -# has_nexus_if --- Please select Nexus interface to offload the data from RTT --has_nexus_if true - -# has_on_chip_mem --- Please select the on-chip memory option to store the trace data in shared memory --has_on_chip_mem true - -# nexus_data_wdt --- Please select the Nexus Data Width to offload the data from RTT --nexus_data_wdt 16 - -# internal_memory_size --- Please select internal memory size to capture the trace data --internal_memory_size 16k - -# ram_type --- Please select Types of internal memories to be inferred for the logic --ram_type 1_PORT - -# power_domains --- Adds isolation signal inputs/power switch controls for use in UPF flow when configuring power domains. --rtt_power_domains false - - -######## Tool Configuration --- cgen.1_0 ######## - -# Create Tool Configuration --create cgen.1_0 "System.Tool Configuration" - -# mwdt_version --- Selects the MetaWare version to be used with the TCF file. -# Change from the default to an older or newer toolset version if you want the TCF file to be used with an older or newer version of the MetaWare tools. --mwdt_version O-2018.09 - -# code_base_addr --- -# The base address to assign to the executable code segment in the linker command file when there is no ICCM in the build. This value is ignored when there is an ICCM. -# --code_base_addr 0x0 - -# data_base_addr --- -# The base address to assign to the data segment in the linker command file when the data is not being mapped to a DCCM. This value is ignored when the data segment is mapped to a DCCM, as in that case the base address of the DCCM memory is used. -# -# A value of 0xffffffff means that the data segment will not be mapped to any specific address. -# --data_base_addr 0xffff_ffff - -# underscores_in_numbers --- Use underscores in hex numbers to improve readability. --underscores_in_numbers false - -# tcf_rebrand --- Alternate branding of TCF (not used) --rebrand false - - -]]> - - - - - - - - - - - - - - - ICCM0 - - GROUP BLOCK(4): { - /* _SDA_BASE_ computed implicitly */ - .sdata?: {} - .sbss?: {} - * (DATA): {} - * (BSS): {} - .stack ALIGN(4) SIZE(DEFINED _STACKSIZE?_STACKSIZE:65536): {} - .heap? ALIGN(4) SIZE(DEFINED _HEAPSIZE?_HEAPSIZE:0): {} - } > SYSTEM3 - GROUP BLOCK(4) : { - .vectors (TEXT) SIZE(DEFINED _IVTSIZE?_IVTSIZE:760): {} = FILL(0xa5a5a5a5,4) - } > IVT - GROUP BLOCK(4) : { - .nvectors (TEXT) SIZE(DEFINED _IVTSIZE?_IVTSIZE:760): {} = FILL(0xa5a5a5a5,4) - } > NIVT - } - -]]> - - - - - - 0x07, sub_opcode => 0x1E , latency_cycles => 8) - -// User extension instruction - dsp_sin -extern long dsp_sin(long); -#pragma intrinsic(dsp_sin, opcode => 0x07, sub_opcode => 0x1F , latency_cycles => 8) - -// User extension instruction - dsp_tan -extern long dsp_tan(long); -#pragma intrinsic(dsp_tan, opcode => 0x07, sub_opcode => 0x22 , latency_cycles => 11) - -// User extension instruction - dsp_acos -extern long dsp_acos(long); -#pragma intrinsic(dsp_acos, opcode => 0x07, sub_opcode => 0x23 , latency_cycles => 31) - -// User extension instruction - dsp_asin -extern long dsp_asin(long); -#pragma intrinsic(dsp_asin, opcode => 0x07, sub_opcode => 0x24 , latency_cycles => 31) - -// User extension instruction - dsp_atan -extern long dsp_atan(long); -#pragma intrinsic(dsp_atan, opcode => 0x07, sub_opcode => 0x25 , latency_cycles => 13) - -// User extension instruction - dsp_sqrt -extern long dsp_sqrt(long); -#pragma intrinsic(dsp_sqrt, opcode => 0x07, sub_opcode => 0x20 , latency_cycles => 31) - -// User extension instruction - dsp_sqrt15 -extern long dsp_sqrt15(long); -#pragma intrinsic(dsp_sqrt15, opcode => 0x07, sub_opcode => 0x21 , latency_cycles => 15) - -#define APEX_COM_ARC_HARDWARE_DFSS_DSP_TRIG_PRESENT 1 -#define APEX_COM_ARC_HARDWARE_DFSS_IO_GPIO0_PRESENT 1 - -// User extension aux register io_gpio0_debounce -#define AR_IO_GPIO0_DEBOUNCE 0x80017048 -#pragma Aux_register(0x80017048, name=>"io_gpio0_debounce") - -// User extension aux register io_gpio0_clken -#define AR_IO_GPIO0_CLKEN 0x80017080 -#pragma Aux_register(0x80017080, name=>"io_gpio0_clken") - -// User extension aux register io_gpio0_swporta_dr -#define AR_IO_GPIO0_SWPORTA_DR 0x80017000 -#pragma Aux_register(0x80017000, name=>"io_gpio0_swporta_dr") - -// User extension aux register io_gpio0_swporta_ddr -#define AR_IO_GPIO0_SWPORTA_DDR 0x80017004 -#pragma Aux_register(0x80017004, name=>"io_gpio0_swporta_ddr") - -// User extension aux register io_gpio0_inten -#define AR_IO_GPIO0_INTEN 0x80017030 -#pragma Aux_register(0x80017030, name=>"io_gpio0_inten") - -// User extension aux register io_gpio0_intmask -#define AR_IO_GPIO0_INTMASK 0x80017034 -#pragma Aux_register(0x80017034, name=>"io_gpio0_intmask") - -// User extension aux register io_gpio0_inttype_level -#define AR_IO_GPIO0_INTTYPE_LEVEL 0x80017038 -#pragma Aux_register(0x80017038, name=>"io_gpio0_inttype_level") - -// User extension aux register io_gpio0_int_polarity -#define AR_IO_GPIO0_INT_POLARITY 0x8001703c -#pragma Aux_register(0x8001703c, name=>"io_gpio0_int_polarity") - -// User extension aux register io_gpio0_intstatus -#define AR_IO_GPIO0_INTSTATUS 0x80017040 -#pragma Aux_register(0x80017040, name=>"io_gpio0_intstatus") - -// User extension aux register io_gpio0_raw_intstatus -#define AR_IO_GPIO0_RAW_INTSTATUS 0x80017044 -#pragma Aux_register(0x80017044, name=>"io_gpio0_raw_intstatus") - -// User extension aux register io_gpio0_porta_eoi -#define AR_IO_GPIO0_PORTA_EOI 0x8001704c -#pragma Aux_register(0x8001704c, name=>"io_gpio0_porta_eoi") - -// User extension aux register io_gpio0_ext_porta -#define AR_IO_GPIO0_EXT_PORTA 0x80017050 -#pragma Aux_register(0x80017050, name=>"io_gpio0_ext_porta") - -// User extension aux register io_gpio0_ls_sync -#define AR_IO_GPIO0_LS_SYNC 0x80017060 -#pragma Aux_register(0x80017060, name=>"io_gpio0_ls_sync") - -// User extension aux register io_gpio0_int_bothedge -#define AR_IO_GPIO0_INT_BOTHEDGE 0x80017068 -#pragma Aux_register(0x80017068, name=>"io_gpio0_int_bothedge") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2C_MST0_PRESENT 1 - -// User extension aux register io_i2c_mst0_clken -#define AR_IO_I2C_MST0_CLKEN 0x800120c0 -#pragma Aux_register(0x800120c0, name=>"io_i2c_mst0_clken") - -// User extension aux register io_i2c_mst0_con -#define AR_IO_I2C_MST0_CON 0x80012000 -#pragma Aux_register(0x80012000, name=>"io_i2c_mst0_con") - -// User extension aux register io_i2c_mst0_tar -#define AR_IO_I2C_MST0_TAR 0x80012004 -#pragma Aux_register(0x80012004, name=>"io_i2c_mst0_tar") - -// User extension aux register io_i2c_mst0_data_cmd -#define AR_IO_I2C_MST0_DATA_CMD 0x80012010 -#pragma Aux_register(0x80012010, name=>"io_i2c_mst0_data_cmd") - -// User extension aux register io_i2c_mst0_ss_scl_hcnt -#define AR_IO_I2C_MST0_SS_SCL_HCNT 0x80012014 -#pragma Aux_register(0x80012014, name=>"io_i2c_mst0_ss_scl_hcnt") - -// User extension aux register io_i2c_mst0_ss_scl_lcnt -#define AR_IO_I2C_MST0_SS_SCL_LCNT 0x80012018 -#pragma Aux_register(0x80012018, name=>"io_i2c_mst0_ss_scl_lcnt") - -// User extension aux register io_i2c_mst0_fs_scl_hcnt -#define AR_IO_I2C_MST0_FS_SCL_HCNT 0x8001201c -#pragma Aux_register(0x8001201c, name=>"io_i2c_mst0_fs_scl_hcnt") - -// User extension aux register io_i2c_mst0_fs_scl_lcnt -#define AR_IO_I2C_MST0_FS_SCL_LCNT 0x80012020 -#pragma Aux_register(0x80012020, name=>"io_i2c_mst0_fs_scl_lcnt") - -// User extension aux register io_i2c_mst0_intr_stat -#define AR_IO_I2C_MST0_INTR_STAT 0x8001202c -#pragma Aux_register(0x8001202c, name=>"io_i2c_mst0_intr_stat") - -// User extension aux register io_i2c_mst0_intr_mask -#define AR_IO_I2C_MST0_INTR_MASK 0x80012030 -#pragma Aux_register(0x80012030, name=>"io_i2c_mst0_intr_mask") - -// User extension aux register io_i2c_mst0_raw_intr_stat -#define AR_IO_I2C_MST0_RAW_INTR_STAT 0x80012034 -#pragma Aux_register(0x80012034, name=>"io_i2c_mst0_raw_intr_stat") - -// User extension aux register io_i2c_mst0_rx_tl -#define AR_IO_I2C_MST0_RX_TL 0x80012038 -#pragma Aux_register(0x80012038, name=>"io_i2c_mst0_rx_tl") - -// User extension aux register io_i2c_mst0_tx_tl -#define AR_IO_I2C_MST0_TX_TL 0x8001203c -#pragma Aux_register(0x8001203c, name=>"io_i2c_mst0_tx_tl") - -// User extension aux register io_i2c_mst0_clr_intr -#define AR_IO_I2C_MST0_CLR_INTR 0x80012040 -#pragma Aux_register(0x80012040, name=>"io_i2c_mst0_clr_intr") - -// User extension aux register io_i2c_mst0_clr_rx_under -#define AR_IO_I2C_MST0_CLR_RX_UNDER 0x80012044 -#pragma Aux_register(0x80012044, name=>"io_i2c_mst0_clr_rx_under") - -// User extension aux register io_i2c_mst0_clr_rx_over -#define AR_IO_I2C_MST0_CLR_RX_OVER 0x80012048 -#pragma Aux_register(0x80012048, name=>"io_i2c_mst0_clr_rx_over") - -// User extension aux register io_i2c_mst0_clr_tx_over -#define AR_IO_I2C_MST0_CLR_TX_OVER 0x8001204c -#pragma Aux_register(0x8001204c, name=>"io_i2c_mst0_clr_tx_over") - -// User extension aux register io_i2c_mst0_clr_tx_abrt -#define AR_IO_I2C_MST0_CLR_TX_ABRT 0x80012054 -#pragma Aux_register(0x80012054, name=>"io_i2c_mst0_clr_tx_abrt") - -// User extension aux register io_i2c_mst0_clr_activity -#define AR_IO_I2C_MST0_CLR_ACTIVITY 0x8001205c -#pragma Aux_register(0x8001205c, name=>"io_i2c_mst0_clr_activity") - -// User extension aux register io_i2c_mst0_clr_stop_det -#define AR_IO_I2C_MST0_CLR_STOP_DET 0x80012060 -#pragma Aux_register(0x80012060, name=>"io_i2c_mst0_clr_stop_det") - -// User extension aux register io_i2c_mst0_clr_start_det -#define AR_IO_I2C_MST0_CLR_START_DET 0x80012064 -#pragma Aux_register(0x80012064, name=>"io_i2c_mst0_clr_start_det") - -// User extension aux register io_i2c_mst0_enable -#define AR_IO_I2C_MST0_ENABLE 0x8001206c -#pragma Aux_register(0x8001206c, name=>"io_i2c_mst0_enable") - -// User extension aux register io_i2c_mst0_status -#define AR_IO_I2C_MST0_STATUS 0x80012070 -#pragma Aux_register(0x80012070, name=>"io_i2c_mst0_status") - -// User extension aux register io_i2c_mst0_txflr -#define AR_IO_I2C_MST0_TXFLR 0x80012074 -#pragma Aux_register(0x80012074, name=>"io_i2c_mst0_txflr") - -// User extension aux register io_i2c_mst0_rxflr -#define AR_IO_I2C_MST0_RXFLR 0x80012078 -#pragma Aux_register(0x80012078, name=>"io_i2c_mst0_rxflr") - -// User extension aux register io_i2c_mst0_sda_hold -#define AR_IO_I2C_MST0_SDA_HOLD 0x8001207c -#pragma Aux_register(0x8001207c, name=>"io_i2c_mst0_sda_hold") - -// User extension aux register io_i2c_mst0_tx_abrt_source -#define AR_IO_I2C_MST0_TX_ABRT_SOURCE 0x80012080 -#pragma Aux_register(0x80012080, name=>"io_i2c_mst0_tx_abrt_source") - -// User extension aux register io_i2c_mst0_enable_status -#define AR_IO_I2C_MST0_ENABLE_STATUS 0x8001209c -#pragma Aux_register(0x8001209c, name=>"io_i2c_mst0_enable_status") - -// User extension aux register io_i2c_mst0_fs_spklen -#define AR_IO_I2C_MST0_FS_SPKLEN 0x800120a0 -#pragma Aux_register(0x800120a0, name=>"io_i2c_mst0_fs_spklen") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2C_SLV0_PRESENT 1 - -// User extension aux register io_i2c_slv0_clken -#define AR_IO_I2C_SLV0_CLKEN 0x800130c0 -#pragma Aux_register(0x800130c0, name=>"io_i2c_slv0_clken") - -// User extension aux register io_i2c_slv0_con -#define AR_IO_I2C_SLV0_CON 0x80013000 -#pragma Aux_register(0x80013000, name=>"io_i2c_slv0_con") - -// User extension aux register io_i2c_slv0_sar -#define AR_IO_I2C_SLV0_SAR 0x80013008 -#pragma Aux_register(0x80013008, name=>"io_i2c_slv0_sar") - -// User extension aux register io_i2c_slv0_data_cmd -#define AR_IO_I2C_SLV0_DATA_CMD 0x80013010 -#pragma Aux_register(0x80013010, name=>"io_i2c_slv0_data_cmd") - -// User extension aux register io_i2c_slv0_intr_stat -#define AR_IO_I2C_SLV0_INTR_STAT 0x8001302c -#pragma Aux_register(0x8001302c, name=>"io_i2c_slv0_intr_stat") - -// User extension aux register io_i2c_slv0_intr_mask -#define AR_IO_I2C_SLV0_INTR_MASK 0x80013030 -#pragma Aux_register(0x80013030, name=>"io_i2c_slv0_intr_mask") - -// User extension aux register io_i2c_slv0_raw_intr_stat -#define AR_IO_I2C_SLV0_RAW_INTR_STAT 0x80013034 -#pragma Aux_register(0x80013034, name=>"io_i2c_slv0_raw_intr_stat") - -// User extension aux register io_i2c_slv0_rx_tl -#define AR_IO_I2C_SLV0_RX_TL 0x80013038 -#pragma Aux_register(0x80013038, name=>"io_i2c_slv0_rx_tl") - -// User extension aux register io_i2c_slv0_tx_tl -#define AR_IO_I2C_SLV0_TX_TL 0x8001303c -#pragma Aux_register(0x8001303c, name=>"io_i2c_slv0_tx_tl") - -// User extension aux register io_i2c_slv0_clr_intr -#define AR_IO_I2C_SLV0_CLR_INTR 0x80013040 -#pragma Aux_register(0x80013040, name=>"io_i2c_slv0_clr_intr") - -// User extension aux register io_i2c_slv0_clr_rx_under -#define AR_IO_I2C_SLV0_CLR_RX_UNDER 0x80013044 -#pragma Aux_register(0x80013044, name=>"io_i2c_slv0_clr_rx_under") - -// User extension aux register io_i2c_slv0_clr_rx_over -#define AR_IO_I2C_SLV0_CLR_RX_OVER 0x80013048 -#pragma Aux_register(0x80013048, name=>"io_i2c_slv0_clr_rx_over") - -// User extension aux register io_i2c_slv0_clr_tx_over -#define AR_IO_I2C_SLV0_CLR_TX_OVER 0x8001304c -#pragma Aux_register(0x8001304c, name=>"io_i2c_slv0_clr_tx_over") - -// User extension aux register io_i2c_slv0_clr_rd_req -#define AR_IO_I2C_SLV0_CLR_RD_REQ 0x80013050 -#pragma Aux_register(0x80013050, name=>"io_i2c_slv0_clr_rd_req") - -// User extension aux register io_i2c_slv0_clr_tx_abrt -#define AR_IO_I2C_SLV0_CLR_TX_ABRT 0x80013054 -#pragma Aux_register(0x80013054, name=>"io_i2c_slv0_clr_tx_abrt") - -// User extension aux register io_i2c_slv0_clr_rx_done -#define AR_IO_I2C_SLV0_CLR_RX_DONE 0x80013058 -#pragma Aux_register(0x80013058, name=>"io_i2c_slv0_clr_rx_done") - -// User extension aux register io_i2c_slv0_clr_activity -#define AR_IO_I2C_SLV0_CLR_ACTIVITY 0x8001305c -#pragma Aux_register(0x8001305c, name=>"io_i2c_slv0_clr_activity") - -// User extension aux register io_i2c_slv0_clr_stop_det -#define AR_IO_I2C_SLV0_CLR_STOP_DET 0x80013060 -#pragma Aux_register(0x80013060, name=>"io_i2c_slv0_clr_stop_det") - -// User extension aux register io_i2c_slv0_clr_start_det -#define AR_IO_I2C_SLV0_CLR_START_DET 0x80013064 -#pragma Aux_register(0x80013064, name=>"io_i2c_slv0_clr_start_det") - -// User extension aux register io_i2c_slv0_enable -#define AR_IO_I2C_SLV0_ENABLE 0x8001306c -#pragma Aux_register(0x8001306c, name=>"io_i2c_slv0_enable") - -// User extension aux register io_i2c_slv0_status -#define AR_IO_I2C_SLV0_STATUS 0x80013070 -#pragma Aux_register(0x80013070, name=>"io_i2c_slv0_status") - -// User extension aux register io_i2c_slv0_txflr -#define AR_IO_I2C_SLV0_TXFLR 0x80013074 -#pragma Aux_register(0x80013074, name=>"io_i2c_slv0_txflr") - -// User extension aux register io_i2c_slv0_rxflr -#define AR_IO_I2C_SLV0_RXFLR 0x80013078 -#pragma Aux_register(0x80013078, name=>"io_i2c_slv0_rxflr") - -// User extension aux register io_i2c_slv0_sda_hold -#define AR_IO_I2C_SLV0_SDA_HOLD 0x8001307c -#pragma Aux_register(0x8001307c, name=>"io_i2c_slv0_sda_hold") - -// User extension aux register io_i2c_slv0_tx_abrt_source -#define AR_IO_I2C_SLV0_TX_ABRT_SOURCE 0x80013080 -#pragma Aux_register(0x80013080, name=>"io_i2c_slv0_tx_abrt_source") - -// User extension aux register io_i2c_slv0_sda_setup -#define AR_IO_I2C_SLV0_SDA_SETUP 0x80013094 -#pragma Aux_register(0x80013094, name=>"io_i2c_slv0_sda_setup") - -// User extension aux register io_i2c_slv0_enable_status -#define AR_IO_I2C_SLV0_ENABLE_STATUS 0x8001309c -#pragma Aux_register(0x8001309c, name=>"io_i2c_slv0_enable_status") - -// User extension aux register io_i2c_slv0_fs_spklen -#define AR_IO_I2C_SLV0_FS_SPKLEN 0x800130a0 -#pragma Aux_register(0x800130a0, name=>"io_i2c_slv0_fs_spklen") - -// User extension aux register io_i2c_slv0_clr_restart_det -#define AR_IO_I2C_SLV0_CLR_RESTART_DET 0x800130a8 -#pragma Aux_register(0x800130a8, name=>"io_i2c_slv0_clr_restart_det") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_SPI_MST0_PRESENT 1 - -// User extension aux register io_spi_mst0_ctrlr0 -#define AR_IO_SPI_MST0_CTRLR0 0x80010000 -#pragma Aux_register(0x80010000, name=>"io_spi_mst0_ctrlr0") - -// User extension aux register io_spi_mst0_ctrlr1 -#define AR_IO_SPI_MST0_CTRLR1 0x80010001 -#pragma Aux_register(0x80010001, name=>"io_spi_mst0_ctrlr1") - -// User extension aux register io_spi_mst0_spien -#define AR_IO_SPI_MST0_SPIEN 0x80010002 -#pragma Aux_register(0x80010002, name=>"io_spi_mst0_spien") - -// User extension aux register io_spi_mst0_ser -#define AR_IO_SPI_MST0_SER 0x80010004 -#pragma Aux_register(0x80010004, name=>"io_spi_mst0_ser") - -// User extension aux register io_spi_mst0_baudr -#define AR_IO_SPI_MST0_BAUDR 0x80010005 -#pragma Aux_register(0x80010005, name=>"io_spi_mst0_baudr") - -// User extension aux register io_spi_mst0_txftlr -#define AR_IO_SPI_MST0_TXFTLR 0x80010006 -#pragma Aux_register(0x80010006, name=>"io_spi_mst0_txftlr") - -// User extension aux register io_spi_mst0_rxftlr -#define AR_IO_SPI_MST0_RXFTLR 0x80010007 -#pragma Aux_register(0x80010007, name=>"io_spi_mst0_rxftlr") - -// User extension aux register io_spi_mst0_txflr -#define AR_IO_SPI_MST0_TXFLR 0x80010008 -#pragma Aux_register(0x80010008, name=>"io_spi_mst0_txflr") - -// User extension aux register io_spi_mst0_rxflr -#define AR_IO_SPI_MST0_RXFLR 0x80010009 -#pragma Aux_register(0x80010009, name=>"io_spi_mst0_rxflr") - -// User extension aux register io_spi_mst0_sr -#define AR_IO_SPI_MST0_SR 0x8001000a -#pragma Aux_register(0x8001000a, name=>"io_spi_mst0_sr") - -// User extension aux register io_spi_mst0_imr -#define AR_IO_SPI_MST0_IMR 0x8001000b -#pragma Aux_register(0x8001000b, name=>"io_spi_mst0_imr") - -// User extension aux register io_spi_mst0_isr -#define AR_IO_SPI_MST0_ISR 0x8001000c -#pragma Aux_register(0x8001000c, name=>"io_spi_mst0_isr") - -// User extension aux register io_spi_mst0_risr -#define AR_IO_SPI_MST0_RISR 0x8001000d -#pragma Aux_register(0x8001000d, name=>"io_spi_mst0_risr") - -// User extension aux register io_spi_mst0_txoicr -#define AR_IO_SPI_MST0_TXOICR 0x8001000e -#pragma Aux_register(0x8001000e, name=>"io_spi_mst0_txoicr") - -// User extension aux register io_spi_mst0_rxoicr -#define AR_IO_SPI_MST0_RXOICR 0x8001000f -#pragma Aux_register(0x8001000f, name=>"io_spi_mst0_rxoicr") - -// User extension aux register io_spi_mst0_rxuicr -#define AR_IO_SPI_MST0_RXUICR 0x80010010 -#pragma Aux_register(0x80010010, name=>"io_spi_mst0_rxuicr") - -// User extension aux register io_spi_mst0_icr -#define AR_IO_SPI_MST0_ICR 0x80010012 -#pragma Aux_register(0x80010012, name=>"io_spi_mst0_icr") - -// User extension aux register io_spi_mst0_clken -#define AR_IO_SPI_MST0_CLKEN 0x80010016 -#pragma Aux_register(0x80010016, name=>"io_spi_mst0_clken") - -// User extension aux register io_spi_mst0_dr -#define AR_IO_SPI_MST0_DR 0x80010018 -#pragma Aux_register(0x80010018, name=>"io_spi_mst0_dr") - -// User extension aux register io_spi_mst0_rx_sample_dly -#define AR_IO_SPI_MST0_RX_SAMPLE_DLY 0x8001003c -#pragma Aux_register(0x8001003c, name=>"io_spi_mst0_rx_sample_dly") -#define APEX_COM_ARC_HARDWARE_DFSS_SUBSYS_BCR_PRESENT 1 - -// User extension aux register SUBSYS_BUILD -#define AR_SUBSYS_BUILD 0xf0 -#pragma Aux_register(0xf0, name=>"SUBSYS_BUILD") - -// User extension aux register SUBSYS_DSP_0_BUILD -#define AR_SUBSYS_DSP_0_BUILD 0xa00 -#pragma Aux_register(0xa00, name=>"SUBSYS_DSP_0_BUILD") - -// User extension aux register SUBSYS_DSP_0_CONFIG -#define AR_SUBSYS_DSP_0_CONFIG 0xa02 -#pragma Aux_register(0xa02, name=>"SUBSYS_DSP_0_CONFIG") - -// User extension aux register SUBSYS_IO_0_BUILD -#define AR_SUBSYS_IO_0_BUILD 0xa04 -#pragma Aux_register(0xa04, name=>"SUBSYS_IO_0_BUILD") - -// User extension aux register SUBSYS_IO_1_BUILD -#define AR_SUBSYS_IO_1_BUILD 0xa05 -#pragma Aux_register(0xa05, name=>"SUBSYS_IO_1_BUILD") - -// User extension aux register SUBSYS_IO_2_BUILD -#define AR_SUBSYS_IO_2_BUILD 0xa06 -#pragma Aux_register(0xa06, name=>"SUBSYS_IO_2_BUILD") - -// User extension aux register SUBSYS_UAUX_OFFSET -#define AR_SUBSYS_UAUX_OFFSET 0xa1e -#pragma Aux_register(0xa1e, name=>"SUBSYS_UAUX_OFFSET") - -// User extension aux register SUBSYS_APEX_OFFSET -#define AR_SUBSYS_APEX_OFFSET 0xa1f -#pragma Aux_register(0xa1f, name=>"SUBSYS_APEX_OFFSET") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_SPI_MST1_PRESENT 1 - -// User extension aux register io_spi_mst1_ctrlr0 -#define AR_IO_SPI_MST1_CTRLR0 0x80010100 -#pragma Aux_register(0x80010100, name=>"io_spi_mst1_ctrlr0") - -// User extension aux register io_spi_mst1_ctrlr1 -#define AR_IO_SPI_MST1_CTRLR1 0x80010101 -#pragma Aux_register(0x80010101, name=>"io_spi_mst1_ctrlr1") - -// User extension aux register io_spi_mst1_spien -#define AR_IO_SPI_MST1_SPIEN 0x80010102 -#pragma Aux_register(0x80010102, name=>"io_spi_mst1_spien") - -// User extension aux register io_spi_mst1_ser -#define AR_IO_SPI_MST1_SER 0x80010104 -#pragma Aux_register(0x80010104, name=>"io_spi_mst1_ser") - -// User extension aux register io_spi_mst1_baudr -#define AR_IO_SPI_MST1_BAUDR 0x80010105 -#pragma Aux_register(0x80010105, name=>"io_spi_mst1_baudr") - -// User extension aux register io_spi_mst1_txftlr -#define AR_IO_SPI_MST1_TXFTLR 0x80010106 -#pragma Aux_register(0x80010106, name=>"io_spi_mst1_txftlr") - -// User extension aux register io_spi_mst1_rxftlr -#define AR_IO_SPI_MST1_RXFTLR 0x80010107 -#pragma Aux_register(0x80010107, name=>"io_spi_mst1_rxftlr") - -// User extension aux register io_spi_mst1_txflr -#define AR_IO_SPI_MST1_TXFLR 0x80010108 -#pragma Aux_register(0x80010108, name=>"io_spi_mst1_txflr") - -// User extension aux register io_spi_mst1_rxflr -#define AR_IO_SPI_MST1_RXFLR 0x80010109 -#pragma Aux_register(0x80010109, name=>"io_spi_mst1_rxflr") - -// User extension aux register io_spi_mst1_sr -#define AR_IO_SPI_MST1_SR 0x8001010a -#pragma Aux_register(0x8001010a, name=>"io_spi_mst1_sr") - -// User extension aux register io_spi_mst1_imr -#define AR_IO_SPI_MST1_IMR 0x8001010b -#pragma Aux_register(0x8001010b, name=>"io_spi_mst1_imr") - -// User extension aux register io_spi_mst1_isr -#define AR_IO_SPI_MST1_ISR 0x8001010c -#pragma Aux_register(0x8001010c, name=>"io_spi_mst1_isr") - -// User extension aux register io_spi_mst1_risr -#define AR_IO_SPI_MST1_RISR 0x8001010d -#pragma Aux_register(0x8001010d, name=>"io_spi_mst1_risr") - -// User extension aux register io_spi_mst1_txoicr -#define AR_IO_SPI_MST1_TXOICR 0x8001010e -#pragma Aux_register(0x8001010e, name=>"io_spi_mst1_txoicr") - -// User extension aux register io_spi_mst1_rxoicr -#define AR_IO_SPI_MST1_RXOICR 0x8001010f -#pragma Aux_register(0x8001010f, name=>"io_spi_mst1_rxoicr") - -// User extension aux register io_spi_mst1_rxuicr -#define AR_IO_SPI_MST1_RXUICR 0x80010110 -#pragma Aux_register(0x80010110, name=>"io_spi_mst1_rxuicr") - -// User extension aux register io_spi_mst1_icr -#define AR_IO_SPI_MST1_ICR 0x80010112 -#pragma Aux_register(0x80010112, name=>"io_spi_mst1_icr") - -// User extension aux register io_spi_mst1_clken -#define AR_IO_SPI_MST1_CLKEN 0x80010116 -#pragma Aux_register(0x80010116, name=>"io_spi_mst1_clken") - -// User extension aux register io_spi_mst1_dr -#define AR_IO_SPI_MST1_DR 0x80010118 -#pragma Aux_register(0x80010118, name=>"io_spi_mst1_dr") - -// User extension aux register io_spi_mst1_rx_sample_dly -#define AR_IO_SPI_MST1_RX_SAMPLE_DLY 0x8001013c -#pragma Aux_register(0x8001013c, name=>"io_spi_mst1_rx_sample_dly") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_SPI_MST2_PRESENT 1 - -// User extension aux register io_spi_mst2_ctrlr0 -#define AR_IO_SPI_MST2_CTRLR0 0x80010200 -#pragma Aux_register(0x80010200, name=>"io_spi_mst2_ctrlr0") - -// User extension aux register io_spi_mst2_ctrlr1 -#define AR_IO_SPI_MST2_CTRLR1 0x80010201 -#pragma Aux_register(0x80010201, name=>"io_spi_mst2_ctrlr1") - -// User extension aux register io_spi_mst2_spien -#define AR_IO_SPI_MST2_SPIEN 0x80010202 -#pragma Aux_register(0x80010202, name=>"io_spi_mst2_spien") - -// User extension aux register io_spi_mst2_ser -#define AR_IO_SPI_MST2_SER 0x80010204 -#pragma Aux_register(0x80010204, name=>"io_spi_mst2_ser") - -// User extension aux register io_spi_mst2_baudr -#define AR_IO_SPI_MST2_BAUDR 0x80010205 -#pragma Aux_register(0x80010205, name=>"io_spi_mst2_baudr") - -// User extension aux register io_spi_mst2_txftlr -#define AR_IO_SPI_MST2_TXFTLR 0x80010206 -#pragma Aux_register(0x80010206, name=>"io_spi_mst2_txftlr") - -// User extension aux register io_spi_mst2_rxftlr -#define AR_IO_SPI_MST2_RXFTLR 0x80010207 -#pragma Aux_register(0x80010207, name=>"io_spi_mst2_rxftlr") - -// User extension aux register io_spi_mst2_txflr -#define AR_IO_SPI_MST2_TXFLR 0x80010208 -#pragma Aux_register(0x80010208, name=>"io_spi_mst2_txflr") - -// User extension aux register io_spi_mst2_rxflr -#define AR_IO_SPI_MST2_RXFLR 0x80010209 -#pragma Aux_register(0x80010209, name=>"io_spi_mst2_rxflr") - -// User extension aux register io_spi_mst2_sr -#define AR_IO_SPI_MST2_SR 0x8001020a -#pragma Aux_register(0x8001020a, name=>"io_spi_mst2_sr") - -// User extension aux register io_spi_mst2_imr -#define AR_IO_SPI_MST2_IMR 0x8001020b -#pragma Aux_register(0x8001020b, name=>"io_spi_mst2_imr") - -// User extension aux register io_spi_mst2_isr -#define AR_IO_SPI_MST2_ISR 0x8001020c -#pragma Aux_register(0x8001020c, name=>"io_spi_mst2_isr") - -// User extension aux register io_spi_mst2_risr -#define AR_IO_SPI_MST2_RISR 0x8001020d -#pragma Aux_register(0x8001020d, name=>"io_spi_mst2_risr") - -// User extension aux register io_spi_mst2_txoicr -#define AR_IO_SPI_MST2_TXOICR 0x8001020e -#pragma Aux_register(0x8001020e, name=>"io_spi_mst2_txoicr") - -// User extension aux register io_spi_mst2_rxoicr -#define AR_IO_SPI_MST2_RXOICR 0x8001020f -#pragma Aux_register(0x8001020f, name=>"io_spi_mst2_rxoicr") - -// User extension aux register io_spi_mst2_rxuicr -#define AR_IO_SPI_MST2_RXUICR 0x80010210 -#pragma Aux_register(0x80010210, name=>"io_spi_mst2_rxuicr") - -// User extension aux register io_spi_mst2_icr -#define AR_IO_SPI_MST2_ICR 0x80010212 -#pragma Aux_register(0x80010212, name=>"io_spi_mst2_icr") - -// User extension aux register io_spi_mst2_clken -#define AR_IO_SPI_MST2_CLKEN 0x80010216 -#pragma Aux_register(0x80010216, name=>"io_spi_mst2_clken") - -// User extension aux register io_spi_mst2_dr -#define AR_IO_SPI_MST2_DR 0x80010218 -#pragma Aux_register(0x80010218, name=>"io_spi_mst2_dr") - -// User extension aux register io_spi_mst2_rx_sample_dly -#define AR_IO_SPI_MST2_RX_SAMPLE_DLY 0x8001023c -#pragma Aux_register(0x8001023c, name=>"io_spi_mst2_rx_sample_dly") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_SPI_SLV0_PRESENT 1 - -// User extension aux register io_spi_slv0_ctrlr0 -#define AR_IO_SPI_SLV0_CTRLR0 0x80011000 -#pragma Aux_register(0x80011000, name=>"io_spi_slv0_ctrlr0") - -// User extension aux register io_spi_slv0_spien -#define AR_IO_SPI_SLV0_SPIEN 0x80011002 -#pragma Aux_register(0x80011002, name=>"io_spi_slv0_spien") - -// User extension aux register io_spi_slv0_txftlr -#define AR_IO_SPI_SLV0_TXFTLR 0x80011006 -#pragma Aux_register(0x80011006, name=>"io_spi_slv0_txftlr") - -// User extension aux register io_spi_slv0_rxftlr -#define AR_IO_SPI_SLV0_RXFTLR 0x80011007 -#pragma Aux_register(0x80011007, name=>"io_spi_slv0_rxftlr") - -// User extension aux register io_spi_slv0_txflr -#define AR_IO_SPI_SLV0_TXFLR 0x80011008 -#pragma Aux_register(0x80011008, name=>"io_spi_slv0_txflr") - -// User extension aux register io_spi_slv0_rxflr -#define AR_IO_SPI_SLV0_RXFLR 0x80011009 -#pragma Aux_register(0x80011009, name=>"io_spi_slv0_rxflr") - -// User extension aux register io_spi_slv0_sr -#define AR_IO_SPI_SLV0_SR 0x8001100a -#pragma Aux_register(0x8001100a, name=>"io_spi_slv0_sr") - -// User extension aux register io_spi_slv0_imr -#define AR_IO_SPI_SLV0_IMR 0x8001100b -#pragma Aux_register(0x8001100b, name=>"io_spi_slv0_imr") - -// User extension aux register io_spi_slv0_isr -#define AR_IO_SPI_SLV0_ISR 0x8001100c -#pragma Aux_register(0x8001100c, name=>"io_spi_slv0_isr") - -// User extension aux register io_spi_slv0_risr -#define AR_IO_SPI_SLV0_RISR 0x8001100d -#pragma Aux_register(0x8001100d, name=>"io_spi_slv0_risr") - -// User extension aux register io_spi_slv0_txoicr -#define AR_IO_SPI_SLV0_TXOICR 0x8001100e -#pragma Aux_register(0x8001100e, name=>"io_spi_slv0_txoicr") - -// User extension aux register io_spi_slv0_rxoicr -#define AR_IO_SPI_SLV0_RXOICR 0x8001100f -#pragma Aux_register(0x8001100f, name=>"io_spi_slv0_rxoicr") - -// User extension aux register io_spi_slv0_rxuicr -#define AR_IO_SPI_SLV0_RXUICR 0x80011010 -#pragma Aux_register(0x80011010, name=>"io_spi_slv0_rxuicr") - -// User extension aux register io_spi_slv0_icr -#define AR_IO_SPI_SLV0_ICR 0x80011012 -#pragma Aux_register(0x80011012, name=>"io_spi_slv0_icr") - -// User extension aux register io_spi_slv0_clken -#define AR_IO_SPI_SLV0_CLKEN 0x80011016 -#pragma Aux_register(0x80011016, name=>"io_spi_slv0_clken") - -// User extension aux register io_spi_slv0_dr -#define AR_IO_SPI_SLV0_DR 0x80011018 -#pragma Aux_register(0x80011018, name=>"io_spi_slv0_dr") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_GPIO1_PRESENT 1 - -// User extension aux register io_gpio1_debounce -#define AR_IO_GPIO1_DEBOUNCE 0x80017148 -#pragma Aux_register(0x80017148, name=>"io_gpio1_debounce") - -// User extension aux register io_gpio1_clken -#define AR_IO_GPIO1_CLKEN 0x80017180 -#pragma Aux_register(0x80017180, name=>"io_gpio1_clken") - -// User extension aux register io_gpio1_swporta_dr -#define AR_IO_GPIO1_SWPORTA_DR 0x80017100 -#pragma Aux_register(0x80017100, name=>"io_gpio1_swporta_dr") - -// User extension aux register io_gpio1_swporta_ddr -#define AR_IO_GPIO1_SWPORTA_DDR 0x80017104 -#pragma Aux_register(0x80017104, name=>"io_gpio1_swporta_ddr") - -// User extension aux register io_gpio1_inten -#define AR_IO_GPIO1_INTEN 0x80017130 -#pragma Aux_register(0x80017130, name=>"io_gpio1_inten") - -// User extension aux register io_gpio1_intmask -#define AR_IO_GPIO1_INTMASK 0x80017134 -#pragma Aux_register(0x80017134, name=>"io_gpio1_intmask") - -// User extension aux register io_gpio1_inttype_level -#define AR_IO_GPIO1_INTTYPE_LEVEL 0x80017138 -#pragma Aux_register(0x80017138, name=>"io_gpio1_inttype_level") - -// User extension aux register io_gpio1_int_polarity -#define AR_IO_GPIO1_INT_POLARITY 0x8001713c -#pragma Aux_register(0x8001713c, name=>"io_gpio1_int_polarity") - -// User extension aux register io_gpio1_intstatus -#define AR_IO_GPIO1_INTSTATUS 0x80017140 -#pragma Aux_register(0x80017140, name=>"io_gpio1_intstatus") - -// User extension aux register io_gpio1_raw_intstatus -#define AR_IO_GPIO1_RAW_INTSTATUS 0x80017144 -#pragma Aux_register(0x80017144, name=>"io_gpio1_raw_intstatus") - -// User extension aux register io_gpio1_porta_eoi -#define AR_IO_GPIO1_PORTA_EOI 0x8001714c -#pragma Aux_register(0x8001714c, name=>"io_gpio1_porta_eoi") - -// User extension aux register io_gpio1_ext_porta -#define AR_IO_GPIO1_EXT_PORTA 0x80017150 -#pragma Aux_register(0x80017150, name=>"io_gpio1_ext_porta") - -// User extension aux register io_gpio1_ls_sync -#define AR_IO_GPIO1_LS_SYNC 0x80017160 -#pragma Aux_register(0x80017160, name=>"io_gpio1_ls_sync") - -// User extension aux register io_gpio1_int_bothedge -#define AR_IO_GPIO1_INT_BOTHEDGE 0x80017168 -#pragma Aux_register(0x80017168, name=>"io_gpio1_int_bothedge") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_GPIO2_PRESENT 1 - -// User extension aux register io_gpio2_debounce -#define AR_IO_GPIO2_DEBOUNCE 0x80017248 -#pragma Aux_register(0x80017248, name=>"io_gpio2_debounce") - -// User extension aux register io_gpio2_clken -#define AR_IO_GPIO2_CLKEN 0x80017280 -#pragma Aux_register(0x80017280, name=>"io_gpio2_clken") - -// User extension aux register io_gpio2_swporta_dr -#define AR_IO_GPIO2_SWPORTA_DR 0x80017200 -#pragma Aux_register(0x80017200, name=>"io_gpio2_swporta_dr") - -// User extension aux register io_gpio2_swporta_ddr -#define AR_IO_GPIO2_SWPORTA_DDR 0x80017204 -#pragma Aux_register(0x80017204, name=>"io_gpio2_swporta_ddr") - -// User extension aux register io_gpio2_inten -#define AR_IO_GPIO2_INTEN 0x80017230 -#pragma Aux_register(0x80017230, name=>"io_gpio2_inten") - -// User extension aux register io_gpio2_intmask -#define AR_IO_GPIO2_INTMASK 0x80017234 -#pragma Aux_register(0x80017234, name=>"io_gpio2_intmask") - -// User extension aux register io_gpio2_inttype_level -#define AR_IO_GPIO2_INTTYPE_LEVEL 0x80017238 -#pragma Aux_register(0x80017238, name=>"io_gpio2_inttype_level") - -// User extension aux register io_gpio2_int_polarity -#define AR_IO_GPIO2_INT_POLARITY 0x8001723c -#pragma Aux_register(0x8001723c, name=>"io_gpio2_int_polarity") - -// User extension aux register io_gpio2_intstatus -#define AR_IO_GPIO2_INTSTATUS 0x80017240 -#pragma Aux_register(0x80017240, name=>"io_gpio2_intstatus") - -// User extension aux register io_gpio2_raw_intstatus -#define AR_IO_GPIO2_RAW_INTSTATUS 0x80017244 -#pragma Aux_register(0x80017244, name=>"io_gpio2_raw_intstatus") - -// User extension aux register io_gpio2_porta_eoi -#define AR_IO_GPIO2_PORTA_EOI 0x8001724c -#pragma Aux_register(0x8001724c, name=>"io_gpio2_porta_eoi") - -// User extension aux register io_gpio2_ext_porta -#define AR_IO_GPIO2_EXT_PORTA 0x80017250 -#pragma Aux_register(0x80017250, name=>"io_gpio2_ext_porta") - -// User extension aux register io_gpio2_ls_sync -#define AR_IO_GPIO2_LS_SYNC 0x80017260 -#pragma Aux_register(0x80017260, name=>"io_gpio2_ls_sync") - -// User extension aux register io_gpio2_int_bothedge -#define AR_IO_GPIO2_INT_BOTHEDGE 0x80017268 -#pragma Aux_register(0x80017268, name=>"io_gpio2_int_bothedge") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2C_MST1_PRESENT 1 - -// User extension aux register io_i2c_mst1_clken -#define AR_IO_I2C_MST1_CLKEN 0x800121c0 -#pragma Aux_register(0x800121c0, name=>"io_i2c_mst1_clken") - -// User extension aux register io_i2c_mst1_con -#define AR_IO_I2C_MST1_CON 0x80012100 -#pragma Aux_register(0x80012100, name=>"io_i2c_mst1_con") - -// User extension aux register io_i2c_mst1_tar -#define AR_IO_I2C_MST1_TAR 0x80012104 -#pragma Aux_register(0x80012104, name=>"io_i2c_mst1_tar") - -// User extension aux register io_i2c_mst1_data_cmd -#define AR_IO_I2C_MST1_DATA_CMD 0x80012110 -#pragma Aux_register(0x80012110, name=>"io_i2c_mst1_data_cmd") - -// User extension aux register io_i2c_mst1_ss_scl_hcnt -#define AR_IO_I2C_MST1_SS_SCL_HCNT 0x80012114 -#pragma Aux_register(0x80012114, name=>"io_i2c_mst1_ss_scl_hcnt") - -// User extension aux register io_i2c_mst1_ss_scl_lcnt -#define AR_IO_I2C_MST1_SS_SCL_LCNT 0x80012118 -#pragma Aux_register(0x80012118, name=>"io_i2c_mst1_ss_scl_lcnt") - -// User extension aux register io_i2c_mst1_fs_scl_hcnt -#define AR_IO_I2C_MST1_FS_SCL_HCNT 0x8001211c -#pragma Aux_register(0x8001211c, name=>"io_i2c_mst1_fs_scl_hcnt") - -// User extension aux register io_i2c_mst1_fs_scl_lcnt -#define AR_IO_I2C_MST1_FS_SCL_LCNT 0x80012120 -#pragma Aux_register(0x80012120, name=>"io_i2c_mst1_fs_scl_lcnt") - -// User extension aux register io_i2c_mst1_intr_stat -#define AR_IO_I2C_MST1_INTR_STAT 0x8001212c -#pragma Aux_register(0x8001212c, name=>"io_i2c_mst1_intr_stat") - -// User extension aux register io_i2c_mst1_intr_mask -#define AR_IO_I2C_MST1_INTR_MASK 0x80012130 -#pragma Aux_register(0x80012130, name=>"io_i2c_mst1_intr_mask") - -// User extension aux register io_i2c_mst1_raw_intr_stat -#define AR_IO_I2C_MST1_RAW_INTR_STAT 0x80012134 -#pragma Aux_register(0x80012134, name=>"io_i2c_mst1_raw_intr_stat") - -// User extension aux register io_i2c_mst1_rx_tl -#define AR_IO_I2C_MST1_RX_TL 0x80012138 -#pragma Aux_register(0x80012138, name=>"io_i2c_mst1_rx_tl") - -// User extension aux register io_i2c_mst1_tx_tl -#define AR_IO_I2C_MST1_TX_TL 0x8001213c -#pragma Aux_register(0x8001213c, name=>"io_i2c_mst1_tx_tl") - -// User extension aux register io_i2c_mst1_clr_intr -#define AR_IO_I2C_MST1_CLR_INTR 0x80012140 -#pragma Aux_register(0x80012140, name=>"io_i2c_mst1_clr_intr") - -// User extension aux register io_i2c_mst1_clr_rx_under -#define AR_IO_I2C_MST1_CLR_RX_UNDER 0x80012144 -#pragma Aux_register(0x80012144, name=>"io_i2c_mst1_clr_rx_under") - -// User extension aux register io_i2c_mst1_clr_rx_over -#define AR_IO_I2C_MST1_CLR_RX_OVER 0x80012148 -#pragma Aux_register(0x80012148, name=>"io_i2c_mst1_clr_rx_over") - -// User extension aux register io_i2c_mst1_clr_tx_over -#define AR_IO_I2C_MST1_CLR_TX_OVER 0x8001214c -#pragma Aux_register(0x8001214c, name=>"io_i2c_mst1_clr_tx_over") - -// User extension aux register io_i2c_mst1_clr_tx_abrt -#define AR_IO_I2C_MST1_CLR_TX_ABRT 0x80012154 -#pragma Aux_register(0x80012154, name=>"io_i2c_mst1_clr_tx_abrt") - -// User extension aux register io_i2c_mst1_clr_activity -#define AR_IO_I2C_MST1_CLR_ACTIVITY 0x8001215c -#pragma Aux_register(0x8001215c, name=>"io_i2c_mst1_clr_activity") - -// User extension aux register io_i2c_mst1_clr_stop_det -#define AR_IO_I2C_MST1_CLR_STOP_DET 0x80012160 -#pragma Aux_register(0x80012160, name=>"io_i2c_mst1_clr_stop_det") - -// User extension aux register io_i2c_mst1_clr_start_det -#define AR_IO_I2C_MST1_CLR_START_DET 0x80012164 -#pragma Aux_register(0x80012164, name=>"io_i2c_mst1_clr_start_det") - -// User extension aux register io_i2c_mst1_enable -#define AR_IO_I2C_MST1_ENABLE 0x8001216c -#pragma Aux_register(0x8001216c, name=>"io_i2c_mst1_enable") - -// User extension aux register io_i2c_mst1_status -#define AR_IO_I2C_MST1_STATUS 0x80012170 -#pragma Aux_register(0x80012170, name=>"io_i2c_mst1_status") - -// User extension aux register io_i2c_mst1_txflr -#define AR_IO_I2C_MST1_TXFLR 0x80012174 -#pragma Aux_register(0x80012174, name=>"io_i2c_mst1_txflr") - -// User extension aux register io_i2c_mst1_rxflr -#define AR_IO_I2C_MST1_RXFLR 0x80012178 -#pragma Aux_register(0x80012178, name=>"io_i2c_mst1_rxflr") - -// User extension aux register io_i2c_mst1_sda_hold -#define AR_IO_I2C_MST1_SDA_HOLD 0x8001217c -#pragma Aux_register(0x8001217c, name=>"io_i2c_mst1_sda_hold") - -// User extension aux register io_i2c_mst1_tx_abrt_source -#define AR_IO_I2C_MST1_TX_ABRT_SOURCE 0x80012180 -#pragma Aux_register(0x80012180, name=>"io_i2c_mst1_tx_abrt_source") - -// User extension aux register io_i2c_mst1_enable_status -#define AR_IO_I2C_MST1_ENABLE_STATUS 0x8001219c -#pragma Aux_register(0x8001219c, name=>"io_i2c_mst1_enable_status") - -// User extension aux register io_i2c_mst1_fs_spklen -#define AR_IO_I2C_MST1_FS_SPKLEN 0x800121a0 -#pragma Aux_register(0x800121a0, name=>"io_i2c_mst1_fs_spklen") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2C_MST2_PRESENT 1 - -// User extension aux register io_i2c_mst2_clken -#define AR_IO_I2C_MST2_CLKEN 0x800122c0 -#pragma Aux_register(0x800122c0, name=>"io_i2c_mst2_clken") - -// User extension aux register io_i2c_mst2_con -#define AR_IO_I2C_MST2_CON 0x80012200 -#pragma Aux_register(0x80012200, name=>"io_i2c_mst2_con") - -// User extension aux register io_i2c_mst2_tar -#define AR_IO_I2C_MST2_TAR 0x80012204 -#pragma Aux_register(0x80012204, name=>"io_i2c_mst2_tar") - -// User extension aux register io_i2c_mst2_data_cmd -#define AR_IO_I2C_MST2_DATA_CMD 0x80012210 -#pragma Aux_register(0x80012210, name=>"io_i2c_mst2_data_cmd") - -// User extension aux register io_i2c_mst2_ss_scl_hcnt -#define AR_IO_I2C_MST2_SS_SCL_HCNT 0x80012214 -#pragma Aux_register(0x80012214, name=>"io_i2c_mst2_ss_scl_hcnt") - -// User extension aux register io_i2c_mst2_ss_scl_lcnt -#define AR_IO_I2C_MST2_SS_SCL_LCNT 0x80012218 -#pragma Aux_register(0x80012218, name=>"io_i2c_mst2_ss_scl_lcnt") - -// User extension aux register io_i2c_mst2_fs_scl_hcnt -#define AR_IO_I2C_MST2_FS_SCL_HCNT 0x8001221c -#pragma Aux_register(0x8001221c, name=>"io_i2c_mst2_fs_scl_hcnt") - -// User extension aux register io_i2c_mst2_fs_scl_lcnt -#define AR_IO_I2C_MST2_FS_SCL_LCNT 0x80012220 -#pragma Aux_register(0x80012220, name=>"io_i2c_mst2_fs_scl_lcnt") - -// User extension aux register io_i2c_mst2_intr_stat -#define AR_IO_I2C_MST2_INTR_STAT 0x8001222c -#pragma Aux_register(0x8001222c, name=>"io_i2c_mst2_intr_stat") - -// User extension aux register io_i2c_mst2_intr_mask -#define AR_IO_I2C_MST2_INTR_MASK 0x80012230 -#pragma Aux_register(0x80012230, name=>"io_i2c_mst2_intr_mask") - -// User extension aux register io_i2c_mst2_raw_intr_stat -#define AR_IO_I2C_MST2_RAW_INTR_STAT 0x80012234 -#pragma Aux_register(0x80012234, name=>"io_i2c_mst2_raw_intr_stat") - -// User extension aux register io_i2c_mst2_rx_tl -#define AR_IO_I2C_MST2_RX_TL 0x80012238 -#pragma Aux_register(0x80012238, name=>"io_i2c_mst2_rx_tl") - -// User extension aux register io_i2c_mst2_tx_tl -#define AR_IO_I2C_MST2_TX_TL 0x8001223c -#pragma Aux_register(0x8001223c, name=>"io_i2c_mst2_tx_tl") - -// User extension aux register io_i2c_mst2_clr_intr -#define AR_IO_I2C_MST2_CLR_INTR 0x80012240 -#pragma Aux_register(0x80012240, name=>"io_i2c_mst2_clr_intr") - -// User extension aux register io_i2c_mst2_clr_rx_under -#define AR_IO_I2C_MST2_CLR_RX_UNDER 0x80012244 -#pragma Aux_register(0x80012244, name=>"io_i2c_mst2_clr_rx_under") - -// User extension aux register io_i2c_mst2_clr_rx_over -#define AR_IO_I2C_MST2_CLR_RX_OVER 0x80012248 -#pragma Aux_register(0x80012248, name=>"io_i2c_mst2_clr_rx_over") - -// User extension aux register io_i2c_mst2_clr_tx_over -#define AR_IO_I2C_MST2_CLR_TX_OVER 0x8001224c -#pragma Aux_register(0x8001224c, name=>"io_i2c_mst2_clr_tx_over") - -// User extension aux register io_i2c_mst2_clr_tx_abrt -#define AR_IO_I2C_MST2_CLR_TX_ABRT 0x80012254 -#pragma Aux_register(0x80012254, name=>"io_i2c_mst2_clr_tx_abrt") - -// User extension aux register io_i2c_mst2_clr_activity -#define AR_IO_I2C_MST2_CLR_ACTIVITY 0x8001225c -#pragma Aux_register(0x8001225c, name=>"io_i2c_mst2_clr_activity") - -// User extension aux register io_i2c_mst2_clr_stop_det -#define AR_IO_I2C_MST2_CLR_STOP_DET 0x80012260 -#pragma Aux_register(0x80012260, name=>"io_i2c_mst2_clr_stop_det") - -// User extension aux register io_i2c_mst2_clr_start_det -#define AR_IO_I2C_MST2_CLR_START_DET 0x80012264 -#pragma Aux_register(0x80012264, name=>"io_i2c_mst2_clr_start_det") - -// User extension aux register io_i2c_mst2_enable -#define AR_IO_I2C_MST2_ENABLE 0x8001226c -#pragma Aux_register(0x8001226c, name=>"io_i2c_mst2_enable") - -// User extension aux register io_i2c_mst2_status -#define AR_IO_I2C_MST2_STATUS 0x80012270 -#pragma Aux_register(0x80012270, name=>"io_i2c_mst2_status") - -// User extension aux register io_i2c_mst2_txflr -#define AR_IO_I2C_MST2_TXFLR 0x80012274 -#pragma Aux_register(0x80012274, name=>"io_i2c_mst2_txflr") - -// User extension aux register io_i2c_mst2_rxflr -#define AR_IO_I2C_MST2_RXFLR 0x80012278 -#pragma Aux_register(0x80012278, name=>"io_i2c_mst2_rxflr") - -// User extension aux register io_i2c_mst2_sda_hold -#define AR_IO_I2C_MST2_SDA_HOLD 0x8001227c -#pragma Aux_register(0x8001227c, name=>"io_i2c_mst2_sda_hold") - -// User extension aux register io_i2c_mst2_tx_abrt_source -#define AR_IO_I2C_MST2_TX_ABRT_SOURCE 0x80012280 -#pragma Aux_register(0x80012280, name=>"io_i2c_mst2_tx_abrt_source") - -// User extension aux register io_i2c_mst2_enable_status -#define AR_IO_I2C_MST2_ENABLE_STATUS 0x8001229c -#pragma Aux_register(0x8001229c, name=>"io_i2c_mst2_enable_status") - -// User extension aux register io_i2c_mst2_fs_spklen -#define AR_IO_I2C_MST2_FS_SPKLEN 0x800122a0 -#pragma Aux_register(0x800122a0, name=>"io_i2c_mst2_fs_spklen") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_UART0_PRESENT 1 - -// User extension aux register io_uart0_clken -#define AR_IO_UART0_CLKEN 0x800140c0 -#pragma Aux_register(0x800140c0, name=>"io_uart0_clken") - -// User extension aux register io_uart0_rbr_thr_dll -#define AR_IO_UART0_RBR_THR_DLL 0x80014000 -#pragma Aux_register(0x80014000, name=>"io_uart0_rbr_thr_dll") - -// User extension aux register io_uart0_ier_dlh -#define AR_IO_UART0_IER_DLH 0x80014004 -#pragma Aux_register(0x80014004, name=>"io_uart0_ier_dlh") - -// User extension aux register io_uart0_iir_fcr -#define AR_IO_UART0_IIR_FCR 0x80014008 -#pragma Aux_register(0x80014008, name=>"io_uart0_iir_fcr") - -// User extension aux register io_uart0_lcr -#define AR_IO_UART0_LCR 0x8001400c -#pragma Aux_register(0x8001400c, name=>"io_uart0_lcr") - -// User extension aux register io_uart0_mcr -#define AR_IO_UART0_MCR 0x80014010 -#pragma Aux_register(0x80014010, name=>"io_uart0_mcr") - -// User extension aux register io_uart0_lsr -#define AR_IO_UART0_LSR 0x80014014 -#pragma Aux_register(0x80014014, name=>"io_uart0_lsr") - -// User extension aux register io_uart0_msr -#define AR_IO_UART0_MSR 0x80014018 -#pragma Aux_register(0x80014018, name=>"io_uart0_msr") - -// User extension aux register io_uart0_usr -#define AR_IO_UART0_USR 0x8001407c -#pragma Aux_register(0x8001407c, name=>"io_uart0_usr") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_UART1_PRESENT 1 - -// User extension aux register io_uart1_clken -#define AR_IO_UART1_CLKEN 0x800141c0 -#pragma Aux_register(0x800141c0, name=>"io_uart1_clken") - -// User extension aux register io_uart1_rbr_thr_dll -#define AR_IO_UART1_RBR_THR_DLL 0x80014100 -#pragma Aux_register(0x80014100, name=>"io_uart1_rbr_thr_dll") - -// User extension aux register io_uart1_ier_dlh -#define AR_IO_UART1_IER_DLH 0x80014104 -#pragma Aux_register(0x80014104, name=>"io_uart1_ier_dlh") - -// User extension aux register io_uart1_iir_fcr -#define AR_IO_UART1_IIR_FCR 0x80014108 -#pragma Aux_register(0x80014108, name=>"io_uart1_iir_fcr") - -// User extension aux register io_uart1_lcr -#define AR_IO_UART1_LCR 0x8001410c -#pragma Aux_register(0x8001410c, name=>"io_uart1_lcr") - -// User extension aux register io_uart1_mcr -#define AR_IO_UART1_MCR 0x80014110 -#pragma Aux_register(0x80014110, name=>"io_uart1_mcr") - -// User extension aux register io_uart1_lsr -#define AR_IO_UART1_LSR 0x80014114 -#pragma Aux_register(0x80014114, name=>"io_uart1_lsr") - -// User extension aux register io_uart1_msr -#define AR_IO_UART1_MSR 0x80014118 -#pragma Aux_register(0x80014118, name=>"io_uart1_msr") - -// User extension aux register io_uart1_usr -#define AR_IO_UART1_USR 0x8001417c -#pragma Aux_register(0x8001417c, name=>"io_uart1_usr") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_UART2_PRESENT 1 - -// User extension aux register io_uart2_clken -#define AR_IO_UART2_CLKEN 0x800142c0 -#pragma Aux_register(0x800142c0, name=>"io_uart2_clken") - -// User extension aux register io_uart2_rbr_thr_dll -#define AR_IO_UART2_RBR_THR_DLL 0x80014200 -#pragma Aux_register(0x80014200, name=>"io_uart2_rbr_thr_dll") - -// User extension aux register io_uart2_ier_dlh -#define AR_IO_UART2_IER_DLH 0x80014204 -#pragma Aux_register(0x80014204, name=>"io_uart2_ier_dlh") - -// User extension aux register io_uart2_iir_fcr -#define AR_IO_UART2_IIR_FCR 0x80014208 -#pragma Aux_register(0x80014208, name=>"io_uart2_iir_fcr") - -// User extension aux register io_uart2_lcr -#define AR_IO_UART2_LCR 0x8001420c -#pragma Aux_register(0x8001420c, name=>"io_uart2_lcr") - -// User extension aux register io_uart2_mcr -#define AR_IO_UART2_MCR 0x80014210 -#pragma Aux_register(0x80014210, name=>"io_uart2_mcr") - -// User extension aux register io_uart2_lsr -#define AR_IO_UART2_LSR 0x80014214 -#pragma Aux_register(0x80014214, name=>"io_uart2_lsr") - -// User extension aux register io_uart2_msr -#define AR_IO_UART2_MSR 0x80014218 -#pragma Aux_register(0x80014218, name=>"io_uart2_msr") - -// User extension aux register io_uart2_usr -#define AR_IO_UART2_USR 0x8001427c -#pragma Aux_register(0x8001427c, name=>"io_uart2_usr") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_UART3_PRESENT 1 - -// User extension aux register io_uart3_clken -#define AR_IO_UART3_CLKEN 0x800143c0 -#pragma Aux_register(0x800143c0, name=>"io_uart3_clken") - -// User extension aux register io_uart3_rbr_thr_dll -#define AR_IO_UART3_RBR_THR_DLL 0x80014300 -#pragma Aux_register(0x80014300, name=>"io_uart3_rbr_thr_dll") - -// User extension aux register io_uart3_ier_dlh -#define AR_IO_UART3_IER_DLH 0x80014304 -#pragma Aux_register(0x80014304, name=>"io_uart3_ier_dlh") - -// User extension aux register io_uart3_iir_fcr -#define AR_IO_UART3_IIR_FCR 0x80014308 -#pragma Aux_register(0x80014308, name=>"io_uart3_iir_fcr") - -// User extension aux register io_uart3_lcr -#define AR_IO_UART3_LCR 0x8001430c -#pragma Aux_register(0x8001430c, name=>"io_uart3_lcr") - -// User extension aux register io_uart3_mcr -#define AR_IO_UART3_MCR 0x80014310 -#pragma Aux_register(0x80014310, name=>"io_uart3_mcr") - -// User extension aux register io_uart3_lsr -#define AR_IO_UART3_LSR 0x80014314 -#pragma Aux_register(0x80014314, name=>"io_uart3_lsr") - -// User extension aux register io_uart3_msr -#define AR_IO_UART3_MSR 0x80014318 -#pragma Aux_register(0x80014318, name=>"io_uart3_msr") - -// User extension aux register io_uart3_usr -#define AR_IO_UART3_USR 0x8001437c -#pragma Aux_register(0x8001437c, name=>"io_uart3_usr") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2S_RX_MST0_PRESENT 1 - -// User extension aux register io_i2s_rx_mst0_ier -#define AR_IO_I2S_RX_MST0_IER 0x8001a000 -#pragma Aux_register(0x8001a000, name=>"io_i2s_rx_mst0_ier") - -// User extension aux register io_i2s_rx_mst0_irer -#define AR_IO_I2S_RX_MST0_IRER 0x8001a004 -#pragma Aux_register(0x8001a004, name=>"io_i2s_rx_mst0_irer") - -// User extension aux register io_i2s_rx_mst0_cer -#define AR_IO_I2S_RX_MST0_CER 0x8001a00c -#pragma Aux_register(0x8001a00c, name=>"io_i2s_rx_mst0_cer") - -// User extension aux register io_i2s_rx_mst0_ccr -#define AR_IO_I2S_RX_MST0_CCR 0x8001a010 -#pragma Aux_register(0x8001a010, name=>"io_i2s_rx_mst0_ccr") - -// User extension aux register io_i2s_rx_mst0_rxffr -#define AR_IO_I2S_RX_MST0_RXFFR 0x8001a014 -#pragma Aux_register(0x8001a014, name=>"io_i2s_rx_mst0_rxffr") - -// User extension aux register io_i2s_rx_mst0_lrbr -#define AR_IO_I2S_RX_MST0_LRBR 0x8001a020 -#pragma Aux_register(0x8001a020, name=>"io_i2s_rx_mst0_lrbr") - -// User extension aux register io_i2s_rx_mst0_rrbr -#define AR_IO_I2S_RX_MST0_RRBR 0x8001a024 -#pragma Aux_register(0x8001a024, name=>"io_i2s_rx_mst0_rrbr") - -// User extension aux register io_i2s_rx_mst0_rer -#define AR_IO_I2S_RX_MST0_RER 0x8001a028 -#pragma Aux_register(0x8001a028, name=>"io_i2s_rx_mst0_rer") - -// User extension aux register io_i2s_rx_mst0_rcr -#define AR_IO_I2S_RX_MST0_RCR 0x8001a030 -#pragma Aux_register(0x8001a030, name=>"io_i2s_rx_mst0_rcr") - -// User extension aux register io_i2s_rx_mst0_isr -#define AR_IO_I2S_RX_MST0_ISR 0x8001a038 -#pragma Aux_register(0x8001a038, name=>"io_i2s_rx_mst0_isr") - -// User extension aux register io_i2s_rx_mst0_imr -#define AR_IO_I2S_RX_MST0_IMR 0x8001a03c -#pragma Aux_register(0x8001a03c, name=>"io_i2s_rx_mst0_imr") - -// User extension aux register io_i2s_rx_mst0_ror -#define AR_IO_I2S_RX_MST0_ROR 0x8001a040 -#pragma Aux_register(0x8001a040, name=>"io_i2s_rx_mst0_ror") - -// User extension aux register io_i2s_rx_mst0_rfcr -#define AR_IO_I2S_RX_MST0_RFCR 0x8001a048 -#pragma Aux_register(0x8001a048, name=>"io_i2s_rx_mst0_rfcr") - -// User extension aux register io_i2s_rx_mst0_rff -#define AR_IO_I2S_RX_MST0_RFF 0x8001a050 -#pragma Aux_register(0x8001a050, name=>"io_i2s_rx_mst0_rff") - -// User extension aux register io_i2s_rx_mst0_rxdma -#define AR_IO_I2S_RX_MST0_RXDMA 0x8001a1c0 -#pragma Aux_register(0x8001a1c0, name=>"io_i2s_rx_mst0_rxdma") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_I2S_TX_MST0_PRESENT 1 - -// User extension aux register io_i2s_tx_mst0_ier -#define AR_IO_I2S_TX_MST0_IER 0x80019000 -#pragma Aux_register(0x80019000, name=>"io_i2s_tx_mst0_ier") - -// User extension aux register io_i2s_tx_mst0_iter -#define AR_IO_I2S_TX_MST0_ITER 0x80019008 -#pragma Aux_register(0x80019008, name=>"io_i2s_tx_mst0_iter") - -// User extension aux register io_i2s_tx_mst0_cer -#define AR_IO_I2S_TX_MST0_CER 0x8001900c -#pragma Aux_register(0x8001900c, name=>"io_i2s_tx_mst0_cer") - -// User extension aux register io_i2s_tx_mst0_ccr -#define AR_IO_I2S_TX_MST0_CCR 0x80019010 -#pragma Aux_register(0x80019010, name=>"io_i2s_tx_mst0_ccr") - -// User extension aux register io_i2s_tx_mst0_txffr -#define AR_IO_I2S_TX_MST0_TXFFR 0x80019018 -#pragma Aux_register(0x80019018, name=>"io_i2s_tx_mst0_txffr") - -// User extension aux register io_i2s_tx_mst0_lthr -#define AR_IO_I2S_TX_MST0_LTHR 0x80019020 -#pragma Aux_register(0x80019020, name=>"io_i2s_tx_mst0_lthr") - -// User extension aux register io_i2s_tx_mst0_rthr -#define AR_IO_I2S_TX_MST0_RTHR 0x80019024 -#pragma Aux_register(0x80019024, name=>"io_i2s_tx_mst0_rthr") - -// User extension aux register io_i2s_tx_mst0_ter -#define AR_IO_I2S_TX_MST0_TER 0x8001902c -#pragma Aux_register(0x8001902c, name=>"io_i2s_tx_mst0_ter") - -// User extension aux register io_i2s_tx_mst0_tcr -#define AR_IO_I2S_TX_MST0_TCR 0x80019034 -#pragma Aux_register(0x80019034, name=>"io_i2s_tx_mst0_tcr") - -// User extension aux register io_i2s_tx_mst0_isr -#define AR_IO_I2S_TX_MST0_ISR 0x80019038 -#pragma Aux_register(0x80019038, name=>"io_i2s_tx_mst0_isr") - -// User extension aux register io_i2s_tx_mst0_imr -#define AR_IO_I2S_TX_MST0_IMR 0x8001903c -#pragma Aux_register(0x8001903c, name=>"io_i2s_tx_mst0_imr") - -// User extension aux register io_i2s_tx_mst0_tor -#define AR_IO_I2S_TX_MST0_TOR 0x80019044 -#pragma Aux_register(0x80019044, name=>"io_i2s_tx_mst0_tor") - -// User extension aux register io_i2s_tx_mst0_tfcr -#define AR_IO_I2S_TX_MST0_TFCR 0x8001904c -#pragma Aux_register(0x8001904c, name=>"io_i2s_tx_mst0_tfcr") - -// User extension aux register io_i2s_tx_mst0_tff -#define AR_IO_I2S_TX_MST0_TFF 0x80019054 -#pragma Aux_register(0x80019054, name=>"io_i2s_tx_mst0_tff") - -// User extension aux register io_i2s_tx_mst0_txdma -#define AR_IO_I2S_TX_MST0_TXDMA 0x800191c8 -#pragma Aux_register(0x800191c8, name=>"io_i2s_tx_mst0_txdma") -#define APEX_COM_ARC_HARDWARE_DFSS_IO_PDM_RX0_PRESENT 1 - -// User extension aux register io_pdm_rx0_pdm_en -#define AR_IO_PDM_RX0_PDM_EN 0x8001b000 -#pragma Aux_register(0x8001b000, name=>"io_pdm_rx0_pdm_en") - -// User extension aux register io_pdm_rx0_pdm_ren -#define AR_IO_PDM_RX0_PDM_REN 0x8001b004 -#pragma Aux_register(0x8001b004, name=>"io_pdm_rx0_pdm_ren") - -// User extension aux register io_pdm_rx0_cer -#define AR_IO_PDM_RX0_CER 0x8001b00c -#pragma Aux_register(0x8001b00c, name=>"io_pdm_rx0_cer") - -// User extension aux register io_pdm_rx0_rxffr -#define AR_IO_PDM_RX0_RXFFR 0x8001b014 -#pragma Aux_register(0x8001b014, name=>"io_pdm_rx0_rxffr") - -// User extension aux register io_pdm_rx0_rer0 -#define AR_IO_PDM_RX0_RER0 0x8001b028 -#pragma Aux_register(0x8001b028, name=>"io_pdm_rx0_rer0") - -// User extension aux register io_pdm_rx0_isr -#define AR_IO_PDM_RX0_ISR 0x8001b038 -#pragma Aux_register(0x8001b038, name=>"io_pdm_rx0_isr") - -// User extension aux register io_pdm_rx0_imr -#define AR_IO_PDM_RX0_IMR 0x8001b03c -#pragma Aux_register(0x8001b03c, name=>"io_pdm_rx0_imr") - -// User extension aux register io_pdm_rx0_ror -#define AR_IO_PDM_RX0_ROR 0x8001b040 -#pragma Aux_register(0x8001b040, name=>"io_pdm_rx0_ror") - -// User extension aux register io_pdm_rx0_rfcr -#define AR_IO_PDM_RX0_RFCR 0x8001b048 -#pragma Aux_register(0x8001b048, name=>"io_pdm_rx0_rfcr") - -// User extension aux register io_pdm_rx0_rxdma -#define AR_IO_PDM_RX0_RXDMA 0x8001b1c0 -#pragma Aux_register(0x8001b1c0, name=>"io_pdm_rx0_rxdma") - -// User extension aux register io_pdm_rx0_pdm_rr -#define AR_IO_PDM_RX0_PDM_RR 0x8001b1d0 -#pragma Aux_register(0x8001b1d0, name=>"io_pdm_rx0_pdm_rr") - -// User extension aux register io_pdm_rx0_cic_n -#define AR_IO_PDM_RX0_CIC_N 0x8001b1d4 -#pragma Aux_register(0x8001b1d4, name=>"io_pdm_rx0_cic_n") - -// User extension aux register io_pdm_rx0_cic_d -#define AR_IO_PDM_RX0_CIC_D 0x8001b1d8 -#pragma Aux_register(0x8001b1d8, name=>"io_pdm_rx0_cic_d") - -// User extension aux register io_pdm_rx0_dcrc -#define AR_IO_PDM_RX0_DCRC 0x8001b1dc -#pragma Aux_register(0x8001b1dc, name=>"io_pdm_rx0_dcrc") - -// User extension aux register io_pdm_rx0_brc_b0 -#define AR_IO_PDM_RX0_BRC_B0 0x8001b1e0 -#pragma Aux_register(0x8001b1e0, name=>"io_pdm_rx0_brc_b0") - -// User extension aux register io_pdm_rx0_brc_clp -#define AR_IO_PDM_RX0_BRC_CLP 0x8001b1f0 -#pragma Aux_register(0x8001b1f0, name=>"io_pdm_rx0_brc_clp") -#define APEX_COM_ARC_HARDWARE_FLOATING_POINT_UNIT_FPU_PRESENT 1 - -// User extension aux register fpu_build -#define AR_FPU_BUILD 0xc8 -#pragma Aux_register(0xc8, name=>"fpu_build") - -// User extension aux register fpu_ctrl -#define AR_FPU_CTRL 0x300 -#pragma Aux_register(0x300, name=>"fpu_ctrl") - -// User extension aux register fpu_status -#define AR_FPU_STATUS 0x301 -#pragma Aux_register(0x301, name=>"fpu_status") - -// User extension instruction fsmadd -extern int fsmadd(int,int); -#pragma intrinsic(fsmadd,opcode=>6,sub_opcode=>5, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fsmsub -extern int fsmsub(int,int); -#pragma intrinsic(fsmsub,opcode=>6,sub_opcode=>6, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fsmul -extern int fsmul(int,int); -#pragma intrinsic(fsmul,opcode=>6,sub_opcode=>0, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fsadd -extern int fsadd(int,int); -#pragma intrinsic(fsadd,opcode=>6,sub_opcode=>1, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fssub -extern int fssub(int,int); -#pragma intrinsic(fssub,opcode=>6,sub_opcode=>2, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fcvt32 -extern int fcvt32(int,int); -#pragma intrinsic(fcvt32,opcode=>6,sub_opcode=>8, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fsdiv -extern int fsdiv(int,int); -#pragma intrinsic(fsdiv,opcode=>6,sub_opcode=>7, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fscmp -extern int fscmp(int,int); -#pragma intrinsic(fscmp,opcode=>6,sub_opcode=>3, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fscmp -extern int fscmp_f(int,int); -#pragma intrinsic(fscmp_f,opcode=>6,sub_opcode=>3, set_flags => 1, flags => "zncv", effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fscmpf -extern int fscmpf(int,int); -#pragma intrinsic(fscmpf,opcode=>6,sub_opcode=>4, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fscmpf -extern int fscmpf_f(int,int); -#pragma intrinsic(fscmpf_f,opcode=>6,sub_opcode=>4, set_flags => 1, flags => "zncv", effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") - -// User extension instruction fssqrt -extern int fssqrt(int); -#pragma intrinsic(fssqrt,opcode=>6,sub_opcode=>0, effects=>"auxreg=0xc8:is_read:is_written; auxreg=0x300:is_read:is_written; auxreg=0x301:is_read:is_written") -#define APEX_COM_ARC_HARDWARE_FLOATING_POINT_UNIT_FPU_DP_ASSIST_PRESENT 1 - -// User extension aux register aux_dpfp1l -#define AR_AUX_DPFP1L 0x302 -#pragma Aux_register(0x302, name=>"aux_dpfp1l") - -// User extension aux register aux_dpfp1h -#define AR_AUX_DPFP1H 0x303 -#pragma Aux_register(0x303, name=>"aux_dpfp1h") - -// User extension aux register aux_dpfp2l -#define AR_AUX_DPFP2L 0x304 -#pragma Aux_register(0x304, name=>"aux_dpfp2l") - -// User extension aux register aux_dpfp2h -#define AR_AUX_DPFP2H 0x305 -#pragma Aux_register(0x305, name=>"aux_dpfp2h") - -// User extension instruction dmulh11 -extern int dmulh11(int,int); -#pragma intrinsic(dmulh11,opcode=>6,sub_opcode=>48,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh11 -extern int dmulh11_f(int,int); -#pragma intrinsic(dmulh11_f,opcode=>6,sub_opcode=>48, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh12 -extern int dmulh12(int,int); -#pragma intrinsic(dmulh12,opcode=>6,sub_opcode=>49,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh12 -extern int dmulh12_f(int,int); -#pragma intrinsic(dmulh12_f,opcode=>6,sub_opcode=>49, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh21 -extern int dmulh21(int,int); -#pragma intrinsic(dmulh21,opcode=>6,sub_opcode=>50,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh21 -extern int dmulh21_f(int,int); -#pragma intrinsic(dmulh21_f,opcode=>6,sub_opcode=>50, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh22 -extern int dmulh22(int,int); -#pragma intrinsic(dmulh22,opcode=>6,sub_opcode=>51,blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dmulh22 -extern int dmulh22_f(int,int); -#pragma intrinsic(dmulh22_f,opcode=>6,sub_opcode=>51, set_flags => 1, flags => "zncv",blocking_cycles=> 7, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh11 -extern int daddh11(int,int); -#pragma intrinsic(daddh11,opcode=>6,sub_opcode=>52,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh11 -extern int daddh11_f(int,int); -#pragma intrinsic(daddh11_f,opcode=>6,sub_opcode=>52, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh12 -extern int daddh12(int,int); -#pragma intrinsic(daddh12,opcode=>6,sub_opcode=>53,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh12 -extern int daddh12_f(int,int); -#pragma intrinsic(daddh12_f,opcode=>6,sub_opcode=>53, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh21 -extern int daddh21(int,int); -#pragma intrinsic(daddh21,opcode=>6,sub_opcode=>54,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh21 -extern int daddh21_f(int,int); -#pragma intrinsic(daddh21_f,opcode=>6,sub_opcode=>54, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh22 -extern int daddh22(int,int); -#pragma intrinsic(daddh22,opcode=>6,sub_opcode=>55,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction daddh22 -extern int daddh22_f(int,int); -#pragma intrinsic(daddh22_f,opcode=>6,sub_opcode=>55, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh11 -extern int dsubh11(int,int); -#pragma intrinsic(dsubh11,opcode=>6,sub_opcode=>56,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh11 -extern int dsubh11_f(int,int); -#pragma intrinsic(dsubh11_f,opcode=>6,sub_opcode=>56, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh12 -extern int dsubh12(int,int); -#pragma intrinsic(dsubh12,opcode=>6,sub_opcode=>57,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh12 -extern int dsubh12_f(int,int); -#pragma intrinsic(dsubh12_f,opcode=>6,sub_opcode=>57, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh21 -extern int dsubh21(int,int); -#pragma intrinsic(dsubh21,opcode=>6,sub_opcode=>58,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh21 -extern int dsubh21_f(int,int); -#pragma intrinsic(dsubh21_f,opcode=>6,sub_opcode=>58, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh22 -extern int dsubh22(int,int); -#pragma intrinsic(dsubh22,opcode=>6,sub_opcode=>59,blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dsubh22 -extern int dsubh22_f(int,int); -#pragma intrinsic(dsubh22_f,opcode=>6,sub_opcode=>59, set_flags => 1, flags => "zncv",blocking_cycles=> 5, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dexcl1 -extern int dexcl1(int,int); -#pragma intrinsic(dexcl1,opcode=>6,sub_opcode=>60, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - -// User extension instruction dexcl2 -extern int dexcl2(int,int); -#pragma intrinsic(dexcl2,opcode=>6,sub_opcode=>61, effects=>"auxreg=0x302:is_read:is_written; auxreg=0x303:is_read:is_written; auxreg=0x304:is_read:is_written; auxreg=0x305:is_read:is_written") - - -#endif - - -]]> - - - - - - diff --git a/board/emsdp/rev2/configs/emsdp_hardware.h b/board/emsdp/rev2/configs/emsdp_hardware.h index f1eaa3498..d7175170c 100644 --- a/board/emsdp/rev2/configs/emsdp_hardware.h +++ b/board/emsdp/rev2/configs/emsdp_hardware.h @@ -32,24 +32,27 @@ #include "arc_feature_config.h" #include "apexextensions.h" - +#include "board_emsdp.h" + +#undef DBG_init +#undef DBG_print +#undef DGB_getChar +#undef DBG_finish +#undef DBG_finish_with_error +#undef BDG_install /** * Clock Definitions */ -#define EMSDP_REF_CLOCK (100000000U) - -#define EMSDP_UART_REF_CLOCK (100000000U) -#define EMSDP_AUDIO_REF_CLOCK (24576000U) -#define EMSDP_SPI_REF_CLOCK (20000000U) - -#if (defined(FAST_UART) ) - #define EMSDP_UART_BAUDRATE (6250000U) -#else - #define EMSDP_UART_BAUDRATE (115200) +#ifndef EMSDP_PWM_TIMER_CLOCK +#define EMSDP_PWM_TIMER_CLOCK (EMSDP_REF_CLOCK) +#endif +#ifndef EMSDP_SPI_CLOCK +#define EMSDP_SPI_REF_CLOCK (EMSDP_REF_CLOCK) #endif -#define EMSDP_I2C_CLOCK (EMSDP_REF_CLOCK) -#define EMSDP_PWM_TIMER_CLOCK (EMSDP_REF_CLOCK) +#ifndef EMSDP_I2C_CLOCK +#define EMSDP_I2C_CLOCK (EMSDP_REF_CLOCK) +#endif /** CPU Clock Frequency definition */ #if defined(BOARD_CPU_FREQ) @@ -72,21 +75,6 @@ #define CLK_BUS_APB (100000000U) #endif -//APB Peripheral address map -#define EMSDP_CRU_BASE (0xF0000000U) -#define EMSDP_CREG_BASE (0xF0001000U) -#define EMSDP_GPIO_BASE (0xF0002000U) -#define EMSDP_TRNG_BASE (0xF0003000U) -#define EMSDP_DBG_UART_BASE (0xF0004000U) -#define EMSDP_WDT_BASE (0xF0005000U) -#define EMSDP_TIMERS0_BASE (0xF0006000U) -#define EMSDP_TIMERS1_BASE (0xF0007000U) -#define EMSDP_SPI_BASE (0xF0008000U) -#define EMSDP_UART_BASE (0xF0009000U) -#define EMSDP_SDIO_BASE (0xF0010000U) -#define EMSDP_FLASH_BASE (0xF1000000U) -#define EMSDP_EBI_BASE (0xF2000000U) -#define EMSDP_PSRAM_BASE (0xF2001000U) //CREG Control Register Map #define EMSDP_CREG_BOOT_OFFSET (0x0000) @@ -98,6 +86,4 @@ #define EMSDP_CREG_IP_VERSION_OFFSET (0x1FF8) #define EMSDP_CREG_IP_TYPE_OFFSET (0x1FFC) -#include "core_hardware.h" - #endif //__EMSDP_HARDWARE_H__ From ea7d11d32a4138603769a5daa5496a5cc2b3380e Mon Sep 17 00:00:00 2001 From: Wayne Ren Date: Thu, 10 Jan 2019 14:17:01 +0800 Subject: [PATCH 14/28] doc: update emsdp doc update emsdp doc Signed-off-by: Wayne Ren --- doc/documents/board/emsdp.rst | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/doc/documents/board/emsdp.rst b/doc/documents/board/emsdp.rst index 4d5285583..2ca9693af 100644 --- a/doc/documents/board/emsdp.rst +++ b/doc/documents/board/emsdp.rst @@ -56,7 +56,7 @@ The |emsdp| contains the following components: - Audio line in/out - USB Data port (JTAG/UART/access to configuration memory) - Micro-SD Card - - WIFI/BT/Zigbee module + - Wi-Fi/BT/Zigbee module - ADC (eight channels) - Motion Sensor - Digital MEMs microphone (2x) @@ -121,17 +121,22 @@ Package Preparation This section talks about how to add new |emsdp| cores into embARC OSP. If you are using default cores of |emsdp|: *em6_scss*, *em7d_esp_dfss*, and *em11d_dfss*, then you may skip this section. -#. You may download the package from our website. Suppose you want to add a new package called ``em9d_dfss``, your package name would be ``embarc_em9d_dfss.zip``. +#. You may download the package from our website. Suppose you want to add a new package called ``em9d_dfss``, your package name would be ``emsdp_em9d_dfss.zip``. #. Download the package and unzip it, you will find four folders: ``/doc``, ``/fpga``, ``/include``, ``/tool_config``. Now create a new folder according to your board revision and package name. In this case *em9d_dfss* is added to *rev2* board, so you should set your directory as this:``/board/emsdp/rev2/configs/em9d_dfss`` -#. Copy ``/tool_config`` folder to ``/board/emsdp/rev2/configs/em9d_dfss/tool_config``. +#. Copy the content of unzipped folder to ``/board/emsdp/rev2/configs/em9d_dfss``. It would be like: -#. Copy all ``/include`` files except ``core_config.h`` to ``/board/emsdp/rev2/configs/em9d_dfss`` +.. code-block:: console + + em9d_dfss + ├─doc + ├─fpga + ├─include + └─tool_config -#. Rename ``board_emsdp.h`` to ``core_hardware.h``, open the file and delete its contents from line 25 to line 100. -#. You are done importing a new package, build with it to make sure everything is working. +#. You are done importing a new package, flash the bit file into board and build with it to make sure everything is working. Run Your First Program ^^^^^^^^^^^^^^^^^^^^^^ @@ -141,16 +146,16 @@ please refer to example `example_blinky` for further details. Build and download .. code-block:: console $ cd /example/baremetal/blinky - $ gmake BOARD=emsdp BD_VER=rev1 CORE=em11d_dfss TOOLCHAIN=mw run + $ gmake BOARD=emsdp BD_VER=rev2 CORE=em11d_dfss TOOLCHAIN=mw run -.. note:: Notice that for CORE option there are multiple core choices, please check `/board/emsdp/rev1` folder for available cores. +.. note:: Notice that for CORE option there are multiple core choices, please check `/board/emsdp/rev2` folder for available cores. Development Guide ^^^^^^^^^^^^^^^^^ Please refer to `Developer Guides`. You may need to specify peripheral driver (`/device/peripheral`) for your own code. -For example, if wifi rs9113 driver is needed, add this line in makefile: +For example, if Wi-Fi rs9113 driver is needed, add this line in makefile: .. code-block:: console From 1fe6217f0d55e434c570370a48c57462f08d3939 Mon Sep 17 00:00:00 2001 From: Wayne Ren Date: Thu, 10 Jan 2019 14:17:47 +0800 Subject: [PATCH 15/28] arc: timer: optimize the definition of timer interrupt no. optimize the definition of timer interrupt no Signed-off-by: Wayne Ren --- inc/arc/arc_timer.h | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/inc/arc/arc_timer.h b/inc/arc/arc_timer.h index e20d0a998..5865ea11b 100644 --- a/inc/arc/arc_timer.h +++ b/inc/arc/arc_timer.h @@ -56,12 +56,26 @@ #define SECURE_TIMER_1 1 /*!< macro name for arc internal secure timer 1 */ /** @} */ - +#ifdef ARC_FEATURE_TIMER0_VECTOR #define INTNO_TIMER0 ARC_FEATURE_TIMER0_VECTOR /*!< ARC Timer0 */ +#else +#define INTNO_TIMER0 16 +#endif +#ifdef ARC_FEATURE_TIMER1_VECTOR #define INTNO_TIMER1 ARC_FEATURE_TIMER1_VECTOR /*!< ARC Timer1 */ +#else +#define INTNO_TIMER1 17 +#endif +#ifdef ARC_FEATURE_SEC_TIMER0_VECTOR #define INTNO_SECURE_TIMER0 ARC_FEATURE_SEC_TIMER0_VECTOR /*!< Core Secure Timer 0 */ +#else +#define INTNO_SECURE_TIMER0 20 +#endif +#ifdef ARC_FEATURE_TIMER1_VECTOR #define INTNO_SECURE_TIMER1 ARC_FEATURE_SEC_TIMER1_VECTOR /*!< Core Secure Timer 1 */ - +#else +#define INTNO_SECURE_TIMER1 21 +#endif /** * \name bit definition of RTC CTRL reg * @{ From 7c561166fbde11896d69c11c572e3b219f760cb8 Mon Sep 17 00:00:00 2001 From: Jingru Wang Date: Thu, 10 Jan 2019 14:24:35 +0800 Subject: [PATCH 16/28] doc: modify some spelling, punctuation errors, etc. Signed-off-by: Jingru Wang --- doc/documents/board/emsdp.rst | 2 +- .../developer/application_development.rst | 16 ++++++++-------- .../developer/build_system_documentation.rst | 6 +++--- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/doc/documents/board/emsdp.rst b/doc/documents/board/emsdp.rst index 4d5285583..6f15178a5 100644 --- a/doc/documents/board/emsdp.rst +++ b/doc/documents/board/emsdp.rst @@ -79,7 +79,7 @@ Drag-and-drop feature enable users to copy an FPGA bitstream from the PC to the Memory ^^^^^^ -Please refer to `ARC_EM_SDP_UserGuide` for memory map and more details. +Please refer to `ARC_EM_SDP_User Guide` for memory map and more details. Interfaces ^^^^^^^^^^ diff --git a/doc/documents/developer/application_development.rst b/doc/documents/developer/application_development.rst index af62406eb..86c78167f 100644 --- a/doc/documents/developer/application_development.rst +++ b/doc/documents/developer/application_development.rst @@ -75,8 +75,8 @@ Here, we will show how to create a new application in embARC OSP, taking a simp option can also be given in cmd line If not specified, the default value will be ``22`` for board ``emsk``. - * Change the core configuration: change the value of **CUR_CORE** to - **arcem7d** This option can also be given in cmd line If not specified, + * Change the core configuration: change the value of ``CUR_CORE`` to + ``arcem7d``. This option can also be given in cmd line. If not specified, the default value will ``arcem7d`` for board ``emsk`` and version ``22``. * Change the embARC OSP root: change the value of ``EMBARC_ROOT`` to @@ -111,9 +111,9 @@ Here, we will show how to create a new application in embARC OSP, taking a simp * Set your application defined macros: Change the value of ``APPL_DEFINES``. - * For example, if define ``APPLICATION=1``, set APPL_DEFINES to ``-DAPPLICATION=1``. + * For example, if define ``APPLICATION=1``, set ``APPL_DEFINES`` to ``-DAPPLICATION=1``. - Then ``hello world`` application's makefile will be like this + Then ``hello_world`` application's makefile will be like this .. code-block:: makefile @@ -215,7 +215,7 @@ Here, we will show how to create a new application in embARC OSP, taking a simp * Enter ``make run`` in the command line to run this application. - * Enter ``make gui`` in the command line to debug this application. Press **CTRL + C** to stop the program. Enter ``q`` to exit the debugger. See the GDB manual for how to debug an application using arc-elf32-gdb. + * Enter ``make gui`` in the command line to debug this application. Press **CTRL + C** to stop the program. Enter ``q`` to exit the debugger. See the `GDB manual `_ for how to debug an application using arc-elf32-gdb. .. note:: @@ -264,11 +264,11 @@ A embARC "helloworld" application has been created and tested. This section prov Debug Multiple Boards ##################### -Multiple EMSK boards are required to run or debug application code on a single PC for some examples in embARC, especially the Pmod RF examples. Here are alternative ways for two EMSK boards running and debugging with using one PC. +Multiple EMSK boards are required to run or debug application code on a single PC for some examples in embARC, especially the Pmod RF examples. Here are alternative ways for two EMSK boards running and debugging with one PC. * MetaWare Toolchain - * In command-line mode, Ashling JTAG and USB-JTAG are necessary rather than multi-USB JTAGs. One node runs ``make TOOLCHAIN=mw xxxx JTAG=opella xx``. the other node runs ``make TOOLCHAIN=mw xxxx JTAG=usb xx``. + * In command-line mode, Ashling JTAG and USB-JTAG are necessary rather than multi-USB JTAGs. One node runs ``make TOOLCHAIN=mw xxxx JTAG=opella xx``, the other node runs ``make TOOLCHAIN=mw xxxx JTAG=usb xx``. * In IDE mode, change the debugger configuration in one of the two nodes for Ashling JTAG. Because the Digilent JTAG Cable is the default option. * Another way for command-line mode is to modify the DIG_NAME option to choose different boards. DIG_NAME is a MetaWare debugger property corresponding to ``-prop=dig_device=name``. @@ -277,4 +277,4 @@ Multiple EMSK boards are required to run or debug application code on a single P * In command-line mode, all nodes run ``make TOOLCHAIN=gnu xxx JTAG=usb xx``. OpenOCD selects the right board automatically. OpenOCD supports multi-USB-JTAG. * In IDE mode, all projects share the same port for the OpenOCD configuration. The same GNU debugger port (49105) is used. To avoid a conflict with GNU debugger ports, set the different GNU debugger ports in the debug configuration. -.. note:: The following methods only support two boards, e.g., one EMSK 1.x and one EMSK 2.x. Two EMSK 1.x boards or two EMSK 2.x boards are not supported. +.. note:: The above methods only support two boards, e.g., one EMSK 1.x and one EMSK 2.x. Two EMSK 1.x boards or two EMSK 2.x boards are not supported. diff --git a/doc/documents/developer/build_system_documentation.rst b/doc/documents/developer/build_system_documentation.rst index caaa78cd5..1793be73f 100644 --- a/doc/documents/developer/build_system_documentation.rst +++ b/doc/documents/developer/build_system_documentation.rst @@ -21,7 +21,7 @@ The **options** directory under the embARC root folder contains the common makef * :file:`options.mk`: entry makefile with common definitions, path definitions, other makefiles, and so on. * :file:`rule.mk`: make targets and rules. * :file:`scripts.mk`: common makefile functions -* :file:`toolchain.mk`: General toolchain definitions, including **toolchain_gnu.mk** for the ARC GNU toolchain and **toolchain_mw.mk** for the MetaWare toolchain. +* :file:`toolchain.mk`: general toolchain definitions, including **toolchain_gnu.mk** for the ARC GNU toolchain and **toolchain_mw.mk** for the MetaWare toolchain. * :file:`toolchain_gnu.mk` & :file:`toolchain_mw.mk`: toolchain specific compile and link options Make Targets @@ -103,7 +103,7 @@ Most options are located in */options/options.mk*. If you change an opti | hsdk | board/hsdk/hsdk.mk | +------------------------+----------------------------------+ -.. note:: The BD_VER must match the target EMSK version. For example, programs built for 1.1 cannot run on an EMSK 2.x board. +.. note:: The BD_VER must match the target BOARD version. For example, programs built for 1.1 cannot run on an EMSK 2.x board. * **CUR_CORE**: Select the core configuration for the specified board version. For example, ``make BOARD=emsk BD_VER=23 CUR_CORE=arcem11d`` selects the arcem11d core configuration for emsk 2.3. @@ -170,7 +170,7 @@ Most options are located in */options/options.mk*. If you change an opti archs ARC HS core ====================== ======================================== - * For nSIM 10, the default value of this option is **archs38_c0** defined in */board/hsdk/configs/10/core_config.mk*. + * For HSDK, the default value of this option is **archs38_c0** defined in */board/hsdk/configs/10/core_config.mk*. .. table:: Make option - CUR_CORE for HSDK :widths: auto From fa2d2f811a0b96ea47d5560fba17370b626bcfe1 Mon Sep 17 00:00:00 2001 From: Watson Zeng Date: Thu, 10 Jan 2019 16:54:50 +0800 Subject: [PATCH 17/28] example: freertos: optimize the memory footprint for different boaeds Signed-off-by: Watson Zeng --- board/board.c | 2 +- board/iotdk/iotdk.h | 2 - .../freertos/esp8266_wifi/FreeRTOSConfig.h | 2 +- example/freertos/esp8266_wifi/esp8266.c | 32 +++++------ .../iot/coap/coap_server/FreeRTOSConfig.h | 2 +- .../freertos/iot/coap/coap_server/lwipopts.h | 2 +- .../freertos/iot/coap/coap_server/makefile | 8 ++- .../iot/lwm2m/lwm2m_client/FreeRTOSConfig.h | 2 +- .../iot/lwm2m/lwm2m_client/lwipopts.h | 2 +- .../iot/lwm2m/lwm2m_client/lwm2mclient.c | 56 ++++++++++--------- .../freertos/iot/lwm2m/lwm2m_client/makefile | 4 ++ .../iot/lwm2m/lwm2m_server/FreeRTOSConfig.h | 2 +- .../iot/lwm2m/lwm2m_server/lwipopts.h | 2 +- .../freertos/iot/lwm2m/lwm2m_server/makefile | 4 ++ example/freertos/kernel/FreeRTOSConfig.h | 2 +- .../freertos/kernel_secure/FreeRTOSConfig.h | 2 +- .../freertos/net/httpserver/FreeRTOSConfig.h | 2 +- example/freertos/net/httpserver/lwipopts.h | 2 +- example/freertos/net/httpserver/makefile | 5 +- example/freertos/net/ntshell/FreeRTOSConfig.h | 2 +- example/freertos/net/ntshell/lwipopts.h | 2 +- example/freertos/net/ntshell/makefile | 9 ++- .../sec/mbedtls/dtls/client/lwipopts.h | 2 +- .../sec/mbedtls/dtls/server/lwipopts.h | 2 +- .../sec/mbedtls/ssl/client2/lwipopts.h | 2 +- .../sec/mbedtls/ssl/server2/lwipopts.h | 2 +- 26 files changed, 88 insertions(+), 68 deletions(-) diff --git a/board/board.c b/board/board.c index ec4b2c3ce..d6ea3ea63 100644 --- a/board/board.c +++ b/board/board.c @@ -88,7 +88,7 @@ static TaskHandle_t task_handle_ntshell; #else /* No middleware ntshell,will activate main task */ #ifndef TASK_STACK_SIZE_MAIN -#define TASK_STACK_SIZE_MAIN MIN_STACKSZ(1024) +#define TASK_STACK_SIZE_MAIN MIN_STACKSZ(4096) #endif #ifndef TASK_PRI_MAIN diff --git a/board/iotdk/iotdk.h b/board/iotdk/iotdk.h index 2d156bf02..0c1703e77 100644 --- a/board/iotdk/iotdk.h +++ b/board/iotdk/iotdk.h @@ -153,8 +153,6 @@ #define BOARD_WIFI_0_INT 4 #define BOARD_WIFI_0_RST 5 -#define TASK_STACK_SIZE_MAIN 1024 - // Un-implemented LED/Switch/Button functions and macros #define BOARD_LED_MASK (0x0) #define BOARD_LED_CNT (0) diff --git a/example/freertos/esp8266_wifi/FreeRTOSConfig.h b/example/freertos/esp8266_wifi/FreeRTOSConfig.h index a3252ca79..ec6317774 100644 --- a/example/freertos/esp8266_wifi/FreeRTOSConfig.h +++ b/example/freertos/esp8266_wifi/FreeRTOSConfig.h @@ -86,7 +86,7 @@ #define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) #define configMAX_PRIORITIES ( 10 ) #define configMINIMAL_STACK_SIZE ( ( unsigned short ) 104 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 16 * 1024 ) ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32 * 1024 ) ) #define configMAX_TASK_NAME_LEN ( 10 ) #define configUSE_TRACE_FACILITY 0 #define configUSE_16_BIT_TICKS 0 diff --git a/example/freertos/esp8266_wifi/esp8266.c b/example/freertos/esp8266_wifi/esp8266.c index 799fc0ef9..ed258b305 100644 --- a/example/freertos/esp8266_wifi/esp8266.c +++ b/example/freertos/esp8266_wifi/esp8266.c @@ -75,7 +75,7 @@ int32_t esp8266_test(ESP8266_DEF_PTR obj) int32_t esp8266_wifi_mode_get(ESP8266_DEF_PTR obj, bool flash) { - char rcv_buf[64]; + char rcv_buf[512]; AT_PARSER_DEF_PTR p_at = obj->p_at; char *pos; uint32_t ret = 0; @@ -95,7 +95,7 @@ int32_t esp8266_wifi_mode_get(ESP8266_DEF_PTR obj, bool flash) int32_t esp8266_wifi_mode_set(ESP8266_DEF_PTR obj, ESP8266_WIFI_MODE mode, bool flash) { - char rcv_buf[64]; + char rcv_buf[512]; char mode_str[4]= {0}; sprintf(mode_str, "%d", mode); at_send_cmd(obj->p_at, AT_WRITE, flash?"CWMODE_DEF":"CWMODE_CUR", mode_str, NULL); @@ -105,7 +105,7 @@ int32_t esp8266_wifi_mode_set(ESP8266_DEF_PTR obj, ESP8266_WIFI_MODE mode, bool /* rcv_buf should be large enough for scan result */ int32_t esp8266_wifi_scan(ESP8266_DEF_PTR obj, char *rcv_buf, char *ssid) { - char cmd_str[64]= {0}; + char cmd_str[512]= {0}; sprintf(cmd_str, "CWLAP=%s", ssid); at_send_cmd(obj->p_at, AT_EXECUTE, cmd_str); return at_get_reply(obj->p_at, rcv_buf, AT_LONG_TIMEOUT); @@ -127,7 +127,7 @@ int32_t esp8266_wifi_scan(ESP8266_DEF_PTR obj, char *rcv_buf, char *ssid) */ int32_t esp8266_wifi_connect(ESP8266_DEF_PTR obj, AT_STRING ssid, AT_STRING pwd, bool flash) { - char rcv_buf[256]; + char rcv_buf[512]; AT_PARSER_DEF_PTR p_at = obj->p_at; char *pos; uint32_t ret = 0; @@ -155,7 +155,7 @@ int32_t esp8266_wifi_connect(ESP8266_DEF_PTR obj, AT_STRING ssid, AT_STRING pwd, int32_t esp8266_wifi_disconnect(ESP8266_DEF_PTR obj) { - char rcv_buf[64]; + char rcv_buf[512]; AT_PARSER_DEF_PTR p_at = obj->p_at; at_send_cmd(p_at, AT_EXECUTE, "CWQAP"); @@ -169,7 +169,7 @@ int32_t esp8266_wifi_disconnect(ESP8266_DEF_PTR obj) int32_t esp8266_address_get(ESP8266_DEF_PTR obj) { - char rcv_buf[128]; + char rcv_buf[512]; AT_PARSER_DEF_PTR p_at = obj->p_at; at_send_cmd(p_at, AT_EXECUTE, "CIFSR"); return at_get_reply(p_at, rcv_buf, AT_NORMAL_TIMEOUT); @@ -185,7 +185,7 @@ int32_t esp8266_address_get(ESP8266_DEF_PTR obj) */ int32_t esp8266_conn_status(ESP8266_DEF_PTR obj) { - char rcv_buf[256]; + char rcv_buf[512]; AT_PARSER_DEF_PTR p_at = obj->p_at; char *pos; uint32_t ret = 0; @@ -205,7 +205,7 @@ int32_t esp8266_conn_status(ESP8266_DEF_PTR obj) int32_t esp8266_dns_lookup(ESP8266_DEF_PTR obj, char *domain_ip, AT_STRING domain_name) { - char rcv_buf[64]; + char rcv_buf[512]; AT_PARSER_DEF_PTR p_at = obj->p_at; char *pos; int len=0; @@ -231,7 +231,7 @@ int32_t esp8266_dns_lookup(ESP8266_DEF_PTR obj, char *domain_ip, AT_STRING domai int32_t esp8266_tcp_connect(ESP8266_DEF_PTR obj, AT_STRING server_IP, uint32_t port) { - char rcv_buf[64]; + char rcv_buf[512]; char IP_Str[32], port_Str[16]; sprintf(IP_Str, "\"%s\"", server_IP); sprintf(port_Str, "%d", port); @@ -241,7 +241,7 @@ int32_t esp8266_tcp_connect(ESP8266_DEF_PTR obj, AT_STRING server_IP, uint32_t p static int32_t esp8266_tcp_server(ESP8266_DEF_PTR obj, uint32_t mode, uint32_t port) { - char rcv_buf[64]; + char rcv_buf[512]; char mode_buf[5]; char port_buf[10]; @@ -255,7 +255,7 @@ static int32_t esp8266_tcp_server(ESP8266_DEF_PTR obj, uint32_t mode, uint32_t p int32_t esp8266_tcp_server_open(ESP8266_DEF_PTR obj, uint32_t port) { - char rcv_buf[64]; + char rcv_buf[512]; AT_PARSER_DEF_PTR p_at = obj->p_at; at_send_cmd(p_at, AT_WRITE, "CIPMUX", "1", NULL); @@ -271,7 +271,7 @@ int32_t esp8266_tcp_server_close(ESP8266_DEF_PTR obj, uint32_t port) int32_t esp8266_transmission_mode(ESP8266_DEF_PTR obj, ESP8266_TRANS_MODE mode) { - char rcv_buf[64]; + char rcv_buf[512]; uint32_t ret; char mode_str[4]= {0}; sprintf(mode_str, "%d", mode); @@ -288,7 +288,7 @@ int32_t esp8266_transmission_mode(ESP8266_DEF_PTR obj, ESP8266_TRANS_MODE mode) int32_t esp8266_passthr_start(ESP8266_DEF_PTR obj) { - char rcv_buf[64]; + char rcv_buf[512]; if (obj->wifi_connected) { if (esp8266_transmission_mode(obj, ESP8266_PASSTHR)==AT_OK) { @@ -327,7 +327,7 @@ int32_t esp8266_passthr_write(ESP8266_DEF_PTR obj, char *buf, uint32_t cnt) uint32_t esp8266_normal_write(ESP8266_DEF_PTR obj, char *buf, uint32_t cnt) { - char rcv_buf[64]; + char rcv_buf[512]; char cnt_str[16]= {0}; if (obj->wifi_connected) { @@ -353,7 +353,7 @@ uint32_t esp8266_normal_write(ESP8266_DEF_PTR obj, char *buf, uint32_t cnt) uint32_t esp8266_connect_write(ESP8266_DEF_PTR obj, char *buf, char *connect, uint32_t cnt) { - char rcv_buf[64]; + char rcv_buf[512]; char cnt_str[16]= {0}; if (obj->wifi_connected) { @@ -412,7 +412,7 @@ uint32_t esp8266_nread(ESP8266_DEF_PTR obj, char *buf, uint32_t n) //at_httpserver int32_t esp8266_CIPCLOSE(ESP8266_DEF_PTR obj, char *conn_buf) { - char rcv_buf[64]; + char rcv_buf[512]; at_send_cmd(obj->p_at, AT_WRITE, "CIPCLOSE", conn_buf, NULL); return at_get_reply(obj->p_at, rcv_buf, AT_EXTRA_TIMEOUT); } \ No newline at end of file diff --git a/example/freertos/iot/coap/coap_server/FreeRTOSConfig.h b/example/freertos/iot/coap/coap_server/FreeRTOSConfig.h index e91c7a312..fe8b126c4 100644 --- a/example/freertos/iot/coap/coap_server/FreeRTOSConfig.h +++ b/example/freertos/iot/coap/coap_server/FreeRTOSConfig.h @@ -86,7 +86,7 @@ #define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) #define configMAX_PRIORITIES ( 10 ) #define configMINIMAL_STACK_SIZE ( ( unsigned short ) 104 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 16 * 1024 ) ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32 * 1024 ) ) #define configMAX_TASK_NAME_LEN ( 10 ) #define configUSE_TRACE_FACILITY 0 #define configUSE_16_BIT_TICKS 0 diff --git a/example/freertos/iot/coap/coap_server/lwipopts.h b/example/freertos/iot/coap/coap_server/lwipopts.h index 4107b8360..d34d19689 100644 --- a/example/freertos/iot/coap/coap_server/lwipopts.h +++ b/example/freertos/iot/coap/coap_server/lwipopts.h @@ -162,7 +162,7 @@ /** * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */ -#define PBUF_POOL_SIZE 120 +#define PBUF_POOL_SIZE 60 /* --------------------------------- diff --git a/example/freertos/iot/coap/coap_server/makefile b/example/freertos/iot/coap/coap_server/makefile index 281c41d10..b1ed7b3e1 100644 --- a/example/freertos/iot/coap/coap_server/makefile +++ b/example/freertos/iot/coap/coap_server/makefile @@ -1,10 +1,14 @@ # Application name APPL ?= freertos_iot_coap_server -EXT_DEV_LIST += wifi/mrf24g - BOARD ?= emsk +ifeq ($(BOARD), emsdp) +EXT_DEV_LIST += wifi/rs9113 +else +EXT_DEV_LIST += wifi/mrf24g +endif + ifeq ($(BOARD), emsk) EXT_DEV_LIST += sensor/temperature/adt7420 endif diff --git a/example/freertos/iot/lwm2m/lwm2m_client/FreeRTOSConfig.h b/example/freertos/iot/lwm2m/lwm2m_client/FreeRTOSConfig.h index e91c7a312..9a10112ac 100644 --- a/example/freertos/iot/lwm2m/lwm2m_client/FreeRTOSConfig.h +++ b/example/freertos/iot/lwm2m/lwm2m_client/FreeRTOSConfig.h @@ -86,7 +86,7 @@ #define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) #define configMAX_PRIORITIES ( 10 ) #define configMINIMAL_STACK_SIZE ( ( unsigned short ) 104 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 16 * 1024 ) ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 48 * 1024 ) ) #define configMAX_TASK_NAME_LEN ( 10 ) #define configUSE_TRACE_FACILITY 0 #define configUSE_16_BIT_TICKS 0 diff --git a/example/freertos/iot/lwm2m/lwm2m_client/lwipopts.h b/example/freertos/iot/lwm2m/lwm2m_client/lwipopts.h index 408a75a32..732ed6842 100644 --- a/example/freertos/iot/lwm2m/lwm2m_client/lwipopts.h +++ b/example/freertos/iot/lwm2m/lwm2m_client/lwipopts.h @@ -162,7 +162,7 @@ /** * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */ -#define PBUF_POOL_SIZE 120 +#define PBUF_POOL_SIZE 60 /* --------------------------------- diff --git a/example/freertos/iot/lwm2m/lwm2m_client/lwm2mclient.c b/example/freertos/iot/lwm2m/lwm2m_client/lwm2mclient.c index 30b4925a2..f88d827c0 100644 --- a/example/freertos/iot/lwm2m/lwm2m_client/lwm2mclient.c +++ b/example/freertos/iot/lwm2m/lwm2m_client/lwm2mclient.c @@ -81,7 +81,11 @@ int g_reboot = 0; static int g_quit = 0; +#if defined(BOARD_EMSK) #define OBJ_COUNT 9 +#else +#define OBJ_COUNT 8 +#endif lwm2m_object_t * objArray[OBJ_COUNT]; // only backup security and server objects @@ -711,25 +715,16 @@ int lwm2mclient(lwm2m_client_info *client_info) return -1; } -#if defined(BOARD_EMSK) - objArray[1] = get_object_firmware(); + objArray[1] = get_test_object(); if (NULL == objArray[1]) - { - EMBARC_PRINTF("Failed to create Firmware object\r\n"); - return -1; - } -#endif - - objArray[2] = get_test_object(); - if (NULL == objArray[2]) { EMBARC_PRINTF("Failed to create test object\r\n"); return -1; } int serverId = 123; - objArray[3] = get_server_object(serverId, "U", lifetime, false); - if (NULL == objArray[3]) + objArray[2] = get_server_object(serverId, "U", lifetime, false); + if (NULL == objArray[2]) { EMBARC_PRINTF("Failed to create server object\r\n"); return -1; @@ -737,57 +732,66 @@ int lwm2mclient(lwm2m_client_info *client_info) char serverUri[50]; sprintf(serverUri, "coap://%s:%s", server, serverPort); - objArray[4] = get_security_object(serverId, serverUri, false); - if (NULL == objArray[4]) + objArray[3] = get_security_object(serverId, serverUri, false); + if (NULL == objArray[3]) { EMBARC_PRINTF("Failed to create security object\r\n"); return -1; } - data.securityObjP = objArray[4]; + data.securityObjP = objArray[3]; - objArray[5] = get_object_location(); - if (NULL == objArray[5]) + objArray[4] = get_object_location(); + if (NULL == objArray[4]) { EMBARC_PRINTF("Failed to create location object\r\n"); return -1; } - objArray[6] = get_object_conn_m(); - if (NULL == objArray[6]) + objArray[5] = get_object_conn_m(); + if (NULL == objArray[5]) { EMBARC_PRINTF("Failed to create connectivity monitoring object\r\n"); return -1; } - objArray[7] = get_object_conn_s(); - if (NULL == objArray[7]) + objArray[6] = get_object_conn_s(); + if (NULL == objArray[6]) { EMBARC_PRINTF("Failed to create connectivity statistics object\r\n"); return -1; } int instId = 0; - objArray[8] = acc_ctrl_create_object(); - if (NULL == objArray[8]) + objArray[7] = acc_ctrl_create_object(); + if (NULL == objArray[7]) { EMBARC_PRINTF("Failed to create Access Control object\r\n"); return -1; } - else if (acc_ctrl_obj_add_inst(objArray[8], instId, 3, 0, serverId)==false) + else if (acc_ctrl_obj_add_inst(objArray[7], instId, 3, 0, serverId)==false) { EMBARC_PRINTF("Failed to create Access Control object instance\r\n"); return -1; } - else if (acc_ctrl_oi_add_ac_val(objArray[8], instId, 0, 0b000000000001111)==false) + else if (acc_ctrl_oi_add_ac_val(objArray[7], instId, 0, 0b000000000001111)==false) { EMBARC_PRINTF("Failed to create Access Control ACL default resource\r\n"); return -1; } - else if (acc_ctrl_oi_add_ac_val(objArray[8], instId, 999, 0b000000000000001)==false) + else if (acc_ctrl_oi_add_ac_val(objArray[7], instId, 999, 0b000000000000001)==false) { EMBARC_PRINTF("Failed to create Access Control ACL resource for serverId: 999\r\n"); return -1; } + +#if defined(BOARD_EMSK) + objArray[8] = get_object_firmware(); + if (NULL == objArray[8]) + { + EMBARC_PRINTF("Failed to create Firmware object\r\n"); + return -1; + } +#endif /* * The liblwm2m library is now initialized with the functions that will be in * charge of communication diff --git a/example/freertos/iot/lwm2m/lwm2m_client/makefile b/example/freertos/iot/lwm2m/lwm2m_client/makefile index 7b59dce73..fc4affff5 100644 --- a/example/freertos/iot/lwm2m/lwm2m_client/makefile +++ b/example/freertos/iot/lwm2m/lwm2m_client/makefile @@ -3,7 +3,11 @@ APPL ?= freertos_iot_lwm2m_client BOARD ?= emsk +ifeq ($(BOARD), emsdp) +EXT_DEV_LIST += wifi/rs9113 +else EXT_DEV_LIST += wifi/mrf24g +endif ## # HEAP & STACK SETTINGS diff --git a/example/freertos/iot/lwm2m/lwm2m_server/FreeRTOSConfig.h b/example/freertos/iot/lwm2m/lwm2m_server/FreeRTOSConfig.h index e91c7a312..9a10112ac 100644 --- a/example/freertos/iot/lwm2m/lwm2m_server/FreeRTOSConfig.h +++ b/example/freertos/iot/lwm2m/lwm2m_server/FreeRTOSConfig.h @@ -86,7 +86,7 @@ #define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) #define configMAX_PRIORITIES ( 10 ) #define configMINIMAL_STACK_SIZE ( ( unsigned short ) 104 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 16 * 1024 ) ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 48 * 1024 ) ) #define configMAX_TASK_NAME_LEN ( 10 ) #define configUSE_TRACE_FACILITY 0 #define configUSE_16_BIT_TICKS 0 diff --git a/example/freertos/iot/lwm2m/lwm2m_server/lwipopts.h b/example/freertos/iot/lwm2m/lwm2m_server/lwipopts.h index 408a75a32..732ed6842 100644 --- a/example/freertos/iot/lwm2m/lwm2m_server/lwipopts.h +++ b/example/freertos/iot/lwm2m/lwm2m_server/lwipopts.h @@ -162,7 +162,7 @@ /** * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */ -#define PBUF_POOL_SIZE 120 +#define PBUF_POOL_SIZE 60 /* --------------------------------- diff --git a/example/freertos/iot/lwm2m/lwm2m_server/makefile b/example/freertos/iot/lwm2m/lwm2m_server/makefile index 05cb4ef7c..0e6aa7701 100644 --- a/example/freertos/iot/lwm2m/lwm2m_server/makefile +++ b/example/freertos/iot/lwm2m/lwm2m_server/makefile @@ -1,7 +1,11 @@ # Application name APPL ?= freertos_iot_lwm2m_server +ifeq ($(BOARD), emsdp) +EXT_DEV_LIST += wifi/rs9113 +else EXT_DEV_LIST += wifi/mrf24g +endif ## # HEAP & STACK SETTINGS diff --git a/example/freertos/kernel/FreeRTOSConfig.h b/example/freertos/kernel/FreeRTOSConfig.h index 77c7b88bb..67ec34531 100644 --- a/example/freertos/kernel/FreeRTOSConfig.h +++ b/example/freertos/kernel/FreeRTOSConfig.h @@ -86,7 +86,7 @@ #define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) #define configMAX_PRIORITIES ( 4 ) #define configMINIMAL_STACK_SIZE ( ( unsigned short ) 104 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 18 * 1024 ) ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32 * 1024 ) ) #define configMAX_TASK_NAME_LEN ( 10 ) #define configUSE_TRACE_FACILITY 0 #define configUSE_16_BIT_TICKS 0 diff --git a/example/freertos/kernel_secure/FreeRTOSConfig.h b/example/freertos/kernel_secure/FreeRTOSConfig.h index 1a5b9a5bd..56f5f2973 100644 --- a/example/freertos/kernel_secure/FreeRTOSConfig.h +++ b/example/freertos/kernel_secure/FreeRTOSConfig.h @@ -86,7 +86,7 @@ #define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) #define configMAX_PRIORITIES ( 4 ) #define configMINIMAL_STACK_SIZE ( ( unsigned short ) 104 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 18 * 1024 ) ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32 * 1024 ) ) #define configMAX_TASK_NAME_LEN ( 10 ) #define configUSE_TRACE_FACILITY 0 #define configUSE_16_BIT_TICKS 0 diff --git a/example/freertos/net/httpserver/FreeRTOSConfig.h b/example/freertos/net/httpserver/FreeRTOSConfig.h index 31f056880..2f0bc4092 100644 --- a/example/freertos/net/httpserver/FreeRTOSConfig.h +++ b/example/freertos/net/httpserver/FreeRTOSConfig.h @@ -86,7 +86,7 @@ #define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) #define configMAX_PRIORITIES ( 10 ) #define configMINIMAL_STACK_SIZE ( ( unsigned short ) 104 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 16 * 1024 ) ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32 * 1024 ) ) #define configMAX_TASK_NAME_LEN ( 10 ) #define configUSE_TRACE_FACILITY 0 #define configUSE_16_BIT_TICKS 0 diff --git a/example/freertos/net/httpserver/lwipopts.h b/example/freertos/net/httpserver/lwipopts.h index 2bd27a24b..2b8e77bf9 100644 --- a/example/freertos/net/httpserver/lwipopts.h +++ b/example/freertos/net/httpserver/lwipopts.h @@ -158,7 +158,7 @@ /** * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */ -#define PBUF_POOL_SIZE 120 +#define PBUF_POOL_SIZE 60 /* --------------------------------- diff --git a/example/freertos/net/httpserver/makefile b/example/freertos/net/httpserver/makefile index 7759caeae..0b3181a0d 100644 --- a/example/freertos/net/httpserver/makefile +++ b/example/freertos/net/httpserver/makefile @@ -1,8 +1,11 @@ # Application name APPL ?= freertos_net_httpserver +ifeq ($(BOARD), emsdp) +EXT_DEV_LIST += wifi/rs9113 +else EXT_DEV_LIST += wifi/mrf24g - +endif # # root dir of embARC diff --git a/example/freertos/net/ntshell/FreeRTOSConfig.h b/example/freertos/net/ntshell/FreeRTOSConfig.h index 133c736ef..c1ec52693 100644 --- a/example/freertos/net/ntshell/FreeRTOSConfig.h +++ b/example/freertos/net/ntshell/FreeRTOSConfig.h @@ -86,7 +86,7 @@ #define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) #define configMAX_PRIORITIES ( 10 ) #define configMINIMAL_STACK_SIZE ( ( unsigned short ) 104 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 24 * 1024 ) ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 32 * 1024 ) ) #define configMAX_TASK_NAME_LEN ( 10 ) #define configUSE_TRACE_FACILITY 0 #define configUSE_16_BIT_TICKS 0 diff --git a/example/freertos/net/ntshell/lwipopts.h b/example/freertos/net/ntshell/lwipopts.h index 2a3e5be84..46c0d42f2 100644 --- a/example/freertos/net/ntshell/lwipopts.h +++ b/example/freertos/net/ntshell/lwipopts.h @@ -158,7 +158,7 @@ /** * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */ -#define PBUF_POOL_SIZE 120 +#define PBUF_POOL_SIZE 60 /* --------------------------------- diff --git a/example/freertos/net/ntshell/makefile b/example/freertos/net/ntshell/makefile index 4f7423126..2ac97706a 100644 --- a/example/freertos/net/ntshell/makefile +++ b/example/freertos/net/ntshell/makefile @@ -1,15 +1,18 @@ # Application name APPL ?= freertos_net_ntshell -EXT_DEV_LIST += wifi/mrf24g - BOARD ?= emsk +ifeq ($(BOARD), emsdp) +EXT_DEV_LIST += wifi/rs9113 +else +EXT_DEV_LIST += wifi/mrf24g +endif + ifeq ($(BOARD),emsk) EXT_DEV_LIST += sensor/temperature/adt7420 endif - # # root dir of embARC # diff --git a/example/freertos/sec/mbedtls/dtls/client/lwipopts.h b/example/freertos/sec/mbedtls/dtls/client/lwipopts.h index b42cf97b0..101fd2546 100644 --- a/example/freertos/sec/mbedtls/dtls/client/lwipopts.h +++ b/example/freertos/sec/mbedtls/dtls/client/lwipopts.h @@ -159,7 +159,7 @@ /** * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */ -#define PBUF_POOL_SIZE 120 +#define PBUF_POOL_SIZE 60 /* --------------------------------- diff --git a/example/freertos/sec/mbedtls/dtls/server/lwipopts.h b/example/freertos/sec/mbedtls/dtls/server/lwipopts.h index b42cf97b0..101fd2546 100644 --- a/example/freertos/sec/mbedtls/dtls/server/lwipopts.h +++ b/example/freertos/sec/mbedtls/dtls/server/lwipopts.h @@ -159,7 +159,7 @@ /** * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */ -#define PBUF_POOL_SIZE 120 +#define PBUF_POOL_SIZE 60 /* --------------------------------- diff --git a/example/freertos/sec/mbedtls/ssl/client2/lwipopts.h b/example/freertos/sec/mbedtls/ssl/client2/lwipopts.h index b42cf97b0..101fd2546 100644 --- a/example/freertos/sec/mbedtls/ssl/client2/lwipopts.h +++ b/example/freertos/sec/mbedtls/ssl/client2/lwipopts.h @@ -159,7 +159,7 @@ /** * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */ -#define PBUF_POOL_SIZE 120 +#define PBUF_POOL_SIZE 60 /* --------------------------------- diff --git a/example/freertos/sec/mbedtls/ssl/server2/lwipopts.h b/example/freertos/sec/mbedtls/ssl/server2/lwipopts.h index b42cf97b0..101fd2546 100644 --- a/example/freertos/sec/mbedtls/ssl/server2/lwipopts.h +++ b/example/freertos/sec/mbedtls/ssl/server2/lwipopts.h @@ -159,7 +159,7 @@ /** * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */ -#define PBUF_POOL_SIZE 120 +#define PBUF_POOL_SIZE 60 /* --------------------------------- From fcfe76243a2be88024c63b0a90b94427a3ed1c80 Mon Sep 17 00:00:00 2001 From: Watson Zeng Date: Thu, 10 Jan 2019 17:43:21 +0800 Subject: [PATCH 18/28] example: imu_mpu9250: fix board support (i.e. STAR9001444868) Signed-off-by: Watson Zeng --- example/baremetal/imu_mpu9250/main.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/example/baremetal/imu_mpu9250/main.c b/example/baremetal/imu_mpu9250/main.c index c4c65e6d4..e3fe7dc2a 100644 --- a/example/baremetal/imu_mpu9250/main.c +++ b/example/baremetal/imu_mpu9250/main.c @@ -33,11 +33,10 @@ #include "mpu9250.h" #include "stdio.h" -#if defined(BOARD_EMSK) -/* pls configure the correct IIC master ID for mpu9250 */ -#define MPU9250_IIC_ID 0 -#else +#if defined(BOARD_IOTDK) || defined(BOARD_EMSDP) #define MPU9250_IIC_ID DFSS_IIC_0_ID +#else +#define MPU9250_IIC_ID 0 #endif static MPU9250_DEFINE(mpu9250_sensor, MPU9250_IIC_ID, MPU9250_IIC_ADDRESS); From c68800a61325ef91e53d5a9bbc0c10e019f7a6dd Mon Sep 17 00:00:00 2001 From: Watson Zeng Date: Thu, 10 Jan 2019 17:48:02 +0800 Subject: [PATCH 19/28] board: hsdk: add led_read function(i.e. STAR9001444897) Signed-off-by: Watson Zeng --- board/hsdk/common/hsdk_io.c | 14 ++++++++++++++ board/hsdk/common/hsdk_io.h | 1 + 2 files changed, 15 insertions(+) diff --git a/board/hsdk/common/hsdk_io.c b/board/hsdk/common/hsdk_io.c index 78562768d..d413834ba 100644 --- a/board/hsdk/common/hsdk_io.c +++ b/board/hsdk/common/hsdk_io.c @@ -123,6 +123,20 @@ void led_write(uint32_t led_val, uint32_t mask) return; } +/** read led value, on for 1, off for 0 */ +uint32_t led_read(uint32_t mask) +{ + uint32_t value; + + cy8c95xx_readport(&cy8c95xx_obj, CY8C95XX_PORT_1, (uint8_t *)&value); + value &= mask; + + return value; + +error_exit: + return 0; +} + /** hsdk on board io init */ void hsdk_io_init(void) { diff --git a/board/hsdk/common/hsdk_io.h b/board/hsdk/common/hsdk_io.h index 013d17c4e..a075e5de5 100644 --- a/board/hsdk/common/hsdk_io.h +++ b/board/hsdk/common/hsdk_io.h @@ -51,6 +51,7 @@ extern "C" { extern void hsdk_io_init(void); extern void led_write(uint32_t led_val, uint32_t mask); +extern uint32_t led_read(uint32_t mask); // Un-implemented Switch/Button functions // extern void hsdk_button_init(void); From cb780a592d4c7ca91f94ed61b639fbda1805a0b0 Mon Sep 17 00:00:00 2001 From: Yuguo Zou Date: Fri, 11 Jan 2019 14:33:06 +0800 Subject: [PATCH 20/28] example: Modify udma example; and correct typos in arc headfiles Signed-off-by: Yuguo Zou --- example/baremetal/arc_feature/udma/main.c | 229 +++++++++++++++------- inc/arc/arc_exception.h | 2 +- inc/arc/arc_udma.h | 4 +- 3 files changed, 158 insertions(+), 77 deletions(-) diff --git a/example/baremetal/arc_feature/udma/main.c b/example/baremetal/arc_feature/udma/main.c index 63f061306..f38583329 100644 --- a/example/baremetal/arc_feature/udma/main.c +++ b/example/baremetal/arc_feature/udma/main.c @@ -39,15 +39,33 @@ #define UDMA_TIMER_ID TIMER_1 #endif +//Waring: remember to increase heap size in makefile in order to use multiple channels. +//Warning: With multiple channels in use, the memory usage is increase and it could exceed cache's capability. A significent redution of cycles for cache operations will be observed. +#define DMA_USE_CHANNEL_NUM 4 //DMA_ALL_CHANNEL_NUM +#define TEST_INCREMENT 1024 //MEMSZ_GAP +#if DMA_USE_CHANNEL_NUM > DMA_ALL_CHANNEL_NUM +#warning Use more channels than the board has! +#undef DMA_USE_CHANNEL_NUM +#define DMA_USE_CHANNEL_NUM DMA_ALL_CHANNEL_NUM +#endif + +//define USE_EXTRA_TASK will stop reading of comparison result, assuming that all memory copy / dma copy are succeed +#define USE_EXTRA_TASK +#ifdef USE_EXTRA_TASK +#define EXTRA_TASK_NUM 1 +#else +#define EXTRA_TASK_NUM 0 +#endif + #define _MEMORY_FENCE() _arc_sync() #define _DCACHE_FLUSH_MLINES(addr, size) dcache_flush_mlines((uint32_t)(addr), (uint32_t)(size)) #define _DCACHE_INVALIDATE_MLINES(addr, size) dcache_invalidate_mlines((uint32_t)(addr), (uint32_t)(size)) #define _ICACHE_INVALIDATE_MLINES(addr, size) icache_invalidate_mlines((uint32_t)(addr), (uint32_t)(size)) -static volatile unsigned int start = 0; -static unsigned int perf_id = 0xFF; +static volatile uint32_t start = 0; +static uint32_t perf_id = 0xFF; /** performance timer initialization */ -static void perf_init(unsigned int id) +static void perf_init(uint32_t id) { if (timer_start(id, TIMER_CTRL_NH, 0xFFFFFFFF) < 0) { EMBARC_PRINTF("perf timer init failed\r\n"); @@ -65,9 +83,9 @@ static void perf_start(void) } /** performance timer end, and return the time passed */ -unsigned int perf_end(void) +uint32_t perf_end(void) { - unsigned int end = 0; + uint32_t end = 0; if (timer_current(perf_id, (void *)(&end)) < 0) { return 0; @@ -81,43 +99,54 @@ unsigned int perf_end(void) } static dma_state_t udma; -static dma_channel_t dma_chn; -static dma_desc_t dma_desc; +static dma_channel_t dma_chn[DMA_USE_CHANNEL_NUM]; +static dma_desc_t dma_desc[DMA_USE_CHANNEL_NUM]; static dma_ctrl_t dma_ctrl; -static int32_t dma_channel = DMA_CHN_ANY; /* Notice: here must use int32_t type */ - +int32_t extra_cpy_task(uint32_t size); int32_t dma_prepare(void) { + int32_t dma_channel = DMA_CHN_ANY; DMA_CTRL_SET_OP(&dma_ctrl, DMA_SINGLE_TRANSFER); DMA_CTRL_SET_RT(&dma_ctrl, DMA_AUTO_REQUEST); DMA_CTRL_SET_DTT(&dma_ctrl, DMA_MEM2MEM); - DMA_CTRL_SET_DWINC(&dma_ctrl, DMA_DW1INC1); + DMA_CTRL_SET_DWINC(&dma_ctrl, DMA_DW4INC4); DMA_CTRL_SET_AM(&dma_ctrl, DMA_AM_SRCINC_DSTINC); DMA_CTRL_SET_ARB(&dma_ctrl, 255); - DMA_CTRL_SET_INT(&dma_ctrl, DMA_INT_DISABLE); - - dmac_config_desc(&dma_desc, NULL, NULL, 0, &dma_ctrl); - - dmac_desc_add_linked(&dma_desc, NULL); - /* Init and configure dma channel transfer with transfer descriptor */ - dmac_init_channel(&dma_chn); - dmac_config_channel(&dma_chn, &dma_desc); - - /* Reserve a channel for use */ - dma_channel = dmac_reserve_channel(DMA_CHN_ANY, &dma_chn, DMA_REQ_SOFT); + DMA_CTRL_SET_INT(&dma_ctrl, DMA_INT_ENABLE); + + for(uint8_t i = 0; i < DMA_USE_CHANNEL_NUM; i++){ + dmac_config_desc(dma_desc + i, NULL, NULL, 0, &dma_ctrl); + dmac_desc_add_linked(dma_desc + i, NULL); + + /* Init and configure dma channel transfer with transfer descriptor */ + dmac_init_channel(dma_chn + i); + dmac_config_channel(dma_chn + i, dma_desc + i); + /* Reserve a channel for use */ + dma_channel = dmac_reserve_channel(DMA_CHN_ANY, dma_chn + i, DMA_REQ_SOFT); + if(dma_channel == DMA_CHN_INVALID){ + EMBARC_PRINTF("dmac_reserve_channel No.%d failed, ret %d\r\n", i, dma_channel); + } + } return dma_channel; } void dma_finish(void) { /* Release channel resource */ - dmac_release_channel(&dma_chn); + for(uint8_t i = 0; i < DMA_USE_CHANNEL_NUM; i++){ + dmac_release_channel(dma_chn+i); + } } #define TEST_ENABLE_DMA_INTERRUPT +static volatile uint32_t task_done_count = 0; static void dma_xfer_callback(void *param) { - + // dma_channel_t *dma_chn = (dma_channel_t *)param; + arc_lock(); + task_done_count++; + arc_unlock(); + // EMBARC_PRINTF("i%d ", dma_chn->channel); } uint32_t cycles_cnt[15]; @@ -127,12 +156,22 @@ int32_t dma_copy(void *dst, void *src, uint32_t size) int32_t ercd = -1; cycles_idx = 0; dma_callback_t xfer_cb = NULL; + uint8_t ch_idx; + uint32_t ch_dst, ch_src, ch_size; #ifdef TEST_ENABLE_DMA_INTERRUPT xfer_cb = dma_xfer_callback; #endif + ch_dst = (uint32_t)dst; + ch_src = (uint32_t)src; + ch_size = size / DMA_USE_CHANNEL_NUM; cycles_cnt[cycles_idx++] = perf_end(); - dmac_config_desc(&dma_desc, src, dst, size, &dma_ctrl); + for(ch_idx = 0; ch_idx < DMA_USE_CHANNEL_NUM; ch_idx++){ + //EMBARC_PRINTF("dma_copy:%d src%x, dst%x, size%d \r\n", ch_idx, ch_src, ch_dst, ch_size); + dmac_config_desc(dma_desc + ch_idx, (void *)ch_src, (void *)ch_dst, ch_size, &dma_ctrl); + ch_src += ch_size; + ch_dst += ch_size; + } cycles_cnt[cycles_idx++] = perf_end(); _MEMORY_FENCE(); @@ -141,16 +180,21 @@ int32_t dma_copy(void *dst, void *src, uint32_t size) _DCACHE_FLUSH_MLINES((void *)dst, size); // _ICACHE_INVALIDATE_MLINES((void *)dst, size); cycles_cnt[cycles_idx++] = perf_end(); + /* Start channel transfer with priority, without callback */ - dmac_start_channel(&dma_chn, xfer_cb, DMA_CHN_HIGH_PRIO); + for(ch_idx = 0; ch_idx < DMA_USE_CHANNEL_NUM; ch_idx++){ + ercd = dmac_start_channel(dma_chn + ch_idx, xfer_cb, DMA_CHN_HIGH_PRIO); + if(ercd != 0){ + EMBARC_PRINTF("dma_copy: start channel failed, index %d ret %d\r\n", ch_idx, ercd); + } + } cycles_cnt[cycles_idx++] = perf_end(); - +#ifdef USE_EXTRA_TASK + ercd = extra_cpy_task(size); + // EMBARC_PRINTF("dma_copy: extra_cpy_task ret %d\r\n", ercd); +#endif /* Wait until transfer is done */ - if (dmac_wait_channel(&dma_chn) != DMA_IDLE) { - ercd = -1; - } else { - ercd = 0; - } + while(task_done_count < DMA_USE_CHANNEL_NUM + EXTRA_TASK_NUM); cycles_cnt[cycles_idx++] = perf_end(); _MEMORY_FENCE(); @@ -165,7 +209,7 @@ int32_t dma_copy(void *dst, void *src, uint32_t size) void init_data(uint8_t *src, uint8_t *dst, uint32_t size) { - for (int i = 0; i < size; i ++) { + for (uint32_t i = 0; i < size; i ++) { src[i] = i; dst[i] = 0xFF; } @@ -173,28 +217,31 @@ void init_data(uint8_t *src, uint8_t *dst, uint32_t size) int32_t cmp_data(uint8_t *src, uint8_t *dst, uint32_t size) { - uint32_t err_cnt = 0; - for (int i = 0; i < size; i ++) { + for (uint32_t i = 0; i < size; i ++) { if (src[i] != dst[i]) { - err_cnt ++; //EMBARC_PRINTF("%u:%u %u\r\n", i, src[i], dst[i]); - //return -1; + #ifndef USE_EXTRA_TASK + return -1; + #endif } } - if (err_cnt == 0) { - return 0; - } else { - return -1; - } + return 0; } int32_t perf_memcpy(uint8_t *src, uint8_t *dst, uint32_t size) { uint32_t cycles; + task_done_count = 0; init_data(src, dst, size); perf_init(UDMA_TIMER_ID); perf_start(); memcpy(dst, src, size); +#ifdef USE_EXTRA_TASK + if(extra_cpy_task(size)!=0){ + return -1; + } +#endif + while(task_done_count < EXTRA_TASK_NUM); cycles = perf_end(); if (cmp_data(src, dst, size) == 0) { return cycles; @@ -206,6 +253,7 @@ int32_t perf_memcpy(uint8_t *src, uint8_t *dst, uint32_t size) int32_t perf_dmacpy(uint8_t *src, uint8_t *dst, uint32_t size) { uint32_t cycles; + task_done_count = 0; init_data(src, dst, size); perf_init(UDMA_TIMER_ID); perf_start(); @@ -227,57 +275,90 @@ int32_t perf_overhead(void) return cycles; } -#define MEMSZ_GAP 256 +#ifdef USE_EXTRA_TASK +int32_t extra_cpy_task(uint32_t size){ + uint8_t *src_ptr = NULL; + uint8_t *dst_ptr = NULL; + + src_ptr = (uint8_t *)malloc(size); + dst_ptr = (uint8_t *)malloc(size); + if ((src_ptr == NULL) || (dst_ptr == NULL)) { + EMBARC_PRINTF("extra_cpy_task: Not enough memory for testing, exit this example!\r\n"); + return -1; + } + init_data(src_ptr, dst_ptr, size); + memcpy(dst_ptr, src_ptr, size); + if (cmp_data(src_ptr, dst_ptr, size) == 0) { + arc_lock(); + task_done_count++; + arc_unlock(); + free(src_ptr); + free(dst_ptr); + return 0; + } else { + EMBARC_PRINTF("extra_cpy_task: data error!\r\n"); + free(src_ptr); + free(dst_ptr); + return -1; + } +} +#endif //USE_EXTRA_TASK + int main( void ) { - uint32_t test_sz = 256; + uint32_t test_sz = TEST_INCREMENT; uint8_t *src_ptr = NULL; uint8_t *dst_ptr = NULL; int32_t dmacpy_cycles, memcpy_cycles; + int32_t ret; /** Must init uDMA before use it */ + EMBARC_PRINTF("DMA test: DMA has %d channels, now uses %d channels\r\n", DMA_ALL_CHANNEL_NUM, DMA_USE_CHANNEL_NUM); dmac_init(&udma); - - if (dma_prepare() == DMA_CHN_INVALID) { - EMBARC_PRINTF("No valid dma channel for testing, failed this example.\r\n"); + ret = dma_prepare(); + if (ret == DMA_CHN_INVALID) { + EMBARC_PRINTF("dma channel failed, exit.\r\n"); return -1; } EMBARC_PRINTF("Performance benchmark timer overhead is %u cycles\r\n", perf_overhead()); EMBARC_PRINTF("Performance benchmark for both dmacpy and memcpy including overhead\r\n"); EMBARC_PRINTF("XFER_SIZE DESC_CONF CACHE_FLUSH XFER_START XFER_WAIT CACHE_INV DMACPY MEMCPY\r\n"); do { - src_ptr = (uint8_t *)malloc(test_sz); - dst_ptr = (uint8_t *)malloc(test_sz); - if ((src_ptr == NULL) || (dst_ptr == NULL)) { - EMBARC_PRINTF("Not enough memory for testing, exit this example!\r\n"); - break; + if(test_sz % DMA_USE_CHANNEL_NUM != 0){ + EMBARC_PRINTF("dma_copy: test_sz unable to be divided by %d channels, skip\r\n", DMA_USE_CHANNEL_NUM); + } else { + src_ptr = (uint8_t *)malloc(test_sz); + dst_ptr = (uint8_t *)malloc(test_sz); + if ((src_ptr == NULL) || (dst_ptr == NULL)) { + EMBARC_PRINTF("Not enough memory for testing, exit this example!\r\n"); + break; + } + memcpy_cycles = perf_memcpy(src_ptr, dst_ptr, test_sz); + dmacpy_cycles = perf_dmacpy(src_ptr, dst_ptr, test_sz); + if (memcpy_cycles == -1) { + EMBARC_PRINTF("MEMCPY API Test failed!\r\n"); + break; + } + if (dmacpy_cycles == -1) { + EMBARC_PRINTF("DMACPY API Test failed!\r\n"); + break; + } + EMBARC_PRINTF("%u ", test_sz); + for (uint32_t i = 1; i < cycles_idx; i++) { + EMBARC_PRINTF("%u ", cycles_cnt[i]-cycles_cnt[i-1]); + } + EMBARC_PRINTF("%u %u\r\n", (uint32_t)dmacpy_cycles, (uint32_t)memcpy_cycles); + + // EMBARC_PRINTF("Copy %u bytes, dmacpy cost %u cycles, memcpy cost %u cycles\r\n", \ + // test_sz, (uint32_t)dmacpy_cycles, (uint32_t)memcpy_cycles); + free(src_ptr); + free(dst_ptr); } - memcpy_cycles = perf_memcpy(src_ptr, dst_ptr, test_sz); - dmacpy_cycles = perf_dmacpy(src_ptr, dst_ptr, test_sz); - if (memcpy_cycles == -1) { - EMBARC_PRINTF("MEMCPY API Test failed!\r\n"); - break; - } - if (dmacpy_cycles == -1) { - EMBARC_PRINTF("DMACPY API Test failed!\r\n"); - break; - } - EMBARC_PRINTF("%u ", test_sz); - for (int i = 1; i < cycles_idx; i++) { - EMBARC_PRINTF("%u ", cycles_cnt[i]-cycles_cnt[i-1]); - } - EMBARC_PRINTF("%u %u\r\n", (uint32_t)dmacpy_cycles, (uint32_t)memcpy_cycles); - - // EMBARC_PRINTF("Copy %u bytes, dmacpy cost %u cycles, memcpy cost %u cycles\r\n", \ - // test_sz, (uint32_t)dmacpy_cycles, (uint32_t)memcpy_cycles); - - test_sz += MEMSZ_GAP; - if (test_sz > 8192) { + test_sz += TEST_INCREMENT; + if (test_sz > 0x2000 * DMA_USE_CHANNEL_NUM) { EMBARC_PRINTF("DMA only support 8K cell transfer\r\n"); break; } - free(src_ptr); - free(dst_ptr); } while(1); if (src_ptr != NULL) { diff --git a/inc/arc/arc_exception.h b/inc/arc/arc_exception.h index f6c7d3109..8abdb92d2 100644 --- a/inc/arc/arc_exception.h +++ b/inc/arc/arc_exception.h @@ -420,7 +420,7 @@ Inline uint32_t arc_locked(void) } /** - * \brief lock cpu and staus + * \brief lock cpu and status * * \returns cpu status */ diff --git a/inc/arc/arc_udma.h b/inc/arc/arc_udma.h index eb621ce4c..8b8ac86bf 100644 --- a/inc/arc/arc_udma.h +++ b/inc/arc/arc_udma.h @@ -209,8 +209,8 @@ typedef enum _dma_ctrl_am { /** DMA channel priority enumeration */ typedef enum _dma_chn_prio { - DMA_CHN_NORM_PRIO = 0, /*!< High priority */ - DMA_CHN_HIGH_PRIO = 1 /*!< Normal priority */ + DMA_CHN_NORM_PRIO = 0, /*!< Normal priority */ + DMA_CHN_HIGH_PRIO = 1 /*!< High priority */ } dma_chn_prio_t; From 026d61cad82196e57ace3b606c76f2c70e3d0136 Mon Sep 17 00:00:00 2001 From: Watson Zeng Date: Mon, 14 Jan 2019 10:10:56 +0800 Subject: [PATCH 21/28] doc: mirror fix; add mcuboot doc; modify bootloader doc Signed-off-by: Watson Zeng --- doc/documents/bsp/bsp.rst | 2 +- .../getting_started/hardware_requirement.rst | 1 + doc/documents/lib/library.rst | 3 +- doc/documents/lib/mcuboot.rst | 52 ++++++++++++++ .../baremetal_bootloader/boot_loader_flow.jpg | Bin 0 -> 64040 bytes .../emsk_bootloader_mcuboot.jpg | Bin 0 -> 149478 bytes example/baremetal/bootloader/README.rst | 64 ++++++++++++++---- 7 files changed, 108 insertions(+), 14 deletions(-) create mode 100644 doc/documents/lib/mcuboot.rst create mode 100644 doc/documents/pic/images/example/baremetal_bootloader/boot_loader_flow.jpg create mode 100644 doc/documents/pic/images/example/baremetal_bootloader/emsk_bootloader_mcuboot.jpg diff --git a/doc/documents/bsp/bsp.rst b/doc/documents/bsp/bsp.rst index d002a3e81..b93c876b2 100644 --- a/doc/documents/bsp/bsp.rst +++ b/doc/documents/bsp/bsp.rst @@ -49,7 +49,7 @@ alternative. # On Linux cd ~ # embARC BSP for EMSK - git clone https://github.com/foss-for-synopsys-dwc-arc-processors/ embarc_emsk_bsp.git embarc_bsp + git clone https://github.com/foss-for-synopsys-dwc-arc-processors/embarc_emsk_bsp.git embarc_bsp 3. The embARC BSP code is independent with build systems. Various build systems can support embARC BSP code. Using the *hello world* as a base model, the following sections will describe how to build a embARC BSP application. diff --git a/doc/documents/getting_started/hardware_requirement.rst b/doc/documents/getting_started/hardware_requirement.rst index d0a398095..28ff9c05f 100644 --- a/doc/documents/getting_started/hardware_requirement.rst +++ b/doc/documents/getting_started/hardware_requirement.rst @@ -7,6 +7,7 @@ Board Requirement ################# * ARC Board + * ARC Software Development Platform * `ARC EM Starter Kit `_ * `ARC HS Development Kit `_ * AXS Board diff --git a/doc/documents/lib/library.rst b/doc/documents/lib/library.rst index 28d6fc84d..e973ef596 100644 --- a/doc/documents/lib/library.rst +++ b/doc/documents/lib/library.rst @@ -7,4 +7,5 @@ Libraries :maxdepth: 2 c_lib.rst - secureshield.rst \ No newline at end of file + secureshield.rst + mcuboot.rst \ No newline at end of file diff --git a/doc/documents/lib/mcuboot.rst b/doc/documents/lib/mcuboot.rst new file mode 100644 index 000000000..7d08a2b72 --- /dev/null +++ b/doc/documents/lib/mcuboot.rst @@ -0,0 +1,52 @@ +.. _lib_c_lib: + +MCUBoot +####### + + +Introduction +============ + +MCUboot is a secure bootloader for 32-bit MCUs. The goal of MCUboot is to define a common infrastructure for the bootloader, +system flash layout on microcontroller systems, and to provide a secure bootloader that enables easy software upgrade. + +MCUboot is operating system and hardware independent and relies on hardware porting layers from the operating system it works with. + +MCUBoot is hosted on github now. + +Using MUCBoot +============= + +embARC uses MCUBoot in bootloader to validate the binary image by SHA-256 hash function and asymmetric encryption RSA algorithm for the integrity check +and signature verification, and embARC uses MCUBoot image tools to sign each application binary. + +Steps +----- + +* Install Python3 +* Install several dependencies on Python libraries + + .. code-block:: console + + $ cd /library/mcuboot + $ pip3 install --user -r scripts/requirements.txt + +Sign your application +--------------------- + +This signs the image by computing hash over the image, and then signing that hash. Signature is computed by newt tool when it's creating the image. +This signature is placed in the image trailer. + +embARC already adds the sign command in compile system, you can use it very conveniently. + +.. code-block:: console + + $ cd + $ make sign + +There is a default public keypair used to signature and validation under the folder */library/mcuboot*. +If you want to use a new one please reference `manage keys manual`_ to generate and replace the *key.c* and *root-rsa-2048.pem*. + +.. note:: By default, embARC configures MCUBoot in the bootloader to use RSA as asymmetric encryption function. So make sure to generate the rsa-2048 keys. + +.. _manage keys manual: https://github.com/JuulLabs-OSS/mcuboot/blob/master/docs/imgtool.md#managing-keys diff --git a/doc/documents/pic/images/example/baremetal_bootloader/boot_loader_flow.jpg b/doc/documents/pic/images/example/baremetal_bootloader/boot_loader_flow.jpg new file mode 100644 index 0000000000000000000000000000000000000000..88e29ad14a8b924cfe4c20c921eee091baaea885 GIT binary patch literal 64040 zcmd?QXFyY3w=Nor(m{F$l`2(wC!*3sM0y7mlqMj(1%e=l9CXUkdTp6-6A8WBqt%cMR$vm znueB^mXv~?fsTfOiiVcv_aHcU*lX}_5Z$;zL_jQR z;8EgWIsxne0L~38+TVcx`wIsbi}5A_ArUbNwnOzT04@$59xguKZ`9b{{@CvU_>?!O z?uaPeq}F~(aMy)K^nH95A;-gtHd>ugIH%Yv*B~NdI(i01CN6Fs-g|uF5|UEVGO~{z zE32rgsXx)x(>E|QGB&ZYe*MPA*3RC|-NVz%+s8NfLr7@Y$MA@R#7{}dDW6l*vU76t z@(T)!ihopARo6gk>+0J(I=i}idi(mv#wRAHre|hhE30ek8=G6dws#Om$0w&}=g5o8 z-*({u@czxLe_HnM?4rclg^Q1mhfna^E*xAhY{R3(zi~(8CY6#l!AlqFyQ1$2X&%OB zRkRUti0Qy-U%8GF({YNga3Ox1_LpVWBf3_yy9gZ=UFC;>pgwQhC< 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bootloader for embARC, it will load boot.hex or boot.bin on SDCard and run that program. And this example itself can be used as ntshell application. + This example is designed to work as a secondary bootloader for embARC, it will load boot.hex or boot.bin on SDCard and run that program. By default, this example will validate the binary image based on MCUBoot to do secure boot. And this example itself can be used as ntshell application. Detailed Description ==================== * Extra Required Tools - NO + - The requirements of MCUBoot image tools * Extra Required Peripherals - SDCard with boot binary(boot.hex or boot.bin) @@ -20,10 +20,14 @@ Detailed Description * Design Concept This example is designed to work as a secondary bootloader for embARC, it will load boot.hex or boot.bin on SDCard and run that program. And this example itself can be used as ntshell application. + This example combines multiple usage cases, including the image is in SD or Flash, and whether or not to use MCUboot. The program flow of this example as following. + + .. image:: /pic/images/example/baremetal_bootloader/boot_loader_flow.jpg + * Usage Manual As shown in the following picture, when the EMSK configuration in SPI flash is loaded into the FPGA, a simple primary bootloader is also loaded in ICCM. Through the primary bootloader, the application or secondary bootloader can be loaded into external memory (DDR memory), bootloader start address is 0x17F00004, ram address is 0x17F00000. - For EMSK1.x, bootloader core configuration must be arcem6, for EMSK2.x, bootloader core configuration must be arcem7d. + For EMSK 1.x, bootloader core configuration must be arcem6, for EMSK2.x, bootloader core configuration must be arcem7d. For EMSK 1.0, it can be upgraded to 1.1 by 1.1's firmware. For EMSK 2.0/2.1/2.2, it can be upgraded to 2.3 by 2.3's firmware. .. image:: /pic/bootloader.jpg @@ -38,9 +42,24 @@ Detailed Description + Then use ntshell command *spirw* to program the *em7d_2bt.bin* into spiflash. - Firstly, run *spirw* to show help - Secondly, run *spirw -i* to check SPIFlash ID, it should be **Device ID = ef4018** - - Thirdly, run *spirw -w em7d_2bt.bin 0x17f00000 0x17f00004* to program spiflash + - Thirdly, run *spirw -w em7d_2bt.bin ram_addr ram_start* to program spiflash, the *ram_addr* and *ram_start* is the load address and program start address of this bootloader, and they are different in each board, please check they in the table below. Usually, developer creates *appl_mem_config.h* and set **APPL_DEFINES += -DUSE_APPL_MEM_CONFIG** in *makefile* to define the addresses. - Check the output message to see if it was programmed successfully. + .. table:: Examples in embARC OSP + :widths: auto + + ======================= ====================== ====================== ======================= + Board version Use MCUBoot ram_addr ram_start + ======================= ====================== ====================== ======================= + axs not support user definition user definition + emsdp not support user definition user definition + emsk true 0x15000000 0x15000004 + emsk false user definition user definition + iotdk true 0x00000000 0x00000004 + iotdk false user definition user definition + nsim not support user definition user definition + ======================= ====================== ====================== ======================= + .. image:: /pic/images/example/baremetal_bootloader/emsk_bootloader_program2splflash.jpg + If programmed successfully, when the board is reset, make sure Bit 4 of the onboard DIP switch is ON to enable secondary bootloader run. @@ -49,7 +68,7 @@ Detailed Description .. image:: /pic/images/example/baremetal_bootloader/emsk_bootloader_onspiflash.jpg - - Generate *boot.bin* using any embARC example which ram start address should be 0x10000000 and use bootloader to run it + - When not using MCUBoot, generate *boot.bin* using any embARC example which ram start address should be 0x10000000 and use bootloader to run it - Know Issues + Bootrom of EMSK1.x is not able to load secondary bootloader on SPIFlash, you need a modified EMSK1.x mcs file to enable this function, please send request in forum about this mcs file. @@ -59,11 +78,15 @@ Detailed Description - Operations on the EMSK, GPIO, I2C, SPI flash - Operations on ARC processors - Automatic boot from SD card, using following instructions: - + burn the bin file of bootloader into EMSK spiflash using spirw command **spirw -w bootloader.bin 0x17f00000 0x17f00004** with the help of JTAG + + program the bin file of bootloader into EMSK spiflash using spirw command **spirw -w bootloader.bin ram_addr ram_start** with the help of JTAG + the primary bootloader should be able to load the secondary bootloader + put the file you want to boot in the root directory of SD card, name it boot.bin + plug in SD card + - Optional secure boot based on MCUBoot: + + validate the binary image by SHA-256 hash function and asymmetric encryption RSA algorithm for the integrity check and signature verification + + validate the new binary image for upgrade and do firmware upgrade + - LED Status of loading application(boot.bin) + Start to load application: LED on board -> 0x0F + Load application finished: LED on board -> 0xFF, if application is running normally, LED will quickly change to 0x0 @@ -72,7 +95,7 @@ Detailed Description - Type *help* command in ntshell to show the list of supported commands. - .. image:: /pic/images/example/baremetal_bootloader/emsk_bootloader.jpg + .. image:: /pic/images/example/baremetal_bootloader/emsk_bootloader.jpg * Extra Comments - Bootrom of EMSK1.x is not able to load secondary bootloader on SPIFlash, you need a modified EMSK1.x mcs file to enable this function, please send @@ -91,6 +114,8 @@ Building and Running - Generate a secondary bootloader binary file +.. note:: If you want to disable MCUBoot, you should set **USE_MCUBOOT = 0** in your makefile + .. code-block:: console $ cd /example/baremetal/bootloader @@ -131,15 +156,28 @@ If the binary file is generated successfully, you will output as follows: "Linking : " obj_emsk_23/gnu_arcem7d/emsk_bootloader_gnu_arcem7d.elf "Generating Binary obj_emsk_23/gnu_arcem7d/emsk_bootloader_gnu_arcem7d.bin" -- Generate *boot.bin* using any embARC example which ram start address should be 0x10000000 and use bootloader to run it +- Generate *boot.bin* using any embARC example + Here take */example/freertos/kernel* for example + + When using MCUBoot, you should modify **LIB_SEL += mcuboot** in your makefile to enable MCUBoot. And you should use the imgtool to sign the generated binary + .. code-block:: console - $ cd /example/freertos/kernel - $ gmake BOARD=emsk BD_VER=22 CUR_CORE=arcem7d TOOLCHAIN=mw bin + $ cd /example/freertos/kernel + $ gmake BOARD=emsk BD_VER=22 CUR_CORE=arcem7d TOOLCHAIN=mw bin + $ gmake BOARD=emsk BD_VER=22 CUR_CORE=arcem7d TOOLCHAIN=mw sign - + Insert SDCard to PC, and copy generated binary file *obj_emsk_23/gnu_arcem7d/freertos_kernel_gnu_arcem7d.bin* to SDCard Root, and rename it to boot.bin + Or you can use sign command directly, which will generate binary firstly and sign it + + + When not using MCUBoot, the example ram start address should be 0x10000000 + + .. code-block:: console + + $ cd /example/freertos/kernel + $ gmake BOARD=emsk BD_VER=22 CUR_CORE=arcem7d TOOLCHAIN=mw bin + + + Insert SDCard to PC, and copy generated binary file *obj_emsk_22/mw_arcem7d/freertos_kernel_mw_arcem7d.bin* to SDCard Root, and rename it to boot.bin + Please note that when using MCUBoot, the origin binary name is *obj_emsk_22/mw_arcem7d/signed_freertos_kernel.bin* + Insert SDCard back to EMSK, make sure bit 4 of DIP Switch is ON, and press re-configure button above letter **C**, and wait for autoload. .. note:: Make sure you have selected the correct configuration of EMSK via dipswitches and that you have reset the board (button above "R") to confirm its configuration @@ -149,4 +187,6 @@ Sample Output The output depends on the *boot.bin*. This sample is using */example/freertos/kernel*. -.. image:: /pic/images/example/baremetal_bootloader/emsk_bootloader_loadbootbin.jpg \ No newline at end of file +.. image:: /pic/images/example/baremetal_bootloader/emsk_bootloader_loadbootbin.jpg + +.. image:: /pic/images/example/baremetal_bootloader/emsk_bootloader_mcuboot.jpg From 257f6b82632d69cd66cff2fe0d8c97c666bb8c8e Mon Sep 17 00:00:00 2001 From: Watson Zeng Date: Wed, 16 Jan 2019 10:24:12 +0800 Subject: [PATCH 22/28] example: dma_spiflash: fix board support (i.e. STAR9001444837) Signed-off-by: Watson Zeng --- example/baremetal/dma_spiflash/README.rst | 3 +++ example/baremetal/dma_spiflash/main.c | 10 ++++++++-- example/baremetal/dma_spiflash/spi_flash.c | 4 +++- 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/example/baremetal/dma_spiflash/README.rst b/example/baremetal/dma_spiflash/README.rst index f8cd3803d..652880385 100644 --- a/example/baremetal/dma_spiflash/README.rst +++ b/example/baremetal/dma_spiflash/README.rst @@ -32,6 +32,9 @@ Detailed Description - This example will stuck at the max frequency that SPI can achieve at that situation. - This example required that the ARC core configuration should has uDMA option and DW SPI also enabled DMA interface with uDMA +.. note:: + this example only support |emsdp| board. + Sample Output ============= diff --git a/example/baremetal/dma_spiflash/main.c b/example/baremetal/dma_spiflash/main.c index 2ec0d8a70..05aa66ca4 100644 --- a/example/baremetal/dma_spiflash/main.c +++ b/example/baremetal/dma_spiflash/main.c @@ -30,6 +30,7 @@ #include "embARC.h" #include "embARC_debug.h" +#if defined(BOARD_EMSK) #include "spi_flash.h" #include "spi_flash_w25qxx.h" @@ -221,5 +222,10 @@ static unsigned int perf_end(void) return (0xFFFFFFFF - start + end); } } - -/** @} */ \ No newline at end of file +#else +int main(void) +{ + EMBARC_PRINTF("\r\n\r\ndma_spiflash example only support EMSK board!\r\n"); + while(1); +} +#endif //BOARD_EMSK \ No newline at end of file diff --git a/example/baremetal/dma_spiflash/spi_flash.c b/example/baremetal/dma_spiflash/spi_flash.c index fccf95be1..2d8cd3572 100644 --- a/example/baremetal/dma_spiflash/spi_flash.c +++ b/example/baremetal/dma_spiflash/spi_flash.c @@ -1,3 +1,4 @@ +#if defined(BOARD_EMSK) #include #include "board.h" #include "spi_flash.h" @@ -540,4 +541,5 @@ int32_t spiflash_write(uint32_t address, uint32_t size, const void *data) } return (int32_t)(size_orig); -} \ No newline at end of file +} +#endif//#if defined(BOARD_EMSK) \ No newline at end of file From 7409b243ae89fe95cbceb1680e9309830d703f67 Mon Sep 17 00:00:00 2001 From: Watson Zeng Date: Fri, 18 Jan 2019 11:52:55 +0800 Subject: [PATCH 23/28] example: bootloader: mirror fix in fatfs module. Signed-off-by: Watson Zeng --- board/iotdk/drivers/ip/designware/sdio/dw_sdio_obj.c | 1 + example/baremetal/bootloader/appl_mem_config.h | 7 +------ example/baremetal/bootloader/makefile | 8 ++------ middleware/fatfs/source/ffconf.h | 3 ++- 4 files changed, 6 insertions(+), 13 deletions(-) diff --git a/board/iotdk/drivers/ip/designware/sdio/dw_sdio_obj.c b/board/iotdk/drivers/ip/designware/sdio/dw_sdio_obj.c index 0d30fa3f4..104488f68 100644 --- a/board/iotdk/drivers/ip/designware/sdio/dw_sdio_obj.c +++ b/board/iotdk/drivers/ip/designware/sdio/dw_sdio_obj.c @@ -96,6 +96,7 @@ static void dw_sdio_0_install(void) dw_sdio_ctrl_ptr->reg_base = (void *) BASE_ADDR_SDIO; dw_sdio_ctrl_ptr->intno = INTNO_SDIO; dw_sdio_ctrl_ptr->ref_clk = 100000000; + dw_sdio_ctrl_ptr->fifo_depth = 128; dw_sdio_ptr->open = dw_sdio_0_open; dw_sdio_ptr->close = dw_sdio_0_close; diff --git a/example/baremetal/bootloader/appl_mem_config.h b/example/baremetal/bootloader/appl_mem_config.h index 1a03d5474..5b8055db8 100644 --- a/example/baremetal/bootloader/appl_mem_config.h +++ b/example/baremetal/bootloader/appl_mem_config.h @@ -3,12 +3,7 @@ #ifdef BOARD_EMSK #define REGION_EXT_RAM_START 0x17F00000 /* boootloader application start address */ -#define REGION_EXT_RAM_SIZE 0x100000 /* the mem space covered by bootloader */ +#define REGION_EXT_RAM_SIZE 0x100000 /* the mem space covered by bootloader */ #endif -#ifdef BOARD_IOTDK -#ifdef USE_EFLASH_LOCATION -#define REGION_ROM REGION_EXT_ROM -#endif -#endif #endif \ No newline at end of file diff --git a/example/baremetal/bootloader/makefile b/example/baremetal/bootloader/makefile index 103900940..91baff96e 100644 --- a/example/baremetal/bootloader/makefile +++ b/example/baremetal/bootloader/makefile @@ -3,15 +3,11 @@ APPL ?= simple_bootloader BOARD ?= emsk -LOCATION ?= +OLEVEL ?= O2 # use mcuboot in bootloader USE_MCUBOOT ?= 1 -ifeq ($(LOCATION), eflash) -APPL_DEFINES += -DUSE_EFLASH_LOCATION -endif - ifeq ($(BOARD), emsk) EXT_DEV_LIST += sensor/temperature/adt7420 endif @@ -45,7 +41,7 @@ LIB_SEL += mcuboot # decrease bootloader size APPL_DEFINES += -DNTSHELL_USE_CMDS_ARC=0 \ -DNTSHELL_USE_CMDS_PERIPHERAL=0 \ - -D_USE_LFN=0 + -DFF_USE_LFN=0 endif # application source dirs diff --git a/middleware/fatfs/source/ffconf.h b/middleware/fatfs/source/ffconf.h index 075ad7f82..88009f888 100644 --- a/middleware/fatfs/source/ffconf.h +++ b/middleware/fatfs/source/ffconf.h @@ -96,8 +96,9 @@ / 0 - Include all code pages above and configured by f_setcp() */ - +#ifndef FF_USE_LFN #define FF_USE_LFN 1 +#endif #define FF_MAX_LFN 255 /* The FF_USE_LFN switches the support for LFN (long file name). / From 278f55db5faee8b9f6643274788d245dd5c907a1 Mon Sep 17 00:00:00 2001 From: Watson Zeng Date: Fri, 18 Jan 2019 12:04:16 +0800 Subject: [PATCH 24/28] example: cache: fix board support (i.e. STAR9001439062) Signed-off-by: Watson Zeng --- example/baremetal/arc_feature/cache/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/example/baremetal/arc_feature/cache/main.c b/example/baremetal/arc_feature/cache/main.c index e118e834d..fc671620f 100644 --- a/example/baremetal/arc_feature/cache/main.c +++ b/example/baremetal/arc_feature/cache/main.c @@ -44,7 +44,7 @@ #define FILLED_DATA 0xcc __attribute__ ((aligned(DCACHE_LINE_LENGTH*DCACHE_LINE_NUM))) -static unsigned char cache_data[DCACHE_LINE_NUM][DCACHE_LINE_LENGTH]; +static unsigned char cache_data[DCACHE_LINE_NUM][DCACHE_LINE_LENGTH] = {0xFF}; /** * \brief call cache related functions From c809b4d640f5a2774f814a12faa594b40f4ad22d Mon Sep 17 00:00:00 2001 From: Watson Zeng Date: Fri, 18 Jan 2019 14:16:29 +0800 Subject: [PATCH 25/28] example: bootloader: fix the document issues. Signed-off-by: Watson Zeng --- example/baremetal/bootloader/README.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/example/baremetal/bootloader/README.rst b/example/baremetal/bootloader/README.rst index 547dd8456..6ed580446 100644 --- a/example/baremetal/bootloader/README.rst +++ b/example/baremetal/bootloader/README.rst @@ -159,7 +159,7 @@ If the binary file is generated successfully, you will output as follows: - Generate *boot.bin* using any embARC example + Here take */example/freertos/kernel* for example - + When using MCUBoot, you should modify **LIB_SEL += mcuboot** in your makefile to enable MCUBoot. And you should use the imgtool to sign the generated binary + + When using MCUBoot, you should modify **LIB_SEL += mcuboot** and **MID_SEL += mbedtls** in your makefile to enable MCUBoot. And you should use the imgtool to sign the generated binary .. code-block:: console From 254c9b3baf0b5d106db0fbe82ba2b87e388ca136 Mon Sep 17 00:00:00 2001 From: Watson Zeng Date: Fri, 18 Jan 2019 14:44:33 +0800 Subject: [PATCH 26/28] board: emsk: configs: mirror fix in target memory config. Signed-off-by: Watson Zeng --- board/emsk/configs/11/target_mem_config.h | 2 +- board/emsk/configs/22/target_mem_config.h | 2 +- board/emsk/configs/23/target_mem_config.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/board/emsk/configs/11/target_mem_config.h b/board/emsk/configs/11/target_mem_config.h index b23ef49b2..f849af7ae 100644 --- a/board/emsk/configs/11/target_mem_config.h +++ b/board/emsk/configs/11/target_mem_config.h @@ -204,7 +204,7 @@ #ifndef REGION_RAM #ifdef ARC_FEATURE_DCACHE_PRESENT -#define REGION_RAM REGION_EXT_ROM +#define REGION_RAM REGION_EXT_RAM #else #define REGION_RAM REGION_DCCM #endif diff --git a/board/emsk/configs/22/target_mem_config.h b/board/emsk/configs/22/target_mem_config.h index 882f1628c..05c07366a 100644 --- a/board/emsk/configs/22/target_mem_config.h +++ b/board/emsk/configs/22/target_mem_config.h @@ -204,7 +204,7 @@ #ifndef REGION_RAM #ifdef ARC_FEATURE_DCACHE_PRESENT -#define REGION_RAM REGION_EXT_ROM +#define REGION_RAM REGION_EXT_RAM #else #define REGION_RAM REGION_DCCM #endif diff --git a/board/emsk/configs/23/target_mem_config.h b/board/emsk/configs/23/target_mem_config.h index 882f1628c..05c07366a 100644 --- a/board/emsk/configs/23/target_mem_config.h +++ b/board/emsk/configs/23/target_mem_config.h @@ -204,7 +204,7 @@ #ifndef REGION_RAM #ifdef ARC_FEATURE_DCACHE_PRESENT -#define REGION_RAM REGION_EXT_ROM +#define REGION_RAM REGION_EXT_RAM #else #define REGION_RAM REGION_DCCM #endif From b29cdd9ebc70b8024a2e3346863c047738c2370c Mon Sep 17 00:00:00 2001 From: Watson Zeng Date: Fri, 18 Jan 2019 15:17:22 +0800 Subject: [PATCH 27/28] hm1x: fix board support Signed-off-by: Watson Zeng --- device/peripheral/ble/hm1x/hm1x.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/device/peripheral/ble/hm1x/hm1x.h b/device/peripheral/ble/hm1x/hm1x.h index c3d01fc99..682354f22 100644 --- a/device/peripheral/ble/hm1x/hm1x.h +++ b/device/peripheral/ble/hm1x/hm1x.h @@ -31,7 +31,16 @@ /** uart id which HM-10 BLE uses */ +#ifndef HM_1X_UART_ID //you can define this at board header file (e.g. emsk.h) +#if defined(BOARD_EMSK) || defined(BOARD_HSDK) #define HM_1X_UART_ID DW_UART_0_ID +#elif defined(BOARD_EMSDP)|| defined(BOARD_IOTDK) +#define HM_1X_UART_ID DFSS_UART_1_ID +#else +#warning hm1x is not supported on this board! +#endif +#endif + /** * HM1X working role: master or slave */ From e8c5947d943491e2a49542177b79b7afd08d1212 Mon Sep 17 00:00:00 2001 From: Wayne Ren Date: Sat, 19 Jan 2019 02:15:06 +0800 Subject: [PATCH 28/28] driver: sdio: fix bugs in write and configuration 1. the original sdio driver is not fully tested for multiple blocks write, which has lots of bugs 2. the sdio configurations for emsdp and iotdk are not correct are not correct. 3. code style cleanup Signed-off-by: Wayne Ren --- .../drivers/ip/designware/sdio/dw_sdio_obj.c | 2 +- .../drivers/ip/designware/sdio/dw_sdio_obj.c | 3 +- board/iotdk/drivers/sysconf/sysconf.c | 4 +- device/ip/designware/sdio/dw_sdio.c | 47 +++++++++---------- device/ip/designware/sdio/dw_sdio_hal.h | 10 ++-- .../fatfs/source/diskdrv/ff_sdcard_sdio.c | 15 +++++- 6 files changed, 47 insertions(+), 34 deletions(-) diff --git a/board/emsdp/drivers/ip/designware/sdio/dw_sdio_obj.c b/board/emsdp/drivers/ip/designware/sdio/dw_sdio_obj.c index f3ed37040..998d32b99 100644 --- a/board/emsdp/drivers/ip/designware/sdio/dw_sdio_obj.c +++ b/board/emsdp/drivers/ip/designware/sdio/dw_sdio_obj.c @@ -91,7 +91,7 @@ static void dw_sdio_0_install(void) dw_sdio_ctrl_ptr->reg_base = (void *) EMSDP_SDIO_BASE; dw_sdio_ctrl_ptr->intno = EMSDP_SDIO_INTR; - dw_sdio_ctrl_ptr->ref_clk = 200000000; + dw_sdio_ctrl_ptr->ref_clk = EMSDP_REF_CLOCK; dw_sdio_ctrl_ptr->fifo_depth = 128; dw_sdio_ptr->open = dw_sdio_0_open; diff --git a/board/iotdk/drivers/ip/designware/sdio/dw_sdio_obj.c b/board/iotdk/drivers/ip/designware/sdio/dw_sdio_obj.c index 104488f68..ba5406433 100644 --- a/board/iotdk/drivers/ip/designware/sdio/dw_sdio_obj.c +++ b/board/iotdk/drivers/ip/designware/sdio/dw_sdio_obj.c @@ -31,7 +31,6 @@ #include "embARC_error.h" #include "iotdk_hardware.h" - #include "ip/designware/sdio/dw_sdio.h" #include "dw_sdio_obj.h" @@ -95,7 +94,7 @@ static void dw_sdio_0_install(void) dw_sdio_ctrl_ptr->reg_base = (void *) BASE_ADDR_SDIO; dw_sdio_ctrl_ptr->intno = INTNO_SDIO; - dw_sdio_ctrl_ptr->ref_clk = 100000000; + dw_sdio_ctrl_ptr->ref_clk = CLK_CPU; dw_sdio_ctrl_ptr->fifo_depth = 128; dw_sdio_ptr->open = dw_sdio_0_open; diff --git a/board/iotdk/drivers/sysconf/sysconf.c b/board/iotdk/drivers/sysconf/sysconf.c index ff4c95be6..cc0de8670 100644 --- a/board/iotdk/drivers/sysconf/sysconf.c +++ b/board/iotdk/drivers/sysconf/sysconf.c @@ -131,6 +131,8 @@ int32_t pll_fout_config(uint32_t freq) eflash_clk_div(1); } + sdio_clk_divisor(1); + return 0; } @@ -204,7 +206,7 @@ void apb_clk_disable(uint8_t dev) */ void sdio_clk_divisor(uint8_t div) { - sysconf_reg_ptr->SDIO_REFCLK_DIV; + sysconf_reg_ptr->SDIO_REFCLK_DIV = div; } diff --git a/device/ip/designware/sdio/dw_sdio.c b/device/ip/designware/sdio/dw_sdio.c index e20510b16..126865674 100644 --- a/device/ip/designware/sdio/dw_sdio.c +++ b/device/ip/designware/sdio/dw_sdio.c @@ -27,7 +27,6 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * --------------------------------------------- */ - #include "embARC_toolchain.h" #include "embARC_error.h" #include "arc_exception.h" @@ -60,7 +59,10 @@ Inline void dw_sdio_fifo_read_poll(DW_SDIO_CTRL_PTR sdio, uint32_t *buf, uint32_ uint32_t i; while (size) { - len = dw_sdio_reg_read(sdio, DWSDIO_REG_STATUS); + do { + len = dw_sdio_reg_read(sdio, DWSDIO_REG_STATUS); + } while (len & DWSDIO_STATUS_FIFO_EMPTY); + len = (len & DWSDIO_STATUS_MASK_FIFO) >> DWSDIO_STATUS_BIT_FIFO; len = min(size, len); @@ -96,8 +98,11 @@ Inline void dw_sdio_fifo_write_poll(DW_SDIO_CTRL_PTR sdio, uint32_t *buf, uint32 uint32_t i; uint32_t fifo_depth = sdio->fifo_depth; - while (size) { - len = dw_sdio_reg_read(sdio, DWSDIO_REG_STATUS); + while (size) { + do { + len = dw_sdio_reg_read(sdio, DWSDIO_REG_STATUS); + } while (len & DWSDIO_STATUS_FIFO_FULL); + len = fifo_depth - ((len & DWSDIO_STATUS_MASK_FIFO) >> DWSDIO_STATUS_BIT_FIFO); len = min(size, len); @@ -188,7 +193,6 @@ static int32_t dw_sdio_bus_freq_set(DW_SDIO_CTRL_PTR sdio, uint32_t card_number, dw_sdio_reg_write(sdio, DWSDIO_REG_CLKSRC, 0); dw_sdio_reg_write(sdio, DWSDIO_REG_CLKDIV, div); - dw_sdio_reg_write(sdio, DWSDIO_REG_CMD, DWSDIO_CMD_PRV_DAT_WAIT | DWSDIO_CMD_UPD_CLK | DWSDIO_CMD_START | DWSDIO_CMD_USE_HOLD_REG); @@ -284,7 +288,6 @@ static int32_t dw_sdio_data_transfer_poll(DW_SDIO_CTRL_PTR sdio, SDIO_DATA_PTR d { uint32_t size; uint32_t status; - int32_t ret; uint32_t timeout = 1000; uint32_t start = OSP_GET_CUR_MS(); @@ -295,30 +298,28 @@ static int32_t dw_sdio_data_transfer_poll(DW_SDIO_CTRL_PTR sdio, SDIO_DATA_PTR d if (status & (DWSDIO_INT_DATA_ERR | DWSDIO_INT_DATA_TMO)) { DBG("%s:, data transfer error!\r\n", __func__); - ret = E_SYS; - break; + return E_SYS; + } + + if (status & DWSDIO_INT_DTO) { + return E_OK; } - if (data->flags == SDIO_DATA_READ && (status & DWSDIO_INT_RXDR)) { + if (data->flags == SDIO_DATA_READ && (status & DWSDIO_INT_RXDR) && size) { dw_sdio_fifo_read_poll(sdio, (uint32_t *)data->in, size); + size = 0; dw_sdio_reg_write(sdio, DWSDIO_REG_RINTSTS, DWSDIO_INT_RXDR); - } else if (data->flags == SDIO_DATA_WRITE && (status & DWSDIO_INT_TXDR)) { + } else if (data->flags == SDIO_DATA_WRITE && (status & DWSDIO_INT_TXDR) && size) { dw_sdio_fifo_write_poll(sdio, (uint32_t *)data->out, size); + size = 0; dw_sdio_reg_write(sdio, DWSDIO_REG_RINTSTS, DWSDIO_INT_TXDR); } - if (status & DWSDIO_INT_DTO) { - ret = E_OK; - break; - } - if ((OSP_GET_CUR_MS() - start) > timeout) { DBG("%s: timeout on data transfer\r\n", __func__); return E_TMOUT; } } - - return ret; } void dw_sdio_isr(DEV_SDIO *sdio_obj, void *ptr) @@ -419,7 +420,6 @@ int32_t dw_sdio_cmd_poll(DEV_SDIO *sdio_obj, SDIO_CMD_PTR cmd, SDIO_DATA_PTR dat return E_SYS; } - if (cmd->resp_type & SDIO_RSP_PRESENT) { if (cmd->resp_type & SDIO_RSP_136) { cmd->resp[0] = dw_sdio_reg_read(sdio, DWSDIO_REG_RESP3); @@ -509,9 +509,9 @@ int32_t dw_sdio_cd(DEV_SDIO *sdio_obj, uint32_t card_number) * Some use 0 (CD pin to GNU) to indicate card detect. */ #ifdef DWSDIO_CARD_DETECT_HIGH_LEVEL - val = dw_sdio_reg_read(sdio, DWSDIO_REG_CDETECT); + val = dw_sdio_reg_read(sdio, DWSDIO_REG_CDETECT); #else - val = ~dw_sdio_reg_read(sdio, DWSDIO_REG_CDETECT); + val = ~dw_sdio_reg_read(sdio, DWSDIO_REG_CDETECT); #endif if ((val & (1 << card_number)) == (1 << card_number)) { @@ -523,13 +523,12 @@ int32_t dw_sdio_cd(DEV_SDIO *sdio_obj, uint32_t card_number) int32_t dw_sdio_wp(DEV_SDIO *sdio_obj, uint32_t card_number) { - uint32_t val; DEV_SDIO_INFO_PTR sdio_info_ptr = &(sdio_obj->sdio_info); DW_SDIO_CTRL_PTR sdio = (DW_SDIO_CTRL_PTR)sdio_info_ptr->sdio_ctrl; - val = dw_sdio_reg_read(sdio, DWSDIO_REG_WRTPRT); + val = dw_sdio_reg_read(sdio, DWSDIO_REG_WRTPRT); if ((val & (1 << card_number)) == (1 << card_number)) { return 1; /* the specific card is write-protect */ @@ -554,8 +553,8 @@ int32_t dw_sdio_control(DEV_SDIO *sdio_obj, SDIO_CTRL_CMD_PTR ctrl_cmd, void *pa dw_sdio_bus_type_set(sdio, card, (uint32_t)param); break; case SDIO_CMD_SET_BUS_FREQ: - dw_sdio_bus_freq_set(sdio, card, (uint32_t)param); - break; + dw_sdio_bus_freq_set(sdio, card, (uint32_t)param); + break; /* \todo add more cmds */ default: ret = E_PAR; diff --git a/device/ip/designware/sdio/dw_sdio_hal.h b/device/ip/designware/sdio/dw_sdio_hal.h index ad45f5043..27c889c63 100644 --- a/device/ip/designware/sdio/dw_sdio_hal.h +++ b/device/ip/designware/sdio/dw_sdio_hal.h @@ -198,6 +198,8 @@ #define DWSDIO_STATUS_BIT_FIFO (17) +#define DWSDIO_STATUS_FIFO_FULL (0x8) +#define DWSDIO_STATUS_FIFO_EMPTY (0x4) #define DWSDIO_STATUS_MASK_FIFO (0x3ffe0000) /* status bit */ @@ -211,9 +213,8 @@ #define DWSDIO_FIFOTH_BIT_DMA_M_SIZE 28 #define DWSDIO_FIFOTH_MASK_DMA_M_SIZE (0x7 << DWSDIO_FIFOTH_BIT_DMA_M_SIZE) #define DWSDIO_FIFOTH_M_SIZE(x) ((x) << DWSDIO_FIFOTH_BIT_DMA_M_SIZE) -#define DWSDIO_FIFOTH_TX_WMASK(x) ((x)) -#define DWSDIO_FIFOTH_RX_WMASK(x) ((x) << DWSDIO_FIFOTH_BIT_RX_WMARK) - +#define DWSDIO_FIFOTH_TX_WMASK(x) ((x)) +#define DWSDIO_FIFOTH_RX_WMASK(x) ((x) << DWSDIO_FIFOTH_BIT_RX_WMARK) /* interrupt status bit */ #define DWSDIO_INT_CAD (0x1U) //Card Detected @@ -237,7 +238,6 @@ DWSDIO_INT_FRUN | DWSDIO_INT_DCRC) #define DWSDIO_INT_DATA_TMO (DWSDIO_INT_DRTO | DWSDIO_INT_HTO) - -#define DWSDIO_ENUMERATION_FREQ (400000) /* 400 Khz for card enumeration */ +#define DWSDIO_ENUMERATION_FREQ (400000) /* 400 Khz for card enumeration */ #endif /* _DW_SDIO_HAL_H_ */ \ No newline at end of file diff --git a/middleware/fatfs/source/diskdrv/ff_sdcard_sdio.c b/middleware/fatfs/source/diskdrv/ff_sdcard_sdio.c index 344832eec..90da42885 100644 --- a/middleware/fatfs/source/diskdrv/ff_sdcard_sdio.c +++ b/middleware/fatfs/source/diskdrv/ff_sdcard_sdio.c @@ -483,7 +483,7 @@ static int32_t sdio_write_blocks(FS_SDCARD_SDIO_CTRL_PTR sd_dev, const void *buf if (sd_dev->card_info.version & SDCARD_CT_SDC) { cmd.cmdidx = CMD55; cmd.resp_type = SDIO_RSP_R1; - cmd.arg = 0; + cmd.arg = sd_dev->card_info.rca << 16;; ret = sd_host->cmd_poll(&cmd, NULL); @@ -516,6 +516,19 @@ static int32_t sdio_write_blocks(FS_SDCARD_SDIO_CTRL_PTR sd_dev, const void *buf return ret; } + if (blkcnt > 1) { + cmd.cmdidx = CMD12; + cmd.arg = 0; + cmd.resp_type= SDIO_RSP_R1b; + + ret = sd_host->cmd_poll(&cmd, NULL); + if (ret < 0 ) { + DBG("fail to send stop cmd\r\n"); + return ret; + } + } + + return blkcnt; }