logi-wishbone: missing synchronizers in gpmc_wishbone_wrapper?

[jcdevel]

Hi experts,

I am trying to get familiar with the Logibone studying the logi-wishbone project. In the gpmc_wishbone_wrapper module there is a clock domain crossing between the GPMC and the Wishbone, but the destination domain only presents a single FF before the signals are sent to the Wishbone interconnect network. Should not it use a dual FF synchronizer to avoid metastability?

In the same file, the attribute IOB of iob_writedata is set to true. After reading Xilinx documentation, I understand that this attribute is used to pull a register into an IOB cell, but iob_writedata is not a registered signal (it connects directly to the three-state buffer in the IO pad). Should not the attribute apply to a registered signal to have any effect?

I apologize if my comments are not issues at all. I am not an expert in hardware design and sometimes I find Xilinx documentation overwhelming (even confusing), so I might miss some details.

Thank you,
JC

[fpga-logi-fam]

Hi,

you are right about the dual flop synchronizer problem that is implemented
as a single flop synchronizer. It would be better to have dual flop to
avoid metastability (that i already observed) but this has a direct impact
on the read access latency (need to add one gpmc clock cycle on reads. This
is something we need to investigate as a tade-off between access speed and
design stability.

iob_write_data is registered when using the gpmc in synchronous mode :

iob_dq_g: for i in 0 to 15 generate
begin
iob_dq_iob: IOBUF
generic map (DRIVE => 12, IOSTANDARD => "LVTTL", SLEW => "SLOW")
port map ( O => iob_writedata(i), IO => gpmc_ad(i), I =>
iob_readdata(i), T => iob_dq_hiz);
end generate;

the iob attribute is not really used because the IOBUF is instantiated
explicitly in the code.

Thanks for your feedback, i'll let you know about the dual flop
synchronizer.

Regards,

Jonathan Piat

On Sat, Feb 21, 2015 at 8:04 PM, jcdevel [email protected] wrote:

Hi experts,

I am trying to get familiar with the Logibone studying the logi-wishbone
project. In the gpmc_wishbone_wrapper module there is a clock domain
crossing between the GPMC and the Wishbone, but the destination domain only
presents a single FF before the signals are sent to the Wishbone
interconnect network. Should not it use a dual FF synchronizer to avoid
metastability?

In the same file, the attribute IOB of iob_writedata is set to true. After
reading Xilinx documentation, I understand that this attribute is used to
pull a register into an IOB cell, but iob_writedata is not a registered
signal (it connects directly to the three-state buffer in the IO pad).
Should not the attribute apply to a registered signal to have any effect?

I apologize if my comments are not issues at all. I am not an expert in
hardware design and sometimes I find Xilinx documentation overwhelming
(even confusing), so I might miss some details.

Thank you,
JC

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