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<div class="content-title">
<a href="https://fritzm.github.io/cpu-debug-6.html"><h1>PDP-11/45: CPU debug VI - RK11 NPRs and first disk boot!</h1></a>
Sun 14 May 2017
by <a class="url fn" href="https://fritzm.github.io/author/fritz-mueller.html">Fritz Mueller</a>
</div>
<div><p>Took a little of time to sort through BC11 cables to find a good one for drive interfacing, but in the end I
found one that worked okay and got the seek tester code from the previous post working reliably. At this
point I mounted one of the recently cleaned RK05 packs, but found that the M9301 bootstrap would hang the bus
on the first read operation.</p>
<p>A little scoping around on the RK11-C showed that it was asserting NPR to the processor, but never receiving
NPG. A quick check of NPG continuity on the backplane showed a missing jumper on one slot of my DD11-D.
Wrapped this on, verified NPG continuity all the way out to the RK11, but still no joy. Turns out the CPU
is not asserting NPG at all.</p>
<p>Threw the CPU UBC card out on extenders and had a go at chasing though the NPG logic with a logic probe.
Turns out to be a failed 8881 bus driver for NPG at the end of the line (E55 on KB11-A drawing UBCD). Pulled,
socketed, replaced.</p>
<p>After this, the CPU was asserting NPG, but the signaling still looked a little squirrelly. Turns out that
there are jumpers (W1-W5) on the M9301 bootstrap terminator that need to be installed to provide grant
pull-ups when they are not otherwise provided internally by the processor (and the 11/45 is one such
case). After installing the jumpers, NPG signaling looked solid.</p>
<p>Tried mounting a booting a few packs. Packs marked as having RT-11 would run for a short while and then hang.
But an RKDP pack <em>successfully booted!</em> Wow, that feels pretty good after about two years of working
seriously on this restoration. :-)</p>
<p>Going to stop here on a high note, and pick up trying to get a good RT-11 boot next time.</p>
<p><img src='/images/pdp11/rkdp-boot_thumbnail_tall.jpg' title='First boot off disk -- RKDP diagnostics pack!' onclick='pswipe("pdp11",57);'/></p></div>
<hr />
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<a href="https://fritzm.github.io/rk05-2.html"><h1>PDP-11/45: RK05 II - Head Load and Servo Calibration</h1></a>
Sun 09 April 2017
by <a class="url fn" href="https://fritzm.github.io/author/fritz-mueller.html">Fritz Mueller</a>
</div>
<div><p>Okay, disassembled and cleaned a few RK05 cartidges, following advice from the vcfed forum and cctalk
mailing list (cleanroom gloves and wipes, 99% anyhydrous isoprop). Was surprised to find foam inside
the hub on the disks (see pic below) but folks on vcfed advise that it is high-density polyeurethane
and not subject to decay to the same extent as the other DEC foams, so I left it be.</p>
<p>Mounted one of the cleaned packs, and let it spin in the drive for a few hours with head load disabled
in order to get a good flush on the air filtration system, let the various bearings on the drive loosen up,
and make sure the replacement head retract batteries got a good charge. Drive ran quiet and balanced.</p>
<p>After that, took a deep breath and let the heads load -- no crash! Proceeded to work through the dynamic
off-line calibration procedure for the head positioning servo system. This involves jumpering the control
electronics on the drive to strobe simulated cylinder addresses from the sector counter. That provides
a convenient source of oscillating seeks that can be used to calibrate the servos. Video here shows head
load, a four cylinder oscillating seek, and a scope trace of the resulting sine position output of the electro-optical carriage position sensor:</p>
<p><span class="videobox">
<iframe width="640" height="390"
src='https://www.youtube.com/embed/b6p2ri-uM9c?rel=0'
frameborder='0' webkitAllowFullScreen
mozallowfullscreen allowFullScreen>
</iframe>
</span></p>
<p>Surprisingly, after about thirty years of non-operation, all of the servo calibration was within specified
error bars, so no adjustments were necessary! At this point I decided to go for broke, cabled the drive
to the RK11-C controller and attempted a boot. Some cncouraging front panel indicator activity, but soon
halted with a seek error flagged in RKER. Not too surprising.</p>
<p>Okay, on to debugging the drive online with the controller, then. Worked up the following test code, inspired
by something in one of the RK05 SPI workbooks. This reads two cylinder addresses from the high and low
bytes of the front panel switches, and instructs the controller to instruct the drive to seek alternately
between them:</p>
<table class="highlighttable"><tr><td class="linenos"><div class="linenodiv"><pre> 1
2
3
4
5
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7
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17
18
19
20
21
22
23</pre></div></td><td class="code"><div class="highlight"><pre><span></span> <span class="nt">177570</span> <span class="nt">SW</span><span class="o">=</span><span class="nt">177570</span>
<span class="nt">177400</span> <span class="nt">RKDS</span><span class="o">=</span><span class="nt">177400</span>
<span class="nt">177404</span> <span class="nt">RKCS</span><span class="o">=</span><span class="nt">177404</span>
<span class="nt">177412</span> <span class="nt">RKDA</span><span class="o">=</span><span class="nt">177412</span>
<span class="nt">000000</span> <span class="p">.</span><span class="nc">ASECT</span>
<span class="nt">001000</span> <span class="o">.=</span><span class="nt">1000</span>
<span class="nt">001000</span> <span class="nt">012706</span> <span class="nt">000700</span> <span class="nt">START</span><span class="o">:</span> <span class="nt">MOV</span> <span class="p">#</span><span class="nn">700</span><span class="o">,</span><span class="nt">SP</span> <span class="o">;</span><span class="nt">INIT</span> <span class="nt">STACK</span> <span class="nt">POINTER</span>
<span class="nt">001004</span> <span class="nt">013700</span> <span class="nt">177570</span> <span class="nt">L0</span><span class="o">:</span> <span class="nt">MOV</span> <span class="o">@</span><span class="p">#</span><span class="nn">SW</span><span class="o">,</span><span class="nt">R0</span> <span class="o">;</span><span class="nt">RETRIEVE</span> <span class="nt">SWITCHES</span>
<span class="nt">001010</span> <span class="nt">000300</span> <span class="nt">SWAB</span> <span class="nt">R0</span> <span class="o">;</span><span class="nt">LOWER</span> <span class="nt">SWITCHES</span> <span class="nt">TO</span> <span class="nt">UPPER</span>
<span class="nt">001012</span> <span class="nt">004767</span> <span class="nt">000012</span> <span class="nt">JSR</span> <span class="nt">PC</span><span class="o">,</span><span class="nt">SEEK</span> <span class="o">;</span><span class="nt">DO</span> <span class="nt">THE</span> <span class="nt">SEEK</span>
<span class="nt">001016</span> <span class="nt">013700</span> <span class="nt">177570</span> <span class="nt">MOV</span> <span class="o">@</span><span class="p">#</span><span class="nn">SW</span><span class="o">,</span><span class="nt">R0</span> <span class="o">;</span><span class="nt">RETRIEVE</span> <span class="nt">SWITCHES</span>
<span class="nt">001022</span> <span class="nt">004767</span> <span class="nt">000002</span> <span class="nt">JSR</span> <span class="nt">PC</span><span class="o">,</span><span class="nt">SEEK</span> <span class="o">;</span><span class="nt">DO</span> <span class="nt">THE</span> <span class="nt">SEEK</span>
<span class="nt">001026</span> <span class="nt">000766</span> <span class="nt">BR</span> <span class="nt">L0</span> <span class="o">;</span><span class="nt">START</span> <span class="nt">OVER</span>
<span class="nt">001030</span> <span class="nt">042700</span> <span class="nt">000377</span> <span class="nt">SEEK</span><span class="o">:</span> <span class="nt">BIC</span> <span class="p">#</span><span class="nn">377</span><span class="o">,</span><span class="nt">R0</span> <span class="o">;</span><span class="nt">MASK</span> <span class="nt">OFF</span> <span class="nt">LOWER</span> <span class="nt">BYTE</span>
<span class="nt">001034</span> <span class="nt">072027</span> <span class="nt">177775</span> <span class="nt">ASH</span> <span class="p">#</span><span class="nn">-3</span><span class="o">,</span><span class="nt">R0</span> <span class="o">;</span><span class="nt">SHIFT</span> <span class="nt">OVER</span> <span class="nt">TO</span> <span class="nt">CYL</span> <span class="nt">ADDRESS</span>
<span class="nt">001040</span> <span class="nt">105737</span> <span class="nt">177404</span> <span class="nt">L1</span><span class="o">:</span> <span class="nt">TSTB</span> <span class="o">@</span><span class="p">#</span><span class="nn">RKCS</span> <span class="o">;</span><span class="nt">CHECK</span> <span class="nt">RKCS</span> <span class="nt">RDY</span> <span class="nt">BIT</span>
<span class="nt">001044</span> <span class="nt">100375</span> <span class="nt">BPL</span> <span class="nt">L1</span> <span class="o">;</span><span class="nt">LOOP</span> <span class="nt">IF</span> <span class="nt">BUSY</span>
<span class="nt">001046</span> <span class="nt">032737</span> <span class="nt">000100</span> <span class="nt">177400</span> <span class="nt">L2</span><span class="o">:</span> <span class="nt">BIT</span> <span class="p">#</span><span class="nn">100</span><span class="o">,@</span><span class="p">#</span><span class="nn">RKDS</span> <span class="o">;</span><span class="nt">CHECK</span> <span class="nt">RKDS</span> <span class="nt">ARDY</span> <span class="nt">BIT</span>
<span class="nt">001054</span> <span class="nt">001774</span> <span class="nt">BEQ</span> <span class="nt">L2</span> <span class="o">;</span><span class="nt">LOOP</span> <span class="nt">IF</span> <span class="nt">BUSY</span>
<span class="nt">001056</span> <span class="nt">010037</span> <span class="nt">177412</span> <span class="nt">MOV</span> <span class="nt">R0</span><span class="o">,@</span><span class="p">#</span><span class="nn">RKDA</span> <span class="o">;</span><span class="nt">WRITE</span> <span class="nt">SEEK</span> <span class="nt">TARGET</span> <span class="nt">TO</span> <span class="nt">RKDA</span>
<span class="nt">001062</span> <span class="nt">012737</span> <span class="nt">000011</span> <span class="nt">177404</span> <span class="nt">MOV</span> <span class="p">#</span><span class="nn">11</span><span class="o">,@</span><span class="p">#</span><span class="nn">RKCS</span> <span class="o">;</span><span class="nt">WRITE</span> <span class="nt">SEEK</span> <span class="nt">CMD</span> <span class="o">+</span> <span class="nt">GO</span> <span class="nt">TO</span> <span class="nt">RKCS</span>
<span class="nt">001070</span> <span class="nt">000207</span> <span class="nt">RTS</span> <span class="nt">PC</span> <span class="o">;</span><span class="nt">RETURN</span> <span class="nt">TO</span> <span class="nt">CALLER</span>
<span class="nt">001000</span> <span class="p">.</span><span class="nc">END</span> <span class="nt">START</span>
</pre></div>
</td></tr></table>
<p>At first this code was generating no seek activity on the drive. Decided to try swapping out the BC11-A
drive cable, and that produced some limited success -- drive seeks, but some bits of the cylinder address
are still apparently not making it across the cable.</p>
<p>The BC11-A cables are problematic. They seem flaky and fragile, and many of my spares seem bad. Any given
cable may beep out fine on the bench, and yet fail consistently in use... It looks like what's up next is a
voyage through my box of spares, swapping in cables looking for one that works reliably. Failing that, I'll
need work on some sort of modern replacement, since original BC11-A in good shape are getting hard to find.
It will be sad if at the end of this journey I can't boot the machine for mere lack of a good cable between
the drives and controller!</p>
<p><img src='/images/pdp11/rk05-cartridge-foam_thumbnail_tall.jpg' title='Foam inside the hub of an RK05 pack -- could be bad news if this is decaying like other DEC foam...' onclick='pswipe("pdp11",54);'/>
<img src='/images/pdp11/rk05-running_thumbnail_tall.jpg' title='RK05 running offline from controller; pack spinning and heads loaded' onclick='pswipe("pdp11",55);'/>
<img src='/images/pdp11/BC11-woes_thumbnail_tall.jpg' title='A box of BC11-A cables to be sorted through...' onclick='pswipe("pdp11",56);'/></p></div>
<hr />
</div>
<div class='article'>
<div class="content-title">
<a href="https://fritzm.github.io/rk11-4.html"><h1>PDP-11/45: RK11 IV</h1></a>
Sat 01 April 2017
by <a class="url fn" href="https://fritzm.github.io/author/fritz-mueller.html">Fritz Mueller</a>
</div>
<div><p>A quick note: rejumpered a spare M105 address decoder, and swapped it in for the one that was in the RK11. SSYN waveform is greatly improved (see before/after shots below), so looks like a bad driver on
the original M105.</p>
<p><a href="https://fritzm.github.io/images/pdp11/rkcs-fixed.jpg"><img src='/images/pdp11/rkcs-fixed_thumbnail_tall.jpg'/></a>
<a href="https://fritzm.github.io/images/pdp11/rkcs-really-fixed.jpg"><img src='/images/pdp11/rkcs-really-fixed_thumbnail_tall.jpg'/></a></p></div>
<hr />
</div>
<div class='article'>
<div class="content-title">
<a href="https://fritzm.github.io/rk05.html"><h1>PDP-11/45: RK05</h1></a>
Sun 19 March 2017
by <a class="url fn" href="https://fritzm.github.io/author/fritz-mueller.html">Fritz Mueller</a>
</div>
<div><p>Started going through the two RK05 drives. Lots of work to remove and clean up all the decaying foam.
Replaced the emergency head retract NiCd battery packs on both units. They were both slightly leaky, but
luckily neither had made a big mess.</p>
<p>Air filter elbows are intact on both units, and still slightly flexible, though they do have a white
powdery coating where the material is degenerating. Cleaned up okay with some warm soapy water and a
toothbrush. I'm sure these will continue to decompose/decay, however, and in the long term having loose
particulates develop inside the elbow seems a certain recipe for a head crash. I may explore the possibility
of 3D printing some sort of modern replacement for these.</p>
<p>Heads on the first unit look to be in decent shape, but some oxide buildup. In the second unit, the
carriage was not parked, so the heads were in contact with each other. They don't look damaged from a
preliminary inspection, but this head pair has considerably more oxide. Before and after cleaning shots of
the upper and lower heads on the first unit below.</p>
<p>Pulled the H743 power supplies and reformed the larger electrolytics. After this, both power supplies
powered up fine, though the -15V regulator on the first unit was trimmed very hot (-23 or so). Trimmed this
down, put the supply back in the first unit and powered up. Under load, the -15V regulator drooped to -8,
and a pico fuse on the +15V supply blew immediately.</p>
<p>Swapped in the -15V regulator from the second supply, which was not trimmed hot, and replaced the blown
pico fuse. Now under load the supply held without drooping, and the +15V pico did not reblow. So looks
like a bad -15V regulator. Put a few 723 regulator ICs on order in advance of debugging this.</p>
<p>After getting the power supply in the first unit up and going, blower powers on, power indicator lights, and
after about three seconds the door safety relay clunks and load indicator lights. Write protect indicator
toggles with panel switch presses per expectation. If the cartridge-on switch is depressed manually and the
load toggle is hit, the spindle motor spins up and runs smoothly.</p>
<p>There are some significant abrasions on the lower panel of the first unit under both the spindle and spindle
motor axles. It looks like a spacer button which is intended to hold off the lower panel has decayed; will
need to improvise some sort of replacement.</p>
<p><img src='/images/pdp11/rk05_thumbnail_tall.jpg' title='RK05 drive internals' onclick='pswipe("pdp11",47);'/>
<img src='/images/pdp11/h743_thumbnail_tall.jpg' title='H743 power supply pulled and on bench' onclick='pswipe("pdp11",48);'/>
<img src='/images/pdp11/rk05-lower-before_thumbnail_tall.jpg' title='First RK05 lower head before cleaning' onclick='pswipe("pdp11",49);'/>
<img src='/images/pdp11/rk05-lower-after_thumbnail_tall.jpg' title='First RK05 lower head after cleaning' onclick='pswipe("pdp11",50);'/>
<img src='/images/pdp11/rk05-upper-before_thumbnail_tall.jpg' title='First RK05 upper head before cleaning' onclick='pswipe("pdp11",51);'/>
<img src='/images/pdp11/rk05-upper-after_thumbnail_tall.jpg' title='First RK05 upder head after cleaning' onclick='pswipe("pdp11",52);'/>
<img src='/images/pdp11/lower-cover-abrasions_thumbnail_tall.jpg' title='Abrasions on first RK05 lower cover, from contact with spindle motor shafts' onclick='pswipe("pdp11",53);'/></p></div>
<hr />
</div>
<div class='article'>
<div class="content-title">
<a href="https://fritzm.github.io/rk11-3.html"><h1>PDP-11/45: RK11 III</h1></a>
Sun 26 February 2017
by <a class="url fn" href="https://fritzm.github.io/author/fritz-mueller.html">Fritz Mueller</a>
</div>
<div><p>Okay, the M9202 bus jumper arrived, and like the 2-foot BC11 cable, the occasional timeouts go away when this
is installed. Hantek digital scope also arrived, so I decided to throw it on the backplane for a closer
look at the SSYN and timeout signals. The results were pretty interesting. Here's a capture of an RKCS
access triggering a timeout glitch with the M902. The yellow trace is BUS A SSYN L (taken from C12J1 on the
11/45 backplane), and the blue trace is UBCB TIMEOUT (1) H (taken from D12U1):</p>
<p><img src='/images/pdp11/rkcs-timeout.jpg'/></p>
<p>What's interesting is that with the M9202 in place, the SSYN waveform shape on RCKS accesses is <strong>not</strong>
significantly different -- and the timeout glitch still ocurrs from time to time, but at a reduced amplitude:</p>
<p><img src='/images/pdp11/rkcs-glitch.jpg'/></p>
<p>If the problem had been one solely of lumped loads on the bus, I would have expected the fix to manifest
as a waveform difference, and for the glitches to have disappeared. These observations steered me back
toward my original (less plausible?) supposition -- the the 74123 one-shot in the Unibus timeout logic in the
CPU was flaky, and particularly sensitive for some reason to SSYN pulses of 568ns. Adding some extra bus
length via a BC11 or the M9202 moves the timing by a nano or two off the troublesome period, and reduces the
magnitude of the glitches.</p>
<p>So I went ahead and clipped out the suspect 74123, and put in a socket and a fresh part. Bingo! Timeout
glitching was eliminated entirely. Here's a trace after the 74123 was replaced. This trace looks different
because with the timeout glitch fixed, I could no longer use it to trigger the scope -- instead I had to
trigger on the trailing edge of SSYN, so we see both RKCS and non-RKCS bus cycles. In any case, the timeout
glitching is now gone:</p>
<p><img src='/images/pdp11/rkcs-fixed.jpg'/></p>
<p>So that's a nice result -- I think the new scope is going to be pretty useful. The rather extreme sawtooth
on the falling edge of SSYN on RKCS accesses still looks pretty bad to me, even though it is no longer
triggering timeouts. I might try swapping out the M105 address decoder on the RK11, which generates this
signal, and see if the integrity here is improved. All for now!</p></div>
<hr />
</div>
<div class='article'>
<div class="content-title">
<a href="https://fritzm.github.io/rk11-2.html"><h1>PDP-11/45: RK11 II</h1></a>
Mon 20 February 2017
by <a class="url fn" href="https://fritzm.github.io/author/fritz-mueller.html">Fritz Mueller</a>
</div>
<div><p>Okay, moving on with the RK11-C debug, the following bit of test code is modeled after that part of the
ZRKJE0 diagnotic that is trapping out:</p>
<table class="highlighttable"><tr><td class="linenos"><div class="linenodiv"><pre> 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24</pre></div></td><td class="code"><div class="highlight"><pre><span></span> <span class="nt">177404</span> <span class="nt">RKCS</span><span class="o">=</span><span class="nt">177404</span>
<span class="nt">000000</span> <span class="p">.</span><span class="nc">ASECT</span>
<span class="nt">001000</span> <span class="o">.=</span><span class="nt">1000</span>
<span class="nt">001000</span> <span class="nt">012706</span> <span class="nt">000770</span> <span class="nt">START</span><span class="o">:</span> <span class="nt">MOV</span> <span class="p">#</span><span class="nn">770</span><span class="o">,</span><span class="nt">SP</span> <span class="o">;</span><span class="nt">INIT</span> <span class="nt">STACK</span> <span class="nt">POINTER</span>
<span class="nt">001004</span> <span class="nt">005000</span> <span class="nt">CLR</span> <span class="nt">R0</span> <span class="o">;</span><span class="nt">INIT</span> <span class="nt">TRAP</span> <span class="nt">BASE</span>
<span class="nt">001006</span> <span class="nt">012701</span> <span class="nt">000002</span> <span class="nt">MOV</span> <span class="p">#</span><span class="nn">2</span><span class="o">,</span><span class="nt">R1</span> <span class="o">;</span><span class="nt">INIT</span> <span class="nt">TRAP</span> <span class="nt">DEST</span>
<span class="nt">001012</span> <span class="nt">010120</span> <span class="nt">L1</span><span class="o">:</span> <span class="nt">MOV</span> <span class="nt">R1</span><span class="o">,(</span><span class="nt">R0</span><span class="o">)+</span> <span class="o">;</span><span class="nt">STORE</span> <span class="nt">TRAP</span> <span class="nt">DEST</span>
<span class="nt">001014</span> <span class="nt">005020</span> <span class="nt">CLR</span> <span class="o">(</span><span class="nt">R0</span><span class="o">)+</span> <span class="o">;</span><span class="nt">AND</span> <span class="nt">STORE</span> <span class="nt">HALT</span> <span class="nt">AT</span> <span class="nt">TRAP</span> <span class="nt">DEST</span>
<span class="nt">001016</span> <span class="nt">062701</span> <span class="nt">000004</span> <span class="nt">ADD</span> <span class="p">#</span><span class="nn">4</span><span class="o">,</span><span class="nt">R1</span> <span class="o">;</span><span class="nt">UPDATE</span> <span class="nt">TRAP</span> <span class="nt">DEST</span>
<span class="nt">001022</span> <span class="nt">020600</span> <span class="nt">CMP</span> <span class="nt">SP</span><span class="o">,</span><span class="nt">R0</span> <span class="o">;</span><span class="nt">ALL</span> <span class="nt">TRAPS</span> <span class="nt">INITD</span><span class="o">?</span>
<span class="nt">001024</span> <span class="nt">001372</span> <span class="nt">BNE</span> <span class="nt">L1</span> <span class="o">;</span><span class="nt">IF</span> <span class="nt">NOT</span><span class="o">,</span> <span class="nt">KEEP</span> <span class="nt">GOING</span>
<span class="nt">001026</span> <span class="nt">005002</span> <span class="nt">CLR</span> <span class="nt">R2</span> <span class="o">;</span><span class="nt">INIT</span> <span class="nt">MAIN</span> <span class="nt">ITERATION</span> <span class="nt">COUNT</span>
<span class="nt">001030</span> <span class="nt">005202</span> <span class="nt">L2</span><span class="o">:</span> <span class="nt">INC</span> <span class="nt">R2</span> <span class="o">;</span><span class="nt">INC</span> <span class="nt">MAIN</span> <span class="nt">ITERATION</span> <span class="nt">COUNT</span>
<span class="nt">001032</span> <span class="nt">010237</span> <span class="nt">177570</span> <span class="nt">MOV</span> <span class="nt">R2</span><span class="o">,@</span><span class="p">#</span><span class="nn">177570</span> <span class="o">;</span><span class="nt">UPDATE</span> <span class="nt">DISPLAY</span> <span class="nt">REG</span>
<span class="nt">001036</span> <span class="nt">012700</span> <span class="nt">177404</span> <span class="nt">MOV</span> <span class="p">#</span><span class="nn">RKCS</span><span class="o">,</span><span class="nt">R0</span> <span class="o">;</span><span class="nt">GET</span> <span class="nt">RKCS</span> <span class="nt">ADDRESS</span>
<span class="nt">001042</span> <span class="nt">012710</span> <span class="nt">007560</span> <span class="nt">MOV</span> <span class="p">#</span><span class="nn">7560</span><span class="o">,</span><span class="p">@</span><span class="k">R0</span> <span class="p">;</span><span class="nt">SET</span> <span class="nt">RESET</span> <span class="nt">CTRLR</span> <span class="nt">CMD</span>
<span class="nt">001046</span> <span class="nt">005210</span> <span class="nt">INC</span> <span class="p">@</span><span class="k">R0</span> <span class="p">;</span><span class="nt">SET</span> <span class="nt">GO</span> <span class="nt">BIT</span>
<span class="nt">001050</span> <span class="nt">005005</span> <span class="nt">CLR</span> <span class="nt">R5</span> <span class="o">;</span><span class="nt">INIT</span> <span class="nt">CHECK</span> <span class="nt">COUNT</span>
<span class="nt">001052</span> <span class="nt">105710</span> <span class="nt">L3</span><span class="o">:</span> <span class="nt">TSTB</span> <span class="p">@</span><span class="k">R0</span> <span class="p">;</span><span class="nt">CHECK</span> <span class="nt">DONE</span> <span class="nt">BIT</span>
<span class="nt">001054</span> <span class="nt">100765</span> <span class="nt">BMI</span> <span class="nt">L2</span> <span class="o">;</span><span class="nt">IF</span> <span class="nt">SET</span><span class="o">,</span> <span class="nt">NEXT</span> <span class="nt">MAIN</span> <span class="nt">LOOP</span>
<span class="nt">001056</span> <span class="nt">005205</span> <span class="nt">INC</span> <span class="nt">R5</span> <span class="o">;</span><span class="nt">OTHERWISE</span> <span class="nt">INC</span> <span class="nt">CHECK</span> <span class="nt">COUNT</span>
<span class="nt">001060</span> <span class="nt">001374</span> <span class="nt">BNE</span> <span class="nt">L3</span> <span class="o">;</span><span class="nt">IF</span> <span class="nt">NOT</span> <span class="nt">EXPIRED</span> <span class="nt">GO</span> <span class="nt">CHECK</span> <span class="nt">AGAIN</span>
<span class="nt">001062</span> <span class="nt">000000</span> <span class="nt">HALT</span> <span class="o">;</span><span class="nt">OTHERWISE</span><span class="o">,</span> <span class="nt">HALT</span> <span class="nt">HERE</span>
<span class="nt">001000</span> <span class="p">.</span><span class="nc">END</span> <span class="nt">START</span>
</pre></div>
</td></tr></table>
<p>Running this code, the error is easily reproduced -- the machine traps on a bus timeout and halts after
anywhere from a few dozen to a few hundred iterations. Put the logic analyzer on MSYN and SSYN at the
back M105 address decode module on the RK11-C backplane and set up a trigger for long bus cycles, but
surprisingly this was not triggering even though the processor was taking a trap 4. Verified that the
trigger itself was working fine by accessing a non-existent memory location from the front panel. Hmmm...</p>
<p>Next step then was to move back to the CPU, and throw the UBC card out on extenders to get more visibility
into the trap. A further surprise here -- the problem went away when the UBC was on the extender! I was
able to run the test code above for hundreds of thousands of iterations without timeouts, and the original
ZRKJE0 diagnostic ran for over half an hour this way.</p>
<p>Took the UBC back off the extender, and the problem re-occurred, so apparently not just a bad seat. Hooked
the logic analyzer up to BUS A MSYN L, BUS A SSYN L, and UBCB TIMEOUT (1) H on the 11/45 backplane. With
this, I was able to capture lots of traces of the failure mode, which looks like this:</p>
<p><img src='/images/pdp11/timeout-trace.jpg'/></p>
<p>Here a glitch on the timeout signal is clearly visible, even though the MSYN/SSYN interval is well under
the bus timeout. The interesting thing is that bus cycles that result in a glitch all have a MSYN/SSYN
interval of 568 nanosceconds, to within a nanosecond. Cycles with a slightly different interval do not
timeout. This jibes with what I saw with the card extender also. As a further verification, replaced
the M920 bus jumper I'd been using with a 2-foot BC11, and the problem disappeared again.</p>
<p>At this point, Don over on the VCFED forum pointed out that the M920 I had been using was discontinued early
on due to negative effects on bus signal integrity, and was replaced with the M9202 (which itself contains 2
feet of BC11). The issue with the M920 is apprently that it provides so little separation that the connected
loads appear to the bus overall as a single lumped load. The M9202 separates the loads on the bus to smear
out reflections and ringing and avoid false triggers. I have tracked down an M9202 on eBay, and have also
put an inexpensive digital storage scope on order so I can start to investigate signal integrity issues like
this that are not apparent on a logic analyzer.</p></div>
<hr />
</div>
<div class='article'>
<div class="content-title">
<a href="https://fritzm.github.io/rk11.html"><h1>PDP-11/45: RK11</h1></a>
Sun 29 January 2017
by <a class="url fn" href="https://fritzm.github.io/author/fritz-mueller.html">Fritz Mueller</a>
</div>
<div><p>Finished up the cleanup and rebuild of the H720E for the RK11-C controller: reformed the big electrolytics
over a couple of days, and swapped out the tantalum filters on the regulator board (one of which had started
to leak) for some replacements. Tantalums of the correct form and value are crazy expensive, and since these
caps (C11-C17, C23) are banked resevoirs on the regulated rails their exact values are not critical. Went
with some aluminum electrolytics instead that worked out to a little more aggregate capacity on each bank.</p>
<p>My H720E is missing its top cover plate, so there was about 40 years worth of accumulated dust in there -- a
lot to clean up! I'm not sure if the cover was customarily left off to facilitate cooling of the regulator
board, or if it is just genuinely missing. Will see if the forums/lists have any wisdom here. Should not be
hard to fab a replacement if it is really supposed to be there.</p>
<p>Routed the inter-cabinet power control wiring, racked the RK11, and cabled everything up. This included
moving the M9301 bootstrap terminator over to slot 0, then rummaging through a box of BC11 bus cables for one
that was both long enough and in decent enough shape to connect the CPU and the RK11. Some of these bus
cables had period-correct labeling (see picture below :-)) Got a good tip off the cctalk mailing list
(thanks, Jerry!) to drape the BC11 with a service loop from the top-rear of the CPU rack, thus avoiding any
entanglement with the rack slides while moving the CPU cabinet in and out.</p>
<p>A 2000pF cap that was flown over the RK11 backplane (+5V to DR BUS DC LO L) had broken free of its pin
connectors; jury-rigged this with some arduino jumpers I had lying around, until I can track down some
appropriate replacement connectors.</p>
<p>Good news is that after this the machine still booted the M9301 bootstrap, and was still able to run and
pass diagnostics loaded via PDP11GUI. So, Unibus still working with the BC11 cable in place and termination
out at the RK11.</p>
<p>Started in with diagnostic ZRKJE0.BIC, which is the controller-only static test. This indicated:</p>
<div class="highlight"><pre><span></span>REGISTER NOT CLEARED
PC REGADD RECVD
002560 177416 040000
</pre></div>
<p>This is the RKDB register, implemented by two M203 R/S flip-flop modules in slots A21 and B21 (see sheet
RK11-C-10 in the RK11-C engineering drawings). Swapped these, and the stuck bit moved to the other half of
of the register, so looks like failed gate. Pulled, socketed, replaced, and diagnostic no longer reports
any stuck bits. Next diagnostic fail is:</p>
<div class="highlight"><pre><span></span>UNEXPECTED TIME OUT AT PC=004300
</pre></div>
<p>This is test #21 of the diagnostic, testing controller reset. Will need to do some reading up on the design
of the controller and the diagnostic source to understand how to troubleshoot it further. All for now!</p>
<p><img src='/images/pdp11/720e-caps_thumbnail_tall.jpg' title='H720e regulator card with refreshed caps' onclick='pswipe("pdp11",42);'/>
<img src='/images/pdp11/rk11-racked_thumbnail_tall.jpg' title='RK11-C controller installed in rack, with temporary jumper hack for flown cap' onclick='pswipe("pdp11",43);'/>
<img src='/images/pdp11/bc11-good_thumbnail_tall.jpg' title='A BC11-A bus cable, with vintage label' onclick='pswipe("pdp11",44);'/>
<img src='/images/pdp11/rk11-back_thumbnail_tall.jpg' title='RK11-C controller from the back, flipchips and cabling visible' onclick='pswipe("pdp11",45);'/>
<img src='/images/pdp11/m203_thumbnail_tall.jpg' title='A failing M203, the cause of a stuck bit in RK11 register RKDB' onclick='pswipe("pdp11",46);'/></p></div>
<hr />
</div>
<div class='article'>
<div class="content-title">
<a href="https://fritzm.github.io/diagnostics-14.html"><h1>PDP-11/45: Diagnostics XIV - CPU, MMU, FPU Complete!</h1></a>
Mon 16 January 2017
by <a class="url fn" href="https://fritzm.github.io/author/fritz-mueller.html">Fritz Mueller</a>
</div>
<div><p>Okay, after socketing in the replacement 74H10 and reseating a few boards, the output from the floating
point diagnostic now looks correct:</p>
<p><span style="font-size: x-small; font-family: monospace; white-space: pre; display: block; line-height: normal; font-weight: bold;">................ ................ ................ ................ .........11..... .........11..... .........11..... .........11.....
................ ................ ................ ................ ..........11.... ..........11.... ..........11.... ..........11....
................ ................ ................ ................ ...........11... ...........11... ...........11... ...........11...
................ ................ ................ ................ ............11.. ............11.. ............11.. ............11..
................ ................ ................ ................ .............11. .............11. .............11. .............11.
................ ................ ................ ................ ..............11 ..............11 ..............11 ..............11
................ ................ ................ ................ ...............1 1..............1 1..............1 1..............1
.......111...... ................ ................ ................ ................ 11.............. 11.............. 11..............
.......1111..... ................ ................ ................ ................ .11............. .11............. .11.............
..........11.... ................ ................ ................ ................ ..11............ ..11............ ..11............
...........11... ................ ................ ................ ................ ...11........... ...11........... ...11...........
............11.. ................ ................ ................ ................ ....11.......... ....11.......... ....11..........
.............11. ................ ................ ................ ................ .....11......... .....11......... .....11.........
..............11 ................ ................ ................ ................ ......11........ ......11........ ......11........
...............1 1............... ................ ................ ................ .......11....... .......11....... .......11.......
................ 11.............. ................ ................ ................ ........11...... ........11...... ........11......
................ .11............. ................ ................ ................ .........11..... .........11..... .........11.....
................ ..11............ ................ ................ ................ ..........11.... ..........11.... ..........11....
................ ...11........... ................ ................ ................ ...........11... ...........11... ...........11...
................ ....11.......... ................ ................ ................ ............11.. ............11.. ............11..
................ .....11......... ................ ................ ................ .............11. .............11. .............11.
................ ......11........ ................ ................ ................ ..............11 ..............11 ..............11
................ .......11....... ................ ................ ................ ...............1 1..............1 1..............1
.......111...... ........11...... ................ ................ ................ ................ 11.............. 11..............
.......1111..... .........11..... ................ ................ ................ ................ .11............. .11.............
..........11.... ..........11.... ................ ................ ................ ................ ..11............ ..11............
...........11... ...........11... ................ ................ ................ ................ ...11........... ...11...........
............11.. ............11.. ................ ................ ................ ................ ....11.......... ....11..........
.............11. .............11. ................ ................ ................ ................ .....11......... .....11.........
..............11 ..............11 ................ ................ ................ ................ ......11........ ......11........
...............1 1..............1 1............... ................ ................ ................ .......11....... .......11.......
................ 11.............. 11.............. ................ ................ ................ ........11...... ........11......
................ .11............. .11............. ................ ................ ................ .........11..... .........11.....
................ ..11............ ..11............ ................ ................ ................ ..........11.... ..........11....
................ ...11........... ...11........... ................ ................ ................ ...........11... ...........11...
................ ....11.......... ....11.......... ................ ................ ................ ............11.. ............11..
................ .....11......... .....11......... ................ ................ ................ .............11. .............11.
................ ......11........ ......11........ ................ ................ ................ ..............11 ..............11
................ .......11....... .......11....... ................ ................ ................ ...............1 1..............1
.......111...... ........11...... ........11...... ................ ................ ................ ................ 11..............
.......1111..... .........11..... .........11..... ................ ................ ................ ................ .11.............
..........11.... ..........11.... ..........11.... ................ ................ ................ ................ ..11............
...........11... ...........11... ...........11... ................ ................ ................ ................ ...11...........
............11.. ............11.. ............11.. ................ ................ ................ ................ ....11..........
.............11. .............11. .............11. ................ ................ ................ ................ .....11.........
..............11 ..............11 ..............11 ................ ................ ................ ................ ......11........
...............1 1..............1 1..............1 1............... ................ ................ ................ .......11.......
................ 11.............. 11.............. 11.............. ................ ................ ................ ........11......
................ .11............. .11............. .11............. ................ ................ ................ .........11.....
................ ..11............ ..11............ ..11............ ................ ................ ................ ..........11....
................ ...11........... ...11........... ...11........... ................ ................ ................ ...........11...
................ ....11.......... ....11.......... ....11.......... ................ ................ ................ ............11..
................ .....11......... .....11......... .....11......... ................ ................ ................ .............11.
................ ......11........ ......11........ ......11........ ................ ................ ................ ..............11
................ .......11....... .......11....... .......11....... ................ ................ ................ ...............1
.......111...... ........11...... ........11...... ........11...... ................ ................ ................ ................
.......1111..... .........11..... .........11..... .........11..... ................ ................ ................ ................
.........11..... .........11..... .........11..... .........11..... ................ ................ ................ ................</span></p>
<p>With this fix, <strong>the machine is now reliably passing the complete suite of CPU, MMU, and FPU diagnostics</strong>
-- a real milestone! I also loaded paper tape BASIC via PDP11GUI, swapped the console over to my VT100, and
played around for a little bit. Working well, and gratifying to see the machine actually running some
software other than diagnostics.</p>
<p>So, now, on to the RK11/RK05 storage subsystem for real. I retrieved the rest of the cabinetry,
cleaned and reassembled it, and inspected and cleaned the cabinet-top 860 power controller in the second
cabinet. This had the usual dead neon indicator and a blown fuse, but was otherwise in good shape. At first
I was puzzled by the relay in the 860 not engaging, but after looking at the schematic is was clear that a
jumper plug on J4 connecting pins 1 and 2 was required. I recalled seeing one such banging around loose
in my spare parts box -- so that's where that came from! Cleaned up the cabinet-top fan in the second
cabinet as well.</p>
<p>I have been running the machine off a GFCI quad box behind my washer/dryer, but at this point there is enough
leakage through filter caps in the various power supplies that the GFCI has started to trip from time to time.
Took a pause to rewire the box -- left two of the outlets GFCI protected for the washer/dryer, and rewired two
as non-protected for use with the PDP-11.</p>
<p><img src='/images/pdp11/cabinets_thumbnail_tall.jpg' title='Cabinet side panels and decorative top panels cleaned and installed' onclick='pswipe("pdp11",40);'/>
<img src='/images/pdp11/basic_thumbnail_tall.jpg' title='Running papertape BASIC, loaded via PDP11GUI' onclick='pswipe("pdp11",41);'/></p></div>
<hr />
</div>
<div class='article'>
<div class="content-title">
<a href="https://fritzm.github.io/diagnostics-13.html"><h1>PDP-11/45: Diagnostics XIII - FP11 FPU, cont.</h1></a>
Thu 24 November 2016
by <a class="url fn" href="https://fritzm.github.io/author/fritz-mueller.html">Fritz Mueller</a>
</div>
<div><p>Have been looking into the FP11 MOD problem in spare moments of the past few weeks, but haven't written up
an account of the progress, so this will be a bit of a catch-up article.</p>
<p>Having now studied the design of this thing in more depth, there are a few things I find interesting:</p>
<ul>
<li>
<p>The inner loops of the multiplication, division, and floating-point normalization algorithms on the FP11
are not implemented in microcode, but rather as "hardware subroutines". Microcode does all the setup of
the various internal registers and counters, then pauses while the hardware runs the inner loop, then picks up
again to mediate rounding, masking, exceptions, etc. afterward.</p>
</li>
<li>
<p>The multiplication implementation uses an interesting algorithm called "skipping over ones and zeros",
described in section 5.3.1 of the FP11 maintenance manual. This reduces the number of time-consuming
additions needed on average. It works along the lines of a familiar mental shortcut: suppose you had to
multiply some number X by 999. Rather than multiply X by 9 three times and shift and add them all up, you
would probably just take X * 1,000 and subtract off X * 1. The key observation is that you can do this
for any contiguous string of 9s in the multiplier: subtract the multiplicand from the partial product at
the place value where the string begins, then add the multiplicand at one past place value where the string
ends. The FP11 implements the binary equivalent of this with a small state machine (comprised of flip-flops
MR1, MR0, and STRG1) which identifies strings of contiguous 1s and invokes ALU subtractions and additions on
the boundaries as the multiplier is shifted through.</p>
</li>
<li>
<p>Debugging techniques: a KM11 in single-clock-transition mode may be used to step within the hardware
subroutines, as they are driven off the main FP11 clock. It can be a lot of switch presses to step through
an entire multiply (120 or so clock transitions at least for a double-precision multiply, and typically
more because each necessary intermediate add/subtract adds eight clock transitions!) and this gets to be
pretty tedious and error-prone. A logic analyzer is very useful here to capture a visualization of an entire
multiplication at one go, and enable counting off clock transitions needed to get to something you'd
like to take a closer look at with a logic probe. Alternatively, if your FP11 is working well enough to
run maintenance instructions, there are software techniques that can prematurely terminate the hardware
subroutines and also give some useful visibility into the intermediate states.</p>
</li>
</ul>
<p>I opted to try out the software techniques to see if I could get more information on the (mis)behavior in
my FP11 order to focus my hardware troubleshooting. The following program came in handy. This is based off
some example code in the FP11 maintenance manual, though I elaborated it slightly with a binary printout
routine:</p>
<table class="highlighttable"><tr><td class="linenos"><div class="linenodiv"><pre> 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85</pre></div></td><td class="code"><div class="highlight"><pre><span></span> <span class="nt">000000</span> <span class="nt">AC0</span><span class="o">=%</span><span class="nt">0</span>
<span class="nt">000001</span> <span class="nt">AC1</span><span class="o">=%</span><span class="nt">1</span>
<span class="nt">000002</span> <span class="nt">AC2</span><span class="o">=%</span><span class="nt">2</span>
<span class="nt">177560</span> <span class="nt">SERIAL</span><span class="o">=</span><span class="nt">177560</span>
<span class="nt">170006</span> <span class="nt">MRS</span><span class="o">=</span><span class="nt">170006</span>
<span class="nt">000000</span> <span class="p">.</span><span class="nc">ASECT</span>
<span class="nt">001000</span> <span class="o">.=</span><span class="nt">1000</span>
<span class="nt">001000</span> <span class="nt">170127</span> <span class="nt">040220</span> <span class="nt">START</span><span class="o">:</span> <span class="nt">LDFPS</span> <span class="p">#</span><span class="nn">40220</span> <span class="o">;</span><span class="nt">DISABLE</span> <span class="nt">INTS</span><span class="o">,</span> <span class="nt">SET</span> <span class="nt">DBL</span> <span class="nt">AND</span> <span class="nt">MAINT</span> <span class="nt">MODE</span>
<span class="nt">001004</span> <span class="nt">172667</span> <span class="nt">000316</span> <span class="nt">LDD</span> <span class="nt">MLYR</span><span class="o">,</span><span class="nt">AC2</span> <span class="o">;</span><span class="nt">LOAD</span> <span class="nt">MULTIPLIER</span> <span class="nt">IN</span> <span class="nt">AC2</span>
<span class="nt">001010</span> <span class="nt">012703</span> <span class="nt">000230</span> <span class="nt">MOV</span> <span class="p">#</span><span class="nn">230</span><span class="o">,</span><span class="nt">R3</span> <span class="o">;</span><span class="nt">R3</span> <span class="nt">GETS</span> <span class="nt">OCTAL</span> <span class="nt">230</span> <span class="o">(</span><span class="nt">FRAC</span> <span class="nt">MUL</span> <span class="nt">MICROSTATE</span><span class="o">)</span>
<span class="nt">001014</span> <span class="nt">170003</span> <span class="nt">LDUB</span> <span class="o">;</span><span class="nt">LOAD</span> <span class="nt">R3</span> <span class="nt">TO</span> <span class="nt">MBR</span>
<span class="nt">001016</span> <span class="nt">012702</span> <span class="nt">177564</span> <span class="nt">MOV</span> <span class="p">#</span><span class="nn">SERIAL</span><span class="o">+</span><span class="nt">4</span><span class="o">,</span><span class="nt">R2</span> <span class="o">;</span><span class="nt">SERIAL</span> <span class="nt">XMIT</span> <span class="nt">BASE</span> <span class="nt">TO</span> <span class="nt">R2</span>
<span class="nt">001022</span> <span class="nt">012762</span> <span class="nt">000015</span> <span class="nt">000002</span> <span class="nt">MOV</span> <span class="p">#</span><span class="nn">15</span><span class="o">,</span><span class="nt">2</span><span class="o">(</span><span class="nt">R2</span><span class="o">)</span> <span class="o">;</span><span class="nt">OUTPUT</span> <span class="s1">'\R'</span>
<span class="nt">001030</span> <span class="nt">105712</span> <span class="nt">TSTB</span> <span class="o">(</span><span class="nt">R2</span><span class="o">)</span> <span class="o">;</span><span class="nt">CHECK</span> <span class="nt">XMIT</span> <span class="nt">CLEAR</span>
<span class="nt">001032</span> <span class="nt">100376</span> <span class="nt">BPL</span> <span class="p">.</span><span class="nc">-2</span> <span class="o">;</span><span class="nt">LOOP</span> <span class="nt">UNTIL</span> <span class="nt">SO</span>
<span class="nt">001034</span> <span class="nt">012762</span> <span class="nt">000012</span> <span class="nt">000002</span> <span class="nt">MOV</span> <span class="p">#</span><span class="nn">12</span><span class="o">,</span><span class="nt">2</span><span class="o">(</span><span class="nt">R2</span><span class="o">)</span> <span class="o">;</span><span class="nt">OUTPUT</span> <span class="s1">'\N'</span>
<span class="nt">001042</span> <span class="nt">105712</span> <span class="nt">TSTB</span> <span class="o">(</span><span class="nt">R2</span><span class="o">)</span> <span class="o">;</span><span class="nt">CHECK</span> <span class="nt">XMIT</span> <span class="nt">CLEAR</span>
<span class="nt">001044</span> <span class="nt">100376</span> <span class="nt">BPL</span> <span class="p">.</span><span class="nc">-2</span> <span class="o">;</span><span class="nt">LOOP</span> <span class="nt">UNTIL</span> <span class="nt">SO</span>
<span class="nt">001046</span> <span class="nt">005004</span> <span class="nt">CLR</span> <span class="nt">R4</span> <span class="o">;</span><span class="nt">R4</span> <span class="nt">HOLDS</span> <span class="nt">SC</span> <span class="nt">VALUE</span>
<span class="nt">001050</span> <span class="nt">005204</span> <span class="nt">NXTMUL</span><span class="o">:</span> <span class="nt">INC</span> <span class="nt">R4</span> <span class="o">;</span><span class="nt">INCREMENT</span> <span class="nt">SC</span>
<span class="nt">001052</span> <span class="nt">170004</span> <span class="nt">LDSC</span> <span class="o">;</span><span class="nt">LOAD</span> <span class="nt">1S</span> <span class="nt">COMPLEMENT</span> <span class="nt">OF</span> <span class="nt">R4</span> <span class="nt">INTO</span> <span class="nt">SC</span>
<span class="nt">001054</span> <span class="nt">012705</span> <span class="nt">001356</span> <span class="nt">LSTMUL</span><span class="o">:</span> <span class="nt">MOV</span> <span class="p">#</span><span class="nn">QR</span><span class="o">+</span><span class="nt">10</span><span class="o">,</span><span class="nt">R5</span> <span class="o">;</span><span class="nt">SET</span> <span class="nt">R5</span> <span class="nt">PAST</span> <span class="nt">END</span> <span class="nt">OF</span> <span class="nt">STORAGE</span> <span class="nt">TABLE</span>
<span class="nt">001060</span> <span class="nt">172567</span> <span class="nt">000232</span> <span class="nt">LDD</span> <span class="nt">MCND</span><span class="o">,</span><span class="nt">AC1</span> <span class="o">;</span><span class="nt">LOAD</span> <span class="nt">MULTIPLICAND</span> <span class="nt">INTO</span> <span class="nt">AC1</span>
<span class="nt">001064</span> <span class="nt">171102</span> <span class="nt">MULD</span> <span class="nt">AC2</span><span class="o">,</span><span class="nt">AC1</span> <span class="o">;</span><span class="nt">DO</span> <span class="nt">PARTIAL</span> <span class="nt">MULTIPLY</span>
<span class="nt">001066</span> <span class="nt">170007</span> <span class="nt">STQ0</span> <span class="o">;</span><span class="nt">TRANSFER</span> <span class="nt">QR</span> <span class="nt">TO</span> <span class="nt">AC0</span>
<span class="nt">001070</span> <span class="nt">174045</span> <span class="nt">STD</span> <span class="nt">AC0</span><span class="o">,</span><span class="nt">-</span><span class="o">(</span><span class="nt">R5</span><span class="o">)</span> <span class="o">;</span><span class="nt">STORE</span> <span class="nt">QR</span> <span class="nt">IN</span> <span class="nt">TABLE</span>
<span class="nt">001072</span> <span class="nt">042715</span> <span class="nt">177600</span> <span class="nt">BIC</span> <span class="p">#</span><span class="nn">177600</span><span class="o">,(</span><span class="nt">R5</span><span class="o">)</span> <span class="o">;</span><span class="nt">CLEAR</span> <span class="nt">OFF</span> <span class="nt">SIGN</span> <span class="nt">AND</span> <span class="nt">EXPONENT</span>
<span class="nt">001076</span> <span class="nt">170005</span> <span class="nt">STA0</span> <span class="o">;</span><span class="nt">TRANSFER</span> <span class="nt">AR</span> <span class="nt">TO</span> <span class="nt">AC0</span>
<span class="nt">001100</span> <span class="nt">174045</span> <span class="nt">STD</span> <span class="nt">AC0</span><span class="o">,</span><span class="nt">-</span><span class="o">(</span><span class="nt">R5</span><span class="o">)</span> <span class="o">;</span><span class="nt">STORE</span> <span class="nt">AR</span> <span class="nt">IN</span> <span class="nt">TABLE</span>
<span class="nt">001102</span> <span class="nt">042715</span> <span class="nt">177600</span> <span class="nt">BIC</span> <span class="p">#</span><span class="nn">177600</span><span class="o">,(</span><span class="nt">R5</span><span class="o">)</span> <span class="o">;</span><span class="nt">CLEAR</span> <span class="nt">OFF</span> <span class="nt">SIGN</span> <span class="nt">AND</span> <span class="nt">EXPONENT</span>
<span class="nt">001106</span> <span class="nt">170006</span> <span class="nt">MRS</span> <span class="o">;</span><span class="nt">SHIFT</span> <span class="nt">AR</span> <span class="nt">AND</span> <span class="nt">QR</span> <span class="nt">RIGHT</span> <span class="nt">ONE</span> <span class="nt">PLACE</span>
<span class="nt">001110</span> <span class="nt">170006</span> <span class="nt">MRS</span> <span class="o">;</span><span class="nt">SHIFT</span> <span class="nt">AR</span> <span class="nt">AND</span> <span class="nt">QR</span> <span class="nt">RIGHT</span> <span class="nt">ONE</span> <span class="nt">PLACE</span>
<span class="nt">001112</span> <span class="nt">170007</span> <span class="nt">STQ0</span> <span class="o">;</span><span class="nt">TRANSFER</span> <span class="nt">QR</span> <span class="nt">TO</span> <span class="nt">AC0</span>
<span class="nt">001114</span> <span class="nt">174067</span> <span class="nt">000236</span> <span class="nt">STD</span> <span class="nt">AC0</span><span class="o">,</span><span class="nt">TEMP</span> <span class="o">;</span><span class="nt">STORE</span> <span class="nt">QR</span> <span class="nt">IN</span> <span class="nt">TEMP</span>
<span class="nt">001120</span> <span class="nt">016703</span> <span class="nt">000232</span> <span class="nt">MOV</span> <span class="nt">TEMP</span><span class="o">,</span><span class="nt">R3</span> <span class="o">;</span><span class="nt">FETCH</span> <span class="nt">MSW</span> <span class="nt">OF</span> <span class="nt">QR</span> <span class="nt">TO</span> <span class="nt">R3</span>
<span class="nt">001124</span> <span class="nt">042703</span> <span class="nt">177600</span> <span class="nt">BIC</span> <span class="p">#</span><span class="nn">177600</span><span class="o">,</span><span class="nt">R3</span> <span class="o">;</span><span class="nt">CLEAR</span> <span class="nt">OFF</span> <span class="nt">SIGN</span> <span class="nt">AND</span> <span class="nt">EXPONENT</span>
<span class="nt">001130</span> <span class="nt">006303</span> <span class="nt">ASL</span> <span class="nt">R3</span> <span class="o">;</span><span class="nt">SHIFT</span> <span class="nt">MSBS</span> <span class="nt">OF</span> <span class="nt">QR</span> <span class="nt">ONE</span> <span class="nt">PLACE</span> <span class="nt">LEFT</span>
<span class="nt">001132</span> <span class="nt">006303</span> <span class="nt">ASL</span> <span class="nt">R3</span> <span class="o">;</span><span class="nt">SHIFT</span> <span class="nt">MSBS</span> <span class="nt">OF</span> <span class="nt">QR</span> <span class="nt">ONE</span> <span class="nt">PLACE</span> <span class="nt">LEFT</span>
<span class="nt">001134</span> <span class="nt">050365</span> <span class="nt">000010</span> <span class="nt">BIS</span> <span class="nt">R3</span><span class="o">,</span><span class="nt">10</span><span class="o">(</span><span class="nt">R5</span><span class="o">)</span> <span class="o">;</span><span class="nt">SET</span> <span class="nt">QR59</span> <span class="nt">AND</span> <span class="nt">QR58</span> <span class="nt">IN</span> <span class="nt">TABLE</span>
<span class="nt">001140</span> <span class="nt">170005</span> <span class="nt">STA0</span> <span class="o">;</span><span class="nt">TRANSFER</span> <span class="nt">AR</span> <span class="nt">TO</span> <span class="nt">AC0</span>
<span class="nt">001142</span> <span class="nt">174067</span> <span class="nt">000210</span> <span class="nt">STD</span> <span class="nt">AC0</span><span class="o">,</span><span class="nt">TEMP</span> <span class="o">;</span><span class="nt">STORE</span> <span class="nt">AR</span> <span class="nt">IN</span> <span class="nt">TEMP</span>
<span class="nt">001146</span> <span class="nt">016703</span> <span class="nt">000204</span> <span class="nt">MOV</span> <span class="nt">TEMP</span><span class="o">,</span><span class="nt">R3</span> <span class="o">;</span><span class="nt">FETCH</span> <span class="nt">MSW</span> <span class="nt">OF</span> <span class="nt">AR</span> <span class="nt">TO</span> <span class="nt">R3</span>
<span class="nt">001152</span> <span class="nt">042703</span> <span class="nt">177600</span> <span class="nt">BIC</span> <span class="p">#</span><span class="nn">177600</span><span class="o">,</span><span class="nt">R3</span> <span class="o">;</span><span class="nt">CLEAR</span> <span class="nt">OFF</span> <span class="nt">SIGN</span> <span class="nt">AND</span> <span class="nt">EXPONENT</span>
<span class="nt">001156</span> <span class="nt">006303</span> <span class="nt">ASL</span> <span class="nt">R3</span> <span class="o">;</span><span class="nt">SHIFT</span> <span class="nt">MSBS</span> <span class="nt">OF</span> <span class="nt">AR</span> <span class="nt">ONE</span> <span class="nt">PLACE</span> <span class="nt">LEFT</span>
<span class="nt">001160</span> <span class="nt">006303</span> <span class="nt">ASL</span> <span class="nt">R3</span> <span class="o">;</span><span class="nt">SHIFT</span> <span class="nt">MSBS</span> <span class="nt">OF</span> <span class="nt">AR</span> <span class="nt">ONE</span> <span class="nt">PLACE</span> <span class="nt">LEFT</span>
<span class="nt">001162</span> <span class="nt">050315</span> <span class="nt">BIS</span> <span class="nt">R3</span><span class="o">,(</span><span class="nt">R5</span><span class="o">)</span> <span class="o">;</span><span class="nt">SET</span> <span class="nt">AR59</span> <span class="nt">AND</span> <span class="nt">AR58</span> <span class="nt">IN</span> <span class="nt">TABLE</span>
<span class="nt">001164</span> <span class="nt">012705</span> <span class="nt">001336</span> <span class="nt">MOV</span> <span class="p">#</span><span class="nn">AR</span><span class="o">,</span><span class="nt">R5</span> <span class="o">;</span><span class="nt">GET</span> <span class="nt">ADDRESS</span> <span class="nt">OF</span> <span class="nt">FIRST</span> <span class="nt">QUAD</span> <span class="nt">FOR</span> <span class="nt">PRINTING</span>
<span class="nt">001170</span> <span class="nt">012700</span> <span class="nt">000010</span> <span class="nt">MOV</span> <span class="p">#</span><span class="nn">10</span><span class="o">,</span><span class="nt">R0</span> <span class="o">;</span><span class="nt">R0</span> <span class="nt">COUNTS</span> <span class="nt">8</span> <span class="nt">WORDS</span> <span class="nt">IN</span> <span class="nt">TWO</span> <span class="nt">QUADS</span>
<span class="nt">001174</span> <span class="nt">012503</span> <span class="nt">LWORD</span><span class="o">:</span> <span class="nt">MOV</span> <span class="o">(</span><span class="nt">R5</span><span class="o">)+,</span><span class="nt">R3</span> <span class="o">;</span><span class="nt">FETCH</span> <span class="nt">NEXT</span> <span class="nt">WORD</span> <span class="nt">OF</span> <span class="nt">QUAD</span>
<span class="nt">001176</span> <span class="nt">012701</span> <span class="nt">000020</span> <span class="nt">MOV</span> <span class="p">#</span><span class="nn">20</span><span class="o">,</span><span class="nt">R1</span> <span class="o">;</span><span class="nt">R1</span> <span class="nt">COUNTS</span> <span class="nt">16</span> <span class="nt">BITS</span> <span class="nt">IN</span> <span class="nt">WORD</span>
<span class="nt">001202</span> <span class="nt">006103</span> <span class="nt">LBIT</span><span class="o">:</span> <span class="nt">ROL</span> <span class="nt">R3</span> <span class="o">;</span><span class="nt">ROTATE</span><span class="o">,</span> <span class="nt">HIGH</span> <span class="nt">BIT</span> <span class="nt">GOES</span> <span class="nt">TO</span> <span class="nt">CARRY</span>
<span class="nt">001204</span> <span class="nt">103405</span> <span class="nt">BCS</span> <span class="nt">LBIT1</span> <span class="o">;</span><span class="nt">SKIP</span> <span class="nt">AHEAD</span> <span class="nt">IF</span> <span class="nt">CARRY</span> <span class="nt">SET</span>
<span class="nt">001206</span> <span class="nt">012762</span> <span class="nt">000056</span> <span class="nt">000002</span> <span class="nt">MOV</span> <span class="p">#</span><span class="nn">56</span><span class="o">,</span><span class="nt">2</span><span class="o">(</span><span class="nt">R2</span><span class="o">)</span> <span class="o">;</span><span class="nt">OTHERWISE</span> <span class="nt">OUTPUT</span> <span class="s1">'.'</span>
<span class="nt">001214</span> <span class="nt">000167</span> <span class="nt">000006</span> <span class="nt">JMP</span> <span class="nt">LBIT2</span> <span class="o">;</span><span class="nt">AND</span> <span class="nt">SKIP</span> <span class="nt">AHEAD</span>
<span class="nt">001220</span> <span class="nt">012762</span> <span class="nt">000061</span> <span class="nt">000002</span> <span class="nt">LBIT1</span><span class="o">:</span> <span class="nt">MOV</span> <span class="p">#</span><span class="nn">61</span><span class="o">,</span><span class="nt">2</span><span class="o">(</span><span class="nt">R2</span><span class="o">)</span> <span class="o">;</span><span class="nt">OUTPUT</span> <span class="s1">'1'</span>
<span class="nt">001226</span> <span class="nt">105712</span> <span class="nt">LBIT2</span><span class="o">:</span> <span class="nt">TSTB</span> <span class="o">(</span><span class="nt">R2</span><span class="o">)</span> <span class="o">;</span><span class="nt">CHECK</span> <span class="nt">XMIT</span> <span class="nt">CLEAR</span>
<span class="nt">001230</span> <span class="nt">100376</span> <span class="nt">BPL</span> <span class="p">.</span><span class="nc">-2</span> <span class="o">;</span><span class="nt">LOOP</span> <span class="nt">UNTIL</span> <span class="nt">SO</span>
<span class="nt">001232</span> <span class="nt">077115</span> <span class="nt">SOB</span> <span class="nt">R1</span><span class="o">,</span><span class="nt">LBIT</span> <span class="o">;</span><span class="nt">LOOP</span> <span class="nt">OVER</span> <span class="nt">BITS</span> <span class="nt">IN</span> <span class="nt">WORD</span>
<span class="nt">001234</span> <span class="nt">012762</span> <span class="nt">000040</span> <span class="nt">000002</span> <span class="nt">MOV</span> <span class="p">#</span><span class="nn">40</span><span class="o">,</span><span class="nt">2</span><span class="o">(</span><span class="nt">R2</span><span class="o">)</span> <span class="o">;</span><span class="nt">OUTPUT</span> <span class="s1">' '</span> <span class="nt">TO</span> <span class="nt">SEPARATE</span> <span class="nt">WORDS</span>
<span class="nt">001242</span> <span class="nt">105712</span> <span class="nt">TSTB</span> <span class="o">(</span><span class="nt">R2</span><span class="o">)</span> <span class="o">;</span><span class="nt">CHECK</span> <span class="nt">XMIT</span> <span class="nt">CLEAR</span>
<span class="nt">001244</span> <span class="nt">100376</span> <span class="nt">BPL</span> <span class="p">.</span><span class="nc">-2</span> <span class="o">;</span><span class="nt">LOOP</span> <span class="nt">UNTIL</span> <span class="nt">SO</span>
<span class="nt">001246</span> <span class="nt">077026</span> <span class="nt">SOB</span> <span class="nt">R0</span><span class="o">,</span><span class="nt">LWORD</span> <span class="o">;</span><span class="nt">LOOP</span> <span class="nt">OVER</span> <span class="nt">WORDS</span> <span class="nt">IN</span> <span class="nt">QUAD</span>
<span class="nt">001250</span> <span class="nt">012762</span> <span class="nt">000015</span> <span class="nt">000002</span> <span class="nt">MOV</span> <span class="p">#</span><span class="nn">15</span><span class="o">,</span><span class="nt">2</span><span class="o">(</span><span class="nt">R2</span><span class="o">)</span> <span class="o">;</span><span class="nt">OUTPUT</span> <span class="s1">'\R'</span>
<span class="nt">001256</span> <span class="nt">105712</span> <span class="nt">TSTB</span> <span class="o">(</span><span class="nt">R2</span><span class="o">)</span> <span class="o">;</span><span class="nt">CHECK</span> <span class="nt">XMIT</span> <span class="nt">CLEAR</span>
<span class="nt">001260</span> <span class="nt">100376</span> <span class="nt">BPL</span> <span class="p">.</span><span class="nc">-2</span> <span class="o">;</span><span class="nt">LOOP</span> <span class="nt">UNTIL</span> <span class="nt">SO</span>
<span class="nt">001262</span> <span class="nt">012762</span> <span class="nt">000012</span> <span class="nt">000002</span> <span class="nt">MOV</span> <span class="p">#</span><span class="nn">12</span><span class="o">,</span><span class="nt">2</span><span class="o">(</span><span class="nt">R2</span><span class="o">)</span> <span class="o">;</span><span class="nt">OUTPUT</span> <span class="s1">'\N'</span>
<span class="nt">001270</span> <span class="nt">105712</span> <span class="nt">TSTB</span> <span class="o">(</span><span class="nt">R2</span><span class="o">)</span> <span class="o">;</span><span class="nt">CHECK</span> <span class="nt">XMIT</span> <span class="nt">CLEAR</span>
<span class="nt">001272</span> <span class="nt">100376</span> <span class="nt">BPL</span> <span class="p">.</span><span class="nc">-2</span> <span class="o">;</span><span class="nt">LOOP</span> <span class="nt">UNTIL</span> <span class="nt">SO</span>
<span class="nt">001274</span> <span class="nt">020427</span> <span class="nt">000071</span> <span class="nt">CMP</span> <span class="nt">R4</span><span class="o">,</span><span class="p">#</span><span class="nn">71</span> <span class="o">;</span><span class="nt">CHECK</span> <span class="nt">PASSES</span> <span class="nt">AGAINST</span> <span class="nt">57</span>
<span class="nt">001300</span> <span class="nt">100663</span> <span class="nt">BMI</span> <span class="nt">NXTMUL</span> <span class="o">;</span><span class="nt">LESS</span><span class="o">:</span> <span class="nt">DO</span> <span class="nt">NEXT</span> <span class="nt">PASS</span>
<span class="nt">001302</span> <span class="nt">001402</span> <span class="nt">BEQ</span> <span class="nt">LSTPAS</span> <span class="o">;</span><span class="nt">EQUAL</span><span class="o">:</span> <span class="nt">DO</span> <span class="nt">LAST</span> <span class="nt">PASS</span>
<span class="nt">001304</span> <span class="nt">000167</span> <span class="nt">171470</span> <span class="nt">JMP</span> <span class="nt">173000</span> <span class="o">;</span><span class="nt">GREATER</span><span class="o">:</span> <span class="nt">RETURN</span> <span class="nt">TO</span> <span class="nt">M9301</span> <span class="nt">MONITOR</span>
<span class="nt">001310</span> <span class="nt">005204</span> <span class="nt">LSTPAS</span><span class="o">:</span> <span class="nt">INC</span> <span class="nt">R4</span> <span class="o">;</span><span class="nt">INDICATE</span> <span class="nt">58TH</span> <span class="nt">PASS</span>
<span class="nt">001312</span> <span class="nt">000167</span> <span class="nt">177536</span> <span class="nt">JMP</span> <span class="nt">LSTMUL</span> <span class="o">;</span><span class="nt">DO</span> <span class="nt">LAST</span> <span class="nt">PASS</span> <span class="nt">WITHOUT</span> <span class="nt">LOADING</span> <span class="nt">SC</span>
<span class="nt">001316</span> <span class="nt">040200</span> <span class="nt">000000</span> <span class="nt">000000</span> <span class="nt">MCND</span><span class="o">:</span> <span class="p">.</span><span class="nc">WORD</span> <span class="nt">040200</span><span class="o">,</span> <span class="nt">000000</span><span class="o">,</span> <span class="nt">000000</span><span class="o">,</span> <span class="nt">000000</span>
<span class="nt">001324</span> <span class="nt">000000</span>
<span class="nt">001326</span> <span class="nt">040300</span> <span class="nt">000300</span> <span class="nt">000300</span> <span class="nt">MLYR</span><span class="o">:</span> <span class="p">.</span><span class="nc">WORD</span> <span class="nt">040300</span><span class="o">,</span> <span class="nt">000300</span><span class="o">,</span> <span class="nt">000300</span><span class="o">,</span> <span class="nt">000300</span>
<span class="nt">001334</span> <span class="nt">000300</span>
<span class="nt">001336</span> <span class="nt">000000</span> <span class="nt">000000</span> <span class="nt">000000</span> <span class="nt">AR</span><span class="o">:</span> <span class="p">.</span><span class="nc">FLT4</span> <span class="nt">0</span>
<span class="nt">001344</span> <span class="nt">000000</span>
<span class="nt">001346</span> <span class="nt">000000</span> <span class="nt">000000</span> <span class="nt">000000</span> <span class="nt">QR</span><span class="o">:</span> <span class="p">.</span><span class="nc">FLT4</span> <span class="nt">0</span>
<span class="nt">001354</span> <span class="nt">000000</span>
<span class="nt">001356</span> <span class="nt">000000</span> <span class="nt">000000</span> <span class="nt">000000</span> <span class="nt">TEMP</span><span class="o">:</span> <span class="p">.</span><span class="nc">FLT4</span> <span class="nt">0</span>
<span class="nt">001364</span> <span class="nt">000000</span>
<span class="nt">001000</span> <span class="p">.</span><span class="nc">END</span> <span class="nt">START</span>
</pre></div>
</td></tr></table>
<p>The idea here is to use the LDUB (load micro-break) and LDSC (load step-counter) maintenance instructions to
cause a multiplication to halt partway through. STA0 and STQ0 (store AR, store QR) instructions, in
conjunction with the MRS (maintenance right shift) instruction, allow retrieval of the internal fraction
registers which are then printed out to the serial console. This is done repetitively, stopping each time
one step further on, so the progression of the internal states of AR and QR over the course of the entire
multiply may be observed.</p>
<p>A quick aside here on tooling: since I don't currently have any storage or an OS running on my PDP-11, I load
and execute diagnostics with PDP11GUI to an M9301 boot monitor over a serial connection. This requires
program binaries in LDA (absolute loader) format. For non-trivial MACRO-11 programs I have found it most
convenient to use the actual vintage toolchain under RT-11 in the simh simulator, because the assembler and
linker provided with PDP11GUI have some limitations. I copy files in and out via the simulated paper tape
reader/punch. This is also how I produce the MACRO-11 listings seen on this blog.</p>
<p>Okay, back to the program above, running this on my machine very clearly illustrates the malfunction. Here's
what the output looks like:</p>
<p><span style="font-size: x-small; font-family: monospace; white-space: pre; display: block; line-height: normal; font-weight: bold;">................ ................ ................ ................ .........11..... .........11..... .........11..... .........11.....
................ ................ ................ ................ ..........11.... ..........11.... ..........11.... ..........11....
................ ................ ................ ................ ...........11... ...........11... ...........11... ...........11...
................ ................ ................ ................ ............11.. ............11.. ............11.. ............11..
................ ................ ................ ................ .............11. .............11. .............11. .............11.
................ ................ ................ ................ ..............11 ..............11 ..............11 ..............11
................ ................ ................ ................ ...............1 1..............1 1..............1 1..............1
.......11.111111 1111111111111111 1111111111111111 1111111111111111 ................ 11.............. 11.............. 11..............
.......111.11111 1111111111111111 1111111111111111 1111111111111111 ................ .11............. .11............. .11.............
..........1.1111 1111111111111111 1111111111111111 1111111111111111 ................ ..11............ ..11............ ..11............
...........1.111 1111111111111111 1111111111111111 1111111111111111 ................ ...11........... ...11........... ...11...........
............1.11 1111111111111111 1111111111111111 1111111111111111 ................ ....11.......... ....11.......... ....11..........
.............1.1 1111111111111111 1111111111111111 1111111111111111 ................ .....11......... .....11......... .....11.........
..............1. 1111111111111111 1111111111111111 1111111111111111 ................ ......11........ ......11........ ......11........
...............1 .111111111111111 1111111111111111 1111111111111111 ................ .......11....... .......11....... .......11.......
................ 1.11111111111111 1111111111111111 1111111111111111 ................ ........11...... ........11...... ........11......
................ .1.1111111111111 1111111111111111 1111111111111111 ................ .........11..... .........11..... .........11.....
................ ..1.111111111111 1111111111111111 1111111111111111 ................ ..........11.... ..........11.... ..........11....
................ ...1.11111111111 1111111111111111 1111111111111111 ................ ...........11... ...........11... ...........11...
................ ....1.1111111111 1111111111111111 1111111111111111 ................ ............11.. ............11.. ............11..
................ .....1.111111111 1111111111111111 1111111111111111 ................ .............11. .............11. .............11.
................ ......1.11111111 1111111111111111 1111111111111111 ................ ..............11 ..............11 ..............11
................ .......1.1111111 1111111111111111 1111111111111111 ................ ...............1 1..............1 1..............1
.......111...... ........1.111111 1111111111111111 1111111111111111 ................ ................ 11.............. 11..............
.......1111..... .........1.11111 1111111111111111 1111111111111111 ................ ................ .11............. .11.............
..........11.... ..........1.1111 1111111111111111 1111111111111111 ................ ................ ..11............ ..11............
...........11... ...........1.111 1111111111111111 1111111111111111 ................ ................ ...11........... ...11...........
............11.. ............1.11 1111111111111111 1111111111111111 ................ ................ ....11.......... ....11..........
.............11. .............1.1 1111111111111111 1111111111111111 ................ ................ .....11......... .....11.........
..............11 ..............1. 1111111111111111 1111111111111111 ................ ................ ......11........ ......11........
...............1 1..............1 .111111111111111 1111111111111111 ................ ................ .......11....... .......11.......
................ 11.............. 1.11111111111111 1111111111111111 ................ ................ ........11...... ........11......
................ .11............. .1.1111111111111 1111111111111111 ................ ................ .........11..... .........11.....
................ ..11............ ..1.111111111111 1111111111111111 ................ ................ ..........11.... ..........11....
................ ...11........... ...1.11111111111 1111111111111111 ................ ................ ...........11... ...........11...
................ ....11.......... ....1.1111111111 1111111111111111 ................ ................ ............11.. ............11..
................ .....11......... .....1.111111111 1111111111111111 ................ ................ .............11. .............11.
................ ......11........ ......1.11111111 1111111111111111 ................ ................ ..............11 ..............11
................ .......11....... .......1.1111111 1111111111111111 ................ ................ ...............1 1..............1
.......111...... ........11...... ........1.111111 1111111111111111 ................ ................ ................ 11..............
.......1111..... .........11..... .........1.11111 1111111111111111 ................ ................ ................ .11.............
..........11.... ..........11.... ..........1.1111 1111111111111111 ................ ................ ................ ..11............
...........11... ...........11... ...........1.111 1111111111111111 ................ ................ ................ ...11...........
............11.. ............11.. ............1.11 1111111111111111 ................ ................ ................ ....11..........
.............11. .............11. .............1.1 1111111111111111 ................ ................ ................ .....11.........
..............11 ..............11 ..............1. 1111111111111111 ................ ................ ................ ......11........
...............1 1..............1 1..............1 .111111111111111 ................ ................ ................ .......11.......
................ 11.............. 11.............. 1.11111111111111 ................ ................ ................ ........11......
................ .11............. .11............. .1.1111111111111 ................ ................ ................ .........11.....
................ ..11............ ..11............ ..1.111111111111 ................ ................ ................ ..........11....
................ ...11........... ...11........... ...1.11111111111 ................ ................ ................ ...........11...
................ ....11.......... ....11.......... ....1.1111111111 ................ ................ ................ ............11..
................ .....11......... .....11......... .....1.111111111 ................ ................ ................ .............11.
................ ......11........ ......11........ ......1.11111111 ................ ................ ................ ..............11
................ .......11....... .......11....... .......1.1111111 ................ ................ ................ ...............1
.......111...... ........11...... ........11...... ........1.111111 ................ ................ ................ ................
.......1111..... .........11..... .........11..... .........1.11111 ................ ................ ................ ................
.........11..... .........11..... .........11..... .........1.11111 ................ ................ ................ ................</span></p>
<p>The left half of the output above shows the contents of AR throughout the progress of the multiply, and the
right half shows the contents of QR. The most significant 57 bits of each are shown, right justified in a
64-bit field.</p>
<p>In the FP11, as the multiplication proceeds, the multiplicand is held constant, while the multiplier (in QR)
and partial product (in AR) are successively right shifted. The bits of the multiplier involved in the
skip-over-ones-and-zeros sate macheine are QR3 and QR2. QR3 is the rightmost bit shown above. QR2, to its
right, is not retrievable by software and thus not shown.</p>
<p>Since the multiplicand in the sample code is 1.0, the result left in AR (bottom row of left half) should be
identical with the initial value of the multiplier in QR (top row of right half), but clearly something is
amiss with the least significant bits of the result. We can also see that things go awry as the first
string off consecutive 1s starts through the state machine (adjusting the values in the test program shows
that this is always the case). So this looks like an issue with the state machine or the FALU control
signals that derive from it. Taking a look with the logic analyzer shows this:</p>
<p><img src='/images/pdp11/multiply-trace.jpg'/></p>
<p>This is a portion of the multiply dealing with the a string of two consecutive 1s on the multiplier.
The clocking and state machine state bits look correct (note that AR clocks falling edges).
A four-cycle pause is inserted in the AR clock whenever the state-machine dictates either an add
or a subtract is to occur, in order to allow for propagation time through the ALUs. The AR and ALU function
selects also look correct: AR 1 for shift, 3 for load, and ALU 6 for subtract, 9 for add. Marker X here
should be clocking in a subtraction at the start of the string, followed by two shifts, then an add at
marker O at the end of the string.</p>
<p>But the ALU CIN control signal looks incorrect -- it is held high throughout the multiply, but should be
driven low for the subtraction at marker X. This means the ALU function actually being selected is A-B-1
instead of A-B, which would produce the results seen above (the first subtract borrows an extra 1 all the
way across the partial product, then subsequent subtracts borrow from the resulting 1s on the right).
So it looks like the logic that generates CIN needs a look:</p>
<p><img src='/images/pdp11/cin-logic.png'/></p>
<p>Stepping through the multiply with the KM11 in single-clock-transition mode, arriving at the first
subtract, FRMH MUL SUB L is asserted low to pin 3 of E21, but pin 6 does not go high. Looks like a
failed gate; pulled the part, put in a socket, and put a replacement 74H10 on order. All for now!</p></div>
<hr />
</div>
<div class='article'>
<div class="content-title">
<a href="https://fritzm.github.io/diagnostics-12.html"><h1>PDP-11/45: Diagnostics XII - FP11 FPU, cont.</h1></a>
Sun 30 October 2016
by <a class="url fn" href="https://fritzm.github.io/author/fritz-mueller.html">Fritz Mueller</a>
</div>
<div><p>Some spare 74194 arrived in the mail; popped one in to the socket I had prepared at E15 on the FRL board,
and the FP add/subtract problem is fixed. The following FP11 diagnostics now pass:</p>
<style>
.diaglist { display: inline; border-collapse: collapse; margin-right: 1em; }
.diaglist caption { font-weight: bold; }
.diaglist tr:nth-child(even) { background-color: #f2f2f2; }
.diaglist th, .diaglist td { padding: 5px; }
.diaglist td { border: 1px solid lightgray; font-family: Menlo,Consolas,monospace; }
</style>
<table class="diaglist">
<thead>
<tr><th>Diagnostic</th><th>Description</th><th>Status</th></tr>
</thead>
<tbody>
<tr><td>CFPAB0.BIC</td><td>LDFPS,STFPS,SETI,SETL,SETF,SETD,CFCC</td><td>pass</td></tr>
<tr><td>CFPBB0.BIC</td><td>STST</td><td>pass</td></tr>
<tr><td>CFPCD0.BIC</td><td>LDF,LDD,STF,STD</td><td>pass</td></tr>
<tr><td>CFPDC0.BIC</td><td>ADDF,ADDD,SUBF,SUBD</td><td>pass</td></tr>
<tr><td>CFPEB0.BIC</td><td>CMPF,CMPD</td><td>pass</td></tr>
<tr><td>CFPFB0.BIC</td><td>MULF,MULD</td><td>pass</td></tr>
<tr><td>CFPGC0.BIC</td><td>DIVF,DIVD</td><td>pass</td></tr>
<tr><td>CFPHB0.BIC</td><td>CLR,TST,ABS,NEG</td><td>pass</td></tr>
<tr><td>CFPIB0.BIC</td><td>LDCDF,LDCFD,STCFD,STCDF</td><td>pass</td></tr>
<tr><td>CFPJB0.BIC</td><td>LDCJX,STCXJ</td><td>pass</td></tr>
<tr><td>CFPKB0.BIC</td><td>LDEXP</td><td>pass</td></tr>
<tr><td>CFPMB0.BIC</td><td>MAINT</td><td>pass</td></tr>
</tbody>
</table>
<p>...which is almost everything. The last failing diagnostic is CFPLB0, which tests MODF and MODD. Set up
a similar test program for this instruction:</p>
<table class="highlighttable"><tr><td class="linenos"><div class="linenodiv"><pre> 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20</pre></div></td><td class="code"><div class="highlight"><pre><span></span> <span class="nt">000000</span> <span class="nt">AC0</span><span class="o">=%</span><span class="nt">0</span>
<span class="nt">000001</span> <span class="nt">AC1</span><span class="o">=%</span><span class="nt">1</span>
<span class="nt">000000</span> <span class="p">.</span><span class="nc">ASECT</span>
<span class="nt">001000</span> <span class="o">.=</span><span class="nt">1000</span>
<span class="nt">001000</span> <span class="nt">170011</span> <span class="nt">START</span><span class="o">:</span> <span class="nt">SETD</span> <span class="o">;</span><span class="nt">SET</span> <span class="nt">DOUBLE</span> <span class="nt">PRECISION</span> <span class="nt">MODE</span>
<span class="nt">001002</span> <span class="nt">172467</span> <span class="nt">000020</span> <span class="nt">LDD</span> <span class="nt">D1</span><span class="o">,</span><span class="nt">AC0</span> <span class="o">;</span><span class="nt">FETCH</span> <span class="nt">FIRST</span> <span class="nt">OPERAND</span> <span class="nt">FROM</span> <span class="nt">D1</span>
<span class="nt">001006</span> <span class="nt">172567</span> <span class="nt">000024</span> <span class="nt">LDD</span> <span class="nt">D2</span><span class="o">,</span><span class="nt">AC1</span> <span class="o">;</span><span class="nt">FETCH</span> <span class="nt">SECOND</span> <span class="nt">OPERAND</span> <span class="nt">FROM</span> <span class="nt">D2</span>
<span class="nt">001012</span> <span class="nt">171401</span> <span class="nt">MODD</span> <span class="nt">AC1</span><span class="o">,</span><span class="nt">AC0</span> <span class="o">;</span><span class="nt">MOD</span> <span class="o">(</span><span class="nt">FRAC</span> <span class="nt">IN</span> <span class="nt">AC0</span><span class="o">,</span> <span class="nt">INT</span> <span class="nt">IN</span> <span class="nt">AC1</span><span class="o">)</span>
<span class="nt">001014</span> <span class="nt">174067</span> <span class="nt">000026</span> <span class="nt">STD</span> <span class="nt">AC0</span><span class="o">,</span><span class="nt">D3</span> <span class="o">;</span><span class="nt">STORE</span> <span class="nt">FRAC</span> <span class="nt">TO</span> <span class="nt">D3</span>
<span class="nt">001020</span> <span class="nt">174167</span> <span class="nt">000032</span> <span class="nt">STD</span> <span class="nt">AC1</span><span class="o">,</span><span class="nt">D4</span> <span class="o">;</span><span class="nt">STORE</span> <span class="nt">INT</span> <span class="nt">TO</span> <span class="nt">D4</span>
<span class="nt">001024</span> <span class="nt">000000</span> <span class="nt">HALT</span>
<span class="nt">001026</span> <span class="nt">040200</span> <span class="nt">000000</span> <span class="nt">000000</span> <span class="nt">D1</span><span class="o">:</span> <span class="p">.</span><span class="nc">WORD</span> <span class="nt">040200</span><span class="o">,</span><span class="nt">000000</span><span class="o">,</span><span class="nt">000000</span><span class="o">,</span><span class="nt">000000</span> <span class="o">;</span><span class="nt">1</span><span class="p">.</span><span class="nc">0</span>
<span class="nt">001034</span> <span class="nt">000000</span>
<span class="nt">001036</span> <span class="nt">040300</span> <span class="nt">000000</span> <span class="nt">000000</span> <span class="nt">D2</span><span class="o">:</span> <span class="p">.</span><span class="nc">WORD</span> <span class="nt">040300</span><span class="o">,</span><span class="nt">000000</span><span class="o">,</span><span class="nt">000000</span><span class="o">,</span><span class="nt">000000</span> <span class="o">;</span><span class="nt">1</span><span class="p">.</span><span class="nc">5</span>
<span class="nt">001044</span> <span class="nt">000000</span>
<span class="nt">001046</span> <span class="nt">000000</span> <span class="nt">000000</span> <span class="nt">000000</span> <span class="nt">D3</span><span class="o">:</span> <span class="p">.</span><span class="nc">WORD</span> <span class="nt">000000</span><span class="o">,</span><span class="nt">000000</span><span class="o">,</span><span class="nt">000000</span><span class="o">,</span><span class="nt">000000</span>
<span class="nt">001054</span> <span class="nt">000000</span>
<span class="nt">001056</span> <span class="nt">000000</span> <span class="nt">000000</span> <span class="nt">000000</span> <span class="nt">D4</span><span class="o">:</span> <span class="p">.</span><span class="nc">WORD</span> <span class="nt">000000</span><span class="o">,</span><span class="nt">000000</span><span class="o">,</span><span class="nt">000000</span><span class="o">,</span><span class="nt">000000</span>
<span class="nt">001064</span> <span class="nt">000000</span>
<span class="nt">001000</span> <span class="p">.</span><span class="nc">END</span> <span class="nt">START</span>
</pre></div>
</td></tr></table>