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Intel® Compiler for SystemC* (ICSC) translates synthesizable SystemC design to synthesizable SystemVerilog design.
ICSC supports SystemC synthesizable subset in method and thread processes and arbitrary C++ code in module constructors. The tool produces human-readable SystemVerilog for complex multi-module designs in tens of seconds. ICSC performs design checks to detect non-synthesizable code and common coding mistakes.
ICSC generates SystemVerilog (IEEE 1800-2017) code. To convert SystemVerilog to Verilog (IEEE 1364-2005) there is SV2V tool which is compatible with ICSC.
See more information at Intel Compiler for SystemC wiki.
ICSC is distributed under the Apache License v2.0 with LLVM Exceptions.
ICSC is based on Clang/LLVM frontend and can be installed at most Linux OS. There is install.sh script that downloads and builds ICSC and the required dependecies at Ubuntu 20.04.
An instruction how to install and run ISCS is given at Getting started.
User guide document describes installation procedure, run tool options, preparation of SystemC design for ICSC, and also tool extensions and advanced verification features.
SystemC/C++ various features supported by ICSC described at SystemC/C++ supported.
- SystemC-to-Verilog Compiler: a productivity-focused tool for hardware design in cycle-accurate SystemC at DvCon'2019
- Temporal assertions in SystemC at DvCon'2020 and SystemC evolution day'2020
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