arisco.core

CAPI=2:
name: namosca:arisco:core:0.0.1
description: RV32I Core made for learning and fun

filesets:
  rtl:
    files:
      - alu.v
      - multiple_instructions.v
      - pc.v
      - register_memory.v
      - single_instruction.v
    file_type: verilogSource

  tb:
    files:
      - alu_tb.v
      - consecutive_instructions_tb.v
      - pc_tb.v
      - register_memory_tb.v
      - instructions_i_tb.v
      - single_instruction_tb.v
      - utilities.v: {is_include_file: true}
    file_type: verilogSource

targets:
  # The "default" target is special in FuseSoC and used in dependencies.
  # The "&default" is a YAML anchor referenced later.
  default: &default
    filesets:
      - rtl
    toplevel: CPU

  # The "sim" target simulates the design. (It could have any name.)
  sim:
    # Copy all key/value pairs from the "default" target.
    <<: *default
    description: Simulate the design
    default_tool: icarus
    filesets_append:
      - tb
    toplevel: consecutive_instructions_tb
    tools:
      icarus:
        iverilog_options:
          - -g2012 # Use SystemVerilog-2012
      modelsim:
        vlog_options:
          - -timescale=1ns/1ns

# provider:
#   name    : github
#   user    : racerxdl
#   repo    : riskow
#   version : v0.0.1