From 548e57c43a11e4d270d37f360d46069b77cd26f3 Mon Sep 17 00:00:00 2001 From: Ryan Oldenburg Date: Sat, 17 Dec 2022 21:39:44 -0600 Subject: [PATCH] add SHA x64 runtime check --- nimsimd.nimble | 2 +- src/nimsimd/runtimecheck.nim | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/nimsimd.nimble b/nimsimd.nimble index 35b6a43..1bed898 100644 --- a/nimsimd.nimble +++ b/nimsimd.nimble @@ -1,4 +1,4 @@ -version = "1.2.1" +version = "1.2.2" author = "Ryan Oldenburg" description = "Pleasant Nim bindings for SIMD instruction sets." license = "MIT" diff --git a/src/nimsimd/runtimecheck.nim b/src/nimsimd/runtimecheck.nim index 009a910..d8226bc 100644 --- a/src/nimsimd/runtimecheck.nim +++ b/src/nimsimd/runtimecheck.nim @@ -1,4 +1,6 @@ when defined(amd64): + ## https://www.felixcloutier.com/x86/cpuid + type InstructionSet* = enum SSE3 @@ -8,6 +10,7 @@ when defined(amd64): AVX AVX2 PCLMULQDQ + SHA InstructionSetCheckInfo = object leaf, register, bit: int @@ -19,7 +22,8 @@ when defined(amd64): InstructionSetCheckInfo(leaf: 1, register: 2, bit: 20), # SSE42 InstructionSetCheckInfo(leaf: 1, register: 2, bit: 28), # AVX InstructionSetCheckInfo(leaf: 7, register: 1, bit: 5), # AVX2 - InstructionSetCheckInfo(leaf: 1, register: 2, bit: 1) # PCLMULQDQ + InstructionSetCheckInfo(leaf: 1, register: 2, bit: 1), # PCLMULQDQ + InstructionSetCheckInfo(leaf: 7, register: 1, bit: 29) # SHA ] proc cpuid(eaxi, ecxi: int32): array[4, int32] = # eax, ebx, ecx, edx