car.epr

<?xml version="1.0" encoding="UTF-8"?>
<!--Product Version: eLinx v1.0.0.0-->
<!--								-->
<!--Copyright 2017-2024 eHiWay, Inc. All Rights Reserved.-->
<Project Path="/car.epr">
    <Configuration>
        <Option Name="ActiveSimSet" Val="sim_1"/>
        <Option Name="App_Version" Val="3.0.7-09/27/2024"/>
        <Option Name="Project Type" Val="RTL"/>
        <Option Name="SimulationTopModule" Val=""/>
        <Option Name="Win_Version" Val="x86"/>
    </Configuration>
    <FileSets>
        <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
            <File Path="/car.srcs/sources_1/new/wires.v"/>
            <File Path="/car.srcs/sources_1/new/PWM_out.v"/>
        </FileSet>
        <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
            <File Path="/car.srcs/constrs_1/new/car.edc"/>
            <Config>
                <Option Name="TargetConstrsFile" Val="/car.srcs/constrs_1/new/car.edc"/>
            </Config>
        </FileSet>
        <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
            <Config>
                <Option Name="TargetSimulationsFile" Val=""/>
            </Config>
        </FileSet>
    </FileSets>
    <Runs>
        <Run Id="synth_1" Type="Synthesis" SrcSet="sources_1" ConstrsSet="constrs_1" State="current" Parent="" Configuration="">
            <Option Id="Compilation Flow">Classic Flow</Option>
            <Option Id="Device">EQ6HL130</Option>
            <Option Id="IPRepositories"></Option>
            <Option Id="LanguageVersion">SYSTEMVERILOG_2005</Option>
            <Option Id="OutOfDate">0</Option>
            <Option Id="Package">CSG484_H</Option>
            <Option Id="Series">eHiChip6</Option>
            <Option Id="TargetLanguage">VERILOG</Option>
            <Option Id="TopModule">wires</Option>
        </Run>
        <Run Id="imple_1" Type="Implementation" SrcSet="sources_1" ConstrsSet="constrs_1" State="current" Parent="" Configuration="" SynthRun="synth_1">
            <Option Id="BitgenOutOfDate">0</Option>
            <Option Id="FRAME_CRC">1</Option>
            <Option Id="OutOfDate">0</Option>
            <Option Id="Strategy"></Option>
        </Run>
    </Runs>
    <PRFlow>
        <PartitionDefs/>
        <PRConfigurations/>
    </PRFlow>
</Project>