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atarist.gprj
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atarist.gprj
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<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
<Template>FPGA</Template>
<Version>5</Version>
<Device name="GW2AR-18C" pn="GW2AR-LV18QN88C8/I7">gw2ar18c-000</Device>
<FileList>
<File path="./src/tangnano20k/top.sv" type="file.verilog" enable="1"/>
<File path="./src/atarist/atarist.v" type="file.verilog" enable="1"/>
<File path="./src/fx68k/fx68k.sv" type="file.verilog" enable="1"/>
<File path="./src/fx68k/fx68kAlu.sv" type="file.verilog" enable="1"/>
<File path="./src/fx68k/uaddrPla.sv" type="file.verilog" enable="1"/>
<File path="./src/fx68k/microrom.mem" type="file.other" enable="1"/>
<File path="./src/fx68k/nanorom.mem" type="file.other" enable="1"/>
<File path="./src/gstmcu/hdl/clockgen.v" type="file.verilog" enable="1"/>
<File path="./src/gstmcu/hdl/gstmcu.v" type="file.verilog" enable="1"/>
<File path="./src/gstmcu/hdl/gstshifter.v" type="file.verilog" enable="1"/>
<File path="./src/gstmcu/hdl/hdegen.v" type="file.verilog" enable="1"/>
<File path="./src/gstmcu/hdl/hsyncgen.v" type="file.verilog" enable="1"/>
<File path="./src/gstmcu/hdl/latch.v" type="file.verilog" enable="1"/>
<File path="./src/gstmcu/hdl/mcucontrol.v" type="file.verilog" enable="1"/>
<File path="./src/gstmcu/hdl/modules.v" type="file.verilog" enable="1"/>
<File path="./src/gstmcu/hdl/register.v" type="file.verilog" enable="1"/>
<File path="./src/gstmcu/hdl/shifter_video.v" type="file.verilog" enable="1"/>
<File path="./src/gstmcu/hdl/sndcnt.v" type="file.verilog" enable="1"/>
<File path="./src/gstmcu/hdl/vdegen.v" type="file.verilog" enable="1"/>
<File path="./src/gstmcu/hdl/vidcnt.v" type="file.verilog" enable="1"/>
<File path="./src/gstmcu/hdl/vsyncgen.v" type="file.verilog" enable="1"/>
<File path="./src/hdmi/audio_clock_regeneration_packet.sv" type="file.verilog" enable="1"/>
<File path="./src/hdmi/audio_info_frame.sv" type="file.verilog" enable="1"/>
<File path="./src/hdmi/audio_sample_packet.sv" type="file.verilog" enable="1"/>
<File path="./src/hdmi/auxiliary_video_information_info_frame.sv" type="file.verilog" enable="1"/>
<File path="./src/hdmi/hdmi.sv" type="file.verilog" enable="1"/>
<File path="./src/hdmi/packet_assembler.sv" type="file.verilog" enable="1"/>
<File path="./src/hdmi/packet_picker.sv" type="file.verilog" enable="1"/>
<File path="./src/hdmi/serializer.sv" type="file.verilog" enable="1"/>
<File path="./src/hdmi/source_product_description_info_frame.sv" type="file.verilog" enable="1"/>
<File path="./src/hdmi/tmds_channel.sv" type="file.verilog" enable="1"/>
<File path="./src/misc/scandoubler.v" type="file.verilog" enable="1"/>
<File path="./src/misc/video_analyzer.v" type="file.verilog" enable="1"/>
<File path="./src/misc/osd_ascii.v" type="file.verilog" enable="1"/>
<File path="./src/tangnano20k/flash_dspi.v" type="file.verilog" enable="1"/>
<File path="./src/tangnano20k/sdram.v" type="file.verilog" enable="1"/>
<File path="./src/tangnano20k/video.v" type="file.verilog" enable="1"/>
<File path="./src/tangnano20k/font_8x8_fnt.v" type="file.verilog" enable="1"/>
<File path="./src/tangnano20k/gowin_rpll/flash_pll.v" type="file.verilog" enable="1"/>
<File path="./src/tangnano20k/gowin_clkdiv/gowin_clkdiv.v" type="file.verilog" enable="1"/>
<File path="./src/tangnano20k/gowin_rpll/pll_160m.v" type="file.verilog" enable="1"/>
<File path="./src/atarist/mfp.v" type="file.verilog" enable="1"/>
<File path="./src/atarist/mfp_hbit16.v" type="file.verilog" enable="1"/>
<File path="./src/atarist/mfp_srff16.v" type="file.verilog" enable="1"/>
<File path="./src/atarist/mfp_timer.v" type="file.verilog" enable="1"/>
<File path="./src/atarist/io_fifo.v" type="file.verilog" enable="1"/>
<File path="./src/atarist/acia.v" type="file.verilog" enable="1"/>
<File path="./src/atarist/stBlitter.sv" type="file.verilog" enable="1"/>
<File path="./src/atarist/ste_joypad.v" type="file.verilog" enable="1"/>
<File path="./src/atarist/dma.v" type="file.verilog" enable="1"/>
<File path="./src/atarist/acsi.v" type="file.verilog" enable="1"/>
<!-- <File path="./src/atarist/YM2149.sv" type="file.verilog" enable="1"/>
<File path="./src/atarist/vol_table_array.v" type="file.verilog" enable="1"/> -->
<File path="./src/jt49/jt49_bus.v" type="file.verilog" enable="1"/>
<File path="./src/jt49/jt49.v" type="file.verilog" enable="1"/>
<File path="./src/jt49/jt49_cen.v" type="file.verilog" enable="1"/>
<File path="./src/jt49/jt49_div.v" type="file.verilog" enable="1"/>
<File path="./src/jt49/jt49_eg.v" type="file.verilog" enable="1"/>
<File path="./src/jt49/jt49_exp.v" type="file.verilog" enable="1"/>
<File path="./src/jt49/jt49_noise.v" type="file.verilog" enable="1"/>
<File path="./src/jt49/filter/jt49_dcrm2.v" type="file.verilog" enable="1"/>
<File path="./src/jt49/filter/jt49_dcrm.v" type="file.verilog" enable="1"/>
<File path="./src/jt49/filter/jt49_dly.v" type="file.verilog" enable="1"/>
<File path="./src/jt49/filter/jt49_mave.v" type="file.verilog" enable="1"/>
<File path="./src/fdc1772/fdc1772.v" type="file.verilog" enable="1"/>
<File path="./src/fdc1772/floppy.v" type="file.verilog" enable="1"/>
<File path="./src/ikbd/ikbd.sv" type="file.verilog" enable="1"/>
<File path="./src/ikbd/hd63701/HD63701_ALU.v" type="file.verilog" enable="1"/>
<File path="./src/ikbd/hd63701/HD63701_CORE.v" type="file.verilog" enable="1"/>
<File path="./src/ikbd/hd63701/HD63701_defs.i" type="file.verilog" enable="1"/>
<File path="./src/ikbd/hd63701/HD63701_EXEC.v" type="file.verilog" enable="1"/>
<File path="./src/ikbd/hd63701/HD63701_MCODE.i" type="file.verilog" enable="1"/>
<File path="./src/ikbd/hd63701/HD63701_MCROM.v" type="file.verilog" enable="1"/>
<File path="./src/ikbd/hd63701/HD63701_SEQ.v" type="file.verilog" enable="1"/>
<File path="./src/ikbd/hd63701/HD63701.v" type="file.verilog" enable="1"/>
<File path="./src/ikbd/rom/MCU_BIROM.v" type="file.verilog" enable="1"/>
<File path="./src/ikbd/rom/ikbd.hex" type="file.other" enable="1"/>
<File path="./src/misc/sdcmd_ctrl.v" type="file.verilog" enable="1"/>
<File path="./src/misc/sd_reader.v" type="file.verilog" enable="1"/>
<File path="./src/misc/sd_fat_reader.v" type="file.verilog" enable="1"/>
<File path="./src/tangnano20k/atarist.cst" type="file.cst" enable="1"/>
<File path="./src/tangnano20k/atarist.sdc" type="file.sdc" enable="1"/>
</FileList>
</Project>