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iostm8s208r8.h
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iostm8s208r8.h
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/*-------------------------------------------------------------------------
* STM8 definitions of SFR registers
*
* Used with STM8 IAR C/C++ Compiler and Assembler.
*
* Copyright 2012 IAR Systems AB.
*
*-----------------------------------------------------------------------*/
#ifndef __IOSTM8S208R8_H__
#define __IOSTM8S208R8_H__
#if (((__TID__ >> 8) & 0x7F) != 0x38) /* 0x38 = 56 dec */
#error This file should only be compiled by STM8 IAR compiler and assembler
#endif
/*-------------------------------------------------------------------------
* I/O register macros
*-----------------------------------------------------------------------*/
#include "io_macros.h"
#ifdef __IAR_SYSTEMS_ICC__
#pragma system_include
#pragma language=save
#pragma language=extended
#endif
/*-------------------------------------------------------------------------
* Port A register definitions
*-----------------------------------------------------------------------*/
/* Port A data output latch register */
#ifdef __IAR_SYSTEMS_ICC__
typedef struct
{
unsigned char ODR0 : 1;
unsigned char ODR1 : 1;
unsigned char ODR2 : 1;
unsigned char ODR3 : 1;
unsigned char ODR4 : 1;
unsigned char ODR5 : 1;
unsigned char ODR6 : 1;
unsigned char ODR7 : 1;
} __BITS_PA_ODR;
#endif
__IO_REG8_BIT(PA_ODR, 0x5000, __READ_WRITE, __BITS_PA_ODR);
/* Port A input pin value register */
#ifdef __IAR_SYSTEMS_ICC__
typedef struct
{
unsigned char IDR0 : 1;
unsigned char IDR1 : 1;
unsigned char IDR2 : 1;
unsigned char IDR3 : 1;
unsigned char IDR4 : 1;
unsigned char IDR5 : 1;
unsigned char IDR6 : 1;
unsigned char IDR7 : 1;
} __BITS_PA_IDR;
#endif
__IO_REG8_BIT(PA_IDR, 0x5001, __READ, __BITS_PA_IDR);
/* Port A data direction register */
#ifdef __IAR_SYSTEMS_ICC__
typedef struct
{
unsigned char DDR0 : 1;
unsigned char DDR1 : 1;
unsigned char DDR2 : 1;
unsigned char DDR3 : 1;
unsigned char DDR4 : 1;
unsigned char DDR5 : 1;
unsigned char DDR6 : 1;
unsigned char DDR7 : 1;
} __BITS_PA_DDR;
#endif
__IO_REG8_BIT(PA_DDR, 0x5002, __READ_WRITE, __BITS_PA_DDR);
/* Port A control register 1 */
#ifdef __IAR_SYSTEMS_ICC__
typedef struct
{
unsigned char C10 : 1;
unsigned char C11 : 1;
unsigned char C12 : 1;
unsigned char C13 : 1;
unsigned char C14 : 1;
unsigned char C15 : 1;
unsigned char C16 : 1;
unsigned char C17 : 1;
} __BITS_PA_CR1;
#endif
__IO_REG8_BIT(PA_CR1, 0x5003, __READ_WRITE, __BITS_PA_CR1);
/* Port A control register 2 */
#ifdef __IAR_SYSTEMS_ICC__
typedef struct
{
unsigned char C20 : 1;
unsigned char C21 : 1;
unsigned char C22 : 1;
unsigned char C23 : 1;
unsigned char C24 : 1;
unsigned char C25 : 1;
unsigned char C26 : 1;
unsigned char C27 : 1;
} __BITS_PA_CR2;
#endif
__IO_REG8_BIT(PA_CR2, 0x5004, __READ_WRITE, __BITS_PA_CR2);
/*-------------------------------------------------------------------------
* Port A bit fields
*-----------------------------------------------------------------------*/
#ifdef __IAR_SYSTEMS_ICC__
#define PA_ODR_ODR0 PA_ODR_bit.ODR0
#define PA_ODR_ODR1 PA_ODR_bit.ODR1
#define PA_ODR_ODR2 PA_ODR_bit.ODR2
#define PA_ODR_ODR3 PA_ODR_bit.ODR3
#define PA_ODR_ODR4 PA_ODR_bit.ODR4
#define PA_ODR_ODR5 PA_ODR_bit.ODR5
#define PA_ODR_ODR6 PA_ODR_bit.ODR6
#define PA_ODR_ODR7 PA_ODR_bit.ODR7
#define PA_IDR_IDR0 PA_IDR_bit.IDR0
#define PA_IDR_IDR1 PA_IDR_bit.IDR1
#define PA_IDR_IDR2 PA_IDR_bit.IDR2
#define PA_IDR_IDR3 PA_IDR_bit.IDR3
#define PA_IDR_IDR4 PA_IDR_bit.IDR4
#define PA_IDR_IDR5 PA_IDR_bit.IDR5
#define PA_IDR_IDR6 PA_IDR_bit.IDR6
#define PA_IDR_IDR7 PA_IDR_bit.IDR7
#define PA_DDR_DDR0 PA_DDR_bit.DDR0
#define PA_DDR_DDR1 PA_DDR_bit.DDR1
#define PA_DDR_DDR2 PA_DDR_bit.DDR2
#define PA_DDR_DDR3 PA_DDR_bit.DDR3
#define PA_DDR_DDR4 PA_DDR_bit.DDR4
#define PA_DDR_DDR5 PA_DDR_bit.DDR5
#define PA_DDR_DDR6 PA_DDR_bit.DDR6
#define PA_DDR_DDR7 PA_DDR_bit.DDR7
#define PA_CR1_C10 PA_CR1_bit.C10
#define PA_CR1_C11 PA_CR1_bit.C11
#define PA_CR1_C12 PA_CR1_bit.C12
#define PA_CR1_C13 PA_CR1_bit.C13
#define PA_CR1_C14 PA_CR1_bit.C14
#define PA_CR1_C15 PA_CR1_bit.C15
#define PA_CR1_C16 PA_CR1_bit.C16
#define PA_CR1_C17 PA_CR1_bit.C17
#define PA_CR2_C20 PA_CR2_bit.C20
#define PA_CR2_C21 PA_CR2_bit.C21
#define PA_CR2_C22 PA_CR2_bit.C22
#define PA_CR2_C23 PA_CR2_bit.C23
#define PA_CR2_C24 PA_CR2_bit.C24
#define PA_CR2_C25 PA_CR2_bit.C25
#define PA_CR2_C26 PA_CR2_bit.C26
#define PA_CR2_C27 PA_CR2_bit.C27
#endif
/*-------------------------------------------------------------------------
* Port A bit masks
*-----------------------------------------------------------------------*/
#define MASK_PA_ODR_ODR0 0x01
#define MASK_PA_ODR_ODR1 0x02
#define MASK_PA_ODR_ODR2 0x04
#define MASK_PA_ODR_ODR3 0x08
#define MASK_PA_ODR_ODR4 0x10
#define MASK_PA_ODR_ODR5 0x20
#define MASK_PA_ODR_ODR6 0x40
#define MASK_PA_ODR_ODR7 0x80
#define MASK_PA_IDR_IDR0 0x01
#define MASK_PA_IDR_IDR1 0x02
#define MASK_PA_IDR_IDR2 0x04
#define MASK_PA_IDR_IDR3 0x08
#define MASK_PA_IDR_IDR4 0x10
#define MASK_PA_IDR_IDR5 0x20
#define MASK_PA_IDR_IDR6 0x40
#define MASK_PA_IDR_IDR7 0x80
#define MASK_PA_DDR_DDR0 0x01
#define MASK_PA_DDR_DDR1 0x02
#define MASK_PA_DDR_DDR2 0x04
#define MASK_PA_DDR_DDR3 0x08
#define MASK_PA_DDR_DDR4 0x10
#define MASK_PA_DDR_DDR5 0x20
#define MASK_PA_DDR_DDR6 0x40
#define MASK_PA_DDR_DDR7 0x80
#define MASK_PA_CR1_C10 0x01
#define MASK_PA_CR1_C11 0x02
#define MASK_PA_CR1_C12 0x04
#define MASK_PA_CR1_C13 0x08
#define MASK_PA_CR1_C14 0x10
#define MASK_PA_CR1_C15 0x20
#define MASK_PA_CR1_C16 0x40
#define MASK_PA_CR1_C17 0x80
#define MASK_PA_CR2_C20 0x01
#define MASK_PA_CR2_C21 0x02
#define MASK_PA_CR2_C22 0x04
#define MASK_PA_CR2_C23 0x08
#define MASK_PA_CR2_C24 0x10
#define MASK_PA_CR2_C25 0x20
#define MASK_PA_CR2_C26 0x40
#define MASK_PA_CR2_C27 0x80
/*-------------------------------------------------------------------------
* Port B register definitions
*-----------------------------------------------------------------------*/
/* Port B data output latch register */
#ifdef __IAR_SYSTEMS_ICC__
typedef struct
{
unsigned char ODR0 : 1;
unsigned char ODR1 : 1;
unsigned char ODR2 : 1;
unsigned char ODR3 : 1;
unsigned char ODR4 : 1;
unsigned char ODR5 : 1;
unsigned char ODR6 : 1;
unsigned char ODR7 : 1;
} __BITS_PB_ODR;
#endif
__IO_REG8_BIT(PB_ODR, 0x5005, __READ_WRITE, __BITS_PB_ODR);
/* Port B input pin value register */
#ifdef __IAR_SYSTEMS_ICC__
typedef struct
{
unsigned char IDR0 : 1;
unsigned char IDR1 : 1;
unsigned char IDR2 : 1;
unsigned char IDR3 : 1;
unsigned char IDR4 : 1;
unsigned char IDR5 : 1;
unsigned char IDR6 : 1;
unsigned char IDR7 : 1;
} __BITS_PB_IDR;
#endif
__IO_REG8_BIT(PB_IDR, 0x5006, __READ, __BITS_PB_IDR);
/* Port B data direction register */
#ifdef __IAR_SYSTEMS_ICC__
typedef struct
{
unsigned char DDR0 : 1;
unsigned char DDR1 : 1;
unsigned char DDR2 : 1;
unsigned char DDR3 : 1;
unsigned char DDR4 : 1;
unsigned char DDR5 : 1;
unsigned char DDR6 : 1;
unsigned char DDR7 : 1;
} __BITS_PB_DDR;
#endif
__IO_REG8_BIT(PB_DDR, 0x5007, __READ_WRITE, __BITS_PB_DDR);
/* Port B control register 1 */
#ifdef __IAR_SYSTEMS_ICC__
typedef struct
{
unsigned char C10 : 1;
unsigned char C11 : 1;
unsigned char C12 : 1;
unsigned char C13 : 1;
unsigned char C14 : 1;
unsigned char C15 : 1;
unsigned char C16 : 1;
unsigned char C17 : 1;
} __BITS_PB_CR1;
#endif
__IO_REG8_BIT(PB_CR1, 0x5008, __READ_WRITE, __BITS_PB_CR1);
/* Port B control register 2 */
#ifdef __IAR_SYSTEMS_ICC__
typedef struct
{
unsigned char C20 : 1;
unsigned char C21 : 1;
unsigned char C22 : 1;
unsigned char C23 : 1;
unsigned char C24 : 1;
unsigned char C25 : 1;
unsigned char C26 : 1;
unsigned char C27 : 1;
} __BITS_PB_CR2;
#endif
__IO_REG8_BIT(PB_CR2, 0x5009, __READ_WRITE, __BITS_PB_CR2);
/*-------------------------------------------------------------------------
* Port B bit fields
*-----------------------------------------------------------------------*/
#ifdef __IAR_SYSTEMS_ICC__
#define PB_ODR_ODR0 PB_ODR_bit.ODR0
#define PB_ODR_ODR1 PB_ODR_bit.ODR1
#define PB_ODR_ODR2 PB_ODR_bit.ODR2
#define PB_ODR_ODR3 PB_ODR_bit.ODR3
#define PB_ODR_ODR4 PB_ODR_bit.ODR4
#define PB_ODR_ODR5 PB_ODR_bit.ODR5
#define PB_ODR_ODR6 PB_ODR_bit.ODR6
#define PB_ODR_ODR7 PB_ODR_bit.ODR7
#define PB_IDR_IDR0 PB_IDR_bit.IDR0
#define PB_IDR_IDR1 PB_IDR_bit.IDR1
#define PB_IDR_IDR2 PB_IDR_bit.IDR2
#define PB_IDR_IDR3 PB_IDR_bit.IDR3
#define PB_IDR_IDR4 PB_IDR_bit.IDR4
#define PB_IDR_IDR5 PB_IDR_bit.IDR5
#define PB_IDR_IDR6 PB_IDR_bit.IDR6
#define PB_IDR_IDR7 PB_IDR_bit.IDR7
#define PB_DDR_DDR0 PB_DDR_bit.DDR0
#define PB_DDR_DDR1 PB_DDR_bit.DDR1
#define PB_DDR_DDR2 PB_DDR_bit.DDR2
#define PB_DDR_DDR3 PB_DDR_bit.DDR3
#define PB_DDR_DDR4 PB_DDR_bit.DDR4
#define PB_DDR_DDR5 PB_DDR_bit.DDR5
#define PB_DDR_DDR6 PB_DDR_bit.DDR6
#define PB_DDR_DDR7 PB_DDR_bit.DDR7
#define PB_CR1_C10 PB_CR1_bit.C10
#define PB_CR1_C11 PB_CR1_bit.C11
#define PB_CR1_C12 PB_CR1_bit.C12
#define PB_CR1_C13 PB_CR1_bit.C13
#define PB_CR1_C14 PB_CR1_bit.C14
#define PB_CR1_C15 PB_CR1_bit.C15
#define PB_CR1_C16 PB_CR1_bit.C16
#define PB_CR1_C17 PB_CR1_bit.C17
#define PB_CR2_C20 PB_CR2_bit.C20
#define PB_CR2_C21 PB_CR2_bit.C21
#define PB_CR2_C22 PB_CR2_bit.C22
#define PB_CR2_C23 PB_CR2_bit.C23
#define PB_CR2_C24 PB_CR2_bit.C24
#define PB_CR2_C25 PB_CR2_bit.C25
#define PB_CR2_C26 PB_CR2_bit.C26
#define PB_CR2_C27 PB_CR2_bit.C27
#endif
/*-------------------------------------------------------------------------
* Port B bit masks
*-----------------------------------------------------------------------*/
#define MASK_PB_ODR_ODR0 0x01
#define MASK_PB_ODR_ODR1 0x02
#define MASK_PB_ODR_ODR2 0x04
#define MASK_PB_ODR_ODR3 0x08
#define MASK_PB_ODR_ODR4 0x10
#define MASK_PB_ODR_ODR5 0x20
#define MASK_PB_ODR_ODR6 0x40
#define MASK_PB_ODR_ODR7 0x80
#define MASK_PB_IDR_IDR0 0x01
#define MASK_PB_IDR_IDR1 0x02
#define MASK_PB_IDR_IDR2 0x04
#define MASK_PB_IDR_IDR3 0x08
#define MASK_PB_IDR_IDR4 0x10
#define MASK_PB_IDR_IDR5 0x20
#define MASK_PB_IDR_IDR6 0x40
#define MASK_PB_IDR_IDR7 0x80
#define MASK_PB_DDR_DDR0 0x01
#define MASK_PB_DDR_DDR1 0x02
#define MASK_PB_DDR_DDR2 0x04
#define MASK_PB_DDR_DDR3 0x08
#define MASK_PB_DDR_DDR4 0x10
#define MASK_PB_DDR_DDR5 0x20
#define MASK_PB_DDR_DDR6 0x40
#define MASK_PB_DDR_DDR7 0x80
#define MASK_PB_CR1_C10 0x01
#define MASK_PB_CR1_C11 0x02
#define MASK_PB_CR1_C12 0x04
#define MASK_PB_CR1_C13 0x08
#define MASK_PB_CR1_C14 0x10
#define MASK_PB_CR1_C15 0x20
#define MASK_PB_CR1_C16 0x40
#define MASK_PB_CR1_C17 0x80
#define MASK_PB_CR2_C20 0x01
#define MASK_PB_CR2_C21 0x02
#define MASK_PB_CR2_C22 0x04
#define MASK_PB_CR2_C23 0x08
#define MASK_PB_CR2_C24 0x10
#define MASK_PB_CR2_C25 0x20
#define MASK_PB_CR2_C26 0x40
#define MASK_PB_CR2_C27 0x80
/*-------------------------------------------------------------------------
* Port C register definitions
*-----------------------------------------------------------------------*/
/* Port C data output latch register */
#ifdef __IAR_SYSTEMS_ICC__
typedef struct
{
unsigned char ODR0 : 1;
unsigned char ODR1 : 1;
unsigned char ODR2 : 1;
unsigned char ODR3 : 1;
unsigned char ODR4 : 1;
unsigned char ODR5 : 1;
unsigned char ODR6 : 1;
unsigned char ODR7 : 1;
} __BITS_PC_ODR;
#endif
__IO_REG8_BIT(PC_ODR, 0x500A, __READ_WRITE, __BITS_PC_ODR);
/* Port C input pin value register */
#ifdef __IAR_SYSTEMS_ICC__
typedef struct
{
unsigned char IDR0 : 1;
unsigned char IDR1 : 1;
unsigned char IDR2 : 1;
unsigned char IDR3 : 1;
unsigned char IDR4 : 1;
unsigned char IDR5 : 1;
unsigned char IDR6 : 1;
unsigned char IDR7 : 1;
} __BITS_PC_IDR;
#endif
__IO_REG8_BIT(PC_IDR, 0x500B, __READ, __BITS_PC_IDR);
/* Port C data direction register */
#ifdef __IAR_SYSTEMS_ICC__
typedef struct
{
unsigned char DDR0 : 1;
unsigned char DDR1 : 1;
unsigned char DDR2 : 1;
unsigned char DDR3 : 1;
unsigned char DDR4 : 1;
unsigned char DDR5 : 1;
unsigned char DDR6 : 1;
unsigned char DDR7 : 1;
} __BITS_PC_DDR;
#endif
__IO_REG8_BIT(PC_DDR, 0x500C, __READ_WRITE, __BITS_PC_DDR);
/* Port C control register 1 */
#ifdef __IAR_SYSTEMS_ICC__
typedef struct
{
unsigned char C10 : 1;
unsigned char C11 : 1;
unsigned char C12 : 1;
unsigned char C13 : 1;
unsigned char C14 : 1;
unsigned char C15 : 1;
unsigned char C16 : 1;
unsigned char C17 : 1;
} __BITS_PC_CR1;
#endif
__IO_REG8_BIT(PC_CR1, 0x500D, __READ_WRITE, __BITS_PC_CR1);
/* Port C control register 2 */
#ifdef __IAR_SYSTEMS_ICC__
typedef struct
{
unsigned char C20 : 1;
unsigned char C21 : 1;
unsigned char C22 : 1;
unsigned char C23 : 1;
unsigned char C24 : 1;
unsigned char C25 : 1;
unsigned char C26 : 1;
unsigned char C27 : 1;
} __BITS_PC_CR2;
#endif
__IO_REG8_BIT(PC_CR2, 0x500E, __READ_WRITE, __BITS_PC_CR2);
/*-------------------------------------------------------------------------
* Port C bit fields
*-----------------------------------------------------------------------*/
#ifdef __IAR_SYSTEMS_ICC__
#define PC_ODR_ODR0 PC_ODR_bit.ODR0
#define PC_ODR_ODR1 PC_ODR_bit.ODR1
#define PC_ODR_ODR2 PC_ODR_bit.ODR2
#define PC_ODR_ODR3 PC_ODR_bit.ODR3
#define PC_ODR_ODR4 PC_ODR_bit.ODR4
#define PC_ODR_ODR5 PC_ODR_bit.ODR5
#define PC_ODR_ODR6 PC_ODR_bit.ODR6
#define PC_ODR_ODR7 PC_ODR_bit.ODR7
#define PC_IDR_IDR0 PC_IDR_bit.IDR0
#define PC_IDR_IDR1 PC_IDR_bit.IDR1
#define PC_IDR_IDR2 PC_IDR_bit.IDR2
#define PC_IDR_IDR3 PC_IDR_bit.IDR3
#define PC_IDR_IDR4 PC_IDR_bit.IDR4
#define PC_IDR_IDR5 PC_IDR_bit.IDR5
#define PC_IDR_IDR6 PC_IDR_bit.IDR6
#define PC_IDR_IDR7 PC_IDR_bit.IDR7
#define PC_DDR_DDR0 PC_DDR_bit.DDR0
#define PC_DDR_DDR1 PC_DDR_bit.DDR1
#define PC_DDR_DDR2 PC_DDR_bit.DDR2
#define PC_DDR_DDR3 PC_DDR_bit.DDR3
#define PC_DDR_DDR4 PC_DDR_bit.DDR4
#define PC_DDR_DDR5 PC_DDR_bit.DDR5
#define PC_DDR_DDR6 PC_DDR_bit.DDR6
#define PC_DDR_DDR7 PC_DDR_bit.DDR7
#define PC_CR1_C10 PC_CR1_bit.C10
#define PC_CR1_C11 PC_CR1_bit.C11
#define PC_CR1_C12 PC_CR1_bit.C12
#define PC_CR1_C13 PC_CR1_bit.C13
#define PC_CR1_C14 PC_CR1_bit.C14
#define PC_CR1_C15 PC_CR1_bit.C15
#define PC_CR1_C16 PC_CR1_bit.C16
#define PC_CR1_C17 PC_CR1_bit.C17
#define PC_CR2_C20 PC_CR2_bit.C20
#define PC_CR2_C21 PC_CR2_bit.C21
#define PC_CR2_C22 PC_CR2_bit.C22
#define PC_CR2_C23 PC_CR2_bit.C23
#define PC_CR2_C24 PC_CR2_bit.C24
#define PC_CR2_C25 PC_CR2_bit.C25
#define PC_CR2_C26 PC_CR2_bit.C26
#define PC_CR2_C27 PC_CR2_bit.C27
#endif
/*-------------------------------------------------------------------------
* Port C bit masks
*-----------------------------------------------------------------------*/
#define MASK_PC_ODR_ODR0 0x01
#define MASK_PC_ODR_ODR1 0x02
#define MASK_PC_ODR_ODR2 0x04
#define MASK_PC_ODR_ODR3 0x08
#define MASK_PC_ODR_ODR4 0x10
#define MASK_PC_ODR_ODR5 0x20
#define MASK_PC_ODR_ODR6 0x40
#define MASK_PC_ODR_ODR7 0x80
#define MASK_PC_IDR_IDR0 0x01
#define MASK_PC_IDR_IDR1 0x02
#define MASK_PC_IDR_IDR2 0x04
#define MASK_PC_IDR_IDR3 0x08
#define MASK_PC_IDR_IDR4 0x10
#define MASK_PC_IDR_IDR5 0x20
#define MASK_PC_IDR_IDR6 0x40
#define MASK_PC_IDR_IDR7 0x80
#define MASK_PC_DDR_DDR0 0x01
#define MASK_PC_DDR_DDR1 0x02
#define MASK_PC_DDR_DDR2 0x04
#define MASK_PC_DDR_DDR3 0x08
#define MASK_PC_DDR_DDR4 0x10
#define MASK_PC_DDR_DDR5 0x20
#define MASK_PC_DDR_DDR6 0x40
#define MASK_PC_DDR_DDR7 0x80
#define MASK_PC_CR1_C10 0x01
#define MASK_PC_CR1_C11 0x02
#define MASK_PC_CR1_C12 0x04
#define MASK_PC_CR1_C13 0x08
#define MASK_PC_CR1_C14 0x10
#define MASK_PC_CR1_C15 0x20
#define MASK_PC_CR1_C16 0x40
#define MASK_PC_CR1_C17 0x80
#define MASK_PC_CR2_C20 0x01
#define MASK_PC_CR2_C21 0x02
#define MASK_PC_CR2_C22 0x04
#define MASK_PC_CR2_C23 0x08
#define MASK_PC_CR2_C24 0x10
#define MASK_PC_CR2_C25 0x20
#define MASK_PC_CR2_C26 0x40
#define MASK_PC_CR2_C27 0x80
/*-------------------------------------------------------------------------
* Port D register definitions
*-----------------------------------------------------------------------*/
/* Port D data output latch register */
#ifdef __IAR_SYSTEMS_ICC__
typedef struct
{
unsigned char ODR0 : 1;
unsigned char ODR1 : 1;
unsigned char ODR2 : 1;
unsigned char ODR3 : 1;
unsigned char ODR4 : 1;
unsigned char ODR5 : 1;
unsigned char ODR6 : 1;
unsigned char ODR7 : 1;
} __BITS_PD_ODR;
#endif
__IO_REG8_BIT(PD_ODR, 0x500F, __READ_WRITE, __BITS_PD_ODR);
/* Port D input pin value register */
#ifdef __IAR_SYSTEMS_ICC__
typedef struct
{
unsigned char IDR0 : 1;
unsigned char IDR1 : 1;
unsigned char IDR2 : 1;
unsigned char IDR3 : 1;
unsigned char IDR4 : 1;
unsigned char IDR5 : 1;
unsigned char IDR6 : 1;
unsigned char IDR7 : 1;
} __BITS_PD_IDR;
#endif
__IO_REG8_BIT(PD_IDR, 0x5010, __READ, __BITS_PD_IDR);
/* Port D data direction register */
#ifdef __IAR_SYSTEMS_ICC__
typedef struct
{
unsigned char DDR0 : 1;
unsigned char DDR1 : 1;
unsigned char DDR2 : 1;
unsigned char DDR3 : 1;
unsigned char DDR4 : 1;
unsigned char DDR5 : 1;
unsigned char DDR6 : 1;
unsigned char DDR7 : 1;
} __BITS_PD_DDR;
#endif
__IO_REG8_BIT(PD_DDR, 0x5011, __READ_WRITE, __BITS_PD_DDR);
/* Port D control register 1 */
#ifdef __IAR_SYSTEMS_ICC__
typedef struct
{
unsigned char C10 : 1;
unsigned char C11 : 1;
unsigned char C12 : 1;
unsigned char C13 : 1;
unsigned char C14 : 1;
unsigned char C15 : 1;
unsigned char C16 : 1;
unsigned char C17 : 1;
} __BITS_PD_CR1;
#endif
__IO_REG8_BIT(PD_CR1, 0x5012, __READ_WRITE, __BITS_PD_CR1);
/* Port D control register 2 */
#ifdef __IAR_SYSTEMS_ICC__
typedef struct
{
unsigned char C20 : 1;
unsigned char C21 : 1;
unsigned char C22 : 1;
unsigned char C23 : 1;
unsigned char C24 : 1;
unsigned char C25 : 1;
unsigned char C26 : 1;
unsigned char C27 : 1;
} __BITS_PD_CR2;
#endif
__IO_REG8_BIT(PD_CR2, 0x5013, __READ_WRITE, __BITS_PD_CR2);
/*-------------------------------------------------------------------------
* Port D bit fields
*-----------------------------------------------------------------------*/
#ifdef __IAR_SYSTEMS_ICC__
#define PD_ODR_ODR0 PD_ODR_bit.ODR0
#define PD_ODR_ODR1 PD_ODR_bit.ODR1
#define PD_ODR_ODR2 PD_ODR_bit.ODR2
#define PD_ODR_ODR3 PD_ODR_bit.ODR3
#define PD_ODR_ODR4 PD_ODR_bit.ODR4
#define PD_ODR_ODR5 PD_ODR_bit.ODR5
#define PD_ODR_ODR6 PD_ODR_bit.ODR6
#define PD_ODR_ODR7 PD_ODR_bit.ODR7
#define PD_IDR_IDR0 PD_IDR_bit.IDR0
#define PD_IDR_IDR1 PD_IDR_bit.IDR1
#define PD_IDR_IDR2 PD_IDR_bit.IDR2
#define PD_IDR_IDR3 PD_IDR_bit.IDR3
#define PD_IDR_IDR4 PD_IDR_bit.IDR4
#define PD_IDR_IDR5 PD_IDR_bit.IDR5
#define PD_IDR_IDR6 PD_IDR_bit.IDR6
#define PD_IDR_IDR7 PD_IDR_bit.IDR7
#define PD_DDR_DDR0 PD_DDR_bit.DDR0
#define PD_DDR_DDR1 PD_DDR_bit.DDR1
#define PD_DDR_DDR2 PD_DDR_bit.DDR2
#define PD_DDR_DDR3 PD_DDR_bit.DDR3
#define PD_DDR_DDR4 PD_DDR_bit.DDR4
#define PD_DDR_DDR5 PD_DDR_bit.DDR5
#define PD_DDR_DDR6 PD_DDR_bit.DDR6
#define PD_DDR_DDR7 PD_DDR_bit.DDR7
#define PD_CR1_C10 PD_CR1_bit.C10
#define PD_CR1_C11 PD_CR1_bit.C11
#define PD_CR1_C12 PD_CR1_bit.C12
#define PD_CR1_C13 PD_CR1_bit.C13
#define PD_CR1_C14 PD_CR1_bit.C14
#define PD_CR1_C15 PD_CR1_bit.C15
#define PD_CR1_C16 PD_CR1_bit.C16
#define PD_CR1_C17 PD_CR1_bit.C17
#define PD_CR2_C20 PD_CR2_bit.C20
#define PD_CR2_C21 PD_CR2_bit.C21
#define PD_CR2_C22 PD_CR2_bit.C22
#define PD_CR2_C23 PD_CR2_bit.C23
#define PD_CR2_C24 PD_CR2_bit.C24
#define PD_CR2_C25 PD_CR2_bit.C25
#define PD_CR2_C26 PD_CR2_bit.C26
#define PD_CR2_C27 PD_CR2_bit.C27
#endif
/*-------------------------------------------------------------------------
* Port D bit masks
*-----------------------------------------------------------------------*/
#define MASK_PD_ODR_ODR0 0x01
#define MASK_PD_ODR_ODR1 0x02
#define MASK_PD_ODR_ODR2 0x04
#define MASK_PD_ODR_ODR3 0x08
#define MASK_PD_ODR_ODR4 0x10
#define MASK_PD_ODR_ODR5 0x20
#define MASK_PD_ODR_ODR6 0x40
#define MASK_PD_ODR_ODR7 0x80
#define MASK_PD_IDR_IDR0 0x01
#define MASK_PD_IDR_IDR1 0x02
#define MASK_PD_IDR_IDR2 0x04
#define MASK_PD_IDR_IDR3 0x08
#define MASK_PD_IDR_IDR4 0x10
#define MASK_PD_IDR_IDR5 0x20
#define MASK_PD_IDR_IDR6 0x40
#define MASK_PD_IDR_IDR7 0x80
#define MASK_PD_DDR_DDR0 0x01
#define MASK_PD_DDR_DDR1 0x02
#define MASK_PD_DDR_DDR2 0x04
#define MASK_PD_DDR_DDR3 0x08
#define MASK_PD_DDR_DDR4 0x10
#define MASK_PD_DDR_DDR5 0x20
#define MASK_PD_DDR_DDR6 0x40
#define MASK_PD_DDR_DDR7 0x80
#define MASK_PD_CR1_C10 0x01
#define MASK_PD_CR1_C11 0x02
#define MASK_PD_CR1_C12 0x04
#define MASK_PD_CR1_C13 0x08
#define MASK_PD_CR1_C14 0x10
#define MASK_PD_CR1_C15 0x20
#define MASK_PD_CR1_C16 0x40
#define MASK_PD_CR1_C17 0x80
#define MASK_PD_CR2_C20 0x01
#define MASK_PD_CR2_C21 0x02
#define MASK_PD_CR2_C22 0x04
#define MASK_PD_CR2_C23 0x08
#define MASK_PD_CR2_C24 0x10
#define MASK_PD_CR2_C25 0x20
#define MASK_PD_CR2_C26 0x40
#define MASK_PD_CR2_C27 0x80
/*-------------------------------------------------------------------------
* Port E register definitions
*-----------------------------------------------------------------------*/
/* Port E data output latch register */
#ifdef __IAR_SYSTEMS_ICC__
typedef struct
{
unsigned char ODR0 : 1;
unsigned char ODR1 : 1;
unsigned char ODR2 : 1;
unsigned char ODR3 : 1;
unsigned char ODR4 : 1;
unsigned char ODR5 : 1;
unsigned char ODR6 : 1;
unsigned char ODR7 : 1;
} __BITS_PE_ODR;
#endif
__IO_REG8_BIT(PE_ODR, 0x5014, __READ_WRITE, __BITS_PE_ODR);
/* Port E input pin value register */
#ifdef __IAR_SYSTEMS_ICC__
typedef struct
{
unsigned char IDR0 : 1;
unsigned char IDR1 : 1;
unsigned char IDR2 : 1;
unsigned char IDR3 : 1;
unsigned char IDR4 : 1;
unsigned char IDR5 : 1;
unsigned char IDR6 : 1;
unsigned char IDR7 : 1;
} __BITS_PE_IDR;
#endif
__IO_REG8_BIT(PE_IDR, 0x5015, __READ, __BITS_PE_IDR);
/* Port E data direction register */
#ifdef __IAR_SYSTEMS_ICC__
typedef struct
{
unsigned char DDR0 : 1;
unsigned char DDR1 : 1;
unsigned char DDR2 : 1;
unsigned char DDR3 : 1;
unsigned char DDR4 : 1;
unsigned char DDR5 : 1;
unsigned char DDR6 : 1;
unsigned char DDR7 : 1;
} __BITS_PE_DDR;
#endif
__IO_REG8_BIT(PE_DDR, 0x5016, __READ_WRITE, __BITS_PE_DDR);
/* Port E control register 1 */
#ifdef __IAR_SYSTEMS_ICC__
typedef struct
{
unsigned char C10 : 1;
unsigned char C11 : 1;
unsigned char C12 : 1;
unsigned char C13 : 1;
unsigned char C14 : 1;
unsigned char C15 : 1;
unsigned char C16 : 1;
unsigned char C17 : 1;
} __BITS_PE_CR1;
#endif
__IO_REG8_BIT(PE_CR1, 0x5017, __READ_WRITE, __BITS_PE_CR1);
/* Port E control register 2 */
#ifdef __IAR_SYSTEMS_ICC__
typedef struct
{
unsigned char C20 : 1;
unsigned char C21 : 1;
unsigned char C22 : 1;
unsigned char C23 : 1;
unsigned char C24 : 1;
unsigned char C25 : 1;
unsigned char C26 : 1;
unsigned char C27 : 1;
} __BITS_PE_CR2;
#endif
__IO_REG8_BIT(PE_CR2, 0x5018, __READ_WRITE, __BITS_PE_CR2);
/*-------------------------------------------------------------------------
* Port E bit fields
*-----------------------------------------------------------------------*/
#ifdef __IAR_SYSTEMS_ICC__
#define PE_ODR_ODR0 PE_ODR_bit.ODR0
#define PE_ODR_ODR1 PE_ODR_bit.ODR1
#define PE_ODR_ODR2 PE_ODR_bit.ODR2
#define PE_ODR_ODR3 PE_ODR_bit.ODR3
#define PE_ODR_ODR4 PE_ODR_bit.ODR4
#define PE_ODR_ODR5 PE_ODR_bit.ODR5
#define PE_ODR_ODR6 PE_ODR_bit.ODR6
#define PE_ODR_ODR7 PE_ODR_bit.ODR7
#define PE_IDR_IDR0 PE_IDR_bit.IDR0
#define PE_IDR_IDR1 PE_IDR_bit.IDR1
#define PE_IDR_IDR2 PE_IDR_bit.IDR2
#define PE_IDR_IDR3 PE_IDR_bit.IDR3
#define PE_IDR_IDR4 PE_IDR_bit.IDR4
#define PE_IDR_IDR5 PE_IDR_bit.IDR5
#define PE_IDR_IDR6 PE_IDR_bit.IDR6
#define PE_IDR_IDR7 PE_IDR_bit.IDR7
#define PE_DDR_DDR0 PE_DDR_bit.DDR0
#define PE_DDR_DDR1 PE_DDR_bit.DDR1
#define PE_DDR_DDR2 PE_DDR_bit.DDR2
#define PE_DDR_DDR3 PE_DDR_bit.DDR3
#define PE_DDR_DDR4 PE_DDR_bit.DDR4
#define PE_DDR_DDR5 PE_DDR_bit.DDR5
#define PE_DDR_DDR6 PE_DDR_bit.DDR6
#define PE_DDR_DDR7 PE_DDR_bit.DDR7
#define PE_CR1_C10 PE_CR1_bit.C10
#define PE_CR1_C11 PE_CR1_bit.C11
#define PE_CR1_C12 PE_CR1_bit.C12
#define PE_CR1_C13 PE_CR1_bit.C13
#define PE_CR1_C14 PE_CR1_bit.C14
#define PE_CR1_C15 PE_CR1_bit.C15
#define PE_CR1_C16 PE_CR1_bit.C16
#define PE_CR1_C17 PE_CR1_bit.C17
#define PE_CR2_C20 PE_CR2_bit.C20
#define PE_CR2_C21 PE_CR2_bit.C21
#define PE_CR2_C22 PE_CR2_bit.C22
#define PE_CR2_C23 PE_CR2_bit.C23
#define PE_CR2_C24 PE_CR2_bit.C24
#define PE_CR2_C25 PE_CR2_bit.C25
#define PE_CR2_C26 PE_CR2_bit.C26
#define PE_CR2_C27 PE_CR2_bit.C27
#endif
/*-------------------------------------------------------------------------
* Port E bit masks
*-----------------------------------------------------------------------*/
#define MASK_PE_ODR_ODR0 0x01
#define MASK_PE_ODR_ODR1 0x02
#define MASK_PE_ODR_ODR2 0x04
#define MASK_PE_ODR_ODR3 0x08
#define MASK_PE_ODR_ODR4 0x10
#define MASK_PE_ODR_ODR5 0x20
#define MASK_PE_ODR_ODR6 0x40
#define MASK_PE_ODR_ODR7 0x80
#define MASK_PE_IDR_IDR0 0x01
#define MASK_PE_IDR_IDR1 0x02
#define MASK_PE_IDR_IDR2 0x04
#define MASK_PE_IDR_IDR3 0x08
#define MASK_PE_IDR_IDR4 0x10
#define MASK_PE_IDR_IDR5 0x20
#define MASK_PE_IDR_IDR6 0x40
#define MASK_PE_IDR_IDR7 0x80
#define MASK_PE_DDR_DDR0 0x01
#define MASK_PE_DDR_DDR1 0x02
#define MASK_PE_DDR_DDR2 0x04
#define MASK_PE_DDR_DDR3 0x08
#define MASK_PE_DDR_DDR4 0x10
#define MASK_PE_DDR_DDR5 0x20
#define MASK_PE_DDR_DDR6 0x40
#define MASK_PE_DDR_DDR7 0x80
#define MASK_PE_CR1_C10 0x01
#define MASK_PE_CR1_C11 0x02
#define MASK_PE_CR1_C12 0x04
#define MASK_PE_CR1_C13 0x08
#define MASK_PE_CR1_C14 0x10
#define MASK_PE_CR1_C15 0x20
#define MASK_PE_CR1_C16 0x40
#define MASK_PE_CR1_C17 0x80
#define MASK_PE_CR2_C20 0x01
#define MASK_PE_CR2_C21 0x02
#define MASK_PE_CR2_C22 0x04
#define MASK_PE_CR2_C23 0x08
#define MASK_PE_CR2_C24 0x10
#define MASK_PE_CR2_C25 0x20
#define MASK_PE_CR2_C26 0x40
#define MASK_PE_CR2_C27 0x80
/*-------------------------------------------------------------------------
* Port F register definitions
*-----------------------------------------------------------------------*/
/* Port F data output latch register */
#ifdef __IAR_SYSTEMS_ICC__
typedef struct
{
unsigned char ODR0 : 1;
unsigned char ODR1 : 1;
unsigned char ODR2 : 1;
unsigned char ODR3 : 1;
unsigned char ODR4 : 1;
unsigned char ODR5 : 1;
unsigned char ODR6 : 1;
unsigned char ODR7 : 1;
} __BITS_PF_ODR;
#endif
__IO_REG8_BIT(PF_ODR, 0x5019, __READ_WRITE, __BITS_PF_ODR);
/* Port F input pin value register */
#ifdef __IAR_SYSTEMS_ICC__
typedef struct
{
unsigned char IDR0 : 1;
unsigned char IDR1 : 1;
unsigned char IDR2 : 1;
unsigned char IDR3 : 1;
unsigned char IDR4 : 1;
unsigned char IDR5 : 1;
unsigned char IDR6 : 1;
unsigned char IDR7 : 1;
} __BITS_PF_IDR;
#endif
__IO_REG8_BIT(PF_IDR, 0x501A, __READ, __BITS_PF_IDR);
/* Port F data direction register */
#ifdef __IAR_SYSTEMS_ICC__
typedef struct
{
unsigned char DDR0 : 1;
unsigned char DDR1 : 1;
unsigned char DDR2 : 1;
unsigned char DDR3 : 1;
unsigned char DDR4 : 1;
unsigned char DDR5 : 1;
unsigned char DDR6 : 1;