Cannot create project for u280

[hecmay]

mkdir -p synthesis_results_HBM
cp Makefile.synthesis synthesis_results_HBM/Makefile
sed -i 's/xcvu9p-flga2104-2l-e/xcu280-fsvh2892-2L-e/g' synthesis_results_HBM/Makefile
make -C synthesis_results_HBM -j4
make[3]: Entering directory '/work/shared/users/phd/sx233/Limago/submodules/fpga-network-stack-core/synthesis_results_HBM'
IP Completed: TOE_hls_prj IPERF2_TCP_hls_prj ECHOSERVER_hls_prj ARP_hls_prj ETH_inserter_hls_prj ICMP_hls_prj PKT_HANDLER_prj userAbstraction_prj portHandler_prj
make[3]: Leaving directory '/work/shared/users/phd/sx233/Limago/submodules/fpga-network-stack-core/synthesis_results_HBM'
make[2]: Leaving directory '/work/shared/users/phd/sx233/Limago/submodules/fpga-network-stack-core'
make[1]: Leaving directory '/work/shared/users/phd/sx233/Limago/submodules'
#rm -rf project/alveou280-fns-single-toe-iperf
vivado -notrace -mode batch -source scripts/common_scripts/create_project.tcl -tclargs alveou280-fns-single-toe-iperf

****** Vivado v2018.3 (64-bit)
  **** SW Build 2405991 on Thu Dec  6 23:36:41 MST 2018
  **** IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source scripts/common_scripts/create_project.tcl -notrace
ERROR: [Board 49-71] The board_part definition was not found for xilinx.com:au280:part0:1.1. The project's board_part property was not set, but the project's part property was set to xcu280-fsvh2892-2L-e. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command. Check if board.repoPaths parameter is set and the board_part is installed from the tcl app store.
INFO: [Common 17-206] Exiting Vivado at Fri Nov 20 22:03:36 2020...
make: *** [Makefile:33: create_prj_alveou280-fns-single-toe-iperf] Error 1

[hecmay]

The au280 board data files have been added to Vivado 2018.3 according to this AR: https://www.xilinx.com/support/answers/72033.html

[mariodruiz]

Yes, you need to install the Alveo U280 board files.

Copy these files https://github.com/Xilinx/XilinxBoardStore/tree/master/boards/Xilinx/au280 into <Vivado Install path>/2018.3/data/boards/board_files

[hecmay]

@mariodruiz Thanks for you help. Unfortunately, the error still comes up when I copied those board files to the folder.

I have the following scripts added to Vivado_init.tcl. And I can make sure that it has been sourced during the initialization.

set_param board.repoPaths [list "/work/shared/common/xilinx/Vivado/XilinxBoardStore"]
set_param ced.repoPaths [list "/work/shared/common/xilinx/Vivado/XilinxCEDStore"]

The board data files have also been copied as you suggested

$ ls /work/shared/common/xilinx/Vivado/2018.3/data/boards/board_files/au280/
1.0  1.1

Should I re-run the make ips command to generate the IPs again?

[mariodruiz]

@hecmay
I would suggest to close old terminals and open a new one a rerun make <project>.
If you are still getting errors, you should create a project manually and try to add the board.

[hecmay]

It seems that the files cannot be imported somehow. This is what I saw in the log

WARNING: [Board 49-26] cannot add Board Part xilinx.com:au280:part0:1.0 available at /work/shared/common/xilinx/Vivado/XilinxBoardStore/boards/Xilinx/au280/1.0/board.xml as part xcu280-fsvh2892-2l-e-es1 specified in board_part file
 is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:au280:part0:1.1 available at /work/shared/common/xilinx/Vivado/XilinxBoardStore/boards/Xilinx/au280/1.1/board.xml as part xcu280-fsvh2892-2l-e-es1 specified in board_part file
 is either invalid or not available

[mariodruiz]

I have not seen that issue. Can you post it in the Xilinx forums?