porting dnnweaver to xilinx zynq xc7z020 board，I have encountered some problems.

[zhang007z]

hi Hardik Sharma
I recently wanted to port dnnweaver to the xilinx zynq xc7z020 board, according to the previous answer:
//------------------------------------------------------------------------------------//
The pci_cl_ctrl* AXI-Lite interface is used by CPU to write to registers in the FPGA.
The pci_cl_data* AXI4-Full interface is used to write from CPU to the BRAM in the FPGA.
The cl_ddr* AXI4-Full interface is used by dnnweaver accelerator on the FPGA fabric to write to/read from a shared DDR space.
You won't need to change any RTL for this. If the FPGA doesn't have enough resources, you can reduce the systolic array dimensions from the 32x32 default value to 16x16 or 8x8.
//------------------------------------------------------------------------------------//
There are a few questions below:
1.pci_cl_ctrl (AXI-Lite interface) What data is sent by the CPU to the FPGA through this interface, is it a control instruction? I see the document. Is this the instructions of the macro-dataflow virtual machine?

2.pci_cl_data (AXI4-Full interface)Is this the CPU that sends image data to the BRAM in the FPGA? What is the format of this image data? (such as YUV420)
Can it to be recognition if the image is 1080 resolution? How speed is the recognition?

3.The cl_ddr (AXI4-Full interface)This explanation is clearer, mainly in communication with DDR.

4. Can you talk about how does the upper layer software call the pci_cl_ctrl and pci_cl_data?
   What is the process?? Give an example, thank you.

5, if the FPGA resources are limited, I see your previous answer is to put systolic array dimensions from the 32x32 default value to 16x16 or 8x8, as follows, can I modify the code of cl_wrapper.v below?
  // Systolic Array
    Parameter integer ARRAY_N = 64, modified to 16
    Parameter integer ARRAY_M = 64, modified to 16

6.Because my image is directly in DDR, if I don't transfer images to dnnweaver through Xilinx PCIe DMA interface, I directly send image data to dnnweaver FPGA in memory.Don't know if this is ok?Also I don't know what image format you are using? I don't know what format your image is in memory?

thank you for helping me in advance.