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The printing logic is currently implemented in flexpret/scripts/hdl/simify_verilog.py which monitors the tohost register in Verilog. As we aim to support more advanced printing (such as printf), it would make sense to move the printing logic to the emulator instead of putting everything in flexpret/scripts/hdl/simify_verilog.py, which should ideally stay small.
The text was updated successfully, but these errors were encountered:
The printing logic is currently implemented in
flexpret/scripts/hdl/simify_verilog.py
which monitors thetohost
register in Verilog. As we aim to support more advanced printing (such asprintf
), it would make sense to move the printing logic to the emulator instead of putting everything inflexpret/scripts/hdl/simify_verilog.py
, which should ideally stay small.The text was updated successfully, but these errors were encountered: