{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":473579288,"defaultBranch":"master","name":"linux","ownerLogin":"intel-lab-lkp","currentUserCanPush":false,"isFork":true,"isEmpty":false,"createdAt":"2022-03-24T11:36:07.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/82017130?v=4","public":true,"private":false,"isOrgOwned":false},"refInfo":{"name":"","listCacheKey":"v0:1727478621.0","currentOid":""},"activityList":{"items":[{"before":null,"after":"3ca630546ccc1d0fa4c04fe61b0416a9723477ac","ref":"refs/heads/Mario-Limonciello/drm-amd-display-switch-amdgpu_dm_connector-to-use-struct-drm_edid/20240928-070822","pushedAt":"2024-09-27T23:10:21.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"intel-lab-lkp","name":null,"path":"/intel-lab-lkp","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/82017130?s=80&v=4"},"commit":{"message":"drm/amd/display: Fetch the EDID from _DDC if available for eDP\n\nSome manufacturers have intentionally put an EDID that differs from\nthe EDID on the internal panel on laptops.\n\nAttempt to fetch this EDID if it exists and prefer it over the EDID\nthat is provided by the panel. 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It should be used when\ncomparing an address returned by rcu_dereference().\n\nThis is needed to prevent the compiler CSE and SSA GVN optimizations\nfrom replacing the registers holding @a or @b based on their\nequality, which does not preserve address dependencies and allows the\nfollowing misordering speculations:\n\n- If @b is a constant, the compiler can issue the loads which depend\n on @a before loading @a.\n- If @b is a register populated by a prior load, weakly-ordered\n CPUs can speculate loads which depend on @a before loading @a.\n\nThe same logic applies with @a and @b swapped.\n\nThe compiler barrier() is ineffective at fixing this issue.\nIt does not prevent the compiler CSE from losing the address dependency:\n\nint fct_2_volatile_barriers(void)\n{\n int *a, *b;\n\n do {\n a = READ_ONCE(p);\n asm volatile (\"\" : : : \"memory\");\n b = READ_ONCE(p);\n } while (a != b);\n asm volatile (\"\" : : : \"memory\"); <----- barrier()\n return *b;\n}\n\nWith gcc 14.2 (arm64):\n\nfct_2_volatile_barriers:\n adrp x0, .LANCHOR0\n add x0, x0, :lo12:.LANCHOR0\n.L2:\n ldr x1, [x0] <------ x1 populated by first load.\n ldr x2, [x0]\n cmp x1, x2\n bne .L2\n ldr w0, [x1] <------ x1 is used for access which should depend on b.\n ret\n\nOn weakly-ordered architectures, this lets CPU speculation use the\nresult from the first load to speculate \"ldr w0, [x1]\" before\n\"ldr x2, [x0]\".\nBased on the RCU documentation, the control dependency does not prevent\nthe CPU from speculating loads.\n\nSuggested-by: Linus Torvalds \nSuggested-by: Boqun Feng \nSigned-off-by: Mathieu Desnoyers \nCc: Greg Kroah-Hartman \nCc: Sebastian Andrzej Siewior \nCc: \"Paul E. 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