diff --git a/cmd/metrics/event_frame.go b/cmd/metrics/event_frame.go index b8dca3f0..7af91245 100644 --- a/cmd/metrics/event_frame.go +++ b/cmd/metrics/event_frame.go @@ -121,12 +121,22 @@ func parseEvents(rawEvents [][]byte, eventGroupDefinitions []GroupDefinition) ([ previousEvent := "" var eventsNotCounted []string var eventsNotSupported []string - for _, rawEvent := range rawEvents { + for i, rawEvent := range rawEvents { event, err := parseEventJSON(rawEvent) // nosemgrep if err != nil { - slog.Error(err.Error(), slog.String("event", string(rawEvent))) + // if error log the current line and up to 5 more lines + out := string(rawEvent) + for j := i + 1; j < len(rawEvents) && j < i+5; j++ { + out += "\n" + string(rawEvents[j]) + } + slog.Error(err.Error(), slog.String("perf output", out)) return nil, err } + // sometimes perf will prepend "cpu/" to the topdown event names, e.g., cpu/topdown-retiring/, we clean it up here to match metric formulas + if strings.HasPrefix(event.Event, "cpu/") && strings.Contains(event.Event, "topdown") && strings.HasSuffix(event.Event, "/") { + event.Event = strings.TrimPrefix(event.Event, "cpu/") + event.Event = strings.TrimSuffix(event.Event, "/") + } switch event.CounterValue { case "": slog.Debug("event not counted", slog.String("event", string(rawEvent))) diff --git a/cmd/metrics/loader.go b/cmd/metrics/loader.go new file mode 100644 index 00000000..41a0408b --- /dev/null +++ b/cmd/metrics/loader.go @@ -0,0 +1,75 @@ +package metrics + +// Copyright (C) 2021-2025 Intel Corporation +// SPDX-License-Identifier: BSD-3-Clause + +import ( + "fmt" + "log/slog" + "strings" + + "github.com/Knetic/govaluate" +) + +type MetricDefinition struct { + Name string `json:"name"` + Expression string `json:"expression"` + Description string `json:"description"` + Variables map[string]int // parsed from Expression for efficiency, int represents group index + Evaluable *govaluate.EvaluableExpression // parse expression once, store here for use in metric evaluation +} + +// EventDefinition represents a single perf event +type EventDefinition struct { + Raw string + Name string + Device string +} + +// GroupDefinition represents a group of perf events +type GroupDefinition []EventDefinition + +type Loader interface { + Load(metricDefinitionOverridePath string, eventDefinitionOverridePath string, selectedMetrics []string, metadata Metadata) (metrics []MetricDefinition, groups []GroupDefinition, err error) +} + +type BaseLoader struct { + microarchitecture string +} + +type LegacyLoader struct { + BaseLoader +} + +type PerfmonLoader struct { + BaseLoader +} + +func NewLoader(uarch string) (Loader, error) { + switch strings.ToLower(uarch) { + case "clx", "skx", "bdx", "bergamo", "genoa", "turin": + slog.Debug("Using legacy loader for microarchitecture", slog.String("uarch", uarch)) + return newLegacyLoader(strings.ToLower(uarch)), nil + case "gnr", "srf", "emr", "spr", "icx": + slog.Debug("Using perfmon loader for microarchitecture", slog.String("uarch", uarch)) + return newPerfmonLoader(strings.ToLower(uarch)), nil + default: + return nil, fmt.Errorf("unsupported microarchitecture: %s", uarch) + } +} + +func newLegacyLoader(uarch string) *LegacyLoader { + return &LegacyLoader{ + BaseLoader: BaseLoader{ + microarchitecture: uarch, + }, + } +} + +func newPerfmonLoader(uarch string) *PerfmonLoader { + return &PerfmonLoader{ + BaseLoader: BaseLoader{ + microarchitecture: uarch, + }, + } +} diff --git a/cmd/metrics/event_defs.go b/cmd/metrics/loader_legacy.go similarity index 74% rename from cmd/metrics/event_defs.go rename to cmd/metrics/loader_legacy.go index aff1bca6..98b1a77f 100644 --- a/cmd/metrics/event_defs.go +++ b/cmd/metrics/loader_legacy.go @@ -3,10 +3,9 @@ package metrics // Copyright (C) 2021-2025 Intel Corporation // SPDX-License-Identifier: BSD-3-Clause -// helper functions for parsing and interpreting the architecture-specific perf event definition files - import ( "bufio" + "encoding/json" "fmt" "io/fs" "log/slog" @@ -19,19 +18,73 @@ import ( mapset "github.com/deckarep/golang-set/v2" ) -// EventDefinition represents a single perf event -type EventDefinition struct { - Raw string - Name string - Device string +func (l *LegacyLoader) Load(metricDefinitionOverridePath string, eventDefinitionOverridePath string, selectedMetrics []string, metadata Metadata) ([]MetricDefinition, []GroupDefinition, error) { + loadedMetricDefinitions, err := loadMetricDefinitions(metricDefinitionOverridePath, selectedMetrics, metadata) + if err != nil { + return nil, nil, fmt.Errorf("failed to load metric definitions: %w", err) + } + loadedEventGroups, uncollectableEvents, err := loadEventGroups(eventDefinitionOverridePath, metadata) + if err != nil { + return nil, nil, fmt.Errorf("failed to load event group definitions: %w", err) + } + configuredMetricDefinitions, err := configureMetrics(loadedMetricDefinitions, uncollectableEvents, metadata) + if err != nil { + return nil, nil, fmt.Errorf("failed to configure metrics: %w", err) + } + return configuredMetricDefinitions, loadedEventGroups, nil } -// GroupDefinition represents a group of perf events -type GroupDefinition []EventDefinition +// loadMetricDefinitions reads and parses metric definitions from an architecture-specific metric +// definition file. When the override path argument is empty, the function will load metrics from +// the file associated with the platform's architecture found in the provided metadata. When +// a list of metric names is provided, only those metric definitions will be loaded. +func loadMetricDefinitions(metricDefinitionOverridePath string, selectedMetrics []string, metadata Metadata) (metrics []MetricDefinition, err error) { + var bytes []byte + if metricDefinitionOverridePath != "" { + bytes, err = os.ReadFile(metricDefinitionOverridePath) // #nosec G304 + if err != nil { + return + } + } else { + uarch := strings.ToLower(strings.Split(metadata.Microarchitecture, "_")[0]) + uarch = strings.Split(uarch, " ")[0] + metricFileName := fmt.Sprintf("%s.json", uarch) + if bytes, err = resources.ReadFile(filepath.Join("resources", "legacy", "metrics", metadata.Architecture, metadata.Vendor, metricFileName)); err != nil { + return + } + } + var metricsInFile []MetricDefinition + if err = json.Unmarshal(bytes, &metricsInFile); err != nil { + return + } + // if a list of metric names provided, reduce list to match + if len(selectedMetrics) > 0 { + // confirm provided metric names are valid (included in metrics defined in file) + // and build list of metrics based on provided list of metric names + metricMap := make(map[string]MetricDefinition) + for _, metric := range metricsInFile { + metricMap[metric.Name] = metric + } + for _, selectedMetricName := range selectedMetrics { + if _, ok := metricMap[selectedMetricName]; !ok { + err = fmt.Errorf("provided metric name not found: %s", selectedMetricName) + return + } + metrics = append(metrics, metricMap[selectedMetricName]) + } + } else { + metrics = metricsInFile + } + // abbreviate event names in metrics to shorten the eventual perf stat command line + for i := range metrics { + metrics[i].Expression = abbreviateEventName(metrics[i].Expression) + } + return +} -// LoadEventGroups reads the events defined in the architecture specific event definition file, then +// loadEventGroups reads the events defined in the architecture specific event definition file, then // expands them to include the per-device uncore events -func LoadEventGroups(eventDefinitionOverridePath string, metadata Metadata) (groups []GroupDefinition, uncollectableEvents []string, err error) { +func loadEventGroups(eventDefinitionOverridePath string, metadata Metadata) (groups []GroupDefinition, uncollectableEvents []string, err error) { var file fs.File if eventDefinitionOverridePath != "" { file, err = os.Open(eventDefinitionOverridePath) // #nosec G304 @@ -41,22 +94,14 @@ func LoadEventGroups(eventDefinitionOverridePath string, metadata Metadata) (gro } else { uarch := strings.ToLower(strings.Split(metadata.Microarchitecture, "_")[0]) uarch = strings.Split(uarch, " ")[0] - // use alternate events/metrics when TMA fixed counters are not supported - alternate := "" - if (uarch == "icx" || uarch == "spr" || uarch == "emr" || uarch == "gnr") && !metadata.SupportsFixedTMA { // AWS/GCP VM instances - alternate = "_nofixedtma" - } - eventFileName := fmt.Sprintf("%s%s.txt", uarch, alternate) - if file, err = resources.Open(filepath.Join("resources", "events", metadata.Architecture, metadata.Vendor, eventFileName)); err != nil { + eventFileName := fmt.Sprintf("%s.txt", uarch) + if file, err = resources.Open(filepath.Join("resources", "legacy", "events", metadata.Architecture, metadata.Vendor, eventFileName)); err != nil { return } } defer file.Close() scanner := bufio.NewScanner(file) uncollectable := mapset.NewSet[string]() - if flagTransactionRate == 0 { - uncollectable.Add("TXN") - } var group GroupDefinition for scanner.Scan() { line := strings.TrimSpace(scanner.Text()) @@ -104,38 +149,6 @@ func LoadEventGroups(eventDefinitionOverridePath string, metadata Metadata) (gro return } -// abbreviateEventName replaces long event names with abbreviations to reduce the length of the perf command. -// focus is on uncore events because they are repeated for each uncore device -func abbreviateEventName(event string) string { - // Abbreviations must be unique and in order. And, if replacing UNC_*, the abbreviation must begin with "UNC" because this is how we identify uncore events when collapsing them. - var abbreviations = [][]string{ - {"UNC_CHA_TOR_INSERTS", "UNCCTI"}, - {"UNC_CHA_TOR_OCCUPANCY", "UNCCTO"}, - {"UNC_CHA_CLOCKTICKS", "UNCCCT"}, - {"UNC_M_CAS_COUNT_SCH", "UNCMCC"}, - {"IA_MISS_DRD_REMOTE", "IMDR"}, - {"IA_MISS_DRD_LOCAL", "IMDL"}, - {"IA_MISS_LLCPREFDATA", "IMLP"}, - {"IA_MISS_LLCPREFRFO", "IMLR"}, - {"IA_MISS_DRD_PREF_LOCAL", "IMDPL"}, - {"IA_MISS_DRD_PREF_REMOTE", "IMDRP"}, - {"IA_MISS_CRD_PREF", "IMCP"}, - {"IA_MISS_RFO_PREF", "IMRP"}, - {"IA_MISS_RFO", "IMRF"}, - {"IA_MISS_CRD", "IMC"}, - {"IA_MISS_DRD", "IMD"}, - {"IO_PCIRDCUR", "IPCI"}, - {"IO_ITOMCACHENEAR", "IITN"}, - {"IO_ITOM", "IITO"}, - {"IMD_OPT", "IMDO"}, - } - // if an abbreviation key is found in the event, replace the matching portion of the event with the abbreviation - for _, abbr := range abbreviations { - event = strings.Replace(event, abbr[0], abbr[1], -1) - } - return event -} - // isCollectableEvent confirms if given event can be collected on the platform func isCollectableEvent(event EventDefinition, metadata Metadata) bool { // fixed-counter TMA @@ -143,26 +156,15 @@ func isCollectableEvent(event EventDefinition, metadata Metadata) bool { slog.Debug("Fixed counter TMA not supported on target", slog.String("event", event.Name)) return false } - // PEBS events (not supported on GCP c4 VMs) - pebsEventNames := []string{"INT_MISC.UNKNOWN_BRANCH_CYCLES", "UOPS_RETIRED.MS"} - if !metadata.SupportsPEBS { - for _, pebsEventName := range pebsEventNames { - if strings.Contains(event.Name, pebsEventName) { - slog.Debug("PEBS events not supported on target", slog.String("event", event.Name)) - return false - } - } - } // short-circuit for cpu events that aren't off-core response events - if event.Device == "cpu" && !(strings.HasPrefix(event.Name, "OCR") || strings.HasPrefix(event.Name, "OFFCORE_REQUESTS_OUTSTANDING")) { + if event.Device == "cpu" && !strings.HasPrefix(event.Name, "OCR") { return true } - // off-core response events - if event.Device == "cpu" && (strings.HasPrefix(event.Name, "OCR") || strings.HasPrefix(event.Name, "OFFCORE_REQUESTS_OUTSTANDING")) { - if !(metadata.SupportsOCR && metadata.SupportsUncore) { - slog.Debug("Off-core response events not supported on target", slog.String("event", event.Name)) - return false - } else if flagScope == scopeProcess || flagScope == scopeCgroup { + // short-circuit off-core response events + if event.Device == "cpu" && + strings.HasPrefix(event.Name, "OCR") && + metadata.SupportsUncore { + if flagScope == scopeProcess || flagScope == scopeCgroup { slog.Debug("Off-core response events not supported in process or cgroup scope", slog.String("event", event.Name)) return false } @@ -308,3 +310,35 @@ func expandUncoreGroups(groups []GroupDefinition, metadata Metadata) (expandedGr } return } + +// abbreviateEventName replaces long event names with abbreviations to reduce the length of the perf command. +// focus is on uncore events because they are repeated for each uncore device +func abbreviateEventName(event string) string { + // Abbreviations must be unique and in order. And, if replacing UNC_*, the abbreviation must begin with "UNC" because this is how we identify uncore events when collapsing them. + var abbreviations = [][]string{ + {"UNC_CHA_TOR_INSERTS", "UNCCTI"}, + {"UNC_CHA_TOR_OCCUPANCY", "UNCCTO"}, + {"UNC_CHA_CLOCKTICKS", "UNCCCT"}, + {"UNC_M_CAS_COUNT_SCH", "UNCMCC"}, + {"IA_MISS_DRD_REMOTE", "IMDR"}, + {"IA_MISS_DRD_LOCAL", "IMDL"}, + {"IA_MISS_LLCPREFDATA", "IMLP"}, + {"IA_MISS_LLCPREFRFO", "IMLR"}, + {"IA_MISS_DRD_PREF_LOCAL", "IMDPL"}, + {"IA_MISS_DRD_PREF_REMOTE", "IMDRP"}, + {"IA_MISS_CRD_PREF", "IMCP"}, + {"IA_MISS_RFO_PREF", "IMRP"}, + {"IA_MISS_RFO", "IMRF"}, + {"IA_MISS_CRD", "IMC"}, + {"IA_MISS_DRD", "IMD"}, + {"IO_PCIRDCUR", "IPCI"}, + {"IO_ITOMCACHENEAR", "IITN"}, + {"IO_ITOM", "IITO"}, + {"IMD_OPT", "IMDO"}, + } + // if an abbreviation key is found in the event, replace the matching portion of the event with the abbreviation + for _, abbr := range abbreviations { + event = strings.Replace(event, abbr[0], abbr[1], -1) + } + return event +} diff --git a/cmd/metrics/loader_perfmon.go b/cmd/metrics/loader_perfmon.go new file mode 100644 index 00000000..524efafa --- /dev/null +++ b/cmd/metrics/loader_perfmon.go @@ -0,0 +1,678 @@ +package metrics + +// Copyright (C) 2021-2025 Intel Corporation +// SPDX-License-Identifier: BSD-3-Clause + +import ( + "encoding/json" + "fmt" + "log/slog" + "os" + "path/filepath" + "perfspect/internal/util" + "regexp" + "slices" + "strings" +) + +type PerfmonMetricsHeader map[string]string + +type PerfmonMetricThreshold struct { + ThresholdMetrics []map[string]string `json:"ThresholdMetrics"` + Formula string `json:"Formula"` + BaseFormula string `json:"BaseFormula"` + ThresholdIssues string `json:"ThresholdIssues"` +} + +type PerfmonMetric struct { + MetricName string `json:"MetricName"` + LegacyName string `json:"LegacyName"` + ParentCategory string `json:"ParentCategory"` + Level int `json:"Level"` + BriefDescription string `json:"BriefDescription"` + UnitOfMeasure string `json:"UnitOfMeasure"` + Events []map[string]string `json:"Events"` + Constants []map[string]string `json:"Constants"` + Formula string `json:"Formula"` + BaseFormula string `json:"BaseFormula"` + Category string `json:"Category"` + CountDomain string `json:"CountDomain"` + Threshold *PerfmonMetricThreshold `json:"Threshold"` + ResolutionLevels string `json:"ResolutionLevels"` + MetricGroup string `json:"MetricGroup"` + LocateWith string `json:"LocateWith"` +} + +type PerfmonMetrics struct { + Header PerfmonMetricsHeader `json:"Header"` + Metrics []PerfmonMetric `json:"Metrics"` +} + +func loadPerfmonMetricsFromFile(path string) (PerfmonMetrics, error) { + var metrics PerfmonMetrics + bytes, err := resources.ReadFile(path) + if err != nil { + return PerfmonMetrics{}, fmt.Errorf("error reading file %s: %w", path, err) + } + if err := json.Unmarshal(bytes, &metrics); err != nil { + return PerfmonMetrics{}, fmt.Errorf("error unmarshaling JSON from %s: %w", path, err) + } + return metrics, nil +} + +type MetricsConfigHeader struct { + Copyright string `json:"Copyright"` + Info string `json:"Info"` +} +type PerfspectMetric struct { + MetricName string `json:"MetricName"` + LegacyName string `json:"LegacyName"` + Origin string `json:"Origin"` +} +type MetricsConfig struct { + Header MetricsConfigHeader `json:"Header"` + PerfmonMetricsFile string `json:"PerfmonMetricsFile"` // Path to the perfmon metrics file + PerfmonCoreEventsFile string `json:"PerfmonCoreEventsFile"` // Path to the perfmon core events file + PerfmonUncoreEventsFile string `json:"PerfmonUncoreEventsFile"` // Path to the perfmon uncore events file + PerfmonRetireLatencyFile string `json:"PerfmonRetireLatencyFile"` // Path to the perfmon retire latency file + Metrics []PerfmonMetric `json:"Metrics"` // Metrics defined by PerfSpect + AlternateTMAMetrics []PerfmonMetric `json:"AlternateTMAMetrics"` // Alternate TMA metrics that can be used in place of the main TMA metrics + ReportMetrics []PerfspectMetric `json:"ReportMetrics"` // Metrics that are reported in the PerfSpect report +} + +func (l *PerfmonLoader) loadMetricsConfig(metricConfigOverridePath string) (MetricsConfig, error) { + var config MetricsConfig + var bytes []byte + if metricConfigOverridePath != "" { + var err error + bytes, err = os.ReadFile(metricConfigOverridePath) + if err != nil { + return MetricsConfig{}, fmt.Errorf("error reading metric config override file: %w", err) + } + } else { + var err error + bytes, err = resources.ReadFile(filepath.Join("resources", "perfmon", strings.ToLower(l.microarchitecture), strings.ToLower(l.microarchitecture)+".json")) + if err != nil { + return MetricsConfig{}, fmt.Errorf("error reading metrics config file: %w", err) + } + } + if err := json.Unmarshal(bytes, &config); err != nil { + return MetricsConfig{}, fmt.Errorf("error unmarshaling metrics config JSON: %w", err) + } + return config, nil +} + +func (l *PerfmonLoader) Load(metricConfigOverridePath string, legacyLoaderEventFile string, selectedMetrics []string, metadata Metadata) ([]MetricDefinition, []GroupDefinition, error) { + if legacyLoaderEventFile != "" { + return nil, nil, fmt.Errorf("legacy loader event file is not supported in PerfmonLoader") + } + // Load the metrics configuration from the JSON file + config, err := l.loadMetricsConfig(metricConfigOverridePath) + if err != nil { + return nil, nil, fmt.Errorf("failed to load metrics config: %w", err) + } + reportMetrics, err := filterReportMetrics(config.ReportMetrics, selectedMetrics) + if err != nil { + return nil, nil, fmt.Errorf("error filtering report metrics: %w", err) + } + // Load the perfmon metric definitions from the JSON file + perfmonMetricDefinitions, err := loadPerfmonMetricsFromFile(filepath.Join("resources", "perfmon", strings.ToLower(l.microarchitecture), config.PerfmonMetricsFile)) + if err != nil { + return nil, nil, fmt.Errorf("error loading perfmon metrics from file: %w", err) + } + // Load the perfmon core events from the JSON file + coreEvents, err := NewCoreEvents(filepath.Join("resources", "perfmon", strings.ToLower(l.microarchitecture), config.PerfmonCoreEventsFile)) + if err != nil { + return nil, nil, fmt.Errorf("error loading perfmon core events: %w", err) + } + // Load the perfmon uncore events from the JSON file + uncoreEvents, err := NewUncoreEvents(filepath.Join("resources", "perfmon", strings.ToLower(l.microarchitecture), config.PerfmonUncoreEventsFile)) + if err != nil { + return nil, nil, fmt.Errorf("error loading perfmon uncore events: %w", err) + } + // Load the other events (not core or uncore) + otherEvents, err := NewOtherEvents() + if err != nil { + return nil, nil, fmt.Errorf("error loading other events: %w", err) + } + // Combine the PerfSpect-defined metrics with the metric definitions from perfmon and filter based on report metrics + // Creates one list of all metrics to be used in the loader + perfmonMetrics, err := loadPerfmonMetrics(reportMetrics, perfmonMetricDefinitions.Metrics, config.Metrics, config.AlternateTMAMetrics, metadata) + if err != nil { + return nil, nil, fmt.Errorf("error loading perfmon metrics: %w", err) + } + // Remove metrics that use uncollectable events + perfmonMetrics, err = removeUncollectableMetrics(perfmonMetrics, coreEvents, uncoreEvents, otherEvents, metadata) + if err != nil { + return nil, nil, fmt.Errorf("error removing uncollectable metrics: %w", err) + } + // Load the metric definitions (this is the type that will be returned per the interface definition) + metricDefs, err := perfmonToMetricDefs(perfmonMetrics) + if err != nil { + return nil, nil, fmt.Errorf("error loading metrics from definitions: %w", err) + } + // Abbreviate uncore event names in metric expressions + metricDefs, err = abbreviateUncoreEventNames(metricDefs, uncoreEvents) + if err != nil { + return nil, nil, fmt.Errorf("error abbreviating uncore event names: %w", err) + } + // Simplify OCR event names in metric expressions + metricDefs, err = customizeOCREventNames(metricDefs) + if err != nil { + return nil, nil, fmt.Errorf("error simplifying OCR event names: %w", err) + } + // Create event groups from the perfspect metrics + coreGroups, uncoreGroups, otherGroups, uncollectableEvents, err := loadEventGroupsFromMetrics( + perfmonMetrics, + coreEvents, + uncoreEvents, + otherEvents, + metadata, + ) + if err != nil { + return nil, nil, fmt.Errorf("error loading event groups from metrics: %v", err) + } + // Eliminate duplicate groups + coreGroups, uncoreGroups, err = eliminateDuplicateGroups(coreGroups, uncoreGroups) + if err != nil { + return nil, nil, fmt.Errorf("error merging duplicate groups: %v", err) + } + // Merge groups that can be merged, i.e., if 2nd group's events fit in the first group + coreGroups, uncoreGroups, err = mergeGroups(coreGroups, uncoreGroups, metadata) + if err != nil { + return nil, nil, fmt.Errorf("error merging groups: %v", err) + } + // Expand uncore groups for uncore devices + uncoreGroups, err = ExpandUncoreGroups(uncoreGroups, metadata.UncoreDeviceIDs) + if err != nil { + return nil, nil, fmt.Errorf("error expanding uncore groups: %v", err) + } + slog.Debug("Number of core groups", slog.Int("count", len(coreGroups))) + slog.Debug("Number of uncore groups", slog.Int("count", len(uncoreGroups))) + slog.Debug("Number of other groups", slog.Int("count", len(otherGroups))) + // Merge all groups into a single slice of GroupDefinition + allGroups := make([]GroupDefinition, 0) + for _, group := range coreGroups { + allGroups = append(allGroups, group.ToGroupDefinition()) + } + for _, group := range uncoreGroups { + allGroups = append(allGroups, group.ToGroupDefinition()) + } + for _, group := range otherGroups { + allGroups = append(allGroups, group.ToGroupDefinition()) + } + // Replace retire latencies variables with their values + if config.PerfmonRetireLatencyFile != "" { + metricDefs, err = replaceRetireLatencies(metricDefs, filepath.Join("resources", "perfmon", strings.ToLower(l.microarchitecture), config.PerfmonRetireLatencyFile)) + if err != nil { + return nil, nil, fmt.Errorf("failed to replace retire latencies: %w", err) + } + } + // Apply common modifications to metric expressions + metricDefs, err = configureMetrics(metricDefs, uncollectableEvents, metadata) + if err != nil { + return nil, nil, fmt.Errorf("failed to configure metrics: %w", err) + } + return metricDefs, allGroups, nil +} + +func filterReportMetrics(reportMetrics []PerfspectMetric, selectedMetricNames []string) ([]PerfspectMetric, error) { + if len(selectedMetricNames) == 0 { + slog.Debug("No selected metrics provided, using all report metrics") + return reportMetrics, nil + } + slog.Debug("Filtering report metrics based on selected metrics", slog.Any("selectedMetrics", selectedMetricNames)) + var filteredMetrics []PerfspectMetric + for _, metricName := range selectedMetricNames { + found := false + for _, metric := range reportMetrics { + if metric.LegacyName == "metric_"+metricName { + filteredMetrics = append(filteredMetrics, metric) + found = true + break + } + } + if !found { + return nil, fmt.Errorf("unknown metric: %s", metricName) + } + } + return filteredMetrics, nil +} + +func loadPerfmonMetrics(reportMetrics []PerfspectMetric, perfmonMetrics []PerfmonMetric, configMetrics []PerfmonMetric, alternateTMAMetrics []PerfmonMetric, metadata Metadata) ([]PerfmonMetric, error) { + var perfmonMetricsToReturn []PerfmonMetric + allPerfmonMetrics := append(configMetrics, perfmonMetrics...) + for _, metric := range reportMetrics { + var perfmonMetric *PerfmonMetric + var found bool + if !metadata.SupportsFixedTMA { + perfmonMetric, found = findPerfmonMetric(alternateTMAMetrics, metric.LegacyName) + } + if !found { + perfmonMetric, found = findPerfmonMetric(allPerfmonMetrics, metric.LegacyName) + } + if !found { + slog.Warn("Metric not found in metric definitions", "metric", metric.LegacyName, "origin", metric.Origin) + continue + } + // Add the metric to the list of metrics to return + perfmonMetricsToReturn = append(perfmonMetricsToReturn, *perfmonMetric) + } + return perfmonMetricsToReturn, nil +} + +func abbreviateUncoreEventNames(metrics []MetricDefinition, uncoreEvents UncoreEvents) ([]MetricDefinition, error) { + for i := range metrics { + metric := &metrics[i] + for _, uncoreEvent := range uncoreEvents.Events { + re, err := regexp.Compile(fmt.Sprintf(`\b%s\b`, uncoreEvent.EventName)) + if err != nil { + return nil, fmt.Errorf("failed to compile regex for uncore event %s: %w", uncoreEvent.EventName, err) + } + for { + index := re.FindStringIndex(metric.Expression) + if index == nil { + break // no more matches found + } + // replace this occurrence of the original with the replacement + metric.Expression = metric.Expression[:index[0]] + uncoreEvent.UniqueID + metric.Expression[index[1]:] + } + } + } + return metrics, nil +} + +func customizeOCREventNames(metrics []MetricDefinition) ([]MetricDefinition, error) { + for i := range metrics { + metric := &metrics[i] + // example portion of expression: [OCR.DEMAND_RFO.L3_MISS:ocr_msr_val=0x103b8000] + if !strings.Contains(metric.Expression, ":ocr_msr_val=") { + continue // only customize OCR events with this format + } + re, err := regexp.Compile(`(OCR\.[^\]]+):ocr_msr_val=([0-9a-fx]+)`) + if err != nil { + return nil, fmt.Errorf("failed to compile regex for OCR event: %w", err) + } + for { + index := re.FindStringSubmatchIndex(metric.Expression) + if index == nil { + break // no more matches found + } + // extract the event name and MSR value from the match + eventName := metric.Expression[index[2]:index[3]] + msrValue := metric.Expression[index[4]:index[5]] + // replace the OCR event with its customized name + customizedName := fmt.Sprintf("%s.%s", eventName, msrValue) + metric.Expression = metric.Expression[:index[0]] + customizedName + metric.Expression[index[1]:] + } + } + return metrics, nil +} + +// getExpression retrieves the expression for a given PerfmonMetric, replacing variables with their corresponding event or constant names. +// example formula: "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS" +// desired output: "( 1000000000 * ([event1] / [event2]) / ([constant1] / ([constant2] * socket_count) ) ) * 1" +func getExpression(perfmonMetric PerfmonMetric) (string, error) { + expression := perfmonMetric.Formula + replacers := make(map[string]string) + for _, event := range perfmonMetric.Events { + replacers[event["Alias"]] = fmt.Sprintf("[%s]", event["Name"]) + } + for _, constant := range perfmonMetric.Constants { + replacers[constant["Alias"]] = fmt.Sprintf("[%s]", constant["Name"]) + } + for alias, replacement := range replacers { + // regex to match alias as a whole word + // this prevents replacing substrings that are part of other words + re, err := regexp.Compile(fmt.Sprintf(`\b%s\b`, alias)) + if err != nil { + return "", fmt.Errorf("failed to compile regex for alias %s: %w", alias, err) + } + for { + index := re.FindStringIndex(expression) + if index == nil { + break // no more matches found + } + // replace the first occurrence of the alias with the replacement + expression = expression[:index[0]] + replacement + expression[index[1]:] + } + } + // replace common constants with their values + commonEventReplacements := map[string]string{ + "DURATIONTIMEINSECONDS": "1", + "[DURATIONTIMEINMILLISECONDS]": "1000", + } + for commonEvent, alias := range commonEventReplacements { + expression = strings.ReplaceAll(expression, commonEvent, alias) + } + // replace fixed counter perfmon event names with their corresponding perf event names + for perfmonEventName, perfEventName := range fixedCounterEventNameTranslation { + // regex to match event name as a whole word + // this prevents replacing substrings that are part of other words + re, err := regexp.Compile(fmt.Sprintf(`\b%s\b`, perfmonEventName)) + if err != nil { + return "", fmt.Errorf("failed to compile regex for perfmonEventName %s: %w", perfmonEventName, err) + } + for { + index := re.FindStringIndex(expression) + if index == nil { + break // no more matches found + } + // replace the first occurrence of the alias with the replacement + expression = expression[:index[0]] + perfEventName + expression[index[1]:] + } + } + return expression, nil +} + +func perfmonToMetricDefs(perfmonMetrics []PerfmonMetric) ([]MetricDefinition, error) { + var metrics []MetricDefinition + for _, perfmonMetric := range perfmonMetrics { + // get the expression for the metric + expression, err := getExpression(perfmonMetric) + if err != nil { + slog.Warn("Failed getting expression for metric", "metric", perfmonMetric.LegacyName, "error", err) + continue + } + // create a MetricDefinition from the perfmon metric + metric := MetricDefinition{ + Name: perfmonMetric.LegacyName, + Description: perfmonMetric.BriefDescription, + Expression: expression, + } + // add the metric to the list of metrics + metrics = append(metrics, metric) + } + return metrics, nil +} + +func removeUncollectableMetrics(perfmonMetrics []PerfmonMetric, coreEvents CoreEvents, uncoreEvents UncoreEvents, otherEvents OtherEvents, metadata Metadata) ([]PerfmonMetric, error) { + var collectableMetrics []PerfmonMetric + for _, perfmonMetric := range perfmonMetrics { + // collect the event names from the metric and check if any of them are not collectable + var eventNames []string + for _, event := range perfmonMetric.Events { + eventNames = util.UniqueAppend(eventNames, event["Name"]) + } + uncollectableEvents := getUncollectableEvents(eventNames, coreEvents, uncoreEvents, otherEvents, metadata) + if len(uncollectableEvents) > 0 { + slog.Warn("Metric contains uncollectable events", "metric", perfmonMetric.LegacyName, "uncollectableEvents", uncollectableEvents) + continue + } + // if the metric is collectable, add it to the list of collectable metrics + collectableMetrics = append(collectableMetrics, perfmonMetric) + } + return collectableMetrics, nil +} + +func loadEventGroupsFromMetrics(perfmonMetrics []PerfmonMetric, coreEvents CoreEvents, uncoreEvents UncoreEvents, otherEvents OtherEvents, metadata Metadata) ([]CoreGroup, []UncoreGroup, []OtherGroup, []string, error) { + coreGroups := make([]CoreGroup, 0) + uncoreGroups := make([]UncoreGroup, 0) + otherGroups := make([]OtherGroup, 0) + uncollectableEvents := make([]string, 0) + + for _, perfmonMetric := range perfmonMetrics { + var metricEventNames []string + for _, event := range perfmonMetric.Events { + metricEventNames = util.UniqueAppend(metricEventNames, event["Name"]) + } + // check if the metric has uncollectable events + uncollectableMetricEvents := getUncollectableEvents(metricEventNames, coreEvents, uncoreEvents, otherEvents, metadata) + // if there are uncollectable events, add them to the uncollectableEvents list + uncollectableEvents = util.UniqueAppend(uncollectableEvents, uncollectableMetricEvents...) + // skip metrics that have uncollectable events + if len(uncollectableMetricEvents) > 0 { + slog.Warn("Metric contains uncollectable events", "metric", perfmonMetric.LegacyName, "uncollectableEvents", uncollectableMetricEvents) + continue + } + metricCoreGroups, metricUncoreGroups, metricOtherGroups, err := groupsFromEventNames( + perfmonMetric.LegacyName, + metricEventNames, + coreEvents, + uncoreEvents, + otherEvents, + metadata, + ) + if err != nil { + slog.Error("Error creating groups from event names", "metric", perfmonMetric.LegacyName, "error", err) + continue + } + // Add the groups to the main lists + coreGroups = append(coreGroups, metricCoreGroups...) + uncoreGroups = append(uncoreGroups, metricUncoreGroups...) + otherGroups = append(otherGroups, metricOtherGroups...) + } + return coreGroups, uncoreGroups, otherGroups, uncollectableEvents, nil +} + +func getUncollectableEvents(eventNames []string, coreEvents CoreEvents, uncoreEvents UncoreEvents, otherEvents OtherEvents, metadata Metadata) []string { + uncollectableEvents := make([]string, 0) + for _, eventName := range eventNames { + coreEvent := coreEvents.FindEventByName(eventName) + if !coreEvent.IsEmpty() { + if !coreEvent.IsCollectable(metadata) { + uncollectableEvents = util.UniqueAppend(uncollectableEvents, coreEvent.EventName) + } + continue + } + uncoreEvent := uncoreEvents.FindEventByName(eventName) + if uncoreEvent != (UncoreEvent{}) { + if !uncoreEvent.IsCollectable(metadata) { + uncollectableEvents = util.UniqueAppend(uncollectableEvents, uncoreEvent.EventName) + } + continue + } + otherEvent := otherEvents.FindEventByName(eventName) + if otherEvent != (OtherEvent{}) { + if !otherEvent.IsCollectable(metadata) { + uncollectableEvents = util.UniqueAppend(uncollectableEvents, otherEvent.EventName) + } + continue + } + if !slices.Contains(constants, eventName) { // ignore constants, they'll be handled separately + slog.Warn("Event not found in core or uncore events", "event", eventName) + uncollectableEvents = util.UniqueAppend(uncollectableEvents, eventName) // if the event is not found in either core or uncore events, we consider it uncollectable + } + } + return uncollectableEvents +} + +func eliminateDuplicateGroups(coreGroups []CoreGroup, uncoreGroups []UncoreGroup) ([]CoreGroup, []UncoreGroup, error) { + coreGroups, err := EliminateDuplicateCoreGroups(coreGroups) + if err != nil { + return nil, nil, fmt.Errorf("failed to eliminate duplicate core groups: %w", err) + } + uncoreGroups, err = EliminateDuplicateUncoreGroups(uncoreGroups) + if err != nil { + return nil, nil, fmt.Errorf("failed to elminate duplicate uncore groups: %w", err) + } + return coreGroups, uncoreGroups, nil +} + +func mergeGroups(coreGroups []CoreGroup, uncoreGroups []UncoreGroup, metadata Metadata) ([]CoreGroup, []UncoreGroup, error) { + coreGroups, err := MergeCoreGroups(coreGroups, metadata) + if err != nil { + return nil, nil, fmt.Errorf("error merging core groups: %w", err) + } + uncoreGroups, err = MergeUncoreGroups(uncoreGroups) + if err != nil { + return nil, nil, fmt.Errorf("error merging uncore groups: %w", err) + } + return coreGroups, uncoreGroups, nil +} + +var constants []string = []string{ + "TSC", +} + +func groupsFromEventNames(metricName string, eventNames []string, coreEvents CoreEvents, uncoreEvents UncoreEvents, otherEvents OtherEvents, metadata Metadata) ([]CoreGroup, []UncoreGroup, []OtherGroup, error) { + var coreGroups []CoreGroup + var uncoreGroups []UncoreGroup + var otherGroups []OtherGroup + coreGroup := NewCoreGroup(metadata) + uncoreGroup := NewUncoreGroup(metadata) + for _, eventName := range eventNames { + // Skip constants, they are not events + if slices.Contains(constants, eventName) { + continue + } + if strings.Contains(eventName, "retire_latency") { + // skip :retire_latency + continue + } + coreEvent := coreEvents.FindEventByName(eventName) + if !coreEvent.IsEmpty() { // this is a core event + // if the event has been customized with :c, :e, or both, we create a new event with + // customizations in the name + if strings.Contains(eventName, ":") { + // Create a copy of the event with the customized name + coreEvent.EventName = eventName + } + coreGroup.MetricNames = util.UniqueAppend(coreGroup.MetricNames, metricName) + err := coreGroup.AddEvent(coreEvent, false, metadata) + if err != nil { + coreGroups = append(coreGroups, coreGroup) + coreGroup = NewCoreGroup(metadata) // Reset coreGroup for the next set of events + coreGroup.MetricNames = util.UniqueAppend(coreGroup.MetricNames, metricName) + err = coreGroup.AddEvent(coreEvent, false, metadata) // Add the event to the new group + if err != nil { + return nil, nil, nil, fmt.Errorf("error adding event %s to new core group: %w", eventName, err) + } + } + } else { + uncoreEvent := uncoreEvents.FindEventByName(eventName) + if !uncoreEvent.IsEmpty() { // this is an uncore event + uncoreGroup.MetricNames = util.UniqueAppend(uncoreGroup.MetricNames, metricName) + err := uncoreGroup.AddEvent(uncoreEvent, false) + if err != nil { + uncoreGroups = append(uncoreGroups, uncoreGroup) + uncoreGroup = NewUncoreGroup(metadata) // Reset uncoreGroup for the next set of events + uncoreGroup.MetricNames = util.UniqueAppend(uncoreGroup.MetricNames, metricName) + err = uncoreGroup.AddEvent(uncoreEvent, false) // Add the event + if err != nil { + return nil, nil, nil, fmt.Errorf("error adding event %s to new uncore group: %w", eventName, err) + } + } + } else { + otherEvent := otherEvents.FindEventByName(eventName) + if !otherEvent.IsEmpty() { // this is an other event + otherGroup := NewOtherGroup(metadata) + otherGroup.MetricNames = util.UniqueAppend(otherGroup.MetricNames, metricName) + err := otherGroup.AddEvent(otherEvent, false) + if err != nil { + return nil, nil, nil, fmt.Errorf("error adding other event %s to group for metric %s: %w", eventName, metricName, err) + } else { + otherGroups = append(otherGroups, otherGroup) + } + } + } + } + } + // if there are any events in the core group, add it to the groups + coreGroupAdded := false + for _, event := range coreGroup.FixedPurposeCounters { + if !event.IsEmpty() { + coreGroups = append(coreGroups, coreGroup) + coreGroupAdded = true + break + } + } + if !coreGroupAdded { + for _, event := range coreGroup.GeneralPurposeCounters { + if !event.IsEmpty() { + coreGroups = append(coreGroups, coreGroup) + break + } + } + } + // if there are any events in the uncore group, add it to the groups + for _, event := range uncoreGroup.GeneralPurposeCounters { + if !event.IsEmpty() { + uncoreGroups = append(uncoreGroups, uncoreGroup) + break + } + } + return coreGroups, uncoreGroups, otherGroups, nil +} + +// findPerfmonMetric -- Helper function to find a metric by name +func findPerfmonMetric(metricsList []PerfmonMetric, metricName string) (*PerfmonMetric, bool) { + for _, metric := range metricsList { + if metric.LegacyName == metricName { + return &metric, true + } + } + return nil, false +} + +// +// Retire Latency Files +// + +type PlatformInfo struct { + ModelName string `json:"Model name"` + CPUFamily string `json:"CPU family"` + Model string `json:"Model"` + ThreadsPerCore string `json:"Thread(s) per core"` + CoresPerSocket string `json:"Core(s) per socket"` + Sockets string `json:"Socket(s)"` + Stepping string `json:"Stepping"` + L3Cache string `json:"L3 cache"` + NUMANodes string `json:"NUMA node(s)"` + TMAVersion string `json:"TMA version"` +} + +type MetricStats struct { + Min float64 `json:"MIN"` + Max float64 `json:"MAX"` + Mean float64 `json:"MEAN"` +} + +type RetireLatency struct { + Platform PlatformInfo `json:"Platform"` + Data map[string]MetricStats `json:"Data"` +} + +// loadRetireLatencies loads the retire latencies from a JSON file based on the microarchitecture +// it returns a map of event names to their retire latencies +// the retire latency is the mean value of the metric stats +func loadRetireLatencies(retireLatenciesFile string) (map[string]string, error) { + var bytes []byte + var err error + if bytes, err = resources.ReadFile(retireLatenciesFile); err != nil { + slog.Error("failed to read retire latencies file", slog.String("file", retireLatenciesFile), slog.String("error", err.Error())) + return nil, fmt.Errorf("failed to read retire latencies file %s: %w", retireLatenciesFile, err) + } + var retireLatency RetireLatency + if err = json.Unmarshal(bytes, &retireLatency); err != nil { + slog.Error("failed to unmarshal retire latencies", slog.String("error", err.Error())) + return nil, fmt.Errorf("failed to unmarshal retire latencies: %w", err) + } + // create a map of retire latencies + retireLatencies := make(map[string]string) + for event, stats := range retireLatency.Data { + // use the mean value for the retire latency + retireLatencies[event] = fmt.Sprintf("%f", stats.Mean) + } + slog.Debug("loaded retire latencies", slog.Any("latencies", retireLatencies)) + return retireLatencies, nil +} + +// replaceRetireLatencies replaces retire latencies in metrics with their values +func replaceRetireLatencies(metrics []MetricDefinition, retireLatenciesFile string) ([]MetricDefinition, error) { + // load retire latencies + retireLatencies, err := loadRetireLatencies(retireLatenciesFile) + if err != nil { + slog.Error("failed to load retire latencies", slog.String("error", err.Error())) + return nil, err + } + // replace retire latencies in metrics + for i := range metrics { + metric := &metrics[i] + for retireEvent, retireLatency := range retireLatencies { + // replace :retire_latency with value + metric.Expression = strings.ReplaceAll(metric.Expression, fmt.Sprintf("[%s:retire_latency]", retireEvent), retireLatency) + } + } + return metrics, nil +} diff --git a/cmd/metrics/loader_perfmon_event_core.go b/cmd/metrics/loader_perfmon_event_core.go new file mode 100644 index 00000000..a8bb685b --- /dev/null +++ b/cmd/metrics/loader_perfmon_event_core.go @@ -0,0 +1,214 @@ +package metrics + +// Copyright (C) 2021-2025 Intel Corporation +// SPDX-License-Identifier: BSD-3-Clause + +import ( + "encoding/json" + "fmt" + "log/slog" + "strconv" + "strings" +) + +type CoreEvent struct { + EventCode string `json:"EventCode"` + UMask string `json:"UMask"` + EventName string `json:"EventName"` + BriefDescription string `json:"BriefDescription"` + PublicDescription string `json:"PublicDescription"` + Counter string `json:"Counter"` + PEBScounters string `json:"PEBScounters"` + SampleAfterValue string `json:"SampleAfterValue"` + MSRIndex string `json:"MSRIndex"` + MSRValue string `json:"MSRValue"` + Precise string `json:"Precise"` + CollectPEBSRecords string `json:"CollectPEBSRecords"` + TakenAlone string `json:"TakenAlone"` + CounterMask string `json:"CounterMask"` + Invert string `json:"Invert"` + EdgeDetect string `json:"EdgeDetect"` + DataLA string `json:"Data_LA"` + L1HitIndication string `json:"L1_Hit_Indication"` + Errata string `json:"Errata"` + Offcore string `json:"Offcore"` + Deprecated string `json:"Deprecated"` + PDISTCounter string `json:"PDISTCounter"` + Speculative string `json:"Speculative"` +} + +type CoreEvents struct { + Header map[string]string `json:"Header"` + Events []CoreEvent `json:"Events"` +} + +var perfMetricsEvents []CoreEvent = []CoreEvent{ + {EventName: "PERF_METRICS.RETIRING", EventCode: "0x00", UMask: "0x80", SampleAfterValue: "10000003"}, + {EventName: "PERF_METRICS.BAD_SPECULATION", EventCode: "0x00", UMask: "0x81", SampleAfterValue: "10000003"}, + {EventName: "PERF_METRICS.FRONTEND_BOUND", EventCode: "0x00", UMask: "0x82", SampleAfterValue: "10000003"}, + {EventName: "PERF_METRICS.BACKEND_BOUND", EventCode: "0x00", UMask: "0x83", SampleAfterValue: "10000003"}, + {EventName: "PERF_METRICS.HEAVY_OPERATIONS", EventCode: "0x00", UMask: "0x84", SampleAfterValue: "10000003"}, + {EventName: "PERF_METRICS.BRANCH_MISPREDICTS", EventCode: "0x00", UMask: "0x85", SampleAfterValue: "10000003"}, + {EventName: "PERF_METRICS.FETCH_LATENCY", EventCode: "0x00", UMask: "0x86", SampleAfterValue: "10000003"}, + {EventName: "PERF_METRICS.MEMORY_BOUND", EventCode: "0x00", UMask: "0x87", SampleAfterValue: "10000003"}, +} + +func NewCoreEvents(path string) (CoreEvents, error) { + var events CoreEvents + bytes, err := resources.ReadFile(path) + if err != nil { + return events, fmt.Errorf("error reading file %s: %w", path, err) + } + if err := json.Unmarshal(bytes, &events); err != nil { + return events, fmt.Errorf("error unmarshaling JSON from %s: %w", path, err) + } + return events, nil +} + +func (events CoreEvents) FindEventByName(eventName string) CoreEvent { + // check if the event is a perf metrics event + for _, perfEvent := range perfMetricsEvents { + if perfEvent.EventName == eventName { + // If the event is a perf metrics event, we return it directly. + return perfEvent + } + } + // Check if event is customized with :c, :e, or both. If it is, then we need to remove them + // from the name to match the event name in the events lists. + // examples: INST_RETIRED.ANY:c0:e1, CPU_CLK_UNHALTED.THREAD:c0 + // Get the base event name + name := strings.Split(eventName, ":")[0] + for _, event := range events.Events { + if event.EventName == name { + return event + } + } + return CoreEvent{} +} + +func (event CoreEvent) IsEmpty() bool { + return event == CoreEvent{} +} + +func (event CoreEvent) IsCollectable(metadata Metadata) bool { + if !metadata.SupportsFixedTMA && (strings.HasPrefix(event.EventName, "TOPDOWN.SLOTS") || strings.HasPrefix(event.EventName, "PERF_METRICS")) && event.EventName != "TOPDOWN.SLOTS_P" { + slog.Debug("Fixed TMA events not supported", slog.String("event", event.EventName)) + return false // TOPDOWN.SLOTS and PERF_METRICS.* events are not supported + } + if event.Offcore == "1" { + if !metadata.SupportsOCR { + slog.Debug("Off-core response (OCR) events not supported", slog.String("event", event.EventName)) + return false // Off-core response events are not supported + } + if flagScope == scopeProcess || flagScope == scopeCgroup { + slog.Debug("Off-core response (OCR) events not supported in process or cgroup scope", slog.String("event", event.EventName)) + return false // Off-core response events are not supported in process or cgroup scope + } + } + if !metadata.SupportsRefCycles && strings.Contains(event.EventName, "ref-cycles") { + slog.Debug("Ref-cycles events not supported", slog.String("event", event.EventName)) + return false // ref-cycles events are not supported + } + pebsEventNames := []string{"INT_MISC.UNKNOWN_BRANCH_CYCLES", "UOPS_RETIRED.MS"} + if !metadata.SupportsPEBS { + for _, pebsEventName := range pebsEventNames { + if strings.Contains(event.EventName, pebsEventName) { + slog.Debug("PEBS events not supported", slog.String("event", event.EventName)) + return false // PEBS events are not supported + } + } + } + return true +} + +// perfmon event name to perf event name +var fixedCounterEventNameTranslation = map[string]string{ + "INST_RETIRED.ANY": "instructions", + "INST_RETIRED.ANY_P:SUP": "instructions:k", + "CPU_CLK_UNHALTED.THREAD": "cpu-cycles", + "CPU_CLK_UNHALTED.CORE": "cpu-cycles", // srf - thread and core are the same + "CPU_CLK_UNHALTED.THREAD_P:SUP": "cpu-cycles:k", + "CPU_CLK_UNHALTED.CORE_P:SUP": "cpu-cycles:k", // srf - thread and core are the same + "CPU_CLK_UNHALTED.REF_TSC": "ref-cycles", + "CPU_CLK_UNHALTED.REF_TSC_P:SUP": "ref-cycles:k", + "TOPDOWN.SLOTS:perf_metrics": "topdown.slots", + "PERF_METRICS.BAD_SPECULATION": "topdown-bad-spec", + "PERF_METRICS.BACKEND_BOUND": "topdown-be-bound", + "PERF_METRICS.BRANCH_MISPREDICTS": "topdown-br-mispredict", + "PERF_METRICS.FRONTEND_BOUND": "topdown-fe-bound", + "PERF_METRICS.FETCH_LATENCY": "topdown-fetch-lat", + "PERF_METRICS.HEAVY_OPERATIONS": "topdown-heavy-ops", + "PERF_METRICS.MEMORY_BOUND": "topdown-mem-bound", + "PERF_METRICS.RETIRING": "topdown-retiring", +} + +func (event CoreEvent) StringForPerf() (string, error) { + if event.IsEmpty() { + return "", fmt.Errorf("event is not initialized") + } + if translatedName, ok := fixedCounterEventNameTranslation[event.EventName]; ok { + return translatedName, nil + } + var parts []string + if event.EventCode != "" { + // unit/event + unit := "cpu" + eventCode := event.EventCode + // special handling of OCR events that have EventCode "0x2A,0x2B" + // for lack of a better way to handle this, we will just use the first part + if strings.Contains(event.EventCode, ",") { + eventCode = strings.Split(event.EventCode, ",")[0] + } + parts = append(parts, fmt.Sprintf("%s/event=%s", strings.ToLower(unit), eventCode)) + } + // umask + if event.UMask != "" { + parts = append(parts, fmt.Sprintf("umask=%s", event.UMask)) + } + // cmask + if event.CounterMask != "" { + cmask, err := strconv.ParseInt(event.CounterMask, 10, 64) + if err != nil { + return "", fmt.Errorf("error parsing CounterMask %s for event %s: %w", event.CounterMask, event.EventName, err) + } + parts = append(parts, fmt.Sprintf("cmask=0x%02x", cmask)) + } + //period + if event.SampleAfterValue != "" { + parts = append(parts, fmt.Sprintf("period=%s", event.SampleAfterValue)) + } + // offcore_rsp, name + if event.Offcore == "1" { + name, msr, err := customizeOCREventName(event) + if err != nil { + return "", fmt.Errorf("error customizing offcore event name %s: %w", event.EventName, err) + } + parts = append(parts, fmt.Sprintf("offcore_rsp=%s", msr)) + parts = append(parts, fmt.Sprintf("name='%s'/", name)) + } else { + // name + parts = append(parts, fmt.Sprintf("name='%s'/", event.EventName)) + } + return strings.Join(parts, ","), nil +} + +// some offcore events have a MSR value appended to their name, like this: +// OCR.DEMAND_RFO.L3_MISS:ocr_msr_val=0x103b8000. +// Returns: +// - the event name +// - the MSR value +// - an error if the event name is not in the expected format +func customizeOCREventName(event CoreEvent) (string, string, error) { + if !strings.Contains(event.EventName, ":ocr_msr_val=") { + return event.EventName, event.MSRValue, nil + } + // parse the msr value from the event name + parts := strings.Split(event.EventName, ":ocr_msr_val=") + if len(parts) != 2 { + return "", "", fmt.Errorf("error parsing offcore event name %s: expected format 'name:ocr_msr_val=msr_value'", event.EventName) + } + name := parts[0] + msrValue := parts[1] + customizedName := fmt.Sprintf("%s.%s", name, msrValue) + return customizedName, msrValue, nil +} diff --git a/cmd/metrics/loader_perfmon_event_other.go b/cmd/metrics/loader_perfmon_event_other.go new file mode 100644 index 00000000..52c30c59 --- /dev/null +++ b/cmd/metrics/loader_perfmon_event_other.go @@ -0,0 +1,60 @@ +package metrics + +import ( + "fmt" + "log/slog" + "strings" +) + +// Copyright (C) 2021-2025 Intel Corporation +// SPDX-License-Identifier: BSD-3-Clause + +type OtherEvent struct { + EventName string +} + +type OtherEvents []OtherEvent + +func NewOtherEvents() (OtherEvents, error) { + var events OtherEvents = []OtherEvent{ + {EventName: "power/energy-pkg/"}, + {EventName: "power/energy-ram/"}, + {EventName: "cstate_core/c6-residency/"}, + {EventName: "cstate_pkg/c6-residency/"}, + } + return events, nil +} + +func (events OtherEvents) FindEventByName(eventName string) OtherEvent { + for _, event := range events { + if event.EventName == eventName { + return event + } + } + return OtherEvent{} // return an empty OtherEvent if not found +} + +func (event OtherEvent) IsEmpty() bool { + return event == OtherEvent{} +} + +func (event OtherEvent) IsCollectable(metadata Metadata) bool { + if flagScope == scopeProcess || flagScope == scopeCgroup { + slog.Debug("Other events not supported in process or cgroup scope", slog.String("event", event.EventName)) + return false // other events are not supported in process or cgroup scope + } + if !strings.Contains(metadata.PerfSupportedEvents, event.EventName) { + slog.Debug("Other event is not supported by perf", slog.String("event", event.EventName)) + return false // other events are not supported + } + return true +} + +func (event OtherEvent) StringForPerf() (string, error) { + if event.IsEmpty() { + return "", fmt.Errorf("event is not initialized") + } + // For other events, we just return the event name as is. + // This is used for events that are not part of core or uncore events. + return event.EventName, nil +} diff --git a/cmd/metrics/loader_perfmon_event_uncore.go b/cmd/metrics/loader_perfmon_event_uncore.go new file mode 100644 index 00000000..4b8fba22 --- /dev/null +++ b/cmd/metrics/loader_perfmon_event_uncore.go @@ -0,0 +1,141 @@ +package metrics + +// Copyright (C) 2021-2025 Intel Corporation +// SPDX-License-Identifier: BSD-3-Clause + +import ( + "encoding/json" + "fmt" + "log/slog" + "strconv" + "strings" +) + +type UncoreEvent struct { + Unit string `json:"Unit"` + EventCode string `json:"EventCode"` + UMask string `json:"UMask"` + PortMask string `json:"PortMask"` + FCMask string `json:"FCMask"` + UMaskExt string `json:"UMaskExt"` + EventName string `json:"EventName"` + BriefDescription string `json:"BriefDescription"` + PublicDescription string `json:"PublicDescription"` + Counter string `json:"Counter"` + ELLC string `json:"ELLC"` + Filter string `json:"Filter"` + ExtSel string `json:"ExtSel"` + Deprecated string `json:"Deprecated"` + FilterValue string `json:"FILTER_VALUE"` + CounterType string `json:"CounterType"` + UniqueID string // This field is not in the JSON. We set it to a unique value after unmarshaling. +} + +type UncoreEvents struct { + Header map[string]string `json:"Header"` + Events []UncoreEvent `json:"Events"` +} + +func NewUncoreEvents(path string) (UncoreEvents, error) { + var events UncoreEvents + bytes, err := resources.ReadFile(path) + if err != nil { + return events, fmt.Errorf("error reading file %s: %w", path, err) + } + if err := json.Unmarshal(bytes, &events); err != nil { + return events, fmt.Errorf("error unmarshaling JSON from %s: %w", path, err) + } + for i := range events.Events { + // Set the UniqueID for each event. We use this when generating perf strings + // instead of the EventName to reduce the length of the perf command line. + events.Events[i].UniqueID = fmt.Sprintf("UNC_%03d", i) + } + return events, nil +} + +func (events UncoreEvents) FindEventByName(eventName string) UncoreEvent { + // Check if event is customized with :c, :e, or both. If it is, then we need to remove them + // from the name to match the event name in the events lists. + // examples: INST_RETIRED.ANY:c0:e1, CPU_CLK_UNHALTED.THREAD:c0 + // Get the base event name + name := strings.Split(eventName, ":")[0] + for _, event := range events.Events { + if event.EventName == name { + return event + } + } + return UncoreEvent{} +} + +func (event UncoreEvent) IsEmpty() bool { + return event == UncoreEvent{} +} + +func (event UncoreEvent) IsCollectable(metadata Metadata) bool { + if !metadata.SupportsUncore { + slog.Debug("Uncore events not supported", slog.String("event", event.EventName)) + return false // uncore events are not supported + } + if flagScope == scopeProcess || flagScope == scopeCgroup { + slog.Debug("Uncore events not supported in process or cgroup scope", slog.String("event", event.EventName)) + return false + } + deviceExists := false + for uncoreDeviceName := range metadata.UncoreDeviceIDs { + if strings.EqualFold(strings.Split(event.Unit, " ")[0], uncoreDeviceName) { + deviceExists = true + break + } + } + if !deviceExists { + slog.Warn("Uncore event unit not found on target", "name", event.EventName, "unit", event.Unit) + return false // uncore device not found + } + return true +} + +func (event UncoreEvent) StringForPerf() (string, error) { + if event.IsEmpty() { + return "", fmt.Errorf("event is not initialized") + } + if event.EventCode == "" { + return "", fmt.Errorf("event %s does not have an EventCode", event.EventName) + } + // name is the uniqueID.deviceID + if event.UniqueID == "" { + return "", fmt.Errorf("event %s does not have a UniqueID", event.EventName) + } + // parse the device ID out of the event name + eventNameParts := strings.Split(event.EventName, ".") + if len(eventNameParts) < 2 { + return "", fmt.Errorf("event %s does not have a device ID in its name", event.EventName) + } + deviceID := eventNameParts[len(eventNameParts)-1] + if deviceID == "" { + return "", fmt.Errorf("event %s does not have a device ID", event.EventName) + } + var parts []string + // unit/event + parts = append(parts, fmt.Sprintf("uncore_%s_%s/event=%s", strings.ToLower(strings.Split(event.Unit, " ")[0]), deviceID, event.EventCode)) + // umask + if event.UMask != "" { + umaskVal, err := strconv.ParseInt(event.UMask, 0, 64) + if err != nil { + return "", fmt.Errorf("error parsing UMask %s for event %s: %w", event.UMask, event.EventName, err) + } + umaskHex := fmt.Sprintf("%02x", umaskVal) + if event.UMaskExt != "" { + umaskExtVal, err := strconv.ParseInt(event.UMaskExt, 0, 64) + if err != nil { + return "", fmt.Errorf("error parsing UMaskExt %s for event %s: %w", event.UMaskExt, event.EventName, err) + } + var umaskExtHex string + if umaskExtVal > 0 { + umaskExtHex = fmt.Sprintf("%x", umaskExtVal) + } + parts = append(parts, fmt.Sprintf("umask=0x%s%s", umaskExtHex, umaskHex)) + } + } + parts = append(parts, fmt.Sprintf("name='%s.%s'/", event.UniqueID, deviceID)) + return strings.Join(parts, ","), nil +} diff --git a/cmd/metrics/loader_perfmon_group_core.go b/cmd/metrics/loader_perfmon_group_core.go new file mode 100644 index 00000000..24ac150a --- /dev/null +++ b/cmd/metrics/loader_perfmon_group_core.go @@ -0,0 +1,375 @@ +package metrics + +// Copyright (C) 2021-2025 Intel Corporation +// SPDX-License-Identifier: BSD-3-Clause + +import ( + "fmt" + "io" + "log/slog" + "perfspect/internal/util" + "strconv" + "strings" +) + +type CoreGroup struct { + GeneralPurposeCounters []CoreEvent + FixedPurposeCounters []CoreEvent + MetricNames []string // List of metric names that this group represents +} + +func NewCoreGroup(metadata Metadata) CoreGroup { + return CoreGroup{ + FixedPurposeCounters: make([]CoreEvent, 0), + GeneralPurposeCounters: make([]CoreEvent, metadata.NumGeneralPurposeCounters), + MetricNames: make([]string, 0), + } +} + +func (group CoreGroup) ToGroupDefinition() GroupDefinition { + // Convert the CoreGroup to a GroupDefinition + groupDef := make(GroupDefinition, 0) + // Add fixed purpose counters + for _, event := range group.FixedPurposeCounters { + if event.IsEmpty() { + continue // Skip empty events + } + raw, err := event.StringForPerf() + if err != nil { + slog.Error("Error formatting event for perf", slog.String("event", event.EventName), slog.Any("error", err)) + continue + } + groupDef = append(groupDef, EventDefinition{ + Raw: raw, + Name: event.EventName, + }) + } + // Add general purpose counters + for _, event := range group.GeneralPurposeCounters { + if event.IsEmpty() { + continue // Skip empty events + } + raw, err := event.StringForPerf() + if err != nil { + slog.Error("Error formatting event for perf", slog.String("event", event.EventName), slog.Any("error", err)) + continue + } + groupDef = append(groupDef, EventDefinition{ + Raw: raw, + Name: event.EventName, + }) + } + return groupDef +} + +func (group CoreGroup) FindEventByName(eventName string) CoreEvent { + for _, event := range group.FixedPurposeCounters { + if event.EventName == eventName { + return event // Event found in fixed purpose counters + } + } + for _, event := range group.GeneralPurposeCounters { + if event.EventName == eventName { + return event // Event found in general purpose counters + } + } + // If we reach here, the event was not found in any of the counters + return CoreEvent{} +} + +func (group CoreGroup) Equal(other CoreGroup) bool { + if len(group.FixedPurposeCounters) != len(other.FixedPurposeCounters) { + return false // Different number of fixed purpose counters + } + // order/placement of fixed purpose counters is important + for i, event := range group.FixedPurposeCounters { + if event != other.FixedPurposeCounters[i] { + return false // Fixed purpose counter differs + } + } + if len(group.GeneralPurposeCounters) != len(other.GeneralPurposeCounters) { + return false // Different number of general purpose counters + } + // order of general purpose counters is not important + // check if the events present in the group are also present in the other group + for _, event := range group.GeneralPurposeCounters { + if event.IsEmpty() { + continue // Skip empty events + } + // if event is not in the other group, they are not equal + if otherEvent := other.FindEventByName(event.EventName); otherEvent.IsEmpty() { + return false // Event not found in other group + } + } + // check if the events present in the other group are also present in this group + for _, event := range other.GeneralPurposeCounters { + if event.IsEmpty() { + continue // Skip empty events + } + // if event is not in the group, they are not equal + if groupEvent := group.FindEventByName(event.EventName); groupEvent.IsEmpty() { + return false // Event not found in group + } + } + return true // All checks passed, groups are equal +} + +func (group CoreGroup) Copy() CoreGroup { + newGroup := CoreGroup{} + newGroup.MetricNames = make([]string, len(group.MetricNames)) + copy(newGroup.MetricNames, group.MetricNames) + newGroup.FixedPurposeCounters = make([]CoreEvent, len(group.FixedPurposeCounters)) + copy(newGroup.FixedPurposeCounters, group.FixedPurposeCounters) + newGroup.GeneralPurposeCounters = make([]CoreEvent, len(group.GeneralPurposeCounters)) + copy(newGroup.GeneralPurposeCounters, group.GeneralPurposeCounters) + return newGroup +} + +func (group *CoreGroup) Merge(other CoreGroup, metadata Metadata) error { + // Merge fixed purpose counters + for _, event := range other.FixedPurposeCounters { + if event.IsEmpty() { + continue // Skip empty events + } + if err := group.AddEvent(event, false, metadata); err != nil { + return fmt.Errorf("error adding fixed purpose counter %s: %w", event.EventName, err) + } + } + // Merge general purpose counters + for _, event := range other.GeneralPurposeCounters { + if event.IsEmpty() { + continue // Skip empty events + } + if err := group.AddEvent(event, true, metadata); err != nil { + return fmt.Errorf("error adding general purpose counter %s: %w", event.EventName, err) + } + } + // Merge metric names + group.MetricNames = util.UniqueAppend(group.MetricNames, other.MetricNames...) + return nil +} + +func (group CoreGroup) HasTakenAloneEvent() bool { + // Check if the group has an event tagged with "TakenAlone" + for i := range group.FixedPurposeCounters { + event := &group.FixedPurposeCounters[i] + if event.TakenAlone == "true" { + return true + } + } + return false +} + +func (group *CoreGroup) AddEvent(event CoreEvent, reorder bool, metadata Metadata) error { + if event.IsEmpty() { + return fmt.Errorf("event is not initialized") + } + // If the event is already in the group, no need to insert it again + if !group.FindEventByName(event.EventName).IsEmpty() { + return nil + } + // check if group already has an event that is tagged with "TakenAlone" + if event.TakenAlone == "true" && group.HasTakenAloneEvent() { + return fmt.Errorf("group already has an event tagged with TakenAlone, cannot add %s", event.EventName) + } + // only 2 offcore events are allowed in a group + if event.Offcore == "1" { + offcoreCount := 0 + for _, existingEvent := range group.GeneralPurposeCounters { + if existingEvent.Offcore == "1" { + offcoreCount++ + } + } + if offcoreCount >= 2 { + return fmt.Errorf("group already has two OCR events, cannot add %s", event.EventName) + } + } + // If the event is a perf metrics event, we handle it separately + if strings.HasPrefix(event.EventName, "PERF_METRICS.") { + if !metadata.SupportsFixedTMA { + slog.Debug("PERF_METRICS events not supported", slog.String("event", event.EventName)) + return fmt.Errorf("PERF_METRICS events not supported on target") + } + // add it to the fixed purpose counters + group.FixedPurposeCounters = append(group.FixedPurposeCounters, event) + // if TOPDOWN.SLOTS:perf_metrics isn't already in the fixed purpose counters, add it as some metric definitions don't include it + if group.FindEventByName("TOPDOWN.SLOTS:perf_metrics").IsEmpty() { + topDownEvent := CoreEvent{ + EventName: "TOPDOWN.SLOTS:perf_metrics", + EventCode: "0x00", + UMask: "0x04", + SampleAfterValue: "10000003", + Counter: "Fixed counter 3", + } + group.FixedPurposeCounters = append([]CoreEvent{topDownEvent}, group.FixedPurposeCounters...) + } + return nil // PERF_METRICS events are always added to the fixed purpose counters + } + if event.EventName == "TOPDOWN.SLOTS:perf_metrics" { + if !metadata.SupportsFixedTMA { + slog.Debug("TOPDOWN.SLOTS:perf_metrics event not supported", slog.String("event", event.EventName)) + return fmt.Errorf("TOPDOWN.SLOTS:perf_metrics event not supported on target") + } + // add it to the top of the fixed purpose counters + group.FixedPurposeCounters = append([]CoreEvent{event}, group.FixedPurposeCounters...) + return nil // TOPDOWN.SLOTS:perf_metrics events are always added to the fixed purpose counters + } + // get the list of valid counters for this event + validCounters := event.Counter + if validCounters == "" { + return fmt.Errorf("event %s has no valid counters defined", event.EventName) + } + if strings.HasPrefix(validCounters, "Fixed counter") { + fixedCounter := strings.TrimPrefix(validCounters, "Fixed counter ") + fixedCounterIndex, err := strconv.Atoi(fixedCounter) + if err != nil { + return fmt.Errorf("invalid fixed counter index %s for event %s: %w", fixedCounter, event.EventName, err) + } + if (metadata.SupportsFixedInstructions && fixedCounterIndex == 0) || (metadata.SupportsFixedCycles && fixedCounterIndex == 1) || (metadata.SupportsFixedRefCycles && fixedCounterIndex == 2) { + // if fixed counter isn't already occupied, place the event in the fixed purpose counters + for _, existingEvent := range group.FixedPurposeCounters { + if existingEvent.Counter == event.Counter { + return fmt.Errorf("fixed purpose counter %s already occupied by %s", event.Counter, existingEvent.EventName) + } + } + group.FixedPurposeCounters = append(group.FixedPurposeCounters, event) + return nil + } + // fall through to add the event to a general purpose counter + validCounters = "" + for i := range len(group.GeneralPurposeCounters) { + validCounters += fmt.Sprintf("%d,", i) + } + } + // otherwise, it is a general purpose event, check if we can place it in one of the general purpose counters + for i := range group.GeneralPurposeCounters { + if counter := group.GeneralPurposeCounters[i]; counter.IsEmpty() { + // this counter is empty, check if it is a valid counter for this event + if strings.Contains(validCounters, fmt.Sprintf("%d", i)) { + group.GeneralPurposeCounters[i] = event // place the event in this counter + return nil + } + } + } + if reorder { + // check if we can move an event that's already in the group to make room for the new event + for counter, existingEvent := range group.GeneralPurposeCounters { + // check if the new event can be placed in the current counter + if !strings.Contains(validCounters, fmt.Sprintf("%d", counter)) { + continue // not a valid counter for this event + } + // check if the existing event can be moved to another unoccupied counter + for otherCounter := 0; otherCounter < len(group.GeneralPurposeCounters); otherCounter++ { + if otherCounter == counter { + continue // skip the current counter + } + if !group.GeneralPurposeCounters[otherCounter].IsEmpty() { + continue // skip occupied counters + } + // check if the existing event is compatible with the other counter + if !strings.Contains(existingEvent.Counter, fmt.Sprintf("%d", otherCounter)) { + continue // not a valid counter for this event + } + // we can move the event to a different counter + group.GeneralPurposeCounters[otherCounter] = existingEvent // move the existing event to the new counter + group.GeneralPurposeCounters[counter] = event // place the new event in the current counter + return nil + } + } + } + // If we reach here, we couldn't find a valid counter for the event + return fmt.Errorf("no counter available for %s: %s", event.EventName, event.Counter) +} + +func (group CoreGroup) Print(w io.Writer) { + fmt.Fprintf(w, " Metric Names: %s\n", strings.Join(group.MetricNames, ", ")) + fmt.Fprintln(w, " Fixed Purpose Counters:") + for i := range group.FixedPurposeCounters { + event := &group.FixedPurposeCounters[i] + if event.IsEmpty() { + continue // Skip empty events + } + fmt.Fprintf(w, " Counter %d: %s [%s]\n", i, event.EventName, event.Counter) + } + fmt.Fprintln(w, " General Purpose Counters:") + for i := range group.GeneralPurposeCounters { + event := &group.GeneralPurposeCounters[i] + if event.IsEmpty() { + continue // Skip empty events + } + fmt.Fprintf(w, " Counter %d: %s [%s]\n", i, event.EventName, event.Counter) + } +} + +func (group CoreGroup) StringForPerf() (string, error) { + var formattedEvents []string + // add the fixed purpose counters first + for _, event := range group.FixedPurposeCounters { + if event.IsEmpty() { + continue // Skip empty events + } + // Format the event for perf + formattedEvent, err := event.StringForPerf() + if err != nil { + return "", fmt.Errorf("error formatting event %s for perf: %w", event.EventName, err) + } + // Add the formatted event to the list + formattedEvents = append(formattedEvents, formattedEvent) + } + for _, event := range group.FixedPurposeCounters { + if event.IsEmpty() { + continue // Skip empty events + } + // Format the event for perf + formattedEvent, err := event.StringForPerf() + if err != nil { + return "", fmt.Errorf("error formatting event %s for perf: %w", event.EventName, err) + } + // Add the formatted event to the list + formattedEvents = append(formattedEvents, formattedEvent) + } + if len(formattedEvents) == 0 { + return "", fmt.Errorf("no valid events found in group") + } + return fmt.Sprintf("{%s}", strings.Join(formattedEvents, ",")), nil +} + +func MergeCoreGroups(coreGroups []CoreGroup, metadata Metadata) ([]CoreGroup, error) { + i := 0 + for i < len(coreGroups) { // this style of for loop is used to allow for removal of elements + j := i + 1 + for j < len(coreGroups) { // len(coreGroups) is recalculated on each iteration + tmpGroup := coreGroups[i].Copy() // Copy the group to avoid modifying the original + if err := tmpGroup.Merge(coreGroups[j], metadata); err == nil { + coreGroups[i] = tmpGroup // Update the group at index i with the merged group + // remove the group at index j + coreGroups = append(coreGroups[:j], coreGroups[j+1:]...) + } else { + j++ // Cannot merge these groups, try the next pair + } + } + i++ + } + return coreGroups, nil +} + +func EliminateDuplicateCoreGroups(coreGroups []CoreGroup) ([]CoreGroup, error) { + // if two groups have the same events, merge them into one group + // combine the metric names of the groups + i := 0 + for i < len(coreGroups) { + j := i + 1 + for j < len(coreGroups) { + if coreGroups[i].Equal(coreGroups[j]) { + // merge the metric names + coreGroups[i].MetricNames = util.UniqueAppend(coreGroups[i].MetricNames, coreGroups[j].MetricNames...) + // remove the group at index j + coreGroups = append(coreGroups[:j], coreGroups[j+1:]...) + } else { + j++ // only increment j if we didn't remove an element + } + } + i++ + } + return coreGroups, nil +} diff --git a/cmd/metrics/loader_perfmon_group_other.go b/cmd/metrics/loader_perfmon_group_other.go new file mode 100644 index 00000000..dedcb94d --- /dev/null +++ b/cmd/metrics/loader_perfmon_group_other.go @@ -0,0 +1,89 @@ +package metrics + +// Copyright (C) 2021-2025 Intel Corporation +// SPDX-License-Identifier: BSD-3-Clause + +import ( + "fmt" + "io" + "log/slog" + "strings" +) + +type OtherGroup struct { + GeneralPurposeCounters []OtherEvent + MetricNames []string +} + +func NewOtherGroup(metadata Metadata) OtherGroup { + return OtherGroup{ + GeneralPurposeCounters: make([]OtherEvent, metadata.NumGeneralPurposeCounters), + MetricNames: make([]string, 0), + } +} + +func (group OtherGroup) ToGroupDefinition() GroupDefinition { + // Convert the CoreGroup to a GroupDefinition + groupDef := make(GroupDefinition, 0) + // Add general purpose counters + for _, event := range group.GeneralPurposeCounters { + if event.IsEmpty() { + continue // Skip empty events + } + raw, err := event.StringForPerf() + if err != nil { + slog.Error("Error formatting event for perf", slog.String("event", event.EventName), slog.Any("error", err)) + continue + } + groupDef = append(groupDef, EventDefinition{ + Raw: raw, + Name: event.EventName, + }) + } + return groupDef +} + +func (group *OtherGroup) AddEvent(event OtherEvent, _ bool) error { + if event.IsEmpty() { + return fmt.Errorf("cannot add empty event") + } + for i, existingEvent := range group.GeneralPurposeCounters { + if existingEvent.IsEmpty() { + // Found an empty slot, add the event here + group.GeneralPurposeCounters[i] = event + return nil + } + } + return fmt.Errorf("no empty slot available in OtherGroup for event %s", event.EventName) +} + +func (group OtherGroup) Print(w io.Writer) { + fmt.Fprintf(w, " Metric Names: %s\n", strings.Join(group.MetricNames, ", ")) + fmt.Fprintln(w, " General Purpose Counters:") + for i, event := range group.GeneralPurposeCounters { + if event.IsEmpty() { + continue // Skip empty events + } + fmt.Fprintf(w, " Counter %d: %s\n", i, event.EventName) + } +} + +func (group OtherGroup) StringForPerf() (string, error) { + var formattedEvents []string + for _, event := range group.GeneralPurposeCounters { + if event.IsEmpty() { + continue // Skip empty events + } + // Format the event for perf + formattedEvent, err := event.StringForPerf() + if err != nil { + return "", fmt.Errorf("error formatting event %s for perf: %w", event.EventName, err) + } + // Add the formatted event to the list + formattedEvents = append(formattedEvents, formattedEvent) + } + if len(formattedEvents) == 0 { + return "", fmt.Errorf("no valid events found in group") + } + return fmt.Sprintf("{%s}", strings.Join(formattedEvents, ",")), nil +} diff --git a/cmd/metrics/loader_perfmon_group_uncore.go b/cmd/metrics/loader_perfmon_group_uncore.go new file mode 100644 index 00000000..04bda9d0 --- /dev/null +++ b/cmd/metrics/loader_perfmon_group_uncore.go @@ -0,0 +1,273 @@ +package metrics + +// Copyright (C) 2021-2025 Intel Corporation +// SPDX-License-Identifier: BSD-3-Clause + +import ( + "fmt" + "io" + "log/slog" + "perfspect/internal/util" + "strings" +) + +type UncoreGroup struct { + GeneralPurposeCounters []UncoreEvent + MetricNames []string +} + +func NewUncoreGroup(metadata Metadata) UncoreGroup { + return UncoreGroup{ + GeneralPurposeCounters: make([]UncoreEvent, metadata.NumGeneralPurposeCounters), + } +} + +func (group UncoreGroup) ToGroupDefinition() GroupDefinition { + // Convert the CoreGroup to a GroupDefinition + groupDef := make(GroupDefinition, 0) + // Add general purpose counters + for _, event := range group.GeneralPurposeCounters { + if event.IsEmpty() { + continue // Skip empty events + } + // Format the event for perf + raw, err := event.StringForPerf() + if err != nil { + slog.Error("Error formatting event for perf", slog.String("event", event.EventName), slog.Any("error", err)) + continue + } + // Add the formatted event to the group definition + groupDef = append(groupDef, EventDefinition{ + Raw: raw, + Name: event.EventName, + }) + } + return groupDef +} + +func (group UncoreGroup) FindEventByName(eventName string) UncoreEvent { + for _, event := range group.GeneralPurposeCounters { + if event.EventName == eventName { + return event // Event found in the group + } + } + // If we reach here, the event was not found in any of the counters + return UncoreEvent{} +} + +func (group UncoreGroup) Equal(other UncoreGroup) bool { + if len(group.GeneralPurposeCounters) != len(other.GeneralPurposeCounters) { + return false // Different number of general purpose counters + } + // order of general purpose counters is not important + // check if the events present in the group are also present in the other group + for _, event := range group.GeneralPurposeCounters { + if event.IsEmpty() { + continue // Skip empty events + } + // if event is not in the other group, they are not equal + if otherEvent := other.FindEventByName(event.EventName); otherEvent.IsEmpty() { + return false // Event not found in other group + } + } + // check if the events present in the other group are also present in the group + for _, event := range other.GeneralPurposeCounters { + if event.IsEmpty() { + continue // Skip empty events + } + // if event is not in the group, they are not equal + if groupEvent := group.FindEventByName(event.EventName); groupEvent.IsEmpty() { + return false // Event not found in group + } + } + return true // All checks passed, groups are equal +} + +func (group UncoreGroup) Copy() UncoreGroup { + newGroup := UncoreGroup{} + newGroup.MetricNames = make([]string, len(group.MetricNames)) + copy(newGroup.MetricNames, group.MetricNames) + newGroup.GeneralPurposeCounters = make([]UncoreEvent, len(group.GeneralPurposeCounters)) + copy(newGroup.GeneralPurposeCounters, group.GeneralPurposeCounters) + return newGroup +} + +func (group *UncoreGroup) Merge(other UncoreGroup) error { + // Merge general purpose counters + for _, event := range other.GeneralPurposeCounters { + if event.IsEmpty() { + continue // Skip empty events + } + if err := group.AddEvent(event, true); err != nil { + return fmt.Errorf("error adding general purpose counter %s: %w", event.EventName, err) + } + } + // Merge metric names + group.MetricNames = util.UniqueAppend(group.MetricNames, other.MetricNames...) + return nil +} + +func (group *UncoreGroup) AddEvent(event UncoreEvent, reorder bool) error { + if event.IsEmpty() { + return fmt.Errorf("event is not initialized") + } + if group.FindEventByName(event.EventName) != (UncoreEvent{}) { + // Event is already in the group, no need to insert it again + return nil + } + // the new event's unit must match the unit of the other events already in the group + for _, existingEvent := range group.GeneralPurposeCounters { + if existingEvent.IsEmpty() { + continue // Skip empty events + } + if existingEvent.Unit != event.Unit { + return fmt.Errorf("incompatible unit for %s, %s != %s", event.EventName, existingEvent.Unit, event.Unit) + } + } + // get the list of valid counters for this event + validCounters := event.Counter + if validCounters == "" { + return fmt.Errorf("event %s has no valid counters defined", event.EventName) + } + // check if the group has an open counter that is in the valid counters list + for i := range group.GeneralPurposeCounters { + if counter := group.GeneralPurposeCounters[i]; counter.IsEmpty() { + // this counter is empty, check if it is a valid counter for this event + if strings.Contains(validCounters, fmt.Sprintf("%d", i)) { + group.GeneralPurposeCounters[i] = event // place the event in this counter + return nil + } + } + } + if reorder { + // check if we can move an event that's already in the group to make room for the new event + for counter, existingEvent := range group.GeneralPurposeCounters { + // check if the new event can be placed in the current counter + if !strings.Contains(validCounters, fmt.Sprintf("%d", counter)) { + continue // not a valid counter for this event + } + // check if the existing event can be moved to another unoccupied counter + for otherCounter := 0; otherCounter < len(group.GeneralPurposeCounters); otherCounter++ { + if otherCounter == counter { + continue // skip the current counter + } + if !group.GeneralPurposeCounters[otherCounter].IsEmpty() { + continue // skip occupied counters + } + // check if the existing event is compatible with the other counter + if !strings.Contains(existingEvent.Counter, fmt.Sprintf("%d", otherCounter)) { + continue // not a valid counter for this event + } + // we can move the event to a different counter + group.GeneralPurposeCounters[otherCounter] = existingEvent // move the existing event to the new counter + group.GeneralPurposeCounters[counter] = event // place the new event in the current counter + return nil + } + } + } + // If we reach here, we couldn't find a valid counter for the event + return fmt.Errorf("no counter available for %s: %s", event.EventName, event.Counter) +} + +func (group UncoreGroup) Print(w io.Writer) { + fmt.Fprintf(w, " Metric Names: %s\n", strings.Join(group.MetricNames, ", ")) + fmt.Fprintln(w, " General Purpose Counters:") + for i, event := range group.GeneralPurposeCounters { + if event.IsEmpty() { + continue // Skip empty events + } + fmt.Fprintf(w, " Counter %d: %s [%s]\n", i, event.EventName, event.Counter) + } +} + +func (group UncoreGroup) StringForPerf() (string, error) { + var formattedEvents []string + for i, event := range group.GeneralPurposeCounters { + if event.IsEmpty() { + continue // Skip empty events + } + // Format the event for perf + formattedEvent, err := event.StringForPerf() + if err != nil { + return "", fmt.Errorf("error formatting event %s for perf: %w", group.GeneralPurposeCounters[i].EventName, err) + } + // Add the formatted event to the list + formattedEvents = append(formattedEvents, formattedEvent) + } + if len(formattedEvents) == 0 { + return "", fmt.Errorf("no valid events found in group") + } + return fmt.Sprintf("{%s}", strings.Join(formattedEvents, ",")), nil +} + +func MergeUncoreGroups(uncoreGroups []UncoreGroup) ([]UncoreGroup, error) { + i := 0 + for i < len(uncoreGroups) { // this style of for loop is used to allow for removal of elements + j := i + 1 + for j < len(uncoreGroups) { // len(coreGroups) is recalculated on each iteration + tmpGroup := uncoreGroups[i].Copy() // Copy the group to avoid modifying the original + if err := tmpGroup.Merge(uncoreGroups[j]); err == nil { + uncoreGroups[i] = tmpGroup // Update the group at index i with the merged group + // remove the group at index j + uncoreGroups = append(uncoreGroups[:j], uncoreGroups[j+1:]...) + } else { + j++ // Cannot merge these groups, try the next pair + } + } + i++ + } + return uncoreGroups, nil +} + +func EliminateDuplicateUncoreGroups(uncoreGroups []UncoreGroup) ([]UncoreGroup, error) { + // if two groups have the same events, merge them into one group + // combine the metric names of the groups + i := 0 + for i < len(uncoreGroups) { + j := i + 1 + for j < len(uncoreGroups) { + if uncoreGroups[i].Equal(uncoreGroups[j]) { + // merge the metric names + uncoreGroups[i].MetricNames = util.UniqueAppend(uncoreGroups[i].MetricNames, uncoreGroups[j].MetricNames...) + // remove the group at index j + uncoreGroups = append(uncoreGroups[:j], uncoreGroups[j+1:]...) + } else { + j++ // only increment j if we didn't remove an element + } + } + i++ + } + return uncoreGroups, nil +} + +func ExpandUncoreGroups(uncoreGroups []UncoreGroup, uncoreDeviceIDs map[string][]int) ([]UncoreGroup, error) { + var expandedGroups []UncoreGroup + for _, group := range uncoreGroups { + groupUnit := group.GeneralPurposeCounters[0].Unit // Assume all events in the group have the same unit + if groupUnit == "" { + return nil, fmt.Errorf("group has no unit defined") + } + // Create a new group for each uncore device ID + for deviceType, deviceIDs := range uncoreDeviceIDs { + if !strings.EqualFold(deviceType, groupUnit) { + continue // Skip if the device type does not match the group unit + } + for _, deviceID := range deviceIDs { + // Create a new group for this device ID + newGroup := group.Copy() + for counter, event := range group.GeneralPurposeCounters { + if event.IsEmpty() { + continue // Skip empty events + } + // add the device ID to the event's name + newName := fmt.Sprintf("%s.%d", event.EventName, deviceID) + newEvent := event // Create a copy of the event + newEvent.EventName = newName // Update the event name with the device ID + newGroup.GeneralPurposeCounters[counter] = newEvent // Update the event in the new group + } + expandedGroups = append(expandedGroups, newGroup) + } + } + } + return expandedGroups, nil +} diff --git a/cmd/metrics/loader_util.go b/cmd/metrics/loader_util.go new file mode 100644 index 00000000..257411e3 --- /dev/null +++ b/cmd/metrics/loader_util.go @@ -0,0 +1,339 @@ +package metrics + +// Copyright (C) 2021-2025 Intel Corporation +// SPDX-License-Identifier: BSD-3-Clause + +import ( + "fmt" + "log/slog" + "regexp" + "strings" + + "github.com/Knetic/govaluate" +) + +// configureMetrics configures the metrics for use +func configureMetrics(metrics []MetricDefinition, uncollectableEvents []string, metadata Metadata) ([]MetricDefinition, error) { + var err error + // remove metrics that use uncollectable events + if flagTransactionRate == 0 { + uncollectableEvents = append(uncollectableEvents, "TXN") // if transaction rate is not set, remove TXN event + } + metrics, err = removeIfUncollectableEvents(metrics, uncollectableEvents) + if err != nil { + return nil, fmt.Errorf("failed to remove uncollectable events: %w", err) + } + + // replace constants variables with their values + metrics, err = replaceConstants(metrics, metadata) + if err != nil { + return nil, fmt.Errorf("failed to replace constants: %w", err) + } + + // transform metric expressions from perfmon format to perfspect format + metrics, err = transformMetricExpressions(metrics) + if err != nil { + return nil, fmt.Errorf("failed to transform metric expressions: %w", err) + } + + // replace constant numbers masquerading as variables with their values + metrics, err = replaceConstantNumbers(metrics) + if err != nil { + return nil, fmt.Errorf("failed to replace constant numbers: %w", err) + } + + // set evaluable expressions for each metric + metrics, err = setEvaluableExpressions(metrics) + if err != nil { + return nil, fmt.Errorf("failed to set evaluable expressions: %w", err) + } + + // initialize metric variables + metrics, err = initializeMetricVariables(metrics) + if err != nil { + return nil, fmt.Errorf("failed to initialize metric variables: %w", err) + } + + // remove "metric_" prefix from metric names + metrics, err = removeMetricsPrefix(metrics) + if err != nil { + return nil, fmt.Errorf("failed to remove metrics prefix: %w", err) + } + + return metrics, nil +} + +// perfmonToPerfspectConditional transforms if/else to ternary conditional (? :) so expression evaluator can handle it +// simple: +// from: if else +// to: ? : +// less simple: +// from: (() if else ()) +// to: ( ? () : +func perfmonToPerfspectConditional(origIn string) (out string, err error) { + numIfs := strings.Count(origIn, "if") + if numIfs == 0 { + out = origIn + return + } + in := origIn + for i := range numIfs { + if i > 0 { + in = out + } + var idxIf, idxElse, idxExpression1, idxExpression3 int + if idxIf = strings.Index(in, "if"); idxIf == -1 { + err = fmt.Errorf("didn't find expected if: %s", in) + return + } + if idxElse = strings.Index(in, "else"); idxElse == -1 { + err = fmt.Errorf("if without else in expression: %s", in) + return + } + // find the beginning of expression 1 (also end of expression 0) + var parens int + for i := idxIf - 1; i >= 0; i-- { + c := in[i] + switch c { + case ')': + parens += 1 + case '(': + parens -= 1 + default: + continue + } + if parens < 0 { + idxExpression1 = i + 1 + break + } + } + // find the end of expression 2 (also beginning of expression 3) + parens = 0 + for i, c := range in[idxElse+5:] { + switch c { + case '(': + parens += 1 + case ')': + parens -= 1 + default: + continue + } + if parens < 0 { + idxExpression3 = i + idxElse + 6 + break + } + } + if idxExpression3 == 0 { + idxExpression3 = len(in) + } + expression0 := in[:idxExpression1] + expression1 := in[idxExpression1 : idxIf-1] + condition := in[idxIf+3 : idxElse-1] + expression2 := in[idxElse+5 : idxExpression3] + expression3 := in[idxExpression3:] + var space0, space3 string + if expression0 != "" { + space0 = " " + } + if expression3 != "" { + space3 = " " + } + out = fmt.Sprintf("%s%s%s ? %s : %s%s%s", expression0, space0, condition, expression1, expression2, space3, expression3) + } + return +} + +// replaceConstants replaces constant variables in expressions with their values +func replaceConstants(metrics []MetricDefinition, metadata Metadata) ([]MetricDefinition, error) { + // get constants as strings + tscFreq := fmt.Sprintf("%f", float64(metadata.TSCFrequencyHz)) + var tsc string + switch flagGranularity { + case granularitySystem: + tsc = fmt.Sprintf("%f", float64(metadata.TSC)) + case granularitySocket: + tsc = fmt.Sprintf("%f", float64(metadata.TSC)/float64(metadata.SocketCount)) + case granularityCPU: + tsc = fmt.Sprintf("%f", float64(metadata.TSC)/(float64(metadata.SocketCount*metadata.CoresPerSocket*metadata.ThreadsPerCore))) + default: + return nil, fmt.Errorf("unknown granularity: %s", flagGranularity) + } + coresPerSocket := fmt.Sprintf("%f", float64(metadata.CoresPerSocket)) + chasPerSocket := fmt.Sprintf("%f", float64(len(metadata.UncoreDeviceIDs["cha"]))) + socketCount := fmt.Sprintf("%f", float64(metadata.SocketCount)) + hyperThreadingOn := fmt.Sprintf("%t", metadata.ThreadsPerCore > 1) + threadsPerCore := fmt.Sprintf("%f", float64(metadata.ThreadsPerCore)) + + for i := range metrics { + metric := &metrics[i] + // replace constants with their values + metric.Expression = strings.ReplaceAll(metric.Expression, "[SYSTEM_TSC_FREQ]", tscFreq) + metric.Expression = strings.ReplaceAll(metric.Expression, "[TSC]", tsc) + metric.Expression = strings.ReplaceAll(metric.Expression, "[CORES_PER_SOCKET]", coresPerSocket) + metric.Expression = strings.ReplaceAll(metric.Expression, "[CHAS_PER_SOCKET]", chasPerSocket) + metric.Expression = strings.ReplaceAll(metric.Expression, "[SOCKET_COUNT]", socketCount) + metric.Expression = strings.ReplaceAll(metric.Expression, "[HYPERTHREADING_ON]", hyperThreadingOn) + metric.Expression = strings.ReplaceAll(metric.Expression, "[CONST_THREAD_COUNT]", threadsPerCore) + metric.Expression = strings.ReplaceAll(metric.Expression, "[TXN]", fmt.Sprintf("%f", flagTransactionRate)) + } + return metrics, nil +} + +// removeIfUncollectableEvents removes metrics that use uncollectable events +func removeIfUncollectableEvents(metrics []MetricDefinition, uncollectableEvents []string) ([]MetricDefinition, error) { + // remove metrics that use uncollectable events + var filteredMetrics []MetricDefinition + for i := range metrics { + metric := &metrics[i] + foundUncollectable := false + for _, uncollectableEvent := range uncollectableEvents { + if strings.Contains(metric.Expression, uncollectableEvent) { + slog.Debug("removing metric that uses uncollectable event", slog.String("metric", metric.Name), slog.String("event", uncollectableEvent)) + foundUncollectable = true + break + } + } + if !foundUncollectable { + filteredMetrics = append(filteredMetrics, *metric) + } + } + return filteredMetrics, nil +} + +// transformMetricExpressions transforms metric expressions from perfmon format to perfspect format +// it replaces if/else with ternary conditional, replaces "> =" with ">=", and "< =" with "<=" +func transformMetricExpressions(metrics []MetricDefinition) ([]MetricDefinition, error) { + // transform if/else to ?/: + var transformedMetrics []MetricDefinition + for i := range metrics { + metric := &metrics[i] + transformed, err := perfmonToPerfspectConditional(metric.Expression) + if err != nil { + return nil, fmt.Errorf("failed to transform metric expression: %w", err) + } + // replace "> =" with ">=" and "< =" with "<=" + transformed = strings.ReplaceAll(transformed, "> =", ">=") + transformed = strings.ReplaceAll(transformed, "< =", "<=") + if transformed != metric.Expression { + slog.Debug("transformed metric", slog.String("name", metric.Name), slog.String("transformed", transformed)) + metric.Expression = transformed + } + // add the transformed metric to the list + transformedMetrics = append(transformedMetrics, *metric) + } + return transformedMetrics, nil +} + +// setEvaluableExpressions sets the EvaluableExpression for each metric +// this allows the expression to be evaluated later without parsing it again +func setEvaluableExpressions(metrics []MetricDefinition) ([]MetricDefinition, error) { + evaluatorFunctions := getEvaluatorFunctions() + for i := range metrics { + metric := &metrics[i] + var err error + if metric.Evaluable, err = govaluate.NewEvaluableExpressionWithFunctions(metric.Expression, evaluatorFunctions); err != nil { + slog.Error("failed to create evaluable expression for metric", slog.String("error", err.Error()), slog.String("name", metric.Name), slog.String("expression", metric.Expression)) + return nil, err + } + } + return metrics, nil +} + +// replaceConstantNumbers replaces constant numbers masquerading as variables with their values, e.g., [20] -> 20 +// there may be more than one with differing values in the expression, so use a regex to find them all +func replaceConstantNumbers(metrics []MetricDefinition) ([]MetricDefinition, error) { + reConstantInt := regexp.MustCompile(`\[(\d+)\]`) + for i := range metrics { + metric := &metrics[i] + for { + // find the first match + found := reConstantInt.FindStringSubmatchIndex(metric.Expression) + if found == nil { + break // no more matches + } + // match[2] is the start of the number, match[3] is the end of the number + number := metric.Expression[found[2]:found[3]] + // replace the whole match with the number + metric.Expression = strings.ReplaceAll(metric.Expression, metric.Expression[found[0]:found[1]], number) + } + } + return metrics, nil +} + +// initializeMetricVariables initializes the Variables map for each metric +// it parses the expression and finds all variables in the form [variable_name] +// the variable name is stored in the map with a value of -1 to indicate it has not yet been determined +// the value will be set later when the group index is determined +func initializeMetricVariables(metrics []MetricDefinition) ([]MetricDefinition, error) { + // get a list of the variables in the expression + for i := range metrics { + metric := &metrics[i] + metric.Variables = make(map[string]int) + expressionIdx := 0 + for { + startVar := strings.IndexRune(metric.Expression[expressionIdx:], '[') + if startVar == -1 { // no more vars in this expression + break + } + endVar := strings.IndexRune(metric.Expression[expressionIdx:], ']') + if endVar == -1 { + return nil, fmt.Errorf("didn't find end of variable indicator (]) in expression: %s", metric.Expression[expressionIdx:]) + } + // add the variable name to the map, set group index to -1 to indicate it has not yet been determined + metric.Variables[metric.Expression[expressionIdx:][startVar+1:endVar]] = -1 + expressionIdx += endVar + 1 + } + } + return metrics, nil +} + +// removeMetricsPrefix removes the "metric_" prefix from metric names +// this is done to make the names more readable and consistent with other metrics +// it is assumed that all metric names start with "metric_" +func removeMetricsPrefix(metrics []MetricDefinition) ([]MetricDefinition, error) { + for i := range metrics { + metric := &metrics[i] + metric.Name = strings.TrimPrefix(metric.Name, "metric_") + } + return metrics, nil +} + +// getEvaluatorFunctions defines functions that can be called in metric expressions +func getEvaluatorFunctions() (functions map[string]govaluate.ExpressionFunction) { + functions = make(map[string]govaluate.ExpressionFunction) + functions["max"] = func(args ...any) (any, error) { + var leftVal float64 + var rightVal float64 + switch t := args[0].(type) { + case int: + leftVal = float64(t) + case float64: + leftVal = t + } + switch t := args[1].(type) { + case int: + rightVal = float64(t) + case float64: + rightVal = t + } + return max(leftVal, rightVal), nil + } + functions["min"] = func(args ...any) (any, error) { + var leftVal float64 + var rightVal float64 + switch t := args[0].(type) { + case int: + leftVal = float64(t) + case float64: + leftVal = t + } + switch t := args[1].(type) { + case int: + rightVal = float64(t) + case float64: + rightVal = t + } + return min(leftVal, rightVal), nil + } + return +} diff --git a/cmd/metrics/metric_defs_test.go b/cmd/metrics/loader_util_test.go similarity index 83% rename from cmd/metrics/metric_defs_test.go rename to cmd/metrics/loader_util_test.go index dc87f112..721cf5db 100644 --- a/cmd/metrics/metric_defs_test.go +++ b/cmd/metrics/loader_util_test.go @@ -11,7 +11,7 @@ func TestTransformConditional(t *testing.T) { var err error in = "100 * x / y" - if out, err = transformConditional(in); err != nil { + if out, err = perfmonToPerfspectConditional(in); err != nil { t.Error(err) } if out != in { @@ -19,12 +19,12 @@ func TestTransformConditional(t *testing.T) { } in = "100 * x / y if z" - if _, err = transformConditional(in); err == nil { + if _, err = perfmonToPerfspectConditional(in); err == nil { t.Error("didn't catch if without else") } in = "a if b else c" - if out, err = transformConditional(in); err != nil { + if out, err = perfmonToPerfspectConditional(in); err != nil { t.Error(err) } if out != "b ? a : c" { @@ -32,7 +32,7 @@ func TestTransformConditional(t *testing.T) { } in = "(1 - x / y) if z > 1 else 0" - if out, err = transformConditional(in); err != nil { + if out, err = perfmonToPerfspectConditional(in); err != nil { t.Error(err) } if out != "z > 1 ? (1 - x / y) : 0" { @@ -40,7 +40,7 @@ func TestTransformConditional(t *testing.T) { } in = "1 - a / b if c > 1 else 0" - if out, err = transformConditional(in); err != nil { + if out, err = perfmonToPerfspectConditional(in); err != nil { t.Error(err) } if out != "c > 1 ? 1 - a / b : 0" { @@ -48,7 +48,7 @@ func TestTransformConditional(t *testing.T) { } in = "1 - ( (a) if c else d )" - if out, err = transformConditional(in); err != nil { + if out, err = perfmonToPerfspectConditional(in); err != nil { t.Error(err) } if out != "1 - ( c ? (a) : d )" { @@ -57,7 +57,7 @@ func TestTransformConditional(t *testing.T) { // from SPR metrics -- TMA_....DRAM_Bound(%) in = "100 * ( min( ( ( ( a / ( b ) ) - ( min( ( ( ( ( 1 - ( ( ( 19 * ( c * ( 1 + ( d / e ) ) ) + 10 * ( ( f * ( 1 + ( d / e ) ) ) + ( g * ( 1 + ( d / e ) ) ) + ( h * ( 1 + ( d / e ) ) ) ) ) / ( ( 19 * ( c * ( 1 + ( d / e ) ) ) + 10 * ( ( f * ( 1 + ( d / e ) ) ) + ( g * ( 1 + ( d / e ) ) ) + ( h * ( 1 + ( d / e ) ) ) ) ) + ( 25 * ( ( i * ( 1 + ( d / e ) ) ) ) + 33 * ( ( j * ( 1 + ( d / e ) ) ) ) ) ) ) ) ) * ( a / ( b ) ) ) if ( ( 1000000 ) * ( j + i ) > e ) else 0 ) ) , ( 1 ) ) ) ) ) , ( 1 ) ) )" - if out, err = transformConditional(in); err != nil { + if out, err = perfmonToPerfspectConditional(in); err != nil { t.Error(err) } if out != "100 * ( min( ( ( ( a / ( b ) ) - ( min( ( ( ( ( 1000000 ) * ( j + i ) > e ) ? ( ( 1 - ( ( ( 19 * ( c * ( 1 + ( d / e ) ) ) + 10 * ( ( f * ( 1 + ( d / e ) ) ) + ( g * ( 1 + ( d / e ) ) ) + ( h * ( 1 + ( d / e ) ) ) ) ) / ( ( 19 * ( c * ( 1 + ( d / e ) ) ) + 10 * ( ( f * ( 1 + ( d / e ) ) ) + ( g * ( 1 + ( d / e ) ) ) + ( h * ( 1 + ( d / e ) ) ) ) ) + ( 25 * ( ( i * ( 1 + ( d / e ) ) ) ) + 33 * ( ( j * ( 1 + ( d / e ) ) ) ) ) ) ) ) ) * ( a / ( b ) ) ) : 0 ) ) , ( 1 ) ) ) ) ) , ( 1 ) ) )" { @@ -66,7 +66,7 @@ func TestTransformConditional(t *testing.T) { // from SPR metrics -- TMA_....Ports_Utilization(%) in = "100 * ( ( a + ( b / ( c ) ) * ( d - e ) + ( f + ( g / ( h + i + g + j ) ) * k ) ) / ( c ) if ( l < ( d - e ) ) else ( f + ( g / ( h + i + g + j ) ) * k ) / ( c ) )" - if out, err = transformConditional(in); err != nil { + if out, err = perfmonToPerfspectConditional(in); err != nil { t.Error(err) } if out != "100 * ( ( l < ( d - e ) ) ? ( a + ( b / ( c ) ) * ( d - e ) + ( f + ( g / ( h + i + g + j ) ) * k ) ) / ( c ) : ( f + ( g / ( h + i + g + j ) ) * k ) / ( c ) )" { diff --git a/cmd/metrics/metadata.go b/cmd/metrics/metadata.go index 5190475f..20e9e4c2 100644 --- a/cmd/metrics/metadata.go +++ b/cmd/metrics/metadata.go @@ -24,6 +24,7 @@ import ( // Metadata is the representation of the platform's state and capabilities type Metadata struct { + NumGeneralPurposeCounters int // number of general purpose counters CoresPerSocket int CPUSocketMap map[int]int UncoreDeviceIDs map[string][]int @@ -36,10 +37,11 @@ type Metadata struct { PerfSupportedEvents string PMUDriverVersion string SocketCount int - SupportsInstructions bool SupportsFixedCycles bool SupportsFixedInstructions bool SupportsFixedTMA bool + SupportsFixedRefCycles bool + SupportsInstructions bool SupportsRefCycles bool SupportsUncore bool SupportsPEBS bool @@ -96,6 +98,12 @@ func LoadMetadata(myTarget target.Target, noRoot bool, noSystemSummary bool, per return } metadata.Microarchitecture = cpu.MicroArchitecture + // Number of General Purpose Counters + metadata.NumGeneralPurposeCounters, err = getNumGPCounters(metadata.Microarchitecture) + if err != nil { + err = fmt.Errorf("failed to get number of general purpose counters: %v", err) + return + } // the rest of the metadata is retrieved by running scripts in parallel metadataScripts, err := getMetadataScripts(noRoot, perfPath, metadata.Microarchitecture, noSystemSummary) if err != nil { @@ -169,6 +177,15 @@ func LoadMetadata(myTarget target.Target, noRoot bool, noSystemSummary bool, per slog.Warn("Fixed-counter 'cpu-cycles' events not supported", slog.String("output", output)) } } + // Fixed-counter ref-cycles events + if metadata.SupportsFixedRefCycles, output, err = getSupportsFixedEvent("ref-cycles", scriptOutputs); err != nil { + slog.Warn("failed to determine if fixed-counter 'ref-cycles' is supported, assuming not supported", slog.String("error", err.Error())) + err = nil + } else { + if !metadata.SupportsFixedRefCycles { + slog.Warn("Fixed-counter 'ref-cycles' events not supported", slog.String("output", output)) + } + } // Fixed-counter instructions events if metadata.SupportsFixedInstructions, output, err = getSupportsFixedEvent("instructions", scriptOutputs); err != nil { slog.Warn("failed to determine if fixed-counter 'instructions' is supported, assuming not supported", slog.String("error", err.Error())) @@ -261,17 +278,17 @@ func getMetadataScripts(noRoot bool, perfPath string, uarch string, noSystemSumm }, { Name: "perf stat pebs", - ScriptTemplate: perfPath + " stat -a -e cpu/event=0xad,umask=0x40,period=1000003,name='INT_MISC.UNKNOWN_BRANCH_CYCLES'/ sleep 1", + ScriptTemplate: perfPath + " stat -a -e INT_MISC.UNKNOWN_BRANCH_CYCLES sleep 1", Superuser: !noRoot, }, { Name: "perf stat ocr", - ScriptTemplate: perfPath + " stat -a -e cpu/event=0x2a,umask=0x01,offcore_rsp=0x104004477,name='OCR.READS_TO_CORE.LOCAL_DRAM'/ sleep 1", + ScriptTemplate: perfPath + " stat -a -e OCR.READS_TO_CORE.LOCAL_DRAM sleep 1", Superuser: !noRoot, }, { Name: "perf stat tma", - ScriptTemplate: perfPath + " stat -a -e '{cpu/event=0x00,umask=0x04,period=10000003,name='TOPDOWN.SLOTS'/,cpu/event=0x00,umask=0x81,period=10000003,name='PERF_METRICS.BAD_SPECULATION'/}' sleep 1", + ScriptTemplate: perfPath + " stat -a -e '{topdown.slots, topdown-bad-spec}' sleep 1", Superuser: !noRoot, }, { @@ -284,6 +301,11 @@ func getMetadataScripts(noRoot bool, perfPath string, uarch string, noSystemSumm ScriptTemplate: perfPath + " stat -a -e '{{{.CpuCyclesList}}}' sleep 1", Superuser: !noRoot, }, + { + Name: "perf stat fixed ref-cycles", + ScriptTemplate: perfPath + " stat -a -e '{{{.RefCyclesList}}}' sleep 1", + Superuser: !noRoot, + }, { Name: "pmu driver version", ScriptTemplate: "dmesg | grep -A 1 \"Intel PMU driver\" | tail -1 | awk '{print $NF}'", @@ -321,6 +343,12 @@ func getMetadataScripts(noRoot bool, perfPath string, uarch string, noSystemSumm eventList = append(eventList, "cpu-cycles") } scriptDef.ScriptTemplate = strings.Replace(scriptDef.ScriptTemplate, "{{.CpuCyclesList}}", strings.Join(eventList, ","), -1) + case "perf stat fixed ref-cycles": + var eventList []string + for range numGPCounters + 1 { + eventList = append(eventList, "ref-cycles") + } + scriptDef.ScriptTemplate = strings.Replace(scriptDef.ScriptTemplate, "{{.RefCyclesList}}", strings.Join(eventList, ","), -1) } metadataScripts = append(metadataScripts, scriptDef) } @@ -575,7 +603,7 @@ func getSupportsOCR(scriptOutputs map[string]script.ScriptOutput) (supported boo // getSupportsFixedTMA - checks if the fixed TMA counter events are // supported by perf. // -// We check for the TOPDOWN.SLOTS and PERF_METRICS.BAD_SPECULATION events as +// We check for the topdown.slots and topdown-bad-spec events as // an indicator of support for fixed TMA counter support. At the time of // writing, these events are not supported on AWS m7i VMs or AWS m6i VMs. On // AWS m7i VMs, we get an error from the perf stat command below. On AWS m6i @@ -593,8 +621,10 @@ func getSupportsFixedTMA(scriptOutputs map[string]script.ScriptOutput) (supporte // event values being zero or equal to each other is 2nd indication that these events are not (properly) supported vals := make(map[string]float64) lines := strings.Split(output, "\n") - // example line: " 784333932 TOPDOWN.SLOTS (59.75%)" - re := regexp.MustCompile(`\s+(\d+)\s+(\w*\.*\w*)\s+.*`) + // example lines: + // " 1078623236 topdown.slots (34.40%)" + // " 83572327 topdown-bad-spec (34.40%)" + re := regexp.MustCompile(`^\s*([0-9]+)\s+(topdown[\w.\-]+)`) for _, line := range lines { // count may include commas as thousands separators, remove them line = strings.ReplaceAll(line, ",", "") @@ -607,8 +637,8 @@ func getSupportsFixedTMA(scriptOutputs map[string]script.ScriptOutput) (supporte } } } - topDownSlots := vals["TOPDOWN.SLOTS"] - badSpeculation := vals["PERF_METRICS.BAD_SPECULATION"] + topDownSlots := vals["topdown.slots"] + badSpeculation := vals["topdown-bad-spec"] supported = topDownSlots != badSpeculation && topDownSlots != 0 && badSpeculation != 0 return } @@ -616,29 +646,11 @@ func getSupportsFixedTMA(scriptOutputs map[string]script.ScriptOutput) (supporte func getNumGPCounters(uarch string) (numGPCounters int, err error) { shortUarch := uarch[:3] switch shortUarch { - case "BDX": - fallthrough - case "SKX": - fallthrough - case "CLX": + case "BDX", "SKX", "CLX": numGPCounters = 4 - case "ICX": - fallthrough - case "SPR": - fallthrough - case "EMR": - fallthrough - case "SRF": - fallthrough - case "CWF": - fallthrough - case "GNR": + case "ICX", "SPR", "EMR", "SRF", "CWF", "GNR": numGPCounters = 8 - case "Gen": - fallthrough - case "Ber": - fallthrough - case "Tur": + case "Gen", "Ber", "Tur": numGPCounters = 5 default: err = fmt.Errorf("unsupported uarch: %s", uarch) diff --git a/cmd/metrics/metric.go b/cmd/metrics/metric.go index ff817cd2..2bdbebdc 100644 --- a/cmd/metrics/metric.go +++ b/cmd/metrics/metric.go @@ -13,7 +13,6 @@ import ( "strings" "sync" - "github.com/Knetic/govaluate" mapset "github.com/deckarep/golang-set/v2" ) @@ -86,46 +85,6 @@ func ProcessEvents(perfEvents [][]byte, eventGroupDefinitions []GroupDefinition, return } -// GetEvaluatorFunctions defines functions that can be called in metric expressions -func GetEvaluatorFunctions() (functions map[string]govaluate.ExpressionFunction) { - functions = make(map[string]govaluate.ExpressionFunction) - functions["max"] = func(args ...any) (any, error) { - var leftVal float64 - var rightVal float64 - switch t := args[0].(type) { - case int: - leftVal = float64(t) - case float64: - leftVal = t - } - switch t := args[1].(type) { - case int: - rightVal = float64(t) - case float64: - rightVal = t - } - return max(leftVal, rightVal), nil - } - functions["min"] = func(args ...any) (any, error) { - var leftVal float64 - var rightVal float64 - switch t := args[0].(type) { - case int: - leftVal = float64(t) - case float64: - leftVal = t - } - switch t := args[1].(type) { - case int: - rightVal = float64(t) - case float64: - rightVal = t - } - return min(leftVal, rightVal), nil - } - return -} - // lock to protect metric variable map that holds the event group where a variable value will be retrieved var metricVariablesLock = sync.RWMutex{} @@ -206,11 +165,13 @@ func getExpressionVariableValues(metric MetricDefinition, frame EventFrame, prev err = fmt.Errorf("variable value set to -2 (shouldn't happen): %s", variableName) return } - // set the variable value to the event value divided by the perf collection time to normalize the value to 1 second - if len(frame.EventGroups) <= metric.Variables[variableName] { - err = fmt.Errorf("event groups have changed") + // check if previously assigned event group is available + if metric.Variables[variableName] >= len(frame.EventGroups) { + // it may not be available, for example, in cpu granularity where uncore events are only in the first CPU of a socket + err = fmt.Errorf("variable %s assigned to group %d, but only %d groups available", variableName, metric.Variables[variableName], len(frame.EventGroups)) return } + // set the variable value to the event value divided by the perf collection time to normalize the value to 1 second variables[variableName] = frame.EventGroups[metric.Variables[variableName]].EventValues[variableName] / (frame.Timestamp - previousTimestamp) // adjust cstate_core/c6-residency value if hyperthreading is enabled // why here? so we don't have to change the perfmon metric formula diff --git a/cmd/metrics/metric_defs.go b/cmd/metrics/metric_defs.go deleted file mode 100644 index c3c8ba93..00000000 --- a/cmd/metrics/metric_defs.go +++ /dev/null @@ -1,318 +0,0 @@ -package metrics - -// Copyright (C) 2021-2025 Intel Corporation -// SPDX-License-Identifier: BSD-3-Clause - -import ( - "encoding/json" - "fmt" - "log/slog" - "os" - "path/filepath" - "regexp" - "strings" - - "github.com/Knetic/govaluate" -) - -type Variable struct { - Name string - EventGroupIdx int // initialized to -1 to indicate that a group has not yet been identified -} - -type MetricDefinition struct { - Name string `json:"name"` - Expression string `json:"expression"` - Variables map[string]int // parsed from Expression for efficiency, int represents group index - Evaluable *govaluate.EvaluableExpression // parse expression once, store here for use in metric evaluation -} - -// LoadMetricDefinitions reads and parses metric definitions from an architecture-specific metric -// definition file. When the override path argument is empty, the function will load metrics from -// the file associated with the platform's architecture found in the provided metadata. When -// a list of metric names is provided, only those metric definitions will be loaded. -func LoadMetricDefinitions(metricDefinitionOverridePath string, selectedMetrics []string, metadata Metadata) (metrics []MetricDefinition, err error) { - var bytes []byte - if metricDefinitionOverridePath != "" { - bytes, err = os.ReadFile(metricDefinitionOverridePath) // #nosec G304 - if err != nil { - return - } - } else { - uarch := strings.ToLower(strings.Split(metadata.Microarchitecture, "_")[0]) - uarch = strings.Split(uarch, " ")[0] - // use alternate events/metrics when TMA fixed counters are not supported - alternate := "" - if (uarch == "icx" || uarch == "spr" || uarch == "emr" || uarch == "gnr") && !metadata.SupportsFixedTMA { - alternate = "_nofixedtma" - } - metricFileName := fmt.Sprintf("%s%s.json", uarch, alternate) - if bytes, err = resources.ReadFile(filepath.Join("resources", "metrics", metadata.Architecture, metadata.Vendor, metricFileName)); err != nil { - return - } - } - var metricsInFile []MetricDefinition - if err = json.Unmarshal(bytes, &metricsInFile); err != nil { - return - } - // if a list of metric names provided, reduce list to match - if len(selectedMetrics) > 0 { - // confirm provided metric names are valid (included in metrics defined in file) - // and build list of metrics based on provided list of metric names - metricMap := make(map[string]MetricDefinition) - for _, metric := range metricsInFile { - metricMap[metric.Name] = metric - } - for _, selectedMetricName := range selectedMetrics { - if _, ok := metricMap[selectedMetricName]; !ok { - err = fmt.Errorf("provided metric name not found: %s", selectedMetricName) - return - } - metrics = append(metrics, metricMap[selectedMetricName]) - } - } else { - metrics = metricsInFile - } - return -} - -// ConfigureMetrics prepares metrics for use by the evaluator, by e.g., replacing -// metric constants with known values and aligning metric variables to perf event -// groups -func ConfigureMetrics(loadedMetrics []MetricDefinition, uncollectableEvents []string, evaluatorFunctions map[string]govaluate.ExpressionFunction, metadata Metadata) (metrics []MetricDefinition, err error) { - // get constants as strings - tscFreq := fmt.Sprintf("%f", float64(metadata.TSCFrequencyHz)) - var tsc string - switch flagGranularity { - case granularitySystem: - tsc = fmt.Sprintf("%f", float64(metadata.TSC)) - case granularitySocket: - tsc = fmt.Sprintf("%f", float64(metadata.TSC)/float64(metadata.SocketCount)) - case granularityCPU: - tsc = fmt.Sprintf("%f", float64(metadata.TSC)/(float64(metadata.SocketCount*metadata.CoresPerSocket*metadata.ThreadsPerCore))) - default: - err = fmt.Errorf("unknown granularity: %s", flagGranularity) - return - } - coresPerSocket := fmt.Sprintf("%f", float64(metadata.CoresPerSocket)) - chasPerSocket := fmt.Sprintf("%f", float64(len(metadata.UncoreDeviceIDs["cha"]))) - socketCount := fmt.Sprintf("%f", float64(metadata.SocketCount)) - hyperThreadingOn := fmt.Sprintf("%t", metadata.ThreadsPerCore > 1) - threadsPerCore := fmt.Sprintf("%f", float64(metadata.ThreadsPerCore)) - // load retire latency constants - var retireLatencies map[string]string - if retireLatencies, err = LoadRetireLatencies(metadata); err != nil { - slog.Error("failed to load retire latencies", slog.String("error", err.Error())) - return - } - // configure each metric - reConstantInt := regexp.MustCompile(`\[(\d+)\]`) - for metricIdx := range loadedMetrics { - tmpMetric := loadedMetrics[metricIdx] - // abbreviate event names in metric expressions to match abbreviations used in uncollectableEvents - tmpMetric.Expression = abbreviateEventName(tmpMetric.Expression) - // skip metrics that use uncollectable events - foundUncollectable := false - for _, uncollectableEvent := range uncollectableEvents { - if strings.Contains(tmpMetric.Expression, uncollectableEvent) { - slog.Debug("removing metric that uses uncollectable event", slog.String("metric", tmpMetric.Name), slog.String("event", uncollectableEvent)) - foundUncollectable = true - break - } - } - if foundUncollectable { - continue - } - // transform if/else to ?/: - var transformed string - if transformed, err = transformConditional(tmpMetric.Expression); err != nil { - return - } - // replace "> =" with ">=" and "< =" with "<=" - transformed = strings.ReplaceAll(transformed, "> =", ">=") - transformed = strings.ReplaceAll(transformed, "< =", "<=") - if transformed != tmpMetric.Expression { - slog.Debug("transformed metric", slog.String("metric name", tmpMetric.Name), slog.String("transformed", transformed)) - tmpMetric.Expression = transformed - } - // replace constants with their values - tmpMetric.Expression = strings.ReplaceAll(tmpMetric.Expression, "[SYSTEM_TSC_FREQ]", tscFreq) - tmpMetric.Expression = strings.ReplaceAll(tmpMetric.Expression, "[TSC]", tsc) - tmpMetric.Expression = strings.ReplaceAll(tmpMetric.Expression, "[CORES_PER_SOCKET]", coresPerSocket) - tmpMetric.Expression = strings.ReplaceAll(tmpMetric.Expression, "[CHAS_PER_SOCKET]", chasPerSocket) - tmpMetric.Expression = strings.ReplaceAll(tmpMetric.Expression, "[SOCKET_COUNT]", socketCount) - tmpMetric.Expression = strings.ReplaceAll(tmpMetric.Expression, "[HYPERTHREADING_ON]", hyperThreadingOn) - tmpMetric.Expression = strings.ReplaceAll(tmpMetric.Expression, "[CONST_THREAD_COUNT]", threadsPerCore) - tmpMetric.Expression = strings.ReplaceAll(tmpMetric.Expression, "[TXN]", fmt.Sprintf("%f", flagTransactionRate)) - // replace retire latencies - for retireEvent, retireLatency := range retireLatencies { - // replace :retire_latency with value - tmpMetric.Expression = strings.ReplaceAll(tmpMetric.Expression, fmt.Sprintf("[%s:retire_latency]", retireEvent), retireLatency) - } - // replace constant numbers masquerading as variables with their values, e.g., [20] -> 20 - // there may be more than one with differing values in the expression, so use a regex to find them all - for { - // find the first match - found := reConstantInt.FindStringSubmatchIndex(tmpMetric.Expression) - if found == nil { - break // no more matches - } - // match[2] is the start of the number, match[3] is the end of the number - number := tmpMetric.Expression[found[2]:found[3]] - // replace the whole match with the number - tmpMetric.Expression = strings.ReplaceAll(tmpMetric.Expression, tmpMetric.Expression[found[0]:found[1]], number) - } - // get a list of the variables in the expression - tmpMetric.Variables = make(map[string]int) - expressionIdx := 0 - for { - startVar := strings.IndexRune(tmpMetric.Expression[expressionIdx:], '[') - if startVar == -1 { // no more vars in this expression - break - } - endVar := strings.IndexRune(tmpMetric.Expression[expressionIdx:], ']') - if endVar == -1 { - err = fmt.Errorf("didn't find end of variable indicator (]) in expression: %s", tmpMetric.Expression[expressionIdx:]) - return - } - // add the variable name to the map, set group index to -1 to indicate it has not yet been determined - tmpMetric.Variables[tmpMetric.Expression[expressionIdx:][startVar+1:endVar]] = -1 - expressionIdx += endVar + 1 - } - if tmpMetric.Evaluable, err = govaluate.NewEvaluableExpressionWithFunctions(tmpMetric.Expression, evaluatorFunctions); err != nil { - slog.Error("failed to create evaluable expression for metric", slog.String("error", err.Error()), slog.String("metric name", tmpMetric.Name), slog.String("metric expression", tmpMetric.Expression)) - return - } - metrics = append(metrics, tmpMetric) - } - return -} - -// transformConditional transforms if/else to ternary conditional (? :) so expression evaluator can handle it -// simple: -// from: if else -// to: ? : -// less simple: -// from: (() if else ()) -// to: ( ? () : -func transformConditional(origIn string) (out string, err error) { - numIfs := strings.Count(origIn, "if") - if numIfs == 0 { - out = origIn - return - } - in := origIn - for i := range numIfs { - if i > 0 { - in = out - } - var idxIf, idxElse, idxExpression1, idxExpression3 int - if idxIf = strings.Index(in, "if"); idxIf == -1 { - err = fmt.Errorf("didn't find expected if: %s", in) - return - } - if idxElse = strings.Index(in, "else"); idxElse == -1 { - err = fmt.Errorf("if without else in expression: %s", in) - return - } - // find the beginning of expression 1 (also end of expression 0) - var parens int - for i := idxIf - 1; i >= 0; i-- { - c := in[i] - switch c { - case ')': - parens += 1 - case '(': - parens -= 1 - default: - continue - } - if parens < 0 { - idxExpression1 = i + 1 - break - } - } - // find the end of expression 2 (also beginning of expression 3) - parens = 0 - for i, c := range in[idxElse+5:] { - switch c { - case '(': - parens += 1 - case ')': - parens -= 1 - default: - continue - } - if parens < 0 { - idxExpression3 = i + idxElse + 6 - break - } - } - if idxExpression3 == 0 { - idxExpression3 = len(in) - } - expression0 := in[:idxExpression1] - expression1 := in[idxExpression1 : idxIf-1] - condition := in[idxIf+3 : idxElse-1] - expression2 := in[idxElse+5 : idxExpression3] - expression3 := in[idxExpression3:] - var space0, space3 string - if expression0 != "" { - space0 = " " - } - if expression3 != "" { - space3 = " " - } - out = fmt.Sprintf("%s%s%s ? %s : %s%s%s", expression0, space0, condition, expression1, expression2, space3, expression3) - } - return -} - -type PlatformInfo struct { - ModelName string `json:"Model name"` - CPUFamily string `json:"CPU family"` - Model string `json:"Model"` - ThreadsPerCore string `json:"Thread(s) per core"` - CoresPerSocket string `json:"Core(s) per socket"` - Sockets string `json:"Socket(s)"` - Stepping string `json:"Stepping"` - L3Cache string `json:"L3 cache"` - NUMANodes string `json:"NUMA node(s)"` - TMAVersion string `json:"TMA version"` -} - -type MetricStats struct { - Min float64 `json:"MIN"` - Max float64 `json:"MAX"` - Mean float64 `json:"MEAN"` -} - -type RetireLatency struct { - Platform PlatformInfo `json:"Platform"` - Data map[string]MetricStats `json:"Data"` -} - -func LoadRetireLatencies(metadata Metadata) (retireLatencies map[string]string, err error) { - uarch := strings.ToLower(strings.Split(metadata.Microarchitecture, "_")[0]) - uarch = strings.Split(uarch, " ")[0] - filename := fmt.Sprintf("%s_retire_latency.json", uarch) - var bytes []byte - if bytes, err = resources.ReadFile(filepath.Join("resources", "metrics", metadata.Architecture, metadata.Vendor, filename)); err != nil { - // not all architectures have retire latencies defined - err = nil - return - } - var retireLatency RetireLatency - if err = json.Unmarshal(bytes, &retireLatency); err != nil { - slog.Error("failed to unmarshal retire latencies", slog.String("error", err.Error())) - return - } - // create a map of retire latencies - retireLatencies = make(map[string]string) - for event, stats := range retireLatency.Data { - // use the mean value for the retire latency - retireLatencies[event] = fmt.Sprintf("%f", stats.Mean) - } - slog.Debug("loaded retire latencies", slog.Any("latencies", retireLatencies)) - return -} diff --git a/cmd/metrics/metrics.go b/cmd/metrics/metrics.go index 65409599..f6c58e95 100644 --- a/cmd/metrics/metrics.go +++ b/cmd/metrics/metrics.go @@ -728,23 +728,15 @@ func processRawData(localOutputDir string) error { return err } defer eventsFile.Close() - // load event definitions - var eventGroupDefinitions []GroupDefinition - var uncollectableEvents []string - if eventGroupDefinitions, uncollectableEvents, err = LoadEventGroups(flagEventFilePath, metadata); err != nil { - err = fmt.Errorf("failed to load event definitions: %w", err) - return err - } - // load metric definitions - var loadedMetrics []MetricDefinition - if loadedMetrics, err = LoadMetricDefinitions(flagMetricFilePath, flagMetricsList, metadata); err != nil { - err = fmt.Errorf("failed to load metric definitions: %w", err) + // load metric and event group definitions + loader, err := NewLoader(metadata.Microarchitecture) + if err != nil { + err = fmt.Errorf("failed to create metric and event loader: %w", err) return err } - // configure metrics - var metricDefinitions []MetricDefinition - if metricDefinitions, err = ConfigureMetrics(loadedMetrics, uncollectableEvents, GetEvaluatorFunctions(), metadata); err != nil { - err = fmt.Errorf("failed to configure metrics: %w", err) + metricDefinitions, eventGroupDefinitions, err := loader.Load(flagMetricFilePath, flagEventFilePath, flagMetricsList, metadata) + if err != nil { + err = fmt.Errorf("failed to load metric and event definitions: %w", err) return err } @@ -1191,32 +1183,24 @@ func prepareMetrics(targetContext *targetContext, localTempDir string, channelEr channelError <- targetError{target: myTarget, err: targetContext.err} return } - // load event definitions - var uncollectableEvents []string - if targetContext.groupDefinitions, uncollectableEvents, err = LoadEventGroups(flagEventFilePath, targetContext.metadata); err != nil { - err = fmt.Errorf("failed to load event definitions: %w", err) - _ = statusUpdate(myTarget.GetName(), fmt.Sprintf("Error: %s", err.Error())) - targetContext.err = err - channelError <- targetError{target: myTarget, err: err} - return - } - // load metric definitions - var loadedMetrics []MetricDefinition - if loadedMetrics, err = LoadMetricDefinitions(flagMetricFilePath, flagMetricsList, targetContext.metadata); err != nil { - err = fmt.Errorf("failed to load metric definitions: %w", err) + // load metric and event groups + loader, err := NewLoader(targetContext.metadata.Microarchitecture) + if err != nil { + err = fmt.Errorf("failed to create metric and event loader: %w", err) _ = statusUpdate(myTarget.GetName(), fmt.Sprintf("Error: %s", err.Error())) targetContext.err = err channelError <- targetError{target: myTarget, err: err} return } - // configure metrics - if targetContext.metricDefinitions, err = ConfigureMetrics(loadedMetrics, uncollectableEvents, GetEvaluatorFunctions(), targetContext.metadata); err != nil { - err = fmt.Errorf("failed to configure metrics: %w", err) + targetContext.metricDefinitions, targetContext.groupDefinitions, err = loader.Load(flagMetricFilePath, flagEventFilePath, flagMetricsList, targetContext.metadata) + if err != nil { + err = fmt.Errorf("failed to load metric and event definitions: %w", err) _ = statusUpdate(myTarget.GetName(), fmt.Sprintf("Error: %s", err.Error())) targetContext.err = err channelError <- targetError{target: myTarget, err: err} return } + // configure the prometheus metrics if requested if flagPrometheusServer { for _, def := range targetContext.metricDefinitions { desc := fmt.Sprintf("%s (expr: %s)", def.Name, def.Expression) @@ -1234,6 +1218,7 @@ func prepareMetrics(targetContext *targetContext, localTempDir string, channelEr prometheus.MustRegister(m) } } + // signal exit with no error channelError <- targetError{target: myTarget, err: nil} } diff --git a/cmd/metrics/perf.go b/cmd/metrics/perf.go index a047f7da..b7df55f8 100644 --- a/cmd/metrics/perf.go +++ b/cmd/metrics/perf.go @@ -98,16 +98,18 @@ func getPerfCommandArgs(pids []string, cgroups []string, timeout int, eventGroup args = append(args, "--for-each-cgroup", strings.Join(cgroups, ",")) // collect only for these cgroups } // -e: event groups to collect - args = append(args, "-e") - var groups []string + //args = append(args, "-e") + //var groups []string for _, group := range eventGroups { var events []string for _, event := range group { events = append(events, event.Raw) } - groups = append(groups, fmt.Sprintf("{%s}", strings.Join(events, ","))) + formattedGroup := fmt.Sprintf("'{%s}'", strings.Join(events, ",")) + args = append(args, "-e", formattedGroup) + //groups = append(groups, fmt.Sprintf("{%s}", strings.Join(events, ","))) } - args = append(args, fmt.Sprintf("'%s'", strings.Join(groups, ","))) + //args = append(args, fmt.Sprintf("'%s'", strings.Join(groups, ","))) if len(argsApplication) > 0 { // add application args args = append(args, "--") diff --git a/cmd/metrics/resources/events/x86_64/GenuineIntel/emr.txt b/cmd/metrics/resources/events/x86_64/GenuineIntel/emr.txt deleted file mode 100644 index e85e21ac..00000000 --- a/cmd/metrics/resources/events/x86_64/GenuineIntel/emr.txt +++ /dev/null @@ -1,201 +0,0 @@ -# SapphireRapids event list - -cpu/event=0x51,umask=0x01,period=100003,name='L1D.REPLACEMENT'/, -cpu/event=0x24,umask=0xe4,period=200003,name='L2_RQSTS.ALL_CODE_RD'/, -cpu/event=0xd1,umask=0x01,period=1000003,name='MEM_LOAD_RETIRED.L1_HIT'/, -cpu/event=0x25,umask=0x1f,period=100003,name='L2_LINES_IN.ALL'/, -cpu/event=0xa6,umask=0x02,period=2000003,name='EXE_ACTIVITY.1_PORTS_UTIL'/, -cpu/event=0xa6,umask=0x04,period=2000003,name='EXE_ACTIVITY.2_PORTS_UTIL'/, -cpu/event=0xa6,umask=0x80,period=2000003,name='EXE_ACTIVITY.3_PORTS_UTIL:u0x80'/, -cpu/event=0xa6,umask=0xc,period=2000003,name='EXE_ACTIVITY.2_PORTS_UTIL:u0xc'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xd1,umask=0x10,period=100021,name='MEM_LOAD_RETIRED.L2_MISS'/, -cpu/event=0x24,umask=0x24,period=200003,name='L2_RQSTS.CODE_RD_MISS'/, -cpu/event=0x11,umask=0x0e,period=100003,name='ITLB_MISSES.WALK_COMPLETED'/, -cpu/event=0x47,umask=0x03,cmask=0x03,period=1000003,name='MEMORY_ACTIVITY.STALLS_L1D_MISS'/, -cpu/event=0xa6,umask=0x40,cmask=0x02,period=1000003,name='EXE_ACTIVITY.BOUND_ON_STORES'/, -cpu/event=0xa6,umask=0x21,cmask=0x05,period=2000003,name='EXE_ACTIVITY.BOUND_ON_LOADS'/, -cpu/event=0xad,umask=0x10,period=1000003,name='INT_MISC.UOP_DROPPING'/, -cpu/event=0xad,umask=0x40,period=1000003,name='INT_MISC.UNKNOWN_BRANCH_CYCLES'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x12,umask=0x0e,period=100003,name='DTLB_LOAD_MISSES.WALK_COMPLETED'/, -cpu/event=0x12,umask=0x04,period=100003,name='DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M'/, -cpu/event=0x13,umask=0x0e,period=100003,name='DTLB_STORE_MISSES.WALK_COMPLETED'/, -cpu/event=0xd1,umask=0x02,period=200003,name='MEM_LOAD_RETIRED.L2_HIT'/, -cpu/event=0x3c,umask=0x02,period=25003,name='CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE'/, -cpu/event=0x3c,umask=0x08,period=2000003,name='CPU_CLK_UNHALTED.REF_DISTRIBUTED'/, -cpu/event=0xa2,umask=0x02,period=2000003,name='RESOURCE_STALLS.SCOREBOARD'/, -cpu/event=0xa3,umask=0x04,cmask=0x04,period=1000003,name='CYCLE_ACTIVITY.STALLS_TOTAL'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x00,umask=0x04,period=10000003,name='TOPDOWN.SLOTS'/, -cpu/event=0x00,umask=0x81,period=10000003,name='PERF_METRICS.BAD_SPECULATION'/, -cpu/event=0x00,umask=0x83,period=10000003,name='PERF_METRICS.BACKEND_BOUND'/, -cpu/event=0x00,umask=0x82,period=10000003,name='PERF_METRICS.FRONTEND_BOUND'/, -cpu/event=0x00,umask=0x80,period=10000003,name='PERF_METRICS.RETIRING'/, -cpu/event=0x00,umask=0x86,period=10000003,name='PERF_METRICS.FETCH_LATENCY'/, -cpu/event=0x00,umask=0x87,period=10000003,name='PERF_METRICS.MEMORY_BOUND'/, -cpu/event=0x00,umask=0x85,period=10000003,name='PERF_METRICS.BRANCH_MISPREDICTS'/, -cpu/event=0x00,umask=0x84,period=10000003,name='PERF_METRICS.HEAVY_OPERATIONS'/, -cpu/event=0x47,umask=0x09,cmask=0x09,period=1000003,name='MEMORY_ACTIVITY.STALLS_L3_MISS'/, -cpu/event=0x80,umask=0x04,period=500009,name='ICACHE_DATA.STALLS'/, -cpu/event=0x83,umask=0x04,period=200003,name='ICACHE_TAG.STALLS'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xc2,umask=0x02,period=2000003,name='UOPS_RETIRED.SLOTS'/, -cpu/event=0xae,umask=0x01,period=2000003,name='UOPS_ISSUED.ANY'/, -cpu/event=0x87,umask=0x01,period=500009,name='DECODE.LCP'/, # 0,1,2,3 -cpu/event=0x61,umask=0x02,period=100003,name='DSB2MITE_SWITCHES.PENALTY_CYCLES'/, # 0,1,2,3 -cpu/event=0xe5,umask=0x03,period=1000003,name='MEM_UOP_RETIRED.ANY'/, -cpu/event=0xc0,umask=0x10,period=2000003,name='INST_RETIRED.MACRO_FUSED'/, -cpu/event=0xc2,umask=0x04,cmask=0x01,period=2000003,name='UOPS_RETIRED.MS:c1:e1'/, # [*]cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xc4,umask=0x00,period=100003,name='BR_INST_RETIRED.ALL_BRANCHES'/, -cpu/event=0xc5,umask=0x00,period=100003,name='BR_MISP_RETIRED.ALL_BRANCHES'/, -cpu/event=0xcf,umask=0x10,cmask=0x00,period=100003,name='FP_ARITH_INST_RETIRED2.512B_PACKED_HALF'/, -cpu/event=0xcf,umask=0x08,cmask=0x00,period=100003,name='FP_ARITH_INST_RETIRED2.256B_PACKED_HALF'/, -cpu/event=0xc7,umask=0x80,cmask=0x00,period=100003,name='FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE'/, -cpu/event=0xc7,umask=0x40,cmask=0x00,period=100003,name='FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE'/, -cpu/event=0xc7,umask=0x20,cmask=0x00,period=100003,name='FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE'/, -cpu/event=0xc7,umask=0x10,cmask=0x00,period=100003,name='FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x47,umask=0x03,cmask=0x03,period=1000003,name='MEMORY_ACTIVITY.STALLS_L1D_MISS'/, -cpu/event=0x47,umask=0x05,cmask=0x05,period=1000003,name='MEMORY_ACTIVITY.STALLS_L2_MISS'/, -cpu/event=0x12,umask=0x20,cmask=0x01,period=100003,name='DTLB_LOAD_MISSES.STLB_HIT:c1'/, -cpu/event=0x12,umask=0x10,cmask=0x01,period=100003,name='DTLB_LOAD_MISSES.WALK_ACTIVE'/, -cpu/event=0xa3,umask=0x10,cmask=0x10,period=1000003,name='CYCLE_ACTIVITY.CYCLES_MEM_ANY'/, -cpu/event=0xb0,umask=0x09,cmask=0x01,period=1000003,name='ARITH.DIV_ACTIVE'/, -cpu/event=0xad,umask=0x80,period=500009,name='INT_MISC.CLEAR_RESTEER_CYCLES'/, -cpu/event=0xec,umask=0x02,period=2000003,name='CPU_CLK_UNHALTED.DISTRIBUTED'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xd3,umask=0x10,cmask=0x00,period=100007,name='MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM'/, -cpu/event=0xd1,umask=0x08,cmask=0x00,period=200003,name='MEM_LOAD_RETIRED.L1_MISS'/, -cpu/event=0xd1,umask=0x80,cmask=0x00,period=1000003,name='MEM_LOAD_RETIRED.LOCAL_PMM'/, -cpu/event=0xb1,umask=0x01,cmask=0x03,period=2000003,name='UOPS_EXECUTED.CYCLES_GE_3'/, -cpu/event=0xc2,umask=0x04,period=2000003,name='UOPS_RETIRED.MS'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xd0,umask=0x21,cmask=0x00,period=1000003,name='MEM_INST_RETIRED.LOCK_LOADS'/, -cpu/event=0xd0,umask=0x82,cmask=0x00,period=1000003,name='MEM_INST_RETIRED.ALL_STORES'/, -cpu/event=0x24,umask=0xe2,cmask=0x00,period=2000003,name='L2_RQSTS.ALL_RFO'/, -cpu/event=0x24,umask=0xc2,cmask=0x00,period=2000003,name='L2_RQSTS.RFO_HIT'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x2a,umask=0x01,cmask=0x00,offcore_rsp=0x8003C0001,name='OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD'/, -cpu/event=0x2a,umask=0x01,cmask=0x00,offcore_rsp=0x10003C0002,name='OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM'/, -cpu/event=0x20,umask=0x04,cmask=0x01,period=1000003,name='OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO'/, -cpu/event=0xd1,umask=0x40,cmask=0x00,period=100007,name='MEM_LOAD_RETIRED.FB_HIT'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x79,umask=0x04,cmask=0x01,period=2000003,name='IDQ.MITE_CYCLES_ANY'/, -cpu/event=0x79,umask=0x04,cmask=0x06,period=2000003,name='IDQ.MITE_CYCLES_OK'/, -cpu/event=0x79,umask=0x08,cmask=0x01,period=2000003,name='IDQ.DSB_CYCLES_ANY'/, -cpu/event=0x79,umask=0x08,cmask=0x06,period=2000003,name='IDQ.DSB_CYCLES_OK'/, -cpu/event=0xec,umask=0x02,period=2000003,name='CPU_CLK_UNHALTED.DISTRIBUTED'/, -cpu/event=0xb7,umask=0x02,period=2000003,name='EXE.AMX_BUSY'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xd3,umask=0x02,cmask=0x00,period=1000003,name='MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM'/, -cpu/event=0xd3,umask=0x01,cmask=0x00,period=100007,name='MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM'/, -cpu/event=0x2a,umask=0x01,offcore_rsp=0x104004477,name='OCR.READS_TO_CORE.LOCAL_DRAM'/, -cpu/event=0x2a,umask=0x01,offcore_rsp=0x730004477,name='OCR.READS_TO_CORE.REMOTE_DRAM'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xd2,umask=0x02,cmask=0x00,period=20011,name='MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD'/, -cpu/event=0xd2,umask=0x04,cmask=0x00,period=20011,name='MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD'/, -cpu/event=0x47,umask=0x02,cmask=0x02,period=1000003,name='MEMORY_ACTIVITY.CYCLES_L1D_MISS'/, -cpu/event=0x2a,umask=0x01,offcore_rsp=0x90002380,name='OCR.HWPF_L3.REMOTE'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x2a,umask=0x01,cmask=0x00,offcore_rsp=0x1030004477,name='OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM'/, -cpu/event=0x2a,umask=0x01,offcore_rsp=0x84002380,name='OCR.HWPF_L3.L3_MISS_LOCAL'/, -cpu/event=0x20,umask=0x08,cmask=0x01,period=1000003,name='OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD'/, -cpu/event=0x20,umask=0x08,cmask=0x04,period=1000003,name='OFFCORE_REQUESTS_OUTSTANDING.DATA_RD:c4'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xe7,umask=0x0c,cmask=0x00,period=100003,name='INT_VEC_RETIRED.ADD_256'/, -cpu/event=0xe7,umask=0x20,cmask=0x00,period=100003,name='INT_VEC_RETIRED.VNNI_256'/, -cpu/event=0xe7,umask=0x80,cmask=0x00,period=100003,name='INT_VEC_RETIRED.MUL_256'/, -cpu/event=0x79,umask=0x08,cmask=0x00,period=2000003,name='IDQ.DSB_UOPS'/, -cpu/event=0x79,umask=0x04,period=100003,name='IDQ.MITE_UOPS'/, -cpu/event=0x79,umask=0x20,period=100003,name='IDQ.MS_UOPS'/, -cpu/event=0xa8,umask=0x01,cmask=0x00,period=2000003,name='LSD.UOPS'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xd3,umask=0x08,cmask=0x00,period=100007,name='MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD'/, -cpu/event=0xd3,umask=0x04,cmask=0x00,period=100007,name='MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM'/, -cpu/event=0x2a,umask=0x01,offcore_rsp=0x1030004477,name='OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM'/, -cpu/event=0x2a,umask=0x01,offcore_rsp=0x830004477,name='OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD'/, -cpu-cycles:k, -ref-cycles:k, -instructions:k; - -#C6 -cstate_core/c6-residency/; -cstate_pkg/c6-residency/; - -#UPI -upi/event=0x02,umask=0x0f,name='UNC_UPI_TxL_FLITS.ALL_DATA'/; - -#CHA (Cache) -cha/event=0x35,umask=0xc80ffe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_CRD'/, -cha/event=0x35,umask=0xc8177e01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE'/, -cha/event=0x36,umask=0xc8177e01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE'/; - -cha/event=0x35,umask=0xC816FE01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL'/, -cha/event=0x36,umask=0xc816fe01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL'/, -cha/event=0x35,umask=0xC896FE01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL'/, -cha/event=0x35,umask=0xC8977E01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE'/; - -cha/event=0x35,umask=0xccd7fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA'/, -cha/event=0x35,umask=0xc817fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD'/, -cha/event=0x35,umask=0xc897fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF'/, -cha/event=0x36,umask=0xC817fe01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD'/; - -#CHA (IO Bandwidth) -cha/event=0x35,umask=0xc8f3ff04,name='UNC_CHA_TOR_INSERTS.IO_PCIRDCUR'/, -cha/event=0x35,umask=0xCC43FF04,name='UNC_CHA_TOR_INSERTS.IO_ITOM'/, -cha/event=0x35,umask=0xCD43FF04,name='UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR'/, -cha/event=0x01,umask=0x00,name='UNC_CHA_CLOCKTICKS'/; - -#IMC (memory read/writes) -imc/event=0x05,umask=0xcf,name='UNC_M_CAS_COUNT.RD'/, -imc/event=0x05,umask=0xf0,name='UNC_M_CAS_COUNT.WR'/; - -#power -power/energy-pkg/, -power/energy-ram/; diff --git a/cmd/metrics/resources/events/x86_64/GenuineIntel/emr_nofixedtma.txt b/cmd/metrics/resources/events/x86_64/GenuineIntel/emr_nofixedtma.txt deleted file mode 100644 index 4c814405..00000000 --- a/cmd/metrics/resources/events/x86_64/GenuineIntel/emr_nofixedtma.txt +++ /dev/null @@ -1,135 +0,0 @@ -# Emerald Rapids event list for platforms that don't have support for the fixed counter -# TMA events, e.g., some AWS VMs. -# Note that there are no more than 10 events per group. On these same platforms, the cpu-cycles fixed -# counter is not supported so a general purpose counter will be used. - -cpu/event=0x51,umask=0x01,period=100003,name='L1D.REPLACEMENT'/, -cpu/event=0x24,umask=0xe4,period=200003,name='L2_RQSTS.ALL_CODE_RD'/, -cpu/event=0xd1,umask=0x01,period=1000003,name='MEM_LOAD_RETIRED.L1_HIT'/, -cpu/event=0x25,umask=0x1f,period=100003,name='L2_LINES_IN.ALL'/, -cpu/event=0xc4,umask=0x00,period=100003,name='BR_INST_RETIRED.ALL_BRANCHES'/, -cpu/event=0xc5,umask=0x00,period=100003,name='BR_MISP_RETIRED.ALL_BRANCHES'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xd1,umask=0x10,period=100021,name='MEM_LOAD_RETIRED.L2_MISS'/, -cpu/event=0x24,umask=0x24,period=200003,name='L2_RQSTS.CODE_RD_MISS'/, -cpu/event=0x11,umask=0x0e,period=100003,name='ITLB_MISSES.WALK_COMPLETED'/, -cpu/event=0x47,umask=0x03,cmask=0x03,period=1000003,name='MEMORY_ACTIVITY.STALLS_L1D_MISS'/, -cpu/event=0xa6,umask=0x40,cmask=0x02,period=1000003,name='EXE_ACTIVITY.BOUND_ON_STORES'/, -cpu/event=0xa6,umask=0x21,cmask=0x05,period=2000003,name='EXE_ACTIVITY.BOUND_ON_LOADS'/, -cpu/event=0xad,umask=0x10,period=1000003,name='INT_MISC.UOP_DROPPING'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x12,umask=0x0e,period=100003,name='DTLB_LOAD_MISSES.WALK_COMPLETED'/, -cpu/event=0x12,umask=0x04,period=100003,name='DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M'/, -cpu/event=0x13,umask=0x0e,period=100003,name='DTLB_STORE_MISSES.WALK_COMPLETED'/, -cpu/event=0xd1,umask=0x02,period=200003,name='MEM_LOAD_RETIRED.L2_HIT'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x47,umask=0x09,cmask=0x09,period=1000003,name='MEMORY_ACTIVITY.STALLS_L3_MISS'/, -cpu/event=0x80,umask=0x04,period=500009,name='ICACHE_DATA.STALLS'/, -cpu/event=0x83,umask=0x04,period=200003,name='ICACHE_TAG.STALLS'/, -cpu-cycles, -ref-cycles, -instructions; - -# events for TMA metrics without fixed counter support (group 1) -cpu/event=0x9c,umask=0x01,name='IDQ_UOPS_NOT_DELIVERED.CORE'/, -cpu/event=0xa4,umask=0x01,name='TOPDOWN.SLOTS_P'/, -cpu/event=0x9c,umask=0x01,name='IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE'/, -cpu/event=0xc2,umask=0x02,name='UOPS_RETIRED.SLOTS'/, -cpu/event=0xae,umask=0x01,name='UOPS_ISSUED.ANY'/, -cpu/event=0x87,umask=0x01,name='DECODE.LCP'/, -cpu/event=0x61,umask=0x02,name='DSB2MITE_SWITCHES.PENALTY_CYCLES'/, -cpu-cycles, -ref-cycles, -instructions; - -# events for TMA metrics without fixed counter support (group 2) -cpu/event=0xa4,umask=0x02,name='TOPDOWN.BACKEND_BOUND_SLOTS'/, -cpu/event=0xa4,umask=0x08,name='TOPDOWN.BR_MISPREDICT_SLOTS'/, -cpu/event=0xa4,umask=0x10,name='TOPDOWN.MEMORY_BOUND_SLOTS'/, -cpu/event=0xc2,umask=0x01,name='UOPS_RETIRED.HEAVY'/, -cpu/event=0xe5,umask=0x03,name='MEM_UOP_RETIRED.ANY'/, -cpu/event=0xc0,umask=0x10,name='INST_RETIRED.MACRO_FUSED'/, -cpu/event=0xc4,umask=0x00,name='BR_INST_RETIRED.ALL_BRANCHES'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x47,umask=0x03,cmask=0x03,period=1000003,name='MEMORY_ACTIVITY.STALLS_L1D_MISS'/, -cpu/event=0x47,umask=0x05,cmask=0x05,period=1000003,name='MEMORY_ACTIVITY.STALLS_L2_MISS'/, -cpu/event=0xb0,umask=0x09,cmask=0x01,period=1000003,name='ARITH.DIV_ACTIVE'/, -cpu/event=0xec,umask=0x02,period=2000003,name='CPU_CLK_UNHALTED.DISTRIBUTED'/, -cpu/event=0xd0,umask=0x21,cmask=0x00,period=1000003,name='MEM_INST_RETIRED.LOCK_LOADS'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x79,umask=0x04,cmask=0x01,period=2000003,name='IDQ.MITE_CYCLES_ANY'/, -cpu/event=0x79,umask=0x04,cmask=0x06,period=2000003,name='IDQ.MITE_CYCLES_OK'/, -cpu/event=0x79,umask=0x08,cmask=0x01,period=2000003,name='IDQ.DSB_CYCLES_ANY'/, -cpu/event=0x79,umask=0x08,cmask=0x06,period=2000003,name='IDQ.DSB_CYCLES_OK'/, -cpu/event=0xec,umask=0x02,period=2000003,name='CPU_CLK_UNHALTED.DISTRIBUTED'/, -cpu/event=0xb7,umask=0x02,period=2000003,name='EXE.AMX_BUSY'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x79,umask=0x08,cmask=0x00,period=2000003,name='IDQ.DSB_UOPS'/, -cpu/event=0x79,umask=0x04,period=100003,name='IDQ.MITE_UOPS'/, -cpu/event=0x79,umask=0x20,period=100003,name='IDQ.MS_UOPS'/, -cpu/event=0xa8,umask=0x01,cmask=0x00,period=2000003,name='LSD.UOPS'/, -cpu-cycles:k, -ref-cycles:k, -instructions:k; - -#OCR -cpu/event=0x2a,umask=0x01,offcore_rsp=0x104004477,name='OCR.READS_TO_CORE.LOCAL_DRAM'/, -cpu/event=0x2a,umask=0x01,offcore_rsp=0x730004477,name='OCR.READS_TO_CORE.REMOTE_DRAM'/, -cpu/event=0x2a,umask=0x01,offcore_rsp=0x90002380,name='OCR.HWPF_L3.REMOTE'/, -cpu/event=0x2a,umask=0x01,offcore_rsp=0x84002380,name='OCR.HWPF_L3.L3_MISS_LOCAL'/, -cpu/event=0x2a,umask=0x01,offcore_rsp=0x1030004477,name='OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM'/, -cpu/event=0x2a,umask=0x01,offcore_rsp=0x830004477,name='OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD'/; - -#C6 -cstate_core/c6-residency/; -cstate_pkg/c6-residency/; - -#UPI -upi/event=0x02,umask=0x0f,name='UNC_UPI_TxL_FLITS.ALL_DATA'/; - -#CHA (Cache) -cha/event=0x35,umask=0xc80ffe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_CRD'/, -cha/event=0x35,umask=0xc8177e01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE'/, -cha/event=0x36,umask=0xc8177e01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE'/; - -cha/event=0x35,umask=0xC816FE01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL'/, -cha/event=0x36,umask=0xc816fe01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL'/, -cha/event=0x35,umask=0xC896FE01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL'/, -cha/event=0x35,umask=0xC8977E01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE'/; - -cha/event=0x35,umask=0xccd7fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA'/, -cha/event=0x35,umask=0xc817fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD'/, -cha/event=0x35,umask=0xc897fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF'/, -cha/event=0x36,umask=0xC817fe01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD'/; - -#CHA (IO Bandwidth) -cha/event=0x35,umask=0xc8f3ff04,name='UNC_CHA_TOR_INSERTS.IO_PCIRDCUR'/, -cha/event=0x35,umask=0xCC43FF04,name='UNC_CHA_TOR_INSERTS.IO_ITOM'/, -cha/event=0x35,umask=0xCD43FF04,name='UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR'/, -cha/event=0x01,umask=0x00,name='UNC_CHA_CLOCKTICKS'/; - -#IMC (memory read/writes) -imc/event=0x05,umask=0xcf,name='UNC_M_CAS_COUNT.RD'/, -imc/event=0x05,umask=0xf0,name='UNC_M_CAS_COUNT.WR'/; - -#power -power/energy-pkg/, -power/energy-ram/; diff --git a/cmd/metrics/resources/events/x86_64/GenuineIntel/gnr.txt b/cmd/metrics/resources/events/x86_64/GenuineIntel/gnr.txt deleted file mode 100644 index 0bf2987a..00000000 --- a/cmd/metrics/resources/events/x86_64/GenuineIntel/gnr.txt +++ /dev/null @@ -1,231 +0,0 @@ -# GraniteRapids event list - -# cpu groups -cpu/event=0x51,umask=0x01,period=100003,name='L1D.REPLACEMENT'/, # 0,1,2,3 -cpu/event=0x24,umask=0xe4,period=200003,name='L2_RQSTS.ALL_CODE_RD'/, # 0,1,2,3 -cpu/event=0xd1,umask=0x01,period=1000003,name='MEM_LOAD_RETIRED.L1_HIT'/, # 0,1,2,3 -cpu/event=0x25,umask=0x1f,period=100003,name='L2_LINES_IN.ALL'/, # 0,1,2,3 -cpu/event=0xa6,umask=0x02,period=2000003,name='EXE_ACTIVITY.1_PORTS_UTIL'/, -cpu/event=0xec,umask=0x02,period=2000003,name='CPU_CLK_UNHALTED.DISTRIBUTED'/, -cpu/event=0xb7,umask=0x02,period=2000003,name='EXE.AMX_BUSY'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xd1,umask=0x10,period=100021,name='MEM_LOAD_RETIRED.L2_MISS'/, # 0,1,2,3 -cpu/event=0x24,umask=0x24,period=200003,name='L2_RQSTS.CODE_RD_MISS'/, # 0,1,2,3 -cpu/event=0x11,umask=0x0e,period=100003,name='ITLB_MISSES.WALK_COMPLETED'/, # 0,1,2,3 -cpu/event=0x47,umask=0x03,cmask=0x03,period=1000003,name='MEMORY_ACTIVITY.STALLS_L1D_MISS'/, # 0,1,2,3 -cpu/event=0xa6,umask=0x40,cmask=0x02,period=1000003,name='EXE_ACTIVITY.BOUND_ON_STORES'/, -cpu/event=0xa6,umask=0x21,cmask=0x05,period=2000003,name='EXE_ACTIVITY.BOUND_ON_LOADS'/, -cpu/event=0xad,umask=0x10,period=1000003,name='INT_MISC.UOP_DROPPING'/, -cpu/event=0xad,umask=0x40,period=1000003,name='INT_MISC.UNKNOWN_BRANCH_CYCLES'/, # [*] -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xe5,umask=0x03,period=1000003,name='MEM_UOP_RETIRED.ANY'/, -cpu/event=0xc0,umask=0x10,period=2000003,name='INST_RETIRED.MACRO_FUSED'/, -cpu/event=0xc4,umask=0x00,period=400009,name='BR_INST_RETIRED.ALL_BRANCHES'/, -cpu/event=0xc5,umask=0x00,period=400009,name='BR_MISP_RETIRED.ALL_BRANCHES'/, -cpu/event=0x12,umask=0x0e,period=100003,name='DTLB_LOAD_MISSES.WALK_COMPLETED'/, # 0,1,2,3 -cpu/event=0x12,umask=0x04,period=100003,name='DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M'/, # 0,1,2,3 -cpu/event=0x13,umask=0x0e,period=100003,name='DTLB_STORE_MISSES.WALK_COMPLETED'/, # 0,1,2,3 -cpu/event=0xd1,umask=0x02,period=200003,name='MEM_LOAD_RETIRED.L2_HIT'/, # 0,1,2,3 -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x00,umask=0x04,period=10000003,name='TOPDOWN.SLOTS'/, # Fixed counter 3 -cpu/event=0x00,umask=0x81,period=10000003,name='PERF_METRICS.BAD_SPECULATION'/, -cpu/event=0x00,umask=0x83,period=10000003,name='PERF_METRICS.BACKEND_BOUND'/, -cpu/event=0x00,umask=0x82,period=10000003,name='PERF_METRICS.FRONTEND_BOUND'/, -cpu/event=0x00,umask=0x80,period=10000003,name='PERF_METRICS.RETIRING'/, -cpu/event=0x00,umask=0x86,period=10000003,name='PERF_METRICS.FETCH_LATENCY'/, -cpu/event=0x00,umask=0x87,period=10000003,name='PERF_METRICS.MEMORY_BOUND'/, -cpu/event=0x00,umask=0x85,period=10000003,name='PERF_METRICS.BRANCH_MISPREDICTS'/, -cpu/event=0x00,umask=0x84,period=10000003,name='PERF_METRICS.HEAVY_OPERATIONS'/, -cpu/event=0x47,umask=0x09,cmask=0x09,period=1000003,name='MEMORY_ACTIVITY.STALLS_L3_MISS'/, # 0,1,2,3 -cpu/event=0x80,umask=0x04,period=500009,name='ICACHE_DATA.STALLS'/, # 0,1,2,3 -cpu/event=0x83,umask=0x04,period=200003,name='ICACHE_TAG.STALLS'/, # 0,1,2,3 -cpu/event=0xc2,umask=0x02,period=2000003,name='UOPS_RETIRED.SLOTS'/, -cpu/event=0xae,umask=0x01,period=2000003,name='UOPS_ISSUED.ANY'/; -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x47,umask=0x03,cmask=0x03,period=1000003,name='MEMORY_ACTIVITY.STALLS_L1D_MISS'/, # 0,1,2,3 -cpu/event=0x47,umask=0x05,cmask=0x05,period=1000003,name='MEMORY_ACTIVITY.STALLS_L2_MISS'/, # 0,1,2,3 -cpu/event=0x12,umask=0x10,cmask=0x01,period=100003,name='DTLB_LOAD_MISSES.WALK_ACTIVE'/, # 0,1,2,3 -cpu/event=0xa3,umask=0x10,cmask=0x10,period=1000003,name='CYCLE_ACTIVITY.CYCLES_MEM_ANY'/, -cpu/event=0xad,umask=0x80,period=500009,name='INT_MISC.CLEAR_RESTEER_CYCLES'/, -cpu/event=0xec,umask=0x02,period=2000003,name='CPU_CLK_UNHALTED.DISTRIBUTED'/, -cpu/event=0xd1,umask=0x08,period=200003,name='MEM_LOAD_RETIRED.L1_MISS'/, # 0,1,2,3 -cpu/event=0xc2,umask=0x04,period=2000003,name='UOPS_RETIRED.MS'/, # [*] -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xc2,umask=0x04,cmask=0x01,period=2000003,name='UOPS_RETIRED.MS:c1'/, # [*] -cpu/event=0xd0,umask=0x21,period=100007,name='MEM_INST_RETIRED.LOCK_LOADS'/, # 0,1,2,3 -cpu/event=0xd0,umask=0x82,period=1000003,name='MEM_INST_RETIRED.ALL_STORES'/, # 0,1,2,3 -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xc2,umask=0x04,cmask=0x01,period=2000003,name='UOPS_RETIRED.MS:c1:e1'/, # [*] -cpu/event=0x2a,umask=0x01,period=100003,offcore_rsp=0x8003C0001,name='OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD'/, # 0,1,2,3 -cpu/event=0x2b,umask=0x01,period=100003,offcore_rsp=0x10003C0002,name='OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM'/, # 0,1,2,3 -cpu/event=0x20,umask=0x04,cmask=0x01,period=1000003,name='OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO'/, # 0,1,2,3 -cpu/event=0xd1,umask=0x40,period=100007,name='MEM_LOAD_RETIRED.FB_HIT'/, # 0,1,2,3 -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xd2,umask=0x02,period=20011,name='MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD'/, # 0,1,2,3 -cpu/event=0xd2,umask=0x04,period=20011,name='MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD'/, # 0,1,2,3 -cpu/event=0x47,umask=0x02,cmask=0x02,period=1000003,name='MEMORY_ACTIVITY.CYCLES_L1D_MISS'/, # 0,1,2,3 -cpu/event=0xc5,umask=0x50,period=400009,name='BR_MISP_RETIRED.COND_NTAKEN_COST'/, -cpu/event=0xc5,umask=0x41,period=400009,name='BR_MISP_RETIRED.COND_TAKEN_COST'/, -cpu/event=0xc5,umask=0x42,period=400009,name='BR_MISP_RETIRED.INDIRECT_CALL_COST'/, -cpu/event=0xc5,umask=0xc0,period=100003,name='BR_MISP_RETIRED.INDIRECT_COST'/, -cpu/event=0xc5,umask=0x48,period=100007,name='BR_MISP_RETIRED.RET_COST'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xe7,umask=0x0c,period=1000003,name='INT_VEC_RETIRED.ADD_256'/, -cpu/event=0xe7,umask=0x20,period=1000003,name='INT_VEC_RETIRED.VNNI_256'/, -cpu/event=0xe7,umask=0x80,period=1000003,name='INT_VEC_RETIRED.MUL_256'/, -cpu/event=0x79,umask=0x08,period=2000003,name='IDQ.DSB_UOPS'/, # 0,1,2,3 -cpu/event=0x79,umask=0x04,period=2000003,name='IDQ.MITE_UOPS'/, # 0,1,2,3 -cpu/event=0x79,umask=0x20,period=1000003,name='IDQ.MS_UOPS'/, # 0,1,2,3 -cpu/event=0xa8,umask=0x01,period=2000003,name='LSD.UOPS'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x2a,umask=0x01,period=100003,offcore_rsp=0x1030004477,name='OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM'/, # 0,1,2,3 -cpu/event=0x2a,umask=0x01,period=100003,offcore_rsp=0x830004477,name='OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD'/, # 0,1,2,3 -cpu/event=0xb0,umask=0x09,cmask=0x01,period=1000003,name='ARITH.DIV_ACTIVE'/, -cpu/event=0xa2,umask=0x02,period=100003,name='RESOURCE_STALLS.SCOREBOARD'/, -cpu/event=0xec,umask=0x20,period=2000003,name='CPU_CLK_UNHALTED.C02'/, -cpu/event=0xa6,umask=0x80,period=1000003,name='EXE_ACTIVITY.EXE_BOUND_0_PORTS'/, -cpu/event=0xa6,umask=0xC,period=2000003,name='EXE_ACTIVITY.2_3_PORTS_UTIL'/, -cpu/event=0xa3,umask=0x04,cmask=0x04,period=1000003,name='CYCLE_ACTIVITY.STALLS_TOTAL'/, -cpu-cycles:k, -ref-cycles:k, -instructions:k; - -cpu/event=0x87,umask=0x01,period=500009,name='DECODE.LCP'/, # 0,1,2,3 -cpu/event=0x61,umask=0x02,period=100003,name='DSB2MITE_SWITCHES.PENALTY_CYCLES'/, # 0,1,2,3 -cpu/event=0x79,umask=0x04,cmask=0x01,period=2000003,name='IDQ.MITE_CYCLES_ANY'/, # 0,1,2,3 -cpu/event=0x79,umask=0x04,cmask=0x06,period=2000003,name='IDQ.MITE_CYCLES_OK'/, # 0,1,2,3 -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x79,umask=0x08,cmask=0x01,period=2000003,name='IDQ.DSB_CYCLES_ANY'/, # 0,1,2,3 -cpu/event=0x79,umask=0x08,cmask=0x06,period=2000003,name='IDQ.DSB_CYCLES_OK'/, # 0,1,2,3 -cpu/event=0x79,umask=0x20,cmask=0x01,period=2000003,name='IDQ.MS_CYCLES_ANY'/, # 0,1,2,3 -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xad,umask=0x01,cmask=0x01,period=500009,name='INT_MISC.CLEARS_COUNT'/, -cpu/event=0xc3,umask=0x01,cmask=0x01,period=100003,name='MACHINE_CLEARS.COUNT'/, -cpu/event=0xc3,umask=0x02,period=100003,name='MACHINE_CLEARS.MEMORY_ORDERING'/, -cpu/event=0xd0,umask=0x09,period=100003,name='MEM_INST_RETIRED.STLB_HIT_LOADS'/, # 0,1,2,3 -cpu/event=0x03,umask=0x82,period=100003,name='LD_BLOCKS.STORE_FORWARD'/, # 0,1,2,3 -cpu/event=0xd0,umask=0x81,period=1000003,name='MEM_INST_RETIRED.ALL_LOADS'/, # 0,1,2,3 -cpu/event=0xd0,umask=0x41,period=100003,name='MEM_INST_RETIRED.SPLIT_LOADS'/, # 0,1,2,3 -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x48,umask=0x01,period=1000003,name='L1D_PEND_MISS.PENDING'/, # 0,1,2,3 -cpu/event=0x43,umask=0xfd,period=1000003,name='MEM_LOAD_COMPLETED.L1_MISS_ANY'/, # 0,1,2,3 -cpu/event=0x48,umask=0x02,period=1000003,name='L1D_PEND_MISS.FB_FULL'/, # 0,1,2,3 -cpu/event=0xd2,umask=0x01,period=20011,name='MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS'/, # 0,1,2,3 -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xd1,umask=0x04,period=100021,name='MEM_LOAD_RETIRED.L3_HIT'/, # 0,1,2,3 -cpu/event=0x2d,umask=0x01,cmask=0x01,period=1000003,name='XQ.FULL_CYCLES'/, # 0,1,2,3 -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x48,umask=0x04,period=1000003,name='L1D_PEND_MISS.L2_STALLS'/, # 0,1,2,3 -cpu/event=0x44,umask=0x01,period=200003,name='MEM_STORE_RETIRED.L2_HIT'/, # 0,1,2,3 -cpu/event=0x2a,umask=0x01,period=100003,offcore_rsp=0x103b800002,name='OCR.DEMAND_RFO.L3_MISS'/, # 0,1,2,3 -cpu/event=0xd0,umask=0x42,period=100003,name='MEM_INST_RETIRED.SPLIT_STORES'/, # 0,1,2,3 -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x2a,umask=0x01,period=100003,offcore_rsp=0x10800,name='OCR.STREAMING_WR.ANY_RESPONSE'/, # 0,1,2,3 -cpu/event=0xd0,umask=0x0a,period=100003,name='MEM_INST_RETIRED.STLB_HIT_STORES'/, # 0,1,2,3 -cpu/event=0x13,umask=0x10,cmask=0x01,period=100003,name='DTLB_STORE_MISSES.WALK_ACTIVE'/, # 0,1,2,3 -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xb1,umask=0x10,period=2000003,name='UOPS_EXECUTED.X87'/, -cpu/event=0xb1,umask=0x01,period=2000003,name='UOPS_EXECUTED.THREAD'/, -cpu/event=0xc7,umask=0x03,period=1000003,name='FP_ARITH_INST_RETIRED.SCALAR'/, -cpu/event=0xcf,umask=0x03,period=100003,name='FP_ARITH_INST_RETIRED2.SCALAR'/, -cpu/event=0xc7,umask=0xfc,period=1000003,name='FP_ARITH_INST_RETIRED.VECTOR'/, -cpu/event=0xcf,umask=0x1c,period=100003,name='FP_ARITH_INST_RETIRED2.VECTOR'/, -cpu/event=0xe7,umask=0x03,period=1000003,name='INT_VEC_RETIRED.ADD_128'/, -cpu/event=0xe7,umask=0x10,period=1000003,name='INT_VEC_RETIRED.VNNI_128'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x2a,umask=0x01,period=100003,offcore_rsp=0x1030004477,name='OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM'/, # 0,1,2,3 -cpu/event=0x20,umask=0x08,cmask=0x01,period=1000003,name='OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD'/, # 0,1,2,3 -cpu/event=0x20,umask=0x08,cmask=0x04,period=1000003,name='OFFCORE_REQUESTS_OUTSTANDING.DATA_RD:c4'/, # 0,1,2,3 -cpu-cycles, -ref-cycles, -instructions; - -# upi groups -upi/event=0x02,umask=0x0f,name='UNC_UPI_TxL_FLITS.ALL_DATA'/; # 0,1,2,3 - -# cha groups -cha/event=0x35,umask=0xc80ffe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_CRD'/, # 0,1,2,3 -cha/event=0x35,umask=0xc8177e01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE'/, # 0,1,2,3 -cha/event=0x36,umask=0xc8177e01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE'/; # 0 - -cha/event=0x35,umask=0xc816fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL'/, # 0,1,2,3 -cha/event=0x36,umask=0xc816fe01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL'/, # 0 -cha/event=0x35,umask=0xc896fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL'/, # 0,1,2,3 -cha/event=0x35,umask=0xc8977e01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE'/; # 0,1,2,3 - -cha/event=0x35,umask=0xccd7fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA'/, # 0,1,2,3 -cha/event=0x35,umask=0xc817fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD'/, # 0,1,2,3 -cha/event=0x35,umask=0xc897fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF'/, # 0,1,2,3 -cha/event=0x36,umask=0xc817fe01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD'/; # 0 - -cha/event=0x35,umask=0xc8f3ff04,name='UNC_CHA_TOR_INSERTS.IO_PCIRDCUR'/, # 0,1,2,3 -cha/event=0x35,umask=0xcc43ff04,name='UNC_CHA_TOR_INSERTS.IO_ITOM'/, # 0,1,2,3 -cha/event=0x35,umask=0xcd43ff04,name='UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR'/, # 0,1,2,3 -cha/event=0x01,umask=0x00,name='UNC_CHA_CLOCKTICKS'/; # 0,1,2,3 - -# imc groups -imc/event=0x05,umask=0xcf,name='UNC_M_CAS_COUNT_SCH0.RD'/, # 0,1,2,3 -imc/event=0x06,umask=0xcf,name='UNC_M_CAS_COUNT_SCH1.RD'/, # 0,1,2,3 -imc/event=0x05,umask=0xf0,name='UNC_M_CAS_COUNT_SCH0.WR'/, # 0,1,2,3 -imc/event=0x06,umask=0xf0,name='UNC_M_CAS_COUNT_SCH1.WR'/; # 0,1,2,3 - -# cstate_core groups -cstate_core/c6-residency/; - -# cstate_pkg groups -cstate_pkg/c6-residency/; - -# power groups -power/energy-pkg/, -power/energy-ram/; diff --git a/cmd/metrics/resources/events/x86_64/GenuineIntel/gnr_nofixedtma.txt b/cmd/metrics/resources/events/x86_64/GenuineIntel/gnr_nofixedtma.txt deleted file mode 100644 index 4f8a758d..00000000 --- a/cmd/metrics/resources/events/x86_64/GenuineIntel/gnr_nofixedtma.txt +++ /dev/null @@ -1,212 +0,0 @@ -# GraniteRapids event list - -# cpu groups -cpu/event=0x51,umask=0x01,period=100003,name='L1D.REPLACEMENT'/, # 0,1,2,3 -cpu/event=0x24,umask=0xe4,period=200003,name='L2_RQSTS.ALL_CODE_RD'/, # 0,1,2,3 -cpu/event=0xd1,umask=0x01,period=1000003,name='MEM_LOAD_RETIRED.L1_HIT'/, # 0,1,2,3 -cpu/event=0x25,umask=0x1f,period=100003,name='L2_LINES_IN.ALL'/, # 0,1,2,3 -cpu/event=0xec,umask=0x02,period=2000003,name='CPU_CLK_UNHALTED.DISTRIBUTED'/, -cpu/event=0xb7,umask=0x02,period=2000003,name='EXE.AMX_BUSY'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xd1,umask=0x10,period=100021,name='MEM_LOAD_RETIRED.L2_MISS'/, # 0,1,2,3 -cpu/event=0x24,umask=0x24,period=200003,name='L2_RQSTS.CODE_RD_MISS'/, # 0,1,2,3 -cpu/event=0x11,umask=0x0e,period=100003,name='ITLB_MISSES.WALK_COMPLETED'/, # 0,1,2,3 -cpu/event=0x47,umask=0x03,cmask=0x03,period=1000003,name='MEMORY_ACTIVITY.STALLS_L1D_MISS'/, # 0,1,2,3 -cpu/event=0xa6,umask=0x40,cmask=0x02,period=1000003,name='EXE_ACTIVITY.BOUND_ON_STORES'/, -cpu/event=0xa6,umask=0x21,cmask=0x05,period=2000003,name='EXE_ACTIVITY.BOUND_ON_LOADS'/, -cpu/event=0xad,umask=0x10,period=1000003,name='INT_MISC.UOP_DROPPING'/, -cpu/event=0xad,umask=0x40,period=1000003,name='INT_MISC.UNKNOWN_BRANCH_CYCLES'/, # [*] -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xe5,umask=0x03,period=1000003,name='MEM_UOP_RETIRED.ANY'/, -cpu/event=0xc0,umask=0x10,period=2000003,name='INST_RETIRED.MACRO_FUSED'/, -cpu/event=0xc4,umask=0x00,period=400009,name='BR_INST_RETIRED.ALL_BRANCHES'/, -cpu/event=0xc5,umask=0x00,period=400009,name='BR_MISP_RETIRED.ALL_BRANCHES'/, -cpu/event=0x12,umask=0x0e,period=100003,name='DTLB_LOAD_MISSES.WALK_COMPLETED'/, # 0,1,2,3 -cpu/event=0x12,umask=0x04,period=100003,name='DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M'/, # 0,1,2,3 -cpu/event=0x13,umask=0x0e,period=100003,name='DTLB_STORE_MISSES.WALK_COMPLETED'/, # 0,1,2,3 -cpu/event=0xd1,umask=0x02,period=200003,name='MEM_LOAD_RETIRED.L2_HIT'/, # 0,1,2,3 -ref-cycles, -instructions; - -cpu/event=0x47,umask=0x09,cmask=0x09,period=1000003,name='MEMORY_ACTIVITY.STALLS_L3_MISS'/, # 0,1,2,3 -cpu/event=0x80,umask=0x04,period=500009,name='ICACHE_DATA.STALLS'/, # 0,1,2,3 -cpu/event=0x83,umask=0x04,period=200003,name='ICACHE_TAG.STALLS'/, # 0,1,2,3 -cpu/event=0xc2,umask=0x02,period=2000003,name='UOPS_RETIRED.SLOTS'/, -cpu/event=0xae,umask=0x01,period=2000003,name='UOPS_ISSUED.ANY'/; -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x47,umask=0x03,cmask=0x03,period=1000003,name='MEMORY_ACTIVITY.STALLS_L1D_MISS'/, # 0,1,2,3 -cpu/event=0x47,umask=0x05,cmask=0x05,period=1000003,name='MEMORY_ACTIVITY.STALLS_L2_MISS'/, # 0,1,2,3 -cpu/event=0x12,umask=0x10,cmask=0x01,period=100003,name='DTLB_LOAD_MISSES.WALK_ACTIVE'/, # 0,1,2,3 -cpu/event=0xa3,umask=0x10,cmask=0x10,period=1000003,name='CYCLE_ACTIVITY.CYCLES_MEM_ANY'/, -cpu/event=0xad,umask=0x80,period=500009,name='INT_MISC.CLEAR_RESTEER_CYCLES'/, -cpu/event=0xec,umask=0x02,period=2000003,name='CPU_CLK_UNHALTED.DISTRIBUTED'/, -cpu/event=0xd1,umask=0x08,period=200003,name='MEM_LOAD_RETIRED.L1_MISS'/, # 0,1,2,3 -cpu/event=0xc2,umask=0x04,period=2000003,name='UOPS_RETIRED.MS'/, # [*] -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xc2,umask=0x04,cmask=0x01,period=2000003,name='UOPS_RETIRED.MS:c1'/, # [*] -cpu/event=0xd0,umask=0x21,period=100007,name='MEM_INST_RETIRED.LOCK_LOADS'/, # 0,1,2,3 -cpu/event=0xd0,umask=0x82,period=1000003,name='MEM_INST_RETIRED.ALL_STORES'/, # 0,1,2,3 -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xc2,umask=0x04,cmask=0x01,period=2000003,name='UOPS_RETIRED.MS:c1:e1'/, # [*] -cpu/event=0x2a,umask=0x01,period=100003,offcore_rsp=0x8003C0001,name='OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD'/, # 0,1,2,3 -cpu/event=0x2b,umask=0x01,period=100003,offcore_rsp=0x10003C0002,name='OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM'/, # 0,1,2,3 -cpu/event=0x20,umask=0x04,cmask=0x01,period=1000003,name='OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO'/, # 0,1,2,3 -cpu/event=0xd1,umask=0x40,period=100007,name='MEM_LOAD_RETIRED.FB_HIT'/, # 0,1,2,3 -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xd2,umask=0x02,period=20011,name='MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD'/, # 0,1,2,3 -cpu/event=0xd2,umask=0x04,period=20011,name='MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD'/, # 0,1,2,3 -cpu/event=0x47,umask=0x02,cmask=0x02,period=1000003,name='MEMORY_ACTIVITY.CYCLES_L1D_MISS'/, # 0,1,2,3 -cpu/event=0xc5,umask=0x50,period=400009,name='BR_MISP_RETIRED.COND_NTAKEN_COST'/, -cpu/event=0xc5,umask=0x41,period=400009,name='BR_MISP_RETIRED.COND_TAKEN_COST'/, -cpu/event=0xc5,umask=0x42,period=400009,name='BR_MISP_RETIRED.INDIRECT_CALL_COST'/, -cpu/event=0xc5,umask=0xc0,period=100003,name='BR_MISP_RETIRED.INDIRECT_COST'/, -cpu/event=0xc5,umask=0x48,period=100007,name='BR_MISP_RETIRED.RET_COST'/, -ref-cycles, -instructions; - -cpu/event=0x79,umask=0x08,period=2000003,name='IDQ.DSB_UOPS'/, # 0,1,2,3 -cpu/event=0x79,umask=0x04,period=2000003,name='IDQ.MITE_UOPS'/, # 0,1,2,3 -cpu/event=0x79,umask=0x20,period=1000003,name='IDQ.MS_UOPS'/, # 0,1,2,3 -cpu/event=0xa8,umask=0x01,period=2000003,name='LSD.UOPS'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x2a,umask=0x01,period=100003,offcore_rsp=0x1030004477,name='OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM'/, # 0,1,2,3 -cpu/event=0x2a,umask=0x01,period=100003,offcore_rsp=0x830004477,name='OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD'/, # 0,1,2,3 -cpu/event=0xb0,umask=0x09,cmask=0x01,period=1000003,name='ARITH.DIV_ACTIVE'/, -cpu/event=0xa2,umask=0x02,period=100003,name='RESOURCE_STALLS.SCOREBOARD'/, -cpu/event=0xec,umask=0x20,period=2000003,name='CPU_CLK_UNHALTED.C02'/, -cpu-cycles:k, -ref-cycles:k, -instructions:k; - -cpu/event=0x87,umask=0x01,period=500009,name='DECODE.LCP'/, # 0,1,2,3 -cpu/event=0x61,umask=0x02,period=100003,name='DSB2MITE_SWITCHES.PENALTY_CYCLES'/, # 0,1,2,3 -cpu/event=0x79,umask=0x04,cmask=0x01,period=2000003,name='IDQ.MITE_CYCLES_ANY'/, # 0,1,2,3 -cpu/event=0x79,umask=0x04,cmask=0x06,period=2000003,name='IDQ.MITE_CYCLES_OK'/, # 0,1,2,3 -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x79,umask=0x08,cmask=0x01,period=2000003,name='IDQ.DSB_CYCLES_ANY'/, # 0,1,2,3 -cpu/event=0x79,umask=0x08,cmask=0x06,period=2000003,name='IDQ.DSB_CYCLES_OK'/, # 0,1,2,3 -cpu/event=0x79,umask=0x20,cmask=0x01,period=2000003,name='IDQ.MS_CYCLES_ANY'/, # 0,1,2,3 -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xad,umask=0x01,cmask=0x01,period=500009,name='INT_MISC.CLEARS_COUNT'/, -cpu/event=0xc3,umask=0x01,cmask=0x01,period=100003,name='MACHINE_CLEARS.COUNT'/, -cpu/event=0xc3,umask=0x02,period=100003,name='MACHINE_CLEARS.MEMORY_ORDERING'/, -cpu/event=0xd0,umask=0x09,period=100003,name='MEM_INST_RETIRED.STLB_HIT_LOADS'/, # 0,1,2,3 -cpu/event=0x03,umask=0x82,period=100003,name='LD_BLOCKS.STORE_FORWARD'/, # 0,1,2,3 -cpu/event=0xd0,umask=0x81,period=1000003,name='MEM_INST_RETIRED.ALL_LOADS'/, # 0,1,2,3 -cpu/event=0xd0,umask=0x41,period=100003,name='MEM_INST_RETIRED.SPLIT_LOADS'/, # 0,1,2,3 -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x48,umask=0x01,period=1000003,name='L1D_PEND_MISS.PENDING'/, # 0,1,2,3 -cpu/event=0x43,umask=0xfd,period=1000003,name='MEM_LOAD_COMPLETED.L1_MISS_ANY'/, # 0,1,2,3 -cpu/event=0x48,umask=0x02,period=1000003,name='L1D_PEND_MISS.FB_FULL'/, # 0,1,2,3 -cpu/event=0xd2,umask=0x01,period=20011,name='MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS'/, # 0,1,2,3 -cpu/event=0x9c,umask=0x01,period=1000003,name='IDQ_BUBBLES.CORE'/, -cpu/event=0x9c,umask=0x01,cmask=0x06,period=1000003,name='IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE'/; -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xa4,umask=0x01,period=10000003,name='TOPDOWN.SLOTS_P'/, -cpu/event=0xa4,umask=0x02,period=10000003,name='TOPDOWN.BACKEND_BOUND_SLOTS'/, -cpu/event=0xa4,umask=0x08,period=10000003,name='TOPDOWN.BR_MISPREDICT_SLOTS'/, # 0 -cpu/event=0xa4,umask=0x10,period=10000003,name='TOPDOWN.MEMORY_BOUND_SLOTS'/, -cpu/event=0xc2,umask=0x01,period=2000003,name='UOPS_RETIRED.HEAVY'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xd1,umask=0x04,period=100021,name='MEM_LOAD_RETIRED.L3_HIT'/, # 0,1,2,3 -cpu/event=0x2d,umask=0x01,cmask=0x01,period=1000003,name='XQ.FULL_CYCLES'/, # 0,1,2,3 -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x48,umask=0x04,period=1000003,name='L1D_PEND_MISS.L2_STALLS'/, # 0,1,2,3 -cpu/event=0x44,umask=0x01,period=200003,name='MEM_STORE_RETIRED.L2_HIT'/, # 0,1,2,3 -cpu/event=0x2a,umask=0x01,period=100003,offcore_rsp=0x103b800002,name='OCR.DEMAND_RFO.L3_MISS'/, # 0,1,2,3 -cpu/event=0xd0,umask=0x42,period=100003,name='MEM_INST_RETIRED.SPLIT_STORES'/, # 0,1,2,3 -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x2a,umask=0x01,period=100003,offcore_rsp=0x10800,name='OCR.STREAMING_WR.ANY_RESPONSE'/, # 0,1,2,3 -cpu/event=0xd0,umask=0x0a,period=100003,name='MEM_INST_RETIRED.STLB_HIT_STORES'/, # 0,1,2,3 -cpu/event=0x13,umask=0x10,cmask=0x01,period=100003,name='DTLB_STORE_MISSES.WALK_ACTIVE'/, # 0,1,2,3 -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x2a,umask=0x01,period=100003,offcore_rsp=0x1030004477,name='OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM'/, # 0,1,2,3 -cpu/event=0x20,umask=0x08,cmask=0x01,period=1000003,name='OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD'/, # 0,1,2,3 -cpu/event=0x20,umask=0x08,cmask=0x04,period=1000003,name='OFFCORE_REQUESTS_OUTSTANDING.DATA_RD:c4'/, # 0,1,2,3 -cpu-cycles, -ref-cycles, -instructions; - -# upi groups -upi/event=0x02,umask=0x0f,name='UNC_UPI_TxL_FLITS.ALL_DATA'/; # 0,1,2,3 - -# cha groups -cha/event=0x35,umask=0xc80ffe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_CRD'/, # 0,1,2,3 -cha/event=0x35,umask=0xc8177e01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE'/, # 0,1,2,3 -cha/event=0x36,umask=0xc8177e01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE'/; # 0 - -cha/event=0x35,umask=0xc816fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL'/, # 0,1,2,3 -cha/event=0x36,umask=0xc816fe01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL'/, # 0 -cha/event=0x35,umask=0xc896fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL'/, # 0,1,2,3 -cha/event=0x35,umask=0xc8977e01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE'/; # 0,1,2,3 - -cha/event=0x35,umask=0xccd7fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA'/, # 0,1,2,3 -cha/event=0x35,umask=0xc817fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD'/, # 0,1,2,3 -cha/event=0x35,umask=0xc897fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF'/, # 0,1,2,3 -cha/event=0x36,umask=0xc817fe01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD'/; # 0 - -cha/event=0x35,umask=0xc8f3ff04,name='UNC_CHA_TOR_INSERTS.IO_PCIRDCUR'/, # 0,1,2,3 -cha/event=0x35,umask=0xcc43ff04,name='UNC_CHA_TOR_INSERTS.IO_ITOM'/, # 0,1,2,3 -cha/event=0x35,umask=0xcd43ff04,name='UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR'/, # 0,1,2,3 -cha/event=0x01,umask=0x00,name='UNC_CHA_CLOCKTICKS'/; # 0,1,2,3 - -# imc groups -imc/event=0x05,umask=0xcf,name='UNC_M_CAS_COUNT_SCH0.RD'/, # 0,1,2,3 -imc/event=0x06,umask=0xcf,name='UNC_M_CAS_COUNT_SCH1.RD'/, # 0,1,2,3 -imc/event=0x05,umask=0xf0,name='UNC_M_CAS_COUNT_SCH0.WR'/, # 0,1,2,3 -imc/event=0x06,umask=0xf0,name='UNC_M_CAS_COUNT_SCH1.WR'/; # 0,1,2,3 - -# cstate_core groups -cstate_core/c6-residency/; - -# cstate_pkg groups -cstate_pkg/c6-residency/; - -# power groups -power/energy-pkg/, -power/energy-ram/; diff --git a/cmd/metrics/resources/events/x86_64/GenuineIntel/icx.txt b/cmd/metrics/resources/events/x86_64/GenuineIntel/icx.txt deleted file mode 100644 index a2d0684a..00000000 --- a/cmd/metrics/resources/events/x86_64/GenuineIntel/icx.txt +++ /dev/null @@ -1,210 +0,0 @@ -# Icelake event list - -cpu/event=0x51,umask=0x01,period=100003,name='L1D.REPLACEMENT'/, -cpu/event=0xd1,umask=0x01,period=1000003,name='MEM_LOAD_RETIRED.L1_HIT'/, -cpu/event=0x24,umask=0xe4,period=200003,name='L2_RQSTS.ALL_CODE_RD'/, -cpu/event=0xe6,umask=0x01,period=100003,name='BACLEARS.ANY'/, -cpu/event=0x0d,umask=0x80,period=500009,name='INT_MISC.CLEAR_RESTEER_CYCLES'/, -cpu/event=0xc3,umask=0x01,cmask=0x01,edge=0x01,period=100003,name='MACHINE_CLEARS.COUNT'/, -cpu/event=0xc5,umask=0x00,period=50021,name='BR_MISP_RETIRED.ALL_BRANCHES'/, -cpu/event=0xb1,umask=0x01,cmask=0x03,period=2000003,name='UOPS_EXECUTED.CYCLES_GE_3'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xc4,umask=0x00,period=100003,name='BR_INST_RETIRED.ALL_BRANCHES'/, -cpu/event=0xc5,umask=0x00,period=100003,name='BR_MISP_RETIRED.ALL_BRANCHES'/, -cpu/event=0xf1,umask=0x1f,period=100003,name='L2_LINES_IN.ALL'/, # 0,1,2,3 -cpu/event=0xd1,umask=0x10,period=100021,name='MEM_LOAD_RETIRED.L2_MISS'/, -cpu/event=0x24,umask=0x24,period=200003,name='L2_RQSTS.CODE_RD_MISS'/, # 0,1,2,3 -cpu-cycles, -ref-cycles, -instructions; - -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xb7,umask=0x01,offcore_rsp=0x104000477,name='OCR.READS_TO_CORE.LOCAL_DRAM'/, -cpu/event=0xb7,umask=0x01,offcore_rsp=0x84002380,name='OCR.HWPF_L3.L3_MISS_LOCAL'/, -cpu/event=0x85,umask=0x0e,period=100003,name='ITLB_MISSES.WALK_COMPLETED'/, -cpu/event=0x08,umask=0x0e,period=100003,name='DTLB_LOAD_MISSES.WALK_COMPLETED'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xb7,umask=0x01,offcore_rsp=0x730000477,name='OCR.READS_TO_CORE.REMOTE_DRAM'/, -cpu/event=0xb7,umask=0x01,offcore_rsp=0x90002380,name='OCR.HWPF_L3.REMOTE'/, -cpu/event=0x08,umask=0x04,period=100003,name='DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M'/, -cpu/event=0x49,umask=0x0e,period=100003,name='DTLB_STORE_MISSES.WALK_COMPLETED'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xb7,umask=0x01,offcore_rsp=0x1030000477,name='OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM'/, -cpu/event=0xb7,umask=0x01,offcore_rsp=0x830000477,name='OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD'/, -cpu/event=0x80,umask=0x4,period=500009,name='ICACHE_16B.IFDATA_STALL'/, -cpu/event=0x83,umask=0x04,period=200003,name='ICACHE_64B.IFTAG_STALL'/, -cpu-cycles, -ref-cycles, -instructions; - -#TMA related -cpu/event=0x00,umask=0x04,period=10000003,name='TOPDOWN.SLOTS'/, -cpu/event=0x00,umask=0x81,period=10000003,name='PERF_METRICS.BAD_SPECULATION'/, -cpu/event=0x00,umask=0x83,period=10000003,name='PERF_METRICS.BACKEND_BOUND'/, -cpu/event=0x00,umask=0x82,period=10000003,name='PERF_METRICS.FRONTEND_BOUND'/, -cpu/event=0x00,umask=0x80,period=10000003,name='PERF_METRICS.RETIRING'/, -cpu/event=0x9c,umask=0x01,cmask=0x05,period=1000003,name='IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE'/, -cpu/event=0x0d,umask=0x10,period=1000003,name='INT_MISC.UOP_DROPPING'/, -cpu/event=0x0d,umask=0x01,cmask=0x01,edge=0x01,period=500009,name='INT_MISC.RECOVERY_CYCLES:c1:e1'/, -cpu-cycles, -ref-cycles, -instructions; - -# more TMA -cpu/event=0x79,umask=0x30,period=100003,name='IDQ.MS_SWITCHES'/, # 0,1,2,3 -cpu/event=0x87,umask=0x01,period=500009,name='DECODE.LCP'/, # 0,1,2,3 -cpu/event=0xab,umask=0x02,period=100003,name='DSB2MITE_SWITCHES.PENALTY_CYCLES'/, # 0,1,2,3 -cpu/event=0xc2,umask=0x02,period=2000003,name='UOPS_RETIRED.SLOTS'/, -cpu/event=0xd0,umask=0x83,period=1000003,name='MEM_INST_RETIRED.ANY'/, # 0,1,2,3 -cpu-cycles, -ref-cycles, -instructions; - - -#TMA AVX512 related -cpu/event=0xc7,umask=0x80,cmask=0x00,period=100003,name='FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE'/, -cpu/event=0xc7,umask=0x40,cmask=0x00,period=100003,name='FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE'/, -cpu/event=0xc7,umask=0x20,cmask=0x00,period=100003,name='FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE'/, -cpu/event=0xc7,umask=0x10,cmask=0x00,period=100003,name='FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE'/, -cpu/event=0xc7,umask=0x08,cmask=0x00,period=100003,name='FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE'/, -cpu/event=0xc7,umask=0x04,cmask=0x00,period=100003,name='FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x79,umask=0x04,cmask=0x01,period=2000003,name='IDQ.MITE_CYCLES_ANY'/, -cpu/event=0x79,umask=0x04,cmask=0x05,period=2000003,name='IDQ.MITE_CYCLES_OK'/, -cpu/event=0x79,umask=0x08,cmask=0x01,period=2000003,name='IDQ.DSB_CYCLES_ANY'/, -cpu/event=0x79,umask=0x08,cmask=0x05,period=2000003,name='IDQ.DSB_CYCLES_OK'/, -cpu/event=0xec,umask=0x02,period=2000003,name='CPU_CLK_UNHALTED.DISTRIBUTED'/, -cpu/event=0xa6,umask=0x80,period=2000003,name='EXE_ACTIVITY.3_PORTS_UTIL:u0x80'/, -cpu/event=0xa2,umask=0x02,period=2000003,name='RESOURCE_STALLS.SCOREBOARD'/, -cpu/event=0x14,umask=0x09,cmask=0x01,period=1000003,name='ARITH.DIVIDER_ACTIVE'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xa3,umask=0x0C,cmask=0x0C,period=1000003,name='CYCLE_ACTIVITY.STALLS_L1D_MISS'/, -cpu/event=0x08,umask=0x20,cmask=0x01,period=100003,name='DTLB_LOAD_MISSES.STLB_HIT:c1'/, -cpu/event=0x08,umask=0x10,cmask=0x01,period=100003,name='DTLB_LOAD_MISSES.WALK_ACTIVE'/, -cpu/event=0xa3,umask=0x14,cmask=0x14,period=2000003,name='CYCLE_ACTIVITY.STALLS_MEM_ANY'/, -cpu/event=0xa6,umask=0x40,cmask=0x02,period=1000003,name='EXE_ACTIVITY.BOUND_ON_STORES'/, -cpu/event=0xa3,umask=0x04,cmask=0x04,period=1000003,name='CYCLE_ACTIVITY.STALLS_TOTAL'/, -cpu/event=0xa6,umask=0x02,period=2000003,name='EXE_ACTIVITY.1_PORTS_UTIL'/, -cpu/event=0xa6,umask=0x04,period=2000003,name='EXE_ACTIVITY.2_PORTS_UTIL'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xd0,umask=0x21,cmask=0x00,period=100007,name='MEM_INST_RETIRED.LOCK_LOADS'/, -cpu/event=0x24,umask=0xe2,cmask=0x00,period=200003,name='L2_RQSTS.ALL_RFO'/, -cpu/event=0xd0,umask=0x82,cmask=0x00,period=1000003,name='MEM_INST_RETIRED.ALL_STORES'/, -cpu/event=0x24,umask=0xc2,cmask=0x00,period=200003,name='L2_RQSTS.RFO_HIT'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xd1,umask=0x02,period=200003,name='MEM_LOAD_RETIRED.L2_HIT'/, -cpu/event=0xd1,umask=0x40,period=100007,name='MEM_LOAD_RETIRED.FB_HIT'/, -cpu/event=0xd1,umask=0x08,period=200003,name='MEM_LOAD_RETIRED.L1_MISS'/, -cpu/event=0x48,umask=0x02,period=1000003,name='L1D_PEND_MISS.FB_FULL_PERIODS'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xa3,umask=0x08,cmask=0x08,period=1000003,name='CYCLE_ACTIVITY.CYCLES_L1D_MISS'/, -cpu/event=0xa3,umask=0x05,cmask=0x05,period=1000003,name='CYCLE_ACTIVITY.STALLS_L2_MISS'/, -cpu/event=0x60,umask=0x08,cmask=0x01,period=1000003,name='OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD'/, -cpu/event=0x60,umask=0x08,cmask=0x04,period=1000003,name='OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xb7,umask=0x01,offcore_rsp=0x10003C0001,name='OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM'/, -cpu/event=0xb7,umask=0x01,offcore_rsp=0x8003C0001,name='OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD'/, -cpu/event=0xd2,umask=0x02,period=1000003,name='MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT'/, -cpu/event=0xd2,umask=0x04,period=1000003,name='MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xd3,umask=0x02,cmask=0x00,period=100007,name='MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM'/, -cpu/event=0xd3,umask=0x01,cmask=0x00,period=100007,name='MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM'/, -cpu/event=0xd3,umask=0x08,cmask=0x00,period=100007,name='MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD'/, -cpu/event=0xd3,umask=0x04,cmask=0x00,period=100007,name='MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xd1,umask=0x80,cmask=0x00,period=100003,name='MEM_LOAD_RETIRED.LOCAL_PMM'/, -cpu/event=0xd3,umask=0x10,cmask=0x00,period=100007,name='MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM'/, -cpu/event=0xa3,umask=0x06,cmask=0x06,period=1000003,name='CYCLE_ACTIVITY.STALLS_L3_MISS'/, -cpu/event=0xa3,umask=0x0c,cmask=0x0c,period=1000003,name='CYCLE_ACTIVITY.STALLS_L1D_MISS'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x79,umask=0x04,period=100003,name='IDQ.MITE_UOPS'/, -cpu/event=0x79,umask=0x30,period=100003,name='IDQ.MS_UOPS'/, -cpu/event=0x56,umask=0x01,period=100003,name='UOPS_DECODED.DEC0'/, -cpu/event=0x56,umask=0x01,cmask=0x01,period=100003,name='UOPS_DECODED.DEC0:c1'/, -cpu/event=0x0e,umask=0x01,period=2000003,name='UOPS_ISSUED.ANY'/, -cpu/event=0xa3,umask=0x10,cmask=0x10,period=1000003,name='CYCLE_ACTIVITY.CYCLES_MEM_ANY'/, -cpu/event=0x3c,umask=0x02,period=25003,name='CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE'/, -cpu/event=0x3c,umask=0x08,period=2000003,name='CPU_CLK_UNHALTED.REF_DISTRIBUTED'/, -cpu-cycles:k, -ref-cycles:k, -instructions:k; - -cpu/event=0x60,umask=0x04,cmask=0x01,period=1000003,name='OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO'/, -cpu/event=0xb7,umask=0x01,cmask=0x00,offcore_rsp=0x10003C0002,name='OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM'/, -cpu/event=0x79,umask=0x08,cmask=0x00,period=2000003,name='IDQ.DSB_UOPS'/, -cpu/event=0xa8,umask=0x01,cmask=0x00,period=2000003,name='LSD.UOPS'/, -cpu-cycles, -ref-cycles, -instructions; - -#C6 -cstate_core/c6-residency/; -cstate_pkg/c6-residency/; - -# UPI related -upi/event=0x2,umask=0xf,name='UNC_UPI_TxL_FLITS.ALL_DATA'/; - -# CHA events -cha/event=0x00,umask=0x00,name='UNC_CHA_CLOCKTICKS'/; - -cha/event=0x35,umask=0xC8177E01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE'/, -cha/event=0x35,umask=0xC816FE01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL'/, -cha/event=0x35,umask=0xC896FE01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL'/, -cha/event=0x35,umask=0xC8977E01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE'/; - -cha/event=0x36,umask=0xc8177e01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE'/; -cha/event=0x35,umask=0xc88ffe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF'/, -cha/event=0x35,umask=0xc80ffe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_CRD'/, -cha/event=0x36,umask=0xC816FE01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL'/; - -cha/event=0x35,umask=0xccd7fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDRD'/, -cha/event=0x35,umask=0xc817fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD'/, -cha/event=0x35,umask=0xc897fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF'/, -cha/event=0x36,umask=0xC817FE01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD'/; - -#memory read/writes -imc/event=0x04,umask=0x0f,name='UNC_M_CAS_COUNT.RD'/, -imc/event=0x04,umask=0x30,name='UNC_M_CAS_COUNT.WR'/; - -#power related -power/energy-pkg/, -power/energy-ram/; diff --git a/cmd/metrics/resources/events/x86_64/GenuineIntel/icx_nofixedtma.txt b/cmd/metrics/resources/events/x86_64/GenuineIntel/icx_nofixedtma.txt deleted file mode 100644 index 041e9b73..00000000 --- a/cmd/metrics/resources/events/x86_64/GenuineIntel/icx_nofixedtma.txt +++ /dev/null @@ -1,145 +0,0 @@ -# Icelake event list for platforms that don't have support for the fixed counter TMA events, e.g., some AWS -# VMs. -# Note that there are no more than 10 events per group. On these same platforms, the cpu-cycles fixed -# counter is not supported so a general purpose counter will be used. - -cpu/event=0x51,umask=0x01,period=100003,name='L1D.REPLACEMENT'/, -cpu/event=0xd1,umask=0x01,period=1000003,name='MEM_LOAD_RETIRED.L1_HIT'/, -cpu/event=0x24,umask=0xe4,period=200003,name='L2_RQSTS.ALL_CODE_RD'/, -cpu/event=0xc3,umask=0x01,cmask=0x01,edge=0x01,period=100003,name='MACHINE_CLEARS.COUNT'/, -cpu/event=0xc5,umask=0x00,period=50021,name='BR_MISP_RETIRED.ALL_BRANCHES'/, -cpu/event=0xf1,umask=0x1f,period=100003,name='L2_LINES_IN.ALL'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xc4,umask=0x00,period=100003,name='BR_INST_RETIRED.ALL_BRANCHES'/, -cpu/event=0xc5,umask=0x00,period=100003,name='BR_MISP_RETIRED.ALL_BRANCHES'/, -cpu/event=0xd1,umask=0x10,period=100021,name='MEM_LOAD_RETIRED.L2_MISS'/, -cpu/event=0x79,umask=0x08,cmask=0x00,period=2000003,name='IDQ.DSB_UOPS'/, -cpu/event=0xa8,umask=0x01,cmask=0x00,period=2000003,name='LSD.UOPS'/, -cpu/event=0x48,umask=0x02,period=1000003,name='L1D_PEND_MISS.FB_FULL_PERIODS'/, -cpu-cycles, -ref-cycles, -instructions; - -# events for TMA metrics without fixed counter support (group 1) -cpu/event=0x9c,umask=0x01,name='IDQ_UOPS_NOT_DELIVERED.CORE'/, -cpu/event=0xa4,umask=0x01,name='TOPDOWN.SLOTS_P'/, -cpu/event=0x80,umask=0x04,name='ICACHE_DATA.STALLS'/, -cpu/event=0x83,umask=0x04,name='ICACHE_TAG.STALLS'/, -cpu/event=0x79,umask=0x30,name='IDQ.MS_SWITCHES'/, -cpu/event=0x87,umask=0x01,name='DECODE.LCP'/, -cpu/event=0x0d,umask=0x10,period=1000003,name='INT_MISC.UOP_DROPPING'/, -cpu-cycles, -ref-cycles, -instructions; - -# events for TMA metrics without fixed counter support (group 2) -cpu/event=0xab,umask=0x02,name='DSB2MITE_SWITCHES.PENALTY_CYCLES'/, -cpu/event=0xa4,umask=0x02,name='TOPDOWN.BACKEND_BOUND_SLOTS'/, -cpu/event=0x0D,umask=0x01,name='INT_MISC.CLEARS_COUNT'/, -cpu/event=0xc2,umask=0x02,name='UOPS_RETIRED.SLOTS'/, -cpu/event=0xd0,umask=0x83,name='MEM_INST_RETIRED.ANY'/, -cpu/event=0xc4,umask=0x00,name='BR_INST_RETIRED.ALL_BRANCHES'/, -cpu/event=0x9c,umask=0x01,cmask=0x05,period=1000003,name='IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x24,umask=0x24,period=200003,name='L2_RQSTS.CODE_RD_MISS'/, -cpu/event=0xa3,umask=0x0C,cmask=0x0C,period=1000003,name='CYCLE_ACTIVITY.STALLS_L1D_MISS'/, -cpu/event=0xa3,umask=0x14,cmask=0x14,period=2000003,name='CYCLE_ACTIVITY.STALLS_MEM_ANY'/, -cpu/event=0xa6,umask=0x40,cmask=0x02,period=1000003,name='EXE_ACTIVITY.BOUND_ON_STORES'/, -cpu/event=0xa3,umask=0x04,cmask=0x04,period=1000003,name='CYCLE_ACTIVITY.STALLS_TOTAL'/, -cpu/event=0xa6,umask=0x02,period=2000003,name='EXE_ACTIVITY.1_PORTS_UTIL'/, -cpu/event=0xa6,umask=0x04,period=2000003,name='EXE_ACTIVITY.2_PORTS_UTIL'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xd0,umask=0x21,cmask=0x00,period=100007,name='MEM_INST_RETIRED.LOCK_LOADS'/, -cpu/event=0xd1,umask=0x02,period=200003,name='MEM_LOAD_RETIRED.L2_HIT'/, -cpu/event=0xd1,umask=0x40,period=100007,name='MEM_LOAD_RETIRED.FB_HIT'/, -cpu/event=0xd1,umask=0x08,period=200003,name='MEM_LOAD_RETIRED.L1_MISS'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xa3,umask=0x05,cmask=0x05,period=1000003,name='CYCLE_ACTIVITY.STALLS_L2_MISS'/, -cpu/event=0xa3,umask=0x06,cmask=0x06,period=1000003,name='CYCLE_ACTIVITY.STALLS_L3_MISS'/, -cpu/event=0xa3,umask=0x0c,cmask=0x0c,period=1000003,name='CYCLE_ACTIVITY.STALLS_L1D_MISS'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x79,umask=0x04,cmask=0x01,period=2000003,name='IDQ.MITE_CYCLES_ANY'/, -cpu/event=0x79,umask=0x04,cmask=0x05,period=2000003,name='IDQ.MITE_CYCLES_OK'/, -cpu/event=0x79,umask=0x08,cmask=0x01,period=2000003,name='IDQ.DSB_CYCLES_ANY'/, -cpu/event=0x79,umask=0x08,cmask=0x05,period=2000003,name='IDQ.DSB_CYCLES_OK'/, -cpu/event=0xec,umask=0x02,period=2000003,name='CPU_CLK_UNHALTED.DISTRIBUTED'/, -cpu/event=0x14,umask=0x09,cmask=0x01,period=1000003,name='ARITH.DIVIDER_ACTIVE'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x79,umask=0x04,period=100003,name='IDQ.MITE_UOPS'/, -cpu/event=0x79,umask=0x30,period=100003,name='IDQ.MS_UOPS'/, -cpu/event=0x56,umask=0x01,period=100003,name='UOPS_DECODED.DEC0'/, -cpu/event=0x56,umask=0x01,cmask=0x01,period=100003,name='UOPS_DECODED.DEC0:c1'/, -cpu/event=0x0e,umask=0x01,period=2000003,name='UOPS_ISSUED.ANY'/, -cpu-cycles:k, -ref-cycles:k, -instructions:k; - -# OCR -cpu/event=0xb7,umask=0x01,offcore_rsp=0x104000477,name='OCR.READS_TO_CORE.LOCAL_DRAM'/, -cpu/event=0xb7,umask=0x01,offcore_rsp=0x84002380,name='OCR.HWPF_L3.L3_MISS_LOCAL'/, -cpu/event=0x85,umask=0x0e,period=100003,name='ITLB_MISSES.WALK_COMPLETED'/, -cpu/event=0x08,umask=0x0e,period=100003,name='DTLB_LOAD_MISSES.WALK_COMPLETED'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xb7,umask=0x01,offcore_rsp=0x1030000477,name='OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM'/, -cpu/event=0xb7,umask=0x01,offcore_rsp=0x830000477,name='OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD'/, -cpu/event=0xb7,umask=0x01,offcore_rsp=0x730000477,name='OCR.READS_TO_CORE.REMOTE_DRAM'/, -cpu/event=0xb7,umask=0x01,offcore_rsp=0x90002380,name='OCR.HWPF_L3.REMOTE'/, -cpu/event=0x08,umask=0x04,period=100003,name='DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M'/, -cpu/event=0x49,umask=0x0e,period=100003,name='DTLB_STORE_MISSES.WALK_COMPLETED'/, -cpu-cycles, -ref-cycles, -instructions; - -# C6 -cstate_core/c6-residency/; -cstate_pkg/c6-residency/; - -# UPI -upi/event=0x2,umask=0xf,name='UNC_UPI_TxL_FLITS.ALL_DATA'/; - -# CHA -cha/event=0x00,umask=0x00,name='UNC_CHA_CLOCKTICKS'/; - -cha/event=0x35,umask=0xC8177E01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE'/, -cha/event=0x35,umask=0xC816FE01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL'/, -cha/event=0x35,umask=0xC896FE01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL'/, -cha/event=0x35,umask=0xC8977E01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE'/; - -cha/event=0x36,umask=0xc8177e01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE'/; -cha/event=0x35,umask=0xc88ffe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF'/, -cha/event=0x35,umask=0xc80ffe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_CRD'/, -cha/event=0x36,umask=0xC816FE01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL'/; - -cha/event=0x35,umask=0xccd7fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDRD'/, -cha/event=0x35,umask=0xc817fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD'/, -cha/event=0x35,umask=0xc897fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF'/, -cha/event=0x36,umask=0xC817FE01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD'/; - -# memory read/writes -imc/event=0x04,umask=0x0f,name='UNC_M_CAS_COUNT.RD'/, -imc/event=0x04,umask=0x30,name='UNC_M_CAS_COUNT.WR'/; - -# power -power/energy-pkg/, -power/energy-ram/; diff --git a/cmd/metrics/resources/events/x86_64/GenuineIntel/spr.txt b/cmd/metrics/resources/events/x86_64/GenuineIntel/spr.txt deleted file mode 100644 index e85e21ac..00000000 --- a/cmd/metrics/resources/events/x86_64/GenuineIntel/spr.txt +++ /dev/null @@ -1,201 +0,0 @@ -# SapphireRapids event list - -cpu/event=0x51,umask=0x01,period=100003,name='L1D.REPLACEMENT'/, -cpu/event=0x24,umask=0xe4,period=200003,name='L2_RQSTS.ALL_CODE_RD'/, -cpu/event=0xd1,umask=0x01,period=1000003,name='MEM_LOAD_RETIRED.L1_HIT'/, -cpu/event=0x25,umask=0x1f,period=100003,name='L2_LINES_IN.ALL'/, -cpu/event=0xa6,umask=0x02,period=2000003,name='EXE_ACTIVITY.1_PORTS_UTIL'/, -cpu/event=0xa6,umask=0x04,period=2000003,name='EXE_ACTIVITY.2_PORTS_UTIL'/, -cpu/event=0xa6,umask=0x80,period=2000003,name='EXE_ACTIVITY.3_PORTS_UTIL:u0x80'/, -cpu/event=0xa6,umask=0xc,period=2000003,name='EXE_ACTIVITY.2_PORTS_UTIL:u0xc'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xd1,umask=0x10,period=100021,name='MEM_LOAD_RETIRED.L2_MISS'/, -cpu/event=0x24,umask=0x24,period=200003,name='L2_RQSTS.CODE_RD_MISS'/, -cpu/event=0x11,umask=0x0e,period=100003,name='ITLB_MISSES.WALK_COMPLETED'/, -cpu/event=0x47,umask=0x03,cmask=0x03,period=1000003,name='MEMORY_ACTIVITY.STALLS_L1D_MISS'/, -cpu/event=0xa6,umask=0x40,cmask=0x02,period=1000003,name='EXE_ACTIVITY.BOUND_ON_STORES'/, -cpu/event=0xa6,umask=0x21,cmask=0x05,period=2000003,name='EXE_ACTIVITY.BOUND_ON_LOADS'/, -cpu/event=0xad,umask=0x10,period=1000003,name='INT_MISC.UOP_DROPPING'/, -cpu/event=0xad,umask=0x40,period=1000003,name='INT_MISC.UNKNOWN_BRANCH_CYCLES'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x12,umask=0x0e,period=100003,name='DTLB_LOAD_MISSES.WALK_COMPLETED'/, -cpu/event=0x12,umask=0x04,period=100003,name='DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M'/, -cpu/event=0x13,umask=0x0e,period=100003,name='DTLB_STORE_MISSES.WALK_COMPLETED'/, -cpu/event=0xd1,umask=0x02,period=200003,name='MEM_LOAD_RETIRED.L2_HIT'/, -cpu/event=0x3c,umask=0x02,period=25003,name='CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE'/, -cpu/event=0x3c,umask=0x08,period=2000003,name='CPU_CLK_UNHALTED.REF_DISTRIBUTED'/, -cpu/event=0xa2,umask=0x02,period=2000003,name='RESOURCE_STALLS.SCOREBOARD'/, -cpu/event=0xa3,umask=0x04,cmask=0x04,period=1000003,name='CYCLE_ACTIVITY.STALLS_TOTAL'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x00,umask=0x04,period=10000003,name='TOPDOWN.SLOTS'/, -cpu/event=0x00,umask=0x81,period=10000003,name='PERF_METRICS.BAD_SPECULATION'/, -cpu/event=0x00,umask=0x83,period=10000003,name='PERF_METRICS.BACKEND_BOUND'/, -cpu/event=0x00,umask=0x82,period=10000003,name='PERF_METRICS.FRONTEND_BOUND'/, -cpu/event=0x00,umask=0x80,period=10000003,name='PERF_METRICS.RETIRING'/, -cpu/event=0x00,umask=0x86,period=10000003,name='PERF_METRICS.FETCH_LATENCY'/, -cpu/event=0x00,umask=0x87,period=10000003,name='PERF_METRICS.MEMORY_BOUND'/, -cpu/event=0x00,umask=0x85,period=10000003,name='PERF_METRICS.BRANCH_MISPREDICTS'/, -cpu/event=0x00,umask=0x84,period=10000003,name='PERF_METRICS.HEAVY_OPERATIONS'/, -cpu/event=0x47,umask=0x09,cmask=0x09,period=1000003,name='MEMORY_ACTIVITY.STALLS_L3_MISS'/, -cpu/event=0x80,umask=0x04,period=500009,name='ICACHE_DATA.STALLS'/, -cpu/event=0x83,umask=0x04,period=200003,name='ICACHE_TAG.STALLS'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xc2,umask=0x02,period=2000003,name='UOPS_RETIRED.SLOTS'/, -cpu/event=0xae,umask=0x01,period=2000003,name='UOPS_ISSUED.ANY'/, -cpu/event=0x87,umask=0x01,period=500009,name='DECODE.LCP'/, # 0,1,2,3 -cpu/event=0x61,umask=0x02,period=100003,name='DSB2MITE_SWITCHES.PENALTY_CYCLES'/, # 0,1,2,3 -cpu/event=0xe5,umask=0x03,period=1000003,name='MEM_UOP_RETIRED.ANY'/, -cpu/event=0xc0,umask=0x10,period=2000003,name='INST_RETIRED.MACRO_FUSED'/, -cpu/event=0xc2,umask=0x04,cmask=0x01,period=2000003,name='UOPS_RETIRED.MS:c1:e1'/, # [*]cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xc4,umask=0x00,period=100003,name='BR_INST_RETIRED.ALL_BRANCHES'/, -cpu/event=0xc5,umask=0x00,period=100003,name='BR_MISP_RETIRED.ALL_BRANCHES'/, -cpu/event=0xcf,umask=0x10,cmask=0x00,period=100003,name='FP_ARITH_INST_RETIRED2.512B_PACKED_HALF'/, -cpu/event=0xcf,umask=0x08,cmask=0x00,period=100003,name='FP_ARITH_INST_RETIRED2.256B_PACKED_HALF'/, -cpu/event=0xc7,umask=0x80,cmask=0x00,period=100003,name='FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE'/, -cpu/event=0xc7,umask=0x40,cmask=0x00,period=100003,name='FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE'/, -cpu/event=0xc7,umask=0x20,cmask=0x00,period=100003,name='FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE'/, -cpu/event=0xc7,umask=0x10,cmask=0x00,period=100003,name='FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x47,umask=0x03,cmask=0x03,period=1000003,name='MEMORY_ACTIVITY.STALLS_L1D_MISS'/, -cpu/event=0x47,umask=0x05,cmask=0x05,period=1000003,name='MEMORY_ACTIVITY.STALLS_L2_MISS'/, -cpu/event=0x12,umask=0x20,cmask=0x01,period=100003,name='DTLB_LOAD_MISSES.STLB_HIT:c1'/, -cpu/event=0x12,umask=0x10,cmask=0x01,period=100003,name='DTLB_LOAD_MISSES.WALK_ACTIVE'/, -cpu/event=0xa3,umask=0x10,cmask=0x10,period=1000003,name='CYCLE_ACTIVITY.CYCLES_MEM_ANY'/, -cpu/event=0xb0,umask=0x09,cmask=0x01,period=1000003,name='ARITH.DIV_ACTIVE'/, -cpu/event=0xad,umask=0x80,period=500009,name='INT_MISC.CLEAR_RESTEER_CYCLES'/, -cpu/event=0xec,umask=0x02,period=2000003,name='CPU_CLK_UNHALTED.DISTRIBUTED'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xd3,umask=0x10,cmask=0x00,period=100007,name='MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM'/, -cpu/event=0xd1,umask=0x08,cmask=0x00,period=200003,name='MEM_LOAD_RETIRED.L1_MISS'/, -cpu/event=0xd1,umask=0x80,cmask=0x00,period=1000003,name='MEM_LOAD_RETIRED.LOCAL_PMM'/, -cpu/event=0xb1,umask=0x01,cmask=0x03,period=2000003,name='UOPS_EXECUTED.CYCLES_GE_3'/, -cpu/event=0xc2,umask=0x04,period=2000003,name='UOPS_RETIRED.MS'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xd0,umask=0x21,cmask=0x00,period=1000003,name='MEM_INST_RETIRED.LOCK_LOADS'/, -cpu/event=0xd0,umask=0x82,cmask=0x00,period=1000003,name='MEM_INST_RETIRED.ALL_STORES'/, -cpu/event=0x24,umask=0xe2,cmask=0x00,period=2000003,name='L2_RQSTS.ALL_RFO'/, -cpu/event=0x24,umask=0xc2,cmask=0x00,period=2000003,name='L2_RQSTS.RFO_HIT'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x2a,umask=0x01,cmask=0x00,offcore_rsp=0x8003C0001,name='OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD'/, -cpu/event=0x2a,umask=0x01,cmask=0x00,offcore_rsp=0x10003C0002,name='OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM'/, -cpu/event=0x20,umask=0x04,cmask=0x01,period=1000003,name='OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO'/, -cpu/event=0xd1,umask=0x40,cmask=0x00,period=100007,name='MEM_LOAD_RETIRED.FB_HIT'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x79,umask=0x04,cmask=0x01,period=2000003,name='IDQ.MITE_CYCLES_ANY'/, -cpu/event=0x79,umask=0x04,cmask=0x06,period=2000003,name='IDQ.MITE_CYCLES_OK'/, -cpu/event=0x79,umask=0x08,cmask=0x01,period=2000003,name='IDQ.DSB_CYCLES_ANY'/, -cpu/event=0x79,umask=0x08,cmask=0x06,period=2000003,name='IDQ.DSB_CYCLES_OK'/, -cpu/event=0xec,umask=0x02,period=2000003,name='CPU_CLK_UNHALTED.DISTRIBUTED'/, -cpu/event=0xb7,umask=0x02,period=2000003,name='EXE.AMX_BUSY'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xd3,umask=0x02,cmask=0x00,period=1000003,name='MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM'/, -cpu/event=0xd3,umask=0x01,cmask=0x00,period=100007,name='MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM'/, -cpu/event=0x2a,umask=0x01,offcore_rsp=0x104004477,name='OCR.READS_TO_CORE.LOCAL_DRAM'/, -cpu/event=0x2a,umask=0x01,offcore_rsp=0x730004477,name='OCR.READS_TO_CORE.REMOTE_DRAM'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xd2,umask=0x02,cmask=0x00,period=20011,name='MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD'/, -cpu/event=0xd2,umask=0x04,cmask=0x00,period=20011,name='MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD'/, -cpu/event=0x47,umask=0x02,cmask=0x02,period=1000003,name='MEMORY_ACTIVITY.CYCLES_L1D_MISS'/, -cpu/event=0x2a,umask=0x01,offcore_rsp=0x90002380,name='OCR.HWPF_L3.REMOTE'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x2a,umask=0x01,cmask=0x00,offcore_rsp=0x1030004477,name='OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM'/, -cpu/event=0x2a,umask=0x01,offcore_rsp=0x84002380,name='OCR.HWPF_L3.L3_MISS_LOCAL'/, -cpu/event=0x20,umask=0x08,cmask=0x01,period=1000003,name='OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD'/, -cpu/event=0x20,umask=0x08,cmask=0x04,period=1000003,name='OFFCORE_REQUESTS_OUTSTANDING.DATA_RD:c4'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xe7,umask=0x0c,cmask=0x00,period=100003,name='INT_VEC_RETIRED.ADD_256'/, -cpu/event=0xe7,umask=0x20,cmask=0x00,period=100003,name='INT_VEC_RETIRED.VNNI_256'/, -cpu/event=0xe7,umask=0x80,cmask=0x00,period=100003,name='INT_VEC_RETIRED.MUL_256'/, -cpu/event=0x79,umask=0x08,cmask=0x00,period=2000003,name='IDQ.DSB_UOPS'/, -cpu/event=0x79,umask=0x04,period=100003,name='IDQ.MITE_UOPS'/, -cpu/event=0x79,umask=0x20,period=100003,name='IDQ.MS_UOPS'/, -cpu/event=0xa8,umask=0x01,cmask=0x00,period=2000003,name='LSD.UOPS'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xd3,umask=0x08,cmask=0x00,period=100007,name='MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD'/, -cpu/event=0xd3,umask=0x04,cmask=0x00,period=100007,name='MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM'/, -cpu/event=0x2a,umask=0x01,offcore_rsp=0x1030004477,name='OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM'/, -cpu/event=0x2a,umask=0x01,offcore_rsp=0x830004477,name='OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD'/, -cpu-cycles:k, -ref-cycles:k, -instructions:k; - -#C6 -cstate_core/c6-residency/; -cstate_pkg/c6-residency/; - -#UPI -upi/event=0x02,umask=0x0f,name='UNC_UPI_TxL_FLITS.ALL_DATA'/; - -#CHA (Cache) -cha/event=0x35,umask=0xc80ffe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_CRD'/, -cha/event=0x35,umask=0xc8177e01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE'/, -cha/event=0x36,umask=0xc8177e01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE'/; - -cha/event=0x35,umask=0xC816FE01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL'/, -cha/event=0x36,umask=0xc816fe01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL'/, -cha/event=0x35,umask=0xC896FE01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL'/, -cha/event=0x35,umask=0xC8977E01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE'/; - -cha/event=0x35,umask=0xccd7fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA'/, -cha/event=0x35,umask=0xc817fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD'/, -cha/event=0x35,umask=0xc897fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF'/, -cha/event=0x36,umask=0xC817fe01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD'/; - -#CHA (IO Bandwidth) -cha/event=0x35,umask=0xc8f3ff04,name='UNC_CHA_TOR_INSERTS.IO_PCIRDCUR'/, -cha/event=0x35,umask=0xCC43FF04,name='UNC_CHA_TOR_INSERTS.IO_ITOM'/, -cha/event=0x35,umask=0xCD43FF04,name='UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR'/, -cha/event=0x01,umask=0x00,name='UNC_CHA_CLOCKTICKS'/; - -#IMC (memory read/writes) -imc/event=0x05,umask=0xcf,name='UNC_M_CAS_COUNT.RD'/, -imc/event=0x05,umask=0xf0,name='UNC_M_CAS_COUNT.WR'/; - -#power -power/energy-pkg/, -power/energy-ram/; diff --git a/cmd/metrics/resources/events/x86_64/GenuineIntel/spr_nofixedtma.txt b/cmd/metrics/resources/events/x86_64/GenuineIntel/spr_nofixedtma.txt deleted file mode 100644 index 30ef2fb9..00000000 --- a/cmd/metrics/resources/events/x86_64/GenuineIntel/spr_nofixedtma.txt +++ /dev/null @@ -1,135 +0,0 @@ -# SapphireRapids event list for platforms that don't have support for the fixed counter -# TMA events, e.g., some AWS VMs. -# Note that there are no more than 10 events per group. On these same platforms, the cpu-cycles fixed -# counter is not supported so a general purpose counter will be used. - -cpu/event=0x51,umask=0x01,period=100003,name='L1D.REPLACEMENT'/, -cpu/event=0x24,umask=0xe4,period=200003,name='L2_RQSTS.ALL_CODE_RD'/, -cpu/event=0xd1,umask=0x01,period=1000003,name='MEM_LOAD_RETIRED.L1_HIT'/, -cpu/event=0x25,umask=0x1f,period=100003,name='L2_LINES_IN.ALL'/, -cpu/event=0xc4,umask=0x00,period=100003,name='BR_INST_RETIRED.ALL_BRANCHES'/, -cpu/event=0xc5,umask=0x00,period=100003,name='BR_MISP_RETIRED.ALL_BRANCHES'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xd1,umask=0x10,period=100021,name='MEM_LOAD_RETIRED.L2_MISS'/, -cpu/event=0x24,umask=0x24,period=200003,name='L2_RQSTS.CODE_RD_MISS'/, -cpu/event=0x11,umask=0x0e,period=100003,name='ITLB_MISSES.WALK_COMPLETED'/, -cpu/event=0x47,umask=0x03,cmask=0x03,period=1000003,name='MEMORY_ACTIVITY.STALLS_L1D_MISS'/, -cpu/event=0xa6,umask=0x40,cmask=0x02,period=1000003,name='EXE_ACTIVITY.BOUND_ON_STORES'/, -cpu/event=0xa6,umask=0x21,cmask=0x05,period=2000003,name='EXE_ACTIVITY.BOUND_ON_LOADS'/, -cpu/event=0xad,umask=0x10,period=1000003,name='INT_MISC.UOP_DROPPING'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x12,umask=0x0e,period=100003,name='DTLB_LOAD_MISSES.WALK_COMPLETED'/, -cpu/event=0x12,umask=0x04,period=100003,name='DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M'/, -cpu/event=0x13,umask=0x0e,period=100003,name='DTLB_STORE_MISSES.WALK_COMPLETED'/, -cpu/event=0xd1,umask=0x02,period=200003,name='MEM_LOAD_RETIRED.L2_HIT'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x47,umask=0x09,cmask=0x09,period=1000003,name='MEMORY_ACTIVITY.STALLS_L3_MISS'/, -cpu/event=0x80,umask=0x04,period=500009,name='ICACHE_DATA.STALLS'/, -cpu/event=0x83,umask=0x04,period=200003,name='ICACHE_TAG.STALLS'/, -cpu-cycles, -ref-cycles, -instructions; - -# events for TMA metrics without fixed counter support (group 1) -cpu/event=0x9c,umask=0x01,name='IDQ_UOPS_NOT_DELIVERED.CORE'/, -cpu/event=0xa4,umask=0x01,name='TOPDOWN.SLOTS_P'/, -cpu/event=0x9c,umask=0x01,name='IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE'/, -cpu/event=0xc2,umask=0x02,name='UOPS_RETIRED.SLOTS'/, -cpu/event=0xae,umask=0x01,name='UOPS_ISSUED.ANY'/, -cpu/event=0x87,umask=0x01,name='DECODE.LCP'/, -cpu/event=0x61,umask=0x02,name='DSB2MITE_SWITCHES.PENALTY_CYCLES'/, -cpu-cycles, -ref-cycles, -instructions; - -# events for TMA metrics without fixed counter support (group 2) -cpu/event=0xa4,umask=0x02,name='TOPDOWN.BACKEND_BOUND_SLOTS'/, -cpu/event=0xa4,umask=0x08,name='TOPDOWN.BR_MISPREDICT_SLOTS'/, -cpu/event=0xa4,umask=0x10,name='TOPDOWN.MEMORY_BOUND_SLOTS'/, -cpu/event=0xc2,umask=0x01,name='UOPS_RETIRED.HEAVY'/, -cpu/event=0xe5,umask=0x03,name='MEM_UOP_RETIRED.ANY'/, -cpu/event=0xc0,umask=0x10,name='INST_RETIRED.MACRO_FUSED'/, -cpu/event=0xc4,umask=0x00,name='BR_INST_RETIRED.ALL_BRANCHES'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x47,umask=0x03,cmask=0x03,period=1000003,name='MEMORY_ACTIVITY.STALLS_L1D_MISS'/, -cpu/event=0x47,umask=0x05,cmask=0x05,period=1000003,name='MEMORY_ACTIVITY.STALLS_L2_MISS'/, -cpu/event=0xb0,umask=0x09,cmask=0x01,period=1000003,name='ARITH.DIV_ACTIVE'/, -cpu/event=0xec,umask=0x02,period=2000003,name='CPU_CLK_UNHALTED.DISTRIBUTED'/, -cpu/event=0xd0,umask=0x21,cmask=0x00,period=1000003,name='MEM_INST_RETIRED.LOCK_LOADS'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x79,umask=0x04,cmask=0x01,period=2000003,name='IDQ.MITE_CYCLES_ANY'/, -cpu/event=0x79,umask=0x04,cmask=0x06,period=2000003,name='IDQ.MITE_CYCLES_OK'/, -cpu/event=0x79,umask=0x08,cmask=0x01,period=2000003,name='IDQ.DSB_CYCLES_ANY'/, -cpu/event=0x79,umask=0x08,cmask=0x06,period=2000003,name='IDQ.DSB_CYCLES_OK'/, -cpu/event=0xec,umask=0x02,period=2000003,name='CPU_CLK_UNHALTED.DISTRIBUTED'/, -cpu/event=0xb7,umask=0x02,period=2000003,name='EXE.AMX_BUSY'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x79,umask=0x08,cmask=0x00,period=2000003,name='IDQ.DSB_UOPS'/, -cpu/event=0x79,umask=0x04,period=100003,name='IDQ.MITE_UOPS'/, -cpu/event=0x79,umask=0x20,period=100003,name='IDQ.MS_UOPS'/, -cpu/event=0xa8,umask=0x01,cmask=0x00,period=2000003,name='LSD.UOPS'/, -cpu-cycles:k, -ref-cycles:k, -instructions:k; - -#OCR -cpu/event=0x2a,umask=0x01,offcore_rsp=0x104004477,name='OCR.READS_TO_CORE.LOCAL_DRAM'/, -cpu/event=0x2a,umask=0x01,offcore_rsp=0x730004477,name='OCR.READS_TO_CORE.REMOTE_DRAM'/, -cpu/event=0x2a,umask=0x01,offcore_rsp=0x90002380,name='OCR.HWPF_L3.REMOTE'/, -cpu/event=0x2a,umask=0x01,offcore_rsp=0x84002380,name='OCR.HWPF_L3.L3_MISS_LOCAL'/, -cpu/event=0x2a,umask=0x01,offcore_rsp=0x1030004477,name='OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM'/, -cpu/event=0x2a,umask=0x01,offcore_rsp=0x830004477,name='OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD'/; - -#C6 -cstate_core/c6-residency/; -cstate_pkg/c6-residency/; - -#UPI -upi/event=0x02,umask=0x0f,name='UNC_UPI_TxL_FLITS.ALL_DATA'/; - -#CHA (Cache) -cha/event=0x35,umask=0xc80ffe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_CRD'/, -cha/event=0x35,umask=0xc8177e01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE'/, -cha/event=0x36,umask=0xc8177e01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE'/; - -cha/event=0x35,umask=0xC816FE01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL'/, -cha/event=0x36,umask=0xc816fe01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL'/, -cha/event=0x35,umask=0xC896FE01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL'/, -cha/event=0x35,umask=0xC8977E01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE'/; - -cha/event=0x35,umask=0xccd7fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA'/, -cha/event=0x35,umask=0xc817fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD'/, -cha/event=0x35,umask=0xc897fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF'/, -cha/event=0x36,umask=0xC817fe01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD'/; - -#CHA (IO Bandwidth) -cha/event=0x35,umask=0xc8f3ff04,name='UNC_CHA_TOR_INSERTS.IO_PCIRDCUR'/, -cha/event=0x35,umask=0xCC43FF04,name='UNC_CHA_TOR_INSERTS.IO_ITOM'/, -cha/event=0x35,umask=0xCD43FF04,name='UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR'/, -cha/event=0x01,umask=0x00,name='UNC_CHA_CLOCKTICKS'/; - -#IMC (memory read/writes) -imc/event=0x05,umask=0xcf,name='UNC_M_CAS_COUNT.RD'/, -imc/event=0x05,umask=0xf0,name='UNC_M_CAS_COUNT.WR'/; - -#power -power/energy-pkg/, -power/energy-ram/; diff --git a/cmd/metrics/resources/events/x86_64/GenuineIntel/srf.txt b/cmd/metrics/resources/events/x86_64/GenuineIntel/srf.txt deleted file mode 100644 index d6844a3e..00000000 --- a/cmd/metrics/resources/events/x86_64/GenuineIntel/srf.txt +++ /dev/null @@ -1,113 +0,0 @@ -# SierraForest event list - -cpu/event=0xc4,umask=0x00,period=100003,name='BR_INST_RETIRED.ALL_BRANCHES'/, -cpu/event=0xc5,umask=0x00,period=100003,name='BR_MISP_RETIRED.ALL_BRANCHES'/, -cpu-cycles:k, -ref-cycles:k, -instructions:k; - -cpu/event=0x08,umask=0x08,name='DTLB_LOAD_MISSES.WALK_COMPLETED_1G'/, -cpu/event=0x08,umask=0xe,name='DTLB_LOAD_MISSES.WALK_COMPLETED'/, -cpu/event=0x49,umask=0xe,name='DTLB_STORE_MISSES.WALK_COMPLETED'/, -cpu/event=0x12,umask=0x02,name='DTLB_LOAD_MISSES.WALK_COMPLETED_4K'/, -cpu/event=0x12,umask=0x04,name='DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x2e,umask=0x41,name='LONGEST_LAT_CACHE.MISS'/, -cpu/event=0x2e,umask=0x4f,name='LONGEST_LAT_CACHE.REFERENCE'/, -cpu/event=0x85,umask=0xe,name='ITLB_MISSES.WALK_COMPLETED'/, -cpu/event=0xd0,umask=0x21,name='MEM_UOPS_RETIRED.LOCK_LOADS'/, -cpu/event=0xd1,umask=0x02,name='MEM_LOAD_UOPS_RETIRED.L2_HIT'/, -cpu/event=0xd1,umask=0x40,name='MEM_LOAD_UOPS_RETIRED.L1_MISS'/, -cpu/event=0xd1,umask=0x1,name='MEM_LOAD_UOPS_RETIRED.L1_HIT'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x71,umask=0x00,name='TOPDOWN_FE_BOUND.ALL'/, -cpu/event=0x71,umask=0x20,name='TOPDOWN_FE_BOUND.ICACHE'/, -cpu/event=0x71,umask=0x10,name='TOPDOWN_FE_BOUND.ITLB_MISS'/, -cpu/event=0x71,umask=0x72,name='TOPDOWN_FE_BOUND.FRONTEND_LATENCY'/, -cpu/event=0x71,umask=0x40,name='TOPDOWN_FE_BOUND.BRANCH_RESTEER'/, -cpu/event=0x71,umask=0x8d,name='TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x80,umask=0x02,name='ICACHE.MISSES'/, -cpu/event=0x05,umask=0xf4,name='LD_HEAD.L1_BOUND_AT_RET'/, -cpu/event=0x72,umask=0x00,name='TOPDOWN_RETIRING.ALL'/, -cpu/event=0x73,umask=0x03,name='TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS'/, -cpu/event=0x73,umask=0x04,name='TOPDOWN_BAD_SPECULATION.MISPREDICT'/, -cpu/event=0x73,umask=0x00,name='TOPDOWN_BAD_SPECULATION.ALL'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x05,umask=0xff,name='LD_HEAD.ANY_AT_RET'/, -cpu/event=0x04,umask=0x07,name='MEM_SCHEDULER_BLOCK.ALL'/, -cpu/event=0x04,umask=0x01,name='MEM_SCHEDULER_BLOCK.ST_BUF'/, -cpu/event=0x74,umask=0x02,name='TOPDOWN_BE_BOUND.MEM_SCHEDULER'/, -cpu/event=0x74,umask=0x10,name='TOPDOWN_BE_BOUND.SERIALIZATION'/, -cpu/event=0x74,umask=0x00,name='TOPDOWN_BE_BOUND.ALL'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0x05,umask=0x81,name='LD_HEAD.L1_MISS_AT_RET'/, -cpu/event=0x34,umask=0x6f,name='MEM_BOUND_STALLS_LOAD.ALL'/, -cpu/event=0x34,umask=0x01,name='MEM_BOUND_STALLS_LOAD.L2_HIT'/, -cpu/event=0x34,umask=0x06,name='MEM_BOUND_STALLS_LOAD.LLC_HIT'/, -cpu-cycles, -ref-cycles, -instructions; - -cpu/event=0xb7,umask=0x01,cmask=0x00,offcore_rsp=0x8000100000004477,name='OCR.READS_TO_CORE.OUTSTANDING'/, -cpu/event=0xb7,umask=0x02,cmask=0x00,offcore_rsp=0x100000014477,name='OCR.READS_TO_CORE.ANY_RESPONSE'/; - -cpu/event=0xB7,umask=0x01,offcore_rsp=0x101030004477,name='OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM'/, -cpu/event=0xB7,umask=0x01,offcore_rsp=0x100830004477,name='OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD'/; - -cpu/event=0xb7,umask=0x01,cmask=0x00,offcore_rsp=0x10244,name='OCR.L2_CODE_MISS'/, -cpu/event=0xb7,umask=0x02,cmask=0x00,offcore_rsp=0x10070,name='OCR.HWPF_L2.ANY_RESPONSE'/; - -cpu/event=0xb7,umask=0x01,cmask=0x00,offcore_rsp=0x1010003C4477,name='OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM'/, -cpu/event=0xb7,umask=0x02,cmask=0x00,offcore_rsp=0x1008003C4477,name='OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD'/; - -#CHA (Cache) -cha/event=0x01,umask=0x00,name='UNC_CHA_CLOCKTICKS'/; - -cha/event=0x35,umask=0x00C827FE01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT'/, -cha/event=0x35,umask=0x00C8A7FE01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF'/, -cha/event=0x35,umask=0x00C80FFE01,name='UNC_CHA_TOR_INSERTS.IA_MISS_CRD'/, -cha/event=0x35,umask=0x00C88FFE01,name='UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF'/; - -cha/event=0x35,umask=0x00CCD7FE01,name='UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA'/, -cha/event=0x35,umask=0x00C807FE01,name='UNC_CHA_TOR_INSERTS.IA_MISS_RFO'/, -cha/event=0x35,umask=0x00C887FE01,name='UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF'/, -cha/event=0x35,umask=0x00CCC7FE01,name='UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO'/; - -#CHA (IO Bandwidth) -cha/event=0x35,umask=0x00C8F3FF04,name='UNC_CHA_TOR_INSERTS.IO_PCIRDCUR'/, -cha/event=0x35,umask=0x00CC43FF04,name='UNC_CHA_TOR_INSERTS.IO_ITOM'/, -cha/event=0x35,umask=0x00CD43FF04,name='UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR'/; - -cha/event=0x36,umask=0x00C827FE01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT'/; - -cha/event=0x36,umask=0x00C807FE01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO'/; - -#IMC (memory read/writes) -imc/event=0x05,umask=0xCF,name='UNC_M_CAS_COUNT_SCH0.RD'/, -imc/event=0x05,umask=0xF0,name='UNC_M_CAS_COUNT_SCH0.WR'/, -imc/event=0x06,umask=0xCF,name='UNC_M_CAS_COUNT_SCH1.RD'/, -imc/event=0x06,umask=0xF0,name='UNC_M_CAS_COUNT_SCH1.WR'/; - -#C6 -cstate_core/c6-residency/; -cstate_pkg/c6-residency/; - -#power -power/energy-pkg/, -power/energy-ram/; diff --git a/cmd/metrics/resources/events/x86_64/AuthenticAMD/bergamo.txt b/cmd/metrics/resources/legacy/events/x86_64/AuthenticAMD/bergamo.txt similarity index 100% rename from cmd/metrics/resources/events/x86_64/AuthenticAMD/bergamo.txt rename to cmd/metrics/resources/legacy/events/x86_64/AuthenticAMD/bergamo.txt diff --git a/cmd/metrics/resources/events/x86_64/AuthenticAMD/genoa.txt b/cmd/metrics/resources/legacy/events/x86_64/AuthenticAMD/genoa.txt similarity index 100% rename from cmd/metrics/resources/events/x86_64/AuthenticAMD/genoa.txt rename to cmd/metrics/resources/legacy/events/x86_64/AuthenticAMD/genoa.txt diff --git a/cmd/metrics/resources/events/x86_64/AuthenticAMD/turin.txt b/cmd/metrics/resources/legacy/events/x86_64/AuthenticAMD/turin.txt similarity index 100% rename from cmd/metrics/resources/events/x86_64/AuthenticAMD/turin.txt rename to cmd/metrics/resources/legacy/events/x86_64/AuthenticAMD/turin.txt diff --git a/cmd/metrics/resources/events/x86_64/GenuineIntel/bdx.txt b/cmd/metrics/resources/legacy/events/x86_64/GenuineIntel/bdx.txt similarity index 100% rename from cmd/metrics/resources/events/x86_64/GenuineIntel/bdx.txt rename to cmd/metrics/resources/legacy/events/x86_64/GenuineIntel/bdx.txt diff --git a/cmd/metrics/resources/events/x86_64/GenuineIntel/clx.txt b/cmd/metrics/resources/legacy/events/x86_64/GenuineIntel/clx.txt similarity index 100% rename from cmd/metrics/resources/events/x86_64/GenuineIntel/clx.txt rename to cmd/metrics/resources/legacy/events/x86_64/GenuineIntel/clx.txt diff --git a/cmd/metrics/resources/events/x86_64/GenuineIntel/skx.txt b/cmd/metrics/resources/legacy/events/x86_64/GenuineIntel/skx.txt similarity index 100% rename from cmd/metrics/resources/events/x86_64/GenuineIntel/skx.txt rename to cmd/metrics/resources/legacy/events/x86_64/GenuineIntel/skx.txt diff --git a/cmd/metrics/resources/metrics/x86_64/AuthenticAMD/bergamo.json b/cmd/metrics/resources/legacy/metrics/x86_64/AuthenticAMD/bergamo.json similarity index 100% rename from cmd/metrics/resources/metrics/x86_64/AuthenticAMD/bergamo.json rename to cmd/metrics/resources/legacy/metrics/x86_64/AuthenticAMD/bergamo.json diff --git a/cmd/metrics/resources/metrics/x86_64/AuthenticAMD/genoa.json b/cmd/metrics/resources/legacy/metrics/x86_64/AuthenticAMD/genoa.json similarity index 100% rename from cmd/metrics/resources/metrics/x86_64/AuthenticAMD/genoa.json rename to cmd/metrics/resources/legacy/metrics/x86_64/AuthenticAMD/genoa.json diff --git a/cmd/metrics/resources/metrics/x86_64/AuthenticAMD/turin.json b/cmd/metrics/resources/legacy/metrics/x86_64/AuthenticAMD/turin.json similarity index 100% rename from cmd/metrics/resources/metrics/x86_64/AuthenticAMD/turin.json rename to cmd/metrics/resources/legacy/metrics/x86_64/AuthenticAMD/turin.json diff --git a/cmd/metrics/resources/metrics/x86_64/GenuineIntel/bdx.json b/cmd/metrics/resources/legacy/metrics/x86_64/GenuineIntel/bdx.json similarity index 100% rename from cmd/metrics/resources/metrics/x86_64/GenuineIntel/bdx.json rename to cmd/metrics/resources/legacy/metrics/x86_64/GenuineIntel/bdx.json diff --git a/cmd/metrics/resources/metrics/x86_64/GenuineIntel/clx.json b/cmd/metrics/resources/legacy/metrics/x86_64/GenuineIntel/clx.json similarity index 100% rename from cmd/metrics/resources/metrics/x86_64/GenuineIntel/clx.json rename to cmd/metrics/resources/legacy/metrics/x86_64/GenuineIntel/clx.json diff --git a/cmd/metrics/resources/metrics/x86_64/GenuineIntel/skx.json b/cmd/metrics/resources/legacy/metrics/x86_64/GenuineIntel/skx.json similarity index 100% rename from cmd/metrics/resources/metrics/x86_64/GenuineIntel/skx.json rename to cmd/metrics/resources/legacy/metrics/x86_64/GenuineIntel/skx.json diff --git a/cmd/metrics/resources/metrics/x86_64/GenuineIntel/emr.json b/cmd/metrics/resources/metrics/x86_64/GenuineIntel/emr.json deleted file mode 100644 index 50aa9642..00000000 --- a/cmd/metrics/resources/metrics/x86_64/GenuineIntel/emr.json +++ /dev/null @@ -1,462 +0,0 @@ -[ - { - "name": "CPU operating frequency (in GHz)", - "expression": "(([cpu-cycles] / [ref-cycles] * [SYSTEM_TSC_FREQ]) / 1000000000)" - }, - { - "name": "CPU utilization %", - "expression": "100 * [ref-cycles] / [TSC]" - }, - { - "name": "CPU utilization% in kernel mode", - "expression": "100 * [ref-cycles:k] / [TSC]" - }, - { - "name": "CPI", - "expression": "[cpu-cycles] / [instructions]" - }, - { - "name": "cycles per txn", - "expression": "[cpu-cycles] / [TXN]" - }, - { - "name": "kernel_CPI", - "expression": "[cpu-cycles:k] / [instructions:k]" - }, - { - "name": "kernel_cycles per txn", - "expression": "[cpu-cycles:k] / [TXN]" - }, - { - "name": "IPC", - "expression": "[instructions] / [cpu-cycles]" - }, - { - "name": "txn per cycle", - "expression": "[TXN] / [cpu-cycles]" - }, - { - "name": "giga_instructions_per_sec", - "expression": "[instructions] / 1000000000" - }, - { - "name": "branch misprediction ratio", - "expression": "[BR_MISP_RETIRED.ALL_BRANCHES] / [BR_INST_RETIRED.ALL_BRANCHES]" - }, - { - "name": "locks retired per instr", - "expression": "[MEM_INST_RETIRED.LOCK_LOADS] / [instructions]" - }, - { - "name": "locks retired per txn", - "expression": "[MEM_INST_RETIRED.LOCK_LOADS] / [TXN]" - }, - { - "name": "L1D MPI (includes data+rfo w/ prefetches)", - "expression": "[L1D.REPLACEMENT] / [instructions]" - }, - { - "name": "L1D misses per txn (includes data+rfo w/ prefetches)", - "expression": "[L1D.REPLACEMENT] / [TXN]" - }, - { - "name": "L1D demand data read hits per instr", - "expression": "[MEM_LOAD_RETIRED.L1_HIT] / [instructions]" - }, - { - "name": "L1D demand data read hits per txn", - "expression": "[MEM_LOAD_RETIRED.L1_HIT] / [TXN]" - }, - { - "name": "L1-I code read misses (w/ prefetches) per instr", - "expression": "[L2_RQSTS.ALL_CODE_RD] / [instructions]" - }, - { - "name": "L1I code read misses (includes prefetches) per txn", - "expression": "[L2_RQSTS.ALL_CODE_RD] / [TXN]" - }, - { - "name": "L2 demand data read hits per instr", - "expression": "[MEM_LOAD_RETIRED.L2_HIT] / [instructions]" - }, - { - "name": "L2 demand data read hits per txn", - "expression": "[MEM_LOAD_RETIRED.L2_HIT] / [TXN]" - }, - { - "name": "L2 MPI (includes code+data+rfo w/ prefetches)", - "expression": "[L2_LINES_IN.ALL] / [instructions]" - }, - { - "name": "L2 misses per txn (includes code+data+rfo w/ prefetches)", - "expression": "[L2_LINES_IN.ALL] / [TXN]" - }, - { - "name": "L2 demand data read MPI", - "expression": "[MEM_LOAD_RETIRED.L2_MISS] / [instructions]" - }, - { - "name": "L2 demand data read misses per txn", - "expression": "[MEM_LOAD_RETIRED.L2_MISS] / [TXN]" - }, - { - "name": "L2 demand code MPI", - "expression": "[L2_RQSTS.CODE_RD_MISS] / [instructions]" - }, - { - "name": "L2 demand code misses per txn", - "expression": "[L2_RQSTS.CODE_RD_MISS] / [TXN]" - }, - { - "name": "LLC code read MPI (demand+prefetch)", - "expression": "[UNC_CHA_TOR_INSERTS.IA_MISS_CRD] / [instructions]" - }, - { - "name": "LLC code read (demand+prefetch) misses per txn", - "expression": "[UNC_CHA_TOR_INSERTS.IA_MISS_CRD] / [TXN]" - }, - { - "name": "LLC data read MPI (demand+prefetch)", - "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF]) / [instructions]" - }, - { - "name": "LLC data read (demand+prefetch) misses per txn", - "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF]) / [TXN]" - }, - { - "name": "LLC total HITM (per instr) (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM] / [instructions]" - }, - { - "name": "LLC total HITM per txn (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM] / [TXN]" - }, - { - "name": "LLC total HIT clean line forwards (per instr) (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD] / [instructions]" - }, - { - "name": "LLC total HIT clean line forwards per txn (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD] / [TXN]" - }, - { - "name": "Average LLC demand data read miss latency (in ns)", - "expression": "( 1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) ) ) * 1" - }, - { - "name": "Average LLC demand data read miss latency for LOCAL requests (in ns)", - "expression": "( 1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) ) ) * 1" - }, - { - "name": "Average LLC demand data read miss latency for REMOTE requests (in ns)", - "expression": "( 1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) ) ) * 1" - }, - { - "name": "UPI Data transmit BW (MB/sec) (only data)", - "expression": "([UNC_UPI_TxL_FLITS.ALL_DATA] * (64 / 9.0) / 1000000) / 1" - }, - { - "name": "package power (watts)", - "expression": "[power/energy-pkg/]" - }, - { - "name": "DRAM power (watts)", - "expression": "[power/energy-ram/]" - }, - { - "name": "core c6 residency %", - "expression": "100 * [cstate_core/c6-residency/] / [TSC]" - }, - { - "name": "package c6 residency %", - "expression": "100 * [cstate_pkg/c6-residency/] * [CORES_PER_SOCKET] / [TSC]" - }, - { - "name": "% Uops delivered from decoded Icache (DSB)", - "expression": "100 * ([IDQ.DSB_UOPS] / ([IDQ.DSB_UOPS] + [IDQ.MITE_UOPS] + [IDQ.MS_UOPS] + [LSD.UOPS]) )" - }, - { - "name": "% Uops delivered from legacy decode pipeline (MITE)", - "expression": "100 * ([IDQ.MITE_UOPS] / ([IDQ.DSB_UOPS] + [IDQ.MITE_UOPS] + [IDQ.MS_UOPS] + [LSD.UOPS]) )" - }, - { - "name": "core initiated local dram read bandwidth (MB/sec)", - "expression": "([OCR.READS_TO_CORE.LOCAL_DRAM] + [OCR.HWPF_L3.L3_MISS_LOCAL]) * 64 / 1000000" - }, - { - "name": "core initiated remote dram read bandwidth (MB/sec)", - "expression": "([OCR.READS_TO_CORE.REMOTE_DRAM] + [OCR.HWPF_L3.REMOTE]) * 64 / 1000000" - }, - { - "name": "memory bandwidth read (MB/sec)", - "expression": "([UNC_M_CAS_COUNT.RD] * 64 / 1000000) / 1" - }, - { - "name": "memory bandwidth write (MB/sec)", - "expression": "([UNC_M_CAS_COUNT.WR] * 64 / 1000000) / 1" - }, - { - "name": "memory bandwidth total (MB/sec)", - "expression": "(([UNC_M_CAS_COUNT.RD] + [UNC_M_CAS_COUNT.WR]) * 64 / 1000000) / 1" - }, - { - "name": "ITLB (2nd level) MPI", - "expression": "[ITLB_MISSES.WALK_COMPLETED] / [instructions]" - }, - { - "name": "ITLB (2nd level) misses per txn", - "expression": "[ITLB_MISSES.WALK_COMPLETED] / [TXN]" - }, - { - "name": "DTLB (2nd level) load MPI", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [instructions]" - }, - { - "name": "DTLB (2nd level) load misses per txn", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [TXN]" - }, - { - "name": "DTLB (2nd level) 2MB large page load MPI", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M] / [instructions]" - }, - { - "name": "DTLB (2nd level) 2MB large page load misses per txn", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M] / [TXN]" - }, - { - "name": "DTLB (2nd level) store MPI", - "expression": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [instructions]" - }, - { - "name": "DTLB (2nd level) store misses per txn", - "expression": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [TXN]" - }, - { - "name": "NUMA %_Reads addressed to local DRAM", - "expression": "100 * ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL]) / ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE])" - }, - { - "name": "NUMA %_Reads addressed to remote DRAM", - "expression": "100 * ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE]) / ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE])" - }, - { - "name": "uncore frequency GHz", - "expression": "([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) / 1000000000) / 1" - }, - { - "name": "IO_bandwidth_disk_or_network_writes (MB/sec)", - "expression": "([UNC_CHA_TOR_INSERTS.IO_PCIRDCUR] * 64 / 1000000) / 1" - }, - { - "name": "IO_bandwidth_disk_or_network_reads (MB/sec)", - "expression": "(([UNC_CHA_TOR_INSERTS.IO_ITOM] + [UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR]) * 64 / 1000000) / 1" - }, - { - "name": "TMA_Frontend_Bound(%)", - "expression": "100 * ( [PERF_METRICS.FRONTEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) )" - }, - { - "name": "TMA_..Fetch_Latency(%)", - "expression": "100 * ( ( [PERF_METRICS.FETCH_LATENCY] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) ) )" - }, - { - "name": "TMA_....ICache_Misses(%)", - "expression": "100 * ( [ICACHE_DATA.STALLS] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....ITLB_Misses(%)", - "expression": "100 * ( [ICACHE_TAG.STALLS] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....MS_Switches(%)", - "expression": "100 * ( ( 3 ) * [UOPS_RETIRED.MS:c1:e1] / ( [UOPS_RETIRED.SLOTS] / [UOPS_ISSUED.ANY] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....LCP(%)", - "expression": "100 * ( [DECODE.LCP] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....DSB_Switches(%)", - "expression": "100 * ( [DSB2MITE_SWITCHES.PENALTY_CYCLES] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....Branch_Resteers(%)", - "expression": "100 * ( [INT_MISC.CLEAR_RESTEER_CYCLES] / ( [cpu-cycles] ) + ( [INT_MISC.UNKNOWN_BRANCH_CYCLES] / ( [cpu-cycles] ) ) )" - }, - { - "name": "TMA_......Mispredicts_Resteers(%)", - "expression": "100 * ( ( ( [PERF_METRICS.BRANCH_MISPREDICTS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) / ( max( 1 - ( ( [PERF_METRICS.FRONTEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) ) + ( [PERF_METRICS.BACKEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) , 0 ) ) ) * [INT_MISC.CLEAR_RESTEER_CYCLES] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Clears_Resteers(%)", - "expression": "100 * ( ( 1 - ( ( [PERF_METRICS.BRANCH_MISPREDICTS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) / ( max( 1 - ( ( [PERF_METRICS.FRONTEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) ) + ( [PERF_METRICS.BACKEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) , 0 ) ) ) ) * [INT_MISC.CLEAR_RESTEER_CYCLES] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Unknown_Branches(%)", - "expression": "100 * ( [INT_MISC.UNKNOWN_BRANCH_CYCLES] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_..Fetch_Bandwidth(%)", - "expression": "100 * ( max( 0 , ( [PERF_METRICS.FRONTEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) ) - ( ( [PERF_METRICS.FETCH_LATENCY] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) ) ) ) )" - }, - { - "name": "TMA_....MITE(%)", - "expression": "100 * ( ( [IDQ.MITE_CYCLES_ANY] - [IDQ.MITE_CYCLES_OK] ) / ( [CPU_CLK_UNHALTED.DISTRIBUTED] ) / 2 )" - }, - { - "name": "TMA_....DSB(%)", - "expression": "100 * ( ( [IDQ.DSB_CYCLES_ANY] - [IDQ.DSB_CYCLES_OK] ) / ( [CPU_CLK_UNHALTED.DISTRIBUTED] ) / 2 )" - }, - { - "name": "TMA_Bad_Speculation(%)", - "expression": "100 * ( max( 1 - ( ( [PERF_METRICS.FRONTEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) ) + ( [PERF_METRICS.BACKEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) , 0 ) )" - }, - { - "name": "TMA_..Branch_Mispredicts(%)", - "expression": "100 * ( [PERF_METRICS.BRANCH_MISPREDICTS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) )" - }, - { - "name": "TMA_..Machine_Clears(%)", - "expression": "100 * ( max( 0 , ( max( 1 - ( ( [PERF_METRICS.FRONTEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) ) + ( [PERF_METRICS.BACKEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) , 0 ) ) - ( [PERF_METRICS.BRANCH_MISPREDICTS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) )" - }, - { - "name": "TMA_Backend_Bound(%)", - "expression": "100 * ( [PERF_METRICS.BACKEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) )" - }, - { - "name": "TMA_..Memory_Bound(%)", - "expression": "100 * ( [PERF_METRICS.MEMORY_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) )" - }, - { - "name": "TMA_....L1_Bound(%)", - "expression": "100 * ( max( ( [EXE_ACTIVITY.BOUND_ON_LOADS] - [MEMORY_ACTIVITY.STALLS_L1D_MISS] ) / ( [cpu-cycles] ) , 0 ) )" - }, - { - "name": "TMA_......DTLB_Load(%)", - "expression": "100 * ( min( ( 7 ) * [DTLB_LOAD_MISSES.STLB_HIT:c1] + [DTLB_LOAD_MISSES.WALK_ACTIVE] , max( [CYCLE_ACTIVITY.CYCLES_MEM_ANY] - [MEMORY_ACTIVITY.CYCLES_L1D_MISS] , 0 ) ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Lock_Latency(%)", - "expression": "100 * ( min( ( ( 16 * max( 0 , [MEM_INST_RETIRED.LOCK_LOADS] - [L2_RQSTS.ALL_RFO] ) + ( [MEM_INST_RETIRED.LOCK_LOADS] / [MEM_INST_RETIRED.ALL_STORES] ) * ( ( 10 ) * [L2_RQSTS.RFO_HIT] + ( min( [cpu-cycles] , [OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO] ) ) ) ) / ( [cpu-cycles] ) ) , ( 1 ) ) )" - }, - { - "name": "TMA_....L2_Bound(%)", - "expression": "100 * ( ( [MEMORY_ACTIVITY.STALLS_L1D_MISS] - [MEMORY_ACTIVITY.STALLS_L2_MISS] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....L3_Bound(%)", - "expression": "100 * ( ( [MEMORY_ACTIVITY.STALLS_L2_MISS] - [MEMORY_ACTIVITY.STALLS_L3_MISS] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Data_Sharing(%)", - "expression": "100 * ( min( ( ( ( 79.5 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( 1000 / 1000 ) ) ) - ( 4 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( 1000 / 1000 ) ) ) ) * ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD] + [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD] * ( 1 - ( [OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM] / ( [OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM] + [OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD] ) ) ) ) * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) / 2 ) / ( [cpu-cycles] ) ) , ( 1 ) ) )" - }, - { - "name": "TMA_....DRAM_Bound(%)", - "expression": "100 * ( min( ( ( ( [MEMORY_ACTIVITY.STALLS_L3_MISS] / ( [cpu-cycles] ) ) - ( min( ( ( ( ( 1 - ( ( ( 19 * ( [MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) + 10 * ( ( [MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) + ( [MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) + ( [MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) ) ) / ( ( 19 * ( [MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) + 10 * ( ( [MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) + ( [MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) + ( [MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) ) ) + ( 25 * ( ( [MEM_LOAD_RETIRED.LOCAL_PMM] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) ) + 33 * ( ( [MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) ) ) ) ) ) ) * ( [MEMORY_ACTIVITY.STALLS_L3_MISS] / ( [cpu-cycles] ) ) ) if ( ( 1000000 ) * ( [MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM] + [MEM_LOAD_RETIRED.LOCAL_PMM] ) > [MEM_LOAD_RETIRED.L1_MISS] ) else 0 ) ) , ( 1 ) ) ) ) ) , ( 1 ) ) )" - }, - { - "name": "TMA_......MEM_Bandwidth(%)", - "expression": "100 * ( ( min( [cpu-cycles] , [OFFCORE_REQUESTS_OUTSTANDING.DATA_RD:c4] ) ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......MEM_Latency(%)", - "expression": "100 * ( ( min( [cpu-cycles] , [OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD] ) ) / ( [cpu-cycles] ) - ( ( min( [cpu-cycles] , [OFFCORE_REQUESTS_OUTSTANDING.DATA_RD:c4] ) ) / ( [cpu-cycles] ) ) )" - }, - { - "name": "TMA_....Store_Bound(%)", - "expression": "100 * ( [EXE_ACTIVITY.BOUND_ON_STORES] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......False_Sharing(%)", - "expression": "100 * ( min( ( ( 80 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( 1000 / 1000 ) ) ) * [OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM] / ( [cpu-cycles] ) ) , ( 1 ) ) )" - }, - { - "name": "TMA_..Core_Bound(%)", - "expression": "100 * ( max( 0 , ( [PERF_METRICS.BACKEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) - ( [PERF_METRICS.MEMORY_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) )" - }, - { - "name": "TMA_....Divider(%)", - "expression": "100 * ( [ARITH.DIV_ACTIVE] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....AMX_Busy(%)", - "expression": "100 * ( [EXE.AMX_BUSY] / ( [CPU_CLK_UNHALTED.DISTRIBUTED] if [HYPERTHREADING_ON] else ( [cpu-cycles] ) ) )" - }, - { - "name": "TMA_....Ports_Utilization(%)", - "expression": "100 * ( ( [EXE_ACTIVITY.3_PORTS_UTIL:u0x80] + ( [RESOURCE_STALLS.SCOREBOARD] / ( [cpu-cycles] ) ) * ( [CYCLE_ACTIVITY.STALLS_TOTAL] - [EXE_ACTIVITY.BOUND_ON_LOADS] ) + ( [EXE_ACTIVITY.1_PORTS_UTIL] + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * [EXE_ACTIVITY.2_PORTS_UTIL:u0xc] ) ) / ( [cpu-cycles] ) if ( [ARITH.DIV_ACTIVE] < ( [CYCLE_ACTIVITY.STALLS_TOTAL] - [EXE_ACTIVITY.BOUND_ON_LOADS] ) ) else ( [EXE_ACTIVITY.1_PORTS_UTIL] + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * [EXE_ACTIVITY.2_PORTS_UTIL:u0xc] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Ports_Utilized_0(%)", - "expression": "100 * ( [EXE_ACTIVITY.3_PORTS_UTIL:u0x80] / ( [cpu-cycles] ) + ( [RESOURCE_STALLS.SCOREBOARD] / ( [cpu-cycles] ) ) * ( [CYCLE_ACTIVITY.STALLS_TOTAL] - [EXE_ACTIVITY.BOUND_ON_LOADS] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_........AMX_Busy(%)", - "expression": "100 * ( [EXE.AMX_BUSY] / ( [CPU_CLK_UNHALTED.DISTRIBUTED] ) )" - }, - { - "name": "TMA_......Ports_Utilized_1(%)", - "expression": "100 * ( [EXE_ACTIVITY.1_PORTS_UTIL] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Ports_Utilized_2(%)", - "expression": "100 * ( [EXE_ACTIVITY.2_PORTS_UTIL] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Ports_Utilized_3m(%)", - "expression": "100 * ( [UOPS_EXECUTED.CYCLES_GE_3] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_Retiring(%)", - "expression": "100 * ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) )" - }, - { - "name": "TMA_..Light_Operations(%)", - "expression": "100 * ( max( 0 , ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) - ( [PERF_METRICS.HEAVY_OPERATIONS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) )" - }, - { - "name": "TMA_....Memory_Operations(%)", - "expression": "100 * ( ( max( 0 , ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) - ( [PERF_METRICS.HEAVY_OPERATIONS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) ) * [MEM_UOP_RETIRED.ANY] / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) )" - }, - { - "name": "TMA_....Fused_Instructions(%)", - "expression": "100 * ( ( max( 0 , ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) - ( [PERF_METRICS.HEAVY_OPERATIONS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) ) * [INST_RETIRED.MACRO_FUSED] / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) )" - }, - { - "name": "TMA_....Non_Fused_Branches(%)", - "expression": "100 * ( ( max( 0 , ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) - ( [PERF_METRICS.HEAVY_OPERATIONS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) ) * ( [BR_INST_RETIRED.ALL_BRANCHES] - [INST_RETIRED.MACRO_FUSED] ) / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) )" - }, - { - "name": "TMA_........FP_Vector_256b(%)", - "expression": "100 * ( min( ( ( [FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE] + [FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE] + [FP_ARITH_INST_RETIRED2.256B_PACKED_HALF] ) / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) ) , ( 1 ) ) )" - }, - { - "name": "TMA_........FP_Vector_512b(%)", - "expression": "100 * ( min( ( ( [FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE] + [FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE] + [FP_ARITH_INST_RETIRED2.512B_PACKED_HALF] ) / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) ) , ( 1 ) ) )" - }, - { - "name": "TMA_......Int_Vector_256b(%)", - "expression": "100 * ( ( [INT_VEC_RETIRED.ADD_256] + [INT_VEC_RETIRED.MUL_256] + [INT_VEC_RETIRED.VNNI_256] ) / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) )" - }, - { - "name": "TMA_..Heavy_Operations(%)", - "expression": "100 * ( [PERF_METRICS.HEAVY_OPERATIONS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) )" - }, - { - "name": "TMA_....Few_Uops_Instructions(%)", - "expression": "100 * ( max( 0 , ( [PERF_METRICS.HEAVY_OPERATIONS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) - ( [UOPS_RETIRED.MS] / ( [TOPDOWN.SLOTS] ) ) ) )" - }, - { - "name": "TMA_....Microcode_Sequencer(%)", - "expression": "100 * ( [UOPS_RETIRED.MS] / ( [TOPDOWN.SLOTS] ) )" - }, - { - "name": "TMA_Info_Thread_IPC", - "expression": "[instructions] / [cpu-cycles]" - }, - { - "name": "TMA_Info_System_SMT_2T_Utilization", - "expression": "(1 - [CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE] / [CPU_CLK_UNHALTED.REF_DISTRIBUTED]) if [SOCKET_COUNT] > 1 else 0" - } -] \ No newline at end of file diff --git a/cmd/metrics/resources/metrics/x86_64/GenuineIntel/emr_nofixedtma.json b/cmd/metrics/resources/metrics/x86_64/GenuineIntel/emr_nofixedtma.json deleted file mode 100644 index a9e07ed4..00000000 --- a/cmd/metrics/resources/metrics/x86_64/GenuineIntel/emr_nofixedtma.json +++ /dev/null @@ -1,378 +0,0 @@ -[ - { - "name": "CPU operating frequency (in GHz)", - "expression": "(([cpu-cycles] / [ref-cycles] * [SYSTEM_TSC_FREQ]) / 1000000000)" - }, - { - "name": "CPU utilization %", - "expression": "100 * [ref-cycles] / [TSC]" - }, - { - "name": "CPU utilization% in kernel mode", - "expression": "100 * [ref-cycles:k] / [TSC]" - }, - { - "name": "CPI", - "expression": "[cpu-cycles] / [instructions]" - }, - { - "name": "cycles per txn", - "expression": "[cpu-cycles] / [TXN]" - }, - { - "name": "kernel_CPI", - "expression": "[cpu-cycles:k] / [instructions:k]" - }, - { - "name": "kernel_cycles per txn", - "expression": "[cpu-cycles:k] / [TXN]" - }, - { - "name": "IPC", - "expression": "[instructions] / [cpu-cycles]" - }, - { - "name": "txn per cycle", - "expression": "[TXN] / [cpu-cycles]" - }, - { - "name": "giga_instructions_per_sec", - "expression": "[instructions] / 1000000000" - }, - { - "name": "branch misprediction ratio", - "expression": "[BR_MISP_RETIRED.ALL_BRANCHES] / [BR_INST_RETIRED.ALL_BRANCHES]" - }, - { - "name": "locks retired per instr", - "expression": "[MEM_INST_RETIRED.LOCK_LOADS] / [instructions]" - }, - { - "name": "locks retired per txn", - "expression": "[MEM_INST_RETIRED.LOCK_LOADS] / [TXN]" - }, - { - "name": "L1D MPI (includes data+rfo w/ prefetches)", - "expression": "[L1D.REPLACEMENT] / [instructions]" - }, - { - "name": "L1D misses per txn (includes data+rfo w/ prefetches)", - "expression": "[L1D.REPLACEMENT] / [TXN]" - }, - { - "name": "L1D demand data read hits per instr", - "expression": "[MEM_LOAD_RETIRED.L1_HIT] / [instructions]" - }, - { - "name": "L1D demand data read hits per txn", - "expression": "[MEM_LOAD_RETIRED.L1_HIT] / [TXN]" - }, - { - "name": "L1-I code read misses (w/ prefetches) per instr", - "expression": "[L2_RQSTS.ALL_CODE_RD] / [instructions]" - }, - { - "name": "L1I code read misses (includes prefetches) per txn", - "expression": "[L2_RQSTS.ALL_CODE_RD] / [TXN]" - }, - { - "name": "L2 demand data read hits per instr", - "expression": "[MEM_LOAD_RETIRED.L2_HIT] / [instructions]" - }, - { - "name": "L2 demand data read hits per txn", - "expression": "[MEM_LOAD_RETIRED.L2_HIT] / [TXN]" - }, - { - "name": "L2 MPI (includes code+data+rfo w/ prefetches)", - "expression": "[L2_LINES_IN.ALL] / [instructions]" - }, - { - "name": "L2 misses per txn (includes code+data+rfo w/ prefetches)", - "expression": "[L2_LINES_IN.ALL] / [TXN]" - }, - { - "name": "L2 demand data read MPI", - "expression": "[MEM_LOAD_RETIRED.L2_MISS] / [instructions]" - }, - { - "name": "L2 demand data read misses per txn", - "expression": "[MEM_LOAD_RETIRED.L2_MISS] / [TXN]" - }, - { - "name": "L2 demand code MPI", - "expression": "[L2_RQSTS.CODE_RD_MISS] / [instructions]" - }, - { - "name": "L2 demand code misses per txn", - "expression": "[L2_RQSTS.CODE_RD_MISS] / [TXN]" - }, - { - "name": "LLC code read MPI (demand+prefetch)", - "expression": "[UNC_CHA_TOR_INSERTS.IA_MISS_CRD] / [instructions]" - }, - { - "name": "LLC code read (demand+prefetch) misses per txn", - "expression": "[UNC_CHA_TOR_INSERTS.IA_MISS_CRD] / [TXN]" - }, - { - "name": "LLC data read MPI (demand+prefetch)", - "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF]) / [instructions]" - }, - { - "name": "LLC data read (demand+prefetch) misses per txn", - "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF]) / [TXN]" - }, - { - "name": "LLC total HITM (per instr) (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM] / [instructions]" - }, - { - "name": "LLC total HITM per txn (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM] / [TXN]" - }, - { - "name": "LLC total HIT clean line forwards (per instr) (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD] / [instructions]" - }, - { - "name": "LLC total HIT clean line forwards per txn (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD] / [TXN]" - }, - { - "name": "Average LLC demand data read miss latency (in ns)", - "expression": "( 1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) ) ) * 1" - }, - { - "name": "Average LLC demand data read miss latency for LOCAL requests (in ns)", - "expression": "( 1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) ) ) * 1" - }, - { - "name": "Average LLC demand data read miss latency for REMOTE requests (in ns)", - "expression": "( 1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) ) ) * 1" - }, - { - "name": "UPI Data transmit BW (MB/sec) (only data)", - "expression": "([UNC_UPI_TxL_FLITS.ALL_DATA] * (64 / 9.0) / 1000000) / 1" - }, - { - "name": "package power (watts)", - "expression": "[power/energy-pkg/]" - }, - { - "name": "DRAM power (watts)", - "expression": "[power/energy-ram/]" - }, - { - "name": "core c6 residency %", - "expression": "100 * [cstate_core/c6-residency/] / [TSC]" - }, - { - "name": "package c6 residency %", - "expression": "100 * [cstate_pkg/c6-residency/] * [CORES_PER_SOCKET] / [TSC]" - }, - { - "name": "% Uops delivered from decoded Icache (DSB)", - "expression": "100 * ([IDQ.DSB_UOPS] / ([IDQ.DSB_UOPS] + [IDQ.MITE_UOPS] + [IDQ.MS_UOPS] + [LSD.UOPS]) )" - }, - { - "name": "% Uops delivered from legacy decode pipeline (MITE)", - "expression": "100 * ([IDQ.MITE_UOPS] / ([IDQ.DSB_UOPS] + [IDQ.MITE_UOPS] + [IDQ.MS_UOPS] + [LSD.UOPS]) )" - }, - { - "name": "core initiated local dram read bandwidth (MB/sec)", - "expression": "([OCR.READS_TO_CORE.LOCAL_DRAM] + [OCR.HWPF_L3.L3_MISS_LOCAL]) * 64 / 1000000" - }, - { - "name": "core initiated remote dram read bandwidth (MB/sec)", - "expression": "([OCR.READS_TO_CORE.REMOTE_DRAM] + [OCR.HWPF_L3.REMOTE]) * 64 / 1000000" - }, - { - "name": "memory bandwidth read (MB/sec)", - "expression": "([UNC_M_CAS_COUNT.RD] * 64 / 1000000) / 1" - }, - { - "name": "memory bandwidth write (MB/sec)", - "expression": "([UNC_M_CAS_COUNT.WR] * 64 / 1000000) / 1" - }, - { - "name": "memory bandwidth total (MB/sec)", - "expression": "(([UNC_M_CAS_COUNT.RD] + [UNC_M_CAS_COUNT.WR]) * 64 / 1000000) / 1" - }, - { - "name": "ITLB (2nd level) MPI", - "expression": "[ITLB_MISSES.WALK_COMPLETED] / [instructions]" - }, - { - "name": "ITLB (2nd level) misses per txn", - "expression": "[ITLB_MISSES.WALK_COMPLETED] / [TXN]" - }, - { - "name": "DTLB (2nd level) load MPI", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [instructions]" - }, - { - "name": "DTLB (2nd level) load misses per txn", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [TXN]" - }, - { - "name": "DTLB (2nd level) 2MB large page load MPI", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M] / [instructions]" - }, - { - "name": "DTLB (2nd level) 2MB large page load misses per txn", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M] / [TXN]" - }, - { - "name": "DTLB (2nd level) store MPI", - "expression": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [instructions]" - }, - { - "name": "DTLB (2nd level) store misses per txn", - "expression": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [TXN]" - }, - { - "name": "NUMA %_Reads addressed to local DRAM", - "expression": "100 * ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL]) / ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE])" - }, - { - "name": "NUMA %_Reads addressed to remote DRAM", - "expression": "100 * ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE]) / ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE])" - }, - { - "name": "uncore frequency GHz", - "expression": "([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) / 1000000000) / 1" - }, - { - "name": "IO_bandwidth_disk_or_network_writes (MB/sec)", - "expression": "([UNC_CHA_TOR_INSERTS.IO_PCIRDCUR] * 64 / 1000000) / 1" - }, - { - "name": "IO_bandwidth_disk_or_network_reads (MB/sec)", - "expression": "(([UNC_CHA_TOR_INSERTS.IO_ITOM] + [UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR]) * 64 / 1000000) / 1" - }, - { - "name": "TMA_Frontend_Bound(%)", - "expression": "100 * ( ( [IDQ_UOPS_NOT_DELIVERED.CORE] - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS_P] ) )" - }, - { - "name": "TMA_..Fetch_Latency(%)", - "expression": "100 * ( ( [IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE] * ( 6 ) - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS_P] ) )" - }, - { - "name": "TMA_....ICache_Misses(%)", - "expression": "100 * ( [ICACHE_DATA.STALLS] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....ITLB_Misses(%)", - "expression": "100 * ( [ICACHE_TAG.STALLS] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....MS_Switches(%)", - "expression": "100 * ( ( 3 ) * [UOPS_RETIRED.MS:c1:e1] / ( [UOPS_RETIRED.SLOTS] / [UOPS_ISSUED.ANY] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....LCP(%)", - "expression": "100 * ( [DECODE.LCP] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....DSB_Switches(%)", - "expression": "100 * ( [DSB2MITE_SWITCHES.PENALTY_CYCLES] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_..Fetch_Bandwidth(%)", - "expression": "100 * ( max( 0 , ( ( [IDQ_UOPS_NOT_DELIVERED.CORE] - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS_P] ) ) - ( ( [IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE] * ( 6 ) - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS_P] ) ) ) )" - }, - { - "name": "TMA_....MITE(%)", - "expression": "100 * ( ( [IDQ.MITE_CYCLES_ANY] - [IDQ.MITE_CYCLES_OK] ) / ( [CPU_CLK_UNHALTED.DISTRIBUTED] ) / 2 )" - }, - { - "name": "TMA_....DSB(%)", - "expression": "100 * ( ( [IDQ.DSB_CYCLES_ANY] - [IDQ.DSB_CYCLES_OK] ) / ( [CPU_CLK_UNHALTED.DISTRIBUTED] ) / 2 )" - }, - { - "name": "TMA_Bad_Speculation(%)", - "expression": "100 * ( max( 1 - ( ( ( [IDQ_UOPS_NOT_DELIVERED.CORE] - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS_P] ) ) + ( [TOPDOWN.BACKEND_BOUND_SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) + ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) ) , 0 ) )" - }, - { - "name": "TMA_..Branch_Mispredicts(%)", - "expression": "100 * ( [TOPDOWN.BR_MISPREDICT_SLOTS] / ( [TOPDOWN.SLOTS_P] ) )" - }, - { - "name": "TMA_..Machine_Clears(%)", - "expression": "100 * ( max( 0 , ( max( 1 - ( ( ( [IDQ_UOPS_NOT_DELIVERED.CORE] - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS_P] ) ) + ( [TOPDOWN.BACKEND_BOUND_SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) + ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) ) , 0 ) ) - ( [TOPDOWN.BR_MISPREDICT_SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) ) )" - }, - { - "name": "TMA_Backend_Bound(%)", - "expression": "100 * ( [TOPDOWN.BACKEND_BOUND_SLOTS] / ( [TOPDOWN.SLOTS_P] ) )" - }, - { - "name": "TMA_..Memory_Bound(%)", - "expression": "100 * ( [TOPDOWN.MEMORY_BOUND_SLOTS] / ( [TOPDOWN.SLOTS_P] ) )" - }, - { - "name": "TMA_....L1_Bound(%)", - "expression": "100 * ( max( ( [EXE_ACTIVITY.BOUND_ON_LOADS] - [MEMORY_ACTIVITY.STALLS_L1D_MISS] ) / ( [cpu-cycles] ) , 0 ) )" - }, - { - "name": "TMA_....L2_Bound(%)", - "expression": "100 * ( ( [MEMORY_ACTIVITY.STALLS_L1D_MISS] - [MEMORY_ACTIVITY.STALLS_L2_MISS] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....L3_Bound(%)", - "expression": "100 * ( ( [MEMORY_ACTIVITY.STALLS_L2_MISS] - [MEMORY_ACTIVITY.STALLS_L3_MISS] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....DRAM_Bound(%)", - "expression": "100 * ( ( [MEMORY_ACTIVITY.STALLS_L3_MISS] / ( [cpu-cycles] ) ) )" - }, - { - "name": "TMA_....Store_Bound(%)", - "expression": "100 * ( [EXE_ACTIVITY.BOUND_ON_STORES] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_..Core_Bound(%)", - "expression": "100 * ( max( 0 , ( [TOPDOWN.BACKEND_BOUND_SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) - ( [TOPDOWN.MEMORY_BOUND_SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) ) )" - }, - { - "name": "TMA_....Divider(%)", - "expression": "100 * ( [ARITH.DIV_ACTIVE] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....AMX_Busy(%)", - "expression": "100 * ( [EXE.AMX_BUSY] / ( [CPU_CLK_UNHALTED.DISTRIBUTED] ) )" - }, - { - "name": "TMA_Retiring(%)", - "expression": "100 * ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) )" - }, - { - "name": "TMA_..Light_Operations(%)", - "expression": "100 * ( max( 0 , ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) - ( [UOPS_RETIRED.HEAVY] / ( [TOPDOWN.SLOTS_P] ) ) ) )" - }, - { - "name": "TMA_....Memory_Operations(%)", - "expression": "100 * ( ( max( 0 , ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) - ( [UOPS_RETIRED.HEAVY] / ( [TOPDOWN.SLOTS_P] ) ) ) ) * [MEM_UOP_RETIRED.ANY] / ( ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) * ( [TOPDOWN.SLOTS_P] ) ) )" - }, - { - "name": "TMA_....Fused_Instructions(%)", - "expression": "100 * ( ( max( 0 , ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) - ( [UOPS_RETIRED.HEAVY] / ( [TOPDOWN.SLOTS_P] ) ) ) ) * [INST_RETIRED.MACRO_FUSED] / ( ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) * ( [TOPDOWN.SLOTS_P] ) ) )" - }, - { - "name": "TMA_....Non_Fused_Branches(%)", - "expression": "100 * ( ( max( 0 , ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) - ( [UOPS_RETIRED.HEAVY] / ( [TOPDOWN.SLOTS_P] ) ) ) ) * ( [BR_INST_RETIRED.ALL_BRANCHES] - [INST_RETIRED.MACRO_FUSED] ) / ( ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) * ( [TOPDOWN.SLOTS_P] ) ) )" - }, - { - "name": "TMA_..Heavy_Operations(%)", - "expression": "100 * ( [UOPS_RETIRED.HEAVY] / ( [TOPDOWN.SLOTS_P] ) )" - }, - { - "name": "TMA_....Few_Uops_Instructions(%)", - "expression": "100 * ( max( 0 , ( [UOPS_RETIRED.HEAVY] / ( [TOPDOWN.SLOTS_P] ) ) - ( [UOPS_RETIRED.MS] / ( [TOPDOWN.SLOTS_P] ) ) ) )" - }, - { - "name": "TMA_....Microcode_Sequencer(%)", - "expression": "100 * ( [UOPS_RETIRED.MS] / ( [TOPDOWN.SLOTS_P] ) )" - } -] \ No newline at end of file diff --git a/cmd/metrics/resources/metrics/x86_64/GenuineIntel/gnr.json b/cmd/metrics/resources/metrics/x86_64/GenuineIntel/gnr.json deleted file mode 100644 index 91b6de82..00000000 --- a/cmd/metrics/resources/metrics/x86_64/GenuineIntel/gnr.json +++ /dev/null @@ -1,494 +0,0 @@ -[ - { - "name": "CPU operating frequency (in GHz)", - "expression": "([cpu-cycles] / [ref-cycles] * [SYSTEM_TSC_FREQ]) / 1000000000" - }, - { - "name": "CPU utilization %", - "expression": "100 * [ref-cycles] / [TSC]" - }, - { - "name": "CPU utilization% in kernel mode", - "expression": "100 * [ref-cycles:k] / [TSC]" - }, - { - "name": "CPI", - "expression": "[cpu-cycles] / [instructions]" - }, - { - "name": "cycles per txn", - "expression": "[cpu-cycles] / [TXN]" - }, - { - "name": "kernel_CPI", - "expression": "[cpu-cycles:k] / [instructions:k]" - }, - { - "name": "kernel_cycles per txn", - "expression": "[cpu-cycles:k] / [TXN]" - }, - { - "name": "IPC", - "expression": "[instructions] / [cpu-cycles]" - }, - { - "name": "txn per cycle", - "expression": "[TXN] / [cpu-cycles]" - }, - { - "name": "giga_instructions_per_sec", - "expression": "[instructions] / 1000000000" - }, - { - "name": "branch misprediction ratio", - "expression": "[BR_MISP_RETIRED.ALL_BRANCHES] / [BR_INST_RETIRED.ALL_BRANCHES]" - }, - { - "name": "locks retired per instr", - "expression": "[MEM_INST_RETIRED.LOCK_LOADS] / [instructions]" - }, - { - "name": "locks retired per txn", - "expression": "[MEM_INST_RETIRED.LOCK_LOADS] / [TXN]" - }, - { - "name": "L1D MPI (includes data+rfo w/ prefetches)", - "expression": "[L1D.REPLACEMENT] / [instructions]" - }, - { - "name": "L1D misses per txn (includes data+rfo w/ prefetches)", - "expression": "[L1D.REPLACEMENT] / [TXN]" - }, - { - "name": "L1D demand data read hits per instr", - "expression": "[MEM_LOAD_RETIRED.L1_HIT] / [instructions]" - }, - { - "name": "L1D demand data read hits per txn", - "expression": "[MEM_LOAD_RETIRED.L1_HIT] / [TXN]" - }, - { - "name": "L1-I code read misses (w/ prefetches) per instr", - "expression": "[L2_RQSTS.ALL_CODE_RD] / [instructions]" - }, - { - "name": "L1I code read misses (includes prefetches) per txn", - "expression": "[L2_RQSTS.ALL_CODE_RD] / [TXN]" - }, - { - "name": "L2 demand data read hits per instr", - "expression": "[MEM_LOAD_RETIRED.L2_HIT] / [instructions]" - }, - { - "name": "L2 demand data read hits per txn", - "expression": "[MEM_LOAD_RETIRED.L2_HIT] / [TXN]" - }, - { - "name": "L2 MPI (includes code+data+rfo w/ prefetches)", - "expression": "[L2_LINES_IN.ALL] / [instructions]" - }, - { - "name": "L2 misses per txn (includes code+data+rfo w/ prefetches)", - "expression": "[L2_LINES_IN.ALL] / [TXN]" - }, - { - "name": "L2 demand data read MPI", - "expression": "[MEM_LOAD_RETIRED.L2_MISS] / [instructions]" - }, - { - "name": "L2 demand data read misses per txn", - "expression": "[MEM_LOAD_RETIRED.L2_MISS] / [TXN]" - }, - { - "name": "L2 demand code MPI", - "expression": "[L2_RQSTS.CODE_RD_MISS] / [instructions]" - }, - { - "name": "L2 demand code misses per txn", - "expression": "[L2_RQSTS.CODE_RD_MISS] / [TXN]" - }, - { - "name": "LLC code read MPI (demand+prefetch)", - "expression": "[UNC_CHA_TOR_INSERTS.IA_MISS_CRD] / [instructions]" - }, - { - "name": "LLC code read (demand+prefetch) misses per txn", - "expression": "[UNC_CHA_TOR_INSERTS.IA_MISS_CRD] / [TXN]" - }, - { - "name": "LLC data read MPI (demand+prefetch)", - "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF]) / [instructions]" - }, - { - "name": "LLC data read (demand+prefetch) misses per txn", - "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF]) / [TXN]" - }, - { - "name": "LLC total HITM (per instr) (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM] / [instructions]" - }, - { - "name": "LLC total HITM per txn (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM] / [TXN]" - }, - { - "name": "LLC total HIT clean line forwards (per instr) (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD] / [instructions]" - }, - { - "name": "LLC total HIT clean line forwards per txn (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD] / [TXN]" - }, - { - "name": "Average LLC demand data read miss latency (in ns)", - "expression": "1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]))" - }, - { - "name": "Average LLC demand data read miss latency for LOCAL requests (in ns)", - "expression": "1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]))" - }, - { - "name": "Average LLC demand data read miss latency for REMOTE requests (in ns)", - "expression": "1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE]) / ([UNC_CHA_CLOCKTICKS]/([CHAS_PER_SOCKET] * [SOCKET_COUNT]))" - }, - { - "name": "UPI Data transmit BW (MB/sec) (only data)", - "expression": "[UNC_UPI_TxL_FLITS.ALL_DATA] * (64/9.0) / 1000000" - }, - { - "name": "package power (watts)", - "expression": "[power/energy-pkg/]" - }, - { - "name": "DRAM power (watts)", - "expression": "[power/energy-ram/]" - }, - { - "name": "core c6 residency %", - "expression": "100 * [cstate_core/c6-residency/] / [TSC]" - }, - { - "name": "package c6 residency %", - "expression": "100 * [cstate_pkg/c6-residency/] * [CORES_PER_SOCKET] / [TSC]" - }, - { - "name": "% Uops delivered from decoded Icache (DSB)", - "expression": "100 * ([IDQ.DSB_UOPS] / ([IDQ.DSB_UOPS] + [IDQ.MITE_UOPS] + [IDQ.MS_UOPS] + [LSD.UOPS]))" - }, - { - "name": "% Uops delivered from legacy decode pipeline (MITE)", - "expression": "100 * ([IDQ.MITE_UOPS] / ([IDQ.DSB_UOPS] + [IDQ.MITE_UOPS] + [IDQ.MS_UOPS] + [LSD.UOPS]))" - }, - { - "name": "memory bandwidth read (MB/sec)", - "expression": "([UNC_M_CAS_COUNT_SCH0.RD] + [UNC_M_CAS_COUNT_SCH1.RD]) * 64 / 1000000" - }, - { - "name": "memory bandwidth write (MB/sec)", - "expression": "([UNC_M_CAS_COUNT_SCH0.WR] + [UNC_M_CAS_COUNT_SCH1.WR]) * 64 / 1000000" - }, - { - "name": "memory bandwidth total (MB/sec)", - "expression": "([UNC_M_CAS_COUNT_SCH0.RD] + [UNC_M_CAS_COUNT_SCH1.RD] + [UNC_M_CAS_COUNT_SCH0.WR] + [UNC_M_CAS_COUNT_SCH1.WR]) * 64 / 1000000" - }, - { - "name": "ITLB (2nd level) MPI", - "expression": "[ITLB_MISSES.WALK_COMPLETED] / [instructions]" - }, - { - "name": "ITLB (2nd level) misses per txn", - "expression": "[ITLB_MISSES.WALK_COMPLETED] / [TXN]" - }, - { - "name": "DTLB (2nd level) load MPI", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [instructions]" - }, - { - "name": "DTLB (2nd level) load misses per txn", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [TXN]" - }, - { - "name": "DTLB (2nd level) 2MB large page load MPI", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M] / [instructions]" - }, - { - "name": "DTLB (2nd level) 2MB large page load misses per txn", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M] / [TXN]" - }, - { - "name": "DTLB (2nd level) store MPI", - "expression": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [instructions]" - }, - { - "name": "DTLB (2nd level) store misses per txn", - "expression": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [TXN]" - }, - { - "name": "NUMA %_Reads addressed to local DRAM", - "expression": "100 * ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL]) / ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE])" - }, - { - "name": "NUMA %_Reads addressed to remote DRAM", - "expression": "100 * ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE]) / ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE])" - }, - { - "name": "uncore frequency GHz", - "expression": "([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) / 1000000000) / 1" - }, - { - "name": "IO_bandwidth_disk_or_network_writes (MB/sec)", - "expression": "([UNC_CHA_TOR_INSERTS.IO_PCIRDCUR] * 64 / 1000000) / 1" - }, - { - "name": "IO_bandwidth_disk_or_network_reads (MB/sec)", - "expression": "(([UNC_CHA_TOR_INSERTS.IO_ITOM] + [UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR]) * 64 / 1000000) / 1" - }, - { - "name": "TMA_Frontend_Bound(%)", - "expression": "100 * ( [PERF_METRICS.FRONTEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) )" - }, - { - "name": "TMA_..Fetch_Latency(%)", - "expression": "100 * ( ( [PERF_METRICS.FETCH_LATENCY] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) ) )" - }, - { - "name": "TMA_....ICache_Misses(%)", - "expression": "100 * ( [ICACHE_DATA.STALLS] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....ITLB_Misses(%)", - "expression": "100 * ( [ICACHE_TAG.STALLS] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....Branch_Resteers(%)", - "expression": "100 * ( [INT_MISC.CLEAR_RESTEER_CYCLES] / ( [cpu-cycles] ) + ( [INT_MISC.UNKNOWN_BRANCH_CYCLES] / ( [cpu-cycles] ) ) )" - }, - { - "name": "TMA_....MS_Switches(%)", - "expression": "100 * ( ( 3 ) * [UOPS_RETIRED.MS:c1:e1] / ( [UOPS_RETIRED.SLOTS] / [UOPS_ISSUED.ANY] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....LCP(%)", - "expression": "100 * ( [DECODE.LCP] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....DSB_Switches(%)", - "expression": "100 * ( [DSB2MITE_SWITCHES.PENALTY_CYCLES] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_..Fetch_Bandwidth(%)", - "expression": "100 * ( max( 0 , ( [PERF_METRICS.FRONTEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) ) - ( ( [PERF_METRICS.FETCH_LATENCY] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) ) ) ) )" - }, - { - "name": "TMA_....MITE(%)", - "expression": "100 * ( ( [IDQ.MITE_CYCLES_ANY] - [IDQ.MITE_CYCLES_OK] ) / ( [CPU_CLK_UNHALTED.DISTRIBUTED] if [HYPERTHREADING_ON] else ( [cpu-cycles] ) ) / 2 )" - }, - { - "name": "TMA_....DSB(%)", - "expression": "100 * ( ( [IDQ.DSB_CYCLES_ANY] - [IDQ.DSB_CYCLES_OK] ) / ( [CPU_CLK_UNHALTED.DISTRIBUTED] if [HYPERTHREADING_ON] else ( [cpu-cycles] ) ) / 2 )" - }, - { - "name": "TMA_....MS(%)", - "expression": "100 * ( max( [IDQ.MS_CYCLES_ANY] , [UOPS_RETIRED.MS:c1] / ( [UOPS_RETIRED.SLOTS] / [UOPS_ISSUED.ANY] ) ) / ( [CPU_CLK_UNHALTED.DISTRIBUTED] if [HYPERTHREADING_ON] else ( [cpu-cycles] ) ) / 2 )" - }, - { - "name": "TMA_Bad_Speculation(%)", - "expression": "100 * ( max( 1 - ( ( [PERF_METRICS.FRONTEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) ) + ( [PERF_METRICS.BACKEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) , 0 ) )" - }, - { - "name": "TMA_..Branch_Mispredicts(%)", - "expression": "100 * ( [PERF_METRICS.BRANCH_MISPREDICTS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) )" - }, - { - "name": "TMA_....Cond_NT_Mispredicts(%)", - "expression": "100 * ( ( [BR_MISP_RETIRED.COND_NTAKEN_COST] * [BR_MISP_RETIRED.COND_NTAKEN_COST:retire_latency] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....Cond_TK_Mispredicts(%)", - "expression": "100 * ( ( [BR_MISP_RETIRED.COND_TAKEN_COST] * [BR_MISP_RETIRED.COND_TAKEN_COST:retire_latency] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....Ind_Call_Mispredicts(%)", - "expression": "100 * ( ( [BR_MISP_RETIRED.INDIRECT_CALL_COST] * [BR_MISP_RETIRED.INDIRECT_CALL_COST:retire_latency] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....Ind_Jump_Mispredicts(%)", - "expression": "100 * ( max( ( ( [BR_MISP_RETIRED.INDIRECT_COST] * [BR_MISP_RETIRED.INDIRECT_COST:retire_latency] ) - ( [BR_MISP_RETIRED.INDIRECT_CALL_COST] * [BR_MISP_RETIRED.INDIRECT_CALL_COST:retire_latency] ) ) / ( [cpu-cycles] ) , 0 ) )" - }, - { - "name": "TMA_....Ret_Mispredicts(%)", - "expression": "100 * ( ( [BR_MISP_RETIRED.RET_COST] * [BR_MISP_RETIRED.RET_COST:retire_latency] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....Other_Mispredicts(%)", - "expression": "100 * ( max( ( [PERF_METRICS.BRANCH_MISPREDICTS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( 1 - [BR_MISP_RETIRED.ALL_BRANCHES] / ( [INT_MISC.CLEARS_COUNT] - [MACHINE_CLEARS.COUNT] ) ) , 0.0001 ) )" - }, - { - "name": "TMA_..Machine_Clears(%)", - "expression": "100 * ( max( 0 , ( max( 1 - ( ( [PERF_METRICS.FRONTEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) ) + ( [PERF_METRICS.BACKEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) , 0 ) ) - ( [PERF_METRICS.BRANCH_MISPREDICTS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) )" - }, - { - "name": "TMA_....Other_Nukes(%)", - "expression": "100 * ( max( ( max( 0 , ( max( 1 - ( ( [PERF_METRICS.FRONTEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) ) + ( [PERF_METRICS.BACKEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) , 0 ) ) - ( [PERF_METRICS.BRANCH_MISPREDICTS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) ) * ( 1 - [MACHINE_CLEARS.MEMORY_ORDERING] / [MACHINE_CLEARS.COUNT] ) , 0.0001 ) )" - }, - { - "name": "TMA_Backend_Bound(%)", - "expression": "100 * ( [PERF_METRICS.BACKEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) )" - }, - { - "name": "TMA_..Memory_Bound(%)", - "expression": "100 * ( [PERF_METRICS.MEMORY_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) )" - }, - { - "name": "TMA_....L1_Bound(%)", - "expression": "100 * ( max( ( [EXE_ACTIVITY.BOUND_ON_LOADS] - [MEMORY_ACTIVITY.STALLS_L1D_MISS] ) / ( [cpu-cycles] ) , 0 ) )" - }, - { - "name": "TMA_......DTLB_Load(%)", - "expression": "100 * ( ( min( ( [MEM_INST_RETIRED.STLB_HIT_LOADS] * [MEM_INST_RETIRED.STLB_HIT_LOADS:retire_latency] ) , [MEM_INST_RETIRED.STLB_HIT_LOADS] * ( 7 ) ) if ( [MEM_INST_RETIRED.STLB_HIT_LOADS:retire_latency] >= 0 ) else ( [MEM_INST_RETIRED.STLB_HIT_LOADS] * ( 7 ) ) ) / ( [cpu-cycles] ) + ( [DTLB_LOAD_MISSES.WALK_ACTIVE] / ( [cpu-cycles] ) ) )" - }, - { - "name": "TMA_......Store_Fwd_Blk(%)", - "expression": "100 * ( 13 * [LD_BLOCKS.STORE_FORWARD] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......L1_Latency_Dependency(%)", - "expression": "100 * ( min( 2 * ( [MEM_INST_RETIRED.ALL_LOADS] - [MEM_LOAD_RETIRED.FB_HIT] - [MEM_LOAD_RETIRED.L1_MISS] ) * 20 / 100 , max( [CYCLE_ACTIVITY.CYCLES_MEM_ANY] - [MEMORY_ACTIVITY.CYCLES_L1D_MISS] , 0 ) ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Lock_Latency(%)", - "expression": "100 * ( ( [MEM_INST_RETIRED.LOCK_LOADS] * [MEM_INST_RETIRED.LOCK_LOADS:retire_latency] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Split_Loads(%)", - "expression": "100 * ( ( min( ( [MEM_INST_RETIRED.SPLIT_LOADS] * [MEM_INST_RETIRED.SPLIT_LOADS:retire_latency] ) , [MEM_INST_RETIRED.SPLIT_LOADS] * ( [L1D_PEND_MISS.PENDING] / [MEM_LOAD_COMPLETED.L1_MISS_ANY] ) ) if ( [MEM_INST_RETIRED.SPLIT_LOADS:retire_latency] >= 0 ) else ( [MEM_INST_RETIRED.SPLIT_LOADS] * ( [L1D_PEND_MISS.PENDING] / [MEM_LOAD_COMPLETED.L1_MISS_ANY] ) ) ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......FB_Full(%)", - "expression": "100 * ( [L1D_PEND_MISS.FB_FULL] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....L2_Bound(%)", - "expression": "100 * ( ( [MEMORY_ACTIVITY.STALLS_L1D_MISS] - [MEMORY_ACTIVITY.STALLS_L2_MISS] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....L3_Bound(%)", - "expression": "100 * ( ( [MEMORY_ACTIVITY.STALLS_L2_MISS] - [MEMORY_ACTIVITY.STALLS_L3_MISS] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Contested_Accesses(%)", - "expression": "100 * ( ( ( min( ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS] * [MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS:retire_latency] ) , [MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS] * ( 79 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) if ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS:retire_latency] >= 0 ) else ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS] * ( 79 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) ) + ( min( ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD] * [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD:retire_latency] ) , [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD] * ( 81 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) if ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD:retire_latency] >= 0 ) else ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD] * ( 81 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) ) * ( [OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM] / ( [OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM] + [OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD] ) ) ) * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) / 2 ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Data_Sharing(%)", - "expression": "100 * ( ( ( min( ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD] * [MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD:retire_latency] ) , [MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD] * ( 79 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) if ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD:retire_latency] >= 0 ) else ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD] * ( 79 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) ) + ( min( ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD] * [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD:retire_latency] ) , [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD] * ( 79 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) if ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD:retire_latency] >= 0 ) else ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD] * ( 79 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) ) * ( 1 - ( [OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM] / ( [OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM] + [OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD] ) ) ) ) * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) / 2 ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......L3_Hit_Latency(%)", - "expression": "100 * ( ( min( ( [MEM_LOAD_RETIRED.L3_HIT] * [MEM_LOAD_RETIRED.L3_HIT:retire_latency] ) , [MEM_LOAD_RETIRED.L3_HIT] * ( 37 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) if ( [MEM_LOAD_RETIRED.L3_HIT:retire_latency] >= 0 ) else ( [MEM_LOAD_RETIRED.L3_HIT] * ( 37 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) ) * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) / 2 ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......SQ_Full(%)", - "expression": "100 * ( ( [XQ.FULL_CYCLES] + [L1D_PEND_MISS.L2_STALLS] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....DRAM_Bound(%)", - "expression": "100 * ( ( [MEMORY_ACTIVITY.STALLS_L3_MISS] / ( [cpu-cycles] ) ) )" - }, - { - "name": "TMA_......MEM_Bandwidth(%)", - "expression": "100 * ( ( min( [cpu-cycles] , [OFFCORE_REQUESTS_OUTSTANDING.DATA_RD:c4] ) ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......MEM_Latency(%)", - "expression": "100 * ( ( min( [cpu-cycles] , [OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD] ) ) / ( [cpu-cycles] ) - ( ( min( [cpu-cycles] , [OFFCORE_REQUESTS_OUTSTANDING.DATA_RD:c4] ) ) / ( [cpu-cycles] ) ) )" - }, - { - "name": "TMA_....Store_Bound(%)", - "expression": "100 * ( [EXE_ACTIVITY.BOUND_ON_STORES] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Store_Latency(%)", - "expression": "100 * ( ( ( [MEM_STORE_RETIRED.L2_HIT] * ( 10 ) * ( 1 - ( [MEM_INST_RETIRED.LOCK_LOADS] / [MEM_INST_RETIRED.ALL_STORES] ) ) ) + ( 1 - ( [MEM_INST_RETIRED.LOCK_LOADS] / [MEM_INST_RETIRED.ALL_STORES] ) ) * ( min( [cpu-cycles] , [OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO] ) ) ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......False_Sharing(%)", - "expression": "100 * ( ( ( 170 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) * [OCR.DEMAND_RFO.L3_MISS] + ( 81 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) * [OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Split_Stores(%)", - "expression": "100 * ( ( min( ( [MEM_INST_RETIRED.SPLIT_STORES] * [MEM_INST_RETIRED.SPLIT_STORES:retire_latency] ) , [MEM_INST_RETIRED.SPLIT_STORES] * 1 ) if ( [MEM_INST_RETIRED.SPLIT_STORES:retire_latency] >= 0 ) else ( [MEM_INST_RETIRED.SPLIT_STORES] * 1 ) ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Streaming_Stores(%)", - "expression": "100 * ( 9 * [OCR.STREAMING_WR.ANY_RESPONSE] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......DTLB_Store(%)", - "expression": "100 * ( ( min( ( [MEM_INST_RETIRED.STLB_HIT_STORES] * [MEM_INST_RETIRED.STLB_HIT_STORES:retire_latency] ) , [MEM_INST_RETIRED.STLB_HIT_STORES] * ( 7 ) ) if ( [MEM_INST_RETIRED.STLB_HIT_STORES:retire_latency] >= 0 ) else ( [MEM_INST_RETIRED.STLB_HIT_STORES] * ( 7 ) ) ) / ( [cpu-cycles] ) + ( [DTLB_STORE_MISSES.WALK_ACTIVE] / ( [CPU_CLK_UNHALTED.DISTRIBUTED] if [HYPERTHREADING_ON] else ( [cpu-cycles] ) ) ) )" - }, - { - "name": "TMA_..Core_Bound(%)", - "expression": "100 * ( max( 0 , ( [PERF_METRICS.BACKEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) - ( [PERF_METRICS.MEMORY_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) )" - }, - { - "name": "TMA_....Divider(%)", - "expression": "100 * ( [ARITH.DIV_ACTIVE] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....Serializing_Operation(%)", - "expression": "100 * ( [RESOURCE_STALLS.SCOREBOARD] / ( [cpu-cycles] ) + ( [CPU_CLK_UNHALTED.C02] / ( [cpu-cycles] ) ) )" - }, - { - "name": "TMA_....AMX_Busy(%)", - "expression": "100 * ( [EXE.AMX_BUSY] / ( [CPU_CLK_UNHALTED.DISTRIBUTED] if [HYPERTHREADING_ON] else ( [cpu-cycles] ) ) )" - }, - { - "name": "TMA_....Ports_Utilization(%)", - "expression": "100 * ( ( ( max( [EXE_ACTIVITY.EXE_BOUND_0_PORTS] - [RESOURCE_STALLS.SCOREBOARD] , 0 ) / ( [cpu-cycles] ) ) * ( [cpu-cycles] ) + ( [EXE_ACTIVITY.1_PORTS_UTIL] + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * [EXE_ACTIVITY.2_3_PORTS_UTIL] ) ) / ( [cpu-cycles] ) if ( [ARITH.DIV_ACTIVE] < ( [CYCLE_ACTIVITY.STALLS_TOTAL] - [EXE_ACTIVITY.BOUND_ON_LOADS] ) ) else ( [EXE_ACTIVITY.1_PORTS_UTIL] + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * [EXE_ACTIVITY.2_3_PORTS_UTIL] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_Retiring(%)", - "expression": "100 * ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) )" - }, - { - "name": "TMA_..Light_Operations(%)", - "expression": "100 * ( max( 0 , ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) - ( [PERF_METRICS.HEAVY_OPERATIONS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) )" - }, - { - "name": "TMA_....FP_Arith(%)", - "expression": "100 * ( ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * [UOPS_EXECUTED.X87] / [UOPS_EXECUTED.THREAD] ) + ( ( [FP_ARITH_INST_RETIRED.SCALAR] + [FP_ARITH_INST_RETIRED2.SCALAR] ) / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) ) + ( ( [FP_ARITH_INST_RETIRED.VECTOR] + [FP_ARITH_INST_RETIRED2.VECTOR] ) / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) ) )" - }, - { - "name": "TMA_....Int_Operations(%)", - "expression": "100 * ( ( ( [INT_VEC_RETIRED.ADD_128] + [INT_VEC_RETIRED.VNNI_128] ) / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) ) + ( ( [INT_VEC_RETIRED.ADD_256] + [INT_VEC_RETIRED.MUL_256] + [INT_VEC_RETIRED.VNNI_256] ) / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) ) )" - }, - { - "name": "TMA_....Memory_Operations(%)", - "expression": "100 * ( ( max( 0 , ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) - ( [PERF_METRICS.HEAVY_OPERATIONS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) ) * [MEM_UOP_RETIRED.ANY] / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) )" - }, - { - "name": "TMA_....Fused_Instructions(%)", - "expression": "100 * ( ( max( 0 , ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) - ( [PERF_METRICS.HEAVY_OPERATIONS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) ) * [INST_RETIRED.MACRO_FUSED] / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) )" - }, - { - "name": "TMA_....Non_Fused_Branches(%)", - "expression": "100 * ( ( max( 0 , ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) - ( [PERF_METRICS.HEAVY_OPERATIONS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) ) * ( [BR_INST_RETIRED.ALL_BRANCHES] - [INST_RETIRED.MACRO_FUSED] ) / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) )" - }, - { - "name": "TMA_....Other_Light_Ops(%)", - "expression": "100 * ( max( 0 , ( max( 0 , ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) - ( [PERF_METRICS.HEAVY_OPERATIONS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) ) - ( ( ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * [UOPS_EXECUTED.X87] / [UOPS_EXECUTED.THREAD] ) + ( ( [FP_ARITH_INST_RETIRED.SCALAR] + [FP_ARITH_INST_RETIRED2.SCALAR] ) / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) ) + ( ( [FP_ARITH_INST_RETIRED.VECTOR] + [FP_ARITH_INST_RETIRED2.VECTOR] ) / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) ) ) + ( ( ( [INT_VEC_RETIRED.ADD_128] + [INT_VEC_RETIRED.VNNI_128] ) / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) ) + ( ( [INT_VEC_RETIRED.ADD_256] + [INT_VEC_RETIRED.MUL_256] + [INT_VEC_RETIRED.VNNI_256] ) / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) ) ) + ( ( max( 0 , ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) - ( [PERF_METRICS.HEAVY_OPERATIONS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) ) * [MEM_UOP_RETIRED.ANY] / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) ) + ( ( max( 0 , ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) - ( [PERF_METRICS.HEAVY_OPERATIONS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) ) * [INST_RETIRED.MACRO_FUSED] / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) ) + ( ( max( 0 , ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) - ( [PERF_METRICS.HEAVY_OPERATIONS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) ) * ( [BR_INST_RETIRED.ALL_BRANCHES] - [INST_RETIRED.MACRO_FUSED] ) / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) ) ) ) )" - }, - { - "name": "TMA_..Heavy_Operations(%)", - "expression": "100 * ( [PERF_METRICS.HEAVY_OPERATIONS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) )" - }, - { - "name": "TMA_....Few_Uops_Instructions(%)", - "expression": "100 * ( max( 0 , ( [PERF_METRICS.HEAVY_OPERATIONS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) - ( [UOPS_RETIRED.MS] / ( [TOPDOWN.SLOTS] ) ) ) )" - }, - { - "name": "TMA_....Microcode_Sequencer(%)", - "expression": "100 * ( [UOPS_RETIRED.MS] / ( [TOPDOWN.SLOTS] ) )" - } -] \ No newline at end of file diff --git a/cmd/metrics/resources/metrics/x86_64/GenuineIntel/gnr_nofixedtma.json b/cmd/metrics/resources/metrics/x86_64/GenuineIntel/gnr_nofixedtma.json deleted file mode 100644 index ee2c1ce5..00000000 --- a/cmd/metrics/resources/metrics/x86_64/GenuineIntel/gnr_nofixedtma.json +++ /dev/null @@ -1,478 +0,0 @@ -[ - { - "name": "CPU operating frequency (in GHz)", - "expression": "([cpu-cycles] / [ref-cycles] * [SYSTEM_TSC_FREQ]) / 1000000000" - }, - { - "name": "CPU utilization %", - "expression": "100 * [ref-cycles] / [TSC]" - }, - { - "name": "CPU utilization% in kernel mode", - "expression": "100 * [ref-cycles:k] / [TSC]" - }, - { - "name": "CPI", - "expression": "[cpu-cycles] / [instructions]" - }, - { - "name": "cycles per txn", - "expression": "[cpu-cycles] / [TXN]" - }, - { - "name": "kernel_CPI", - "expression": "[cpu-cycles:k] / [instructions:k]" - }, - { - "name": "kernel_cycles per txn", - "expression": "[cpu-cycles:k] / [TXN]" - }, - { - "name": "IPC", - "expression": "[instructions] / [cpu-cycles]" - }, - { - "name": "txn per cycle", - "expression": "[TXN] / [cpu-cycles]" - }, - { - "name": "giga_instructions_per_sec", - "expression": "[instructions] / 1000000000" - }, - { - "name": "branch misprediction ratio", - "expression": "[BR_MISP_RETIRED.ALL_BRANCHES] / [BR_INST_RETIRED.ALL_BRANCHES]" - }, - { - "name": "locks retired per instr", - "expression": "[MEM_INST_RETIRED.LOCK_LOADS] / [instructions]" - }, - { - "name": "locks retired per txn", - "expression": "[MEM_INST_RETIRED.LOCK_LOADS] / [TXN]" - }, - { - "name": "L1D MPI (includes data+rfo w/ prefetches)", - "expression": "[L1D.REPLACEMENT] / [instructions]" - }, - { - "name": "L1D misses per txn (includes data+rfo w/ prefetches)", - "expression": "[L1D.REPLACEMENT] / [TXN]" - }, - { - "name": "L1D demand data read hits per instr", - "expression": "[MEM_LOAD_RETIRED.L1_HIT] / [instructions]" - }, - { - "name": "L1D demand data read hits per txn", - "expression": "[MEM_LOAD_RETIRED.L1_HIT] / [TXN]" - }, - { - "name": "L1-I code read misses (w/ prefetches) per instr", - "expression": "[L2_RQSTS.ALL_CODE_RD] / [instructions]" - }, - { - "name": "L1I code read misses (includes prefetches) per txn", - "expression": "[L2_RQSTS.ALL_CODE_RD] / [TXN]" - }, - { - "name": "L2 demand data read hits per instr", - "expression": "[MEM_LOAD_RETIRED.L2_HIT] / [instructions]" - }, - { - "name": "L2 demand data read hits per txn", - "expression": "[MEM_LOAD_RETIRED.L2_HIT] / [TXN]" - }, - { - "name": "L2 MPI (includes code+data+rfo w/ prefetches)", - "expression": "[L2_LINES_IN.ALL] / [instructions]" - }, - { - "name": "L2 misses per txn (includes code+data+rfo w/ prefetches)", - "expression": "[L2_LINES_IN.ALL] / [TXN]" - }, - { - "name": "L2 demand data read MPI", - "expression": "[MEM_LOAD_RETIRED.L2_MISS] / [instructions]" - }, - { - "name": "L2 demand data read misses per txn", - "expression": "[MEM_LOAD_RETIRED.L2_MISS] / [TXN]" - }, - { - "name": "L2 demand code MPI", - "expression": "[L2_RQSTS.CODE_RD_MISS] / [instructions]" - }, - { - "name": "L2 demand code misses per txn", - "expression": "[L2_RQSTS.CODE_RD_MISS] / [TXN]" - }, - { - "name": "LLC code read MPI (demand+prefetch)", - "expression": "[UNC_CHA_TOR_INSERTS.IA_MISS_CRD] / [instructions]" - }, - { - "name": "LLC code read (demand+prefetch) misses per txn", - "expression": "[UNC_CHA_TOR_INSERTS.IA_MISS_CRD] / [TXN]" - }, - { - "name": "LLC data read MPI (demand+prefetch)", - "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF]) / [instructions]" - }, - { - "name": "LLC data read (demand+prefetch) misses per txn", - "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF]) / [TXN]" - }, - { - "name": "LLC total HITM (per instr) (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM] / [instructions]" - }, - { - "name": "LLC total HITM per txn (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM] / [TXN]" - }, - { - "name": "LLC total HIT clean line forwards (per instr) (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD] / [instructions]" - }, - { - "name": "LLC total HIT clean line forwards per txn (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD] / [TXN]" - }, - { - "name": "Average LLC demand data read miss latency (in ns)", - "expression": "1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]))" - }, - { - "name": "Average LLC demand data read miss latency for LOCAL requests (in ns)", - "expression": "1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]))" - }, - { - "name": "Average LLC demand data read miss latency for REMOTE requests (in ns)", - "expression": "1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE]) / ([UNC_CHA_CLOCKTICKS]/([CHAS_PER_SOCKET] * [SOCKET_COUNT]))" - }, - { - "name": "UPI Data transmit BW (MB/sec) (only data)", - "expression": "[UNC_UPI_TxL_FLITS.ALL_DATA] * (64/9.0) / 1000000" - }, - { - "name": "package power (watts)", - "expression": "[power/energy-pkg/]" - }, - { - "name": "DRAM power (watts)", - "expression": "[power/energy-ram/]" - }, - { - "name": "core c6 residency %", - "expression": "100 * [cstate_core/c6-residency/] / [TSC]" - }, - { - "name": "package c6 residency %", - "expression": "100 * [cstate_pkg/c6-residency/] * [CORES_PER_SOCKET] / [TSC]" - }, - { - "name": "% Uops delivered from decoded Icache (DSB)", - "expression": "100 * ([IDQ.DSB_UOPS] / ([IDQ.DSB_UOPS] + [IDQ.MITE_UOPS] + [IDQ.MS_UOPS] + [LSD.UOPS]))" - }, - { - "name": "% Uops delivered from legacy decode pipeline (MITE)", - "expression": "100 * ([IDQ.MITE_UOPS] / ([IDQ.DSB_UOPS] + [IDQ.MITE_UOPS] + [IDQ.MS_UOPS] + [LSD.UOPS]))" - }, - { - "name": "memory bandwidth read (MB/sec)", - "expression": "([UNC_M_CAS_COUNT_SCH0.RD] + [UNC_M_CAS_COUNT_SCH1.RD]) * 64 / 1000000" - }, - { - "name": "memory bandwidth write (MB/sec)", - "expression": "([UNC_M_CAS_COUNT_SCH0.WR] + [UNC_M_CAS_COUNT_SCH1.WR]) * 64 / 1000000" - }, - { - "name": "memory bandwidth total (MB/sec)", - "expression": "([UNC_M_CAS_COUNT_SCH0.RD] + [UNC_M_CAS_COUNT_SCH1.RD] + [UNC_M_CAS_COUNT_SCH0.WR] + [UNC_M_CAS_COUNT_SCH1.WR]) * 64 / 1000000" - }, - { - "name": "ITLB (2nd level) MPI", - "expression": "[ITLB_MISSES.WALK_COMPLETED] / [instructions]" - }, - { - "name": "ITLB (2nd level) misses per txn", - "expression": "[ITLB_MISSES.WALK_COMPLETED] / [TXN]" - }, - { - "name": "DTLB (2nd level) load MPI", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [instructions]" - }, - { - "name": "DTLB (2nd level) load misses per txn", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [TXN]" - }, - { - "name": "DTLB (2nd level) 2MB large page load MPI", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M] / [instructions]" - }, - { - "name": "DTLB (2nd level) 2MB large page load misses per txn", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M] / [TXN]" - }, - { - "name": "DTLB (2nd level) store MPI", - "expression": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [instructions]" - }, - { - "name": "DTLB (2nd level) store misses per txn", - "expression": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [TXN]" - }, - { - "name": "NUMA %_Reads addressed to local DRAM", - "expression": "100 * ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL]) / ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE])" - }, - { - "name": "NUMA %_Reads addressed to remote DRAM", - "expression": "100 * ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE]) / ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE])" - }, - { - "name": "uncore frequency GHz", - "expression": "([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) / 1000000000) / 1" - }, - { - "name": "IO_bandwidth_disk_or_network_writes (MB/sec)", - "expression": "([UNC_CHA_TOR_INSERTS.IO_PCIRDCUR] * 64 / 1000000) / 1" - }, - { - "name": "IO_bandwidth_disk_or_network_reads (MB/sec)", - "expression": "(([UNC_CHA_TOR_INSERTS.IO_ITOM] + [UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR]) * 64 / 1000000) / 1" - }, - { - "name": "TMA_Frontend_Bound(%)", - "expression": "100 * ( ( [IDQ_BUBBLES.CORE] - [INT_MISC.UOP_DROPPING] ) / [TOPDOWN.SLOTS_P] )" - }, - { - "name": "TMA_..Fetch_Latency(%)", - "expression": "100 * ( ( [IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE] * ( 6 ) - [INT_MISC.UOP_DROPPING] ) / [TOPDOWN.SLOTS_P] )" - }, - { - "name": "TMA_....ICache_Misses(%)", - "expression": "100 * ( [ICACHE_DATA.STALLS] / [cpu-cycles] )" - }, - { - "name": "TMA_....ITLB_Misses(%)", - "expression": "100 * ( [ICACHE_TAG.STALLS] / [cpu-cycles] )" - }, - { - "name": "TMA_....Branch_Resteers(%)", - "expression": "100 * ( [INT_MISC.CLEAR_RESTEER_CYCLES] / [cpu-cycles] + ( [INT_MISC.UNKNOWN_BRANCH_CYCLES] / [cpu-cycles] ) )" - }, - { - "name": "TMA_....MS_Switches(%)", - "expression": "100 * ( ( 3 ) * [UOPS_RETIRED.MS:c1:e1] / ( [UOPS_RETIRED.SLOTS] / [UOPS_ISSUED.ANY] ) / [cpu-cycles] )" - }, - { - "name": "TMA_....LCP(%)", - "expression": "100 * ( [DECODE.LCP] / [cpu-cycles] )" - }, - { - "name": "TMA_....DSB_Switches(%)", - "expression": "100 * ( [DSB2MITE_SWITCHES.PENALTY_CYCLES] / [cpu-cycles] )" - }, - { - "name": "TMA_..Fetch_Bandwidth(%)", - "expression": "100 * ( max( 0 , ( ( [IDQ_BUBBLES.CORE] - [INT_MISC.UOP_DROPPING] ) / [TOPDOWN.SLOTS_P] ) - ( ( [IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE] * ( 6 ) - [INT_MISC.UOP_DROPPING] ) / [TOPDOWN.SLOTS_P] ) ) )" - }, - { - "name": "TMA_....MITE(%)", - "expression": "100 * ( ( [IDQ.MITE_CYCLES_ANY] - [IDQ.MITE_CYCLES_OK] ) / ( [CPU_CLK_UNHALTED.DISTRIBUTED] if [HYPERTHREADING_ON] else [cpu-cycles] ) / 2 )" - }, - { - "name": "TMA_....DSB(%)", - "expression": "100 * ( ( [IDQ.DSB_CYCLES_ANY] - [IDQ.DSB_CYCLES_OK] ) / ( [CPU_CLK_UNHALTED.DISTRIBUTED] if [HYPERTHREADING_ON] else [cpu-cycles] ) / 2 )" - }, - { - "name": "TMA_....MS(%)", - "expression": "100 * ( max( [IDQ.MS_CYCLES_ANY] , [UOPS_RETIRED.MS:c1] / ( [UOPS_RETIRED.SLOTS] / [UOPS_ISSUED.ANY] ) ) / ( [CPU_CLK_UNHALTED.DISTRIBUTED] if [HYPERTHREADING_ON] else [cpu-cycles] ) / 2 )" - }, - { - "name": "TMA_Bad_Speculation(%)", - "expression": "100 * ( max( 1 - ( ( ( [IDQ_BUBBLES.CORE] - [INT_MISC.UOP_DROPPING] ) / [TOPDOWN.SLOTS_P] ) + ( [TOPDOWN.BACKEND_BOUND_SLOTS] / [TOPDOWN.SLOTS_P] ) + ( [UOPS_RETIRED.SLOTS] / [TOPDOWN.SLOTS_P] ) ) , 0 ) )" - }, - { - "name": "TMA_..Branch_Mispredicts(%)", - "expression": "100 * ( [TOPDOWN.BR_MISPREDICT_SLOTS] / [TOPDOWN.SLOTS_P] )" - }, - { - "name": "TMA_....Cond_NT_Mispredicts(%)", - "expression": "100 * ( ( [BR_MISP_RETIRED.COND_NTAKEN_COST] * [BR_MISP_RETIRED.COND_NTAKEN_COST:retire_latency] ) / [cpu-cycles] )" - }, - { - "name": "TMA_....Cond_TK_Mispredicts(%)", - "expression": "100 * ( ( [BR_MISP_RETIRED.COND_TAKEN_COST] * [BR_MISP_RETIRED.COND_TAKEN_COST:retire_latency] ) / [cpu-cycles] )" - }, - { - "name": "TMA_....Ind_Call_Mispredicts(%)", - "expression": "100 * ( ( [BR_MISP_RETIRED.INDIRECT_CALL_COST] * [BR_MISP_RETIRED.INDIRECT_CALL_COST:retire_latency] ) / [cpu-cycles] )" - }, - { - "name": "TMA_....Ind_Jump_Mispredicts(%)", - "expression": "100 * ( max( ( ( [BR_MISP_RETIRED.INDIRECT_COST] * [BR_MISP_RETIRED.INDIRECT_COST:retire_latency] ) - ( [BR_MISP_RETIRED.INDIRECT_CALL_COST] * [BR_MISP_RETIRED.INDIRECT_CALL_COST:retire_latency] ) ) / [cpu-cycles] , 0 ) )" - }, - { - "name": "TMA_....Ret_Mispredicts(%)", - "expression": "100 * ( ( [BR_MISP_RETIRED.RET_COST] * [BR_MISP_RETIRED.RET_COST:retire_latency] ) / [cpu-cycles] )" - }, - { - "name": "TMA_....Other_Mispredicts(%)", - "expression": "max( ( 100 * ( [TOPDOWN.BR_MISPREDICT_SLOTS] / [TOPDOWN.SLOTS_P] ) ) * ( 1 - [BR_MISP_RETIRED.ALL_BRANCHES] / ( [INT_MISC.CLEARS_COUNT] - [MACHINE_CLEARS.COUNT] ) ) , 0.0001 )" - }, - { - "name": "TMA_..Machine_Clears(%)", - "expression": "100 * ( max( 0 , ( max( 1 - ( ( ( [IDQ_BUBBLES.CORE] - [INT_MISC.UOP_DROPPING] ) / [TOPDOWN.SLOTS_P] ) + ( [TOPDOWN.BACKEND_BOUND_SLOTS] / [TOPDOWN.SLOTS_P] ) + ( [UOPS_RETIRED.SLOTS] / [TOPDOWN.SLOTS_P] ) ) , 0 ) ) - ( [TOPDOWN.BR_MISPREDICT_SLOTS] / [TOPDOWN.SLOTS_P] ) ) )" - }, - { - "name": "TMA_....Other_Nukes(%)", - "expression": "max ( ( 100 * ( max( 0 , ( max( 1 - ( ( ( [IDQ_BUBBLES.CORE] - [INT_MISC.UOP_DROPPING] ) / [TOPDOWN.SLOTS_P] ) + ( [TOPDOWN.BACKEND_BOUND_SLOTS] / [TOPDOWN.SLOTS_P] ) + ( [UOPS_RETIRED.SLOTS] / [TOPDOWN.SLOTS_P] ) ) , 0 ) ) - ( [TOPDOWN.BR_MISPREDICT_SLOTS] / [TOPDOWN.SLOTS_P] ) ) ) ) * ( 1 - [MACHINE_CLEARS.MEMORY_ORDERING] / [MACHINE_CLEARS.COUNT] ), 0.0001 )" - }, - { - "name": "TMA_Backend_Bound(%)", - "expression": "100 * ( [TOPDOWN.BACKEND_BOUND_SLOTS] / [TOPDOWN.SLOTS_P] )" - }, - { - "name": "TMA_..Memory_Bound(%)", - "expression": "100 * ( [TOPDOWN.MEMORY_BOUND_SLOTS] / [TOPDOWN.SLOTS_P] )" - }, - { - "name": "TMA_....L1_Bound(%)", - "expression": "100 * ( max( ( [EXE_ACTIVITY.BOUND_ON_LOADS] - [MEMORY_ACTIVITY.STALLS_L1D_MISS] ) / [cpu-cycles] , 0 ) )" - }, - { - "name": "TMA_......DTLB_Load(%)", - "expression": "100 * ( ( min( ( [MEM_INST_RETIRED.STLB_HIT_LOADS] * [MEM_INST_RETIRED.STLB_HIT_LOADS:retire_latency] ) , [MEM_INST_RETIRED.STLB_HIT_LOADS] * ( 7 ) ) if ( [MEM_INST_RETIRED.STLB_HIT_LOADS:retire_latency] >= 0 ) else ( [MEM_INST_RETIRED.STLB_HIT_LOADS] * ( 7 ) ) ) / [cpu-cycles] + ( [DTLB_LOAD_MISSES.WALK_ACTIVE] / [cpu-cycles] ) )" - }, - { - "name": "TMA_......Store_Fwd_Blk(%)", - "expression": "100 * ( 13 * [LD_BLOCKS.STORE_FORWARD] / [cpu-cycles] )" - }, - { - "name": "TMA_......L1_Latency_Dependency(%)", - "expression": "100 * ( min( 2 * ( [MEM_INST_RETIRED.ALL_LOADS] - [MEM_LOAD_RETIRED.FB_HIT] - [MEM_LOAD_RETIRED.L1_MISS] ) * 20 / 100 , max( [CYCLE_ACTIVITY.CYCLES_MEM_ANY] - [MEMORY_ACTIVITY.CYCLES_L1D_MISS] , 0 ) ) / [cpu-cycles] )" - }, - { - "name": "TMA_......Lock_Latency(%)", - "expression": "100 * ( ( [MEM_INST_RETIRED.LOCK_LOADS] * [MEM_INST_RETIRED.LOCK_LOADS:retire_latency] ) / [cpu-cycles] )" - }, - { - "name": "TMA_......Split_Loads(%)", - "expression": "100 * ( ( min( ( [MEM_INST_RETIRED.SPLIT_LOADS] * [MEM_INST_RETIRED.SPLIT_LOADS:retire_latency] ) , [MEM_INST_RETIRED.SPLIT_LOADS] * ( [L1D_PEND_MISS.PENDING] / [MEM_LOAD_COMPLETED.L1_MISS_ANY] ) ) if ( [MEM_INST_RETIRED.SPLIT_LOADS:retire_latency] >= 0 ) else ( [MEM_INST_RETIRED.SPLIT_LOADS] * ( [L1D_PEND_MISS.PENDING] / [MEM_LOAD_COMPLETED.L1_MISS_ANY] ) ) ) / [cpu-cycles] )" - }, - { - "name": "TMA_......FB_Full(%)", - "expression": "100 * ( [L1D_PEND_MISS.FB_FULL] / [cpu-cycles] )" - }, - { - "name": "TMA_....L2_Bound(%)", - "expression": "100 * ( ( [MEMORY_ACTIVITY.STALLS_L1D_MISS] - [MEMORY_ACTIVITY.STALLS_L2_MISS] ) / [cpu-cycles] )" - }, - { - "name": "TMA_....L3_Bound(%)", - "expression": "100 * ( ( [MEMORY_ACTIVITY.STALLS_L2_MISS] - [MEMORY_ACTIVITY.STALLS_L3_MISS] ) / [cpu-cycles] )" - }, - { - "name": "TMA_......Contested_Accesses(%)", - "expression": "100 * ( ( ( min( ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS] * [MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS:retire_latency] ) , [MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS] * ( 79 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) if ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS:retire_latency] >= 0 ) else ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS] * ( 79 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) ) + ( min( ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD] * [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD:retire_latency] ) , [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD] * ( 81 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) if ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD:retire_latency] >= 0 ) else ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD] * ( 81 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) ) * ( [OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM] / ( [OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM] + [OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD] ) ) ) * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) / 2 ) / [cpu-cycles] )" - }, - { - "name": "TMA_......Data_Sharing(%)", - "expression": "100 * ( ( ( min( ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD] * [MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD:retire_latency] ) , [MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD] * ( 79 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) if ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD:retire_latency] >= 0 ) else ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD] * ( 79 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) ) + ( min( ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD] * [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD:retire_latency] ) , [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD] * ( 79 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) if ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD:retire_latency] >= 0 ) else ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD] * ( 79 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) ) * ( 1 - ( [OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM] / ( [OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM] + [OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD] ) ) ) ) * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) / 2 ) / [cpu-cycles] )" - }, - { - "name": "TMA_......L3_Hit_Latency(%)", - "expression": "100 * ( ( min( ( [MEM_LOAD_RETIRED.L3_HIT] * [MEM_LOAD_RETIRED.L3_HIT:retire_latency] ) , [MEM_LOAD_RETIRED.L3_HIT] * ( 37 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) if ( [MEM_LOAD_RETIRED.L3_HIT:retire_latency] >= 0 ) else ( [MEM_LOAD_RETIRED.L3_HIT] * ( 37 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) ) * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) / 2 ) / [cpu-cycles] )" - }, - { - "name": "TMA_......SQ_Full(%)", - "expression": "100 * ( ( [XQ.FULL_CYCLES] + [L1D_PEND_MISS.L2_STALLS] ) / [cpu-cycles] )" - }, - { - "name": "TMA_....DRAM_Bound(%)", - "expression": "100 * ( ( [MEMORY_ACTIVITY.STALLS_L3_MISS] / [cpu-cycles] ) )" - }, - { - "name": "TMA_......MEM_Bandwidth(%)", - "expression": "100 * ( ( min( [cpu-cycles] , [OFFCORE_REQUESTS_OUTSTANDING.DATA_RD:c4] ) ) / [cpu-cycles] )" - }, - { - "name": "TMA_......MEM_Latency(%)", - "expression": "100 * ( ( min( [cpu-cycles] , [OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD] ) ) / [cpu-cycles] - ( ( min( [cpu-cycles] , [OFFCORE_REQUESTS_OUTSTANDING.DATA_RD:c4] ) ) / [cpu-cycles] ) )" - }, - { - "name": "TMA_....Store_Bound(%)", - "expression": "100 * ( [EXE_ACTIVITY.BOUND_ON_STORES] / [cpu-cycles] )" - }, - { - "name": "TMA_......Store_Latency(%)", - "expression": "100 * ( ( ( [MEM_STORE_RETIRED.L2_HIT] * ( 10 ) * ( 1 - ( [MEM_INST_RETIRED.LOCK_LOADS] / [MEM_INST_RETIRED.ALL_STORES] ) ) ) + ( 1 - ( [MEM_INST_RETIRED.LOCK_LOADS] / [MEM_INST_RETIRED.ALL_STORES] ) ) * ( min( [cpu-cycles] , [OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO] ) ) ) / [cpu-cycles] )" - }, - { - "name": "TMA_......False_Sharing(%)", - "expression": "100 * ( ( ( 170 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) * [OCR.DEMAND_RFO.L3_MISS] + ( 81 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) * [OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM] ) / [cpu-cycles] )" - }, - { - "name": "TMA_......Split_Stores(%)", - "expression": "100 * ( ( min( ( [MEM_INST_RETIRED.SPLIT_STORES] * [MEM_INST_RETIRED.SPLIT_STORES:retire_latency] ) , [MEM_INST_RETIRED.SPLIT_STORES] * 1 ) if ( [MEM_INST_RETIRED.SPLIT_STORES:retire_latency] >= 0 ) else ( [MEM_INST_RETIRED.SPLIT_STORES] * 1 ) ) / [cpu-cycles] )" - }, - { - "name": "TMA_......Streaming_Stores(%)", - "expression": "100 * ( 9 * [OCR.STREAMING_WR.ANY_RESPONSE] / [cpu-cycles] )" - }, - { - "name": "TMA_......DTLB_Store(%)", - "expression": "100 * ( ( min( ( [MEM_INST_RETIRED.STLB_HIT_STORES] * [MEM_INST_RETIRED.STLB_HIT_STORES:retire_latency] ) , [MEM_INST_RETIRED.STLB_HIT_STORES] * ( 7 ) ) if ( [MEM_INST_RETIRED.STLB_HIT_STORES:retire_latency] >= 0 ) else ( [MEM_INST_RETIRED.STLB_HIT_STORES] * ( 7 ) ) ) / [cpu-cycles] + ( [DTLB_STORE_MISSES.WALK_ACTIVE] / ( [CPU_CLK_UNHALTED.DISTRIBUTED] if [HYPERTHREADING_ON] else [cpu-cycles] ) ) )" - }, - { - "name": "TMA_..Core_Bound(%)", - "expression": "100 * max( 0 , ( [TOPDOWN.BACKEND_BOUND_SLOTS] / [TOPDOWN.SLOTS_P] ) - ( [TOPDOWN.MEMORY_BOUND_SLOTS] / [TOPDOWN.SLOTS_P] ) )" - }, - { - "name": "TMA_....Divider(%)", - "expression": "100 * ( [ARITH.DIV_ACTIVE] / [cpu-cycles] )" - }, - { - "name": "TMA_....Serializing_Operation(%)", - "expression": "100 * ( [RESOURCE_STALLS.SCOREBOARD] / [cpu-cycles] + ( [CPU_CLK_UNHALTED.C02] / [cpu-cycles] ) )" - }, - { - "name": "TMA_....AMX_Busy(%)", - "expression": "100 * ( [EXE.AMX_BUSY] / ( [CPU_CLK_UNHALTED.DISTRIBUTED] if [HYPERTHREADING_ON] else [cpu-cycles] ) )" - }, - { - "name": "TMA_Retiring(%)", - "expression": "100 * ( [UOPS_RETIRED.SLOTS] / [TOPDOWN.SLOTS_P] )" - }, - { - "name": "TMA_..Light_Operations(%)", - "expression": "100 * ( max( 0 , ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) - ( [UOPS_RETIRED.HEAVY] / ( [TOPDOWN.SLOTS_P] ) ) ) )" - }, - { - "name": "TMA_....Memory_Operations(%)", - "expression": "100 * ( ( max( 0 , ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) - ( [UOPS_RETIRED.HEAVY] / ( [TOPDOWN.SLOTS_P] ) ) ) ) * [MEM_UOP_RETIRED.ANY] / ( ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) * ( [TOPDOWN.SLOTS_P] ) ) )" - }, - { - "name": "TMA_....Fused_Instructions(%)", - "expression": "100 * ( ( max( 0 , ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) - ( [UOPS_RETIRED.HEAVY] / ( [TOPDOWN.SLOTS_P] ) ) ) ) * [INST_RETIRED.MACRO_FUSED] / ( ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) * ( [TOPDOWN.SLOTS_P] ) ) )" - }, - { - "name": "TMA_....Non_Fused_Branches(%)", - "expression": "100 * ( ( max( 0 , ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) - ( [UOPS_RETIRED.HEAVY] / ( [TOPDOWN.SLOTS_P] ) ) ) ) * ( [BR_INST_RETIRED.ALL_BRANCHES] - [INST_RETIRED.MACRO_FUSED] ) / ( ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) * ( [TOPDOWN.SLOTS_P] ) ) )" - }, - { - "name": "TMA_..Heavy_Operations(%)", - "expression": "100 * ( [UOPS_RETIRED.HEAVY] / [TOPDOWN.SLOTS_P] )" - }, - { - "name": "TMA_....Few_Uops_Instructions(%)", - "expression": "100 * max( 0 , ( [UOPS_RETIRED.HEAVY] / [TOPDOWN.SLOTS_P] ) - ( [UOPS_RETIRED.MS] / [TOPDOWN.SLOTS_P] ) )" - }, - { - "name": "TMA_....Microcode_Sequencer(%)", - "expression": "100 * ( [UOPS_RETIRED.MS] / [TOPDOWN.SLOTS_P] )" - } -] \ No newline at end of file diff --git a/cmd/metrics/resources/metrics/x86_64/GenuineIntel/icx.json b/cmd/metrics/resources/metrics/x86_64/GenuineIntel/icx.json deleted file mode 100644 index d35dd848..00000000 --- a/cmd/metrics/resources/metrics/x86_64/GenuineIntel/icx.json +++ /dev/null @@ -1,438 +0,0 @@ -[ - { - "name": "CPU operating frequency (in GHz)", - "expression": "(([cpu-cycles] / [ref-cycles] * [SYSTEM_TSC_FREQ]) / 1000000000)" - }, - { - "name": "CPU utilization %", - "expression": "100 * [ref-cycles] / [TSC]" - }, - { - "name": "CPU utilization% in kernel mode", - "expression": "100 * [ref-cycles:k] / [TSC]" - }, - { - "name": "CPI", - "expression": "[cpu-cycles] / [instructions]" - }, - { - "name": "cycles per txn", - "expression": "[cpu-cycles] / [TXN]" - }, - { - "name": "kernel_CPI", - "expression": "[cpu-cycles:k] / [instructions:k]" - }, - { - "name": "kernel_cycles per txn", - "expression": "[cpu-cycles:k] / [TXN]" - }, - { - "name": "IPC", - "expression": "[instructions] / [cpu-cycles]" - }, - { - "name": "txn per cycles", - "expression": "[instructions] / [TXN]" - }, - { - "name": "giga_instructions_per_sec", - "expression": "[instructions] / 1000000000" - }, - { - "name": "branch misprediction ratio", - "expression": "[BR_MISP_RETIRED.ALL_BRANCHES] / [BR_INST_RETIRED.ALL_BRANCHES]" - }, - { - "name": "locks retired per instr", - "expression": "[MEM_INST_RETIRED.LOCK_LOADS] / [instructions]" - }, - { - "name": "locks retired per txn", - "expression": "[MEM_INST_RETIRED.LOCK_LOADS] / [TXN]" - }, - { - "name": "L1D MPI (includes data+rfo w/ prefetches)", - "expression": "[L1D.REPLACEMENT] / [instructions]" - }, - { - "name": "L1D misses per txn (includes data+rfo w/ prefetches)", - "expression": "[L1D.REPLACEMENT] / [TXN]" - }, - { - "name": "L1D demand data read hits per instr", - "expression": "[MEM_LOAD_RETIRED.L1_HIT] / [instructions]" - }, - { - "name": "L1D demand data read hits per txn", - "expression": "[MEM_LOAD_RETIRED.L1_HIT] / [TXN]" - }, - { - "name": "L1-I code read misses (w/ prefetches) per instr", - "expression": "[L2_RQSTS.ALL_CODE_RD] / [instructions]" - }, - { - "name": "L1I code read misses (includes prefetches) per txn", - "expression": "[L2_RQSTS.ALL_CODE_RD] / [TXN]" - }, - { - "name": "L2 demand data read hits per instr", - "expression": "[MEM_LOAD_RETIRED.L2_HIT] / [instructions]" - }, - { - "name": "L2 demand data read hits per txn", - "expression": "[MEM_LOAD_RETIRED.L2_HIT] / [TXN]" - }, - { - "name": "L2 MPI (includes code+data+rfo w/ prefetches)", - "expression": "[L2_LINES_IN.ALL] / [instructions]" - }, - { - "name": "L2 misses per txn (includes code+data+rfo w/ prefetches)", - "expression": "[L2_LINES_IN.ALL] / [TXN]" - }, - { - "name": "L2 demand data read MPI", - "expression": "[MEM_LOAD_RETIRED.L2_MISS] / [instructions]" - }, - { - "name": "L2 demand data read misses per txn", - "expression": "[MEM_LOAD_RETIRED.L2_MISS] / [TXN]" - }, - { - "name": "L2 demand code MPI", - "expression": "[L2_RQSTS.CODE_RD_MISS] / [instructions]" - }, - { - "name": "L2 demand code misses per txn", - "expression": "[L2_RQSTS.CODE_RD_MISS] / [TXN]" - }, - { - "name": "LLC code read MPI (demand+prefetch)", - "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_CRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF]) / [instructions]" - }, - { - "name": "LLC code read (demand+prefetch) misses per txn", - "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_CRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF]) / [TXN]" - }, - { - "name": "LLC data read MPI (demand+prefetch)", - "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF]) / [instructions]" - }, - { - "name": "LLC data read (demand+prefetch) misses per txn", - "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF]) / [TXN]" - }, - { - "name": "LLC total HITM (per instr) (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM] / [instructions]" - }, - { - "name": "LLC total HITM per txn (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM] / [TXN]" - }, - { - "name": "LLC total HIT clean line forwards (per instr) (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD] / [instructions]" - }, - { - "name": "LLC total HIT clean line forwards per txn (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD] / [TXN]" - }, - { - "name": "Average LLC demand data read miss latency (in ns)", - "expression": "( 1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) ) ) * 1" - }, - { - "name": "Average LLC demand data read miss latency for LOCAL requests (in ns)", - "expression": "( 1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) ) ) * 1" - }, - { - "name": "Average LLC demand data read miss latency for REMOTE requests (in ns)", - "expression": "( 1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) ) ) * 1" - }, - { - "name": "UPI Data transmit BW (MB/sec) (only data)", - "expression": "([UNC_UPI_TxL_FLITS.ALL_DATA] * (64 / 9.0) / 1000000) / 1" - }, - { - "name": "package power (watts)", - "expression": "[power/energy-pkg/]" - }, - { - "name": "DRAM power (watts)", - "expression": "[power/energy-ram/]" - }, - { - "name": "core c6 residency %", - "expression": "100 * [cstate_core/c6-residency/] / [TSC]" - }, - { - "name": "package c6 residency %", - "expression": "100 * [cstate_pkg/c6-residency/] * [CORES_PER_SOCKET] / [TSC]" - }, - { - "name": "% Uops delivered from decoded Icache (DSB)", - "expression": "100 * ([IDQ.DSB_UOPS] / ([IDQ.DSB_UOPS] + [IDQ.MITE_UOPS] + [IDQ.MS_UOPS] + [LSD.UOPS]) )" - }, - { - "name": "% Uops delivered from legacy decode pipeline (MITE)", - "expression": "100 * ([IDQ.MITE_UOPS] / ([IDQ.DSB_UOPS] + [IDQ.MITE_UOPS] + [IDQ.MS_UOPS] + [LSD.UOPS]) )" - }, - { - "name": "core initiated local dram read bandwidth (MB/sec)", - "expression": "(([OCR.READS_TO_CORE.LOCAL_DRAM] + [OCR.HWPF_L3.L3_MISS_LOCAL]) * 64 / 1000000) / 1" - }, - { - "name": "core initiated remote dram read bandwidth (MB/sec)", - "expression": "(([OCR.READS_TO_CORE.REMOTE_DRAM] + [OCR.HWPF_L3.REMOTE]) * 64 / 1000000) / 1" - }, - { - "name": "memory bandwidth read (MB/sec)", - "expression": "([UNC_M_CAS_COUNT.RD] * 64 / 1000000) / 1" - }, - { - "name": "memory bandwidth write (MB/sec)", - "expression": "([UNC_M_CAS_COUNT.WR] * 64 / 1000000) / 1" - }, - { - "name": "memory bandwidth total (MB/sec)", - "expression": "(([UNC_M_CAS_COUNT.RD] + [UNC_M_CAS_COUNT.WR]) * 64 / 1000000) / 1" - }, - { - "name": "ITLB (2nd level) MPI", - "expression": "[ITLB_MISSES.WALK_COMPLETED] / [instructions]" - }, - { - "name": "ITLB (2nd level) misses per txn", - "expression": "[ITLB_MISSES.WALK_COMPLETED] / [TXN]" - }, - { - "name": "DTLB (2nd level) load MPI", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [instructions]" - }, - { - "name": "DTLB (2nd level) load misses per txn", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [TXN]" - }, - { - "name": "DTLB (2nd level) 2MB large page load MPI", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M] / [instructions]" - }, - { - "name": "DTLB (2nd level) 2MB large page load misses per txn", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M] / [TXN]" - }, - { - "name": "DTLB (2nd level) store MPI", - "expression": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [instructions]" - }, - { - "name": "DTLB (2nd level) store misses per txn", - "expression": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [TXN]" - }, - { - "name": "NUMA %_Reads addressed to local DRAM", - "expression": "100 * ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL]) / ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE])" - }, - { - "name": "NUMA %_Reads addressed to remote DRAM", - "expression": "100 * ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE]) / ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE])" - }, - { - "name": "uncore frequency GHz", - "expression": "([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) / 1000000000) / 1" - }, - { - "name": "TMA_Frontend_Bound(%)", - "expression": "100 * ( [PERF_METRICS.FRONTEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) )" - }, - { - "name": "TMA_..Fetch_Latency(%)", - "expression": "100 * ( ( ( 5 ) * [IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE] - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS] ) )" - }, - { - "name": "TMA_....ICache_Misses(%)", - "expression": "100 * ( [ICACHE_16B.IFDATA_STALL] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....ITLB_Misses(%)", - "expression": "100 * ( [ICACHE_64B.IFTAG_STALL] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....MS_Switches(%)", - "expression": "100 * ( ( 3 ) * [IDQ.MS_SWITCHES] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....LCP(%)", - "expression": "100 * ( [DECODE.LCP] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....DSB_Switches(%)", - "expression": "100 * ( [DSB2MITE_SWITCHES.PENALTY_CYCLES] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....Branch_Resteers(%)", - "expression": "100 * ( [INT_MISC.CLEAR_RESTEER_CYCLES] / ( [cpu-cycles] ) + ( ( 10 ) * [BACLEARS.ANY] / ( [cpu-cycles] ) ) )" - }, - { - "name": "TMA_......Mispredicts_Resteers(%)", - "expression": "100 * ( ( [BR_MISP_RETIRED.ALL_BRANCHES] / ( [BR_MISP_RETIRED.ALL_BRANCHES] + [MACHINE_CLEARS.COUNT] ) ) * [INT_MISC.CLEAR_RESTEER_CYCLES] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Clears_Resteers(%)", - "expression": "100 * ( ( 1 - ( [BR_MISP_RETIRED.ALL_BRANCHES] / ( [BR_MISP_RETIRED.ALL_BRANCHES] + [MACHINE_CLEARS.COUNT] ) ) ) * [INT_MISC.CLEAR_RESTEER_CYCLES] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Unknown_Branches(%)", - "expression": "100 * ( ( 10 ) * [BACLEARS.ANY] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_..Fetch_Bandwidth(%)", - "expression": "100 * ( max( 0 , ( [PERF_METRICS.FRONTEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) ) - ( ( ( 5 ) * [IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE] - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS] ) ) ) )" - }, - { - "name": "TMA_....MITE(%)", - "expression": "100 * ( ( [IDQ.MITE_CYCLES_ANY] - [IDQ.MITE_CYCLES_OK] ) / ( [CPU_CLK_UNHALTED.DISTRIBUTED] ) / 2 )" - }, - { - "name": "TMA_....DSB(%)", - "expression": "100 * ( ( [IDQ.DSB_CYCLES_ANY] - [IDQ.DSB_CYCLES_OK] ) / ( [CPU_CLK_UNHALTED.DISTRIBUTED] ) / 2 )" - }, - { - "name": "TMA_Bad_Speculation(%)", - "expression": "100 * ( max( 1 - ( ( [PERF_METRICS.FRONTEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) ) + ( [PERF_METRICS.BACKEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) + ( ( 5 ) * [INT_MISC.RECOVERY_CYCLES:c1:e1] ) / ( [TOPDOWN.SLOTS] ) ) + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) , 0 ) )" - }, - { - "name": "TMA_..Branch_Mispredicts(%)", - "expression": "100 * ( ( [BR_MISP_RETIRED.ALL_BRANCHES] / ( [BR_MISP_RETIRED.ALL_BRANCHES] + [MACHINE_CLEARS.COUNT] ) ) * ( max( 1 - ( ( [PERF_METRICS.FRONTEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) ) + ( [PERF_METRICS.BACKEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) + ( ( 5 ) * [INT_MISC.RECOVERY_CYCLES:c1:e1] ) / ( [TOPDOWN.SLOTS] ) ) + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) , 0 ) ) )" - }, - { - "name": "TMA_..Machine_Clears(%)", - "expression": "100 * ( max( 0 , ( max( 1 - ( ( [PERF_METRICS.FRONTEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) ) + ( [PERF_METRICS.BACKEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) + ( ( 5 ) * [INT_MISC.RECOVERY_CYCLES:c1:e1] ) / ( [TOPDOWN.SLOTS] ) ) + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) , 0 ) ) - ( ( [BR_MISP_RETIRED.ALL_BRANCHES] / ( [BR_MISP_RETIRED.ALL_BRANCHES] + [MACHINE_CLEARS.COUNT] ) ) * ( max( 1 - ( ( [PERF_METRICS.FRONTEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) ) + ( [PERF_METRICS.BACKEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) + ( ( 5 ) * [INT_MISC.RECOVERY_CYCLES:c1:e1] ) / ( [TOPDOWN.SLOTS] ) ) + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) , 0 ) ) ) ) )" - }, - { - "name": "TMA_Backend_Bound(%)", - "expression": "100 * ( [PERF_METRICS.BACKEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) + ( ( 5 ) * [INT_MISC.RECOVERY_CYCLES:c1:e1] ) / ( [TOPDOWN.SLOTS] ) )" - }, - { - "name": "TMA_..Memory_Bound(%)", - "expression": "100 * ( ( ( [CYCLE_ACTIVITY.STALLS_MEM_ANY] + [EXE_ACTIVITY.BOUND_ON_STORES] ) / ( [CYCLE_ACTIVITY.STALLS_TOTAL] + ( [EXE_ACTIVITY.1_PORTS_UTIL] + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * [EXE_ACTIVITY.2_PORTS_UTIL] ) + [EXE_ACTIVITY.BOUND_ON_STORES] ) ) * ( [PERF_METRICS.BACKEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) + ( ( 5 ) * [INT_MISC.RECOVERY_CYCLES:c1:e1] ) / ( [TOPDOWN.SLOTS] ) ) )" - }, - { - "name": "TMA_....L1_Bound(%)", - "expression": "100 * ( max( ( [CYCLE_ACTIVITY.STALLS_MEM_ANY] - [CYCLE_ACTIVITY.STALLS_L1D_MISS] ) / ( [cpu-cycles] ) , 0 ) )" - }, - { - "name": "TMA_......DTLB_Load(%)", - "expression": "100 * ( min( ( 7 ) * [DTLB_LOAD_MISSES.STLB_HIT:c1] + [DTLB_LOAD_MISSES.WALK_ACTIVE] , max( [CYCLE_ACTIVITY.CYCLES_MEM_ANY] - [CYCLE_ACTIVITY.CYCLES_L1D_MISS] , 0 ) ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Lock_Latency(%)", - "expression": "100 * ( min( ( ( 16 * max( 0 , [MEM_INST_RETIRED.LOCK_LOADS] - [L2_RQSTS.ALL_RFO] ) + ( [MEM_INST_RETIRED.LOCK_LOADS] / [MEM_INST_RETIRED.ALL_STORES] ) * ( ( 10 ) * [L2_RQSTS.RFO_HIT] + ( min( [cpu-cycles] , [OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO] ) ) ) ) / ( [cpu-cycles] ) ) , ( 1 ) ) )" - }, - { - "name": "TMA_....L2_Bound(%)", - "expression": "100 * ( ( ( [MEM_LOAD_RETIRED.L2_HIT] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) / ( ( [MEM_LOAD_RETIRED.L2_HIT] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) + [L1D_PEND_MISS.FB_FULL_PERIODS] ) ) * ( ( [CYCLE_ACTIVITY.STALLS_L1D_MISS] - [CYCLE_ACTIVITY.STALLS_L2_MISS] ) / ( [cpu-cycles] ) ) )" - }, - { - "name": "TMA_....L3_Bound(%)", - "expression": "100 * ( ( [CYCLE_ACTIVITY.STALLS_L2_MISS] - [CYCLE_ACTIVITY.STALLS_L3_MISS] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Data_Sharing(%)", - "expression": "100 * ( min( ( ( ( 47.5 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( 1000 / 1000 ) ) ) - ( 4 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( 1000 / 1000 ) ) ) ) * ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT] + [MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM] * ( 1 - ( [OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM] / ( [OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM] + [OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD] ) ) ) ) * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) / 2 ) / ( [cpu-cycles] ) ) , ( 1 ) ) )" - }, - { - "name": "TMA_....DRAM_Bound(%)", - "expression": "100 * ( min( ( ( ( [CYCLE_ACTIVITY.STALLS_L3_MISS] / ( [cpu-cycles] ) + ( ( [CYCLE_ACTIVITY.STALLS_L1D_MISS] - [CYCLE_ACTIVITY.STALLS_L2_MISS] ) / ( [cpu-cycles] ) ) - ( ( ( [MEM_LOAD_RETIRED.L2_HIT] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) / ( ( [MEM_LOAD_RETIRED.L2_HIT] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) + [L1D_PEND_MISS.FB_FULL_PERIODS] ) ) * ( ( [CYCLE_ACTIVITY.STALLS_L1D_MISS] - [CYCLE_ACTIVITY.STALLS_L2_MISS] ) / ( [cpu-cycles] ) ) ) ) - ( min( ( ( ( ( 1 - ( ( ( 19 * ( [MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) + 10 * ( ( [MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) + ( [MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) + ( [MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) ) ) / ( ( 19 * ( [MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) + 10 * ( ( [MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) + ( [MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) + ( [MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) ) ) + ( 25 * ( ( [MEM_LOAD_RETIRED.LOCAL_PMM] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) ) + 33 * ( ( [MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) ) ) ) ) ) ) * ( [CYCLE_ACTIVITY.STALLS_L3_MISS] / ( [cpu-cycles] ) + ( ( [CYCLE_ACTIVITY.STALLS_L1D_MISS] - [CYCLE_ACTIVITY.STALLS_L2_MISS] ) / ( [cpu-cycles] ) ) - ( ( ( [MEM_LOAD_RETIRED.L2_HIT] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) / ( ( [MEM_LOAD_RETIRED.L2_HIT] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) + [L1D_PEND_MISS.FB_FULL_PERIODS] ) ) * ( ( [CYCLE_ACTIVITY.STALLS_L1D_MISS] - [CYCLE_ACTIVITY.STALLS_L2_MISS] ) / ( [cpu-cycles] ) ) ) ) ) if ( ( 1000000 ) * ( [MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM] + [MEM_LOAD_RETIRED.LOCAL_PMM] ) > [MEM_LOAD_RETIRED.L1_MISS] ) else 0 ) ) , ( 1 ) ) ) ) ) , ( 1 ) ) )" - }, - { - "name": "TMA_......MEM_Bandwidth(%)", - "expression": "100 * ( ( min( [cpu-cycles] , [OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4] ) ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......MEM_Latency(%)", - "expression": "100 * ( ( min( [cpu-cycles] , [OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD] ) ) / ( [cpu-cycles] ) - ( ( min( [cpu-cycles] , [OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4] ) ) / ( [cpu-cycles] ) ) )" - }, - { - "name": "TMA_....Store_Bound(%)", - "expression": "100 * ( [EXE_ACTIVITY.BOUND_ON_STORES] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......False_Sharing(%)", - "expression": "100 * ( min( ( ( 48 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( 1000 / 1000 ) ) ) * [OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM] / ( [cpu-cycles] ) ) , ( 1 ) ) )" - }, - { - "name": "TMA_..Core_Bound(%)", - "expression": "100 * ( max( 0 , ( [PERF_METRICS.BACKEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) + ( ( 5 ) * [INT_MISC.RECOVERY_CYCLES:c1:e1] ) / ( [TOPDOWN.SLOTS] ) ) - ( ( ( [CYCLE_ACTIVITY.STALLS_MEM_ANY] + [EXE_ACTIVITY.BOUND_ON_STORES] ) / ( [CYCLE_ACTIVITY.STALLS_TOTAL] + ( [EXE_ACTIVITY.1_PORTS_UTIL] + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * [EXE_ACTIVITY.2_PORTS_UTIL] ) + [EXE_ACTIVITY.BOUND_ON_STORES] ) ) * ( [PERF_METRICS.BACKEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) + ( ( 5 ) * [INT_MISC.RECOVERY_CYCLES:c1:e1] ) / ( [TOPDOWN.SLOTS] ) ) ) ) )" - }, - { - "name": "TMA_....Divider(%)", - "expression": "100 * ( [ARITH.DIVIDER_ACTIVE] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....Ports_Utilization(%)", - "expression": "100 * ( ( [EXE_ACTIVITY.3_PORTS_UTIL:u0x80] + ( [RESOURCE_STALLS.SCOREBOARD] / ( [cpu-cycles] ) ) * ( [CYCLE_ACTIVITY.STALLS_TOTAL] - [CYCLE_ACTIVITY.STALLS_MEM_ANY] ) + ( [EXE_ACTIVITY.1_PORTS_UTIL] + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * [EXE_ACTIVITY.2_PORTS_UTIL] ) ) / ( [cpu-cycles] ) if ( [ARITH.DIVIDER_ACTIVE] < ( [CYCLE_ACTIVITY.STALLS_TOTAL] - [CYCLE_ACTIVITY.STALLS_MEM_ANY] ) ) else ( [EXE_ACTIVITY.1_PORTS_UTIL] + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * [EXE_ACTIVITY.2_PORTS_UTIL] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Ports_Utilized_0(%)", - "expression": "100 * ( [EXE_ACTIVITY.3_PORTS_UTIL:u0x80] / ( [cpu-cycles] ) + ( [RESOURCE_STALLS.SCOREBOARD] / ( [cpu-cycles] ) ) * ( [CYCLE_ACTIVITY.STALLS_TOTAL] - [CYCLE_ACTIVITY.STALLS_MEM_ANY] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Ports_Utilized_1(%)", - "expression": "100 * ( [EXE_ACTIVITY.1_PORTS_UTIL] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Ports_Utilized_2(%)", - "expression": "100 * ( [EXE_ACTIVITY.2_PORTS_UTIL] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Ports_Utilized_3m(%)", - "expression": "100 * ( [UOPS_EXECUTED.CYCLES_GE_3] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_Retiring(%)", - "expression": "100 * ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) )" - }, - { - "name": "TMA_..Light_Operations(%)", - "expression": "100 * ( max( 0 , ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) - ( ( ( ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) / [UOPS_ISSUED.ANY] ) * [IDQ.MS_UOPS] / ( [TOPDOWN.SLOTS] ) ) + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [UOPS_DECODED.DEC0] - [UOPS_DECODED.DEC0:c1] ) / [IDQ.MITE_UOPS] ) ) )" - }, - { - "name": "TMA_....Memory_Operations(%)", - "expression": "100 * ( ( max( 0 , ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) - ( ( ( [UOPS_RETIRED.SLOTS] / [UOPS_ISSUED.ANY] ) * [IDQ.MS_UOPS] / ( [TOPDOWN.SLOTS] ) ) + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [UOPS_DECODED.DEC0] - [UOPS_DECODED.DEC0:c1] ) / [IDQ.MITE_UOPS] ) ) ) * [MEM_INST_RETIRED.ANY] / [instructions] )" - }, - { - "name": "TMA_....Branch_Instructions(%)", - "expression": "100 * ( ( max( 0 , ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) - ( ( ( [UOPS_RETIRED.SLOTS] / [UOPS_ISSUED.ANY] ) * [IDQ.MS_UOPS] / ( [TOPDOWN.SLOTS] ) ) + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [UOPS_DECODED.DEC0] - [UOPS_DECODED.DEC0:c1] ) / [IDQ.MITE_UOPS] ) ) ) * [BR_INST_RETIRED.ALL_BRANCHES] / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) )" - }, - { - "name": "TMA_........FP_Vector_128b(%)", - "expression": "100 * ( min( ( ( [FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE] + [FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE] ) / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) ) , ( 1 ) ) )" - }, - { - "name": "TMA_........FP_Vector_256b(%)", - "expression": "100 * ( min( ( ( [FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE] + [FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE] ) / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) ) , ( 1 ) ) )" - }, - { - "name": "TMA_........FP_Vector_512b(%)", - "expression": "100 * ( min( ( ( [FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE] + [FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE] ) / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) ) , ( 1 ) ) )" - }, - { - "name": "TMA_..Heavy_Operations(%)", - "expression": "100 * ( ( ( ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) / [UOPS_ISSUED.ANY] ) * [IDQ.MS_UOPS] / ( [TOPDOWN.SLOTS] ) ) + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [UOPS_DECODED.DEC0] - [UOPS_DECODED.DEC0:c1] ) / [IDQ.MITE_UOPS] )" - }, - { - "name": "TMA_....Few_Uops_Instructions(%)", - "expression": "100 * ( ( ( ( [UOPS_RETIRED.SLOTS] / [UOPS_ISSUED.ANY] ) * [IDQ.MS_UOPS] / ( [TOPDOWN.SLOTS] ) ) + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [UOPS_DECODED.DEC0] - [UOPS_DECODED.DEC0:c1] ) / [IDQ.MITE_UOPS] ) - ( ( [UOPS_RETIRED.SLOTS] / [UOPS_ISSUED.ANY] ) * [IDQ.MS_UOPS] / ( [TOPDOWN.SLOTS] ) ) )" - }, - { - "name": "TMA_....Microcode_Sequencer(%)", - "expression": "100 * ( ( ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) / [UOPS_ISSUED.ANY] ) * [IDQ.MS_UOPS] / ( [TOPDOWN.SLOTS] ) )" - }, - { - "name": "TMA_Info_System_SMT_2T_Utilization", - "expression": "1 - [CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE] / [CPU_CLK_UNHALTED.REF_DISTRIBUTED] if [SOCKET_COUNT] > 1 else 0" - } -] \ No newline at end of file diff --git a/cmd/metrics/resources/metrics/x86_64/GenuineIntel/icx_nofixedtma.json b/cmd/metrics/resources/metrics/x86_64/GenuineIntel/icx_nofixedtma.json deleted file mode 100644 index baec0539..00000000 --- a/cmd/metrics/resources/metrics/x86_64/GenuineIntel/icx_nofixedtma.json +++ /dev/null @@ -1,362 +0,0 @@ -[ - { - "name": "CPU operating frequency (in GHz)", - "expression": "(([cpu-cycles] / [ref-cycles] * [SYSTEM_TSC_FREQ]) / 1000000000)" - }, - { - "name": "CPU utilization %", - "expression": "100 * [ref-cycles] / [TSC]" - }, - { - "name": "CPU utilization% in kernel mode", - "expression": "100 * [ref-cycles:k] / [TSC]" - }, - { - "name": "CPI", - "expression": "[cpu-cycles] / [instructions]" - }, - { - "name": "cycles per txn", - "expression": "[cpu-cycles] / [TXN]" - }, - { - "name": "kernel_CPI", - "expression": "[cpu-cycles:k] / [instructions:k]" - }, - { - "name": "kernel_cycles per txn", - "expression": "[cpu-cycles:k] / [TXN]" - }, - { - "name": "IPC", - "expression": "[instructions] / [cpu-cycles]" - }, - { - "name": "txn per cycles", - "expression": "[instructions] / [TXN]" - }, - { - "name": "giga_instructions_per_sec", - "expression": "[instructions] / 1000000000" - }, - { - "name": "branch misprediction ratio", - "expression": "[BR_MISP_RETIRED.ALL_BRANCHES] / [BR_INST_RETIRED.ALL_BRANCHES]" - }, - { - "name": "locks retired per instr", - "expression": "[MEM_INST_RETIRED.LOCK_LOADS] / [instructions]" - }, - { - "name": "locks retired per txn", - "expression": "[MEM_INST_RETIRED.LOCK_LOADS] / [TXN]" - }, - { - "name": "L1D MPI (includes data+rfo w/ prefetches)", - "expression": "[L1D.REPLACEMENT] / [instructions]" - }, - { - "name": "L1D misses per txn (includes data+rfo w/ prefetches)", - "expression": "[L1D.REPLACEMENT] / [TXN]" - }, - { - "name": "L1D demand data read hits per instr", - "expression": "[MEM_LOAD_RETIRED.L1_HIT] / [instructions]" - }, - { - "name": "L1D demand data read hits per txn", - "expression": "[MEM_LOAD_RETIRED.L1_HIT] / [TXN]" - }, - { - "name": "L1-I code read misses (w/ prefetches) per instr", - "expression": "[L2_RQSTS.ALL_CODE_RD] / [instructions]" - }, - { - "name": "L1I code read misses (includes prefetches) per txn", - "expression": "[L2_RQSTS.ALL_CODE_RD] / [TXN]" - }, - { - "name": "L2 demand data read hits per instr", - "expression": "[MEM_LOAD_RETIRED.L2_HIT] / [instructions]" - }, - { - "name": "L2 demand data read hits per txn", - "expression": "[MEM_LOAD_RETIRED.L2_HIT] / [TXN]" - }, - { - "name": "L2 MPI (includes code+data+rfo w/ prefetches)", - "expression": "[L2_LINES_IN.ALL] / [instructions]" - }, - { - "name": "L2 misses per txn (includes code+data+rfo w/ prefetches)", - "expression": "[L2_LINES_IN.ALL] / [TXN]" - }, - { - "name": "L2 demand data read MPI", - "expression": "[MEM_LOAD_RETIRED.L2_MISS] / [instructions]" - }, - { - "name": "L2 demand data read misses per txn", - "expression": "[MEM_LOAD_RETIRED.L2_MISS] / [TXN]" - }, - { - "name": "L2 demand code MPI", - "expression": "[L2_RQSTS.CODE_RD_MISS] / [instructions]" - }, - { - "name": "L2 demand code misses per txn", - "expression": "[L2_RQSTS.CODE_RD_MISS] / [TXN]" - }, - { - "name": "LLC code read MPI (demand+prefetch)", - "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_CRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF]) / [instructions]" - }, - { - "name": "LLC code read (demand+prefetch) misses per txn", - "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_CRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF]) / [TXN]" - }, - { - "name": "LLC data read MPI (demand+prefetch)", - "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF]) / [instructions]" - }, - { - "name": "LLC data read (demand+prefetch) misses per txn", - "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF]) / [TXN]" - }, - { - "name": "LLC total HITM (per instr) (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM] / [instructions]" - }, - { - "name": "LLC total HITM per txn (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM] / [TXN]" - }, - { - "name": "LLC total HIT clean line forwards (per instr) (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD] / [instructions]" - }, - { - "name": "LLC total HIT clean line forwards per txn (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD] / [TXN]" - }, - { - "name": "Average LLC demand data read miss latency (in ns)", - "expression": "( 1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) ) ) * 1" - }, - { - "name": "Average LLC demand data read miss latency for LOCAL requests (in ns)", - "expression": "( 1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) ) ) * 1" - }, - { - "name": "Average LLC demand data read miss latency for REMOTE requests (in ns)", - "expression": "( 1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) ) ) * 1" - }, - { - "name": "UPI Data transmit BW (MB/sec) (only data)", - "expression": "([UNC_UPI_TxL_FLITS.ALL_DATA] * (64 / 9.0) / 1000000) / 1" - }, - { - "name": "package power (watts)", - "expression": "[power/energy-pkg/]" - }, - { - "name": "DRAM power (watts)", - "expression": "[power/energy-ram/]" - }, - { - "name": "core c6 residency %", - "expression": "100 * [cstate_core/c6-residency/] / [TSC]" - }, - { - "name": "package c6 residency %", - "expression": "100 * [cstate_pkg/c6-residency/] * [CORES_PER_SOCKET] / [TSC]" - }, - { - "name": "% Uops delivered from decoded Icache (DSB)", - "expression": "100 * ([IDQ.DSB_UOPS] / ([IDQ.DSB_UOPS] + [IDQ.MITE_UOPS] + [IDQ.MS_UOPS] + [LSD.UOPS]) )" - }, - { - "name": "% Uops delivered from legacy decode pipeline (MITE)", - "expression": "100 * ([IDQ.MITE_UOPS] / ([IDQ.DSB_UOPS] + [IDQ.MITE_UOPS] + [IDQ.MS_UOPS] + [LSD.UOPS]) )" - }, - { - "name": "core initiated local dram read bandwidth (MB/sec)", - "expression": "(([OCR.READS_TO_CORE.LOCAL_DRAM] + [OCR.HWPF_L3.L3_MISS_LOCAL]) * 64 / 1000000) / 1" - }, - { - "name": "core initiated remote dram read bandwidth (MB/sec)", - "expression": "(([OCR.READS_TO_CORE.REMOTE_DRAM] + [OCR.HWPF_L3.REMOTE]) * 64 / 1000000) / 1" - }, - { - "name": "memory bandwidth read (MB/sec)", - "expression": "([UNC_M_CAS_COUNT.RD] * 64 / 1000000) / 1" - }, - { - "name": "memory bandwidth write (MB/sec)", - "expression": "([UNC_M_CAS_COUNT.WR] * 64 / 1000000) / 1" - }, - { - "name": "memory bandwidth total (MB/sec)", - "expression": "(([UNC_M_CAS_COUNT.RD] + [UNC_M_CAS_COUNT.WR]) * 64 / 1000000) / 1" - }, - { - "name": "ITLB (2nd level) MPI", - "expression": "[ITLB_MISSES.WALK_COMPLETED] / [instructions]" - }, - { - "name": "ITLB (2nd level) misses per txn", - "expression": "[ITLB_MISSES.WALK_COMPLETED] / [TXN]" - }, - { - "name": "DTLB (2nd level) load MPI", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [instructions]" - }, - { - "name": "DTLB (2nd level) load misses per txn", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [TXN]" - }, - { - "name": "DTLB (2nd level) 2MB large page load MPI", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M] / [instructions]" - }, - { - "name": "DTLB (2nd level) 2MB large page load misses per txn", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M] / [TXN]" - }, - { - "name": "DTLB (2nd level) store MPI", - "expression": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [instructions]" - }, - { - "name": "DTLB (2nd level) store misses per txn", - "expression": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [TXN]" - }, - { - "name": "NUMA %_Reads addressed to local DRAM", - "expression": "100 * ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL]) / ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE])" - }, - { - "name": "NUMA %_Reads addressed to remote DRAM", - "expression": "100 * ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE]) / ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE])" - }, - { - "name": "uncore frequency GHz", - "expression": "([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) / 1000000000) / 1" - }, - { - "name": "TMA_Frontend_Bound(%)", - "expression": "100 * ( ( [IDQ_UOPS_NOT_DELIVERED.CORE] - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS_P] ) )" - }, - { - "name": "TMA_..Fetch_Latency(%)", - "expression": "100 * ( ( ( 5 ) * [IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE] - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS_P] ) )" - }, - { - "name": "TMA_....ICache_Misses(%)", - "expression": "100 * ( [ICACHE_DATA.STALLS] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....ITLB_Misses(%)", - "expression": "100 * ( [ICACHE_TAG.STALLS] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....MS_Switches(%)", - "expression": "100 * ( ( 3 ) * [IDQ.MS_SWITCHES] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....LCP(%)", - "expression": "100 * ( [DECODE.LCP] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....DSB_Switches(%)", - "expression": "100 * ( [DSB2MITE_SWITCHES.PENALTY_CYCLES] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_..Fetch_Bandwidth(%)", - "expression": "100 * ( max( 0 , ( ( [IDQ_UOPS_NOT_DELIVERED.CORE] - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS_P] ) ) - ( ( ( 5 ) * [IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE] - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS_P] ) ) ) )" - }, - { - "name": "TMA_....MITE(%)", - "expression": "100 * ( ( [IDQ.MITE_CYCLES_ANY] - [IDQ.MITE_CYCLES_OK] ) / ( [CPU_CLK_UNHALTED.DISTRIBUTED] ) / 2 )" - }, - { - "name": "TMA_....DSB(%)", - "expression": "100 * ( ( [IDQ.DSB_CYCLES_ANY] - [IDQ.DSB_CYCLES_OK] ) / ( [CPU_CLK_UNHALTED.DISTRIBUTED] ) / 2 )" - }, - { - "name": "TMA_Bad_Speculation(%)", - "expression": "100 * ( max( 1 - ( ( ( [IDQ_UOPS_NOT_DELIVERED.CORE] - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS_P] ) ) + ( ( [TOPDOWN.BACKEND_BOUND_SLOTS] + ( 5 ) * [INT_MISC.CLEARS_COUNT] ) / ( [TOPDOWN.SLOTS_P] ) ) + ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) ) , 0 ) )" - }, - { - "name": "TMA_..Branch_Mispredicts(%)", - "expression": "100 * ( ( [BR_MISP_RETIRED.ALL_BRANCHES] / ( [BR_MISP_RETIRED.ALL_BRANCHES] + [MACHINE_CLEARS.COUNT] ) ) * ( max( 1 - ( ( ( [IDQ_UOPS_NOT_DELIVERED.CORE] - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS_P] ) ) + ( ( [TOPDOWN.BACKEND_BOUND_SLOTS] + ( 5 ) * [INT_MISC.CLEARS_COUNT] ) / ( [TOPDOWN.SLOTS_P] ) ) + ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) ) , 0 ) ) )" - }, - { - "name": "TMA_..Machine_Clears(%)", - "expression": "100 * ( max( 0 , ( max( 1 - ( ( ( [IDQ_UOPS_NOT_DELIVERED.CORE] - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS_P] ) ) + ( ( [TOPDOWN.BACKEND_BOUND_SLOTS] + ( 5 ) * [INT_MISC.CLEARS_COUNT] ) / ( [TOPDOWN.SLOTS_P] ) ) + ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) ) , 0 ) ) - ( ( [BR_MISP_RETIRED.ALL_BRANCHES] / ( [BR_MISP_RETIRED.ALL_BRANCHES] + [MACHINE_CLEARS.COUNT] ) ) * ( max( 1 - ( ( ( [IDQ_UOPS_NOT_DELIVERED.CORE] - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS_P] ) ) + ( ( [TOPDOWN.BACKEND_BOUND_SLOTS] + ( 5 ) * [INT_MISC.CLEARS_COUNT] ) / ( [TOPDOWN.SLOTS_P] ) ) + ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) ) , 0 ) ) ) ) )" - }, - { - "name": "TMA_Backend_Bound(%)", - "expression": "100 * ( ( [TOPDOWN.BACKEND_BOUND_SLOTS] + ( 5 ) * [INT_MISC.CLEARS_COUNT] ) / ( [TOPDOWN.SLOTS_P] ) )" - }, - { - "name": "TMA_..Memory_Bound(%)", - "expression": "100 * ( ( ( [CYCLE_ACTIVITY.STALLS_MEM_ANY] + [EXE_ACTIVITY.BOUND_ON_STORES] ) / ( [CYCLE_ACTIVITY.STALLS_TOTAL] + ( [EXE_ACTIVITY.1_PORTS_UTIL] + ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) * [EXE_ACTIVITY.2_PORTS_UTIL] ) + [EXE_ACTIVITY.BOUND_ON_STORES] ) ) * ( ( [TOPDOWN.BACKEND_BOUND_SLOTS] + ( 5 ) * [INT_MISC.CLEARS_COUNT] ) / ( [TOPDOWN.SLOTS_P] ) ) )" - }, - { - "name": "TMA_....L1_Bound(%)", - "expression": "100 * ( max( ( [CYCLE_ACTIVITY.STALLS_MEM_ANY] - [CYCLE_ACTIVITY.STALLS_L1D_MISS] ) / ( [cpu-cycles] ) , 0 ) )" - }, - { - "name": "TMA_....L2_Bound(%)", - "expression": "100 * ( ( ( [MEM_LOAD_RETIRED.L2_HIT] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) / ( ( [MEM_LOAD_RETIRED.L2_HIT] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) + [L1D_PEND_MISS.FB_FULL_PERIODS] ) ) * ( ( [CYCLE_ACTIVITY.STALLS_L1D_MISS] - [CYCLE_ACTIVITY.STALLS_L2_MISS] ) / ( [cpu-cycles] ) ) )" - }, - { - "name": "TMA_....L3_Bound(%)", - "expression": "100 * ( ( [CYCLE_ACTIVITY.STALLS_L2_MISS] - [CYCLE_ACTIVITY.STALLS_L3_MISS] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....DRAM_Bound(%)", - "expression": "100 * ( ( [CYCLE_ACTIVITY.STALLS_L3_MISS] / ( [cpu-cycles] ) + ( ( [CYCLE_ACTIVITY.STALLS_L1D_MISS] - [CYCLE_ACTIVITY.STALLS_L2_MISS] ) / ( [cpu-cycles] ) ) - ( ( ( [MEM_LOAD_RETIRED.L2_HIT] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) / ( ( [MEM_LOAD_RETIRED.L2_HIT] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) + [L1D_PEND_MISS.FB_FULL_PERIODS] ) ) * ( ( [CYCLE_ACTIVITY.STALLS_L1D_MISS] - [CYCLE_ACTIVITY.STALLS_L2_MISS] ) / ( [cpu-cycles] ) ) ) ) )" - }, - { - "name": "TMA_....Store_Bound(%)", - "expression": "100 * ( [EXE_ACTIVITY.BOUND_ON_STORES] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_..Core_Bound(%)", - "expression": "100 * ( max( 0 , ( ( [TOPDOWN.BACKEND_BOUND_SLOTS] + ( 5 ) * [INT_MISC.CLEARS_COUNT] ) / ( [TOPDOWN.SLOTS_P] ) ) - ( ( ( [CYCLE_ACTIVITY.STALLS_MEM_ANY] + [EXE_ACTIVITY.BOUND_ON_STORES] ) / ( [CYCLE_ACTIVITY.STALLS_TOTAL] + ( [EXE_ACTIVITY.1_PORTS_UTIL] + ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) * [EXE_ACTIVITY.2_PORTS_UTIL] ) + [EXE_ACTIVITY.BOUND_ON_STORES] ) ) * ( ( [TOPDOWN.BACKEND_BOUND_SLOTS] + ( 5 ) * [INT_MISC.CLEARS_COUNT] ) / ( [TOPDOWN.SLOTS_P] ) ) ) ) )" - }, - { - "name": "TMA_....Divider(%)", - "expression": "100 * ( [ARITH.DIVIDER_ACTIVE] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_Retiring(%)", - "expression": "100 * ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) )" - }, - { - "name": "TMA_..Light_Operations(%)", - "expression": "100 * ( max( 0 , ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) - ( ( ( [UOPS_RETIRED.SLOTS] / [UOPS_ISSUED.ANY] ) * [IDQ.MS_UOPS] / ( [TOPDOWN.SLOTS_P] ) ) + ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) * ( [UOPS_DECODED.DEC0] - [UOPS_DECODED.DEC0:c1] ) / [IDQ.MITE_UOPS] ) ) )" - }, - { - "name": "TMA_....Memory_Operations(%)", - "expression": "100 * ( ( max( 0 , ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) - ( ( ( [UOPS_RETIRED.SLOTS] / [UOPS_ISSUED.ANY] ) * [IDQ.MS_UOPS] / ( [TOPDOWN.SLOTS_P] ) ) + ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) * ( [UOPS_DECODED.DEC0] - [UOPS_DECODED.DEC0:c1] ) / [IDQ.MITE_UOPS] ) ) ) * [MEM_INST_RETIRED.ANY] / [instructions] )" - }, - { - "name": "TMA_....Branch_Instructions(%)", - "expression": "100 * ( ( max( 0 , ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) - ( ( ( [UOPS_RETIRED.SLOTS] / [UOPS_ISSUED.ANY] ) * [IDQ.MS_UOPS] / ( [TOPDOWN.SLOTS_P] ) ) + ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) * ( [UOPS_DECODED.DEC0] - [UOPS_DECODED.DEC0:c1] ) / [IDQ.MITE_UOPS] ) ) ) * [BR_INST_RETIRED.ALL_BRANCHES] / ( ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) * ( [TOPDOWN.SLOTS_P] ) ) )" - }, - { - "name": "TMA_..Heavy_Operations(%)", - "expression": "100 * ( ( ( [UOPS_RETIRED.SLOTS] / [UOPS_ISSUED.ANY] ) * [IDQ.MS_UOPS] / ( [TOPDOWN.SLOTS_P] ) ) + ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) * ( [UOPS_DECODED.DEC0] - [UOPS_DECODED.DEC0:c1] ) / [IDQ.MITE_UOPS] )" - }, - { - "name": "TMA_....Few_Uops_Instructions(%)", - "expression": "100 * ( ( ( ( [UOPS_RETIRED.SLOTS] / [UOPS_ISSUED.ANY] ) * [IDQ.MS_UOPS] / ( [TOPDOWN.SLOTS_P] ) ) + ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) * ( [UOPS_DECODED.DEC0] - [UOPS_DECODED.DEC0:c1] ) / [IDQ.MITE_UOPS] ) - ( ( [UOPS_RETIRED.SLOTS] / [UOPS_ISSUED.ANY] ) * [IDQ.MS_UOPS] / ( [TOPDOWN.SLOTS_P] ) ) )" - }, - { - "name": "TMA_....Microcode_Sequencer(%)", - "expression": "100 * ( ( [UOPS_RETIRED.SLOTS] / [UOPS_ISSUED.ANY] ) * [IDQ.MS_UOPS] / ( [TOPDOWN.SLOTS_P] ) )" - } -] \ No newline at end of file diff --git a/cmd/metrics/resources/metrics/x86_64/GenuineIntel/spr.json b/cmd/metrics/resources/metrics/x86_64/GenuineIntel/spr.json deleted file mode 100644 index 50aa9642..00000000 --- a/cmd/metrics/resources/metrics/x86_64/GenuineIntel/spr.json +++ /dev/null @@ -1,462 +0,0 @@ -[ - { - "name": "CPU operating frequency (in GHz)", - "expression": "(([cpu-cycles] / [ref-cycles] * [SYSTEM_TSC_FREQ]) / 1000000000)" - }, - { - "name": "CPU utilization %", - "expression": "100 * [ref-cycles] / [TSC]" - }, - { - "name": "CPU utilization% in kernel mode", - "expression": "100 * [ref-cycles:k] / [TSC]" - }, - { - "name": "CPI", - "expression": "[cpu-cycles] / [instructions]" - }, - { - "name": "cycles per txn", - "expression": "[cpu-cycles] / [TXN]" - }, - { - "name": "kernel_CPI", - "expression": "[cpu-cycles:k] / [instructions:k]" - }, - { - "name": "kernel_cycles per txn", - "expression": "[cpu-cycles:k] / [TXN]" - }, - { - "name": "IPC", - "expression": "[instructions] / [cpu-cycles]" - }, - { - "name": "txn per cycle", - "expression": "[TXN] / [cpu-cycles]" - }, - { - "name": "giga_instructions_per_sec", - "expression": "[instructions] / 1000000000" - }, - { - "name": "branch misprediction ratio", - "expression": "[BR_MISP_RETIRED.ALL_BRANCHES] / [BR_INST_RETIRED.ALL_BRANCHES]" - }, - { - "name": "locks retired per instr", - "expression": "[MEM_INST_RETIRED.LOCK_LOADS] / [instructions]" - }, - { - "name": "locks retired per txn", - "expression": "[MEM_INST_RETIRED.LOCK_LOADS] / [TXN]" - }, - { - "name": "L1D MPI (includes data+rfo w/ prefetches)", - "expression": "[L1D.REPLACEMENT] / [instructions]" - }, - { - "name": "L1D misses per txn (includes data+rfo w/ prefetches)", - "expression": "[L1D.REPLACEMENT] / [TXN]" - }, - { - "name": "L1D demand data read hits per instr", - "expression": "[MEM_LOAD_RETIRED.L1_HIT] / [instructions]" - }, - { - "name": "L1D demand data read hits per txn", - "expression": "[MEM_LOAD_RETIRED.L1_HIT] / [TXN]" - }, - { - "name": "L1-I code read misses (w/ prefetches) per instr", - "expression": "[L2_RQSTS.ALL_CODE_RD] / [instructions]" - }, - { - "name": "L1I code read misses (includes prefetches) per txn", - "expression": "[L2_RQSTS.ALL_CODE_RD] / [TXN]" - }, - { - "name": "L2 demand data read hits per instr", - "expression": "[MEM_LOAD_RETIRED.L2_HIT] / [instructions]" - }, - { - "name": "L2 demand data read hits per txn", - "expression": "[MEM_LOAD_RETIRED.L2_HIT] / [TXN]" - }, - { - "name": "L2 MPI (includes code+data+rfo w/ prefetches)", - "expression": "[L2_LINES_IN.ALL] / [instructions]" - }, - { - "name": "L2 misses per txn (includes code+data+rfo w/ prefetches)", - "expression": "[L2_LINES_IN.ALL] / [TXN]" - }, - { - "name": "L2 demand data read MPI", - "expression": "[MEM_LOAD_RETIRED.L2_MISS] / [instructions]" - }, - { - "name": "L2 demand data read misses per txn", - "expression": "[MEM_LOAD_RETIRED.L2_MISS] / [TXN]" - }, - { - "name": "L2 demand code MPI", - "expression": "[L2_RQSTS.CODE_RD_MISS] / [instructions]" - }, - { - "name": "L2 demand code misses per txn", - "expression": "[L2_RQSTS.CODE_RD_MISS] / [TXN]" - }, - { - "name": "LLC code read MPI (demand+prefetch)", - "expression": "[UNC_CHA_TOR_INSERTS.IA_MISS_CRD] / [instructions]" - }, - { - "name": "LLC code read (demand+prefetch) misses per txn", - "expression": "[UNC_CHA_TOR_INSERTS.IA_MISS_CRD] / [TXN]" - }, - { - "name": "LLC data read MPI (demand+prefetch)", - "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF]) / [instructions]" - }, - { - "name": "LLC data read (demand+prefetch) misses per txn", - "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF]) / [TXN]" - }, - { - "name": "LLC total HITM (per instr) (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM] / [instructions]" - }, - { - "name": "LLC total HITM per txn (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM] / [TXN]" - }, - { - "name": "LLC total HIT clean line forwards (per instr) (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD] / [instructions]" - }, - { - "name": "LLC total HIT clean line forwards per txn (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD] / [TXN]" - }, - { - "name": "Average LLC demand data read miss latency (in ns)", - "expression": "( 1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) ) ) * 1" - }, - { - "name": "Average LLC demand data read miss latency for LOCAL requests (in ns)", - "expression": "( 1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) ) ) * 1" - }, - { - "name": "Average LLC demand data read miss latency for REMOTE requests (in ns)", - "expression": "( 1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) ) ) * 1" - }, - { - "name": "UPI Data transmit BW (MB/sec) (only data)", - "expression": "([UNC_UPI_TxL_FLITS.ALL_DATA] * (64 / 9.0) / 1000000) / 1" - }, - { - "name": "package power (watts)", - "expression": "[power/energy-pkg/]" - }, - { - "name": "DRAM power (watts)", - "expression": "[power/energy-ram/]" - }, - { - "name": "core c6 residency %", - "expression": "100 * [cstate_core/c6-residency/] / [TSC]" - }, - { - "name": "package c6 residency %", - "expression": "100 * [cstate_pkg/c6-residency/] * [CORES_PER_SOCKET] / [TSC]" - }, - { - "name": "% Uops delivered from decoded Icache (DSB)", - "expression": "100 * ([IDQ.DSB_UOPS] / ([IDQ.DSB_UOPS] + [IDQ.MITE_UOPS] + [IDQ.MS_UOPS] + [LSD.UOPS]) )" - }, - { - "name": "% Uops delivered from legacy decode pipeline (MITE)", - "expression": "100 * ([IDQ.MITE_UOPS] / ([IDQ.DSB_UOPS] + [IDQ.MITE_UOPS] + [IDQ.MS_UOPS] + [LSD.UOPS]) )" - }, - { - "name": "core initiated local dram read bandwidth (MB/sec)", - "expression": "([OCR.READS_TO_CORE.LOCAL_DRAM] + [OCR.HWPF_L3.L3_MISS_LOCAL]) * 64 / 1000000" - }, - { - "name": "core initiated remote dram read bandwidth (MB/sec)", - "expression": "([OCR.READS_TO_CORE.REMOTE_DRAM] + [OCR.HWPF_L3.REMOTE]) * 64 / 1000000" - }, - { - "name": "memory bandwidth read (MB/sec)", - "expression": "([UNC_M_CAS_COUNT.RD] * 64 / 1000000) / 1" - }, - { - "name": "memory bandwidth write (MB/sec)", - "expression": "([UNC_M_CAS_COUNT.WR] * 64 / 1000000) / 1" - }, - { - "name": "memory bandwidth total (MB/sec)", - "expression": "(([UNC_M_CAS_COUNT.RD] + [UNC_M_CAS_COUNT.WR]) * 64 / 1000000) / 1" - }, - { - "name": "ITLB (2nd level) MPI", - "expression": "[ITLB_MISSES.WALK_COMPLETED] / [instructions]" - }, - { - "name": "ITLB (2nd level) misses per txn", - "expression": "[ITLB_MISSES.WALK_COMPLETED] / [TXN]" - }, - { - "name": "DTLB (2nd level) load MPI", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [instructions]" - }, - { - "name": "DTLB (2nd level) load misses per txn", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [TXN]" - }, - { - "name": "DTLB (2nd level) 2MB large page load MPI", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M] / [instructions]" - }, - { - "name": "DTLB (2nd level) 2MB large page load misses per txn", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M] / [TXN]" - }, - { - "name": "DTLB (2nd level) store MPI", - "expression": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [instructions]" - }, - { - "name": "DTLB (2nd level) store misses per txn", - "expression": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [TXN]" - }, - { - "name": "NUMA %_Reads addressed to local DRAM", - "expression": "100 * ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL]) / ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE])" - }, - { - "name": "NUMA %_Reads addressed to remote DRAM", - "expression": "100 * ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE]) / ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE])" - }, - { - "name": "uncore frequency GHz", - "expression": "([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) / 1000000000) / 1" - }, - { - "name": "IO_bandwidth_disk_or_network_writes (MB/sec)", - "expression": "([UNC_CHA_TOR_INSERTS.IO_PCIRDCUR] * 64 / 1000000) / 1" - }, - { - "name": "IO_bandwidth_disk_or_network_reads (MB/sec)", - "expression": "(([UNC_CHA_TOR_INSERTS.IO_ITOM] + [UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR]) * 64 / 1000000) / 1" - }, - { - "name": "TMA_Frontend_Bound(%)", - "expression": "100 * ( [PERF_METRICS.FRONTEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) )" - }, - { - "name": "TMA_..Fetch_Latency(%)", - "expression": "100 * ( ( [PERF_METRICS.FETCH_LATENCY] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) ) )" - }, - { - "name": "TMA_....ICache_Misses(%)", - "expression": "100 * ( [ICACHE_DATA.STALLS] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....ITLB_Misses(%)", - "expression": "100 * ( [ICACHE_TAG.STALLS] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....MS_Switches(%)", - "expression": "100 * ( ( 3 ) * [UOPS_RETIRED.MS:c1:e1] / ( [UOPS_RETIRED.SLOTS] / [UOPS_ISSUED.ANY] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....LCP(%)", - "expression": "100 * ( [DECODE.LCP] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....DSB_Switches(%)", - "expression": "100 * ( [DSB2MITE_SWITCHES.PENALTY_CYCLES] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....Branch_Resteers(%)", - "expression": "100 * ( [INT_MISC.CLEAR_RESTEER_CYCLES] / ( [cpu-cycles] ) + ( [INT_MISC.UNKNOWN_BRANCH_CYCLES] / ( [cpu-cycles] ) ) )" - }, - { - "name": "TMA_......Mispredicts_Resteers(%)", - "expression": "100 * ( ( ( [PERF_METRICS.BRANCH_MISPREDICTS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) / ( max( 1 - ( ( [PERF_METRICS.FRONTEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) ) + ( [PERF_METRICS.BACKEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) , 0 ) ) ) * [INT_MISC.CLEAR_RESTEER_CYCLES] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Clears_Resteers(%)", - "expression": "100 * ( ( 1 - ( ( [PERF_METRICS.BRANCH_MISPREDICTS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) / ( max( 1 - ( ( [PERF_METRICS.FRONTEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) ) + ( [PERF_METRICS.BACKEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) , 0 ) ) ) ) * [INT_MISC.CLEAR_RESTEER_CYCLES] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Unknown_Branches(%)", - "expression": "100 * ( [INT_MISC.UNKNOWN_BRANCH_CYCLES] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_..Fetch_Bandwidth(%)", - "expression": "100 * ( max( 0 , ( [PERF_METRICS.FRONTEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) ) - ( ( [PERF_METRICS.FETCH_LATENCY] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) ) ) ) )" - }, - { - "name": "TMA_....MITE(%)", - "expression": "100 * ( ( [IDQ.MITE_CYCLES_ANY] - [IDQ.MITE_CYCLES_OK] ) / ( [CPU_CLK_UNHALTED.DISTRIBUTED] ) / 2 )" - }, - { - "name": "TMA_....DSB(%)", - "expression": "100 * ( ( [IDQ.DSB_CYCLES_ANY] - [IDQ.DSB_CYCLES_OK] ) / ( [CPU_CLK_UNHALTED.DISTRIBUTED] ) / 2 )" - }, - { - "name": "TMA_Bad_Speculation(%)", - "expression": "100 * ( max( 1 - ( ( [PERF_METRICS.FRONTEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) ) + ( [PERF_METRICS.BACKEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) , 0 ) )" - }, - { - "name": "TMA_..Branch_Mispredicts(%)", - "expression": "100 * ( [PERF_METRICS.BRANCH_MISPREDICTS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) )" - }, - { - "name": "TMA_..Machine_Clears(%)", - "expression": "100 * ( max( 0 , ( max( 1 - ( ( [PERF_METRICS.FRONTEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) - [INT_MISC.UOP_DROPPING] / ( [TOPDOWN.SLOTS] ) ) + ( [PERF_METRICS.BACKEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) , 0 ) ) - ( [PERF_METRICS.BRANCH_MISPREDICTS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) )" - }, - { - "name": "TMA_Backend_Bound(%)", - "expression": "100 * ( [PERF_METRICS.BACKEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) )" - }, - { - "name": "TMA_..Memory_Bound(%)", - "expression": "100 * ( [PERF_METRICS.MEMORY_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) )" - }, - { - "name": "TMA_....L1_Bound(%)", - "expression": "100 * ( max( ( [EXE_ACTIVITY.BOUND_ON_LOADS] - [MEMORY_ACTIVITY.STALLS_L1D_MISS] ) / ( [cpu-cycles] ) , 0 ) )" - }, - { - "name": "TMA_......DTLB_Load(%)", - "expression": "100 * ( min( ( 7 ) * [DTLB_LOAD_MISSES.STLB_HIT:c1] + [DTLB_LOAD_MISSES.WALK_ACTIVE] , max( [CYCLE_ACTIVITY.CYCLES_MEM_ANY] - [MEMORY_ACTIVITY.CYCLES_L1D_MISS] , 0 ) ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Lock_Latency(%)", - "expression": "100 * ( min( ( ( 16 * max( 0 , [MEM_INST_RETIRED.LOCK_LOADS] - [L2_RQSTS.ALL_RFO] ) + ( [MEM_INST_RETIRED.LOCK_LOADS] / [MEM_INST_RETIRED.ALL_STORES] ) * ( ( 10 ) * [L2_RQSTS.RFO_HIT] + ( min( [cpu-cycles] , [OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO] ) ) ) ) / ( [cpu-cycles] ) ) , ( 1 ) ) )" - }, - { - "name": "TMA_....L2_Bound(%)", - "expression": "100 * ( ( [MEMORY_ACTIVITY.STALLS_L1D_MISS] - [MEMORY_ACTIVITY.STALLS_L2_MISS] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....L3_Bound(%)", - "expression": "100 * ( ( [MEMORY_ACTIVITY.STALLS_L2_MISS] - [MEMORY_ACTIVITY.STALLS_L3_MISS] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Data_Sharing(%)", - "expression": "100 * ( min( ( ( ( 79.5 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( 1000 / 1000 ) ) ) - ( 4 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( 1000 / 1000 ) ) ) ) * ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD] + [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD] * ( 1 - ( [OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM] / ( [OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM] + [OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD] ) ) ) ) * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) / 2 ) / ( [cpu-cycles] ) ) , ( 1 ) ) )" - }, - { - "name": "TMA_....DRAM_Bound(%)", - "expression": "100 * ( min( ( ( ( [MEMORY_ACTIVITY.STALLS_L3_MISS] / ( [cpu-cycles] ) ) - ( min( ( ( ( ( 1 - ( ( ( 19 * ( [MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) + 10 * ( ( [MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) + ( [MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) + ( [MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) ) ) / ( ( 19 * ( [MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) + 10 * ( ( [MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) + ( [MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) + ( [MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) ) ) + ( 25 * ( ( [MEM_LOAD_RETIRED.LOCAL_PMM] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) ) + 33 * ( ( [MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM] * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) ) ) ) ) ) ) ) ) * ( [MEMORY_ACTIVITY.STALLS_L3_MISS] / ( [cpu-cycles] ) ) ) if ( ( 1000000 ) * ( [MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM] + [MEM_LOAD_RETIRED.LOCAL_PMM] ) > [MEM_LOAD_RETIRED.L1_MISS] ) else 0 ) ) , ( 1 ) ) ) ) ) , ( 1 ) ) )" - }, - { - "name": "TMA_......MEM_Bandwidth(%)", - "expression": "100 * ( ( min( [cpu-cycles] , [OFFCORE_REQUESTS_OUTSTANDING.DATA_RD:c4] ) ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......MEM_Latency(%)", - "expression": "100 * ( ( min( [cpu-cycles] , [OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD] ) ) / ( [cpu-cycles] ) - ( ( min( [cpu-cycles] , [OFFCORE_REQUESTS_OUTSTANDING.DATA_RD:c4] ) ) / ( [cpu-cycles] ) ) )" - }, - { - "name": "TMA_....Store_Bound(%)", - "expression": "100 * ( [EXE_ACTIVITY.BOUND_ON_STORES] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......False_Sharing(%)", - "expression": "100 * ( min( ( ( 80 * ( ( ( [cpu-cycles] ) / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( 1000 / 1000 ) ) ) * [OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM] / ( [cpu-cycles] ) ) , ( 1 ) ) )" - }, - { - "name": "TMA_..Core_Bound(%)", - "expression": "100 * ( max( 0 , ( [PERF_METRICS.BACKEND_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) - ( [PERF_METRICS.MEMORY_BOUND] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) )" - }, - { - "name": "TMA_....Divider(%)", - "expression": "100 * ( [ARITH.DIV_ACTIVE] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....AMX_Busy(%)", - "expression": "100 * ( [EXE.AMX_BUSY] / ( [CPU_CLK_UNHALTED.DISTRIBUTED] if [HYPERTHREADING_ON] else ( [cpu-cycles] ) ) )" - }, - { - "name": "TMA_....Ports_Utilization(%)", - "expression": "100 * ( ( [EXE_ACTIVITY.3_PORTS_UTIL:u0x80] + ( [RESOURCE_STALLS.SCOREBOARD] / ( [cpu-cycles] ) ) * ( [CYCLE_ACTIVITY.STALLS_TOTAL] - [EXE_ACTIVITY.BOUND_ON_LOADS] ) + ( [EXE_ACTIVITY.1_PORTS_UTIL] + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * [EXE_ACTIVITY.2_PORTS_UTIL:u0xc] ) ) / ( [cpu-cycles] ) if ( [ARITH.DIV_ACTIVE] < ( [CYCLE_ACTIVITY.STALLS_TOTAL] - [EXE_ACTIVITY.BOUND_ON_LOADS] ) ) else ( [EXE_ACTIVITY.1_PORTS_UTIL] + ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * [EXE_ACTIVITY.2_PORTS_UTIL:u0xc] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Ports_Utilized_0(%)", - "expression": "100 * ( [EXE_ACTIVITY.3_PORTS_UTIL:u0x80] / ( [cpu-cycles] ) + ( [RESOURCE_STALLS.SCOREBOARD] / ( [cpu-cycles] ) ) * ( [CYCLE_ACTIVITY.STALLS_TOTAL] - [EXE_ACTIVITY.BOUND_ON_LOADS] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_........AMX_Busy(%)", - "expression": "100 * ( [EXE.AMX_BUSY] / ( [CPU_CLK_UNHALTED.DISTRIBUTED] ) )" - }, - { - "name": "TMA_......Ports_Utilized_1(%)", - "expression": "100 * ( [EXE_ACTIVITY.1_PORTS_UTIL] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Ports_Utilized_2(%)", - "expression": "100 * ( [EXE_ACTIVITY.2_PORTS_UTIL] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_......Ports_Utilized_3m(%)", - "expression": "100 * ( [UOPS_EXECUTED.CYCLES_GE_3] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_Retiring(%)", - "expression": "100 * ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) )" - }, - { - "name": "TMA_..Light_Operations(%)", - "expression": "100 * ( max( 0 , ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) - ( [PERF_METRICS.HEAVY_OPERATIONS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) )" - }, - { - "name": "TMA_....Memory_Operations(%)", - "expression": "100 * ( ( max( 0 , ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) - ( [PERF_METRICS.HEAVY_OPERATIONS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) ) * [MEM_UOP_RETIRED.ANY] / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) )" - }, - { - "name": "TMA_....Fused_Instructions(%)", - "expression": "100 * ( ( max( 0 , ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) - ( [PERF_METRICS.HEAVY_OPERATIONS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) ) * [INST_RETIRED.MACRO_FUSED] / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) )" - }, - { - "name": "TMA_....Non_Fused_Branches(%)", - "expression": "100 * ( ( max( 0 , ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) - ( [PERF_METRICS.HEAVY_OPERATIONS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) ) ) * ( [BR_INST_RETIRED.ALL_BRANCHES] - [INST_RETIRED.MACRO_FUSED] ) / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) )" - }, - { - "name": "TMA_........FP_Vector_256b(%)", - "expression": "100 * ( min( ( ( [FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE] + [FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE] + [FP_ARITH_INST_RETIRED2.256B_PACKED_HALF] ) / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) ) , ( 1 ) ) )" - }, - { - "name": "TMA_........FP_Vector_512b(%)", - "expression": "100 * ( min( ( ( [FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE] + [FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE] + [FP_ARITH_INST_RETIRED2.512B_PACKED_HALF] ) / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) ) , ( 1 ) ) )" - }, - { - "name": "TMA_......Int_Vector_256b(%)", - "expression": "100 * ( ( [INT_VEC_RETIRED.ADD_256] + [INT_VEC_RETIRED.MUL_256] + [INT_VEC_RETIRED.VNNI_256] ) / ( ( [PERF_METRICS.RETIRING] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) * ( [TOPDOWN.SLOTS] ) ) )" - }, - { - "name": "TMA_..Heavy_Operations(%)", - "expression": "100 * ( [PERF_METRICS.HEAVY_OPERATIONS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) )" - }, - { - "name": "TMA_....Few_Uops_Instructions(%)", - "expression": "100 * ( max( 0 , ( [PERF_METRICS.HEAVY_OPERATIONS] / ( [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND] ) ) - ( [UOPS_RETIRED.MS] / ( [TOPDOWN.SLOTS] ) ) ) )" - }, - { - "name": "TMA_....Microcode_Sequencer(%)", - "expression": "100 * ( [UOPS_RETIRED.MS] / ( [TOPDOWN.SLOTS] ) )" - }, - { - "name": "TMA_Info_Thread_IPC", - "expression": "[instructions] / [cpu-cycles]" - }, - { - "name": "TMA_Info_System_SMT_2T_Utilization", - "expression": "(1 - [CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE] / [CPU_CLK_UNHALTED.REF_DISTRIBUTED]) if [SOCKET_COUNT] > 1 else 0" - } -] \ No newline at end of file diff --git a/cmd/metrics/resources/metrics/x86_64/GenuineIntel/spr_nofixedtma.json b/cmd/metrics/resources/metrics/x86_64/GenuineIntel/spr_nofixedtma.json deleted file mode 100644 index a9e07ed4..00000000 --- a/cmd/metrics/resources/metrics/x86_64/GenuineIntel/spr_nofixedtma.json +++ /dev/null @@ -1,378 +0,0 @@ -[ - { - "name": "CPU operating frequency (in GHz)", - "expression": "(([cpu-cycles] / [ref-cycles] * [SYSTEM_TSC_FREQ]) / 1000000000)" - }, - { - "name": "CPU utilization %", - "expression": "100 * [ref-cycles] / [TSC]" - }, - { - "name": "CPU utilization% in kernel mode", - "expression": "100 * [ref-cycles:k] / [TSC]" - }, - { - "name": "CPI", - "expression": "[cpu-cycles] / [instructions]" - }, - { - "name": "cycles per txn", - "expression": "[cpu-cycles] / [TXN]" - }, - { - "name": "kernel_CPI", - "expression": "[cpu-cycles:k] / [instructions:k]" - }, - { - "name": "kernel_cycles per txn", - "expression": "[cpu-cycles:k] / [TXN]" - }, - { - "name": "IPC", - "expression": "[instructions] / [cpu-cycles]" - }, - { - "name": "txn per cycle", - "expression": "[TXN] / [cpu-cycles]" - }, - { - "name": "giga_instructions_per_sec", - "expression": "[instructions] / 1000000000" - }, - { - "name": "branch misprediction ratio", - "expression": "[BR_MISP_RETIRED.ALL_BRANCHES] / [BR_INST_RETIRED.ALL_BRANCHES]" - }, - { - "name": "locks retired per instr", - "expression": "[MEM_INST_RETIRED.LOCK_LOADS] / [instructions]" - }, - { - "name": "locks retired per txn", - "expression": "[MEM_INST_RETIRED.LOCK_LOADS] / [TXN]" - }, - { - "name": "L1D MPI (includes data+rfo w/ prefetches)", - "expression": "[L1D.REPLACEMENT] / [instructions]" - }, - { - "name": "L1D misses per txn (includes data+rfo w/ prefetches)", - "expression": "[L1D.REPLACEMENT] / [TXN]" - }, - { - "name": "L1D demand data read hits per instr", - "expression": "[MEM_LOAD_RETIRED.L1_HIT] / [instructions]" - }, - { - "name": "L1D demand data read hits per txn", - "expression": "[MEM_LOAD_RETIRED.L1_HIT] / [TXN]" - }, - { - "name": "L1-I code read misses (w/ prefetches) per instr", - "expression": "[L2_RQSTS.ALL_CODE_RD] / [instructions]" - }, - { - "name": "L1I code read misses (includes prefetches) per txn", - "expression": "[L2_RQSTS.ALL_CODE_RD] / [TXN]" - }, - { - "name": "L2 demand data read hits per instr", - "expression": "[MEM_LOAD_RETIRED.L2_HIT] / [instructions]" - }, - { - "name": "L2 demand data read hits per txn", - "expression": "[MEM_LOAD_RETIRED.L2_HIT] / [TXN]" - }, - { - "name": "L2 MPI (includes code+data+rfo w/ prefetches)", - "expression": "[L2_LINES_IN.ALL] / [instructions]" - }, - { - "name": "L2 misses per txn (includes code+data+rfo w/ prefetches)", - "expression": "[L2_LINES_IN.ALL] / [TXN]" - }, - { - "name": "L2 demand data read MPI", - "expression": "[MEM_LOAD_RETIRED.L2_MISS] / [instructions]" - }, - { - "name": "L2 demand data read misses per txn", - "expression": "[MEM_LOAD_RETIRED.L2_MISS] / [TXN]" - }, - { - "name": "L2 demand code MPI", - "expression": "[L2_RQSTS.CODE_RD_MISS] / [instructions]" - }, - { - "name": "L2 demand code misses per txn", - "expression": "[L2_RQSTS.CODE_RD_MISS] / [TXN]" - }, - { - "name": "LLC code read MPI (demand+prefetch)", - "expression": "[UNC_CHA_TOR_INSERTS.IA_MISS_CRD] / [instructions]" - }, - { - "name": "LLC code read (demand+prefetch) misses per txn", - "expression": "[UNC_CHA_TOR_INSERTS.IA_MISS_CRD] / [TXN]" - }, - { - "name": "LLC data read MPI (demand+prefetch)", - "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF]) / [instructions]" - }, - { - "name": "LLC data read (demand+prefetch) misses per txn", - "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF]) / [TXN]" - }, - { - "name": "LLC total HITM (per instr) (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM] / [instructions]" - }, - { - "name": "LLC total HITM per txn (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM] / [TXN]" - }, - { - "name": "LLC total HIT clean line forwards (per instr) (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD] / [instructions]" - }, - { - "name": "LLC total HIT clean line forwards per txn (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD] / [TXN]" - }, - { - "name": "Average LLC demand data read miss latency (in ns)", - "expression": "( 1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) ) ) * 1" - }, - { - "name": "Average LLC demand data read miss latency for LOCAL requests (in ns)", - "expression": "( 1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) ) ) * 1" - }, - { - "name": "Average LLC demand data read miss latency for REMOTE requests (in ns)", - "expression": "( 1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) ) ) * 1" - }, - { - "name": "UPI Data transmit BW (MB/sec) (only data)", - "expression": "([UNC_UPI_TxL_FLITS.ALL_DATA] * (64 / 9.0) / 1000000) / 1" - }, - { - "name": "package power (watts)", - "expression": "[power/energy-pkg/]" - }, - { - "name": "DRAM power (watts)", - "expression": "[power/energy-ram/]" - }, - { - "name": "core c6 residency %", - "expression": "100 * [cstate_core/c6-residency/] / [TSC]" - }, - { - "name": "package c6 residency %", - "expression": "100 * [cstate_pkg/c6-residency/] * [CORES_PER_SOCKET] / [TSC]" - }, - { - "name": "% Uops delivered from decoded Icache (DSB)", - "expression": "100 * ([IDQ.DSB_UOPS] / ([IDQ.DSB_UOPS] + [IDQ.MITE_UOPS] + [IDQ.MS_UOPS] + [LSD.UOPS]) )" - }, - { - "name": "% Uops delivered from legacy decode pipeline (MITE)", - "expression": "100 * ([IDQ.MITE_UOPS] / ([IDQ.DSB_UOPS] + [IDQ.MITE_UOPS] + [IDQ.MS_UOPS] + [LSD.UOPS]) )" - }, - { - "name": "core initiated local dram read bandwidth (MB/sec)", - "expression": "([OCR.READS_TO_CORE.LOCAL_DRAM] + [OCR.HWPF_L3.L3_MISS_LOCAL]) * 64 / 1000000" - }, - { - "name": "core initiated remote dram read bandwidth (MB/sec)", - "expression": "([OCR.READS_TO_CORE.REMOTE_DRAM] + [OCR.HWPF_L3.REMOTE]) * 64 / 1000000" - }, - { - "name": "memory bandwidth read (MB/sec)", - "expression": "([UNC_M_CAS_COUNT.RD] * 64 / 1000000) / 1" - }, - { - "name": "memory bandwidth write (MB/sec)", - "expression": "([UNC_M_CAS_COUNT.WR] * 64 / 1000000) / 1" - }, - { - "name": "memory bandwidth total (MB/sec)", - "expression": "(([UNC_M_CAS_COUNT.RD] + [UNC_M_CAS_COUNT.WR]) * 64 / 1000000) / 1" - }, - { - "name": "ITLB (2nd level) MPI", - "expression": "[ITLB_MISSES.WALK_COMPLETED] / [instructions]" - }, - { - "name": "ITLB (2nd level) misses per txn", - "expression": "[ITLB_MISSES.WALK_COMPLETED] / [TXN]" - }, - { - "name": "DTLB (2nd level) load MPI", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [instructions]" - }, - { - "name": "DTLB (2nd level) load misses per txn", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [TXN]" - }, - { - "name": "DTLB (2nd level) 2MB large page load MPI", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M] / [instructions]" - }, - { - "name": "DTLB (2nd level) 2MB large page load misses per txn", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M] / [TXN]" - }, - { - "name": "DTLB (2nd level) store MPI", - "expression": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [instructions]" - }, - { - "name": "DTLB (2nd level) store misses per txn", - "expression": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [TXN]" - }, - { - "name": "NUMA %_Reads addressed to local DRAM", - "expression": "100 * ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL]) / ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE])" - }, - { - "name": "NUMA %_Reads addressed to remote DRAM", - "expression": "100 * ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE]) / ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE])" - }, - { - "name": "uncore frequency GHz", - "expression": "([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) / 1000000000) / 1" - }, - { - "name": "IO_bandwidth_disk_or_network_writes (MB/sec)", - "expression": "([UNC_CHA_TOR_INSERTS.IO_PCIRDCUR] * 64 / 1000000) / 1" - }, - { - "name": "IO_bandwidth_disk_or_network_reads (MB/sec)", - "expression": "(([UNC_CHA_TOR_INSERTS.IO_ITOM] + [UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR]) * 64 / 1000000) / 1" - }, - { - "name": "TMA_Frontend_Bound(%)", - "expression": "100 * ( ( [IDQ_UOPS_NOT_DELIVERED.CORE] - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS_P] ) )" - }, - { - "name": "TMA_..Fetch_Latency(%)", - "expression": "100 * ( ( [IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE] * ( 6 ) - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS_P] ) )" - }, - { - "name": "TMA_....ICache_Misses(%)", - "expression": "100 * ( [ICACHE_DATA.STALLS] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....ITLB_Misses(%)", - "expression": "100 * ( [ICACHE_TAG.STALLS] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....MS_Switches(%)", - "expression": "100 * ( ( 3 ) * [UOPS_RETIRED.MS:c1:e1] / ( [UOPS_RETIRED.SLOTS] / [UOPS_ISSUED.ANY] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....LCP(%)", - "expression": "100 * ( [DECODE.LCP] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....DSB_Switches(%)", - "expression": "100 * ( [DSB2MITE_SWITCHES.PENALTY_CYCLES] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_..Fetch_Bandwidth(%)", - "expression": "100 * ( max( 0 , ( ( [IDQ_UOPS_NOT_DELIVERED.CORE] - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS_P] ) ) - ( ( [IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE] * ( 6 ) - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS_P] ) ) ) )" - }, - { - "name": "TMA_....MITE(%)", - "expression": "100 * ( ( [IDQ.MITE_CYCLES_ANY] - [IDQ.MITE_CYCLES_OK] ) / ( [CPU_CLK_UNHALTED.DISTRIBUTED] ) / 2 )" - }, - { - "name": "TMA_....DSB(%)", - "expression": "100 * ( ( [IDQ.DSB_CYCLES_ANY] - [IDQ.DSB_CYCLES_OK] ) / ( [CPU_CLK_UNHALTED.DISTRIBUTED] ) / 2 )" - }, - { - "name": "TMA_Bad_Speculation(%)", - "expression": "100 * ( max( 1 - ( ( ( [IDQ_UOPS_NOT_DELIVERED.CORE] - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS_P] ) ) + ( [TOPDOWN.BACKEND_BOUND_SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) + ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) ) , 0 ) )" - }, - { - "name": "TMA_..Branch_Mispredicts(%)", - "expression": "100 * ( [TOPDOWN.BR_MISPREDICT_SLOTS] / ( [TOPDOWN.SLOTS_P] ) )" - }, - { - "name": "TMA_..Machine_Clears(%)", - "expression": "100 * ( max( 0 , ( max( 1 - ( ( ( [IDQ_UOPS_NOT_DELIVERED.CORE] - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS_P] ) ) + ( [TOPDOWN.BACKEND_BOUND_SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) + ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) ) , 0 ) ) - ( [TOPDOWN.BR_MISPREDICT_SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) ) )" - }, - { - "name": "TMA_Backend_Bound(%)", - "expression": "100 * ( [TOPDOWN.BACKEND_BOUND_SLOTS] / ( [TOPDOWN.SLOTS_P] ) )" - }, - { - "name": "TMA_..Memory_Bound(%)", - "expression": "100 * ( [TOPDOWN.MEMORY_BOUND_SLOTS] / ( [TOPDOWN.SLOTS_P] ) )" - }, - { - "name": "TMA_....L1_Bound(%)", - "expression": "100 * ( max( ( [EXE_ACTIVITY.BOUND_ON_LOADS] - [MEMORY_ACTIVITY.STALLS_L1D_MISS] ) / ( [cpu-cycles] ) , 0 ) )" - }, - { - "name": "TMA_....L2_Bound(%)", - "expression": "100 * ( ( [MEMORY_ACTIVITY.STALLS_L1D_MISS] - [MEMORY_ACTIVITY.STALLS_L2_MISS] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....L3_Bound(%)", - "expression": "100 * ( ( [MEMORY_ACTIVITY.STALLS_L2_MISS] - [MEMORY_ACTIVITY.STALLS_L3_MISS] ) / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....DRAM_Bound(%)", - "expression": "100 * ( ( [MEMORY_ACTIVITY.STALLS_L3_MISS] / ( [cpu-cycles] ) ) )" - }, - { - "name": "TMA_....Store_Bound(%)", - "expression": "100 * ( [EXE_ACTIVITY.BOUND_ON_STORES] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_..Core_Bound(%)", - "expression": "100 * ( max( 0 , ( [TOPDOWN.BACKEND_BOUND_SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) - ( [TOPDOWN.MEMORY_BOUND_SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) ) )" - }, - { - "name": "TMA_....Divider(%)", - "expression": "100 * ( [ARITH.DIV_ACTIVE] / ( [cpu-cycles] ) )" - }, - { - "name": "TMA_....AMX_Busy(%)", - "expression": "100 * ( [EXE.AMX_BUSY] / ( [CPU_CLK_UNHALTED.DISTRIBUTED] ) )" - }, - { - "name": "TMA_Retiring(%)", - "expression": "100 * ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) )" - }, - { - "name": "TMA_..Light_Operations(%)", - "expression": "100 * ( max( 0 , ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) - ( [UOPS_RETIRED.HEAVY] / ( [TOPDOWN.SLOTS_P] ) ) ) )" - }, - { - "name": "TMA_....Memory_Operations(%)", - "expression": "100 * ( ( max( 0 , ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) - ( [UOPS_RETIRED.HEAVY] / ( [TOPDOWN.SLOTS_P] ) ) ) ) * [MEM_UOP_RETIRED.ANY] / ( ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) * ( [TOPDOWN.SLOTS_P] ) ) )" - }, - { - "name": "TMA_....Fused_Instructions(%)", - "expression": "100 * ( ( max( 0 , ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) - ( [UOPS_RETIRED.HEAVY] / ( [TOPDOWN.SLOTS_P] ) ) ) ) * [INST_RETIRED.MACRO_FUSED] / ( ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) * ( [TOPDOWN.SLOTS_P] ) ) )" - }, - { - "name": "TMA_....Non_Fused_Branches(%)", - "expression": "100 * ( ( max( 0 , ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) - ( [UOPS_RETIRED.HEAVY] / ( [TOPDOWN.SLOTS_P] ) ) ) ) * ( [BR_INST_RETIRED.ALL_BRANCHES] - [INST_RETIRED.MACRO_FUSED] ) / ( ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) * ( [TOPDOWN.SLOTS_P] ) ) )" - }, - { - "name": "TMA_..Heavy_Operations(%)", - "expression": "100 * ( [UOPS_RETIRED.HEAVY] / ( [TOPDOWN.SLOTS_P] ) )" - }, - { - "name": "TMA_....Few_Uops_Instructions(%)", - "expression": "100 * ( max( 0 , ( [UOPS_RETIRED.HEAVY] / ( [TOPDOWN.SLOTS_P] ) ) - ( [UOPS_RETIRED.MS] / ( [TOPDOWN.SLOTS_P] ) ) ) )" - }, - { - "name": "TMA_....Microcode_Sequencer(%)", - "expression": "100 * ( [UOPS_RETIRED.MS] / ( [TOPDOWN.SLOTS_P] ) )" - } -] \ No newline at end of file diff --git a/cmd/metrics/resources/metrics/x86_64/GenuineIntel/srf.json b/cmd/metrics/resources/metrics/x86_64/GenuineIntel/srf.json deleted file mode 100644 index 8c657d61..00000000 --- a/cmd/metrics/resources/metrics/x86_64/GenuineIntel/srf.json +++ /dev/null @@ -1,350 +0,0 @@ -[ - { - "name": "CPU operating frequency (in GHz)", - "expression": "(([cpu-cycles] / [ref-cycles] * [SYSTEM_TSC_FREQ]) / 1000000000)" - }, - { - "name": "CPU utilization %", - "expression": "100 * [ref-cycles] / [TSC]" - }, - { - "name": "CPU utilization% in kernel mode", - "expression": "100 * [ref-cycles:k] / [TSC]" - }, - { - "name": "CPI", - "expression": "[cpu-cycles] / [instructions]" - }, - { - "name": "cycles per txn", - "expression": "[cpu-cycles] / [TXN]" - }, - { - "name": "kernel_CPI", - "expression": "[cpu-cycles:k] / [instructions:k]" - }, - { - "name": "kernel_cycles per txn", - "expression": "[cpu-cycles:k] / [TXN]" - }, - { - "name": "IPC", - "expression": "[instructions] / [cpu-cycles]" - }, - { - "name": "txn per cycle", - "expression": "[TXN] / [cpu-cycles]" - }, - { - "name": "giga_instructions_per_sec", - "expression": "[instructions] / 1000000000" - }, - { - "name": "branch misprediction ratio", - "expression": "[BR_MISP_RETIRED.ALL_BRANCHES] / [BR_INST_RETIRED.ALL_BRANCHES]" - }, - { - "name": "locks retired per instr", - "expression": "[MEM_UOPS_RETIRED.LOCK_LOADS] / [instructions]" - }, - { - "name": "locks retired per txn", - "expression": "[MEM_UOPS_RETIRED.LOCK_LOADS] / [TXN]" - }, - { - "name": "L1D demand data read MPI", - "expression": "[MEM_LOAD_UOPS_RETIRED.L1_MISS] / [instructions]" - }, - { - "name": "L1D demand data read misses per txn", - "expression": "[MEM_LOAD_UOPS_RETIRED.L1_MISS] / [TXN]" - }, - { - "name": "L1D demand data read hits per instr", - "expression": "[MEM_LOAD_UOPS_RETIRED.L1_HIT] / [instructions]" - }, - { - "name": "L1D demand data read hits per txn", - "expression": "[MEM_LOAD_UOPS_RETIRED.L1_HIT] / [TXN]" - }, - { - "name": "L1-I code read misses (w/ prefetches) per instr", - "expression": "[ICACHE.MISSES] / [instructions]" - }, - { - "name": "L1-I code read misses (w/ prefetches) per txn", - "expression": "[ICACHE.MISSES] / [TXN]" - }, - { - "name": "L2 demand data read hits per instr", - "expression": "[MEM_LOAD_UOPS_RETIRED.L2_HIT] / [instructions]" - }, - { - "name": "L2 demand data read hits per txn", - "expression": "[MEM_LOAD_UOPS_RETIRED.L2_HIT] / [TXN]" - }, - { - "name": "L2 MPI (includes code+data+rfo w/ prefetches)", - "expression": "[LONGEST_LAT_CACHE.REFERENCE] / [instructions]" - }, - { - "name": "L2 misses per txn (includes code+data+rfo w/ prefetches)", - "expression": "[LONGEST_LAT_CACHE.REFERENCE] / [TXN]" - }, - { - "name": "L2 code MPI", - "expression": "[OCR.L2_CODE_MISS] / [instructions]" - }, - { - "name": "L2 code misses per txn", - "expression": "[OCR.L2_CODE_MISS] / [TXN]" - }, - { - "name": "L2 Any local request that HITM in another module (per instr)", - "expression": "[OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM] / [instructions]" - }, - { - "name": "L2 Any local request that HITM in another module per txn", - "expression": "[OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM] / [TXN]" - }, - { - "name": "L2 Any local request that HIT in another module and forwarded(per instr)", - "expression": "[OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD] / [instructions]" - }, - { - "name": "L2 Any local request that HIT in another module and forwarded per txn", - "expression": "[OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD] / [TXN]" - }, - { - "name": "L2 all L2 prefetches(per instr)", - "expression": "[OCR.HWPF_L2.ANY_RESPONSE] / [instructions]" - }, - { - "name": "L2 all L2 prefetches per txn", - "expression": "[OCR.HWPF_L2.ANY_RESPONSE] / [TXN]" - }, - { - "name": "data_read_L2_Miss_Latency_using_ORO_events(ns)", - "expression": "( 1000000000 * ([OCR.READS_TO_CORE.OUTSTANDING] / [OCR.READS_TO_CORE.ANY_RESPONSE]) / ([cpu-cycles] / [TSC] * [SYSTEM_TSC_FREQ]) )" - }, - { - "name": "L3 MPI (includes code+data+rfo w/ prefetches)", - "expression": "[LONGEST_LAT_CACHE.MISS] / [instructions]" - }, - { - "name": "L3 misses per txn (includes code+data+rfo w/ prefetches)", - "expression": "[LONGEST_LAT_CACHE.MISS] / [TXN]" - }, - { - "name": "LLC MPI (includes code+data+rfo w/ prefetches)", - "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_CRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF] + [UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA] + [UNC_CHA_TOR_INSERTS.IA_MISS_RFO] + [UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF] + [UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO]) / [instructions]" - }, - { - "name": "LLC misses per txn (includes code+data+rfo w/ prefetches)", - "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_CRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF] + [UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA] + [UNC_CHA_TOR_INSERTS.IA_MISS_RFO] + [UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF] + [UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO]) / [TXN]" - }, - { - "name": "LLC total HITM (per instr)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM] / [instructions]" - }, - { - "name": "LLC total HITM per txn (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM] / [TXN]" - }, - { - "name": "LLC total HIT clean line forwards (per instr)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD] / [instructions]" - }, - { - "name": "LLC total HIT clean line forwards per txn (excludes LLC prefetches)", - "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD] / [TXN]" - }, - { - "name": "LLC data read MPI (demand+prefetch)", - "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF] + [UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA]) / [instructions]" - }, - { - "name": "LLC data read (demand+prefetch) misses per txn", - "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF] + [UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA]) / [TXN]" - }, - { - "name": "LLC code read MPI (demand+prefetch)", - "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_CRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF]) / [instructions]" - }, - { - "name": "LLC code read (demand+prefetch) misses per txn", - "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_CRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF]) / [TXN]" - }, - { - "name": "Average LLC demand data read miss latency (in ns)", - "expression": "( 1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) ) ) * 1" - }, - { - "name": "Average LLC demand RFO miss latency (in ns)", - "expression": "( 1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO] / [UNC_CHA_TOR_INSERTS.IA_MISS_RFO]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) ) ) * 1" - }, - { - "name": "core initiated local dram read bandwidth (MB/sec)", - "expression": "([LONGEST_LAT_CACHE.MISS]) * 64 / 1000000" - }, - { - "name": "memory bandwidth read (MB/sec)", - "expression": "(([UNC_M_CAS_COUNT_SCH0.RD] + [UNC_M_CAS_COUNT_SCH1.RD]) * 64 / 1000000) / 1" - }, - { - "name": "memory bandwidth write (MB/sec)", - "expression": "(([UNC_M_CAS_COUNT_SCH0.WR] + [UNC_M_CAS_COUNT_SCH1.WR]) * 64 / 1000000) / 1" - }, - { - "name": "memory bandwidth total (MB/sec)", - "expression": "(([UNC_M_CAS_COUNT_SCH0.RD] + [UNC_M_CAS_COUNT_SCH1.RD] + [UNC_M_CAS_COUNT_SCH0.WR] + [UNC_M_CAS_COUNT_SCH1.WR]) * 64 / 1000000) / 1" - }, - { - "name": "IO_bandwidth_disk_or_network_writes (MB/sec)", - "expression": "([UNC_CHA_TOR_INSERTS.IO_PCIRDCUR] * 64 / 1000000) / 1" - }, - { - "name": "IO_bandwidth_disk_or_network_reads (MB/sec)", - "expression": "(([UNC_CHA_TOR_INSERTS.IO_ITOM] + [UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR]) * 64 / 1000000) / 1" - }, - { - "name": "package power (watts)", - "expression": "[power/energy-pkg/]" - }, - { - "name": "DRAM power (watts)", - "expression": "[power/energy-ram/]" - }, - { - "name": "core c6 residency %", - "expression": "100 * [cstate_core/c6-residency/] / [TSC]" - }, - { - "name": "package c6 residency %", - "expression": "100 * [cstate_pkg/c6-residency/] * [CORES_PER_SOCKET] / [TSC]" - }, - { - "name": "uncore frequency GHz", - "expression": "([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) / 1000000000) / 1" - }, - { - "name": "ITLB (2nd level) MPI", - "expression": "[ITLB_MISSES.WALK_COMPLETED] / [instructions]" - }, - { - "name": "ITLB (2nd level) misses per txn", - "expression": "[ITLB_MISSES.WALK_COMPLETED] / [TXN]" - }, - { - "name": "DTLB (2nd level) load MPI", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [instructions]" - }, - { - "name": "DTLB (2nd level) load misses per txn", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [TXN]" - }, - { - "name": "DTLB (2nd level) 4KB page load MPI", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED_4K] / [instructions]" - }, - { - "name": "DTLB (2nd level) 4KB page load misses per txn", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED_4K] / [TXN]" - }, - { - "name": "DTLB (2nd level) 2MB large page load MPI", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M] / [instructions]" - }, - { - "name": "DTLB (2nd level) 2MB large page load misses per txn", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M] / [TXN]" - }, - { - "name": "DTLB (2nd level) 1GB large page load MPI", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED_1G] / [instructions]" - }, - { - "name": "DTLB (2nd level) 1GB large page load misses per txn", - "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED_1G] / [TXN]" - }, - { - "name": "DTLB (2nd level) store MPI", - "expression": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [instructions]" - }, - { - "name": "DTLB (2nd level) store misses per txn", - "expression": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [TXN]" - }, - { - "name": "TMA_Frontend_Bound(%)", - "expression": "100 * ( [TOPDOWN_FE_BOUND.ALL] / ( 6 * [cpu-cycles] ) )" - }, - { - "name": "TMA_..Fetch_Latency(%)", - "expression": "100*([TOPDOWN_FE_BOUND.FRONTEND_LATENCY] / (6.0 * [cpu-cycles]))" - }, - { - "name": "TMA_....ICache_Misses(%)", - "expression": "100 * ( [TOPDOWN_FE_BOUND.ICACHE] / ( 6 * [cpu-cycles] ) )" - }, - { - "name": "TMA_....ITLB_Misses(%)", - "expression": "100 * ( [TOPDOWN_FE_BOUND.ITLB_MISS] / ( 6 * [cpu-cycles] ) )" - }, - { - "name": "TMA_....Branch_Resteer(%)", - "expression": "100*([TOPDOWN_FE_BOUND.BRANCH_RESTEER] / (6.0 * [cpu-cycles]))" - }, - { - "name": "TMA_..Fetch_Bandwidth(%)", - "expression": "100*([TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH] / (6.0 * [cpu-cycles]))" - }, - { - "name": "TMA_Bad_Speculation(%)", - "expression": "100 * ( [TOPDOWN_BAD_SPECULATION.ALL] / ( 6 * [cpu-cycles] ) )" - }, - { - "name": "TMA_..Branch_Mispredicts(%)", - "expression": "100*([TOPDOWN_BAD_SPECULATION.MISPREDICT] / (6.0 * [cpu-cycles]))" - }, - { - "name": "TMA_..Machine_Clears(%)", - "expression": "100*([TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS] / (6.0 * [cpu-cycles]))" - }, - { - "name": "TMA_Backend_Bound(%)", - "expression": "100 * ( [TOPDOWN_BE_BOUND.ALL] / ( 6 * [cpu-cycles] ) )" - }, - { - "name": "TMA_..Memory_Bound(%)", - "expression": "100*min(1*([TOPDOWN_BE_BOUND.ALL] / (6.0 * [cpu-cycles])), 1*([LD_HEAD.ANY_AT_RET] / [cpu-cycles] + ([TOPDOWN_BE_BOUND.MEM_SCHEDULER] / (6.0 * [cpu-cycles])) * [MEM_SCHEDULER_BLOCK.ST_BUF] / [MEM_SCHEDULER_BLOCK.ALL]))" - }, - { - "name": "TMA_....L1_Bound(%)", - "expression": "100*([LD_HEAD.L1_BOUND_AT_RET] / [cpu-cycles])" - }, - { - "name": "TMA_....L2_Bound(%)", - "expression": "100*([MEM_BOUND_STALLS_LOAD.L2_HIT] / [cpu-cycles] - (max(1*(([MEM_BOUND_STALLS_LOAD.ALL] - [LD_HEAD.L1_MISS_AT_RET]) / [cpu-cycles]), 0) * [MEM_BOUND_STALLS_LOAD.L2_HIT] / [MEM_BOUND_STALLS_LOAD.ALL]))" - }, - { - "name": "TMA_....L3_Bound(%)", - "expression": "100*([MEM_BOUND_STALLS_LOAD.LLC_HIT] / [cpu-cycles] - (max(1*(([MEM_BOUND_STALLS_LOAD.ALL] - [LD_HEAD.L1_MISS_AT_RET]) / [cpu-cycles]), 0) * [MEM_BOUND_STALLS_LOAD.LLC_HIT] / [MEM_BOUND_STALLS_LOAD.ALL]))" - }, - { - "name": "TMA_....Store_Bound(%)", - "expression": "100*(([TOPDOWN_BE_BOUND.MEM_SCHEDULER] / (6.0 * [cpu-cycles])) * [MEM_SCHEDULER_BLOCK.ST_BUF] / [MEM_SCHEDULER_BLOCK.ALL])" - }, - { - "name": "TMA_..Core_Bound(%)", - "expression": "100*max(0, 1*([TOPDOWN_BE_BOUND.ALL] / (6.0 * [cpu-cycles]) - min(1*([TOPDOWN_BE_BOUND.ALL] / (6.0 * [cpu-cycles])), 1*([LD_HEAD.ANY_AT_RET] / [cpu-cycles] + ([TOPDOWN_BE_BOUND.MEM_SCHEDULER] / (6.0 * [cpu-cycles])) * [MEM_SCHEDULER_BLOCK.ST_BUF] / [MEM_SCHEDULER_BLOCK.ALL]))))" - }, - { - "name": "TMA_....Serialization(%)", - "expression": "100*([TOPDOWN_BE_BOUND.SERIALIZATION] / (6.0 * [cpu-cycles]))" - }, - { - "name": "TMA_Retiring(%)", - "expression": "100 * ( [TOPDOWN_RETIRING.ALL] / ( 6 * [cpu-cycles] ) )" - } -] \ No newline at end of file diff --git a/cmd/metrics/resources/perfmon/emr/emeraldrapids_core.json b/cmd/metrics/resources/perfmon/emr/emeraldrapids_core.json new file mode 100644 index 00000000..b18ce6a1 --- /dev/null +++ b/cmd/metrics/resources/perfmon/emr/emeraldrapids_core.json @@ -0,0 +1,9811 @@ +{ + "Header": { + "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.16", + "DatePublished": "07/03/2025", + "Version": "1.16", + "Legend": "" + }, + "Events": [ + { + "EventCode": "0x00", + "UMask": "0x01", + "EventName": "INST_RETIRED.ANY", + "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event", + "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", + "Counter": "Fixed counter 0", + "PEBScounters": "32", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "32", + "Speculative": "0" + }, + { + "EventCode": "0x00", + "UMask": "0x01", + "EventName": "INST_RETIRED.PREC_DIST", + "BriefDescription": "Precise instruction retired with PEBS precise-distribution", + "PublicDescription": "A version of INST_RETIRED that allows for a precise distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR++) feature to fix bias in how retired instructions get sampled. Use on Fixed Counter 0.", + "Counter": "Fixed counter 0", + "PEBScounters": "32", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "32", + "Speculative": "0" + }, + { + "EventCode": "0x00", + "UMask": "0x02", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "BriefDescription": "Core cycles when the thread is not in halt state", + "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.", + "Counter": "Fixed counter 1", + "PEBScounters": "33", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x00", + "UMask": "0x03", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "BriefDescription": "Reference cycles when the core is not in halt state.", + "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", + "Counter": "Fixed counter 2", + "PEBScounters": "34", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x00", + "UMask": "0x04", + "EventName": "TOPDOWN.SLOTS", + "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", + "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", + "Counter": "Fixed counter 3", + "PEBScounters": "35", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x03", + "UMask": "0x04", + "EventName": "LD_BLOCKS.ADDRESS_ALIAS", + "BriefDescription": "False dependencies in MOB due to partial compare on address.", + "PublicDescription": "Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x03", + "UMask": "0x82", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", + "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x03", + "UMask": "0x88", + "EventName": "LD_BLOCKS.NO_SR", + "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x11", + "UMask": "0x02", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", + "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x11", + "UMask": "0x04", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", + "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x11", + "UMask": "0x0e", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", + "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x11", + "UMask": "0x10", + "EventName": "ITLB_MISSES.WALK_ACTIVE", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.", + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x11", + "UMask": "0x10", + "EventName": "ITLB_MISSES.WALK_PENDING", + "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.", + "PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x11", + "UMask": "0x20", + "EventName": "ITLB_MISSES.STLB_HIT", + "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.", + "PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x12", + "UMask": "0x02", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Page walks completed due to a demand data load to a 4K page.", + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x12", + "UMask": "0x04", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.", + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x12", + "UMask": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "BriefDescription": "Page walks completed due to a demand data load to a 1G page.", + "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x12", + "UMask": "0x0e", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x12", + "UMask": "0x10", + "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.", + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x12", + "UMask": "0x10", + "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", + "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.", + "PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x12", + "UMask": "0x20", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "BriefDescription": "Loads that miss the DTLB and hit the STLB.", + "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x13", + "UMask": "0x02", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Page walks completed due to a demand data store to a 4K page.", + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x13", + "UMask": "0x04", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.", + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x13", + "UMask": "0x08", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "BriefDescription": "Page walks completed due to a demand data store to a 1G page.", + "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x13", + "UMask": "0x0e", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x13", + "UMask": "0x10", + "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.", + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x13", + "UMask": "0x10", + "EventName": "DTLB_STORE_MISSES.WALK_PENDING", + "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.", + "PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x13", + "UMask": "0x20", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "BriefDescription": "Stores that miss the DTLB and hit the STLB.", + "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x01", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "BriefDescription": "Cycles where at least 1 outstanding demand data read request is pending.", + "PublicDescription": "Cycles where at least 1 outstanding demand data read request is pending.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x01", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "BriefDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.", + "PublicDescription": "For every cycle, increments by the number of outstanding demand data read requests pending. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x02", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", + "BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.", + "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x02", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.", + "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x04", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "PublicDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x08", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "BriefDescription": "This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "PublicDescription": "This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x08", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "PublicDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x08", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "PublicDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x10", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", + "BriefDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.", + "PublicDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known by the requesting core to have missed the L3 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x21", + "UMask": "0x01", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "BriefDescription": "Demand Data Read requests sent to uncore", + "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x21", + "UMask": "0x02", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "BriefDescription": "Cacheable and noncacheable code read requests", + "PublicDescription": "Counts both cacheable and non-cacheable code read requests.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x21", + "UMask": "0x04", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", + "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x21", + "UMask": "0x08", + "EventName": "OFFCORE_REQUESTS.DATA_RD", + "BriefDescription": "Demand and prefetch data reads", + "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x21", + "UMask": "0x10", + "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "BriefDescription": "Counts demand data read requests that miss the L3 cache.", + "PublicDescription": "Counts demand data read requests that miss the L3 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x21", + "UMask": "0x80", + "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", + "BriefDescription": "OFFCORE_REQUESTS.ALL_REQUESTS", + "PublicDescription": "OFFCORE_REQUESTS.ALL_REQUESTS", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x23", + "UMask": "0x40", + "EventName": "L2_TRANS.L2_WB", + "BriefDescription": "L2 writebacks that access L2 cache", + "PublicDescription": "Counts L2 writebacks that access L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x21", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "BriefDescription": "Demand Data Read miss L2 cache", + "PublicDescription": "Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x22", + "EventName": "L2_RQSTS.RFO_MISS", + "BriefDescription": "RFO requests that miss L2 cache", + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "BriefDescription": "L2 cache misses when fetching instructions", + "PublicDescription": "Counts L2 cache misses when fetching instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x27", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "BriefDescription": "Demand requests that miss L2 cache", + "PublicDescription": "Counts demand requests that miss L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x28", + "EventName": "L2_RQSTS.SWPF_MISS", + "BriefDescription": "SW prefetch requests that miss L2 cache.", + "PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x30", + "EventName": "L2_RQSTS.HWPF_MISS", + "BriefDescription": "L2_RQSTS.HWPF_MISS", + "PublicDescription": "L2_RQSTS.HWPF_MISS", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x3f", + "EventName": "L2_RQSTS.MISS", + "BriefDescription": "Read requests with true-miss in L2 cache. [This event is alias to L2_REQUEST.MISS]", + "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.MISS]", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x3f", + "EventName": "L2_REQUEST.MISS", + "BriefDescription": "Read requests with true-miss in L2 cache. [This event is alias to L2_RQSTS.MISS]", + "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.MISS]", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xc1", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "BriefDescription": "Demand Data Read requests that hit L2 cache", + "PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xc2", + "EventName": "L2_RQSTS.RFO_HIT", + "BriefDescription": "RFO requests that hit L2 cache", + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xc4", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xc8", + "EventName": "L2_RQSTS.SWPF_HIT", + "BriefDescription": "SW prefetch requests that hit L2 cache.", + "PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xe1", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "BriefDescription": "Demand Data Read access L2 cache", + "PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xe2", + "EventName": "L2_RQSTS.ALL_RFO", + "BriefDescription": "RFO requests to L2 cache", + "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xe4", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "BriefDescription": "L2 code requests", + "PublicDescription": "Counts the total number of L2 code requests.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xe7", + "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", + "BriefDescription": "Demand requests to L2 cache", + "PublicDescription": "Counts demand requests to L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xf0", + "EventName": "L2_RQSTS.ALL_HWPF", + "BriefDescription": "L2_RQSTS.ALL_HWPF", + "PublicDescription": "L2_RQSTS.ALL_HWPF", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xff", + "EventName": "L2_RQSTS.REFERENCES", + "BriefDescription": "All accesses to L2 cache [This event is alias to L2_REQUEST.ALL]", + "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.ALL]", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xff", + "EventName": "L2_REQUEST.ALL", + "BriefDescription": "All accesses to L2 cache [This event is alias to L2_RQSTS.REFERENCES]", + "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES]", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x25", + "UMask": "0x1f", + "EventName": "L2_LINES_IN.ALL", + "BriefDescription": "L2 cache lines filling L2", + "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x26", + "UMask": "0x01", + "EventName": "L2_LINES_OUT.SILENT", + "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache.", + "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache. These lines are typically in Shared or Exclusive state. A non-threaded event.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x26", + "UMask": "0x02", + "EventName": "L2_LINES_OUT.NON_SILENT", + "BriefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill.", + "PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x26", + "UMask": "0x04", + "EventName": "L2_LINES_OUT.USELESS_HWPF", + "BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses", + "PublicDescription": "Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x2c", + "UMask": "0x10", + "EventName": "SQ_MISC.BUS_LOCK", + "BriefDescription": "Counts bus locks, accounts for cache line split locks and UC locks.", + "PublicDescription": "Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically. Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x2d", + "UMask": "0x01", + "EventName": "XQ.FULL_CYCLES", + "BriefDescription": "Cycles the uncore cannot take further requests", + "PublicDescription": "number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x2e", + "UMask": "0x41", + "EventName": "LONGEST_LAT_CACHE.MISS", + "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)", + "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x2e", + "UMask": "0x4f", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)", + "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x3c", + "UMask": "0x00", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "BriefDescription": "Thread cycles when thread is not in halt state", + "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x3c", + "UMask": "0x01", + "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", + "BriefDescription": "Reference cycles when the core is not in halt state.", + "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x3c", + "UMask": "0x02", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.", + "PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "25003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x3c", + "UMask": "0x08", + "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.", + "PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x40", + "UMask": "0x01", + "EventName": "SW_PREFETCH_ACCESS.NTA", + "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x40", + "UMask": "0x02", + "EventName": "SW_PREFETCH_ACCESS.T0", + "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x40", + "UMask": "0x04", + "EventName": "SW_PREFETCH_ACCESS.T1_T2", + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x40", + "UMask": "0x08", + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", + "BriefDescription": "Number of PREFETCHW instructions executed.", + "PublicDescription": "Counts the number of PREFETCHW instructions executed.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x40", + "UMask": "0xF", + "EventName": "SW_PREFETCH_ACCESS.ANY", + "BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.", + "PublicDescription": "Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x43", + "UMask": "0xfd", + "EventName": "MEM_LOAD_COMPLETED.L1_MISS_ANY", + "BriefDescription": "Completed demand load uops that miss the L1 d-cache.", + "PublicDescription": "Number of completed demand load requests that missed the L1 data cache including shadow misses (FB hits, merge to an ongoing L1D miss)", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x44", + "UMask": "0x01", + "EventName": "MEM_STORE_RETIRED.L2_HIT", + "BriefDescription": "MEM_STORE_RETIRED.L2_HIT", + "PublicDescription": "MEM_STORE_RETIRED.L2_HIT", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0x47", + "UMask": "0x02", + "EventName": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "PublicDescription": "Cycles while L1 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "2", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x47", + "UMask": "0x03", + "EventName": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "PublicDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "3", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x47", + "UMask": "0x05", + "EventName": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "BriefDescription": "Execution stalls while L2 cache miss demand cacheable load request is outstanding.", + "PublicDescription": "Execution stalls while L2 cache miss demand cacheable load request is outstanding (will not count for uncacheable demand requests e.g. bus lock).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "5", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x47", + "UMask": "0x09", + "EventName": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "BriefDescription": "Execution stalls while L3 cache miss demand cacheable load request is outstanding.", + "PublicDescription": "Execution stalls while L3 cache miss demand cacheable load request is outstanding (will not count for uncacheable demand requests e.g. bus lock).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "9", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x48", + "UMask": "0x01", + "EventName": "L1D_PEND_MISS.PENDING", + "BriefDescription": "Number of L1D misses that are outstanding", + "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x48", + "UMask": "0x01", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "PublicDescription": "Counts duration of L1D miss outstanding in cycles.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x48", + "UMask": "0x02", + "EventName": "L1D_PEND_MISS.FB_FULL", + "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.", + "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x48", + "UMask": "0x02", + "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS", + "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.", + "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x48", + "UMask": "0x04", + "EventName": "L1D_PEND_MISS.L2_STALL", + "BriefDescription": "This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS", + "PublicDescription": "This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x48", + "UMask": "0x04", + "EventName": "L1D_PEND_MISS.L2_STALLS", + "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", + "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x4c", + "UMask": "0x01", + "EventName": "LOAD_HIT_PREFETCH.SWPF", + "BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.", + "PublicDescription": "Counts all software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x51", + "UMask": "0x01", + "EventName": "L1D.REPLACEMENT", + "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.", + "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x51", + "UMask": "0x20", + "EventName": "L1D.HWPF_MISS", + "BriefDescription": "L1D.HWPF_MISS", + "PublicDescription": "L1D.HWPF_MISS", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x54", + "UMask": "0x01", + "EventName": "TX_MEM.ABORT_CONFLICT", + "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", + "PublicDescription": "Counts the number of times a TSX line had a cache conflict.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x54", + "UMask": "0x02", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.", + "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x54", + "UMask": "0x80", + "EventName": "TX_MEM.ABORT_CAPACITY_READ", + "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads", + "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x60", + "UMask": "0x01", + "EventName": "BACLEARS.ANY", + "BriefDescription": "Clears due to Unknown Branches.", + "PublicDescription": "Number of times the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x61", + "UMask": "0x02", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "BriefDescription": "DSB-to-MITE switch true penalty cycles.", + "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x75", + "UMask": "0x01", + "EventName": "INST_DECODED.DECODERS", + "BriefDescription": "Instruction decoders utilized in a cycle", + "PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x76", + "UMask": "0x01", + "EventName": "UOPS_DECODED.DEC0_UOPS", + "BriefDescription": "UOPS_DECODED.DEC0_UOPS", + "PublicDescription": "UOPS_DECODED.DEC0_UOPS", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x04", + "EventName": "IDQ.MITE_CYCLES_ANY", + "BriefDescription": "Cycles MITE is delivering any Uop", + "PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x04", + "EventName": "IDQ.MITE_CYCLES_OK", + "BriefDescription": "Cycles MITE is delivering optimal number of Uops", + "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "6", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x04", + "EventName": "IDQ.MITE_UOPS", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x08", + "EventName": "IDQ.DSB_CYCLES_ANY", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", + "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x08", + "EventName": "IDQ.DSB_CYCLES_OK", + "BriefDescription": "Cycles DSB is delivering optimal number of Uops", + "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode Stream Buffer) path. Count includes uops that may 'bypass' the IDQ.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "6", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x08", + "EventName": "IDQ.DSB_UOPS", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", + "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x20", + "EventName": "IDQ.MS_CYCLES_ANY", + "BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy", + "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x20", + "EventName": "IDQ.MS_SWITCHES", + "BriefDescription": "Number of switches from DSB or MITE to the MS", + "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x20", + "EventName": "IDQ.MS_UOPS", + "BriefDescription": "Uops delivered to IDQ while MS is busy", + "PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x80", + "UMask": "0x04", + "EventName": "ICACHE_DATA.STALLS", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.", + "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The decode pipeline works at a 32 Byte granularity.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x80", + "UMask": "0x04", + "EventName": "ICACHE_DATA.STALL_PERIODS", + "BriefDescription": "ICACHE_DATA.STALL_PERIODS", + "PublicDescription": "ICACHE_DATA.STALL_PERIODS", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x83", + "UMask": "0x04", + "EventName": "ICACHE_TAG.STALLS", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.", + "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x87", + "UMask": "0x01", + "EventName": "DECODE.LCP", + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x87", + "UMask": "0x02", + "EventName": "DECODE.MS_BUSY", + "BriefDescription": "Cycles the Microcode Sequencer is busy.", + "PublicDescription": "Cycles the Microcode Sequencer is busy.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x9c", + "UMask": "0x01", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CORE]", + "PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CORE]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x9c", + "UMask": "0x01", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE]", + "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "6", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x9c", + "UMask": "0x01", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_FE_WAS_OK]", + "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CYCLES_FE_WAS_OK]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x9c", + "UMask": "0x01", + "EventName": "IDQ_BUBBLES.CORE", + "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CORE]", + "PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CORE]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x9c", + "UMask": "0x01", + "EventName": "IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE", + "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE]", + "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "6", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x9c", + "UMask": "0x01", + "EventName": "IDQ_BUBBLES.CYCLES_FE_WAS_OK", + "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK]", + "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa2", + "UMask": "0x02", + "EventName": "RESOURCE_STALLS.SCOREBOARD", + "BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.", + "PublicDescription": "Counts cycles where the pipeline is stalled due to serializing operations.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa2", + "UMask": "0x08", + "EventName": "RESOURCE_STALLS.SB", + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x01", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", + "PublicDescription": "Cycles while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x04", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", + "BriefDescription": "Total execution stalls.", + "PublicDescription": "Total execution stalls.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "4", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x05", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "PublicDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "5", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x06", + "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", + "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", + "PublicDescription": "Execution stalls while L3 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "6", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x08", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "PublicDescription": "Cycles while L1 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "8", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x0c", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "PublicDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "12", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x10", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "PublicDescription": "Cycles while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "16", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa4", + "UMask": "0x01", + "EventName": "TOPDOWN.SLOTS_P", + "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", + "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa4", + "UMask": "0x02", + "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", + "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", + "PublicDescription": "Number of slots in TMA method where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa4", + "UMask": "0x04", + "EventName": "TOPDOWN.BAD_SPEC_SLOTS", + "BriefDescription": "TMA slots wasted due to incorrect speculations.", + "PublicDescription": "Number of slots of TMA method that were wasted due to incorrect speculation. It covers all types of control-flow or data-related mis-speculations.", + "Counter": "0", + "PEBScounters": "0", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa4", + "UMask": "0x08", + "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", + "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", + "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by (any type of) branch mispredictions. This event estimates number of speculative operations that were issued but not retired as well as the out-of-order engine recovery past a branch misprediction.", + "Counter": "0", + "PEBScounters": "0", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa4", + "UMask": "0x10", + "EventName": "TOPDOWN.MEMORY_BOUND_SLOTS", + "BriefDescription": "TOPDOWN.MEMORY_BOUND_SLOTS", + "PublicDescription": "TOPDOWN.MEMORY_BOUND_SLOTS", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa5", + "UMask": "0x01", + "EventName": "RS.EMPTY_RESOURCE", + "BriefDescription": "Cycles when Reservation Station (RS) is empty due to a resource in the back-end", + "PublicDescription": "Cycles when Reservation Station (RS) is empty due to a resource in the back-end", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa5", + "UMask": "0x07", + "EventName": "RS_EMPTY.COUNT", + "BriefDescription": "This event is deprecated. Refer to new event RS.EMPTY_COUNT", + "PublicDescription": "This event is deprecated. Refer to new event RS.EMPTY_COUNT", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa5", + "UMask": "0x07", + "EventName": "RS_EMPTY.CYCLES", + "BriefDescription": "This event is deprecated. Refer to new event RS.EMPTY", + "PublicDescription": "This event is deprecated. Refer to new event RS.EMPTY", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa5", + "UMask": "0x07", + "EventName": "RS.EMPTY", + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.", + "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses)", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa5", + "UMask": "0x07", + "EventName": "RS.EMPTY_COUNT", + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.", + "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x02", + "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", + "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.", + "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x04", + "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", + "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.", + "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x08", + "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", + "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.", + "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x10", + "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", + "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.", + "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x21", + "EventName": "EXE_ACTIVITY.BOUND_ON_LOADS", + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "PublicDescription": "Execution stalls while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "5", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x40", + "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", + "BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.", + "PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "2", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x80", + "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "BriefDescription": "Cycles no uop executed while RS was not empty, the SB was not full and there was no outstanding load.", + "PublicDescription": "Number of cycles total of 0 uops executed on all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) was not full and there was no outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0xC", + "EventName": "EXE_ACTIVITY.2_3_PORTS_UTIL", + "BriefDescription": "Cycles total of 2 or 3 uops are executed on all ports and Reservation Station (RS) was not empty.", + "PublicDescription": "Cycles total of 2 or 3 uops are executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa8", + "UMask": "0x01", + "EventName": "LSD.CYCLES_ACTIVE", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa8", + "UMask": "0x01", + "EventName": "LSD.CYCLES_OK", + "BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.", + "PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "6", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa8", + "UMask": "0x01", + "EventName": "LSD.UOPS", + "BriefDescription": "Number of Uops delivered by the LSD.", + "PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xad", + "UMask": "0x01", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread", + "PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xad", + "UMask": "0x01", + "EventName": "INT_MISC.CLEARS_COUNT", + "BriefDescription": "Clears speculative count", + "PublicDescription": "Counts the number of speculative clears due to any type of branch misprediction or machine clears", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xad", + "UMask": "0x10", + "EventName": "INT_MISC.UOP_DROPPING", + "BriefDescription": "TMA slots where uops got dropped", + "PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xad", + "UMask": "0x20", + "EventName": "INT_MISC.MBA_STALLS", + "BriefDescription": "INT_MISC.MBA_STALLS", + "PublicDescription": "INT_MISC.MBA_STALLS", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xad", + "UMask": "0x40", + "EventName": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "BriefDescription": "Bubble cycles of BAClear (Unknown Branch).", + "PublicDescription": "Bubble cycles of BAClear (Unknown Branch).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x3F7", + "MSRValue": "0x7", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xad", + "UMask": "0x80", + "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", + "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", + "PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xae", + "UMask": "0x01", + "EventName": "UOPS_ISSUED.ANY", + "BriefDescription": "Uops that RAT issues to RS", + "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xae", + "UMask": "0x01", + "EventName": "UOPS_ISSUED.CYCLES", + "BriefDescription": "UOPS_ISSUED.CYCLES", + "PublicDescription": "UOPS_ISSUED.CYCLES", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb0", + "UMask": "0x01", + "EventName": "ARITH.FP_DIVIDER_ACTIVE", + "BriefDescription": "This event is deprecated. Refer to new event ARITH.FPDIV_ACTIVE", + "PublicDescription": "This event is deprecated. Refer to new event ARITH.FPDIV_ACTIVE", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb0", + "UMask": "0x01", + "EventName": "ARITH.FPDIV_ACTIVE", + "BriefDescription": "ARITH.FPDIV_ACTIVE", + "PublicDescription": "ARITH.FPDIV_ACTIVE", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb0", + "UMask": "0x08", + "EventName": "ARITH.IDIV_ACTIVE", + "BriefDescription": "This event counts the cycles the integer divider is busy.", + "PublicDescription": "This event counts the cycles the integer divider is busy.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb0", + "UMask": "0x08", + "EventName": "ARITH.INT_DIVIDER_ACTIVE", + "BriefDescription": "This event is deprecated. Refer to new event ARITH.IDIV_ACTIVE", + "PublicDescription": "This event is deprecated. Refer to new event ARITH.IDIV_ACTIVE", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb0", + "UMask": "0x09", + "EventName": "ARITH.DIVIDER_ACTIVE", + "BriefDescription": "This event is deprecated. Refer to new event ARITH.DIV_ACTIVE", + "PublicDescription": "This event is deprecated. Refer to new event ARITH.DIV_ACTIVE", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb0", + "UMask": "0x09", + "EventName": "ARITH.DIV_ACTIVE", + "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.", + "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1", + "BriefDescription": "Cycles where at least 1 uop was executed per-thread", + "PublicDescription": "Cycles where at least 1 uop was executed per-thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2", + "BriefDescription": "Cycles where at least 2 uops were executed per-thread", + "PublicDescription": "Cycles where at least 2 uops were executed per-thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "2", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3", + "BriefDescription": "Cycles where at least 3 uops were executed per-thread", + "PublicDescription": "Cycles where at least 3 uops were executed per-thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "3", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4", + "BriefDescription": "Cycles where at least 4 uops were executed per-thread", + "PublicDescription": "Cycles where at least 4 uops were executed per-thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "4", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "BriefDescription": "This event is deprecated. Refer to new event UOPS_EXECUTED.STALLS", + "PublicDescription": "This event is deprecated. Refer to new event UOPS_EXECUTED.STALLS", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.THREAD", + "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", + "PublicDescription": "Counts the number of uops to be executed per-thread each cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.STALLS", + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE", + "BriefDescription": "Number of uops executed on the core.", + "PublicDescription": "Counts the number of uops executed from any thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "2", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "3", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "4", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x10", + "EventName": "UOPS_EXECUTED.X87", + "BriefDescription": "Counts the number of x87 uops dispatched.", + "PublicDescription": "Counts the number of x87 uops executed.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb2", + "UMask": "0x01", + "EventName": "UOPS_DISPATCHED.PORT_0", + "BriefDescription": "Uops executed on port 0", + "PublicDescription": "Number of uops dispatch to execution port 0.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb2", + "UMask": "0x02", + "EventName": "UOPS_DISPATCHED.PORT_1", + "BriefDescription": "Uops executed on port 1", + "PublicDescription": "Number of uops dispatch to execution port 1.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb2", + "UMask": "0x04", + "EventName": "UOPS_DISPATCHED.PORT_2_3_10", + "BriefDescription": "Uops executed on ports 2, 3 and 10", + "PublicDescription": "Number of uops dispatch to execution ports 2, 3 and 10", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb2", + "UMask": "0x10", + "EventName": "UOPS_DISPATCHED.PORT_4_9", + "BriefDescription": "Uops executed on ports 4 and 9", + "PublicDescription": "Number of uops dispatch to execution ports 4 and 9", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb2", + "UMask": "0x20", + "EventName": "UOPS_DISPATCHED.PORT_5_11", + "BriefDescription": "Uops executed on ports 5 and 11", + "PublicDescription": "Number of uops dispatch to execution ports 5 and 11", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb2", + "UMask": "0x40", + "EventName": "UOPS_DISPATCHED.PORT_6", + "BriefDescription": "Uops executed on port 6", + "PublicDescription": "Number of uops dispatch to execution port 6.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb2", + "UMask": "0x80", + "EventName": "UOPS_DISPATCHED.PORT_7_8", + "BriefDescription": "Uops executed on ports 7 and 8", + "PublicDescription": "Number of uops dispatch to execution ports 7 and 8.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb3", + "UMask": "0x01", + "EventName": "FP_ARITH_DISPATCHED.PORT_0", + "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0]", + "PublicDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb3", + "UMask": "0x01", + "EventName": "FP_ARITH_DISPATCHED.V0", + "BriefDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0]", + "PublicDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb3", + "UMask": "0x02", + "EventName": "FP_ARITH_DISPATCHED.PORT_1", + "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1]", + "PublicDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb3", + "UMask": "0x02", + "EventName": "FP_ARITH_DISPATCHED.V1", + "BriefDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1]", + "PublicDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb3", + "UMask": "0x04", + "EventName": "FP_ARITH_DISPATCHED.PORT_5", + "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2]", + "PublicDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb3", + "UMask": "0x04", + "EventName": "FP_ARITH_DISPATCHED.V2", + "BriefDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5]", + "PublicDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb7", + "UMask": "0x02", + "EventName": "EXE.AMX_BUSY", + "BriefDescription": "Counts the cycles where the AMX (Advance Matrix Extension) unit is busy performing an operation.", + "PublicDescription": "Counts the cycles where the AMX (Advance Matrix Extension) unit is busy performing an operation.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc0", + "UMask": "0x00", + "EventName": "INST_RETIRED.ANY_P", + "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc0", + "UMask": "0x02", + "EventName": "INST_RETIRED.NOP", + "BriefDescription": "Retired NOP instructions.", + "PublicDescription": "Counts all retired NOP or ENDBR32/64 instructions", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc0", + "UMask": "0x08", + "EventName": "INST_RETIRED.REP_ITERATION", + "BriefDescription": "Iterations of Repeat string retired instructions.", + "PublicDescription": "Number of iterations of Repeat (REP) string retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, and doubleword version and string instructions can be repeated using a repetition prefix, REP, that allows their architectural execution to be repeated a number of times as specified by the RCX register. Note the number of iterations is implementation-dependent.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc0", + "UMask": "0x10", + "EventName": "INST_RETIRED.MACRO_FUSED", + "BriefDescription": "INST_RETIRED.MACRO_FUSED", + "PublicDescription": "INST_RETIRED.MACRO_FUSED", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc1", + "UMask": "0x02", + "EventName": "ASSISTS.FP", + "BriefDescription": "Counts all microcode FP assists.", + "PublicDescription": "Counts all microcode Floating Point assists.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc1", + "UMask": "0x08", + "EventName": "ASSISTS.PAGE_FAULT", + "BriefDescription": "ASSISTS.PAGE_FAULT", + "PublicDescription": "ASSISTS.PAGE_FAULT", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc1", + "UMask": "0x10", + "EventName": "ASSISTS.SSE_AVX_MIX", + "BriefDescription": "ASSISTS.SSE_AVX_MIX", + "PublicDescription": "ASSISTS.SSE_AVX_MIX", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc1", + "UMask": "0x1b", + "EventName": "ASSISTS.ANY", + "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.", + "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware. Examples include AD (page Access Dirty), FP and AVX related assists.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc2", + "UMask": "0x01", + "EventName": "UOPS_RETIRED.HEAVY", + "BriefDescription": "Retired uops except the last uop of each instruction.", + "PublicDescription": "Counts the number of retired micro-operations (uops) except the last uop of each instruction. An instruction that is decoded into less than two uops does not contribute to the count.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x02", + "EventName": "UOPS_RETIRED.SLOTS", + "BriefDescription": "Retirement slots used.", + "PublicDescription": "Counts the retirement slots used each cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x02", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "BriefDescription": "This event is deprecated. Refer to new event UOPS_RETIRED.STALLS", + "PublicDescription": "This event is deprecated. Refer to new event UOPS_RETIRED.STALLS", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x02", + "EventName": "UOPS_RETIRED.STALLS", + "BriefDescription": "Cycles without actually retired uops.", + "PublicDescription": "This event counts cycles without actually retired uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x02", + "EventName": "UOPS_RETIRED.CYCLES", + "BriefDescription": "Cycles with retired uop(s).", + "PublicDescription": "Counts cycles where at least one uop has retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x04", + "EventName": "UOPS_RETIRED.MS", + "BriefDescription": "UOPS_RETIRED.MS", + "PublicDescription": "UOPS_RETIRED.MS", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x3F7", + "MSRValue": "0x8", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc3", + "UMask": "0x01", + "EventName": "MACHINE_CLEARS.COUNT", + "BriefDescription": "Number of machine clears (nukes) of any type.", + "PublicDescription": "Counts the number of machine clears (nukes) of any type.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc3", + "UMask": "0x02", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "BriefDescription": "Number of machine clears due to memory ordering conflicts.", + "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc3", + "UMask": "0x04", + "EventName": "MACHINE_CLEARS.SMC", + "BriefDescription": "Self-modifying code (SMC) detected.", + "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc4", + "UMask": "0x00", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "BriefDescription": "All branch instructions retired.", + "PublicDescription": "Counts all branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x01", + "EventName": "BR_INST_RETIRED.COND_TAKEN", + "BriefDescription": "Taken conditional branch instructions retired.", + "PublicDescription": "Counts taken conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x02", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "BriefDescription": "Direct and indirect near call instructions retired.", + "PublicDescription": "Counts both direct and indirect near call instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x08", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "BriefDescription": "Return instructions retired.", + "PublicDescription": "Counts return instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x10", + "EventName": "BR_INST_RETIRED.COND_NTAKEN", + "BriefDescription": "Not taken branch instructions retired.", + "PublicDescription": "Counts not taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x11", + "EventName": "BR_INST_RETIRED.COND", + "BriefDescription": "Conditional branch instructions retired.", + "PublicDescription": "Counts conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x20", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "BriefDescription": "Taken branch instructions retired.", + "PublicDescription": "Counts taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x40", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "BriefDescription": "Far branch instructions retired.", + "PublicDescription": "Counts far branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x80", + "EventName": "BR_INST_RETIRED.INDIRECT", + "BriefDescription": "Indirect near branch instructions retired (excluding returns)", + "PublicDescription": "Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x00", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "BriefDescription": "All mispredicted branch instructions retired.", + "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x01", + "EventName": "BR_MISP_RETIRED.COND_TAKEN", + "BriefDescription": "number of branch instructions retired that were mispredicted and taken.", + "PublicDescription": "Counts taken conditional mispredicted branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x02", + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", + "BriefDescription": "Mispredicted indirect CALL retired.", + "PublicDescription": "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x08", + "EventName": "BR_MISP_RETIRED.RET", + "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x10", + "EventName": "BR_MISP_RETIRED.COND_NTAKEN", + "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", + "PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x11", + "EventName": "BR_MISP_RETIRED.COND", + "BriefDescription": "Mispredicted conditional branch instructions retired.", + "PublicDescription": "Counts mispredicted conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x20", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", + "PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x80", + "EventName": "BR_MISP_RETIRED.INDIRECT", + "BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)", + "PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.DSB_MISS", + "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", + "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x11", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.ITLB_MISS", + "BriefDescription": "Retired Instructions who experienced iTLB true miss.", + "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x14", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.L1I_MISS", + "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", + "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x12", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.L2_MISS", + "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", + "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x13", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", + "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x600106", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x608006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x601006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", + "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x600206", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x100206", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x610006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x602006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x600406", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x620006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x604006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x600806", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.STLB_MISS", + "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.", + "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x15", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.UNKNOWN_BRANCH", + "BriefDescription": "FRONTEND_RETIRED.UNKNOWN_BRANCH", + "PublicDescription": "FRONTEND_RETIRED.UNKNOWN_BRANCH", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x17", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.MS_FLOWS", + "BriefDescription": "FRONTEND_RETIRED.MS_FLOWS", + "PublicDescription": "FRONTEND_RETIRED.MS_FLOWS", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x8", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", + "BriefDescription": "Retired Instructions who experienced DSB miss.", + "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x1", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x01", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x02", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x03", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR", + "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x04", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x08", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x10", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x18", + "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x20", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x40", + "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x60", + "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x80", + "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0xfc", + "EventName": "FP_ARITH_INST_RETIRED.VECTOR", + "BriefDescription": "Number of any Vector retired FP arithmetic instructions", + "PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x01", + "EventName": "RTM_RETIRED.START", + "BriefDescription": "Number of times an RTM execution started.", + "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x02", + "EventName": "RTM_RETIRED.COMMIT", + "BriefDescription": "Number of times an RTM execution successfully committed", + "PublicDescription": "Counts the number of times RTM commit succeeded.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x04", + "EventName": "RTM_RETIRED.ABORTED", + "BriefDescription": "Number of times an RTM execution aborted.", + "PublicDescription": "Counts the number of times RTM abort was triggered.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x08", + "EventName": "RTM_RETIRED.ABORTED_MEM", + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", + "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x20", + "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", + "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", + "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x40", + "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", + "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", + "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x80", + "EventName": "RTM_RETIRED.ABORTED_EVENTS", + "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 3 categories (e.g. interrupt)", + "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 3 categories (e.g. interrupt).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcb", + "UMask": "0x01", + "EventName": "HW_INTERRUPTS.RECEIVED", + "BriefDescription": "Number of hardware interrupts received by the processor.", + "PublicDescription": "Counts the number of hardware interruptions received by the processor.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "203", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xcb", + "UMask": "0x02", + "EventName": "HW_INTERRUPTS.MASKED", + "BriefDescription": "HW_INTERRUPTS.MASKED", + "PublicDescription": "HW_INTERRUPTS.MASKED", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xcb", + "UMask": "0x04", + "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED", + "BriefDescription": "HW_INTERRUPTS.PENDING_AND_MASKED", + "PublicDescription": "HW_INTERRUPTS.PENDING_AND_MASKED", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xcc", + "UMask": "0x20", + "EventName": "MISC_RETIRED.LBR_INSERTS", + "BriefDescription": "Increments whenever there is an update to the LBR array.", + "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "1009", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "20011", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "503", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "101", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "2003", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "53", + "MSRIndex": "0x3F6", + "MSRValue": "0x400", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x02", + "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE", + "BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.", + "PublicDescription": "Counts Retired memory accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) trigger covering all stores uops for sampling by the PEBS Store Latency Facility. The facility is described in Intel SDM Volume 3 section 19.9.8", + "Counter": "0", + "PEBScounters": "0", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcf", + "UMask": "0x01", + "EventName": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", + "BriefDescription": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", + "PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcf", + "UMask": "0x02", + "EventName": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", + "BriefDescription": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", + "PublicDescription": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcf", + "UMask": "0x03", + "EventName": "FP_ARITH_INST_RETIRED2.SCALAR", + "BriefDescription": "Number of all Scalar Half-Precision FP arithmetic instructions(1) retired - regular and complex.", + "PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcf", + "UMask": "0x04", + "EventName": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", + "BriefDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", + "PublicDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcf", + "UMask": "0x08", + "EventName": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", + "BriefDescription": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", + "PublicDescription": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcf", + "UMask": "0x10", + "EventName": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", + "BriefDescription": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", + "PublicDescription": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcf", + "UMask": "0x1c", + "EventName": "FP_ARITH_INST_RETIRED2.VECTOR", + "BriefDescription": "Number of all Vector (also called packed) Half-Precision FP arithmetic instructions(1) retired.", + "PublicDescription": "FP_ARITH_INST_RETIRED2.VECTOR", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x11", + "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", + "BriefDescription": "Retired load instructions that miss the STLB.", + "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x12", + "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", + "BriefDescription": "Retired store instructions that miss the STLB.", + "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x21", + "EventName": "MEM_INST_RETIRED.LOCK_LOADS", + "BriefDescription": "Retired load instructions with locked access.", + "PublicDescription": "Counts retired load instructions with locked access.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x41", + "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", + "BriefDescription": "Retired load instructions that split across a cacheline boundary.", + "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x42", + "EventName": "MEM_INST_RETIRED.SPLIT_STORES", + "BriefDescription": "Retired store instructions that split across a cacheline boundary.", + "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x81", + "EventName": "MEM_INST_RETIRED.ALL_LOADS", + "BriefDescription": "Retired load instructions.", + "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x82", + "EventName": "MEM_INST_RETIRED.ALL_STORES", + "BriefDescription": "Retired store instructions.", + "PublicDescription": "Counts all retired store instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x83", + "EventName": "MEM_INST_RETIRED.ANY", + "BriefDescription": "All retired memory instructions.", + "PublicDescription": "Counts all retired memory instructions - loads and stores.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x01", + "EventName": "MEM_LOAD_RETIRED.L1_HIT", + "BriefDescription": "Retired load instructions with L1 cache hits as data sources", + "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x02", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "BriefDescription": "Retired load instructions with L2 cache hits as data sources", + "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x04", + "EventName": "MEM_LOAD_RETIRED.L3_HIT", + "BriefDescription": "Retired load instructions with L3 cache hits as data sources", + "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x08", + "EventName": "MEM_LOAD_RETIRED.L1_MISS", + "BriefDescription": "Retired load instructions missed L1 cache as data sources", + "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x10", + "EventName": "MEM_LOAD_RETIRED.L2_MISS", + "BriefDescription": "Retired load instructions missed L2 cache as data sources", + "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x20", + "EventName": "MEM_LOAD_RETIRED.L3_MISS", + "BriefDescription": "Retired load instructions missed L3 cache as data sources", + "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "50021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x40", + "EventName": "MEM_LOAD_RETIRED.FB_HIT", + "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.", + "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd2", + "UMask": "0x01", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd2", + "UMask": "0x02", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache", + "PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd2", + "UMask": "0x04", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", + "PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd2", + "UMask": "0x08", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", + "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required", + "PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd3", + "UMask": "0x01", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", + "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram", + "PublicDescription": "Retired load instructions which data sources missed L3 but serviced from local DRAM.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd3", + "UMask": "0x02", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "BriefDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "PublicDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd3", + "UMask": "0x04", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "BriefDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "PublicDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd3", + "UMask": "0x08", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "BriefDescription": "Retired load instructions whose data sources was forwarded from a remote cache", + "PublicDescription": "Retired load instructions whose data sources was forwarded from a remote cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd4", + "UMask": "0x04", + "EventName": "MEM_LOAD_MISC_RETIRED.UC", + "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.", + "PublicDescription": "Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xe0", + "UMask": "0x20", + "EventName": "MISC2_RETIRED.LFENCE", + "BriefDescription": "LFENCE instructions retired", + "PublicDescription": "number of LFENCE retired instructions", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xe5", + "UMask": "0x03", + "EventName": "MEM_UOP_RETIRED.ANY", + "BriefDescription": "Retired memory uops for any access", + "PublicDescription": "Number of retired micro-operations (uops) for load or store memory accesses", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe7", + "UMask": "0x03", + "EventName": "INT_VEC_RETIRED.ADD_128", + "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.", + "PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vector instructions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe7", + "UMask": "0x0c", + "EventName": "INT_VEC_RETIRED.ADD_256", + "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.", + "PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vector instructions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe7", + "UMask": "0x10", + "EventName": "INT_VEC_RETIRED.VNNI_128", + "BriefDescription": "INT_VEC_RETIRED.VNNI_128", + "PublicDescription": "INT_VEC_RETIRED.VNNI_128", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe7", + "UMask": "0x13", + "EventName": "INT_VEC_RETIRED.128BIT", + "BriefDescription": "INT_VEC_RETIRED.128BIT", + "PublicDescription": "INT_VEC_RETIRED.128BIT", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe7", + "UMask": "0x20", + "EventName": "INT_VEC_RETIRED.VNNI_256", + "BriefDescription": "INT_VEC_RETIRED.VNNI_256", + "PublicDescription": "INT_VEC_RETIRED.VNNI_256", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe7", + "UMask": "0x40", + "EventName": "INT_VEC_RETIRED.SHUFFLES", + "BriefDescription": "INT_VEC_RETIRED.SHUFFLES", + "PublicDescription": "INT_VEC_RETIRED.SHUFFLES", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe7", + "UMask": "0x80", + "EventName": "INT_VEC_RETIRED.MUL_256", + "BriefDescription": "INT_VEC_RETIRED.MUL_256", + "PublicDescription": "INT_VEC_RETIRED.MUL_256", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe7", + "UMask": "0xac", + "EventName": "INT_VEC_RETIRED.256BIT", + "BriefDescription": "INT_VEC_RETIRED.256BIT", + "PublicDescription": "INT_VEC_RETIRED.256BIT", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xec", + "UMask": "0x02", + "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", + "BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.", + "PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xec", + "UMask": "0x10", + "EventName": "CPU_CLK_UNHALTED.C01", + "BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state.", + "PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xec", + "UMask": "0x20", + "EventName": "CPU_CLK_UNHALTED.C02", + "BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state.", + "PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xec", + "UMask": "0x40", + "EventName": "CPU_CLK_UNHALTED.PAUSE", + "BriefDescription": "CPU_CLK_UNHALTED.PAUSE", + "PublicDescription": "CPU_CLK_UNHALTED.PAUSE", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xec", + "UMask": "0x40", + "EventName": "CPU_CLK_UNHALTED.PAUSE_INST", + "BriefDescription": "CPU_CLK_UNHALTED.PAUSE_INST", + "PublicDescription": "CPU_CLK_UNHALTED.PAUSE_INST", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xec", + "UMask": "0x70", + "EventName": "CPU_CLK_UNHALTED.C0_WAIT", + "BriefDescription": "Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 ACPI state.", + "PublicDescription": "Counts core clocks when the thread is in the C0.1 or C0.2 power saving optimized states (TPAUSE or UMWAIT instructions) or running the PAUSE instruction.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "BriefDescription": "Counts demand data reads that have any type of response.", + "PublicDescription": "Counts demand data reads that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F3FFC0002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.HWPF_L1D.ANY_RESPONSE", + "BriefDescription": "Counts data load hardware prefetch requests to the L1 data cache that have any type of response.", + "PublicDescription": "Counts data load hardware prefetch requests to the L1 data cache that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10400", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", + "BriefDescription": "Counts streaming stores that have any type of response.", + "PublicDescription": "Counts streaming stores that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10800", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F3FFC4477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.HWPF_L3.ANY_RESPONSE", + "BriefDescription": "Counts hardware prefetches to the L3 only that have any type of response.", + "PublicDescription": "Counts hardware prefetches to the L3 only that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x12380", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", + "BriefDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.", + "PublicDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.L3_HIT", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.L3_HIT", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F003C4477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.STREAMING_WR.L3_HIT", + "BriefDescription": "Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket.", + "PublicDescription": "Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80080800", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.HWPF_L3.L3_HIT", + "BriefDescription": "Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket.", + "PublicDescription": "Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80082380", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL", + "BriefDescription": "Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "PublicDescription": "Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x84000800", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.HWPF_L3.L3_MISS_LOCAL", + "BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "PublicDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x84002380", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F04C04477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.REMOTE", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F33004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.HWPF_L3.REMOTE", + "BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.", + "PublicDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x90002380", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", + "BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", + "PublicDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.L3_MISS", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F3FC00002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.L3_MISS", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F3FC04477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.STREAMING_WR.L3_MISS", + "BriefDescription": "Counts streaming stores that missed the local socket's L1, L2, and L3 caches.", + "PublicDescription": "Counts streaming stores that missed the local socket's L1, L2, and L3 caches.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x94000800", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.HWPF_L3.L3_MISS", + "BriefDescription": "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.", + "PublicDescription": "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x94002380", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", + "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "PublicDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104000002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104000004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.REMOTE_DRAM", + "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to another socket.", + "PublicDescription": "Counts demand data reads that were supplied by DRAM attached to another socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x730000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.REMOTE_DRAM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x730004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.DRAM", + "BriefDescription": "Counts demand data reads that were supplied by DRAM.", + "PublicDescription": "Counts demand data reads that were supplied by DRAM.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.DRAM", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C000002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.DRAM", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C000004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.DRAM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data.", + "PublicDescription": "Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C4477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "PublicDescription": "Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HIT_WITH_FWD", + "BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "PublicDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x830000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C4477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x830004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "BriefDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "PublicDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HITM", + "BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.", + "PublicDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1030000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C4477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1030004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.SNC_DRAM", + "BriefDescription": "Counts demand data reads that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand data reads that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x708000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.SNC_DRAM", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x708000002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.SNC_DRAM", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x708000004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.SNC_DRAM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x708004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HITM", + "BriefDescription": "Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HIT_WITH_FWD", + "BriefDescription": "Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x808000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.SNC_CACHE.HITM", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008000002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.SNC_CACHE.HIT_WITH_FWD", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x808000002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HITM", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008000004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HIT_WITH_FWD", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x808000004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HITM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HIT_WITH_FWD", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x808004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_DRAM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x70C004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.HWPF_L2.ANY_RESPONSE", + "BriefDescription": "Counts hardware prefetches (which bring data to L2) that have any type of response.", + "PublicDescription": "Counts hardware prefetches (which bring data to L2) that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10070", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster. It does not count misses to the L3 which go to Local CXL Type 2 Memory or Local Non DRAM.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster. It does not count misses to the L3 which go to Local CXL Type 2 Memory or Local Non DRAM.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x70CC04477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified).", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified).", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1830004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.REMOTE_MEMORY", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x733004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.RFO_TO_CORE.L3_HIT_M", + "BriefDescription": "Counts demand reads for ownership (RFO), hardware prefetch RFOs (which bring data to L2), and software prefetches for exclusive ownership (PREFETCHW) that hit to a (M)odified cacheline in the L3 or snoop filter.", + "PublicDescription": "Counts demand reads for ownership (RFO), hardware prefetch RFOs (which bring data to L2), and software prefetches for exclusive ownership (PREFETCHW) that hit to a (M)odified cacheline in the L3 or snoop filter.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F80040022", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.MODIFIED_WRITE.ANY_RESPONSE", + "BriefDescription": "Counts writebacks of modified cachelines and streaming stores that have any type of response.", + "PublicDescription": "Counts writebacks of modified cachelines and streaming stores that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10808", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.WRITE_ESTIMATE.MEMORY", + "BriefDescription": "Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM)", + "PublicDescription": "Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM)", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFBFF80822", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + } + ] +} \ No newline at end of file diff --git a/cmd/metrics/resources/perfmon/emr/emeraldrapids_metrics.json b/cmd/metrics/resources/perfmon/emr/emeraldrapids_metrics.json new file mode 100644 index 00000000..01e34067 --- /dev/null +++ b/cmd/metrics/resources/perfmon/emr/emeraldrapids_metrics.json @@ -0,0 +1,14490 @@ +{ + "Header": { + "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Metrics for 5th Generation Intel(R) Xeon(R) Processor Scalable Family0", + "DatePublished": "06/17/2025", + "Version": "1.1", + "Legend": "", + "TmaVersion": "5.1", + "TmaFlavor": "Full" + }, + "Metrics": [ + { + "MetricName": "cpu_operating_frequency", + "LegacyName": "metric_CPU operating frequency (in GHz)", + "Level": 1, + "BriefDescription": "CPU operating frequency (in GHz)", + "UnitOfMeasure": "GHz", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + } + ], + "Formula": "(a / b * c) / 1000000000", + "Category": "Freq", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "cpu_utilization", + "LegacyName": "metric_CPU utilization %", + "Level": 1, + "BriefDescription": "Percentage of time spent in the active CPU power state C0", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + }, + { + "Name": "TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "Category": "Util", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "cpi", + "LegacyName": "metric_CPI", + "Level": 1, + "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "CPI", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "loads_per_instr", + "LegacyName": "metric_loads per instr", + "Level": 1, + "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "stores_per_instr", + "LegacyName": "metric_stores per instr", + "Level": 1, + "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l1d_mpi", + "LegacyName": "metric_L1D MPI (includes data+rfo w/ prefetches)", + "Level": 1, + "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "L1D.REPLACEMENT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l1d_demand_data_read_hits_per_instr", + "LegacyName": "metric_L1D demand data read hits per instr", + "Level": 1, + "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L1_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", + "LegacyName": "metric_L1-I code read misses (w/ prefetches) per instr", + "Level": 1, + "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "L2_RQSTS.ALL_CODE_RD", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, I-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_demand_data_read_hits_per_instr", + "LegacyName": "metric_L2 demand data read hits per instr", + "Level": 1, + "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_mpi", + "LegacyName": "metric_L2 MPI (includes code+data+rfo w/ prefetches)", + "Level": 1, + "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "L2_LINES_IN.ALL", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_demand_data_read_mpi", + "LegacyName": "metric_L2 demand data read MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_demand_code_mpi", + "LegacyName": "metric_L2 demand code MPI", + "Level": 1, + "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "L2_RQSTS.CODE_RD_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, I-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_data_read_mpi_demand_plus_prefetch", + "LegacyName": "metric_LLC data read MPI (demand+prefetch)", + "Level": 1, + "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF", + "Alias": "c" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "(a + b + c) / d", + "Category": "MPI, D-side", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_code_read_mpi_demand_plus_prefetch", + "LegacyName": "metric_LLC code read MPI (demand+prefetch)", + "Level": 1, + "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "Alias": "b" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "b / d", + "Category": "MPI, I-side", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_latency", + "LegacyName": "metric_Average LLC demand data read miss latency (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "Latency", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_latency_for_local_requests", + "LegacyName": "metric_Average LLC demand data read miss latency for LOCAL requests (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to local memory in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "Latency", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_latency_for_remote_requests", + "LegacyName": "metric_Average LLC demand data read miss latency for REMOTE requests (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to remote memory in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "Latency", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_to_dram_latency", + "LegacyName": "metric_Average LLC demand data read miss to DRAM latency (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to DRAM in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "Latency", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "itlb_2nd_level_mpi", + "LegacyName": "metric_ITLB (2nd level) MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, I-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "itlb_2nd_level_large_page_mpi", + "LegacyName": "metric_ITLB (2nd level) large page MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "dtlb_2nd_level_load_mpi", + "LegacyName": "metric_DTLB (2nd level) load MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi", + "LegacyName": "metric_DTLB (2nd level) 2MB large page load MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "dtlb_2nd_level_store_mpi", + "LegacyName": "metric_DTLB (2nd level) store MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "numa_reads_addressed_to_local_dram", + "LegacyName": "metric_NUMA %_Reads addressed to local DRAM", + "Level": 1, + "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", + "Alias": "c" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (a + b) / (a + b + c + d)", + "Category": "NUMA", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "numa_reads_addressed_to_remote_dram", + "LegacyName": "metric_NUMA %_Reads addressed to remote DRAM", + "Level": 1, + "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", + "Alias": "c" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (c + d) / (a + b + c + d)", + "Category": "NUMA", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "uncore_frequency", + "LegacyName": "metric_uncore frequency GHz", + "Level": 1, + "BriefDescription": "Uncore operating frequency in GHz", + "UnitOfMeasure": "GHz", + "Events": [ + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "b" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "(a / (b * socket_count) / 1000000000) / DURATIONTIMEINSECONDS", + "Category": "Freq", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "upi_data_transmit_bw", + "LegacyName": "metric_UPI Data transmit BW (MB/sec) (only data)", + "Level": 1, + "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_UPI_TxL_FLITS.ALL_DATA", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * (64 / 9.0) / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW", + "ResolutionLevels": "UPI, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_bandwidth_read", + "LegacyName": "metric_memory bandwidth read (MB/sec)", + "Level": 1, + "BriefDescription": "DDR memory read bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT.RD", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, MC", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_bandwidth_write", + "LegacyName": "metric_memory bandwidth write (MB/sec)", + "Level": 1, + "BriefDescription": "DDR memory write bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT.WR", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, MC", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_bandwidth_total", + "LegacyName": "metric_memory bandwidth total (MB/sec)", + "Level": 1, + "BriefDescription": "DDR memory bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT.RD", + "Alias": "a" + }, + { + "Name": "UNC_M_CAS_COUNT.WR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, MC", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_extra_write_bw_due_to_directory_updates", + "LegacyName": "metric_memory extra write b/w due to directory updates (MB/sec)", + "Level": 1, + "BriefDescription": "Memory write bandwidth (MB/sec) caused by directory updates; includes DDR and Intel(R) Optane(TM) Persistent Memory(PMEM).", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_DIR_UPDATE.HA", + "Alias": "a" + }, + { + "Name": "UNC_CHA_DIR_UPDATE.TOR", + "Alias": "b" + }, + { + "Name": "UNC_M2M_DIRECTORY_UPDATE.ANY", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "((a + b + c) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, MC", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_read", + "LegacyName": "metric_IO_bandwidth_disk_or_network_writes (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_write", + "LegacyName": "metric_IO_bandwidth_disk_or_network_reads (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_read_l3_miss", + "LegacyName": "metric_IO % of inbound reads that miss L3", + "Level": 1, + "BriefDescription": "Percentage of inbound reads initiated by end device controllers that miss the L3 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_partial_write_l3_miss", + "LegacyName": "metric_IO % of inbound partial writes that miss L3", + "Level": 1, + "BriefDescription": "Percentage of inbound partial cacheline writes initiated by end device controllers that miss the L3 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_RFO", + "Alias": "c" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ((b + d) / (a + c) )", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_full_write_l3_miss", + "LegacyName": "metric_IO % of inbound full writes that miss L3", + "Level": 1, + "BriefDescription": "Percentage of inbound full cacheline writes initiated by end device controllers that miss the L3 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * (b / a)", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "percent_uops_delivered_from_decoded_icache", + "LegacyName": "metric_% Uops delivered from decoded Icache (DSB)", + "Level": 1, + "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "LSD.UOPS", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (a / (a + b + c + d) )", + "Category": "I-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline", + "LegacyName": "metric_% Uops delivered from legacy decode pipeline (MITE)", + "Level": 1, + "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "LSD.UOPS", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (b / (a + b + c + d) )", + "Category": "I-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "percent_uops_delivered_from_microcode_sequencer", + "LegacyName": "metric_% Uops delivered from microcode sequencer (MS)", + "Level": 1, + "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "LSD.UOPS", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (c / (a + b + c + d) )", + "Category": "I-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_read_local", + "LegacyName": "metric_IO bandwidth read local (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the local CPU socket.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_read_remote", + "LegacyName": "metric_IO bandwidth read remote (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from a remote CPU socket.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_write_local", + "LegacyName": "metric_IO bandwidth write local (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the local CPU socket.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_write_remote", + "LegacyName": "metric_IO bandwidth write remote (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to a remote CPU socket.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_read_l3_miss", + "LegacyName": "metric_IO_bandwidth_read_L3_miss (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of inbound IO reads that are initiated by end device controllers that are requesting memory from the CPU and miss the L3 cache.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_write_l3_miss", + "LegacyName": "metric_IO_bandwidth_write_L3_miss (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of inbound IO writes that are initiated by end device controllers that are writing memory to the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Bottleneck_Mispredictions", + "LegacyName": "metric_TMA_Bottleneck_Mispredictions", + "Level": 1, + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.MS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "h" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "i" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "j" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "k" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "l" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "m" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "n" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "o" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "p" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "q" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "r" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "s" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "t" + }, + { + "Name": "DECODE.LCP", + "Alias": "u" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "v" + } + ], + "Constants": [], + "Formula": "100 * ( 1 - ( 10 * ( a / ( b ) ) * ( max( ( c / ( d + e + f + g ) ) * ( 1 - h / ( i - j ) ) , 0.0001 ) ) / ( c / ( d + e + f + g ) ) ) ) * ( ( c / ( d + e + f + g ) ) + ( ( k / ( d + e + f + g ) - l / ( b ) ) ) * ( ( ( c / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - l / ( b ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) * m / ( n ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) )", + "BaseFormula": "100 * ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * ( tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Mispredictions" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Mispredictions > 20", + "ThresholdIssues": "$issueBM" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BadSpec;BrMispredicts;BvMP", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Big_Code", + "LegacyName": "metric_TMA_Bottleneck_Big_Code", + "Level": 1, + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "j" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "k" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "l" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "m" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "n" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "o" + }, + { + "Name": "DECODE.LCP", + "Alias": "p" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "q" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( h / ( i ) ) + ( j / ( i ) ) + ( k / ( i ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) )", + "BaseFormula": "100 * tma_fetch_latency * ( tma_itlb_misses + tma_icache_misses + tma_unknown_branches ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Big_Code" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Big_Code > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvBC;BigFootprint;Fed;Frontend;IcMiss;MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Instruction_Fetch_BW", + "LegacyName": "metric_TMA_Bottleneck_Instruction_Fetch_BW", + "Level": 1, + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "UOPS_RETIRED.MS", + "Alias": "g" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "h" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "i" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "j" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "k" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "l" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "m" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "n" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "o" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "p" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "q" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "r" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "s" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "t" + }, + { + "Name": "DECODE.LCP", + "Alias": "u" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "v" + }, + { + "Name": "INST_RETIRED.REP_ITERATION", + "Alias": "w" + }, + { + "Name": "UOPS_RETIRED.MS:c1", + "Alias": "x" + }, + { + "Name": "IDQ.MS_CYCLES_ANY", + "Alias": "y" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a / ( a + b + c + d ) - e / ( f ) ) - ( 1 - ( 10 * ( g / ( f ) ) * ( max( ( h / ( a + b + c + d ) ) * ( 1 - i / ( j - k ) ) , 0.0001 ) ) / ( h / ( a + b + c + d ) ) ) ) * ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) - ( ( 1 - w / x ) * ( ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) * ( ( ( 1 - ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * m / ( n ) ) + ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) * ( max( ( h / ( a + b + c + d ) ) * ( 1 - i / ( j - k ) ) , 0.0001 ) ) / ( h / ( a + b + c + d ) ) ) / ( ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) + ( ( 1 - ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * m / ( n ) ) + ( q / ( n ) ) ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) + ( max( y , x / ( s / t ) ) / ( z if smt_on else ( n ) ) / 2.4 ) ) ) ) - ( 100 * ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( p / ( n ) ) + ( o / ( n ) ) + ( q / ( n ) ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) )", + "BaseFormula": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - inst_retired.rep_iteration / uops_retired.ms:c1 ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_ms ) ) ) - tma_bottleneck_big_code", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Instruction_Fetch_BW" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Instruction_Fetch_BW > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvFB;Fed;FetchBW;Frontend", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Data_Cache_Memory_Bandwidth", + "LegacyName": "metric_TMA_Bottleneck_Data_Cache_Memory_Bandwidth", + "Level": 1, + "BriefDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "a" + }, + { + "Name": "L1D_PEND_MISS.FB_FULL", + "Alias": "a_a" + }, + { + "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", + "Alias": "a_b" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a_c" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "a_d" + }, + { + "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "a_e" + }, + { + "Name": "LD_BLOCKS.STORE_FORWARD", + "Alias": "a_f" + }, + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "a_g" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a_i" + }, + { + "Name": "L2_RQSTS.ALL_RFO", + "Alias": "a_j" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "a_k" + }, + { + "Name": "L2_RQSTS.RFO_HIT", + "Alias": "a_l" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "a_m" + }, + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a_n" + }, + { + "Name": "MEM_LOAD_COMPLETED.L1_MISS_ANY", + "Alias": "a_o" + }, + { + "Name": "LD_BLOCKS.NO_SR", + "Alias": "a_p" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "h" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Alias": "i" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "k" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Alias": "l" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "m" + }, + { + "Name": "XQ.FULL_CYCLES", + "Alias": "n" + }, + { + "Name": "L1D_PEND_MISS.L2_STALLS", + "Alias": "o" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "p" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Alias": "s" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "t" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "u" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Alias": "v" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "w" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "x" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "Alias": "y" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": "20", + "Alias": "dependentloadsweight" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + }, + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "q" + } + ], + "Formula": "( 100 * ( ( ( a / ( b + c + d + e ) ) * ( ( ( f / ( g ) ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( min( g , l ) ) / ( g ) ) / ( ( ( min( g , l ) ) / ( g ) ) + ( ( min( g , m ) ) / ( g ) - ( ( min( g , l ) ) / ( g ) ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( j - f ) / ( g ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( min( g , l ) ) / ( g ) ) / ( ( ( min( g , l ) ) / ( g ) ) + ( ( min( g , m ) ) / ( g ) - ( ( min( g , l ) ) / ( g ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( ( j - f ) / ( g ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( n + o ) / ( g ) ) / ( ( ( ( ( 81 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( s * ( t / ( t + u ) ) ) + ( ( 79 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( v ) ) * ( 1 + ( w / x ) / 2 ) / ( g ) ) + ( ( ( 79 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( y + s * ( 1 - ( t / ( t + u ) ) ) ) * ( 1 + ( w / x ) / 2 ) / ( g ) ) + ( ( ( 37 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( z * ( 1 + ( w / x ) / 2 ) ) / ( g ) ) + ( ( n + o ) / ( g ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( max( ( h - i ) / ( g ) , 0 ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( a_a / ( g ) ) / ( ( min( ( 7 ) * a_b + a_c , max( a_d - a_e , 0 ) ) / ( g ) ) + ( 13 * a_f / ( g ) ) + ( min( 2 * ( a_g - w - x ) * dependentloadsweight / 100 , max( a_d - a_e , 0 ) ) / ( g ) ) + ( ( 16 * max( 0 , a_i - a_j ) + ( a_i / a_k ) * ( ( 10 ) * a_l + ( min( g , a_m ) ) ) ) / ( g ) ) + ( ( a_n / a_o ) * a_p / ( g ) ) + ( a_a / ( g ) ) ) ) ) ) )", + "BaseFormula": "( 100 * ( ( tma_memory_bound * ( tma_dram_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_mem_bandwidth / ( tma_mem_bandwidth + tma_mem_latency ) ) ) + ( tma_memory_bound * hbm_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * tma_mem_bandwidth / ( tma_mem_bandwidth + tma_mem_latency ) + ( tma_memory_bound * ( tma_l3_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_sq_full / ( tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full ) ) ) + ( tma_memory_bound * ( tma_l1_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_fb_full / ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_fb_full ) ) ) ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Data_Cache_Memory_Bandwidth" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Data_Cache_Memory_Bandwidth > 20", + "ThresholdIssues": "$issueBW" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMB;Mem;MemoryBW;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Data_Cache_Memory_Latency", + "LegacyName": "metric_TMA_Bottleneck_Data_Cache_Memory_Latency", + "Level": 1, + "BriefDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "a_a" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "a_c" + }, + { + "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "a_d" + }, + { + "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", + "Alias": "a_e" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a_f" + }, + { + "Name": "LD_BLOCKS.STORE_FORWARD", + "Alias": "a_g" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a_h" + }, + { + "Name": "L2_RQSTS.ALL_RFO", + "Alias": "a_i" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "a_j" + }, + { + "Name": "L2_RQSTS.RFO_HIT", + "Alias": "a_k" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "a_l" + }, + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a_m" + }, + { + "Name": "MEM_LOAD_COMPLETED.L1_MISS_ANY", + "Alias": "a_n" + }, + { + "Name": "LD_BLOCKS.NO_SR", + "Alias": "a_o" + }, + { + "Name": "L1D_PEND_MISS.FB_FULL", + "Alias": "a_p" + }, + { + "Name": "MEM_INST_RETIRED.SPLIT_STORES", + "Alias": "a_q" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "a_r" + }, + { + "Name": "MEM_STORE_RETIRED.L2_HIT", + "Alias": "a_s" + }, + { + "Name": "OCR.DEMAND_RFO.L3_MISS:ocr_msr_val=0x103b800002", + "Alias": "a_t" + }, + { + "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "Alias": "a_u" + }, + { + "Name": "OCR.STREAMING_WR.ANY_RESPONSE", + "Alias": "a_v" + }, + { + "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", + "Alias": "a_w" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a_x" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "h" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Alias": "i" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "k" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "l" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Alias": "m" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "n" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Alias": "q" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "r" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "s" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Alias": "t" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "u" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "v" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Alias": "w" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "Alias": "x" + }, + { + "Name": "XQ.FULL_CYCLES", + "Alias": "y" + }, + { + "Name": "L1D_PEND_MISS.L2_STALLS", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": "20", + "Alias": "dependentloadsweight" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + }, + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "o" + }, + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( ( a / ( b + c + d + e ) ) * ( ( ( f / ( g ) ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( min( g , l ) ) / ( g ) - ( ( min( g , m ) ) / ( g ) ) ) / ( ( ( min( g , m ) ) / ( g ) ) + ( ( min( g , l ) ) / ( g ) - ( ( min( g , m ) ) / ( g ) ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( j - f ) / ( g ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( min( g , l ) ) / ( g ) - ( ( min( g , m ) ) / ( g ) ) ) / ( ( ( min( g , m ) ) / ( g ) ) + ( ( min( g , l ) ) / ( g ) - ( ( min( g , m ) ) / ( g ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( ( j - f ) / ( g ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( ( 37 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( q * ( 1 + ( r / s ) / 2 ) ) / ( g ) ) / ( ( ( ( ( 81 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( t * ( u / ( u + v ) ) ) + ( ( 79 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( w ) ) * ( 1 + ( r / s ) / 2 ) / ( g ) ) + ( ( ( 79 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( x + t * ( 1 - ( u / ( u + v ) ) ) ) * ( 1 + ( r / s ) / 2 ) / ( g ) ) + ( ( ( 37 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( q * ( 1 + ( r / s ) / 2 ) ) / ( g ) ) + ( ( y + z ) / ( g ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( i - j ) / ( g ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( max( ( h - i ) / ( g ) , 0 ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( min( 2 * ( a_a - r - s ) * dependentloadsweight / 100 , max( a_c - a_d , 0 ) ) / ( g ) ) / ( ( min( ( 7 ) * a_e + a_f , max( a_c - a_d , 0 ) ) / ( g ) ) + ( 13 * a_g / ( g ) ) + ( min( 2 * ( a_a - r - s ) * dependentloadsweight / 100 , max( a_c - a_d , 0 ) ) / ( g ) ) + ( ( 16 * max( 0 , a_h - a_i ) + ( a_h / a_j ) * ( ( 10 ) * a_k + ( min( g , a_l ) ) ) ) / ( g ) ) + ( ( a_m / a_n ) * a_o / ( g ) ) + ( a_p / ( g ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( max( ( h - i ) / ( g ) , 0 ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( 16 * max( 0 , a_h - a_i ) + ( a_h / a_j ) * ( ( 10 ) * a_k + ( min( g , a_l ) ) ) ) / ( g ) ) / ( ( min( ( 7 ) * a_e + a_f , max( a_c - a_d , 0 ) ) / ( g ) ) + ( 13 * a_g / ( g ) ) + ( min( 2 * ( a_a - r - s ) * dependentloadsweight / 100 , max( a_c - a_d , 0 ) ) / ( g ) ) + ( ( 16 * max( 0 , a_h - a_i ) + ( a_h / a_j ) * ( ( 10 ) * a_k + ( min( g , a_l ) ) ) ) / ( g ) ) + ( ( a_m / a_n ) * a_o / ( g ) ) + ( a_p / ( g ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( max( ( h - i ) / ( g ) , 0 ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( a_m / a_n ) * a_o / ( g ) ) / ( ( min( ( 7 ) * a_e + a_f , max( a_c - a_d , 0 ) ) / ( g ) ) + ( 13 * a_g / ( g ) ) + ( min( 2 * ( a_a - r - s ) * dependentloadsweight / 100 , max( a_c - a_d , 0 ) ) / ( g ) ) + ( ( 16 * max( 0 , a_h - a_i ) + ( a_h / a_j ) * ( ( 10 ) * a_k + ( min( g , a_l ) ) ) ) / ( g ) ) + ( ( a_m / a_n ) * a_o / ( g ) ) + ( a_p / ( g ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( k / ( g ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( a_q / ( a_r if smt_on else ( g ) ) ) / ( ( ( ( a_s * ( 10 ) * ( 1 - ( a_h / a_j ) ) ) + ( 1 - ( a_h / a_j ) ) * ( min( g , a_l ) ) ) / ( g ) ) + ( ( ( 170 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_t + ( 81 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_u ) / ( g ) ) + ( a_q / ( a_r if smt_on else ( g ) ) ) + ( 9 * a_v / ( g ) ) + ( ( ( 7 ) * a_w + a_x ) / ( a_r if smt_on else ( g ) ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( k / ( g ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( ( a_s * ( 10 ) * ( 1 - ( a_h / a_j ) ) ) + ( 1 - ( a_h / a_j ) ) * ( min( g , a_l ) ) ) / ( g ) ) / ( ( ( ( a_s * ( 10 ) * ( 1 - ( a_h / a_j ) ) ) + ( 1 - ( a_h / a_j ) ) * ( min( g , a_l ) ) ) / ( g ) ) + ( ( ( 170 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_t + ( 81 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_u ) / ( g ) ) + ( a_q / ( a_r if smt_on else ( g ) ) ) + ( 9 * a_v / ( g ) ) + ( ( ( 7 ) * a_w + a_x ) / ( a_r if smt_on else ( g ) ) ) ) ) ) )", + "BaseFormula": "100 * ( ( tma_memory_bound * ( tma_dram_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_mem_latency / ( tma_mem_bandwidth + tma_mem_latency ) ) ) + ( tma_memory_bound * hbm_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * tma_mem_latency / ( tma_mem_bandwidth + tma_mem_latency ) + ( tma_memory_bound * ( tma_l3_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_l3_hit_latency / ( tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full ) ) ) + ( tma_memory_bound * tma_l2_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) + ( tma_memory_bound * ( tma_l1_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_l1_latency_dependency / ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_fb_full ) ) ) + ( tma_memory_bound * ( tma_l1_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_lock_latency / ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_fb_full ) ) ) + ( tma_memory_bound * ( tma_l1_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_split_loads / ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_fb_full ) ) ) + ( tma_memory_bound * ( tma_store_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_split_stores / ( tma_store_latency + tma_false_sharing + tma_split_stores + tma_streaming_stores + tma_dtlb_store ) ) ) + ( tma_memory_bound * ( tma_store_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_store_latency / ( tma_store_latency + tma_false_sharing + tma_split_stores + tma_streaming_stores + tma_dtlb_store ) ) ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Data_Cache_Memory_Latency" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Data_Cache_Memory_Latency > 20", + "ThresholdIssues": "$issueLat" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvML;Mem;MemoryLat;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Memory_Data_TLBs", + "LegacyName": "metric_TMA_Bottleneck_Memory_Data_TLBs", + "Level": 1, + "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_COMPLETED.L1_MISS_ANY", + "Alias": "a_a" + }, + { + "Name": "LD_BLOCKS.NO_SR", + "Alias": "a_b" + }, + { + "Name": "L1D_PEND_MISS.FB_FULL", + "Alias": "a_c" + }, + { + "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", + "Alias": "a_d" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a_e" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "a_f" + }, + { + "Name": "MEM_STORE_RETIRED.L2_HIT", + "Alias": "a_g" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a_h" + }, + { + "Name": "OCR.DEMAND_RFO.L3_MISS:ocr_msr_val=0x103b800002", + "Alias": "a_k" + }, + { + "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "Alias": "a_l" + }, + { + "Name": "MEM_INST_RETIRED.SPLIT_STORES", + "Alias": "a_m" + }, + { + "Name": "OCR.STREAMING_WR.ANY_RESPONSE", + "Alias": "a_n" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "f" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Alias": "g" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "h" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Alias": "i" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "k" + }, + { + "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", + "Alias": "l" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "m" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "n" + }, + { + "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "o" + }, + { + "Name": "LD_BLOCKS.STORE_FORWARD", + "Alias": "p" + }, + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "q" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "r" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "s" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "u" + }, + { + "Name": "L2_RQSTS.ALL_RFO", + "Alias": "v" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "w" + }, + { + "Name": "L2_RQSTS.RFO_HIT", + "Alias": "x" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "y" + }, + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "a_i" + }, + { + "Name": "20", + "Alias": "dependentloadsweight" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + }, + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a / ( b + c + d + e ) ) * ( ( max( ( f - g ) / ( h ) , 0 ) ) / max( ( a / ( b + c + d + e ) ) , ( ( max( ( f - g ) / ( h ) , 0 ) ) + ( ( g - i ) / ( h ) ) + ( ( i - j ) / ( h ) ) + ( ( j / ( h ) ) ) + ( k / ( h ) ) ) ) ) * ( ( min( ( 7 ) * l + m , max( n - o , 0 ) ) / ( h ) ) / max( ( max( ( f - g ) / ( h ) , 0 ) ) , ( ( min( ( 7 ) * l + m , max( n - o , 0 ) ) / ( h ) ) + ( 13 * p / ( h ) ) + ( min( 2 * ( q - r - s ) * dependentloadsweight / 100 , max( n - o , 0 ) ) / ( h ) ) + ( ( 16 * max( 0 , u - v ) + ( u / w ) * ( ( 10 ) * x + ( min( h , y ) ) ) ) / ( h ) ) + ( ( z / a_a ) * a_b / ( h ) ) + ( a_c / ( h ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( k / ( h ) ) / ( ( max( ( f - g ) / ( h ) , 0 ) ) + ( ( g - i ) / ( h ) ) + ( ( i - j ) / ( h ) ) + ( ( j / ( h ) ) ) + ( k / ( h ) ) ) ) * ( ( ( ( 7 ) * a_d + a_e ) / ( a_f if smt_on else ( h ) ) ) / ( ( ( ( a_g * ( 10 ) * ( 1 - ( u / w ) ) ) + ( 1 - ( u / w ) ) * ( min( h , y ) ) ) / ( h ) ) + ( ( ( 170 * ( ( ( h ) / a_h ) * a_i / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_k + ( 81 * ( ( ( h ) / a_h ) * a_i / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_l ) / ( h ) ) + ( a_m / ( a_f if smt_on else ( h ) ) ) + ( 9 * a_n / ( h ) ) + ( ( ( 7 ) * a_d + a_e ) / ( a_f if smt_on else ( h ) ) ) ) ) ) )", + "BaseFormula": "100 * ( tma_memory_bound * ( tma_l1_bound / max( tma_memory_bound , ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) ) * ( tma_dtlb_load / max( tma_l1_bound , ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_fb_full ) ) ) + ( tma_memory_bound * ( tma_store_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_dtlb_store / ( tma_store_latency + tma_false_sharing + tma_split_stores + tma_streaming_stores + tma_dtlb_store ) ) ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Memory_Data_TLBs" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Memory_Data_TLBs > 20", + "ThresholdIssues": "$issueTLB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMT;Mem;MemoryTLB;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Memory_Synchronization", + "LegacyName": "metric_TMA_Bottleneck_Memory_Synchronization", + "Level": 1, + "BriefDescription": "Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "Alias": "a_a" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Alias": "a_b" + }, + { + "Name": "XQ.FULL_CYCLES", + "Alias": "a_c" + }, + { + "Name": "L1D_PEND_MISS.L2_STALLS", + "Alias": "a_d" + }, + { + "Name": "OCR.DEMAND_RFO.L3_MISS:ocr_msr_val=0x103b800002", + "Alias": "a_e" + }, + { + "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "Alias": "a_f" + }, + { + "Name": "MEM_STORE_RETIRED.L2_HIT", + "Alias": "a_g" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a_h" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "a_i" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "a_j" + }, + { + "Name": "MEM_INST_RETIRED.SPLIT_STORES", + "Alias": "a_k" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "a_l" + }, + { + "Name": "OCR.STREAMING_WR.ANY_RESPONSE", + "Alias": "a_m" + }, + { + "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", + "Alias": "a_n" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a_o" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "a_p" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "a_q" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "a_r" + }, + { + "Name": "MACHINE_CLEARS.MEMORY_ORDERING", + "Alias": "a_s" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "a_t" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "h" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Alias": "i" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "k" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "l" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Alias": "m" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "n" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Alias": "q" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "Alias": "r" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "s" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "t" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", + "Alias": "u" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "Alias": "v" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Alias": "w" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "x" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "y" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + }, + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "o" + }, + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a / ( b + c + d + e ) ) * ( ( ( ( f / ( g ) ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( min( g , l ) ) / ( g ) - ( ( min( g , m ) ) / ( g ) ) ) / ( ( ( min( g , m ) ) / ( g ) ) + ( ( min( g , l ) ) / ( g ) - ( ( min( g , m ) ) / ( g ) ) ) ) ) * ( ( ( ( 170 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * q + ( ( 170 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * r ) * ( 1 + ( s / t ) / 2 ) / ( g ) ) / ( ( ( ( 109 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * u * ( 1 + ( s / t ) / 2 ) / ( g ) ) + ( ( ( 190 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * v * ( 1 + ( s / t ) / 2 ) / ( g ) ) + ( ( ( ( 170 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * q + ( ( 170 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * r ) * ( 1 + ( s / t ) / 2 ) / ( g ) ) ) + ( ( ( j - f ) / ( g ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( ( ( 81 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( w * ( x / ( x + y ) ) ) + ( ( 79 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( z ) ) * ( 1 + ( s / t ) / 2 ) / ( g ) ) + ( ( ( 79 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_a + w * ( 1 - ( x / ( x + y ) ) ) ) * ( 1 + ( s / t ) / 2 ) / ( g ) ) ) / ( ( ( ( ( 81 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( w * ( x / ( x + y ) ) ) + ( ( 79 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( z ) ) * ( 1 + ( s / t ) / 2 ) / ( g ) ) + ( ( ( 79 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_a + w * ( 1 - ( x / ( x + y ) ) ) ) * ( 1 + ( s / t ) / 2 ) / ( g ) ) + ( ( ( 37 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_b * ( 1 + ( s / t ) / 2 ) ) / ( g ) ) + ( ( a_c + a_d ) / ( g ) ) ) + ( ( k / ( g ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( 170 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_e + ( 81 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_f ) / ( g ) ) / ( ( ( ( ( a_g * ( 10 ) * ( 1 - ( a_h / a_i ) ) ) + ( 1 - ( a_h / a_i ) ) * ( min( g , a_j ) ) ) / ( g ) ) + ( ( ( 170 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_e + ( 81 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_f ) / ( g ) ) + ( a_k / ( a_l if smt_on else ( g ) ) ) + ( 9 * a_m / ( g ) ) + ( ( ( 7 ) * a_n + a_o ) / ( a_l if smt_on else ( g ) ) ) ) - ( ( ( a_g * ( 10 ) * ( 1 - ( a_h / a_i ) ) ) + ( 1 - ( a_h / a_i ) ) * ( min( g , a_j ) ) ) / ( g ) ) ) ) + ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - a_p / ( a_q ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( a_r / ( b + c + d + e ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - a_p / ( a_q ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( a_r / ( b + c + d + e ) ) ) ) * ( 1 - a_s / a_t ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - a_p / ( a_q ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( a_r / ( b + c + d + e ) ) ) ) * ( 1 - a_s / a_t ) , 0.0001 ) ) ) ) )", + "BaseFormula": "100 * ( tma_memory_bound * ( ( tma_dram_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_mem_latency / ( tma_mem_bandwidth + tma_mem_latency ) ) * tma_remote_cache / ( tma_local_mem + tma_remote_mem + tma_remote_cache ) + ( tma_l3_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_contested_accesses + tma_data_sharing ) / ( tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full ) + ( tma_store_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * tma_false_sharing / ( ( tma_store_latency + tma_false_sharing + tma_split_stores + tma_streaming_stores + tma_dtlb_store ) - tma_store_latency ) ) + tma_machine_clears * ( 1 - tma_other_nukes / ( tma_other_nukes ) ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Memory_Synchronization" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_Bottleneck_Memory_Synchronization > 10", + "ThresholdIssues": "$issueSyncxn" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMS;LockCont;Mem;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Compute_Bound_Est", + "LegacyName": "metric_TMA_Bottleneck_Compute_Bound_Est", + "Level": 1, + "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "e" + }, + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + }, + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.C02", + "Alias": "i" + }, + { + "Name": "EXE.AMX_BUSY", + "Alias": "j" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "k" + }, + { + "Name": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "Alias": "l" + }, + { + "Name": "RS.EMPTY_RESOURCE", + "Alias": "m" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "n" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "o" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "p" + }, + { + "Name": "EXE_ACTIVITY.2_3_PORTS_UTIL", + "Alias": "q" + }, + { + "Name": "UOPS_EXECUTED.CYCLES_GE_3", + "Alias": "r" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "s" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) * ( f / ( g ) ) / ( ( f / ( g ) ) + ( h / ( g ) + ( i / ( g ) ) ) + ( j / ( k if smt_on else ( g ) ) ) + ( ( ( ( l + max( m - h , 0 ) ) / ( g ) * ( n - o ) / ( g ) ) * ( g ) + ( p + ( d / ( b + c + d + a ) ) * q ) ) / ( g ) if ( f < ( n - o ) ) else ( p + ( d / ( b + c + d + a ) ) * q ) / ( g ) ) ) ) + ( ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) * ( j / ( k if smt_on else ( g ) ) ) / ( ( f / ( g ) ) + ( h / ( g ) + ( i / ( g ) ) ) + ( j / ( k if smt_on else ( g ) ) ) + ( ( ( ( l + max( m - h , 0 ) ) / ( g ) * ( n - o ) / ( g ) ) * ( g ) + ( p + ( d / ( b + c + d + a ) ) * q ) ) / ( g ) if ( f < ( n - o ) ) else ( p + ( d / ( b + c + d + a ) ) * q ) / ( g ) ) ) ) + ( ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) * ( ( ( ( ( l + max( m - h , 0 ) ) / ( g ) * ( n - o ) / ( g ) ) * ( g ) + ( p + ( d / ( b + c + d + a ) ) * q ) ) / ( g ) if ( f < ( n - o ) ) else ( p + ( d / ( b + c + d + a ) ) * q ) / ( g ) ) / ( ( f / ( g ) ) + ( h / ( g ) + ( i / ( g ) ) ) + ( j / ( k if smt_on else ( g ) ) ) + ( ( ( ( l + max( m - h , 0 ) ) / ( g ) * ( n - o ) / ( g ) ) * ( g ) + ( p + ( d / ( b + c + d + a ) ) * q ) ) / ( g ) if ( f < ( n - o ) ) else ( p + ( d / ( b + c + d + a ) ) * q ) / ( g ) ) ) ) * ( ( r / ( g ) ) / ( ( ( l + max( m - h , 0 ) ) / ( g ) * ( n - o ) / ( g ) ) + ( p / ( g ) ) + ( s / ( g ) ) + ( r / ( g ) ) ) ) ) )", + "BaseFormula": "100 * ( ( tma_core_bound * tma_divider / ( tma_divider + tma_serializing_operation + tma_amx_busy + tma_ports_utilization ) ) + ( tma_core_bound * tma_amx_busy / ( tma_divider + tma_serializing_operation + tma_amx_busy + tma_ports_utilization ) ) + ( tma_core_bound * ( tma_ports_utilization / ( tma_divider + tma_serializing_operation + tma_amx_busy + tma_ports_utilization ) ) * ( tma_ports_utilized_3m / ( tma_ports_utilized_0 + tma_ports_utilized_1 + tma_ports_utilized_2 + tma_ports_utilized_3m ) ) ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Compute_Bound_Est" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Compute_Bound_Est > 20", + "ThresholdIssues": "$issueComp" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvCB;Cor", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Irregular_Overhead", + "LegacyName": "metric_TMA_Bottleneck_Irregular_Overhead", + "Level": 1, + "BriefDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.REP_ITERATION", + "Alias": "a" + }, + { + "Name": "MACHINE_CLEARS.MEMORY_ORDERING", + "Alias": "a_a" + }, + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "a_b" + }, + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "a_c" + }, + { + "Name": "CPU_CLK_UNHALTED.C02", + "Alias": "a_d" + }, + { + "Name": "RS.EMPTY_RESOURCE", + "Alias": "a_e" + }, + { + "Name": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "Alias": "a_f" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "a_g" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "a_h" + }, + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "a_i" + }, + { + "Name": "EXE.AMX_BUSY", + "Alias": "a_j" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "a_k" + }, + { + "Name": "EXE_ACTIVITY.2_3_PORTS_UTIL", + "Alias": "a_l" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "a_m" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "a_n" + }, + { + "Name": "UOPS_RETIRED.MS:c1", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "h" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "i" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "j" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "k" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "l" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "m" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "n" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "o" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "p" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "q" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "r" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "s" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "t" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "u" + }, + { + "Name": "DECODE.LCP", + "Alias": "v" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "w" + }, + { + "Name": "IDQ.MS_CYCLES_ANY", + "Alias": "x" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "y" + }, + { + "Name": "UOPS_RETIRED.MS", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( ( 1 - a / b ) * ( ( ( c / ( d + e + f + g ) - h / ( i ) ) ) * ( ( ( 3 ) * j / ( k / l ) / ( m ) ) + ( n / ( m ) + ( o / ( m ) ) ) * ( ( ( 1 - ( ( p / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) ) * n / ( m ) ) + ( ( ( p / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) * n / ( m ) ) * ( max( ( p / ( d + e + f + g ) ) * ( 1 - q / ( r - s ) ) , 0.0001 ) ) / ( p / ( d + e + f + g ) ) ) / ( ( ( ( p / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) * n / ( m ) ) + ( ( 1 - ( ( p / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) ) * n / ( m ) ) + ( o / ( m ) ) ) ) / ( ( t / ( m ) ) + ( u / ( m ) ) + ( n / ( m ) + ( o / ( m ) ) ) + ( ( 3 ) * j / ( k / l ) / ( m ) ) + ( v / ( m ) ) + ( w / ( m ) ) ) + ( max( x , b / ( k / l ) ) / ( y if smt_on else ( m ) ) / 2.4 ) ) ) + ( 10 * ( z / ( i ) ) * ( max( ( p / ( d + e + f + g ) ) * ( 1 - q / ( r - s ) ) , 0.0001 ) ) / ( p / ( d + e + f + g ) ) ) * ( p / ( d + e + f + g ) ) + ( ( max( 0 , ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) - ( p / ( d + e + f + g ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) - ( p / ( d + e + f + g ) ) ) ) * ( 1 - a_a / s ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) - ( p / ( d + e + f + g ) ) ) ) * ( 1 - a_a / s ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( g / ( d + e + f + g ) ) - ( a_b / ( d + e + f + g ) ) ) ) * ( ( a_c / ( m ) + ( a_d / ( m ) ) ) + a_e / ( m ) * ( ( a_f + max( a_e - a_c , 0 ) ) / ( m ) * ( a_g - a_h ) / ( m ) ) ) / ( ( a_i / ( m ) ) + ( a_c / ( m ) + ( a_d / ( m ) ) ) + ( a_j / ( y if smt_on else ( m ) ) ) + ( ( ( ( a_f + max( a_e - a_c , 0 ) ) / ( m ) * ( a_g - a_h ) / ( m ) ) * ( m ) + ( a_k + ( f / ( d + e + f + g ) ) * a_l ) ) / ( m ) if ( a_i < ( a_g - a_h ) ) else ( a_k + ( f / ( d + e + f + g ) ) * a_l ) / ( m ) ) ) ) + ( ( ( ( z / ( i ) ) / ( ( max( 0 , ( a_m / ( d + e + f + g ) ) - ( z / ( i ) ) ) ) + ( z / ( i ) ) ) ) * ( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * a_n / ( i ) ) / ( z / ( i ) ) ) ) * ( a_m / ( d + e + f + g ) ) ) )", + "BaseFormula": "100 * ( ( ( 1 - inst_retired.rep_iteration / uops_retired.ms:c1 ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_ms ) ) + ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) * tma_branch_mispredicts + ( tma_machine_clears * tma_other_nukes / ( tma_other_nukes ) ) + ( tma_core_bound * ( tma_serializing_operation + rs.empty_resource / tma_info_thread_clks * tma_ports_utilized_0 ) / ( tma_divider + tma_serializing_operation + tma_amx_busy + tma_ports_utilization ) ) + ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * tma_heavy_operations ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Irregular_Overhead" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_Bottleneck_Irregular_Overhead > 10", + "ThresholdIssues": "$issueMS" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BvIO;Cor;Ret", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Other_Bottlenecks", + "LegacyName": "metric_TMA_Bottleneck_Other_Bottlenecks", + "Level": 1, + "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end. Examples include data-dependencies (Core Bound when Low ILP) and other unlisted memory-related stalls.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "a_a" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "a_b" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "a_c" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Alias": "a_d" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Alias": "a_e" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "a_f" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Alias": "a_g" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "a_h" + }, + { + "Name": "XQ.FULL_CYCLES", + "Alias": "a_i" + }, + { + "Name": "L1D_PEND_MISS.L2_STALLS", + "Alias": "a_j" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a_k" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Alias": "a_n" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "a_o" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "a_p" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Alias": "a_q" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "a_r" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "a_s" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "Alias": "a_t" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Alias": "a_u" + }, + { + "Name": "L1D_PEND_MISS.FB_FULL", + "Alias": "a_v" + }, + { + "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", + "Alias": "a_w" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a_x" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "a_y" + }, + { + "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "a_z" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "LD_BLOCKS.STORE_FORWARD", + "Alias": "b_a" + }, + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "b_b" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "b_d" + }, + { + "Name": "L2_RQSTS.ALL_RFO", + "Alias": "b_e" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "b_f" + }, + { + "Name": "L2_RQSTS.RFO_HIT", + "Alias": "b_g" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "b_h" + }, + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "b_i" + }, + { + "Name": "MEM_LOAD_COMPLETED.L1_MISS_ANY", + "Alias": "b_j" + }, + { + "Name": "LD_BLOCKS.NO_SR", + "Alias": "b_k" + }, + { + "Name": "MEM_INST_RETIRED.SPLIT_STORES", + "Alias": "b_l" + }, + { + "Name": "MEM_STORE_RETIRED.L2_HIT", + "Alias": "b_m" + }, + { + "Name": "OCR.DEMAND_RFO.L3_MISS:ocr_msr_val=0x103b800002", + "Alias": "b_n" + }, + { + "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "Alias": "b_o" + }, + { + "Name": "OCR.STREAMING_WR.ANY_RESPONSE", + "Alias": "b_p" + }, + { + "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", + "Alias": "b_q" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "b_r" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Alias": "b_s" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "Alias": "b_t" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", + "Alias": "b_u" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "Alias": "b_v" + }, + { + "Name": "MACHINE_CLEARS.MEMORY_ORDERING", + "Alias": "b_w" + }, + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "b_x" + }, + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "b_y" + }, + { + "Name": "CPU_CLK_UNHALTED.C02", + "Alias": "b_z" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "EXE.AMX_BUSY", + "Alias": "c_a" + }, + { + "Name": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "Alias": "c_b" + }, + { + "Name": "RS.EMPTY_RESOURCE", + "Alias": "c_c" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "c_d" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "c_e" + }, + { + "Name": "EXE_ACTIVITY.2_3_PORTS_UTIL", + "Alias": "c_f" + }, + { + "Name": "UOPS_EXECUTED.CYCLES_GE_3", + "Alias": "c_g" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "c_h" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "c_i" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "c_j" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "c_k" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "c_l" + }, + { + "Name": "INST_RETIRED.NOP", + "Alias": "c_m" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "j" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "k" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "l" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "m" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "n" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "o" + }, + { + "Name": "DECODE.LCP", + "Alias": "p" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "q" + }, + { + "Name": "UOPS_RETIRED.MS", + "Alias": "r" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "s" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "t" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "u" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "v" + }, + { + "Name": "INST_RETIRED.REP_ITERATION", + "Alias": "w" + }, + { + "Name": "UOPS_RETIRED.MS:c1", + "Alias": "x" + }, + { + "Name": "IDQ.MS_CYCLES_ANY", + "Alias": "y" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": 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b_e ) + ( b_d / b_f ) * ( ( 10 ) * b_g + ( min( i , b_h ) ) ) ) / ( i ) ) + ( ( b_i / b_j ) * b_k / ( i ) ) + ( a_v / ( i ) ) ) ) ) + ( ( a_a / ( b + c + d + e ) ) * ( ( a_f / ( i ) ) / ( ( max( ( a_c - a_d ) / ( i ) , 0 ) ) + ( ( a_d - a_e ) / ( i ) ) + ( ( a_e - a_b ) / ( i ) ) + ( ( a_b / ( i ) ) ) + ( a_f / ( i ) ) ) ) * ( ( ( ( 7 ) * b_q + b_r ) / ( z if smt_on else ( i ) ) ) / ( ( ( ( b_m * ( 10 ) * ( 1 - ( b_d / b_f ) ) ) + ( 1 - ( b_d / b_f ) ) * ( min( i , b_h ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_n + ( 81 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_o ) / ( i ) ) + ( b_l / ( z if smt_on else ( i ) ) ) + ( 9 * b_p / ( i ) ) + ( ( ( 7 ) * b_q + b_r ) / ( z if smt_on else ( i ) ) ) ) ) ) ) ) + ( 100 * ( ( a_a / ( b + c + d + e ) ) * ( ( ( ( a_b / ( i ) ) ) / ( ( max( ( a_c - a_d ) / ( i ) , 0 ) ) + ( ( a_d - a_e ) / ( i ) ) + ( ( a_e - a_b ) / ( i ) ) + ( ( a_b / ( i ) ) ) + ( a_f / ( i ) ) ) ) * ( ( ( min( i , a_h ) ) / ( i ) - ( ( min( i , a_g ) ) / ( i ) ) ) / ( ( ( min( i , a_g ) ) / ( i ) ) + ( ( min( i , a_h ) ) / ( i ) - ( ( min( i , a_g ) ) / ( i ) ) ) ) ) * ( ( ( ( 170 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_s + ( ( 170 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_t ) * ( 1 + ( a_r / a_s ) / 2 ) / ( i ) ) / ( ( ( ( 109 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_u * ( 1 + ( a_r / a_s ) / 2 ) / ( i ) ) + ( ( ( 190 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_v * ( 1 + ( a_r / a_s ) / 2 ) / ( i ) ) + ( ( ( ( 170 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_s + ( ( 170 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_t ) * ( 1 + ( a_r / a_s ) / 2 ) / ( i ) ) ) + ( ( ( a_e - a_b ) / ( i ) ) / ( ( max( ( a_c - a_d ) / ( i ) , 0 ) ) + ( ( a_d - a_e ) / ( i ) ) + ( ( a_e - a_b ) / ( i ) ) + ( ( a_b / ( i ) ) ) + ( a_f / ( i ) ) ) ) * ( ( ( ( ( 81 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_n * ( a_o / ( a_o + a_p ) ) ) + ( ( 79 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_q ) ) * ( 1 + ( a_r / a_s ) / 2 ) / ( i ) ) + ( ( ( 79 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_t + a_n * ( 1 - ( a_o / ( a_o + a_p ) ) ) ) * ( 1 + ( a_r / a_s ) / 2 ) / ( i ) ) ) / ( ( ( ( ( 81 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_n * ( a_o / ( a_o + a_p ) ) ) + ( ( 79 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_q ) ) * ( 1 + ( a_r / a_s ) / 2 ) / ( i ) ) + ( ( ( 79 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_t + a_n * ( 1 - ( a_o / ( a_o + a_p ) ) ) ) * ( 1 + ( a_r / a_s ) / 2 ) / ( i ) ) + ( ( ( 37 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_u * ( 1 + ( a_r / a_s ) / 2 ) ) / ( i ) ) + ( ( a_i + a_j ) / ( i ) ) ) + ( ( a_f / ( i ) ) / ( ( max( ( a_c - a_d ) / ( i ) , 0 ) ) + ( ( a_d - a_e ) / ( i ) ) + ( ( a_e - a_b ) / ( i ) ) + ( ( a_b / ( i ) ) ) + ( a_f / ( i ) ) ) ) * ( ( ( 170 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_n + ( 81 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_o ) / ( i ) ) / ( ( ( ( ( b_m * ( 10 ) * ( 1 - ( b_d / b_f ) ) ) + ( 1 - ( b_d / b_f ) ) * ( min( i , b_h ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_n + ( 81 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_o ) / ( i ) ) + ( b_l / ( z if smt_on else ( i ) ) ) + ( 9 * b_p / ( i ) ) + ( ( ( 7 ) * b_q + b_r ) / ( z if smt_on else ( i ) ) ) ) - ( ( ( b_m * ( 10 ) * ( 1 - ( b_d / b_f ) ) ) + ( 1 - ( b_d / b_f ) ) * ( min( i , b_h ) ) ) / ( i ) ) ) ) + ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - b_w / v ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - b_w / v ) , 0.0001 ) ) ) ) ) ) + ( 100 * ( ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_a / ( b + c + d + e ) ) ) ) * ( b_x / ( i ) ) / ( ( b_x / ( i ) ) + ( b_y / ( i ) + ( b_z / ( i ) ) ) + ( c_a / ( z if smt_on else ( i ) ) ) + ( ( ( ( c_b + max( c_c - b_y , 0 ) ) / ( i ) * ( c_d - a_c ) / ( i ) ) * ( i ) + ( c_e + ( d / ( b + c + d + e ) ) * c_f ) ) / ( i ) if ( b_x < ( c_d - a_c ) ) else ( c_e + ( d / ( b + c + d + e ) ) * c_f ) / ( i ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_a / ( b + c + d + e ) ) ) ) * ( c_a / ( z if smt_on else ( i ) ) ) / ( ( b_x / ( i ) ) + ( b_y / ( i ) + ( b_z / ( i ) ) ) + ( c_a / ( z if smt_on else ( i ) ) ) + ( ( ( ( c_b + max( c_c - b_y , 0 ) ) / ( i ) * ( c_d - a_c ) / ( i ) ) * ( i ) + ( c_e + ( d / ( b + c + d + e ) ) * c_f ) ) / ( i ) if ( b_x < ( c_d - a_c ) ) else ( c_e + ( d / ( b + c + d + e ) ) * c_f ) / ( i ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_a / ( b + c + d + e ) ) ) ) * ( ( ( ( ( c_b + max( c_c - b_y , 0 ) ) / ( i ) * ( c_d - a_c ) / ( i ) ) * ( i ) + ( c_e + ( d / ( b + c + d + e ) ) * c_f ) ) / ( i ) if ( b_x < ( c_d - a_c ) ) else ( c_e + ( d / ( b + c + d + e ) ) * c_f ) / ( i ) ) / ( ( b_x / ( i ) ) + ( b_y / ( i ) + ( b_z / ( i ) ) ) + ( c_a / ( z if smt_on else ( i ) ) ) + ( ( ( ( c_b + max( c_c - b_y , 0 ) ) / ( i ) * ( c_d - a_c ) / ( i ) ) * ( i ) + ( c_e + ( d / ( b + c + d + e ) ) * c_f ) ) / ( i ) if ( b_x < ( c_d - a_c ) ) else ( c_e + ( d / ( b + c + d + e ) ) * c_f ) / ( i ) ) ) ) * ( ( c_g / ( i ) ) / ( ( ( c_b + max( c_c - b_y , 0 ) ) / ( i ) * ( c_d - a_c ) / ( i ) ) + ( c_e / ( i ) ) + ( c_h / ( i ) ) + ( c_g / ( i ) ) ) ) ) ) ) + ( 100 * ( ( ( 1 - w / x ) * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) * ( ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) / ( ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) + ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( k / ( i ) ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) + ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2.4 ) ) ) + ( 10 * ( r / ( g ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) * ( s / ( b + c + d + e ) ) + ( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - b_w / v ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - b_w / v ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_a / ( b + c + d + e ) ) ) ) * ( ( b_y / ( i ) + ( b_z / ( i ) ) ) + c_c / ( i ) * ( ( c_b + max( c_c - b_y , 0 ) ) / ( i ) * ( c_d - a_c ) / ( i ) ) ) / ( ( b_x / ( i ) ) + ( b_y / ( i ) + ( b_z / ( i ) ) ) + ( c_a / ( z if smt_on else ( i ) ) ) + ( ( ( ( c_b + max( c_c - b_y , 0 ) ) / ( i ) * ( c_d - a_c ) / ( i ) ) * ( i ) + ( c_e + ( d / ( b + c + d + e ) ) * c_f ) ) / ( i ) if ( b_x < ( c_d - a_c ) ) else ( c_e + ( d / ( b + c + d + e ) ) * c_f ) / ( i ) ) ) ) + ( ( ( ( r / ( g ) ) / ( ( max( 0 , ( c_i / ( b + c + d + e ) ) - ( r / ( g ) ) ) ) + ( r / ( g ) ) ) ) * ( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c_j / ( g ) ) / ( r / ( g ) ) ) ) * ( c_i / ( b + c + d + e ) ) ) ) ) + ( 100 * ( ( c_k + 2 * c_l + c_m ) / ( g ) ) ) + ( 100 * ( ( d / ( b + c + d + e ) ) - ( ( c_k + 2 * c_l + c_m ) / ( g ) ) - ( ( ( ( r / ( g ) ) / ( ( max( 0 , ( c_i / ( b + c + d + e ) ) - ( r / ( g ) ) ) ) + ( r / ( g ) ) ) ) * ( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c_j / ( g ) ) / ( r / ( g ) ) ) ) * ( c_i / ( b + c + d + e ) ) ) ) ) )", + "BaseFormula": "100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_data_cache_memory_bandwidth + tma_bottleneck_data_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Other_Bottlenecks" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Other_Bottlenecks > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvOB;Cor;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Branching_Overhead", + "LegacyName": "metric_TMA_Bottleneck_Branching_Overhead", + "Level": 1, + "BriefDescription": "Total pipeline cost of instructions used for program control-flow - a subset of the Retiring category in TMA. Examples include function calls; loops and alignments. (A lower bound)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "b" + }, + { + "Name": "INST_RETIRED.NOP", + "Alias": "c" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + 2 * b + c ) / ( d ) )", + "BaseFormula": "100 * ( ( br_inst_retired.all_branches + 2 * br_inst_retired.near_call + inst_retired.nop ) / tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Branching_Overhead" + } + ], + "Formula": "a > 5", + "BaseFormula": "metric_TMA_Bottleneck_Branching_Overhead > 5", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvBO;Ret", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Useful_Work", + "LegacyName": "metric_TMA_Bottleneck_Useful_Work", + "Level": 1, + "BriefDescription": "Total pipeline cost of \"useful operations\" - the portion of Retiring category not covered by Branching_Overhead nor Irregular_Overhead.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "e" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "f" + }, + { + "Name": "INST_RETIRED.NOP", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + }, + { + "Name": "UOPS_RETIRED.MS", + "Alias": "i" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "j" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "k" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b + c + a + d ) ) - ( ( e + 2 * f + g ) / ( h ) ) - ( ( ( ( i / ( h ) ) / ( ( max( 0 , ( j / ( b + c + a + d ) ) - ( i / ( h ) ) ) ) + ( i / ( h ) ) ) ) * ( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * k / ( h ) ) / ( i / ( h ) ) ) ) * ( j / ( b + c + a + d ) ) ) )", + "BaseFormula": "100 * ( tma_retiring - ( ( br_inst_retired.all_branches + 2 * br_inst_retired.near_call + inst_retired.nop ) / tma_info_thread_slots ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * tma_heavy_operations ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Useful_Work" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Useful_Work > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvUW;Ret", + "LocateWith": "" + }, + { + "MetricName": "Frontend_Bound", + "LegacyName": "metric_TMA_Frontend_Bound(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( a + b + c + d ) - e / ( f ) )", + "BaseFormula": "perf_metrics.frontend_bound / ( perf_metrics.frontend_bound + perf_metrics.bad_speculation + perf_metrics.retiring + perf_metrics.backend_bound ) - int_misc.uop_dropping / tma_info_thread_slots", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 15", + "BaseFormula": "metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvFB;BvIO;TmaL1;PGO", + "LocateWith": "FRONTEND_RETIRED.LATENCY_GE_4" + }, + { + "MetricName": "Fetch_Latency", + "LegacyName": "metric_TMA_..Fetch_Latency(%)", + "ParentCategory": "Frontend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b + c + d + e ) - f / ( g ) ) )", + "BaseFormula": "( perf_metrics.fetch_latency / ( perf_metrics.frontend_bound + perf_metrics.bad_speculation + perf_metrics.retiring + perf_metrics.backend_bound ) - int_misc.uop_dropping / tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 15", + "BaseFormula": "metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Frontend;TmaL2", + "LocateWith": "FRONTEND_RETIRED.LATENCY_GE_16;FRONTEND_RETIRED.LATENCY_GE_8" + }, + { + "MetricName": "ICache_Misses", + "LegacyName": "metric_TMA_....ICache_Misses(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "icache_data.stalls / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....ICache_Misses(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....ICache_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss", + "LocateWith": "FRONTEND_RETIRED.L2_MISS;FRONTEND_RETIRED.L1I_MISS" + }, + { + "MetricName": "Code_L2_Hit", + "LegacyName": "metric_TMA_......Code_L2_Hit(%)", + "ParentCategory": "ICache_Misses", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles the CPU was stalled due to instruction cache misses that hit in the L2 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b ) ) - ( c / ( b ) ) ) )", + "BaseFormula": "max( 0 , tma_icache_misses - tma_code_l2_miss )", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Code_L2_Hit(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....ICache_Misses(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 15", + "BaseFormula": "metric_TMA_......Code_L2_Hit(%) > 5 & metric_TMA_....ICache_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "IcMiss;FetchLat;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Code_L2_Miss", + "LegacyName": "metric_TMA_......Code_L2_Miss(%)", + "ParentCategory": "ICache_Misses", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles the CPU was stalled due to instruction cache misses that miss in the L2 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "offcore_requests_outstanding.cycles_with_demand_code_rd / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Code_L2_Miss(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....ICache_Misses(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 15", + "BaseFormula": "metric_TMA_......Code_L2_Miss(%) > 5 & metric_TMA_....ICache_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "IcMiss;FetchLat;Offcore", + "LocateWith": "" + }, + { + "MetricName": "ITLB_Misses", + "LegacyName": "metric_TMA_....ITLB_Misses(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "icache_tag.stalls / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....ITLB_Misses(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....ITLB_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB", + "LocateWith": "FRONTEND_RETIRED.STLB_MISS;FRONTEND_RETIRED.ITLB_MISS" + }, + { + "MetricName": "Code_STLB_Hit", + "LegacyName": "metric_TMA_......Code_STLB_Hit(%)", + "ParentCategory": "ITLB_Misses", + "Level": 4, + "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) ITLB was missed by instructions fetches, that later on hit in second-level TLB (STLB)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "ITLB_MISSES.WALK_ACTIVE", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b ) ) - ( c / ( b ) ) ) )", + "BaseFormula": "max( 0 , tma_itlb_misses - tma_code_stlb_miss )", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Code_STLB_Hit(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....ITLB_Misses(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 15", + "BaseFormula": "metric_TMA_......Code_STLB_Hit(%) > 5 & metric_TMA_....ITLB_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat;MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Code_STLB_Miss", + "LegacyName": "metric_TMA_......Code_STLB_Miss(%)", + "ParentCategory": "ITLB_Misses", + "Level": 4, + "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by instruction fetches, performing a hardware page walk", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "itlb_misses.walk_active / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Code_STLB_Miss(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....ITLB_Misses(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 15", + "BaseFormula": "metric_TMA_......Code_STLB_Miss(%) > 5 & metric_TMA_....ITLB_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat;MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Code_STLB_Miss_4K", + "LegacyName": "metric_TMA_........Code_STLB_Miss_4K(%)", + "ParentCategory": "Code_STLB_Miss", + "Level": 5, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 4 KB pages for (instruction) code accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "ITLB_MISSES.WALK_COMPLETED_4K", + "Alias": "c" + }, + { + "Name": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b ) ) * c / ( c + d ) )", + "BaseFormula": "tma_code_stlb_miss * itlb_misses.walk_completed_4k / ( itlb_misses.walk_completed_4k + itlb_misses.walk_completed_2m_4m )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Code_STLB_Miss_4K(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......Code_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....ITLB_Misses(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 5 & d > 10 & e > 15", + "BaseFormula": "metric_TMA_........Code_STLB_Miss_4K(%) > 5 & metric_TMA_......Code_STLB_Miss(%) > 5 & metric_TMA_....ITLB_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat;MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Code_STLB_Miss_2M", + "LegacyName": "metric_TMA_........Code_STLB_Miss_2M(%)", + "ParentCategory": "Code_STLB_Miss", + "Level": 5, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 2 or 4 MB pages for (instruction) code accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "c" + }, + { + "Name": "ITLB_MISSES.WALK_COMPLETED_4K", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b ) ) * c / ( d + c ) )", + "BaseFormula": "tma_code_stlb_miss * itlb_misses.walk_completed_2m_4m / ( itlb_misses.walk_completed_4k + itlb_misses.walk_completed_2m_4m )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Code_STLB_Miss_2M(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......Code_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....ITLB_Misses(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 5 & d > 10 & e > 15", + "BaseFormula": "metric_TMA_........Code_STLB_Miss_2M(%) > 5 & metric_TMA_......Code_STLB_Miss(%) > 5 & metric_TMA_....ITLB_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat;MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Branch_Resteers", + "LegacyName": "metric_TMA_....Branch_Resteers(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) + ( c / ( b ) ) )", + "BaseFormula": "int_misc.clear_resteer_cycles / tma_info_thread_clks + tma_unknown_branches", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Branch_Resteers(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....Branch_Resteers(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "~overlap" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat", + "LocateWith": "BR_MISP_RETIRED.ALL_BRANCHES" + }, + { + "MetricName": "Mispredicts_Resteers", + "LegacyName": "metric_TMA_......Mispredicts_Resteers(%)", + "ParentCategory": "Branch_Resteers", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * h / ( i ) )", + "BaseFormula": "( tma_branch_mispredicts / tma_bad_speculation ) * int_misc.clear_resteer_cycles / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Mispredicts_Resteers(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Branch_Resteers(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 15", + "BaseFormula": "metric_TMA_......Mispredicts_Resteers(%) > 5 & metric_TMA_....Branch_Resteers(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "$issueBM" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP", + "LocateWith": "INT_MISC.CLEAR_RESTEER_CYCLES" + }, + { + "MetricName": "Clears_Resteers", + "LegacyName": "metric_TMA_......Clears_Resteers(%)", + "ParentCategory": "Branch_Resteers", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + } + ], + "Constants": [], + "Formula": "100 * ( ( 1 - ( ( a / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * h / ( i ) )", + "BaseFormula": "( 1 - ( tma_branch_mispredicts / tma_bad_speculation ) ) * int_misc.clear_resteer_cycles / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Clears_Resteers(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Branch_Resteers(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 15", + "BaseFormula": "metric_TMA_......Clears_Resteers(%) > 5 & metric_TMA_....Branch_Resteers(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "$issueMC" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;MachineClears", + "LocateWith": "INT_MISC.CLEAR_RESTEER_CYCLES" + }, + { + "MetricName": "Unknown_Branches", + "LegacyName": "metric_TMA_......Unknown_Branches(%)", + "ParentCategory": "Branch_Resteers", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "int_misc.unknown_branch_cycles / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Unknown_Branches(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Branch_Resteers(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 15", + "BaseFormula": "metric_TMA_......Unknown_Branches(%) > 5 & metric_TMA_....Branch_Resteers(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;BvBC;FetchLat", + "LocateWith": "FRONTEND_RETIRED.UNKNOWN_BRANCH" + }, + { + "MetricName": "MS_Switches", + "LegacyName": "metric_TMA_....MS_Switches(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "a" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "b" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( 3 ) * a / ( b / c ) / ( d ) )", + "BaseFormula": "( 3 ) * uops_retired.ms:c1:e1 / ( uops_retired.slots / uops_issued.any ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....MS_Switches(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....MS_Switches(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "$issueMC, $issueMS, $issueMV, $issueSO" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat;MicroSeq", + "LocateWith": "FRONTEND_RETIRED.MS_FLOWS" + }, + { + "MetricName": "LCP", + "LegacyName": "metric_TMA_....LCP(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DECODE.LCP", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "decode.lcp / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....LCP(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....LCP(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat", + "LocateWith": "" + }, + { + "MetricName": "DSB_Switches", + "LegacyName": "metric_TMA_....DSB_Switches(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "dsb2mite_switches.penalty_cycles / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....DSB_Switches(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....DSB_Switches(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;FetchLat", + "LocateWith": "FRONTEND_RETIRED.DSB_MISS" + }, + { + "MetricName": "Fetch_Bandwidth", + "LegacyName": "metric_TMA_..Fetch_Bandwidth(%)", + "ParentCategory": "Frontend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( a + b + c + d ) - e / ( f ) ) - ( ( g / ( a + b + c + d ) - e / ( f ) ) ) ) )", + "BaseFormula": "max( 0 , tma_frontend_bound - tma_fetch_latency )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Fetch_Bandwidth(%)" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_..Fetch_Bandwidth(%) > 20", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchBW;Frontend;TmaL2", + "LocateWith": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1;FRONTEND_RETIRED.LATENCY_GE_1;FRONTEND_RETIRED.LATENCY_GE_2" + }, + { + "MetricName": "MITE", + "LegacyName": "metric_TMA_....MITE(%)", + "ParentCategory": "Fetch_Bandwidth", + "Level": 3, + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.MITE_CYCLES_ANY", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_CYCLES_OK", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a - b ) / ( c if smt_on else ( d ) ) / 2 )", + "BaseFormula": "( idq.mite_cycles_any - idq.mite_cycles_ok ) / tma_info_core_core_clks / 2", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....MITE(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Bandwidth(%)" + } + ], + "Formula": "a > 10 & b > 20", + "BaseFormula": "metric_TMA_....MITE(%) > 10 & metric_TMA_..Fetch_Bandwidth(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;FetchBW", + "LocateWith": "FRONTEND_RETIRED.ANY_DSB_MISS" + }, + { + "MetricName": "Decoder0_Alone", + "LegacyName": "metric_TMA_......Decoder0_Alone(%)", + "ParentCategory": "MITE", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INST_DECODED.DECODERS:c1", + "Alias": "a" + }, + { + "Name": "INST_DECODED.DECODERS:c2", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a - b ) / ( c if smt_on else ( d ) ) / 2 )", + "BaseFormula": "( inst_decoded.decoders:c1 - inst_decoded.decoders:c2 ) / tma_info_core_core_clks / 2", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Decoder0_Alone(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....MITE(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Bandwidth(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20", + "BaseFormula": "metric_TMA_......Decoder0_Alone(%) > 10 & metric_TMA_....MITE(%) > 10 & metric_TMA_..Fetch_Bandwidth(%) > 20", + "ThresholdIssues": "$issueD0" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "DSB", + "LegacyName": "metric_TMA_....DSB(%)", + "ParentCategory": "Fetch_Bandwidth", + "Level": 3, + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.DSB_CYCLES_ANY", + "Alias": "a" + }, + { + "Name": "IDQ.DSB_CYCLES_OK", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a - b ) / ( c if smt_on else ( d ) ) / 2 )", + "BaseFormula": "( idq.dsb_cycles_any - idq.dsb_cycles_ok ) / tma_info_core_core_clks / 2", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....DSB(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Bandwidth(%)" + } + ], + "Formula": "a > 15 & b > 20", + "BaseFormula": "metric_TMA_....DSB(%) > 15 & metric_TMA_..Fetch_Bandwidth(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSB;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "MS", + "LegacyName": "metric_TMA_....MS(%)", + "ParentCategory": "Fetch_Bandwidth", + "Level": 3, + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the Microcode Sequencer (MS) unit - see Microcode_Sequencer node for details.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.MS_CYCLES_ANY", + "Alias": "a" + }, + { + "Name": "UOPS_RETIRED.MS:c1", + "Alias": "b" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "c" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "e" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "f" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( max( a , b / ( c / d ) ) / ( e if smt_on else ( f ) ) / 2.4 )", + "BaseFormula": "max( idq.ms_cycles_any , uops_retired.ms:c1 / ( uops_retired.slots / uops_issued.any ) ) / tma_info_core_core_clks / 2.4", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....MS(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Bandwidth(%)" + } + ], + "Formula": "a > 5 & b > 20", + "BaseFormula": "metric_TMA_....MS(%) > 5 & metric_TMA_..Fetch_Bandwidth(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq", + "LocateWith": "" + }, + { + "MetricName": "Bad_Speculation", + "LegacyName": "metric_TMA_Bad_Speculation(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) )", + "BaseFormula": "max( 1 - ( tma_frontend_bound + tma_backend_bound + tma_retiring ) , 0 )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 15", + "BaseFormula": "metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "TmaL1", + "LocateWith": "#NA" + }, + { + "MetricName": "Branch_Mispredicts", + "LegacyName": "metric_TMA_..Branch_Mispredicts(%)", + "ParentCategory": "Bad_Speculation", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b + c + d + e ) )", + "BaseFormula": "perf_metrics.branch_mispredicts / ( perf_metrics.frontend_bound + perf_metrics.bad_speculation + perf_metrics.retiring + perf_metrics.backend_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Branch_Mispredicts(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 10 & b > 15", + "BaseFormula": "metric_TMA_..Branch_Mispredicts(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "$issueBM" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2", + "LocateWith": "TOPDOWN.BR_MISPREDICT_SLOTS" + }, + { + "MetricName": "Other_Mispredicts", + "LegacyName": "metric_TMA_....Other_Mispredicts(%)", + "ParentCategory": "Branch_Mispredicts", + "Level": 3, + "BriefDescription": "This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "f" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "g" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( max( ( a / ( b + c + d + e ) ) * ( 1 - f / ( g - h ) ) , 0.0001 ) )", + "BaseFormula": "max( tma_branch_mispredicts * ( 1 - br_misp_retired.all_branches / ( int_misc.clears_count - machine_clears.count ) ) , 0.0001 )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Other_Mispredicts(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Branch_Mispredicts(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....Other_Mispredicts(%) > 5 & metric_TMA_..Branch_Mispredicts(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvIO;BrMispredicts", + "LocateWith": "" + }, + { + "MetricName": "Machine_Clears", + "LegacyName": "metric_TMA_..Machine_Clears(%)", + "ParentCategory": "Bad_Speculation", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) - ( g / ( a + b + c + d ) ) ) )", + "BaseFormula": "max( 0 , tma_bad_speculation - tma_branch_mispredicts )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Machine_Clears(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 10 & b > 15", + "BaseFormula": "metric_TMA_..Machine_Clears(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "$issueMC, $issueSyncxn" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2", + "LocateWith": "MACHINE_CLEARS.COUNT" + }, + { + "MetricName": "Other_Nukes", + "LegacyName": "metric_TMA_....Other_Nukes(%)", + "ParentCategory": "Machine_Clears", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "g" + }, + { + "Name": "MACHINE_CLEARS.MEMORY_ORDERING", + "Alias": "h" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "i" + } + ], + "Constants": [], + "Formula": "100 * ( max( ( max( 0 , ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) - ( g / ( a + b + c + d ) ) ) ) * ( 1 - h / i ) , 0.0001 ) )", + "BaseFormula": "max( tma_machine_clears * ( 1 - machine_clears.memory_ordering / machine_clears.count ) , 0.0001 )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Other_Nukes(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Machine_Clears(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....Other_Nukes(%) > 5 & metric_TMA_..Machine_Clears(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvIO;Machine_Clears", + "LocateWith": "" + }, + { + "MetricName": "Backend_Bound", + "LegacyName": "metric_TMA_Backend_Bound(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b + c + d + a ) )", + "BaseFormula": "perf_metrics.backend_bound / ( perf_metrics.frontend_bound + perf_metrics.bad_speculation + perf_metrics.retiring + perf_metrics.backend_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvOB;TmaL1", + "LocateWith": "TOPDOWN.BACKEND_BOUND_SLOTS" + }, + { + "MetricName": "Memory_Bound", + "LegacyName": "metric_TMA_..Memory_Bound(%)", + "ParentCategory": "Backend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b + c + d + e ) )", + "BaseFormula": "perf_metrics.memory_bound / ( perf_metrics.frontend_bound + perf_metrics.bad_speculation + perf_metrics.retiring + perf_metrics.backend_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20", + "BaseFormula": "metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Backend;TmaL2", + "LocateWith": "#NA" + }, + { + "MetricName": "L1_Bound", + "LegacyName": "metric_TMA_....L1_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 Data (L1D) cache. The L1D cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1D. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "a" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( max( ( a - b ) / ( c ) , 0 ) )", + "BaseFormula": "max( ( exe_activity.bound_on_loads - memory_activity.stalls_l1d_miss ) / tma_info_thread_clks , 0 )", + "Category": "TMA", + "CountDomain": "Stalls", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 20", + "BaseFormula": "metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueL1, $issueMC" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem", + "LocateWith": "MEM_LOAD_RETIRED.L1_HIT" + }, + { + "MetricName": "DTLB_Load", + "LegacyName": "metric_TMA_......DTLB_Load(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", + "Alias": "a" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "b" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "c" + }, + { + "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( 7 ) * a + b , max( c - d , 0 ) ) / ( e ) )", + "BaseFormula": "min( ( 7 ) * dtlb_load_misses.stlb_hit:c1 + dtlb_load_misses.walk_active , max( cycle_activity.cycles_mem_any - memory_activity.cycles_l1d_miss , 0 ) ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......DTLB_Load(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......DTLB_Load(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueTLB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMT;MemoryTLB", + "LocateWith": "MEM_INST_RETIRED.STLB_MISS_LOADS" + }, + { + "MetricName": "Load_STLB_Hit", + "LegacyName": "metric_TMA_........Load_STLB_Hit(%)", + "ParentCategory": "DTLB_Load", + "Level": 5, + "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", + "Alias": "a" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "b" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "c" + }, + { + "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( ( min( ( 7 ) * a + b , max( c - d , 0 ) ) / ( e ) ) - ( b / ( e ) ) )", + "BaseFormula": "tma_dtlb_load - tma_load_stlb_miss", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Load_STLB_Hit(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......DTLB_Load(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 10 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........Load_STLB_Hit(%) > 5 & metric_TMA_......DTLB_Load(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Load_STLB_Miss", + "LegacyName": "metric_TMA_........Load_STLB_Miss(%)", + "ParentCategory": "DTLB_Load", + "Level": 5, + "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "dtlb_load_misses.walk_active / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Calculated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Load_STLB_Miss(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......DTLB_Load(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 10 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........Load_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Load(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Load_STLB_Miss_4K", + "LegacyName": "metric_TMA_..........Load_STLB_Miss_4K(%)", + "ParentCategory": "Load_STLB_Miss", + "Level": 6, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 4 KB pages for data load accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "Alias": "c" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "d" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b ) ) * c / ( c + d + e ) )", + "BaseFormula": "tma_load_stlb_miss * dtlb_load_misses.walk_completed_4k / ( dtlb_load_misses.walk_completed_4k + dtlb_load_misses.walk_completed_2m_4m + dtlb_load_misses.walk_completed_1g )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Load_STLB_Miss_4K(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_........Load_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_......DTLB_Load(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "f", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 10 & e > 20 & f > 20", + "BaseFormula": "metric_TMA_..........Load_STLB_Miss_4K(%) > 5 & metric_TMA_........Load_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Load(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Load_STLB_Miss_2M", + "LegacyName": "metric_TMA_..........Load_STLB_Miss_2M(%)", + "ParentCategory": "Load_STLB_Miss", + "Level": 6, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 2 or 4 MB pages for data load accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "c" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "Alias": "d" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b ) ) * c / ( d + c + e ) )", + "BaseFormula": "tma_load_stlb_miss * dtlb_load_misses.walk_completed_2m_4m / ( dtlb_load_misses.walk_completed_4k + dtlb_load_misses.walk_completed_2m_4m + dtlb_load_misses.walk_completed_1g )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Load_STLB_Miss_2M(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_........Load_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_......DTLB_Load(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "f", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 10 & e > 20 & f > 20", + "BaseFormula": "metric_TMA_..........Load_STLB_Miss_2M(%) > 5 & metric_TMA_........Load_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Load(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Load_STLB_Miss_1G", + "LegacyName": "metric_TMA_..........Load_STLB_Miss_1G(%)", + "ParentCategory": "Load_STLB_Miss", + "Level": 6, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 1 GB pages for data load accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "Alias": "c" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "Alias": "d" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b ) ) * c / ( d + e + c ) )", + "BaseFormula": "tma_load_stlb_miss * dtlb_load_misses.walk_completed_1g / ( dtlb_load_misses.walk_completed_4k + dtlb_load_misses.walk_completed_2m_4m + dtlb_load_misses.walk_completed_1g )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Load_STLB_Miss_1G(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_........Load_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_......DTLB_Load(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "f", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 10 & e > 20 & f > 20", + "BaseFormula": "metric_TMA_..........Load_STLB_Miss_1G(%) > 5 & metric_TMA_........Load_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Load(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Store_Fwd_Blk", + "LegacyName": "metric_TMA_......Store_Fwd_Blk(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "LD_BLOCKS.STORE_FORWARD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 13 * a / ( b ) )", + "BaseFormula": "13 * ld_blocks.store_forward / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Store_Fwd_Blk(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Store_Fwd_Blk(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "L1_Latency_Dependency", + "LegacyName": "metric_TMA_......L1_Latency_Dependency(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric ([SKL+] roughly; [LNL]) estimates fraction of cycles with demand load accesses that hit the L1D cache. The short latency of the L1D cache may be exposed in pointer-chasing memory access patterns as an example.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "c" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "e" + }, + { + "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + } + ], + "Constants": [ + { + "Name": "20", + "Alias": "dependentloadsweight" + } + ], + "Formula": "100 * ( min( 2 * ( a - b - c ) * dependentloadsweight / 100 , max( e - f , 0 ) ) / ( g ) )", + "BaseFormula": "min( 2 * ( mem_inst_retired.all_loads - mem_load_retired.fb_hit - mem_load_retired.l1_miss ) * 20 / 100 , max( cycle_activity.cycles_mem_any - memory_activity.cycles_l1d_miss , 0 ) ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......L1_Latency_Dependency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......L1_Latency_Dependency(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvML;MemoryLat", + "LocateWith": "MEM_LOAD_RETIRED.L1_HIT" + }, + { + "MetricName": "Lock_Latency", + "LegacyName": "metric_TMA_......Lock_Latency(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a" + }, + { + "Name": "L2_RQSTS.ALL_RFO", + "Alias": "b" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "c" + }, + { + "Name": "L2_RQSTS.RFO_HIT", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( ( 16 * max( 0 , a - b ) + ( a / c ) * ( ( 10 ) * d + ( min( e , f ) ) ) ) / ( e ) )", + "BaseFormula": "( 16 * max( 0 , mem_inst_retired.lock_loads - l2_rqsts.all_rfo ) + ( mem_inst_retired.lock_loads / mem_inst_retired.all_stores ) * ( ( 10 ) * l2_rqsts.rfo_hit + ( min( cpu_clk_unhalted.thread , offcore_requests_outstanding.cycles_with_demand_rfo ) ) ) ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Lock_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Lock_Latency(%) > 20 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueRFO" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "LockCont;Offcore", + "LocateWith": "MEM_INST_RETIRED.LOCK_LOADS" + }, + { + "MetricName": "Split_Loads", + "LegacyName": "metric_TMA_......Split_Loads(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_COMPLETED.L1_MISS_ANY", + "Alias": "b" + }, + { + "Name": "LD_BLOCKS.NO_SR", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / b ) * c / ( d ) )", + "BaseFormula": "tma_info_memory_load_miss_real_latency * ld_blocks.no_sr / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Calculated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Split_Loads(%)" + } + ], + "Formula": "a > 30", + "BaseFormula": "metric_TMA_......Split_Loads(%) > 30", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "MEM_INST_RETIRED.SPLIT_LOADS" + }, + { + "MetricName": "FB_Full", + "LegacyName": "metric_TMA_......FB_Full(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "L1D_PEND_MISS.FB_FULL", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "l1d_pend_miss.fb_full / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Calculated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......FB_Full(%)" + } + ], + "Formula": "a > 30", + "BaseFormula": "metric_TMA_......FB_Full(%) > 30", + "ThresholdIssues": "$issueBW, $issueSL, $issueSmSt" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMB;MemoryBW", + "LocateWith": "" + }, + { + "MetricName": "L2_Bound", + "LegacyName": "metric_TMA_....L2_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Alias": "a" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a - b ) / ( c ) )", + "BaseFormula": "( memory_activity.stalls_l1d_miss - memory_activity.stalls_l2_miss ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Stalls", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....L2_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 20 & c > 20", + "BaseFormula": "metric_TMA_....L2_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvML;CacheHits;MemoryBound;TmaL3mem", + "LocateWith": "MEM_LOAD_RETIRED.L2_HIT" + }, + { + "MetricName": "L2_Hit_Latency", + "LegacyName": "metric_TMA_......L2_Hit_Latency(%)", + "ParentCategory": "L2_Bound", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L2 cache under unloaded scenarios (possibly L2 latency limited). Avoiding L1 cache misses (i.e. L1 misses/L2 hits) will improve the latency.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_RETIRED.L2_HIT", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "f" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "g" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( ( 4.4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) )", + "BaseFormula": "( 4.4 * tma_info_system_core_frequency ) * mem_load_retired.l2_hit * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) / 2 ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......L2_Hit_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L2_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......L2_Hit_Latency(%) > 5 & metric_TMA_....L2_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryLat", + "LocateWith": "MEM_LOAD_RETIRED.L2_HIT" + }, + { + "MetricName": "L3_Bound", + "LegacyName": "metric_TMA_....L3_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Alias": "a" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a - b ) / ( c ) )", + "BaseFormula": "( memory_activity.stalls_l2_miss - memory_activity.stalls_l3_miss ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Stalls", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....L3_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 20 & c > 20", + "BaseFormula": "metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem", + "LocateWith": "MEM_LOAD_RETIRED.L3_HIT" + }, + { + "MetricName": "Contested_Accesses", + "LegacyName": "metric_TMA_......Contested_Accesses(%)", + "ParentCategory": "L3_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Alias": "e" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "f" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "g" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Alias": "h" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "i" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "j" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( ( ( ( 81 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( e * ( f / ( f + g ) ) ) + ( ( 79 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( h ) ) * ( 1 + ( i / j ) / 2 ) / ( a ) )", + "BaseFormula": "( ( ( 81 * tma_info_system_core_frequency ) - ( 4.4 * tma_info_system_core_frequency ) ) * ( mem_load_l3_hit_retired.xsnp_fwd * ( ocr.demand_data_rd.l3_hit.snoop_hitm / ( ocr.demand_data_rd.l3_hit.snoop_hitm + ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd ) ) ) + ( ( 79 * tma_info_system_core_frequency ) - ( 4.4 * tma_info_system_core_frequency ) ) * ( mem_load_l3_hit_retired.xsnp_miss ) ) * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) / 2 ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Contested_Accesses(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L3_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Contested_Accesses(%) > 5 & metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSyncxn" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMS;DataSharing;LockCont;Offcore;Snoop", + "LocateWith": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS" + }, + { + "MetricName": "Data_Sharing", + "LegacyName": "metric_TMA_......Data_Sharing(%)", + "ParentCategory": "L3_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Alias": "f" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "g" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "h" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "i" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "j" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( ( ( 79 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( e + f * ( 1 - ( g / ( g + h ) ) ) ) * ( 1 + ( i / j ) / 2 ) / ( a ) )", + "BaseFormula": "( ( 79 * tma_info_system_core_frequency ) - ( 4.4 * tma_info_system_core_frequency ) ) * ( mem_load_l3_hit_retired.xsnp_no_fwd + mem_load_l3_hit_retired.xsnp_fwd * ( 1 - ( ocr.demand_data_rd.l3_hit.snoop_hitm / ( ocr.demand_data_rd.l3_hit.snoop_hitm + ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd ) ) ) ) * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) / 2 ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Data_Sharing(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L3_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Data_Sharing(%) > 5 & metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSyncxn" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMS;Offcore;Snoop", + "LocateWith": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD" + }, + { + "MetricName": "L3_Hit_Latency", + "LegacyName": "metric_TMA_......L3_Hit_Latency(%)", + "ParentCategory": "L3_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "f" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "g" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( ( ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( e * ( 1 + ( f / g ) / 2 ) ) / ( a ) )", + "BaseFormula": "( ( 37 * tma_info_system_core_frequency ) - ( 4.4 * tma_info_system_core_frequency ) ) * ( mem_load_retired.l3_hit * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) / 2 ) ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......L3_Hit_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L3_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 5 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......L3_Hit_Latency(%) > 10 & metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueLat, ~overlap" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvML;MemoryLat", + "LocateWith": "MEM_LOAD_RETIRED.L3_HIT" + }, + { + "MetricName": "SQ_Full", + "LegacyName": "metric_TMA_......SQ_Full(%)", + "ParentCategory": "L3_Bound", + "Level": 4, + "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "XQ.FULL_CYCLES", + "Alias": "a" + }, + { + "Name": "L1D_PEND_MISS.L2_STALLS", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b ) / ( c ) )", + "BaseFormula": "( xq.full_cycles + l1d_pend_miss.l2_stalls ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......SQ_Full(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L3_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 30 & b > 5 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......SQ_Full(%) > 30 & metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueBW" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMB;MemoryBW;Offcore", + "LocateWith": "" + }, + { + "MetricName": "DRAM_Bound", + "LegacyName": "metric_TMA_....DRAM_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b ) ) )", + "BaseFormula": "( memory_activity.stalls_l3_miss / tma_info_thread_clks )", + "Category": "TMA", + "CountDomain": "Stalls", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 20", + "BaseFormula": "metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBound;TmaL3mem", + "LocateWith": "MEM_LOAD_RETIRED.L3_MISS" + }, + { + "MetricName": "MEM_Bandwidth", + "LegacyName": "metric_TMA_......MEM_Bandwidth(%)", + "ParentCategory": "DRAM_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( ( min( a , b ) ) / ( a ) )", + "BaseFormula": "( min( cpu_clk_unhalted.thread , offcore_requests_outstanding.all_data_rd:c4 ) ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......MEM_Bandwidth(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......MEM_Bandwidth(%) > 20 & metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueBW" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMB;MemoryBW;Offcore", + "LocateWith": "" + }, + { + "MetricName": "MBA_Stalls", + "LegacyName": "metric_TMA_........MBA_Stalls(%)", + "ParentCategory": "MEM_Bandwidth", + "Level": 5, + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to memory bandwidth Allocation feature (RDT's memory bandwidth throttling).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_MISC.MBA_STALLS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "int_misc.mba_stalls / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........MBA_Stalls(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......MEM_Bandwidth(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 10 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........MBA_Stalls(%) > 10 & metric_TMA_......MEM_Bandwidth(%) > 20 & metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBW;Offcore;Server", + "LocateWith": "" + }, + { + "MetricName": "MEM_Latency", + "LegacyName": "metric_TMA_......MEM_Latency(%)", + "ParentCategory": "DRAM_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "b" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( min( a , b ) ) / ( a ) - ( ( min( a , c ) ) / ( a ) ) )", + "BaseFormula": "( min( cpu_clk_unhalted.thread , offcore_requests_outstanding.cycles_with_data_rd ) ) / tma_info_thread_clks - tma_mem_bandwidth", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......MEM_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......MEM_Latency(%) > 10 & metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueLat" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvML;MemoryLat;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Local_MEM", + "LegacyName": "metric_TMA_........Local_MEM(%)", + "ParentCategory": "MEM_Latency", + "Level": 5, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "f" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "g" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( ( ( 109 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) )", + "BaseFormula": "( ( 109 * tma_info_system_core_frequency ) - ( 37 * tma_info_system_core_frequency ) ) * mem_load_l3_miss_retired.local_dram * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) / 2 ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Local_MEM(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......MEM_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 10 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........Local_MEM(%) > 10 & metric_TMA_......MEM_Latency(%) > 10 & metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Server", + "LocateWith": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM" + }, + { + "MetricName": "Remote_MEM", + "LegacyName": "metric_TMA_........Remote_MEM(%)", + "ParentCategory": "MEM_Latency", + "Level": 5, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "f" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "g" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( ( ( 190 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) )", + "BaseFormula": "( ( 190 * tma_info_system_core_frequency ) - ( 37 * tma_info_system_core_frequency ) ) * mem_load_l3_miss_retired.remote_dram * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) / 2 ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Remote_MEM(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......MEM_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 10 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........Remote_MEM(%) > 10 & metric_TMA_......MEM_Latency(%) > 10 & metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Server;Snoop", + "LocateWith": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM" + }, + { + "MetricName": "Remote_Cache", + "LegacyName": "metric_TMA_........Remote_Cache(%)", + "ParentCategory": "MEM_Latency", + "Level": 5, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "Alias": "f" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "g" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "h" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( ( ( ( 170 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * e + ( ( 170 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * f ) * ( 1 + ( g / h ) / 2 ) / ( a ) )", + "BaseFormula": "( ( ( 170 * tma_info_system_core_frequency ) - ( 37 * tma_info_system_core_frequency ) ) * mem_load_l3_miss_retired.remote_hitm + ( ( 170 * tma_info_system_core_frequency ) - ( 37 * tma_info_system_core_frequency ) ) * mem_load_l3_miss_retired.remote_fwd ) * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) / 2 ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Remote_Cache(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......MEM_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 10 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........Remote_Cache(%) > 5 & metric_TMA_......MEM_Latency(%) > 10 & metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSyncxn" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Offcore;Server;Snoop", + "LocateWith": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD" + }, + { + "MetricName": "Store_Bound", + "LegacyName": "metric_TMA_....Store_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "exe_activity.bound_on_stores / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Stalls", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20 & c > 20", + "BaseFormula": "metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBound;TmaL3mem", + "LocateWith": "MEM_INST_RETIRED.ALL_STORES" + }, + { + "MetricName": "Store_Latency", + "LegacyName": "metric_TMA_......Store_Latency(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_STORE_RETIRED.L2_HIT", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "b" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a * ( 10 ) * ( 1 - ( b / c ) ) ) + ( 1 - ( b / c ) ) * ( min( d , e ) ) ) / ( d ) )", + "BaseFormula": "( ( mem_store_retired.l2_hit * ( 10 ) * ( 1 - ( mem_inst_retired.lock_loads / mem_inst_retired.all_stores ) ) ) + ( 1 - ( mem_inst_retired.lock_loads / mem_inst_retired.all_stores ) ) * ( min( cpu_clk_unhalted.thread , offcore_requests_outstanding.cycles_with_demand_rfo ) ) ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Store_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Store_Latency(%) > 10 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueRFO, $issueSL, ~overlap" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvML;LockCont;MemoryLat;Offcore", + "LocateWith": "" + }, + { + "MetricName": "False_Sharing", + "LegacyName": "metric_TMA_......False_Sharing(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "OCR.DEMAND_RFO.L3_MISS:ocr_msr_val=0x103b800002", + "Alias": "e" + }, + { + "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "Alias": "f" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( ( ( 170 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * e + ( 81 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * f ) / ( a ) )", + "BaseFormula": "( ( 170 * tma_info_system_core_frequency ) * ocr.demand_rfo.l3_miss:ocr_msr_val=0x103b800002 + ( 81 * tma_info_system_core_frequency ) * ocr.demand_rfo.l3_hit.snoop_hitm ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......False_Sharing(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 20 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......False_Sharing(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSyncxn" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMS;DataSharing;LockCont;Offcore;Snoop", + "LocateWith": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM" + }, + { + "MetricName": "Split_Stores", + "LegacyName": "metric_TMA_......Split_Stores(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_INST_RETIRED.SPLIT_STORES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( a / ( b if smt_on else ( c ) ) )", + "BaseFormula": "mem_inst_retired.split_stores / tma_info_core_core_clks", + "Category": "TMA", + "CountDomain": "Core_Utilization", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Split_Stores(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Split_Stores(%) > 20 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSpSt" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "MEM_INST_RETIRED.SPLIT_STORES" + }, + { + "MetricName": "Streaming_Stores", + "LegacyName": "metric_TMA_......Streaming_Stores(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "OCR.STREAMING_WR.ANY_RESPONSE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 9 * a / ( b ) )", + "BaseFormula": "9 * ocr.streaming_wr.any_response / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Streaming_Stores(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Streaming_Stores(%) > 20 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSmSt" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBW;Offcore", + "LocateWith": "OCR.STREAMING_WR.ANY_RESPONSE" + }, + { + "MetricName": "DTLB_Store", + "LegacyName": "metric_TMA_......DTLB_Store(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", + "Alias": "a" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( ( 7 ) * a + b ) / ( c if smt_on else ( d ) ) )", + "BaseFormula": "( ( 7 ) * dtlb_store_misses.stlb_hit:c1 + dtlb_store_misses.walk_active ) / tma_info_core_core_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......DTLB_Store(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 20 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......DTLB_Store(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueTLB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMT;MemoryTLB", + "LocateWith": "MEM_INST_RETIRED.STLB_MISS_STORES" + }, + { + "MetricName": "Store_STLB_Hit", + "LegacyName": "metric_TMA_........Store_STLB_Hit(%)", + "ParentCategory": "DTLB_Store", + "Level": 5, + "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", + "Alias": "a" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( ( ( 7 ) * a + b ) / ( c if smt_on else ( d ) ) ) - ( b / ( c if smt_on else ( d ) ) ) )", + "BaseFormula": "tma_dtlb_store - tma_store_stlb_miss", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Store_STLB_Hit(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......DTLB_Store(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 20 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........Store_STLB_Hit(%) > 5 & metric_TMA_......DTLB_Store(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Store_STLB_Miss", + "LegacyName": "metric_TMA_........Store_STLB_Miss(%)", + "ParentCategory": "DTLB_Store", + "Level": 5, + "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( a / ( b if smt_on else ( c ) ) )", + "BaseFormula": "dtlb_store_misses.walk_active / tma_info_core_core_clks", + "Category": "TMA", + "CountDomain": "Clocks_Calculated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Store_STLB_Miss(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......DTLB_Store(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 20 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........Store_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Store(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Store_STLB_Miss_4K", + "LegacyName": "metric_TMA_..........Store_STLB_Miss_4K(%)", + "ParentCategory": "Store_STLB_Miss", + "Level": 6, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 4 KB pages for data store accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "Alias": "d" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "e" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "Alias": "f" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a / ( b if smt_on else ( c ) ) ) * d / ( d + e + f ) )", + "BaseFormula": "tma_store_stlb_miss * dtlb_store_misses.walk_completed_4k / ( dtlb_store_misses.walk_completed_4k + dtlb_store_misses.walk_completed_2m_4m + dtlb_store_misses.walk_completed_1g )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Store_STLB_Miss_4K(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_........Store_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_......DTLB_Store(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "f", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 5 & d > 20 & e > 20 & f > 20", + "BaseFormula": "metric_TMA_..........Store_STLB_Miss_4K(%) > 5 & metric_TMA_........Store_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Store(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Store_STLB_Miss_2M", + "LegacyName": "metric_TMA_..........Store_STLB_Miss_2M(%)", + "ParentCategory": "Store_STLB_Miss", + "Level": 6, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 2 or 4 MB pages for data store accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "d" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "Alias": "e" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "Alias": "f" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a / ( b if smt_on else ( c ) ) ) * d / ( e + d + f ) )", + "BaseFormula": "tma_store_stlb_miss * dtlb_store_misses.walk_completed_2m_4m / ( dtlb_store_misses.walk_completed_4k + dtlb_store_misses.walk_completed_2m_4m + dtlb_store_misses.walk_completed_1g )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Store_STLB_Miss_2M(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_........Store_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_......DTLB_Store(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "f", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 5 & d > 20 & e > 20 & f > 20", + "BaseFormula": "metric_TMA_..........Store_STLB_Miss_2M(%) > 5 & metric_TMA_........Store_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Store(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Store_STLB_Miss_1G", + "LegacyName": "metric_TMA_..........Store_STLB_Miss_1G(%)", + "ParentCategory": "Store_STLB_Miss", + "Level": 6, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 1 GB pages for data store accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "Alias": "d" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "Alias": "e" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "f" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a / ( b if smt_on else ( c ) ) ) * d / ( e + f + d ) )", + "BaseFormula": "tma_store_stlb_miss * dtlb_store_misses.walk_completed_1g / ( dtlb_store_misses.walk_completed_4k + dtlb_store_misses.walk_completed_2m_4m + dtlb_store_misses.walk_completed_1g )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Store_STLB_Miss_1G(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_........Store_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_......DTLB_Store(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "f", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 5 & d > 20 & e > 20 & f > 20", + "BaseFormula": "metric_TMA_..........Store_STLB_Miss_1G(%) > 5 & metric_TMA_........Store_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Store(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Core_Bound", + "LegacyName": "metric_TMA_..Core_Bound(%)", + "ParentCategory": "Backend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) )", + "BaseFormula": "max( 0 , tma_backend_bound - tma_memory_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 20", + "BaseFormula": "metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Backend;TmaL2;Compute", + "LocateWith": "" + }, + { + "MetricName": "Divider", + "LegacyName": "metric_TMA_....Divider(%)", + "ParentCategory": "Core_Bound", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "arith.div_active / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Divider(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 10 & c > 20", + "BaseFormula": "metric_TMA_....Divider(%) > 20 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvCB", + "LocateWith": "ARITH.DIVIDER_ACTIVE" + }, + { + "MetricName": "FP_Divider", + "LegacyName": "metric_TMA_......FP_Divider(%)", + "ParentCategory": "Divider", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles where the Floating-Point Divider unit was active.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ARITH.FPDIV_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "arith.fpdiv_active / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......FP_Divider(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Divider(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......FP_Divider(%) > 20 & metric_TMA_....Divider(%) > 20 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "INT_Divider", + "LegacyName": "metric_TMA_......INT_Divider(%)", + "ParentCategory": "Divider", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles where the Integer Divider unit was active.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "ARITH.FPDIV_ACTIVE", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b ) ) - ( c / ( b ) ) )", + "BaseFormula": "tma_divider - tma_fp_divider", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......INT_Divider(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Divider(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......INT_Divider(%) > 20 & metric_TMA_....Divider(%) > 20 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "Serializing_Operation", + "LegacyName": "metric_TMA_....Serializing_Operation(%)", + "ParentCategory": "Core_Bound", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.C02", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) + ( c / ( b ) ) )", + "BaseFormula": "resource_stalls.scoreboard / tma_info_thread_clks + tma_c02_wait", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Serializing_Operation(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20", + "BaseFormula": "metric_TMA_....Serializing_Operation(%) > 10 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSO" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvIO;PortsUtil", + "LocateWith": "RESOURCE_STALLS.SCOREBOARD" + }, + { + "MetricName": "Slow_Pause", + "LegacyName": "metric_TMA_......Slow_Pause(%)", + "ParentCategory": "Serializing_Operation", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.PAUSE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "cpu_clk_unhalted.pause / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Slow_Pause(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Serializing_Operation(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......Slow_Pause(%) > 5 & metric_TMA_....Serializing_Operation(%) > 10 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "CPU_CLK_UNHALTED.PAUSE_INST" + }, + { + "MetricName": "C01_Wait", + "LegacyName": "metric_TMA_......C01_Wait(%)", + "ParentCategory": "Serializing_Operation", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due staying in C0.1 power-performance optimized state (Faster wakeup time; Smaller power savings).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.C01", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "cpu_clk_unhalted.c01 / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......C01_Wait(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Serializing_Operation(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......C01_Wait(%) > 5 & metric_TMA_....Serializing_Operation(%) > 10 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "C0Wait", + "LocateWith": "" + }, + { + "MetricName": "C02_Wait", + "LegacyName": "metric_TMA_......C02_Wait(%)", + "ParentCategory": "Serializing_Operation", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due staying in C0.2 power-performance optimized state (Slower wakeup time; Larger power savings).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.C02", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "cpu_clk_unhalted.c02 / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......C02_Wait(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Serializing_Operation(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......C02_Wait(%) > 5 & metric_TMA_....Serializing_Operation(%) > 10 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "C0Wait", + "LocateWith": "" + }, + { + "MetricName": "Memory_Fence", + "LegacyName": "metric_TMA_......Memory_Fence(%)", + "ParentCategory": "Serializing_Operation", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to LFENCE Instructions.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MISC2_RETIRED.LFENCE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 13 * a / ( b ) )", + "BaseFormula": "13 * misc2_retired.lfence / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Memory_Fence(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Serializing_Operation(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......Memory_Fence(%) > 5 & metric_TMA_....Serializing_Operation(%) > 10 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "AMX_Busy", + "LegacyName": "metric_TMA_....AMX_Busy(%)", + "ParentCategory": "Core_Bound", + "Level": 3, + "BriefDescription": "This metric estimates fraction of cycles where the Advanced Matrix eXtensions (AMX) execution engine was busy with tile (arithmetic) operations", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE.AMX_BUSY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( a / ( b if smt_on else ( c ) ) )", + "BaseFormula": "exe.amx_busy / tma_info_core_core_clks", + "Category": "TMA", + "CountDomain": "Core_Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....AMX_Busy(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 50 & b > 10 & c > 20", + "BaseFormula": "metric_TMA_....AMX_Busy(%) > 50 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvCB;Compute;HPC;Server", + "LocateWith": "" + }, + { + "MetricName": "Ports_Utilization", + "LegacyName": "metric_TMA_....Ports_Utilization(%)", + "ParentCategory": "Core_Bound", + "Level": 3, + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "Alias": "a" + }, + { + "Name": "RS.EMPTY_RESOURCE", + "Alias": "b" + }, + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "e" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "f" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "g" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "h" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "i" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "j" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "k" + }, + { + "Name": "EXE_ACTIVITY.2_3_PORTS_UTIL", + "Alias": "l" + }, + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "m" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( ( a + max( b - c , 0 ) ) / ( d ) * ( e - f ) / ( d ) ) * ( d ) + ( g + ( h / ( i + j + h + k ) ) * l ) ) / ( d ) if ( m < ( e - f ) ) else ( g + ( h / ( i + j + h + k ) ) * l ) / ( d ) )", + "BaseFormula": "( tma_ports_utilized_0 * tma_info_thread_clks + ( exe_activity.1_ports_util + tma_retiring * exe_activity.2_3_ports_util ) ) / tma_info_thread_clks if ( arith.div_active < ( cycle_activity.stalls_total - exe_activity.bound_on_loads ) ) else ( exe_activity.1_ports_util + tma_retiring * exe_activity.2_3_ports_util ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Ports_Utilization(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 15 & b > 10 & c > 20", + "BaseFormula": "metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil", + "LocateWith": "" + }, + { + "MetricName": "Ports_Utilized_0", + "LegacyName": "metric_TMA_......Ports_Utilized_0(%)", + "ParentCategory": "Ports_Utilization", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "Alias": "a" + }, + { + "Name": "RS.EMPTY_RESOURCE", + "Alias": "b" + }, + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "e" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + max( b - c , 0 ) ) / ( d ) * ( e - f ) / ( d ) )", + "BaseFormula": "( exe_activity.exe_bound_0_ports + max( rs.empty_resource - resource_stalls.scoreboard , 0 ) ) / tma_info_thread_clks * ( cycle_activity.stalls_total - exe_activity.bound_on_loads ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Ports_Utilized_0(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Ports_Utilization(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 15 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......Ports_Utilized_0(%) > 20 & metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil", + "LocateWith": "" + }, + { + "MetricName": "Mixing_Vectors", + "LegacyName": "metric_TMA_........Mixing_Vectors(%)", + "ParentCategory": "Ports_Utilized_0", + "Level": 5, + "BriefDescription": "This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued , the Count Domain; [ADL+] cycles). Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ASSISTS.SSE_AVX_MIX", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 160 * a / ( b ) )", + "BaseFormula": "160 * assists.sse_avx_mix / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Mixing_Vectors(%)" + } + ], + "Formula": "a > 5", + "BaseFormula": "metric_TMA_........Mixing_Vectors(%) > 5", + "ThresholdIssues": "$issueMV" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "Ports_Utilized_1", + "LegacyName": "metric_TMA_......Ports_Utilized_1(%)", + "ParentCategory": "Ports_Utilization", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "exe_activity.1_ports_util / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Ports_Utilized_1(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Ports_Utilization(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 15 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......Ports_Utilized_1(%) > 20 & metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueL1" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil", + "LocateWith": "EXE_ACTIVITY.1_PORTS_UTIL" + }, + { + "MetricName": "Ports_Utilized_2", + "LegacyName": "metric_TMA_......Ports_Utilized_2(%)", + "ParentCategory": "Ports_Utilization", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "exe_activity.2_ports_util / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Ports_Utilized_2(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Ports_Utilization(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 15 & b > 15 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......Ports_Utilized_2(%) > 15 & metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil", + "LocateWith": "EXE_ACTIVITY.2_PORTS_UTIL" + }, + { + "MetricName": "Ports_Utilized_3m", + "LegacyName": "metric_TMA_......Ports_Utilized_3m(%)", + "ParentCategory": "Ports_Utilization", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_EXECUTED.CYCLES_GE_3", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "uops_executed.cycles_ge_3 / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Ports_Utilized_3m(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Ports_Utilization(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 40 & b > 15 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......Ports_Utilized_3m(%) > 40 & metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvCB;PortsUtil", + "LocateWith": "UOPS_EXECUTED.CYCLES_GE_3" + }, + { + "MetricName": "ALU_Op_Utilization", + "LegacyName": "metric_TMA_........ALU_Op_Utilization(%)", + "ParentCategory": "Ports_Utilized_3m", + "Level": 5, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_0", + "Alias": "a" + }, + { + "Name": "UOPS_DISPATCHED.PORT_1", + "Alias": "b" + }, + { + "Name": "UOPS_DISPATCHED.PORT_5_11", + "Alias": "c" + }, + { + "Name": "UOPS_DISPATCHED.PORT_6", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "e" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "f" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a + b + c + d ) / ( 5 * ( e if smt_on else ( f ) ) ) )", + "BaseFormula": "( uops_dispatched.port_0 + uops_dispatched.port_1 + uops_dispatched.port_5_11 + uops_dispatched.port_6 ) / ( 5 * tma_info_core_core_clks )", + "Category": "TMA", + "CountDomain": "Core_Execution", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........ALU_Op_Utilization(%)" + } + ], + "Formula": "a > 40", + "BaseFormula": "metric_TMA_........ALU_Op_Utilization(%) > 40", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "Port_0", + "LegacyName": "metric_TMA_..........Port_0(%)", + "ParentCategory": "ALU_Op_Utilization", + "Level": 6, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_0", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( a / ( b if smt_on else ( c ) ) )", + "BaseFormula": "uops_dispatched.port_0 / tma_info_core_core_clks", + "Category": "TMA", + "CountDomain": "Core_Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Port_0(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..........Port_0(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute", + "LocateWith": "UOPS_DISPATCHED.PORT_0" + }, + { + "MetricName": "Port_1", + "LegacyName": "metric_TMA_..........Port_1(%)", + "ParentCategory": "ALU_Op_Utilization", + "Level": 6, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_1", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( a / ( b if smt_on else ( c ) ) )", + "BaseFormula": "uops_dispatched.port_1 / tma_info_core_core_clks", + "Category": "TMA", + "CountDomain": "Core_Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Port_1(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..........Port_1(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "UOPS_DISPATCHED.PORT_1" + }, + { + "MetricName": "Port_6", + "LegacyName": "metric_TMA_..........Port_6(%)", + "ParentCategory": "ALU_Op_Utilization", + "Level": 6, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_6", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( a / ( b if smt_on else ( c ) ) )", + "BaseFormula": "uops_dispatched.port_6 / tma_info_core_core_clks", + "Category": "TMA", + "CountDomain": "Core_Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Port_6(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..........Port_6(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "UOPS_DISPATCHED.PORT_1" + }, + { + "MetricName": "Load_Op_Utilization", + "LegacyName": "metric_TMA_........Load_Op_Utilization(%)", + "ParentCategory": "Ports_Utilized_3m", + "Level": 5, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_2_3_10", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( a / ( 3 * ( b if smt_on else ( c ) ) ) )", + "BaseFormula": "uops_dispatched.port_2_3_10 / ( 3 * tma_info_core_core_clks )", + "Category": "TMA", + "CountDomain": "Core_Execution", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Load_Op_Utilization(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_........Load_Op_Utilization(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "UOPS_DISPATCHED.PORT_2_3_10" + }, + { + "MetricName": "Store_Op_Utilization", + "LegacyName": "metric_TMA_........Store_Op_Utilization(%)", + "ParentCategory": "Ports_Utilized_3m", + "Level": 5, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_4_9", + "Alias": "a" + }, + { + "Name": "UOPS_DISPATCHED.PORT_7_8", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a + b ) / ( 4 * ( c if smt_on else ( d ) ) ) )", + "BaseFormula": "( uops_dispatched.port_4_9 + uops_dispatched.port_7_8 ) / ( 4 * tma_info_core_core_clks )", + "Category": "TMA", + "CountDomain": "Core_Execution", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Store_Op_Utilization(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_........Store_Op_Utilization(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "UOPS_DISPATCHED.PORT_7_8" + }, + { + "MetricName": "Retiring", + "LegacyName": "metric_TMA_Retiring(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b + c + a + d ) )", + "BaseFormula": "perf_metrics.retiring / ( perf_metrics.frontend_bound + perf_metrics.bad_speculation + perf_metrics.retiring + perf_metrics.backend_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Retiring(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 70 | b > 10", + "BaseFormula": "metric_TMA_Retiring(%) > 70 | metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvUW;TmaL1", + "LocateWith": "UOPS_RETIRED.SLOTS" + }, + { + "MetricName": "Light_Operations", + "LegacyName": "metric_TMA_..Light_Operations(%)", + "ParentCategory": "Retiring", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations , instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) )", + "BaseFormula": "max( 0 , tma_retiring - tma_heavy_operations )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Retire;TmaL2", + "LocateWith": "INST_RETIRED.PREC_DIST" + }, + { + "MetricName": "FP_Arith", + "LegacyName": "metric_TMA_....FP_Arith(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "UOPS_EXECUTED.X87", + "Alias": "e" + }, + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "f" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "g" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR", + "Alias": "h" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "i" + }, + { + "Name": "FP_ARITH_INST_RETIRED.VECTOR", + "Alias": "j" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.VECTOR", + "Alias": "k" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a / ( b + c + a + d ) ) * e / f ) + ( ( g + h ) / ( ( a / ( b + c + a + d ) ) * ( i ) ) ) + ( ( j + k ) / ( ( a / ( b + c + a + d ) ) * ( i ) ) ) )", + "BaseFormula": "tma_x87_use + tma_fp_scalar + tma_fp_vector", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....FP_Arith(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 20 & b > 60", + "BaseFormula": "metric_TMA_....FP_Arith(%) > 20 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC", + "LocateWith": "" + }, + { + "MetricName": "X87_Use", + "LegacyName": "metric_TMA_......X87_Use(%)", + "ParentCategory": "FP_Arith", + "Level": 4, + "BriefDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "UOPS_EXECUTED.X87", + "Alias": "e" + }, + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b + c + a + d ) ) * e / f )", + "BaseFormula": "tma_retiring * uops_executed.x87 / uops_executed.thread", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......X87_Use(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....FP_Arith(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 60", + "BaseFormula": "metric_TMA_......X87_Use(%) > 10 & metric_TMA_....FP_Arith(%) > 20 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute", + "LocateWith": "" + }, + { + "MetricName": "FP_Scalar", + "LegacyName": "metric_TMA_......FP_Scalar(%)", + "ParentCategory": "FP_Arith", + "Level": 4, + "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) )", + "BaseFormula": "( fp_arith_inst_retired.scalar + fp_arith_inst_retired2.scalar ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......FP_Scalar(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....FP_Arith(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 60", + "BaseFormula": "metric_TMA_......FP_Scalar(%) > 10 & metric_TMA_....FP_Arith(%) > 20 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops", + "LocateWith": "" + }, + { + "MetricName": "FP_Vector", + "LegacyName": "metric_TMA_......FP_Vector(%)", + "ParentCategory": "FP_Arith", + "Level": 4, + "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.VECTOR", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.VECTOR", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) )", + "BaseFormula": "( fp_arith_inst_retired.vector + fp_arith_inst_retired2.vector ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......FP_Vector(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....FP_Arith(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 60", + "BaseFormula": "metric_TMA_......FP_Vector(%) > 10 & metric_TMA_....FP_Arith(%) > 20 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops", + "LocateWith": "" + }, + { + "MetricName": "FP_Vector_128b", + "LegacyName": "metric_TMA_........FP_Vector_128b(%)", + "ParentCategory": "FP_Vector", + "Level": 5, + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting prior to LNL.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b + c ) / ( ( d / ( e + f + d + g ) ) * ( h ) ) )", + "BaseFormula": "( fp_arith_inst_retired.128b_packed_double + fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired2.128b_packed_half ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........FP_Vector_128b(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......FP_Vector(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....FP_Arith(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 60", + "BaseFormula": "metric_TMA_........FP_Vector_128b(%) > 10 & metric_TMA_......FP_Vector(%) > 10 & metric_TMA_....FP_Arith(%) > 20 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops", + "LocateWith": "" + }, + { + "MetricName": "FP_Vector_256b", + "LegacyName": "metric_TMA_........FP_Vector_256b(%)", + "ParentCategory": "FP_Vector", + "Level": 5, + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting prior to LNL.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b + c ) / ( ( d / ( e + f + d + g ) ) * ( h ) ) )", + "BaseFormula": "( fp_arith_inst_retired.256b_packed_double + fp_arith_inst_retired.256b_packed_single + fp_arith_inst_retired2.256b_packed_half ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........FP_Vector_256b(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......FP_Vector(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....FP_Arith(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 60", + "BaseFormula": "metric_TMA_........FP_Vector_256b(%) > 10 & metric_TMA_......FP_Vector(%) > 10 & metric_TMA_....FP_Arith(%) > 20 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops", + "LocateWith": "" + }, + { + "MetricName": "FP_Vector_512b", + "LegacyName": "metric_TMA_........FP_Vector_512b(%)", + "ParentCategory": "FP_Vector", + "Level": 5, + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b + c ) / ( ( d / ( e + f + d + g ) ) * ( h ) ) )", + "BaseFormula": "( fp_arith_inst_retired.512b_packed_double + fp_arith_inst_retired.512b_packed_single + fp_arith_inst_retired2.512b_packed_half ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........FP_Vector_512b(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......FP_Vector(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....FP_Arith(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 60", + "BaseFormula": "metric_TMA_........FP_Vector_512b(%) > 10 & metric_TMA_......FP_Vector(%) > 10 & metric_TMA_....FP_Arith(%) > 20 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops", + "LocateWith": "" + }, + { + "MetricName": "Int_Operations", + "LegacyName": "metric_TMA_....Int_Operations(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired). Vector/Matrix Int operations and shuffles are counted. Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_VEC_RETIRED.ADD_128", + "Alias": "a" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_128", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "INT_VEC_RETIRED.ADD_256", + "Alias": "h" + }, + { + "Name": "INT_VEC_RETIRED.MUL_256", + "Alias": "i" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_256", + "Alias": "j" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) ) + ( ( h + i + j ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) ) )", + "BaseFormula": "tma_int_vector_128b + tma_int_vector_256b", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Int_Operations(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 60", + "BaseFormula": "metric_TMA_....Int_Operations(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Int_Vector_128b", + "LegacyName": "metric_TMA_......Int_Vector_128b(%)", + "ParentCategory": "Int_Operations", + "Level": 4, + "BriefDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_VEC_RETIRED.ADD_128", + "Alias": "a" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_128", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) )", + "BaseFormula": "( int_vec_retired.add_128 + int_vec_retired.vnni_128 ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Int_Vector_128b(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Int_Operations(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 60", + "BaseFormula": "metric_TMA_......Int_Vector_128b(%) > 10 & metric_TMA_....Int_Operations(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;IntVector;Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Int_Vector_256b", + "LegacyName": "metric_TMA_......Int_Vector_256b(%)", + "ParentCategory": "Int_Operations", + "Level": 4, + "BriefDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_VEC_RETIRED.ADD_256", + "Alias": "a" + }, + { + "Name": "INT_VEC_RETIRED.MUL_256", + "Alias": "b" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_256", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b + c ) / ( ( d / ( e + f + d + g ) ) * ( h ) ) )", + "BaseFormula": "( int_vec_retired.add_256 + int_vec_retired.mul_256 + int_vec_retired.vnni_256 ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Int_Vector_256b(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Int_Operations(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 60", + "BaseFormula": "metric_TMA_......Int_Vector_256b(%) > 10 & metric_TMA_....Int_Operations(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;IntVector;Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Memory_Operations", + "LegacyName": "metric_TMA_....Memory_Operations(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations , uops for memory load or store accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "MEM_UOP_RETIRED.ANY", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * f / ( ( a / ( b + c + a + d ) ) * ( g ) ) )", + "BaseFormula": "tma_light_operations * mem_uop_retired.any / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Memory_Operations(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 60", + "BaseFormula": "metric_TMA_....Memory_Operations(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Fused_Instructions", + "LegacyName": "metric_TMA_....Fused_Instructions(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions , where one uop can represent multiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Other_Light_Ops in MTL!)}", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "INST_RETIRED.MACRO_FUSED", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * f / ( ( a / ( b + c + a + d ) ) * ( g ) ) )", + "BaseFormula": "tma_light_operations * inst_retired.macro_fused / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Fused_Instructions(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 60", + "BaseFormula": "metric_TMA_....Fused_Instructions(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;BvBO;Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Non_Fused_Branches", + "LegacyName": "metric_TMA_....Non_Fused_Branches(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "f" + }, + { + "Name": "INST_RETIRED.MACRO_FUSED", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * ( f - g ) / ( ( a / ( b + c + a + d ) ) * ( h ) ) )", + "BaseFormula": "tma_light_operations * ( br_inst_retired.all_branches - inst_retired.macro_fused ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Non_Fused_Branches(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 60", + "BaseFormula": "metric_TMA_....Non_Fused_Branches(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;BvBO;Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Other_Light_Ops", + "LegacyName": "metric_TMA_....Other_Light_Ops(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "UOPS_EXECUTED.X87", + "Alias": "f" + }, + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "g" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "h" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR", + "Alias": "i" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "j" + }, + { + "Name": "FP_ARITH_INST_RETIRED.VECTOR", + "Alias": "k" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.VECTOR", + "Alias": "l" + }, + { + "Name": "INT_VEC_RETIRED.ADD_128", + "Alias": "m" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_128", + "Alias": "n" + }, + { + "Name": "INT_VEC_RETIRED.ADD_256", + "Alias": "o" + }, + { + "Name": "INT_VEC_RETIRED.MUL_256", + "Alias": "p" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_256", + "Alias": "q" + }, + { + "Name": "MEM_UOP_RETIRED.ANY", + "Alias": "r" + }, + { + "Name": "INST_RETIRED.MACRO_FUSED", + "Alias": "s" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "t" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) - ( ( ( ( a / ( b + c + a + d ) ) * f / g ) + ( ( h + i ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( ( k + l ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) ) + ( ( ( m + n ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( ( o + p + q ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * r / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * s / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * ( t - s ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) ) ) )", + "BaseFormula": "max( 0 , tma_light_operations - ( tma_fp_arith + tma_int_operations + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Other_Light_Ops(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 30 & b > 60", + "BaseFormula": "metric_TMA_....Other_Light_Ops(%) > 30 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Nop_Instructions", + "LegacyName": "metric_TMA_......Nop_Instructions(%)", + "ParentCategory": "Other_Light_Ops", + "Level": 4, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "INST_RETIRED.NOP", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * f / ( ( a / ( b + c + a + d ) ) * ( g ) ) )", + "BaseFormula": "tma_light_operations * inst_retired.nop / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Nop_Instructions(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Other_Light_Ops(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 30 & c > 60", + "BaseFormula": "metric_TMA_......Nop_Instructions(%) > 10 & metric_TMA_....Other_Light_Ops(%) > 30 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvBO;Pipeline", + "LocateWith": "INST_RETIRED.NOP" + }, + { + "MetricName": "Shuffles_256b", + "LegacyName": "metric_TMA_......Shuffles_256b(%)", + "ParentCategory": "Other_Light_Ops", + "Level": 4, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP or Integer). Shuffles may incur slow cross \"vector lane\" data transfers.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "INT_VEC_RETIRED.SHUFFLES", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * f / ( ( a / ( b + c + a + d ) ) * ( g ) ) )", + "BaseFormula": "tma_light_operations * int_vec_retired.shuffles / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Shuffles_256b(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Other_Light_Ops(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 30 & c > 60", + "BaseFormula": "metric_TMA_......Shuffles_256b(%) > 10 & metric_TMA_....Other_Light_Ops(%) > 30 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Heavy_Operations", + "LegacyName": "metric_TMA_..Heavy_Operations(%)", + "ParentCategory": "Retiring", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations , instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.([ICL+] Note this may overcount due to approximation using indirect events; [ADL+])", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b + c + d + e ) )", + "BaseFormula": "perf_metrics.heavy_operations / ( perf_metrics.frontend_bound + perf_metrics.bad_speculation + perf_metrics.retiring + perf_metrics.backend_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Retire;TmaL2", + "LocateWith": "UOPS_RETIRED.HEAVY" + }, + { + "MetricName": "Few_Uops_Instructions", + "LegacyName": "metric_TMA_....Few_Uops_Instructions(%)", + "ParentCategory": "Heavy_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or more uops. This highly-correlates with the number of uops in such instructions.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "UOPS_RETIRED.MS", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b + c + d + e ) ) - ( f / ( g ) ) ) )", + "BaseFormula": "max( 0 , tma_heavy_operations - tma_microcode_sequencer )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Few_Uops_Instructions(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 5 & b > 10", + "BaseFormula": "metric_TMA_....Few_Uops_Instructions(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "$issueD0" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "Microcode_Sequencer", + "LegacyName": "metric_TMA_....Microcode_Sequencer(%)", + "ParentCategory": "Heavy_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.MS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "uops_retired.ms / tma_info_thread_slots", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Microcode_Sequencer(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 5 & b > 10", + "BaseFormula": "metric_TMA_....Microcode_Sequencer(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "$issueMC, $issueMS" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq", + "LocateWith": "UOPS_RETIRED.MS" + }, + { + "MetricName": "Assists", + "LegacyName": "metric_TMA_......Assists(%)", + "ParentCategory": "Microcode_Sequencer", + "Level": 4, + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ASSISTS.ANY", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * a / ( b ) )", + "BaseFormula": "( ( 99 *3 + 63 + 30 ) / 5 ) * assists.any / tma_info_thread_slots", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Assists(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Microcode_Sequencer(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 10 & b > 5 & c > 10", + "BaseFormula": "metric_TMA_......Assists(%) > 10 & metric_TMA_....Microcode_Sequencer(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvIO", + "LocateWith": "ASSISTS.ANY" + }, + { + "MetricName": "Page_Faults", + "LegacyName": "metric_TMA_........Page_Faults(%)", + "ParentCategory": "Assists", + "Level": 5, + "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults. A Page Fault may apply on first application access to a memory page. Note operating system handling of page faults accounts for the majority of its cost.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ASSISTS.PAGE_FAULT", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 99 * a / ( b ) )", + "BaseFormula": "99 * assists.page_fault / tma_info_thread_slots", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Page_Faults(%)" + } + ], + "Formula": "a > 5", + "BaseFormula": "metric_TMA_........Page_Faults(%) > 5", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "FP_Assists", + "LegacyName": "metric_TMA_........FP_Assists(%)", + "ParentCategory": "Assists", + "Level": 5, + "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ASSISTS.FP", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 30 * a / ( b ) )", + "BaseFormula": "30 * assists.fp / tma_info_thread_slots", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........FP_Assists(%)" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_........FP_Assists(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC", + "LocateWith": "" + }, + { + "MetricName": "AVX_Assists", + "LegacyName": "metric_TMA_........AVX_Assists(%)", + "ParentCategory": "Assists", + "Level": 5, + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ASSISTS.SSE_AVX_MIX", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 63 * a / ( b ) )", + "BaseFormula": "63 * assists.sse_avx_mix / tma_info_thread_slots", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........AVX_Assists(%)" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_........AVX_Assists(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC", + "LocateWith": "" + }, + { + "MetricName": "CISC", + "LegacyName": "metric_TMA_......CISC(%)", + "ParentCategory": "Microcode_Sequencer", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.MS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b ) ) - ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c / ( b ) ) ) )", + "BaseFormula": "max( 0 , tma_microcode_sequencer - tma_assists )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......CISC(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Microcode_Sequencer(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 10 & b > 5 & c > 10", + "BaseFormula": "metric_TMA_......CISC(%) > 10 & metric_TMA_....Microcode_Sequencer(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "FRONTEND_RETIRED.MS_FLOWS" + }, + { + "MetricName": "Info_Botlnk_L0_Core_Bound_Likely", + "LegacyName": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely", + "Level": 1, + "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "e" + }, + { + "Name": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "Alias": "f" + }, + { + "Name": "RS.EMPTY_RESOURCE", + "Alias": "g" + }, + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "k" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "l" + }, + { + "Name": "EXE_ACTIVITY.2_3_PORTS_UTIL", + "Alias": "m" + }, + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "n" + }, + { + "Name": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "Alias": "o" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "Alias": "p" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( 1 - ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) / ( ( ( ( f + max( g - h , 0 ) ) / ( i ) * ( j - k ) / ( i ) ) * ( i ) + ( l + ( d / ( b + c + d + a ) ) * m ) ) / ( i ) if ( n < ( j - k ) ) else ( l + ( d / ( b + c + d + a ) ) * m ) / ( i ) ) if ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) < ( ( ( ( f + max( g - h , 0 ) ) / ( i ) * ( j - k ) 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+ } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "br_inst_retired.all_branches / br_inst_retired.near_taken", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;PGO", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpFLOP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpFLOP", + "Level": 1, + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", + "Alias": "e" + }, + { + "Name": "FP_ARITH_INST_RETIRED.4_FLOPS", + "Alias": "f" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", + "Alias": "g" + }, + { + "Name": "FP_ARITH_INST_RETIRED.8_FLOPS", + "Alias": "h" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", + "Alias": "i" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "j" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", + "Alias": "k" + } + ], + "Constants": [], + "Formula": "a / ( ( 1 * ( b + c ) + 2 * ( d + e ) + 4 * f + 8 * ( g + h ) + 16 * ( i + j ) + 32 * k ) )", + "BaseFormula": "inst_retired.any / ( ( 1 * ( fp_arith_inst_retired.scalar + fp_arith_inst_retired2.scalar_half ) + 2 * ( fp_arith_inst_retired.128b_packed_double + fp_arith_inst_retired2.complex_scalar_half ) + 4 * fp_arith_inst_retired.4_flops + 8 * ( fp_arith_inst_retired2.128b_packed_half + fp_arith_inst_retired.8_flops ) + 16 * ( fp_arith_inst_retired2.256b_packed_half + fp_arith_inst_retired.512b_packed_single ) + 32 * fp_arith_inst_retired2.512b_packed_half ) )", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpFLOP" + } + ], + "Formula": "a < 10", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpFLOP < 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpArith", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.VECTOR", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.VECTOR", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "a / ( ( b + c ) + ( d + e ) )", + "BaseFormula": "inst_retired.any / ( ( fp_arith_inst_retired.scalar + fp_arith_inst_retired2.scalar ) + ( fp_arith_inst_retired.vector + fp_arith_inst_retired2.vector ) )", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpArith" + } + ], + "Formula": "a < 10", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpArith < 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_Scalar_HP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_HP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Half-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / fp_arith_inst_retired2.scalar", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_HP" + } + ], + "Formula": "a < 10", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_HP < 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpScalar;InsType;Server", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_Scalar_SP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_SP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / fp_arith_inst_retired.scalar_single", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_SP" + } + ], + "Formula": "a < 10", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_SP < 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpScalar;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_Scalar_DP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_DP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / fp_arith_inst_retired.scalar_double", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_DP" + } + ], + "Formula": "a < 10", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_DP < 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpScalar;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX128", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX128", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "a / ( b + c + d )", + "BaseFormula": "inst_retired.any / ( fp_arith_inst_retired.128b_packed_double + fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired2.128b_packed_half )", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpArith_AVX128" + } + ], + "Formula": "a < 10", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpArith_AVX128 < 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX256", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX256", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "a / ( b + c + d )", + "BaseFormula": "inst_retired.any / ( fp_arith_inst_retired.256b_packed_double + fp_arith_inst_retired.256b_packed_single + fp_arith_inst_retired2.256b_packed_half )", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpArith_AVX256" + } + ], + "Formula": "a < 10", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpArith_AVX256 < 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX512", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX512", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "a / ( b + c + d )", + "BaseFormula": "inst_retired.any / ( fp_arith_inst_retired.512b_packed_double + fp_arith_inst_retired.512b_packed_single + fp_arith_inst_retired2.512b_packed_half )", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpArith_AVX512" + } + ], + "Formula": "a < 10", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpArith_AVX512 < 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpPause", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpPause", + "Level": 1, + "BriefDescription": "Instructions per PAUSE (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.PAUSE_INST", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "BaseFormula": "tma_info_inst_mix_instructions / cpu_clk_unhalted.pause_inst", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpSWPF", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpSWPF", + "Level": 1, + "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "SW_PREFETCH_ACCESS.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / sw_prefetch_access.any", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpSWPF" + } + ], + "Formula": "a < 100", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpSWPF < 100", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Prefetches", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_Instructions", + "LegacyName": "metric_TMA_Info_Inst_Mix_Instructions", + "Level": 1, + "BriefDescription": "Total number of retired Instructions", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "BaseFormula": "inst_retired.any", + "Category": "TMA", + "CountDomain": "Count", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary;TmaL1", + "LocateWith": "INST_RETIRED.PREC_DIST" + }, + { + "MetricName": "Info_Pipeline_Retire", + "LegacyName": "metric_TMA_Info_Pipeline_Retire", + "Level": 1, + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "e" + }, + { + "Name": "UOPS_RETIRED.SLOTS:c1", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "( ( a / ( b + c + a + d ) ) * ( e ) ) / f", + "BaseFormula": "( tma_retiring * tma_info_thread_slots ) / uops_retired.slots:c1", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline;Ret", + "LocateWith": "" + }, + { + "MetricName": "Info_Pipeline_Strings_Cycles", + "LegacyName": "metric_TMA_Info_Pipeline_Strings_Cycles", + "Level": 1, + "BriefDescription": "Estimated fraction of retirement-cycles dealing with repeat instructions", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.REP_ITERATION", + "Alias": "a" + }, + { + "Name": "UOPS_RETIRED.SLOTS:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.rep_iteration / uops_retired.slots:c1", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Pipeline_Strings_Cycles" + } + ], + "Formula": "a > 0.1", + "BaseFormula": "metric_TMA_Info_Pipeline_Strings_Cycles > 0.1", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq;Pipeline;Ret", + "LocateWith": "" + }, + { + "MetricName": "Info_Pipeline_IpAssist", + "LegacyName": "metric_TMA_Info_Pipeline_IpAssist", + "Level": 1, + "BriefDescription": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / assists.any", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Pipeline_IpAssist" + } + ], + "Formula": "a < 100000", + "BaseFormula": "metric_TMA_Info_Pipeline_IpAssist < 100000", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq;Pipeline;Ret;Retire", + "LocateWith": "" + }, + { + "MetricName": "Info_Pipeline_Execute", + "LegacyName": "metric_TMA_Info_Pipeline_Execute", + "Level": 1, + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per physical core", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "Alias": "b" + }, + { + "Name": "UOPS_EXECUTED.THREAD:c1", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "a / ( ( b / 2 ) if smt_on else c )", + "BaseFormula": "uops_executed.thread / ( ( uops_executed.core_cycles_ge_1 / 2 ) if smt_on else uops_executed.thread:c1 )", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "LocateWith": "" + }, + { + "MetricName": "Info_Pipeline_Fetch_DSB", + "LegacyName": "metric_TMA_Info_Pipeline_Fetch_DSB", + "Level": 1, + "BriefDescription": "Average number of uops fetched from DSB per cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.DSB_CYCLES_ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "idq.dsb_uops / idq.dsb_cycles_any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Pipeline_Fetch_MITE", + "LegacyName": "metric_TMA_Info_Pipeline_Fetch_MITE", + "Level": 1, + "BriefDescription": "Average number of uops fetched from MITE per cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ.MITE_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_CYCLES_ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "idq.mite_uops / idq.mite_cycles_any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_Fetch_UpC", + "LegacyName": "metric_TMA_Info_Frontend_Fetch_UpC", + "Level": 1, + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "uops_issued.any / uops_issued.any:c1", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_DSB_Coverage", + "LegacyName": "metric_TMA_Info_Frontend_DSB_Coverage", + "Level": 1, + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "BaseFormula": "idq.dsb_uops / ( uops_issued.any )", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Frontend_DSB_Coverage" + }, + { + "Alias": "b", + "Value": "metric_TMA_Info_Thread_IPC" + } + ], + "Formula": "a < 0.7 & b / 6 > 0.35", + "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & metric_TMA_Info_Thread_IPC / 6 > 0.35", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSB;Fed;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_Unknown_Branch_Cost", + "LegacyName": "metric_TMA_Info_Frontend_Unknown_Branch_Cost", + "Level": 1, + "BriefDescription": "Average number of cycles the front-end was delayed due to an Unknown Branch detection. See Unknown_Branches node.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "a" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES:c1:e1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "int_misc.unknown_branch_cycles / int_misc.unknown_branch_cycles:c1:e1", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_DSB_Switch_Cost", + "LegacyName": "metric_TMA_Info_Frontend_DSB_Switch_Cost", + "Level": 1, + "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "a" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES:c1:e1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "dsb2mite_switches.penalty_cycles / dsb2mite_switches.penalty_cycles:c1:e1", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_TBpC", + "LegacyName": "metric_TMA_Info_Frontend_TBpC", + "Level": 1, + "BriefDescription": "Taken Branches retired Per Cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "BaseFormula": "br_inst_retired.near_taken / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_ICache_Miss_Latency", + "LegacyName": "metric_TMA_Info_Frontend_ICache_Miss_Latency", + "Level": 1, + "BriefDescription": "Average Latency for L1 instruction cache misses", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "a" + }, + { + "Name": "ICACHE_DATA.STALLS:c1:e1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "icache_data.stalls / icache_data.stalls:c1:e1", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchLat;IcMiss", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_IpDSB_Miss_Ret", + "LegacyName": "metric_TMA_Info_Frontend_IpDSB_Miss_Ret", + "Level": 1, + "BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FRONTEND_RETIRED.ANY_DSB_MISS", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / frontend_retired.any_dsb_miss", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Frontend_IpDSB_Miss_Ret" + } + ], + "Formula": "a < 50", + "BaseFormula": "metric_TMA_Info_Frontend_IpDSB_Miss_Ret < 50", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;Fed", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_IpUnknown_Branch", + "LegacyName": "metric_TMA_Info_Frontend_IpUnknown_Branch", + "Level": 1, + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "BaseFormula": "tma_info_inst_mix_instructions / baclears.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_L2MPKI_Code", + "LegacyName": "metric_TMA_Info_Frontend_L2MPKI_Code", + "Level": 1, + "BriefDescription": "L2 cache true code cacheline misses per kilo instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FRONTEND_RETIRED.L2_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": "1000 * frontend_retired.l2_miss / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "IcMiss", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_L2MPKI_Code_All", + "LegacyName": "metric_TMA_Info_Frontend_L2MPKI_Code_All", + "Level": 1, + "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.CODE_RD_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": "1000 * l2_rqsts.code_rd_miss / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "IcMiss", + "LocateWith": "" + }, + { + "MetricName": "Info_Botlnk_L2_DSB_Misses", + "LegacyName": "metric_TMA_Info_Botlnk_L2_DSB_Misses", + "Level": 1, + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "j" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "k" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "l" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "m" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "n" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "o" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "p" + }, + { + "Name": "DECODE.LCP", + "Alias": "q" + }, + { + "Name": "IDQ.MITE_CYCLES_ANY", + "Alias": "r" + }, + { + "Name": "IDQ.MITE_CYCLES_OK", + "Alias": "s" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "t" + }, + { + "Name": "IDQ.DSB_CYCLES_ANY", + "Alias": "u" + }, + { + "Name": "IDQ.DSB_CYCLES_OK", + "Alias": "v" + }, + { + "Name": "IDQ.MS_CYCLES_ANY", + "Alias": "w" + }, + { + "Name": "UOPS_RETIRED.MS:c1", + "Alias": "x" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( h / ( i ) ) / ( ( j / ( i ) ) + ( k / ( i ) ) + ( l / ( i ) + ( m / ( i ) ) ) + ( ( 3 ) * n / ( o / p ) / ( i ) ) + ( q / ( i ) ) + ( h / ( i ) ) ) + ( max( 0 , ( b / ( b + c + d + e ) - f / ( g ) ) - ( ( a / ( b + c + d + e ) - f / ( g ) ) ) ) ) * ( ( r - s ) / ( t if smt_on else ( i ) ) / 2 ) / ( ( ( r - s ) / ( t if smt_on else ( i ) ) / 2 ) + ( ( u - v ) / ( t if smt_on else ( i ) ) / 2 ) + ( max( w , x / ( o / p ) ) / ( t if smt_on else ( i ) ) / 2.4 ) ) )", + "BaseFormula": "100 * ( tma_fetch_latency * tma_dsb_switches / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_mite / ( tma_mite + tma_dsb + tma_ms ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Misses" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Misses > 10", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;Fed", + "LocateWith": "" + }, + { + "MetricName": "Info_Botlnk_L2_DSB_Bandwidth", + "LegacyName": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth", + "Level": 1, + "BriefDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "g" + }, + { + "Name": "IDQ.DSB_CYCLES_ANY", + "Alias": "h" + }, + { + "Name": "IDQ.DSB_CYCLES_OK", + "Alias": "i" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "j" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "k" + }, + { + "Name": "IDQ.MITE_CYCLES_ANY", + "Alias": "l" + }, + { + "Name": "IDQ.MITE_CYCLES_OK", + "Alias": "m" + }, + { + "Name": "IDQ.MS_CYCLES_ANY", + "Alias": "n" + }, + { + "Name": "UOPS_RETIRED.MS:c1", + "Alias": "o" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "p" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "q" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a / ( a + b + c + d ) - e / ( f ) ) * ( ( max( 0 , ( a / ( a + b + c + d ) - e / ( f ) ) - ( ( g / ( a + b + c + d ) - e / ( f ) ) ) ) ) / ( ( ( g / ( a + b + c + d ) - e / ( f ) ) ) + ( max( 0 , ( a / ( a + b + c + d ) - e / ( f ) ) - ( ( g / ( a + b + c + d ) - e / ( f ) ) ) ) ) ) ) * ( ( ( h - i ) / ( j if smt_on else ( k ) ) / 2 ) / ( ( ( l - m ) / ( j if smt_on else ( k ) ) / 2 ) + ( ( h - i ) / ( j if smt_on else ( k ) ) / 2 ) + ( max( n , o / ( p / q ) ) / ( j if smt_on else ( k ) ) / 2.4 ) ) ) )", + "BaseFormula": "100 * ( tma_frontend_bound * ( tma_fetch_bandwidth / ( tma_fetch_latency + tma_fetch_bandwidth ) ) * ( tma_dsb / ( tma_mite + tma_dsb + tma_ms ) ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth > 10", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSB;Fed;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Botlnk_L2_IC_Misses", + "LegacyName": "metric_TMA_Info_Botlnk_L2_IC_Misses", + "Level": 1, + "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "j" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "k" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "l" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "m" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "n" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "o" + }, + { + "Name": "DECODE.LCP", + "Alias": "p" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "q" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( h / ( i ) ) / ( ( h / ( i ) ) + ( j / ( i ) ) + ( k / ( i ) + ( l / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) )", + "BaseFormula": "100 * ( tma_fetch_latency * tma_icache_misses / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Botlnk_L2_IC_Misses" + } + ], + "Formula": "a > 5", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_IC_Misses > 5", + "ThresholdIssues": "$issueFL" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchLat;IcMiss", + "LocateWith": "" + }, + { + "MetricName": "Info_Bad_Spec_IpMispredict", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMispredict", + "Level": 1, + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / br_misp_retired.all_branches", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Bad_Spec_IpMispredict" + } + ], + "Formula": "a < 200", + "BaseFormula": "metric_TMA_Info_Bad_Spec_IpMispredict < 200", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "LocateWith": "" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Cond_Ntaken", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Cond_Ntaken", + "Level": 1, + "BriefDescription": "Instructions per retired Mispredicts for conditional non-taken branches (lower number means higher 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"Name": "BR_MISP_RETIRED.RET", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / br_misp_retired.ret", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Bad_Spec_IpMisp_Ret" + } + ], + "Formula": "a < 500", + "BaseFormula": "metric_TMA_Info_Bad_Spec_IpMisp_Ret < 500", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts", + "LocateWith": "" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Indirect", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Indirect", + "Level": 1, + "BriefDescription": "Instructions per retired Mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.INDIRECT", + "Alias": "b" + } + ], + "Constants": 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"BaseFormula": "1000 * mem_load_retired.l3_miss / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_FB_HPKI", + "LegacyName": "metric_TMA_Info_Memory_FB_HPKI", + "Level": 1, + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": "1000 * mem_load_retired.fb_hit / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, 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"Events": [ + { + "Name": "LONGEST_LAT_CACHE.MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": "64 * longest_lat_cache.miss / ( 1000000000 ) / tma_info_system_time", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_L3_Cache_Access_BW", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Access_BW", + "Level": 1, + "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS.ALL_REQUESTS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": "64 * offcore_requests.all_requests / ( 1000000000 ) / tma_info_system_time", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_TLB_Page_Walks_Utilization", + "LegacyName": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization", + "Level": 1, + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_PENDING", + "Alias": "a" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_PENDING", + "Alias": "b" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_PENDING", + "Alias": "c" + }, + { + "Name": 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"metric_TMA_Info_Memory_TLB_Code_STLB_MPKI", + "Level": 1, + "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": "1000 * itlb_misses.walk_completed / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_TLB_Load_STLB_MPKI", + "LegacyName": "metric_TMA_Info_Memory_TLB_Load_STLB_MPKI", + "Level": 1, + "BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page 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"LocateWith": "" + }, + { + "MetricName": "Info_Memory_Core_L3_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_Core_L3_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "LONGEST_LAT_CACHE.MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "BaseFormula": "tma_info_memory_l3_cache_fill_bw", + "Category": "TMA", + "CountDomain": "Core_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Core_L3_Cache_Access_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_Core_L3_Cache_Access_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS.ALL_REQUESTS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "BaseFormula": "tma_info_memory_l3_cache_access_bw", + "Category": "TMA", + "CountDomain": "Core_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Core_L2_Evictions_Silent_PKI", + "LegacyName": "metric_TMA_Info_Memory_Core_L2_Evictions_Silent_PKI", + "Level": 1, + "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or 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"BaseFormula": "1000 * l2_lines_out.non_silent / tma_info_inst_mix_instructions", + "Category": "TMA", + "CountDomain": "Core_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "L2Evicts;Mem;Server", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Prefetches_Useless_HWPF", + "LegacyName": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF", + "Level": 1, + "BriefDescription": "Rate of L2 HW prefetched lines that were not used by demand accesses", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_OUT.USELESS_HWPF", + "Alias": "a" + }, + { + "Name": "L2_LINES_OUT.SILENT", + "Alias": "b" + }, + { + "Name": "L2_LINES_OUT.NON_SILENT", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "BaseFormula": "l2_lines_out.useless_hwpf / ( l2_lines_out.silent + l2_lines_out.non_silent )", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF" + } + ], + "Formula": "a > 0.15", + "BaseFormula": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF > 0.15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Prefetches", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Latency_Load_L2_Miss_Latency", + "LegacyName": "metric_TMA_Info_Memory_Latency_Load_L2_Miss_Latency", + "Level": 1, + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "offcore_requests_outstanding.demand_data_rd / offcore_requests.demand_data_rd", + "Category": "TMA", + "CountDomain": "Clocks_Latency", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "LockCont;Memory_Lat;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Latency_Load_L3_Miss_Latency", + "LegacyName": "metric_TMA_Info_Memory_Latency_Load_L3_Miss_Latency", + "Level": 1, + "BriefDescription": "Average Latency for L3 cache miss demand Loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "offcore_requests_outstanding.l3_miss_demand_data_rd / offcore_requests.l3_miss_demand_data_rd", + "Category": "TMA", + "CountDomain": "Clocks_Latency", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_Lat;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Latency_Load_L2_MLP", + "LegacyName": "metric_TMA_Info_Memory_Latency_Load_L2_MLP", + "Level": 1, + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "offcore_requests_outstanding.demand_data_rd / offcore_requests_outstanding.demand_data_rd:c1", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_BW;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Latency_Data_L2_MLP", + "LegacyName": "metric_TMA_Info_Memory_Latency_Data_L2_MLP", + "Level": 1, + "BriefDescription": "Average Parallel L2 cache miss data reads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "offcore_requests_outstanding.data_rd / offcore_requests_outstanding.cycles_with_data_rd", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_BW;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Mix_Offcore_Read_Any_PKI", + "LegacyName": "metric_TMA_Info_Memory_Mix_Offcore_Read_Any_PKI", + "Level": 1, + "BriefDescription": "Off-core accesses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.READS_TO_CORE.ANY_RESPONSE", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "BaseFormula": "1000 * ocr.reads_to_core.any_response / tma_info_inst_mix_instructions", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Offcore;Server", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Mix_Offcore_Read_L3M_PKI", + "LegacyName": "metric_TMA_Info_Memory_Mix_Offcore_Read_L3M_PKI", + "Level": 1, + "BriefDescription": "L3 cache misses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.READS_TO_CORE.L3_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "BaseFormula": "1000 * ocr.reads_to_core.l3_miss / tma_info_inst_mix_instructions", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Offcore;Server", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Mix_Offcore_MWrite_Any_PKI", + "LegacyName": "metric_TMA_Info_Memory_Mix_Offcore_MWrite_Any_PKI", + "Level": 1, + "BriefDescription": "Off-core accesses per kilo instruction for modified write requests", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.MODIFIED_WRITE.ANY_RESPONSE", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "BaseFormula": "1000 * ocr.modified_write.any_response / tma_info_inst_mix_instructions", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Offcore;Server", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Mix_UC_Load_PKI", + "LegacyName": "metric_TMA_Info_Memory_Mix_UC_Load_PKI", + "Level": 1, + "BriefDescription": "Un-cacheable retired load per kilo instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_MISC_RETIRED.UC", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": "1000 * mem_load_misc_retired.uc / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Mix_Bus_Lock_PKI", + "LegacyName": "metric_TMA_Info_Memory_Mix_Bus_Lock_PKI", + "Level": 1, + "BriefDescription": "\"Bus lock\" per kilo instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "SQ_MISC.BUS_LOCK", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": "1000 * sq_misc.bus_lock / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem", + "LocateWith": "" + }, + { + "MetricName": "Info_System_CPU_Utilization", + "LegacyName": "metric_TMA_Info_System_CPU_Utilization", + "Level": 1, + "BriefDescription": "Average CPU Utilization (percentage)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "b" + }, + { + "Name": "system.sockets[0].cpus.count * system.socket_count", + "Alias": "c" + } + ], + "Formula": "( a / b ) / c", + "BaseFormula": "tma_info_system_cpus_utilized / num_cpus", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Summary", + "LocateWith": "" + }, + { + "MetricName": "Info_System_CPUs_Utilized", + "LegacyName": "metric_TMA_Info_System_CPUs_Utilized", + "Level": 1, + "BriefDescription": "Average number of utilized CPUs", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "b" + } + ], + "Formula": "a / b", + "BaseFormula": "cpu_clk_unhalted.ref_tsc / tsc", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SYSTEM", + "MetricGroup": "Summary", + "LocateWith": "" + }, + { + "MetricName": "Info_System_Core_Frequency", + "LegacyName": "metric_TMA_Info_System_Core_Frequency", + "Level": 1, + "BriefDescription": "Measured Average Core Frequency for unhalted processors [GHz]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": "tma_info_system_turbo_utilization * tsc / ( 1000000000 ) / tma_info_system_time", + "Category": "TMA", + "CountDomain": "System_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Summary;Power", + "LocateWith": "" + }, + { + "MetricName": "Info_System_Uncore_Frequency", + "LegacyName": "metric_TMA_Info_System_Uncore_Frequency", + "Level": 1, + "BriefDescription": "Measured Average Uncore Frequency for the SoC [GHz]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a ) / 1e9 / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": "tma_info_system_socket_clks / 1e9 / tma_info_system_time", + "Category": "TMA", + "CountDomain": "System_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "SoC", + "LocateWith": "" + }, + { + "MetricName": "Info_System_GFLOPs", + "LegacyName": "metric_TMA_Info_System_GFLOPs", + "Level": 1, + "BriefDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED.4_FLOPS", + "Alias": "e" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", + "Alias": "f" + }, + { + "Name": "FP_ARITH_INST_RETIRED.8_FLOPS", + "Alias": "g" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", + "Alias": "h" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "i" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", + "Alias": "j" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( ( 1 * ( a + b ) + 2 * ( c + d ) + 4 * e + 8 * ( f + g ) + 16 * ( h + i ) + 32 * j ) ) / ( 1000000000 ) ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": "( ( ( 1 * ( fp_arith_inst_retired.scalar + fp_arith_inst_retired2.scalar_half ) + 2 * ( fp_arith_inst_retired.128b_packed_double + fp_arith_inst_retired2.complex_scalar_half ) + 4 * fp_arith_inst_retired.4_flops + 8 * ( fp_arith_inst_retired2.128b_packed_half + fp_arith_inst_retired.8_flops ) + 16 * ( fp_arith_inst_retired2.256b_packed_half + fp_arith_inst_retired.512b_packed_single ) + 32 * fp_arith_inst_retired2.512b_packed_half ) ) / ( 1000000000 ) ) / tma_info_system_time", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;Flops;HPC", + "LocateWith": "" + }, + { + "MetricName": "Info_System_Turbo_Utilization", + "LegacyName": "metric_TMA_Info_System_Turbo_Utilization", + "Level": 1, + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "BaseFormula": "tma_info_thread_clks / cpu_clk_unhalted.ref_tsc", + "Category": "TMA", + "CountDomain": "Core_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Power", + "LocateWith": "" + }, + { + "MetricName": "Info_System_SMT_2T_Utilization", + "LegacyName": "metric_TMA_Info_System_SMT_2T_Utilization", + "Level": 1, + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "1 - 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Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 1000000000 ) * ( a / b ) / ( ( c ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "BaseFormula": "( 1000000000 ) * ( unc_cha_tor_occupancy.ia_miss_drd / unc_cha_tor_inserts.ia_miss_drd ) / ( tma_info_system_socket_clks / tma_info_system_time )", + "Category": "TMA", + "CountDomain": "NanoSeconds", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryLat;SoC", + "LocateWith": "" + }, + { + "MetricName": "Info_System_MEM_Parallel_Reads", + "LegacyName": "metric_TMA_Info_System_MEM_Parallel_Reads", + "Level": 1, + "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "unc_cha_tor_occupancy.ia_miss_drd / unc_cha_tor_occupancy.ia_miss_drd:c1", + "Category": "TMA", + "CountDomain": "System_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;SoC", + "LocateWith": "" + }, + { + "MetricName": "Info_System_MEM_DRAM_Read_Latency", + "LegacyName": "metric_TMA_Info_System_MEM_DRAM_Read_Latency", + "Level": 1, + "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "( 1000000000 ) * ( a / b ) / c", + "BaseFormula": "( 1000000000 ) * ( unc_cha_tor_occupancy.ia_miss_drd_ddr / unc_cha_tor_inserts.ia_miss_drd_ddr ) / unc_cha_clockticks:one_unit", + "Category": "TMA", + "CountDomain": "NanoSeconds", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "MemOffcore;MemoryLat;SoC;Server", + "LocateWith": "" + }, + { + "MetricName": "Info_System_IO_Read_BW", + "LegacyName": "metric_TMA_Info_System_IO_Read_BW", + "Level": 1, + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]. Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "a * 64 / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": "unc_cha_tor_inserts.io_pcirdcur * 64 / ( 1000000000 ) / tma_info_system_time", + "Category": "TMA", + "CountDomain": "GB/sec", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "IoBW;MemOffcore;SoC;Server", + "LocateWith": "" + }, + { + "MetricName": "Info_System_IO_Write_BW", + "LegacyName": "metric_TMA_Info_System_IO_Write_BW", + "Level": 1, + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]. Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a + b ) * 64 / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": "( unc_cha_tor_inserts.io_itom + unc_cha_tor_inserts.io_itomcachenear ) * 64 / ( 1000000000 ) / tma_info_system_time", + "Category": "TMA", + "CountDomain": "GB/sec", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "IoBW;MemOffcore;SoC;Server", + "LocateWith": "" + }, + { + "MetricName": "Info_System_UPI_Data_Transmit_BW", + "LegacyName": "metric_TMA_Info_System_UPI_Data_Transmit_BW", + "Level": 1, + "BriefDescription": "Cross-socket Ultra Path Interconnect (UPI) data transmit bandwidth for data only [MB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_UPI_TxL_FLITS.ALL_DATA", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a * 64 / 9 / 1000000", + "BaseFormula": "unc_upi_txl_flits.all_data * 64 / 9 / 1000000", + "Category": "TMA", + "CountDomain": "MB/sec", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "UPI, SOCKET, SYSTEM", + "MetricGroup": "SoC;Server", + "LocateWith": "" + }, + { + "MetricName": "Info_System_Power", + "LegacyName": "metric_TMA_Info_System_Power", + "Level": 1, + "BriefDescription": "Total package Power in Watts", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FREERUN_PKG_ENERGY_STATUS", + "Alias": "a" + }, + { + "Name": "FREERUN_DRAM_ENERGY_STATUS", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a * ( 61 ) + 15.6 * b ) / ( ( durationtimeinmilliseconds / 1000 ) * ( 1000000 ) )", + "BaseFormula": "( freerun_pkg_energy_status * ( 61 ) + 15.6 * freerun_dram_energy_status ) / ( ( duration_time ) * ( 1000000 ) )", + "Category": "TMA", + "CountDomain": "System_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Power;SoC", + "LocateWith": "" + }, + { + "MetricName": "Info_System_Time", + "LegacyName": "metric_TMA_Info_System_Time", + "Level": 1, + "BriefDescription": "Run duration time in seconds", + "UnitOfMeasure": "", + "Events": [], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( durationtimeinmilliseconds / 1000 )", + "BaseFormula": "duration_time", + "Category": "TMA", + "CountDomain": "Seconds", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_System_Time" + } + ], + "Formula": "a < 1", + "BaseFormula": "metric_TMA_Info_System_Time < 1", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Summary", + "LocateWith": "" + }, + { + "MetricName": "Info_System_MUX", + "LegacyName": "metric_TMA_Info_System_MUX", + "Level": 1, + "BriefDescription": "PerfMon Event Multiplexing accuracy indicator", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "cpu_clk_unhalted.thread_p / cpu_clk_unhalted.thread", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_System_MUX" + } + ], + "Formula": "a > 1.1 | a < 0.9", + "BaseFormula": "metric_TMA_Info_System_MUX > 1.1 | metric_TMA_Info_System_MUX < 0.9", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary", + "LocateWith": "" + }, + { + "MetricName": "Info_System_Socket_CLKS", + "LegacyName": "metric_TMA_Info_System_Socket_CLKS", + "Level": 1, + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "BaseFormula": "unc_cha_clockticks:one_unit", + "Category": "TMA", + "CountDomain": "Count", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "SoC", + "LocateWith": "" + }, + { + "MetricName": "Info_System_IpFarBranch", + "LegacyName": "metric_TMA_Info_System_IpFarBranch", + "Level": 1, + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.FAR_BRANCH:USER", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / br_inst_retired.far_branch:user", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_System_IpFarBranch" + } + ], + "Formula": "a < 1000000", + "BaseFormula": "metric_TMA_Info_System_IpFarBranch < 1000000", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;OS", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_SoC_R2C_Offcore_BW", + "LegacyName": "metric_TMA_Info_Memory_SoC_R2C_Offcore_BW", + "Level": 1, + "BriefDescription": "Average Off-core access BW for Reads-to-Core (R2C). R2C account for demand or prefetch load/RFO/code access that fill data into the Core caches.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.READS_TO_CORE.ANY_RESPONSE", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / 1e9 / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": "64 * ocr.reads_to_core.any_response / 1e9 / tma_info_system_time", + "Category": "TMA", + "CountDomain": "GB/sec", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Mem;MemoryBW;Server;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_SoC_R2C_L3M_BW", + "LegacyName": "metric_TMA_Info_Memory_SoC_R2C_L3M_BW", + "Level": 1, + "BriefDescription": "Average L3-cache miss BW for Reads-to-Core (R2C). This covering going to DRAM or other memory off-chip memory tears. See R2C_Offcore_BW.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.READS_TO_CORE.L3_MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / 1e9 / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": "64 * ocr.reads_to_core.l3_miss / 1e9 / tma_info_system_time", + "Category": "TMA", + "CountDomain": "GB/sec", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Mem;MemoryBW;Server;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_SoC_R2C_DRAM_BW", + "LegacyName": "metric_TMA_Info_Memory_SoC_R2C_DRAM_BW", + "Level": 1, + "BriefDescription": "Average DRAM BW for Reads-to-Core (R2C) covering for memory attached to local- and remote-socket. See R2C_Offcore_BW.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.READS_TO_CORE.DRAM", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / 1e9 / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": "64 * ocr.reads_to_core.dram / 1e9 / tma_info_system_time", + "Category": "TMA", + "CountDomain": "GB/sec", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Mem;MemoryBW;Server;Offcore", + "LocateWith": "" + } + ] +} \ No newline at end of file diff --git a/cmd/metrics/resources/perfmon/emr/emeraldrapids_uncore.json b/cmd/metrics/resources/perfmon/emr/emeraldrapids_uncore.json new file mode 100644 index 00000000..4fc83cc0 --- /dev/null +++ b/cmd/metrics/resources/perfmon/emr/emeraldrapids_uncore.json @@ -0,0 +1,5177 @@ +{ + "Header": { + "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.16", + "DatePublished": "07/03/2025", + "Version": "1.16", + "Legend": "" + }, + "Events": [ + { + "Unit": "PCU", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_P_CLOCKTICKS", + "BriefDescription": "PCU PCLK Clockticks", + "PublicDescription": "Number of PCU PCLK Clock cycles while the event is enabled", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_CLOCKTICKS", + "BriefDescription": "IRP Clockticks", + "PublicDescription": "Number of IRP clock cycles while the event is enabled", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x16", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_FAF_TRANSACTIONS", + "BriefDescription": "FAF allocation -- sent to ADQ", + "PublicDescription": "FAF allocation -- sent to ADQ", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x17", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_FAF_FULL", + "BriefDescription": "FAF RF full", + "PublicDescription": "FAF RF full", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x18", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_FAF_INSERTS", + "BriefDescription": "FAF - request insert from TC.", + "PublicDescription": "FAF - request insert from TC.", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x19", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_FAF_OCCUPANCY", + "BriefDescription": "FAF occupancy", + "PublicDescription": "FAF occupancy", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x1f", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_MISC1.LOST_FWD", + "BriefDescription": "Misc Events - Set 1 : Lost Forward", + "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x20", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", + "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)", + "PublicDescription": ": All Inserts Inbound (p2p + faf + cset)", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2PCIe", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M2P_CLOCKTICKS", + "BriefDescription": "M2P Clockticks", + "PublicDescription": "Number of M2P clock cycles while the event is enabled", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2PCIe", + "EventCode": "0xc0", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M2P_CMS_CLOCKTICKS", + "BriefDescription": "CMS Clockticks", + "PublicDescription": "CMS Clockticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x0000", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_CLOCKTICKS", + "BriefDescription": "IIO Clockticks", + "PublicDescription": "Number of IIO clock cycles while the event is enabled", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x0001", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "BriefDescription": "Write request of 4 bytes made by IIO Part0 to Memory", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x0002", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "BriefDescription": "Write request of 4 bytes made by IIO Part1 to Memory", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x0004", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "BriefDescription": "Write request of 4 bytes made by IIO Part2 to Memory", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x0008", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "BriefDescription": "Write request of 4 bytes made by IIO Part3 to Memory", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x0001", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "BriefDescription": "Read request for 4 bytes made by IIO Part0 to Memory", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x0002", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "BriefDescription": "Read request for 4 bytes made by IIO Part1 to Memory", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x0004", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "BriefDescription": "Read request for 4 bytes made by IIO Part2 to Memory", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x0008", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "BriefDescription": "Read request for 4 bytes made by IIO Part3 to Memory", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x0010", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", + "BriefDescription": "Data requested of the CPU : Card writing to DRAM", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x0020", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", + "BriefDescription": "Data requested of the CPU : Card writing to DRAM", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x0040", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", + "BriefDescription": "Data requested of the CPU : Card writing to DRAM", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x0080", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", + "BriefDescription": "Data requested of the CPU : Card writing to DRAM", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x0010", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", + "BriefDescription": "Data requested of the CPU : Card reading from DRAM", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x0020", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", + "BriefDescription": "Data requested of the CPU : Card reading from DRAM", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x0040", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", + "BriefDescription": "Data requested of the CPU : Card reading from DRAM", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x0080", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", + "BriefDescription": "Data requested of the CPU : Card reading from DRAM", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x0001", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", + "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part0 to Memory", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x0002", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", + "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part1 to Memory", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x0004", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", + "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part2 to Memory", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x0008", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", + "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part3 to Memory", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x0001", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", + "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part0 to Memory", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x0002", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", + "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part1 to Memory", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x0004", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", + "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part2 to Memory", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x0008", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", + "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part3 to Memory", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x0010", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x0020", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x0040", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x0080", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x0010", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x0020", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x0040", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x0080", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x01", + "PortMask": "0x0001", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", + "BriefDescription": "Write request of 4 bytes made to IIO Part0 by the CPU", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x01", + "PortMask": "0x0002", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", + "BriefDescription": "Write request of 4 bytes made to IIO Part1 by the CPU", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x01", + "PortMask": "0x0004", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", + "BriefDescription": "Write request of 4 bytes made to IIO Part2 by the CPU", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x01", + "PortMask": "0x0008", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", + "BriefDescription": "Write request of 4 bytes made to IIO Part3 by the CPU", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x04", + "PortMask": "0x0001", + "FCMask": "0x07", + "UMaskExt": "0x00070010", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0", + "PublicDescription": "Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x04", + "PortMask": "0x0002", + "FCMask": "0x07", + "UMaskExt": "0x00070020", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part1", + "PublicDescription": "Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x04", + "PortMask": "0x0004", + "FCMask": "0x07", + "UMaskExt": "0x00070040", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part2", + "PublicDescription": "Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x04", + "PortMask": "0x0008", + "FCMask": "0x07", + "UMaskExt": "0x00070080", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part3", + "PublicDescription": "Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x01", + "PortMask": "0x0010", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4", + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x01", + "PortMask": "0x0020", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5", + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x01", + "PortMask": "0x0040", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6", + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x01", + "PortMask": "0x0080", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7", + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x04", + "PortMask": "0x0010", + "FCMask": "0x07", + "UMaskExt": "0x00070100", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4", + "BriefDescription": "Data requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x04", + "PortMask": "0x0020", + "FCMask": "0x07", + "UMaskExt": "0x00070200", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5", + "BriefDescription": "Data requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x04", + "PortMask": "0x0040", + "FCMask": "0x07", + "UMaskExt": "0x00070400", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6", + "BriefDescription": "Data requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x04", + "PortMask": "0x0080", + "FCMask": "0x07", + "UMaskExt": "0x00070800", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7", + "BriefDescription": "Data requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x01", + "PortMask": "0x0001", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", + "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x01", + "PortMask": "0x0002", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", + "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x01", + "PortMask": "0x0004", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", + "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x01", + "PortMask": "0x0008", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", + "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x04", + "PortMask": "0x0001", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", + "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part0", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x04", + "PortMask": "0x0002", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", + "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part1", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x04", + "PortMask": "0x0004", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", + "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part2", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x04", + "PortMask": "0x0008", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", + "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part3", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x01", + "PortMask": "0x0010", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x01", + "PortMask": "0x0020", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x01", + "PortMask": "0x0040", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x01", + "PortMask": "0x0080", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x04", + "PortMask": "0x0010", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x04", + "PortMask": "0x0020", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x04", + "PortMask": "0x0040", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x04", + "PortMask": "0x0080", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x01", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CLOCKTICKS", + "BriefDescription": "IMC Clockticks at DCLK frequency", + "PublicDescription": "Number of DRAM DCLK clock cycles while the event is enabled", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_HCLOCKTICKS", + "BriefDescription": "IMC Clockticks at HCLK frequency", + "PublicDescription": "Number of DRAM HCLK clock cycles while the event is enabled", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x02", + "UMask": "0xff", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_ACT_COUNT.ALL", + "BriefDescription": "Activate due to read, write, underfill, or bypass", + "PublicDescription": "DRAM Activate Count : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x03", + "UMask": "0x11", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_PRE_COUNT.RD", + "BriefDescription": "Precharge due to read on page miss", + "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x03", + "UMask": "0x22", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_PRE_COUNT.WR", + "BriefDescription": "Precharge due to write on page miss", + "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x03", + "UMask": "0x88", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_PRE_COUNT.PGT", + "BriefDescription": "DRAM Precharge commands", + "PublicDescription": "DRAM Precharge commands. Counts the number of DRAM Precharge commands sent on this channel.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x03", + "UMask": "0xff", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_PRE_COUNT.ALL", + "BriefDescription": "Precharge due to read, write, underfill, or PGT.", + "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x05", + "UMask": "0xcf", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT.RD", + "BriefDescription": "All DRAM read CAS commands issued (including underfills)", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM Read CAS commands issued on this channel. This includes underfills.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x05", + "UMask": "0xf0", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT.WR", + "BriefDescription": "All DRAM write CAS commands issued", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM Write CAS commands issued on this channel.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x05", + "UMask": "0xff", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT.ALL", + "BriefDescription": "All DRAM CAS commands issued", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : All DRAM Read and Write actions : DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM CAS commands issued on this channel.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x10", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_INSERTS.PCH0", + "BriefDescription": "Read Pending Queue Allocations", + "PublicDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x10", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_INSERTS.PCH1", + "BriefDescription": "Read Pending Queue Allocations", + "PublicDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x20", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_INSERTS.PCH0", + "BriefDescription": "Write Pending Queue Allocations", + "PublicDescription": "Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x20", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_INSERTS.PCH1", + "BriefDescription": "Write Pending Queue Allocations", + "PublicDescription": "Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x80", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0", + "BriefDescription": "Read Pending Queue Occupancy", + "PublicDescription": "Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x81", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1", + "BriefDescription": "Read Pending Queue Occupancy", + "PublicDescription": "Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x82", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0", + "BriefDescription": "Write Pending Queue Occupancy", + "PublicDescription": "Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x83", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1", + "BriefDescription": "Write Pending Queue Occupancy", + "PublicDescription": "Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xd3", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_TAGCHK.HIT", + "BriefDescription": "2LM Tag check hit in near memory cache (DDR4)", + "PublicDescription": "2LM Tag check hit in near memory cache (DDR4)", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xd3", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_TAGCHK.MISS_CLEAN", + "BriefDescription": "2LM Tag check miss, no data at this line", + "PublicDescription": "2LM Tag check miss, no data at this line", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xd3", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_TAGCHK.MISS_DIRTY", + "BriefDescription": "2LM Tag check miss, existing data may be evicted to PMM", + "PublicDescription": "2LM Tag check miss, existing data may be evicted to PMM", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xd3", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_TAGCHK.NM_RD_HIT", + "BriefDescription": "2LM Tag check hit due to memory read", + "PublicDescription": "2LM Tag check hit due to memory read", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xd3", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_TAGCHK.NM_WR_HIT", + "BriefDescription": "2LM Tag check hit due to memory write", + "PublicDescription": "2LM Tag check hit due to memory write", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M2M_CLOCKTICKS", + "BriefDescription": "M2M Clockticks", + "PublicDescription": "Clockticks of the mesh to memory (M2M)", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x20", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY", + "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)", + "PublicDescription": "Counts the number of hit data returns to egress with any directory to non persistent memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x20", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A", + "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)", + "PublicDescription": "Counts the number of hit data returns to egress with directory A to non persistent memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x20", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I", + "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)", + "PublicDescription": "Counts the number of hit data returns to egress with directory I to non persistent memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x20", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S", + "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)", + "PublicDescription": "Counts the number of hit data returns to egress with directory S to non persistent memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x21", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x03", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY", + "BriefDescription": "Multi-socket cacheline Directory update from/to Any state", + "PublicDescription": "Multi-socket cacheline Directory update from/to Any state", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0xc0", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x800000", + "EventName": "UNC_M2M_CMS_CLOCKTICKS", + "BriefDescription": "CMS Clockticks", + "PublicDescription": "CMS Clockticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M3UPI", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M3UPI_CLOCKTICKS", + "BriefDescription": "M3UPI Clockticks", + "PublicDescription": "Number of M2UPI clock cycles while the event is enabled", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_CLOCKTICKS", + "BriefDescription": "UPI Clockticks", + "PublicDescription": "Number of UPI LL clock cycles while the event is enabled", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x02", + "UMask": "0x0f", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", + "BriefDescription": "Valid Flits Sent : All Data", + "PublicDescription": "Valid Flits Sent : All Data : Counts number of data flits across this UPI link.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x02", + "UMask": "0x97", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", + "BriefDescription": "Valid Flits Sent : All Non Data", + "PublicDescription": "Valid Flits Sent : All Non Data : Shows legal flit time (hides impact of L0p and L0c).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x02", + "UMask": "0x27", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", + "BriefDescription": "All Null Flits", + "PublicDescription": "All Null Flits", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x03", + "UMask": "0x0f", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", + "BriefDescription": "Valid Flits Received : All Data", + "PublicDescription": "Valid Flits Received : All Data : Shows legal flit time (hides impact of L0p and L0c).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x03", + "UMask": "0x97", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", + "BriefDescription": "Valid Flits Received : All Non Data", + "PublicDescription": "Valid Flits Received : All Non Data : Shows legal flit time (hides impact of L0p and L0c).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x03", + "UMask": "0x27", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", + "BriefDescription": "Null FLITs received from any slot", + "PublicDescription": "Null FLITs received from any slot", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x21", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_L1_POWER_CYCLES", + "BriefDescription": "Cycles in L1", + "PublicDescription": "Cycles in L1 : Number of UPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a UPI link. Use edge detect to count the number of instances when the UPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", + "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data", + "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x20", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE", + "BriefDescription": "Remote requests for exclusive ownership of a cache line without receiving data", + "PublicDescription": "Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", + "BriefDescription": "Read requests from a unit on this socket", + "PublicDescription": "Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.READS_REMOTE", + "BriefDescription": "Read requests from a remote socket", + "PublicDescription": "Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL", + "BriefDescription": "Write Requests from a unit on this socket", + "PublicDescription": "Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", + "BriefDescription": "Read and Write Requests; Writes Remote", + "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x03", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.READS", + "BriefDescription": "Read requests made into the CHA", + "PublicDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) .", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x0c", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.WRITES", + "BriefDescription": "Write requests made into the CHA", + "PublicDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x54", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_DIR_UPDATE.HA", + "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe", + "PublicDescription": "Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x54", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_DIR_UPDATE.TOR", + "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe", + "PublicDescription": "Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x59", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", + "BriefDescription": "Normal priority reads issued to the memory controller from the CHA", + "PublicDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x5b", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", + "BriefDescription": "CHA to iMC Full Line Writes Issued; Full Line Non-ISOCH", + "PublicDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channels.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0xc0", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_CMS_CLOCKTICKS", + "BriefDescription": "CMS Clockticks", + "PublicDescription": "CMS Clockticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_CLOCKTICKS", + "BriefDescription": "CHA Clockticks", + "PublicDescription": "Number of CHA clock cycles while the event is enabled", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c001ff", + "EventName": "UNC_CHA_TOR_INSERTS.IA", + "BriefDescription": "TOR Inserts; All from Local IA", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests from IA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c001fd", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", + "BriefDescription": "TOR Inserts; Hits from Local IA", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c80ffd", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", + "BriefDescription": "TOR Inserts; CRd hits from local IA", + "PublicDescription": "TOR Inserts; Code read from local IA that hits in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c817fd", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD", + "BriefDescription": "TOR Inserts; DRd hits from local IA", + "PublicDescription": "TOR Inserts; Data read from local IA that hits in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00ccc7fd", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO", + "BriefDescription": "TOR Inserts; LLCPrefRFO hits from local IA", + "PublicDescription": "TOR Inserts; Last level cache prefetch read for ownership from local IA that hits in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c807fd", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", + "BriefDescription": "TOR Inserts; RFO hits from local IA", + "PublicDescription": "TOR Inserts; Read for ownership from local IA that hits in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c001fe", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", + "BriefDescription": "TOR Inserts; misses from Local IA", + "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c80ffe", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "BriefDescription": "TOR Inserts for CRd misses from local IA", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode CRd", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c817fe", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "BriefDescription": "TOR Inserts for DRd misses from local IA", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00ccc7fe", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO", + "BriefDescription": "TOR Inserts; LLCPrefRFO misses from local IA", + "PublicDescription": "TOR Inserts; Last level cache prefetch read for ownership from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c807fe", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", + "BriefDescription": "TOR Inserts; RFO misses from local IA", + "PublicDescription": "TOR Inserts; Read for ownership from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c001ff", + "EventName": "UNC_CHA_TOR_INSERTS.IO", + "BriefDescription": "TOR Inserts; All from local IO", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c001fd", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", + "BriefDescription": "TOR Inserts; Hits from local IO", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c001fe", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", + "BriefDescription": "TOR Inserts; Misses from local IO", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00cc43fe", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "BriefDescription": "TOR Inserts : ItoM, indicating a full cacheline write request, from IO Devices that missed the LLC", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c803fe", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "BriefDescription": "TOR Inserts; RFO misses from local IO", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c88ffd", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF", + "BriefDescription": "TOR Inserts; CRd Pref hits from local IA", + "PublicDescription": "TOR Inserts; Code read prefetch from local IA that hits in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c897fd", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF", + "BriefDescription": "TOR Inserts; DRd Pref hits from local IA", + "PublicDescription": "TOR Inserts; Data read prefetch from local IA that hits in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c887fd", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF", + "BriefDescription": "TOR Inserts; RFO Pref hits from local IA", + "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that hits in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c88ffe", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", + "BriefDescription": "TOR Inserts; CRd Pref misses from local IA", + "PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c897fe", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF", + "BriefDescription": "TOR Inserts for DRd Pref misses from local IA", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c887fe", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", + "BriefDescription": "TOR Inserts; RFO pref misses from local IA", + "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00cc43fd", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", + "BriefDescription": "TOR Inserts; ItoM hits from local IO", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c803fd", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO", + "BriefDescription": "TOR Inserts; RFO hits from local IO", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c803ff", + "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO", + "BriefDescription": "TOR Inserts; RFO from local IO", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00cc43ff", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "BriefDescription": "TOR Inserts for ItoM from local IO", + "PublicDescription": "Inserts into the TOR from local IO with the opcode ItoM", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c887ff", + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF", + "BriefDescription": "TOR Inserts; RFO pref from local IA", + "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c807ff", + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO", + "BriefDescription": "TOR Inserts; RFO from local IA", + "PublicDescription": "TOR Inserts; Read for ownership from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00ccc7ff", + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO", + "BriefDescription": "TOR Inserts; LLCPrefRFO from local IA", + "PublicDescription": "TOR Inserts; Last level cache prefetch read for ownership from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c817ff", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD", + "BriefDescription": "TOR Inserts; DRd from local IA", + "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c897ff", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF", + "BriefDescription": "TOR Inserts; DRd Pref from local IA", + "PublicDescription": "TOR Inserts; Data read prefetch from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c80fff", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD", + "BriefDescription": "TOR Inserts; CRd from local IA", + "PublicDescription": "TOR Inserts; Code read from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c816fe", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", + "BriefDescription": "TOR Inserts for DRd misses from local IA targeting local memory", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target local memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8177e", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", + "BriefDescription": "TOR Inserts for DRd misses from local IA targeting remote memory", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and target remote memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C896FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL", + "BriefDescription": "TOR Inserts for DRd Pref misses from local IA targeting local memory", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target local memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8977E", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE", + "BriefDescription": "TOR Inserts for DRd Pref misses from local IA targeting remote memory", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target remote memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c806fe", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL", + "BriefDescription": "TOR Inserts RFO misses from local IA", + "PublicDescription": "TOR Inserts; Read for ownership from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8077e", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE", + "BriefDescription": "TOR Inserts; RFO misses from local IA", + "PublicDescription": "TOR Inserts Read for ownership from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c886fe", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL", + "BriefDescription": "TOR Inserts; RFO prefetch misses from local IA", + "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8877e", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE", + "BriefDescription": "TOR Inserts; RFO prefetch misses from local IA", + "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8c7ff", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH", + "BriefDescription": "TOR Inserts;CLFlush from Local IA", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; CLFlush events that are initiated from the Core", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00cc57ff", + "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM", + "BriefDescription": "TOR Inserts;SpecItoM from Local IA", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; SpecItoM events that are initiated from the Core", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c001ff", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", + "BriefDescription": "TOR Occupancy; All from local IA", + "PublicDescription": "TOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c001fd", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", + "BriefDescription": "TOR Occupancy; Hits from local IA", + "PublicDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c80ffd", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", + "BriefDescription": "TOR Occupancy; CRd hits from local IA", + "PublicDescription": "TOR Occupancy; Code read from local IA that hits in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c817fd", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", + "BriefDescription": "TOR Occupancy; DRd hits from local IA", + "PublicDescription": "TOR Occupancy; Data read from local IA that hits in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00ccc7fd", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO", + "BriefDescription": "TOR Occupancy; LLCPrefRFO hits from local IA", + "PublicDescription": "TOR Occupancy; Last level cache prefetch read for ownership from local IA that hits in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c807fd", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "BriefDescription": "TOR Occupancy; RFO hits from local IA", + "PublicDescription": "TOR Occupancy; Read for ownership from local IA that hits in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c001fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", + "BriefDescription": "TOR Occupancy; Misses from Local IA", + "PublicDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c80ffe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", + "BriefDescription": "TOR Occupancy; CRd misses from local IA", + "PublicDescription": "TOR Occupancy; Code read from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c817fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "BriefDescription": "TOR Occupancy for DRd misses from local IA", + "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00ccc7fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO", + "BriefDescription": "TOR Occupancy; LLCPrefRFO misses from local IA", + "PublicDescription": "TOR Occupancy; Last level cache prefetch read for ownership from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c807fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", + "BriefDescription": "TOR Occupancy; RFO misses from local IA", + "PublicDescription": "TOR Occupancy; Read for ownership from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c001ff", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", + "BriefDescription": "TOR Occupancy; All from local IO", + "PublicDescription": "TOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c001fd", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", + "BriefDescription": "TOR Occupancy; Hits from local IO", + "PublicDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c001fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", + "BriefDescription": "TOR Occupancy; Misses from local IO", + "PublicDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00cc43fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", + "BriefDescription": "TOR Occupancy; ITOM misses from local IO", + "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c88ffd", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF", + "BriefDescription": "TOR Occupancy; CRd Pref hits from local IA", + "PublicDescription": "TOR Occupancy; Code read prefetch from local IA that hits in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c897fd", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_PREF", + "BriefDescription": "TOR Occupancy; DRd Pref hits from local IA", + "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that hits in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c887fd", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF", + "BriefDescription": "TOR Occupancy; RFO Pref hits from local IA", + "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that hits in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c897fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF", + "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA", + "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c887fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF", + "BriefDescription": "TOR Occupancy; RFO prefetch misses from local IA", + "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00cc43fd", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM", + "BriefDescription": "TOR Occupancy; ITOM hits from local IO", + "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00cc43ff", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM", + "BriefDescription": "TOR Occupancy; ITOM from local IO", + "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c807ff", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO", + "BriefDescription": "TOR Occupancy; RFO from local IA", + "PublicDescription": "TOR Occupancy; Read for ownership from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c887ff", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF", + "BriefDescription": "TOR Occupancy; RFO prefetch from local IA", + "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00ccc7ff", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO", + "BriefDescription": "TOR Occupancy; LLCPrefRFO from local IA", + "PublicDescription": "TOR Occupancy; Last level cache prefetch read for ownership from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c817ff", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD", + "BriefDescription": "TOR Occupancy; DRd from local IA", + "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c80fff", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD", + "BriefDescription": "TOR Occupancy; CRd from local IA", + "PublicDescription": "TOR Occupancy; Code read from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c897ff", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_PREF", + "BriefDescription": "TOR Occupancy; DRd Pref from local IA", + "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c816fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL", + "BriefDescription": "TOR Occupancy for DRd misses from local IA targeting local memory", + "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target local memory", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8177e", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE", + "BriefDescription": "TOR Occupancy for DRd misses from local IA targeting remote memory", + "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target remote memory", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8977E", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE", + "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA", + "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c806fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL", + "BriefDescription": "TOR Occupancy; RFO misses from local IA", + "PublicDescription": "TOR Occupancy; Read for ownership from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8077e", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_REMOTE", + "BriefDescription": "TOR Occupancy; RFO misses from local IA", + "PublicDescription": "TOR Occupancy; Read for ownership from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c886fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL", + "BriefDescription": "TOR Occupancy; RFO prefetch misses from local IA", + "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8877e", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE", + "BriefDescription": "TOR Occupancy; RFO prefetch misses from local IA", + "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8178a", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM", + "BriefDescription": "TOR Inserts for DRds issued by iA Cores targeting PMM Mem that Missed the LLC", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target PMM memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c81786", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", + "BriefDescription": "TOR Inserts for DRds issued by IA Cores targeting DDR Mem that Missed the LLC", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target DDR memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00cd43fd", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00cd43fe", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c81786", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR", + "BriefDescription": "TOR Occupancy for DRds issued by iA Cores targeting DDR Mem that Missed the LLC", + "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target DDR memory", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8178a", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM", + "BriefDescription": "TOR Occupancy for DRds issued by iA Cores targeting PMM Mem that Missed the LLC", + "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target PMM memory", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8f3fd", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR", + "BriefDescription": "TOR Inserts; RdCur and FsRdCur hits from local IO", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x24", + "UMask": "0x20", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000003", + "EventName": "UNC_M2M_IMC_READS.TO_PMM", + "BriefDescription": "UNC_M2M_IMC_READS.TO_PMM", + "PublicDescription": "UNC_M2M_IMC_READS.TO_PMM", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8f3fe", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "BriefDescription": "TOR Inserts; RdCur and FsRdCur requests from local IO that miss LLC", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8f3ff", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "BriefDescription": "TOR Inserts for RdCur from local IO", + "PublicDescription": "Inserts into the TOR from local IO with the opcode RdCur", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x25", + "UMask": "0x80", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000018", + "EventName": "UNC_M2M_IMC_WRITES.TO_PMM", + "BriefDescription": "PMM - All Channels", + "PublicDescription": "PMM - All Channels", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8f3fd", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR", + "BriefDescription": "TOR Occupancy; RdCur and FsRdCur hits from local IO", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8f3fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR", + "BriefDescription": "TOR Occupancy; RdCur and FsRdCur misses from local IO", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8f3ff", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR", + "BriefDescription": "TOR Occupancy; RdCur and FsRdCur from local IO", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00ccd7ff", + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA", + "BriefDescription": "TOR Inserts; LLCPrefData from local IA", + "PublicDescription": "TOR Inserts; Last level cache prefetch data read from local IA.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00ccd7fe", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", + "BriefDescription": "TOR Inserts; LLCPrefData misses from local IA", + "PublicDescription": "TOR Inserts; Last level cache prefetch data read from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00ccd7ff", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA", + "BriefDescription": "TOR Occupancy; LLCPrefData from local IA", + "PublicDescription": "TOR Occupancy; Last level cache prefetch data read from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00ccd7fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA", + "BriefDescription": "TOR Occupancy; LLCPrefData misses from local IA", + "PublicDescription": "TOR Occupancy; Last level cache prefetch data read from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00cd43ff", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "BriefDescription": "TOR Inserts for ItoMCacheNears from IO devices.", + "PublicDescription": "Inserts into the TOR from local IO devices with the opcode ItoMCacheNears. This event indicates a partial write request.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xe0", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL_SCH0", + "BriefDescription": "PMM Read Pending Queue occupancy", + "PublicDescription": "Accumulates the per cycle occupancy of the PMM Read Pending Queue.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xe0", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL_SCH1", + "BriefDescription": "PMM Read Pending Queue occupancy", + "PublicDescription": "Accumulates the per cycle occupancy of the PMM Read Pending Queue.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xe3", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_PMM_RPQ_INSERTS", + "BriefDescription": "PMM Read Pending Queue inserts", + "PublicDescription": "Counts number of read requests allocated in the PMM Read Pending Queue.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xe4", + "UMask": "0x03", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL", + "BriefDescription": "PMM Write Pending Queue Occupancy", + "PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the Write Pending Queue to the PMM DIMM.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xe7", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_PMM_WPQ_INSERTS", + "BriefDescription": "PMM Write Pending Queue inserts", + "PublicDescription": "Counts number of write requests allocated in the PMM Write Pending Queue.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x17", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_RDB_INSERTS.PCH0", + "BriefDescription": "Read Data Buffer Inserts", + "PublicDescription": "Read Data Buffer Inserts", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x17", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_RDB_INSERTS.PCH1", + "BriefDescription": "Read Data Buffer Inserts", + "PublicDescription": "Read Data Buffer Inserts", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xE4", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL_SCH0", + "BriefDescription": "PMM Write Pending Queue Occupancy", + "PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xE4", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL_SCH1", + "BriefDescription": "PMM Write Pending Queue Occupancy", + "PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8168a", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM", + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8170a", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM", + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c81686", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR", + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c81706", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR", + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC23FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI", + "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8C3FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH", + "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8168a", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_PMM", + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8170a", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_PMM", + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c81686", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_DDR", + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c81706", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_DDR", + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8c7ff", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH", + "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores", + "PublicDescription": "TOR Occupancy : CLFlushes issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00cc57ff", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM", + "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores", + "PublicDescription": "TOR Occupancy : SpecItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00cd43fd", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR", + "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00cd43fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR", + "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x1F", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN", + "BriefDescription": "Clean NearMem Read Hit", + "PublicDescription": "Counts clean full line read hits (reads and RFOs).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x1F", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY", + "BriefDescription": "Dirty NearMem Read Hit", + "PublicDescription": "Counts dirty full line read hits (reads and RFOs).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x00", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_CLOCKTICKS_FREERUN", + "BriefDescription": "Free running counter that increments for IIO clocktick", + "PublicDescription": "0", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "FREERUN" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x80", + "PortMask": "0x0001", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0", + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x80", + "PortMask": "0x0002", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1", + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x80", + "PortMask": "0x0004", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2", + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x80", + "PortMask": "0x0008", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3", + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x80", + "PortMask": "0x0010", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4", + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x80", + "PortMask": "0x0020", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5", + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x80", + "PortMask": "0x0040", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6", + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x80", + "PortMask": "0x0080", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7", + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x80", + "PortMask": "0x0001", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0", + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x80", + "PortMask": "0x0002", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1", + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x80", + "PortMask": "0x0004", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2", + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x80", + "PortMask": "0x0008", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3", + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x80", + "PortMask": "0x0010", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4", + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x80", + "PortMask": "0x0020", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5", + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x80", + "PortMask": "0x0040", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6", + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x80", + "PortMask": "0x0080", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7", + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x85", + "UMask": "0x01", + "PortMask": "0x0FFF", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL", + "BriefDescription": "Number requests PCIe makes of the main die : All", + "PublicDescription": "Number requests PCIe makes of the main die : All : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x12", + "UMask": "0x78", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", + "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x11", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "BriefDescription": "Inbound write (fast path) requests received by the IRP.", + "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CXLCM", + "EventCode": "0x01", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CXLCM_CLOCKTICKS", + "BriefDescription": "Counts the number of lfclk ticks", + "PublicDescription": "Counts the number of lfclk ticks", + "Counter": "0,1,2,3,4,5,6,7", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CXLDP", + "EventCode": "0x01", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CXLDP_CLOCKTICKS", + "BriefDescription": "Counts the number of uclk ticks", + "PublicDescription": "Counts the number of uclk ticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x00ff", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS", + "BriefDescription": "Read request for 4 bytes made by IIO Part0-7 to Memory", + "PublicDescription": "Read request for 4 bytes made by IIO Part0-7 to Memory", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x00ff", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS", + "BriefDescription": "Write request of 4 bytes made by IIO Part0-7 to Memory", + "PublicDescription": "Write request of 4 bytes made by IIO Part0-7 to Memory", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "MCHBM", + "EventCode": "0x01", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_MCHBM_CLOCKTICKS", + "BriefDescription": "IMC Clockticks at DCLK frequency", + "PublicDescription": "IMC Clockticks at DCLK frequency", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2HBM", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M2HBM_CLOCKTICKS", + "BriefDescription": "Cycles - at UCLK", + "PublicDescription": "Cycles - at UCLK", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2HBM", + "EventCode": "0x20", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M2HBM_DIRECTORY_LOOKUP.ANY", + "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)", + "PublicDescription": "Counts the number of hit data returns to egress with any directory to non persistent memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2HBM", + "EventCode": "0x20", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M2HBM_DIRECTORY_LOOKUP.STATE_A", + "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)", + "PublicDescription": "Counts the number of hit data returns to egress with directory A to non persistent memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2HBM", + "EventCode": "0x20", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M2HBM_DIRECTORY_LOOKUP.STATE_I", + "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)", + "PublicDescription": "Counts the number of hit data returns to egress with directory I to non persistent memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2HBM", + "EventCode": "0x20", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M2HBM_DIRECTORY_LOOKUP.STATE_S", + "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)", + "PublicDescription": "Counts the number of hit data returns to egress with directory S to non persistent memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2HBM", + "EventCode": "0x21", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000003", + "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.ANY", + "BriefDescription": "Multi-socket cacheline Directory update from/to Any state", + "PublicDescription": "Multi-socket cacheline Directory update from/to Any state", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2HBM", + "EventCode": "0xc0", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00800000", + "EventName": "UNC_M2HBM_CMS_CLOCKTICKS", + "BriefDescription": "CMS Clockticks", + "PublicDescription": "CMS Clockticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8F2FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL", + "BriefDescription": "PCIRDCUR (read) transactions from an IO device that addresses memory on a remote socket", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8F37F", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE", + "BriefDescription": "PCIRDCUR (read) transactions from an IO device that addresses memory on the local socket", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC437F", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE", + "BriefDescription": "ItoM (write) transactions from an IO device that addresses memory on a remote socket", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC42FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL", + "BriefDescription": "ItoM (write) transactions from an IO device that addresses memory on the local socket", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD437F", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE", + "BriefDescription": "ItoMCacheNear (partial write) transactions from an IO device that addresses memory on a remote socket", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD42FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL", + "BriefDescription": "ItoMCacheNear (partial write) transactions from an IO device that addresses memory on the local socket", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + } + ] +} \ No newline at end of file diff --git a/cmd/metrics/resources/perfmon/emr/emr.json b/cmd/metrics/resources/perfmon/emr/emr.json new file mode 100644 index 00000000..1a2b7d6e --- /dev/null +++ b/cmd/metrics/resources/perfmon/emr/emr.json @@ -0,0 +1,1801 @@ +{ + "Header": { + "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", + "Info": "PerfSpect Performance Monitoring Metrics for Intel(R) Xeon(R) 5 Processor (Emerald Rapids)" + }, + "PerfmonMetricsFile": "emeraldrapids_metrics.json", + "PerfmonCoreEventsFile": "emeraldrapids_core.json", + "PerfmonUncoreEventsFile": "emeraldrapids_uncore.json", + "PerfmonRetireLatencyFile": "", + "ReportMetrics": [ + { + "MetricName": "cpu_operating_frequency", + "LegacyName": "metric_CPU operating frequency (in GHz)", + "Origin": "perfmon" + }, + { + "MetricName": "cpu_utilization", + "LegacyName": "metric_CPU utilization %", + "Origin": "perfmon" + }, + { + "MetricName": "cpu_util_kernel", + "LegacyName": "metric_CPU utilization % in kernel mode", + "Origin": "perfspect" + }, + { + "MetricName": "cpi", + "LegacyName": "metric_CPI", + "Origin": "perfmon" + }, + { + "MetricName": "cycles_per_txn", + "LegacyName": "metric_cycles per txn", + "Origin": "perfspect" + }, + { + "MetricName": "kernel_cpi", + "LegacyName": "metric_kernel_CPI", + "Origin": "perfspect" + }, + { + "MetricName": "kernel_cycles_per_txn", + "LegacyName": "metric_kernel_cycles per txn", + "Origin": "perfspect" + }, + { + "MetricName": "ipc", + "LegacyName": "metric_IPC", + "Origin": "perfspect" + }, + { + "MetricName": "giga_instructions_per_sec", + "LegacyName": "metric_giga_instructions_per_sec", + "Origin": "perfspect" + }, + { + "MetricName": "branch_misprediction_ratio", + "LegacyName": "metric_branch misprediction ratio", + "Origin": "perfspect" + }, + { + "MetricName": "locks_retired_per_instr", + "LegacyName": "metric_locks retired per instr", + "Origin": "perfspect" + }, + { + "MetricName": "locks_retired_per_txn", + "LegacyName": "metric_locks retired per txn", + "Origin": "perfspect" + }, + { + "MetricName": "l1d_mpi", + "LegacyName": "metric_L1D MPI (includes data+rfo w/ prefetches)", + "Origin": "perfmon" + }, + { + "MetricName": "l1d_misses_per_txn", + "LegacyName": "metric_L1D misses per txn (includes data+rfo w/ prefetches)", + "Origin": "perfspect" + }, + { + "MetricName": "l1d_demand_data_read_hits_per_instr", + "LegacyName": "metric_L1D demand data read hits per instr", + "Origin": "perfmon" + }, + { + "MetricName": "l1d_demand_data_read_hits_per_txn", + "LegacyName": "metric_L1D demand data read hits per txn", + "Origin": "perfspect" + }, + { + "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", + "LegacyName": "metric_L1-I code read misses (w/ prefetches) per instr", + "Origin": "perfmon" + }, + { + "MetricName": "l1i_code_read_misses_per_txn", + "LegacyName": "metric_L1I code read misses (includes prefetches) per txn", + "Origin": "perfspect" + }, + { + "MetricName": "l2_demand_data_read_hits_per_instr", + "LegacyName": "metric_L2 demand data read hits per instr", + "Origin": "perfmon" + }, + { + "MetricName": "l2_demand_data_read_hits_per_txn", + "LegacyName": "metric_L2 demand data read hits per txn", + "Origin": "perfspect" + }, + { + "MetricName": "l2_mpi", + "LegacyName": "metric_L2 MPI (includes code+data+rfo w/ prefetches)", + "Origin": "perfmon" + }, + { + "MetricName": "l2_misses_per_txn", + "LegacyName": "metric_L2 misses per txn (includes code+data+rfo w/ prefetches)", + "Origin": "perfspect" + }, + { + "MetricName": "l2_demand_data_read_mpi", + "LegacyName": "metric_L2 demand data read MPI", + "Origin": "perfmon" + }, + { + "MetricName": "l2_demand_data_read_misses_per_txn", + "LegacyName": "metric_L2 demand data read misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "l2_demand_code_mpi", + "LegacyName": "metric_L2 demand code MPI", + "Origin": "perfmon" + }, + { + "MetricName": "l2_demand_code_misses_per_txn", + "LegacyName": "metric_L2 demand code misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "llc_code_read_mpi_demand_plus_prefetch", + "LegacyName": "metric_LLC code read MPI (demand+prefetch)", + "Origin": "perfmon" + }, + { + "MetricName": "llc_code_read_misses_per_txn", + "LegacyName": "metric_LLC code read (demand+prefetch) misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "llc_data_read_mpi_demand_plus_prefetch", + "LegacyName": "metric_LLC data read MPI (demand+prefetch)", + "Origin": "perfmon" + }, + { + "MetricName": "llc_data_read_misses_per_txn", + "LegacyName": "metric_LLC data read (demand+prefetch) misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "llc_demand_data_read_miss_latency", + "LegacyName": "metric_Average LLC demand data read miss latency (in ns)", + "Origin": "perfmon" + }, + { + "MetricName": "llc_demand_data_read_miss_latency_for_local_requests", + "LegacyName": "metric_Average LLC demand data read miss latency for LOCAL requests (in ns)", + "Origin": "perfmon" + }, + { + "MetricName": "llc_demand_data_read_miss_latency_for_remote_requests", + "LegacyName": "metric_Average LLC demand data read miss latency for REMOTE requests (in ns)", + "Origin": "perfmon" + }, + { + "MetricName": "upi_data_transmit_bw", + "LegacyName": "metric_UPI Data transmit BW (MB/sec) (only data)", + "Origin": "perfmon" + }, + { + "MetricName": "package_power", + "LegacyName": "metric_package power (watts)", + "Origin": "perfspect" + }, + { + "MetricName": "dram_power", + "LegacyName": "metric_DRAM power (watts)", + "Origin": "perfspect" + }, + { + "MetricName": "core_c6_residency", + "LegacyName": "metric_core c6 residency %", + "Origin": "perfspect" + }, + { + "MetricName": "package_c6_residency", + "LegacyName": "metric_package c6 residency %", + "Origin": "perfspect" + }, + { + "MetricName": "percent_uops_delivered_from_decoded_icache", + "LegacyName": "metric_% Uops delivered from decoded Icache (DSB)", + "Origin": "perfmon" + }, + { + "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline", + "LegacyName": "metric_% Uops delivered from legacy decode pipeline (MITE)", + "Origin": "perfmon" + }, + { + "MetricName": "memory_bandwidth_read", + "LegacyName": "metric_memory bandwidth read (MB/sec)", + "Origin": "perfmon" + }, + { + "MetricName": "memory_bandwidth_write", + "LegacyName": "metric_memory bandwidth write (MB/sec)", + "Origin": "perfmon" + }, + { + "MetricName": "memory_bandwidth_total", + "LegacyName": "metric_memory bandwidth total (MB/sec)", + "Origin": "perfmon" + }, + { + "MetricName": "itlb_2nd_level_mpi", + "LegacyName": "metric_ITLB (2nd level) MPI", + "Origin": "perfmon" + }, + { + "MetricName": "itlb_misses_per_txn", + "LegacyName": "metric_ITLB (2nd level) misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "dtlb_2nd_level_load_mpi", + "LegacyName": "metric_DTLB (2nd level) load MPI", + "Origin": "perfmon" + }, + { + "MetricName": "dtlb_load_misses_per_txn", + "LegacyName": "metric_DTLB (2nd level) load misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "dtlb_2nd_level_store_mpi", + "LegacyName": "metric_DTLB (2nd level) store MPI", + "Origin": "perfmon" + }, + { + "MetricName": "dtlb_store_misses_per_txn", + "LegacyName": "metric_DTLB (2nd level) store misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "numa_reads_addressed_to_local_dram", + "LegacyName": "metric_NUMA %_Reads addressed to local DRAM", + "Origin": "perfmon" + }, + { + "MetricName": "numa_reads_addressed_to_remote_dram", + "LegacyName": "metric_NUMA %_Reads addressed to remote DRAM", + "Origin": "perfmon" + }, + { + "MetricName": "uncore_frequency", + "LegacyName": "metric_uncore frequency GHz", + "Origin": "perfmon" + }, + { + "MetricName": "io_bandwidth_write", + "LegacyName": "metric_IO_bandwidth_disk_or_network_writes (MB/sec)", + "Origin": "perfmon" + }, + { + "MetricName": "io_bandwidth_read", + "LegacyName": "metric_IO_bandwidth_disk_or_network_reads (MB/sec)", + "Origin": "perfmon" + }, + { + "MetricName": "Frontend_Bound", + "LegacyName": "metric_TMA_Frontend_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Fetch_Latency", + "LegacyName": "metric_TMA_..Fetch_Latency(%)", + "Origin": "perfmon" + }, + { + "MetricName": "ICache_Misses", + "LegacyName": "metric_TMA_....ICache_Misses(%)", + "Origin": "perfmon" + }, + { + "MetricName": "ITLB_Misses", + "LegacyName": "metric_TMA_....ITLB_Misses(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Branch_Resteers", + "LegacyName": "metric_TMA_....Branch_Resteers(%)", + "Origin": "perfmon" + }, + { + "MetricName": "MS_Switches", + "LegacyName": "metric_TMA_....MS_Switches(%)", + "Origin": "perfmon" + }, + { + "MetricName": "LCP", + "LegacyName": "metric_TMA_....LCP(%)", + "Origin": "perfmon" + }, + { + "MetricName": "DSB_Switches", + "LegacyName": "metric_TMA_....DSB_Switches(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Fetch_Bandwidth", + "LegacyName": "metric_TMA_..Fetch_Bandwidth(%)", + "Origin": "perfmon" + }, + { + "MetricName": "MITE", + "LegacyName": "metric_TMA_....MITE(%)", + "Origin": "perfmon" + }, + { + "MetricName": "DSB", + "LegacyName": "metric_TMA_....DSB(%)", + "Origin": "perfmon" + }, + { + "MetricName": "MS", + "LegacyName": "metric_TMA_....MS(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Bad_Speculation", + "LegacyName": "metric_TMA_Bad_Speculation(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Branch_Mispredicts", + "LegacyName": "metric_TMA_..Branch_Mispredicts(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Other_Mispredicts", + "LegacyName": "metric_TMA_....Other_Mispredicts(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Machine_Clears", + "LegacyName": "metric_TMA_..Machine_Clears(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Other_Nukes", + "LegacyName": "metric_TMA_....Other_Nukes(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Backend_Bound", + "LegacyName": "metric_TMA_Backend_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Memory_Bound", + "LegacyName": "metric_TMA_..Memory_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "L1_Bound", + "LegacyName": "metric_TMA_....L1_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "DTLB_Load", + "LegacyName": "metric_TMA_......DTLB_Load(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Store_Fwd_Blk", + "LegacyName": "metric_TMA_......Store_Fwd_Blk(%)", + "Origin": "perfmon" + }, + { + "MetricName": "L1_Latency_Dependency", + "LegacyName": "metric_TMA_......L1_Latency_Dependency(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Lock_Latency", + "LegacyName": "metric_TMA_......Lock_Latency(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Split_Loads", + "LegacyName": "metric_TMA_......Split_Loads(%)", + "Origin": "perfmon" + }, + { + "MetricName": "FB_Full", + "LegacyName": "metric_TMA_......FB_Full(%)", + "Origin": "perfmon" + }, + { + "MetricName": "L2_Bound", + "LegacyName": "metric_TMA_....L2_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "L3_Bound", + "LegacyName": "metric_TMA_....L3_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Contested_Accesses", + "LegacyName": "metric_TMA_......Contested_Accesses(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Data_Sharing", + "LegacyName": "metric_TMA_......Data_Sharing(%)", + "Origin": "perfmon" + }, + { + "MetricName": "L3_Hit_Latency", + "LegacyName": "metric_TMA_......L3_Hit_Latency(%)", + "Origin": "perfmon" + }, + { + "MetricName": "SQ_Full", + "LegacyName": "metric_TMA_......SQ_Full(%)", + "Origin": "perfmon" + }, + { + "MetricName": "DRAM_Bound", + "LegacyName": "metric_TMA_....DRAM_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "MEM_Bandwidth", + "LegacyName": "metric_TMA_......MEM_Bandwidth(%)", + "Origin": "perfmon" + }, + { + "MetricName": "MEM_Latency", + "LegacyName": "metric_TMA_......MEM_Latency(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Store_Bound", + "LegacyName": "metric_TMA_....Store_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Store_Latency", + "LegacyName": "metric_TMA_......Store_Latency(%)", + "Origin": "perfmon" + }, + { + "MetricName": "False_Sharing", + "LegacyName": "metric_TMA_......False_Sharing(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Split_Stores", + "LegacyName": "metric_TMA_......Split_Stores(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Streaming_Stores", + "LegacyName": "metric_TMA_......Streaming_Stores(%)", + "Origin": "perfmon" + }, + { + "MetricName": "DTLB_Store", + "LegacyName": "metric_TMA_......DTLB_Store(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Core_Bound", + "LegacyName": "metric_TMA_..Core_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Divider", + "LegacyName": "metric_TMA_....Divider(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Serializing_Operation", + "LegacyName": "metric_TMA_....Serializing_Operation(%)", + "Origin": "perfmon" + }, + { + "MetricName": "AMX_Busy", + "LegacyName": "metric_TMA_....AMX_Busy(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Ports_Utilization", + "LegacyName": "metric_TMA_....Ports_Utilization(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Retiring", + "LegacyName": "metric_TMA_Retiring(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Light_Operations", + "LegacyName": "metric_TMA_..Light_Operations(%)", + "Origin": "perfmon" + }, + { + "MetricName": "FP_Arith", + "LegacyName": "metric_TMA_....FP_Arith(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Int_Operations", + "LegacyName": "metric_TMA_....Int_Operations(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Memory_Operations", + "LegacyName": "metric_TMA_....Memory_Operations(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Fused_Instructions", + "LegacyName": "metric_TMA_....Fused_Instructions(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Non_Fused_Branches", + "LegacyName": "metric_TMA_....Non_Fused_Branches(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Other_Light_Ops", + "LegacyName": "metric_TMA_....Other_Light_Ops(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Heavy_Operations", + "LegacyName": "metric_TMA_..Heavy_Operations(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Few_Uops_Instructions", + "LegacyName": "metric_TMA_....Few_Uops_Instructions(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Microcode_Sequencer", + "LegacyName": "metric_TMA_....Microcode_Sequencer(%)", + "Origin": "perfmon" + } +], + "Metrics": [ + { + "MetricName": "cpu_util_kernel", + "LegacyName": "metric_CPU utilization % in kernel mode", + "BriefDescription": "CPU utilization percentage in kernel mode", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + }, + { + "Name": "TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * (a / b)", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "cycles_per_txn", + "LegacyName": "metric_cycles per txn", + "BriefDescription": "Number of cycles per transaction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "kernel_cpi", + "LegacyName": "metric_kernel_CPI", + "BriefDescription": "Kernel cycles per instruction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "kernel_cycles_per_txn", + "LegacyName": "metric_kernel_cycles per txn", + "BriefDescription": "Number of kernel cycles per transaction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "ipc", + "LegacyName": "metric_IPC", + "BriefDescription": "Instructions per cycle", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "giga_instructions_per_sec", + "LegacyName": "metric_giga_instructions_per_sec", + "BriefDescription": "Billions of instructions per second", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + } + ], + "Constants": [ + ], + "Formula": "a / 1000000000", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "branch_misprediction_ratio", + "LegacyName": "metric_branch misprediction ratio", + "BriefDescription": "Ratio of branch mispredictions to the total number of branches retired.", + "Events": [ + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "locks_retired_per_instr", + "LegacyName": "metric_locks retired per instr", + "BriefDescription": "Locks retired per instruction", + "Events": [ + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "locks_retired_per_txn", + "LegacyName": "metric_locks retired per txn", + "BriefDescription": "Locks retired per transaction", + "Events": [ + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l1d_misses_per_txn", + "LegacyName": "metric_L1D misses per txn (includes data+rfo w/ prefetches)", + "BriefDescription": "L1D misses per transaction (includes data+rfo with prefetches)", + "Events": [ + { + "Name": "L1D.REPLACEMENT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l1d_demand_data_read_hits_per_txn", + "LegacyName": "metric_L1D demand data read hits per txn", + "BriefDescription": "L1D demand data read hits per transaction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L1_HIT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l1i_code_read_misses_per_txn", + "LegacyName": "metric_L1I code read misses (includes prefetches) per txn", + "BriefDescription": "L1I code read misses (includes prefetches) per transaction", + "Events": [ + { + "Name": "L2_RQSTS.ALL_CODE_RD", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l2_demand_data_read_hits_per_txn", + "LegacyName": "metric_L2 demand data read hits per txn", + "BriefDescription": "L2 demand data read hits per transaction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_HIT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l2_misses_per_txn", + "LegacyName": "metric_L2 misses per txn (includes code+data+rfo w/ prefetches)", + "BriefDescription": "L2 misses per transaction (includes code+data+rfo with prefetches)", + "Events": [ + { + "Name": "L2_LINES_IN.ALL", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l2_demand_data_read_misses_per_txn", + "LegacyName": "metric_L2 demand data read misses per txn", + "BriefDescription": "L2 demand data read misses per transaction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l2_demand_code_misses_per_txn", + "LegacyName": "metric_L2 demand code misses per txn", + "BriefDescription": "L2 demand code misses per transaction", + "Events": [ + { + "Name": "L2_RQSTS.CODE_RD_MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "llc_code_read_misses_per_txn", + "LegacyName": "metric_LLC code read (demand+prefetch) misses per txn", + "BriefDescription": "LLC code read (demand+prefetch) misses per transaction", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "llc_data_read_misses_per_txn", + "LegacyName": "metric_LLC data read (demand+prefetch) misses per txn", + "BriefDescription": "LLC data read (demand+prefetch) misses per transaction", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "d" + } + ], + "Formula": "(a + b + c) / d", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "package_power", + "LegacyName": "metric_package power (watts)", + "BriefDescription": "Package power consumption in watts", + "Events": [ + { + "Name": "power/energy-pkg/", + "Alias": "a" + } + ], + "Constants": [ + ], + "Formula": "a", + "ResolutionLevels": "SOCKET, SYSTEM" + }, + { + "MetricName": "dram_power", + "LegacyName": "metric_DRAM power (watts)", + "BriefDescription": "DRAM power consumption in watts", + "Events": [ + { + "Name": "power/energy-ram/", + "Alias": "a" + } + ], + "Constants": [ + ], + "Formula": "a", + "ResolutionLevels": "SOCKET, SYSTEM" + }, + { + "MetricName": "core_c6_residency", + "LegacyName": "metric_core c6 residency %", + "BriefDescription": "Core C6 state residency percentage", + "Events": [ + { + "Name": "cstate_core/c6-residency/", + "Alias": "a" + }, + { + "Name": "TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "ResolutionLevels": "CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "package_c6_residency", + "LegacyName": "metric_package c6 residency %", + "BriefDescription": "Package C6 state residency percentage", + "Events": [ + { + "Name": "cstate_pkg/c6-residency/", + "Alias": "a" + }, + { + "Name": "TSC", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "CORES_PER_SOCKET", + "Alias": "c" + } + ], + "Formula": "100 * a * c / b", + "ResolutionLevels": "SOCKET, SYSTEM" + }, + { + "MetricName": "itlb_misses_per_txn", + "LegacyName": "metric_ITLB (2nd level) misses per txn", + "BriefDescription": "ITLB (2nd level) misses per transaction", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "dtlb_load_misses_per_txn", + "LegacyName": "metric_DTLB (2nd level) load misses per txn", + "BriefDescription": "DTLB (2nd level) load misses per transaction", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "dtlb_store_misses_per_txn", + "LegacyName": "metric_DTLB (2nd level) store misses per txn", + "BriefDescription": "DTLB (2nd level) store misses per transaction", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + } + ], + "AlternateTMAMetrics": [ + { + "MetricName": "Frontend_Bound", + "LegacyName": "metric_TMA_Frontend_Bound(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ_BUBBLES.CORE", + "Alias": "a" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a - b ) / c )", + "BaseFormula": "100 * ( ( [IDQ_BUBBLES.CORE] - [INT_MISC.UOP_DROPPING] ) / [TOPDOWN.SLOTS_P] )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 15", + "BaseFormula": "metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvFB;BvIO;TmaL1;PGO", + "LocateWith": " FRONTEND_RETIRED.LATENCY_GE_4" + }, + { + "MetricName": "Fetch_Latency", + "LegacyName": "metric_TMA_..Fetch_Latency(%)", + "ParentCategory": "Frontend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "a" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a * ( 6 ) - b ) / c )", + "BaseFormula": " ( 100 * ( ( [IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE] * ( 6 ) - [INT_MISC.UOP_DROPPING] ) / [TOPDOWN.SLOTS_P] ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 15", + "BaseFormula": "metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Frontend;TmaL2", + "LocateWith": " FRONTEND_RETIRED.LATENCY_GE_16;FRONTEND_RETIRED.LATENCY_GE_8" + }, + { + "MetricName": "Fetch_Bandwidth", + "LegacyName": "metric_TMA_..Fetch_Bandwidth(%)", + "ParentCategory": "Frontend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CORE", + "Alias": "a" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "c" + }, + { + "Name": "IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( ( a - b ) / ( c ) ) - ( ( d * ( 6 ) - b ) / ( c ) ) ) )", + "BaseFormula": "max( 0 , tma_frontend_bound - tma_fetch_latency )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Fetch_Bandwidth(%)" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_..Fetch_Bandwidth(%) > 20", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchBW;Frontend;TmaL2", + "LocateWith": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1;FRONTEND_RETIRED.LATENCY_GE_1;FRONTEND_RETIRED.LATENCY_GE_2" + }, + { + "MetricName": "Bad_Speculation", + "LegacyName": "metric_TMA_Bad_Speculation(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ_BUBBLES.CORE", + "Alias": "a" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "c" + }, + { + "Name": "TOPDOWN.BACKEND_BOUND_SLOTS", + "Alias": "d" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( max( 1 - ( ( ( a - b ) / c ) + ( d / c ) + ( e / c ) ) , 0 ) )", + "BaseFormula": " 100 * ( max( 1 - ( ( ( [IDQ_BUBBLES.CORE] - [INT_MISC.UOP_DROPPING] ) / [TOPDOWN.SLOTS_P] ) + ( [TOPDOWN.BACKEND_BOUND_SLOTS] / [TOPDOWN.SLOTS_P] ) + ( [UOPS_RETIRED.SLOTS] / [TOPDOWN.SLOTS_P] ) ) , 0 ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 15", + "BaseFormula": "metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "TmaL1", + "LocateWith": "#NA" + }, + { + "MetricName": "Branch_Mispredicts", + "LegacyName": "metric_TMA_..Branch_Mispredicts(%)", + "ParentCategory": "Bad_Speculation", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN.BR_MISPREDICT_SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "perf_metrics.branch_mispredicts / ( perf_metrics.frontend_bound + perf_metrics.bad_speculation + perf_metrics.retiring + perf_metrics.backend_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Branch_Mispredicts(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 10 & b > 15", + "BaseFormula": "metric_TMA_..Branch_Mispredicts(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "$issueBM" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2", + "LocateWith": "TOPDOWN.BR_MISPREDICT_SLOTS" + }, + { + "MetricName": "Machine_Clears", + "LegacyName": "metric_TMA_..Machine_Clears(%)", + "ParentCategory": "Bad_Speculation", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CORE", + "Alias": "a" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "c" + }, + { + "Name": "TOPDOWN.BACKEND_BOUND_SLOTS", + "Alias": "d" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "e" + }, + { + "Name": "TOPDOWN.BR_MISPREDICT_SLOTS", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( max( 1 - ( ( ( a - b ) / ( c ) ) + ( d / ( c ) ) + ( e / ( c ) ) ) , 0 ) ) - ( f / ( c ) ) ) )", + "BaseFormula": "max( 0 , tma_bad_speculation - tma_branch_mispredicts )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Machine_Clears(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 10 & b > 15", + "BaseFormula": "metric_TMA_..Machine_Clears(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "$issueMC, $issueSyncxn" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2", + "LocateWith": "MACHINE_CLEARS.COUNT" + }, + { + "MetricName": "Backend_Bound", + "LegacyName": "metric_TMA_Backend_Bound(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN.BACKEND_BOUND_SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / b )", + "BaseFormula": " 100 * ( [TOPDOWN.BACKEND_BOUND_SLOTS] / [TOPDOWN.SLOTS_P] )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvOB;TmaL1", + "LocateWith": " TOPDOWN.BACKEND_BOUND_SLOTS" + }, + { + "MetricName": "Memory_Bound", + "LegacyName": "metric_TMA_..Memory_Bound(%)", + "ParentCategory": "Backend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN.MEMORY_BOUND_SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / b )", + "BaseFormula": " 100 * ( [TOPDOWN.MEMORY_BOUND_SLOTS] / [TOPDOWN.SLOTS_P] )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20", + "BaseFormula": "metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Backend;TmaL2", + "LocateWith": "#NA" + }, + { + "MetricName": "Core_Bound", + "LegacyName": "metric_TMA_..Core_Bound(%)", + "ParentCategory": "Backend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN.BACKEND_BOUND_SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + }, + { + "Name": "TOPDOWN.MEMORY_BOUND_SLOTS", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b ) ) - ( c / ( b ) ) ) )", + "BaseFormula": "max( 0 , tma_backend_bound - tma_memory_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 20", + "BaseFormula": "metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Backend;TmaL2;Compute", + "LocateWith": "" + }, + { + "MetricName": "Retiring", + "LegacyName": "metric_TMA_Retiring(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / b )", + "BaseFormula": " 100 * ( [UOPS_RETIRED.SLOTS] / [TOPDOWN.SLOTS_P] )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Retiring(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 70 | b > 10", + "BaseFormula": "metric_TMA_Retiring(%) > 70 | metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvUW;TmaL1", + "LocateWith": " UOPS_RETIRED.SLOTS" + }, + { + "MetricName": "Light_Operations", + "LegacyName": "metric_TMA_..Light_Operations(%)", + "ParentCategory": "Retiring", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations , instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + }, + { + "Name": "UOPS_RETIRED.HEAVY", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b ) ) - ( c / ( b ) ) ) )", + "BaseFormula": "max( 0 , tma_retiring - tma_heavy_operations )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Retire;TmaL2", + "LocateWith": "INST_RETIRED.PREC_DIST" + }, + { + "MetricName": "Memory_Operations", + "LegacyName": "metric_TMA_....Memory_Operations(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations , uops for memory load or store accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + }, + { + "Name": "UOPS_RETIRED.HEAVY", + "Alias": "c" + }, + { + "Name": "MEM_UOP_RETIRED.ANY", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b ) ) - ( c / ( b ) ) ) ) * d / ( ( a / ( b ) ) * ( b ) ) )", + "BaseFormula": "tma_light_operations * mem_uop_retired.any / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Memory_Operations(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 60", + "BaseFormula": "metric_TMA_....Memory_Operations(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Fused_Instructions", + "LegacyName": "metric_TMA_....Fused_Instructions(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions , where one uop can represent multiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Other_Light_Ops in MTL!)}", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + }, + { + "Name": "UOPS_RETIRED.HEAVY", + "Alias": "c" + }, + { + "Name": "INST_RETIRED.MACRO_FUSED", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b ) ) - ( c / ( b ) ) ) ) * d / ( ( a / ( b ) ) * ( b ) ) )", + "BaseFormula": "tma_light_operations * inst_retired.macro_fused / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Fused_Instructions(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 60", + "BaseFormula": "metric_TMA_....Fused_Instructions(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;BvBO;Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Non_Fused_Branches", + "LegacyName": "metric_TMA_....Non_Fused_Branches(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + }, + { + "Name": "UOPS_RETIRED.HEAVY", + "Alias": "c" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "d" + }, + { + "Name": "INST_RETIRED.MACRO_FUSED", + "Alias": "e" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "f" + }, + { + "Name": "INST_RETIRED.MACRO_FUSED", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b ) ) - ( c / ( b ) ) ) ) * ( d - e ) / ( ( a / ( b ) ) * ( b ) ) )", + "BaseFormula": "tma_light_operations * ( br_inst_retired.all_branches - inst_retired.macro_fused ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Non_Fused_Branches(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 60", + "BaseFormula": "metric_TMA_....Non_Fused_Branches(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;BvBO;Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Heavy_Operations", + "LegacyName": "metric_TMA_..Heavy_Operations(%)", + "ParentCategory": "Retiring", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations , instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.([ICL+] Note this may overcount due to approximation using indirect events; [ADL+])", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.HEAVY", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / b )", + "BaseFormula": " 100 * ( [UOPS_RETIRED.HEAVY] / [TOPDOWN.SLOTS_P] )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Retire;TmaL2", + "LocateWith": " UOPS_RETIRED.HEAVY" + }, + { + "MetricName": "Few_Uops_Instructions", + "LegacyName": "metric_TMA_....Few_Uops_Instructions(%)", + "ParentCategory": "Heavy_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or more uops. This highly-correlates with the number of uops in such instructions.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.HEAVY", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + }, + { + "Name": "UOPS_RETIRED.MS", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b ) ) - ( c / ( b ) ) ) )", + "BaseFormula": "max( 0 , tma_heavy_operations - tma_microcode_sequencer )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Few_Uops_Instructions(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 5 & b > 10", + "BaseFormula": "metric_TMA_....Few_Uops_Instructions(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "$issueD0" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "Microcode_Sequencer", + "LegacyName": "metric_TMA_....Microcode_Sequencer(%)", + "ParentCategory": "Heavy_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.MS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "uops_retired.ms / tma_info_thread_slots", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Microcode_Sequencer(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 5 & b > 10", + "BaseFormula": "metric_TMA_....Microcode_Sequencer(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "$issueMC, $issueMS" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq", + "LocateWith": "UOPS_RETIRED.MS" + } + ] +} diff --git a/cmd/metrics/resources/perfmon/gnr/gnr.json b/cmd/metrics/resources/perfmon/gnr/gnr.json new file mode 100644 index 00000000..fa6aaedd --- /dev/null +++ b/cmd/metrics/resources/perfmon/gnr/gnr.json @@ -0,0 +1,1826 @@ +{ + "Header": { + "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", + "Info": "PerfSpect Performance Monitoring Metrics for Intel(R) Xeon(R) 6 Processor with P-cores (Granite Rapids)" + }, + "PerfmonMetricsFile": "graniterapids_metrics.json", + "PerfmonCoreEventsFile": "graniterapids_core.json", + "PerfmonUncoreEventsFile": "graniterapids_uncore.json", + "PerfmonRetireLatencyFile": "graniterapids_retire_latency.json", + "ReportMetrics": [ + { + "MetricName": "cpu_operating_frequency", + "LegacyName": "metric_CPU operating frequency (in GHz)", + "Origin": "perfmon" + }, + { + "MetricName": "cpu_utilization", + "LegacyName": "metric_CPU utilization %", + "Origin": "perfmon" + }, + { + "MetricName": "cpu_util_kernel", + "LegacyName": "metric_CPU utilization % in kernel mode", + "Origin": "perfspect" + }, + { + "MetricName": "cpi", + "LegacyName": "metric_CPI", + "Origin": "perfmon" + }, + { + "MetricName": "cycles_per_txn", + "LegacyName": "metric_cycles per txn", + "Origin": "perfspect" + }, + { + "MetricName": "kernel_cpi", + "LegacyName": "metric_kernel_CPI", + "Origin": "perfspect" + }, + { + "MetricName": "kernel_cycles_per_txn", + "LegacyName": "metric_kernel_cycles per txn", + "Origin": "perfspect" + }, + { + "MetricName": "ipc", + "LegacyName": "metric_IPC", + "Origin": "perfspect" + }, + { + "MetricName": "giga_instructions_per_sec", + "LegacyName": "metric_giga_instructions_per_sec", + "Origin": "perfspect" + }, + { + "MetricName": "branch_misprediction_ratio", + "LegacyName": "metric_branch misprediction ratio", + "Origin": "perfspect" + }, + { + "MetricName": "locks_retired_per_instr", + "LegacyName": "metric_locks retired per instr", + "Origin": "perfspect" + }, + { + "MetricName": "locks_retired_per_txn", + "LegacyName": "metric_locks retired per txn", + "Origin": "perfspect" + }, + { + "MetricName": "l1d_mpi", + "LegacyName": "metric_L1D MPI (includes data+rfo w/ prefetches)", + "Origin": "perfmon" + }, + { + "MetricName": "l1d_misses_per_txn", + "LegacyName": "metric_L1D misses per txn (includes data+rfo w/ prefetches)", + "Origin": "perfspect" + }, + { + "MetricName": "l1d_demand_data_read_hits_per_instr", + "LegacyName": "metric_L1D demand data read hits per instr", + "Origin": "perfmon" + }, + { + "MetricName": "l1d_demand_data_read_hits_per_txn", + "LegacyName": "metric_L1D demand data read hits per txn", + "Origin": "perfspect" + }, + { + "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", + "LegacyName": "metric_L1-I code read misses (w/ prefetches) per instr", + "Origin": "perfmon" + }, + { + "MetricName": "l1i_code_read_misses_per_txn", + "LegacyName": "metric_L1I code read misses (includes prefetches) per txn", + "Origin": "perfspect" + }, + { + "MetricName": "l2_demand_data_read_hits_per_instr", + "LegacyName": "metric_L2 demand data read hits per instr", + "Origin": "perfmon" + }, + { + "MetricName": "l2_demand_data_read_hits_per_txn", + "LegacyName": "metric_L2 demand data read hits per txn", + "Origin": "perfspect" + }, + { + "MetricName": "l2_mpi", + "LegacyName": "metric_L2 MPI (includes code+data+rfo w/ prefetches)", + "Origin": "perfmon" + }, + { + "MetricName": "l2_misses_per_txn", + "LegacyName": "metric_L2 misses per txn (includes code+data+rfo w/ prefetches)", + "Origin": "perfspect" + }, + { + "MetricName": "l2_demand_data_read_mpi", + "LegacyName": "metric_L2 demand data read MPI", + "Origin": "perfmon" + }, + { + "MetricName": "l2_demand_data_read_misses_per_txn", + "LegacyName": "metric_L2 demand data read misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "l2_demand_code_mpi", + "LegacyName": "metric_L2 demand code MPI", + "Origin": "perfmon" + }, + { + "MetricName": "l2_demand_code_misses_per_txn", + "LegacyName": "metric_L2 demand code misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "llc_code_read_mpi_demand_plus_prefetch", + "LegacyName": "metric_LLC code read MPI (demand+prefetch)", + "Origin": "perfmon" + }, + { + "MetricName": "llc_code_read_misses_per_txn", + "LegacyName": "metric_LLC code read (demand+prefetch) misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "llc_data_read_mpi_demand_plus_prefetch", + "LegacyName": "metric_LLC data read MPI (demand+prefetch)", + "Origin": "perfmon" + }, + { + "MetricName": "llc_data_read_misses_per_txn", + "LegacyName": "metric_LLC data read (demand+prefetch) misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "llc_demand_data_read_miss_latency", + "LegacyName": "metric_Average LLC demand data read miss latency (in ns)", + "Origin": "perfmon" + }, + { + "MetricName": "llc_demand_data_read_miss_latency_for_local_requests", + "LegacyName": "metric_Average LLC demand data read miss latency for LOCAL requests (in ns)", + "Origin": "perfmon" + }, + { + "MetricName": "llc_demand_data_read_miss_latency_for_remote_requests", + "LegacyName": "metric_Average LLC demand data read miss latency for REMOTE requests (in ns)", + "Origin": "perfmon" + }, + { + "MetricName": "upi_data_transmit_bw", + "LegacyName": "metric_UPI Data transmit BW (MB/sec) (only data)", + "Origin": "perfmon" + }, + { + "MetricName": "package_power", + "LegacyName": "metric_package power (watts)", + "Origin": "perfspect" + }, + { + "MetricName": "dram_power", + "LegacyName": "metric_DRAM power (watts)", + "Origin": "perfspect" + }, + { + "MetricName": "core_c6_residency", + "LegacyName": "metric_core c6 residency %", + "Origin": "perfspect" + }, + { + "MetricName": "package_c6_residency", + "LegacyName": "metric_package c6 residency %", + "Origin": "perfspect" + }, + { + "MetricName": "percent_uops_delivered_from_decoded_icache", + "LegacyName": "metric_% Uops delivered from decoded Icache (DSB)", + "Origin": "perfmon" + }, + { + "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline", + "LegacyName": "metric_% Uops delivered from legacy decode pipeline (MITE)", + "Origin": "perfmon" + }, + { + "MetricName": "memory_bandwidth_read", + "LegacyName": "metric_memory bandwidth read (MB/sec)", + "Origin": "perfmon" + }, + { + "MetricName": "memory_bandwidth_write", + "LegacyName": "metric_memory bandwidth write (MB/sec)", + "Origin": "perfmon" + }, + { + "MetricName": "memory_bandwidth_total", + "LegacyName": "metric_memory bandwidth total (MB/sec)", + "Origin": "perfmon" + }, + { + "MetricName": "itlb_2nd_level_mpi", + "LegacyName": "metric_ITLB (2nd level) MPI", + "Origin": "perfmon" + }, + { + "MetricName": "itlb_misses_per_txn", + "LegacyName": "metric_ITLB (2nd level) misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "dtlb_2nd_level_load_mpi", + "LegacyName": "metric_DTLB (2nd level) load MPI", + "Origin": "perfmon" + }, + { + "MetricName": "dtlb_load_misses_per_txn", + "LegacyName": "metric_DTLB (2nd level) load misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "dtlb_2nd_level_store_mpi", + "LegacyName": "metric_DTLB (2nd level) store MPI", + "Origin": "perfmon" + }, + { + "MetricName": "dtlb_store_misses_per_txn", + "LegacyName": "metric_DTLB (2nd level) store misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "numa_reads_addressed_to_local_dram", + "LegacyName": "metric_NUMA %_Reads addressed to local DRAM", + "Origin": "perfmon" + }, + { + "MetricName": "numa_reads_addressed_to_remote_dram", + "LegacyName": "metric_NUMA %_Reads addressed to remote DRAM", + "Origin": "perfmon" + }, + { + "MetricName": "uncore_frequency", + "LegacyName": "metric_uncore frequency GHz", + "Origin": "perfmon" + }, + { + "MetricName": "io_bandwidth_write", + "LegacyName": "metric_IO_bandwidth_disk_or_network_writes (MB/sec)", + "Origin": "perfmon" + }, + { + "MetricName": "io_bandwidth_read", + "LegacyName": "metric_IO_bandwidth_disk_or_network_reads (MB/sec)", + "Origin": "perfmon" + }, + { + "MetricName": "Frontend_Bound", + "LegacyName": "metric_TMA_Frontend_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Fetch_Latency", + "LegacyName": "metric_TMA_..Fetch_Latency(%)", + "Origin": "perfmon" + }, + { + "MetricName": "ICache_Misses", + "LegacyName": "metric_TMA_....ICache_Misses(%)", + "Origin": "perfmon" + }, + { + "MetricName": "ITLB_Misses", + "LegacyName": "metric_TMA_....ITLB_Misses(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Branch_Resteers", + "LegacyName": "metric_TMA_....Branch_Resteers(%)", + "Origin": "perfmon" + }, + { + "MetricName": "MS_Switches", + "LegacyName": "metric_TMA_....MS_Switches(%)", + "Origin": "perfmon" + }, + { + "MetricName": "LCP", + "LegacyName": "metric_TMA_....LCP(%)", + "Origin": "perfmon" + }, + { + "MetricName": "DSB_Switches", + "LegacyName": "metric_TMA_....DSB_Switches(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Fetch_Bandwidth", + "LegacyName": "metric_TMA_..Fetch_Bandwidth(%)", + "Origin": "perfmon" + }, + { + "MetricName": "MITE", + "LegacyName": "metric_TMA_....MITE(%)", + "Origin": "perfmon" + }, + { + "MetricName": "DSB", + "LegacyName": "metric_TMA_....DSB(%)", + "Origin": "perfmon" + }, + { + "MetricName": "MS", + "LegacyName": "metric_TMA_....MS(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Bad_Speculation", + "LegacyName": "metric_TMA_Bad_Speculation(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Branch_Mispredicts", + "LegacyName": "metric_TMA_..Branch_Mispredicts(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Cond_NT_Mispredicts", + "LegacyName": "metric_TMA_....Cond_NT_Mispredicts(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Cond_TK_Mispredicts", + "LegacyName": "metric_TMA_....Cond_TK_Mispredicts(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Ind_Call_Mispredicts", + "LegacyName": "metric_TMA_....Ind_Call_Mispredicts(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Ind_Jump_Mispredicts", + "LegacyName": "metric_TMA_....Ind_Jump_Mispredicts(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Ret_Mispredicts", + "LegacyName": "metric_TMA_....Ret_Mispredicts(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Other_Mispredicts", + "LegacyName": "metric_TMA_....Other_Mispredicts(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Machine_Clears", + "LegacyName": "metric_TMA_..Machine_Clears(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Other_Nukes", + "LegacyName": "metric_TMA_....Other_Nukes(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Backend_Bound", + "LegacyName": "metric_TMA_Backend_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Memory_Bound", + "LegacyName": "metric_TMA_..Memory_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "L1_Bound", + "LegacyName": "metric_TMA_....L1_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "DTLB_Load", + "LegacyName": "metric_TMA_......DTLB_Load(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Store_Fwd_Blk", + "LegacyName": "metric_TMA_......Store_Fwd_Blk(%)", + "Origin": "perfmon" + }, + { + "MetricName": "L1_Latency_Dependency", + "LegacyName": "metric_TMA_......L1_Latency_Dependency(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Lock_Latency", + "LegacyName": "metric_TMA_......Lock_Latency(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Split_Loads", + "LegacyName": "metric_TMA_......Split_Loads(%)", + "Origin": "perfmon" + }, + { + "MetricName": "FB_Full", + "LegacyName": "metric_TMA_......FB_Full(%)", + "Origin": "perfmon" + }, + { + "MetricName": "L2_Bound", + "LegacyName": "metric_TMA_....L2_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "L3_Bound", + "LegacyName": "metric_TMA_....L3_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Contested_Accesses", + "LegacyName": "metric_TMA_......Contested_Accesses(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Data_Sharing", + "LegacyName": "metric_TMA_......Data_Sharing(%)", + "Origin": "perfmon" + }, + { + "MetricName": "L3_Hit_Latency", + "LegacyName": "metric_TMA_......L3_Hit_Latency(%)", + "Origin": "perfmon" + }, + { + "MetricName": "SQ_Full", + "LegacyName": "metric_TMA_......SQ_Full(%)", + "Origin": "perfmon" + }, + { + "MetricName": "DRAM_Bound", + "LegacyName": "metric_TMA_....DRAM_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "MEM_Bandwidth", + "LegacyName": "metric_TMA_......MEM_Bandwidth(%)", + "Origin": "perfmon" + }, + { + "MetricName": "MEM_Latency", + "LegacyName": "metric_TMA_......MEM_Latency(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Store_Bound", + "LegacyName": "metric_TMA_....Store_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Store_Latency", + "LegacyName": "metric_TMA_......Store_Latency(%)", + "Origin": "perfmon" + }, + { + "MetricName": "False_Sharing", + "LegacyName": "metric_TMA_......False_Sharing(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Split_Stores", + "LegacyName": "metric_TMA_......Split_Stores(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Streaming_Stores", + "LegacyName": "metric_TMA_......Streaming_Stores(%)", + "Origin": "perfmon" + }, + { + "MetricName": "DTLB_Store", + "LegacyName": "metric_TMA_......DTLB_Store(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Core_Bound", + "LegacyName": "metric_TMA_..Core_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Divider", + "LegacyName": "metric_TMA_....Divider(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Serializing_Operation", + "LegacyName": "metric_TMA_....Serializing_Operation(%)", + "Origin": "perfmon" + }, + { + "MetricName": "AMX_Busy", + "LegacyName": "metric_TMA_....AMX_Busy(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Ports_Utilization", + "LegacyName": "metric_TMA_....Ports_Utilization(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Retiring", + "LegacyName": "metric_TMA_Retiring(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Light_Operations", + "LegacyName": "metric_TMA_..Light_Operations(%)", + "Origin": "perfmon" + }, + { + "MetricName": "FP_Arith", + "LegacyName": "metric_TMA_....FP_Arith(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Int_Operations", + "LegacyName": "metric_TMA_....Int_Operations(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Memory_Operations", + "LegacyName": "metric_TMA_....Memory_Operations(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Fused_Instructions", + "LegacyName": "metric_TMA_....Fused_Instructions(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Non_Fused_Branches", + "LegacyName": "metric_TMA_....Non_Fused_Branches(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Other_Light_Ops", + "LegacyName": "metric_TMA_....Other_Light_Ops(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Heavy_Operations", + "LegacyName": "metric_TMA_..Heavy_Operations(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Few_Uops_Instructions", + "LegacyName": "metric_TMA_....Few_Uops_Instructions(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Microcode_Sequencer", + "LegacyName": "metric_TMA_....Microcode_Sequencer(%)", + "Origin": "perfmon" + } +], + "Metrics": [ + { + "MetricName": "cpu_util_kernel", + "LegacyName": "metric_CPU utilization % in kernel mode", + "BriefDescription": "CPU utilization percentage in kernel mode", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + }, + { + "Name": "TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * (a / b)", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "cycles_per_txn", + "LegacyName": "metric_cycles per txn", + "BriefDescription": "Number of cycles per transaction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "kernel_cpi", + "LegacyName": "metric_kernel_CPI", + "BriefDescription": "Kernel cycles per instruction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "kernel_cycles_per_txn", + "LegacyName": "metric_kernel_cycles per txn", + "BriefDescription": "Number of kernel cycles per transaction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "ipc", + "LegacyName": "metric_IPC", + "BriefDescription": "Instructions per cycle", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "giga_instructions_per_sec", + "LegacyName": "metric_giga_instructions_per_sec", + "BriefDescription": "Billions of instructions per second", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + } + ], + "Constants": [ + ], + "Formula": "a / 1000000000", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "branch_misprediction_ratio", + "LegacyName": "metric_branch misprediction ratio", + "BriefDescription": "Ratio of branch mispredictions to the total number of branches retired.", + "Events": [ + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "locks_retired_per_instr", + "LegacyName": "metric_locks retired per instr", + "BriefDescription": "Locks retired per instruction", + "Events": [ + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "locks_retired_per_txn", + "LegacyName": "metric_locks retired per txn", + "BriefDescription": "Locks retired per transaction", + "Events": [ + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l1d_misses_per_txn", + "LegacyName": "metric_L1D misses per txn (includes data+rfo w/ prefetches)", + "BriefDescription": "L1D misses per transaction (includes data+rfo with prefetches)", + "Events": [ + { + "Name": "L1D.REPLACEMENT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l1d_demand_data_read_hits_per_txn", + "LegacyName": "metric_L1D demand data read hits per txn", + "BriefDescription": "L1D demand data read hits per transaction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L1_HIT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l1i_code_read_misses_per_txn", + "LegacyName": "metric_L1I code read misses (includes prefetches) per txn", + "BriefDescription": "L1I code read misses (includes prefetches) per transaction", + "Events": [ + { + "Name": "L2_RQSTS.ALL_CODE_RD", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l2_demand_data_read_hits_per_txn", + "LegacyName": "metric_L2 demand data read hits per txn", + "BriefDescription": "L2 demand data read hits per transaction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_HIT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l2_misses_per_txn", + "LegacyName": "metric_L2 misses per txn (includes code+data+rfo w/ prefetches)", + "BriefDescription": "L2 misses per transaction (includes code+data+rfo with prefetches)", + "Events": [ + { + "Name": "L2_LINES_IN.ALL", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l2_demand_data_read_misses_per_txn", + "LegacyName": "metric_L2 demand data read misses per txn", + "BriefDescription": "L2 demand data read misses per transaction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l2_demand_code_misses_per_txn", + "LegacyName": "metric_L2 demand code misses per txn", + "BriefDescription": "L2 demand code misses per transaction", + "Events": [ + { + "Name": "L2_RQSTS.CODE_RD_MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "llc_code_read_misses_per_txn", + "LegacyName": "metric_LLC code read (demand+prefetch) misses per txn", + "BriefDescription": "LLC code read (demand+prefetch) misses per transaction", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "llc_data_read_misses_per_txn", + "LegacyName": "metric_LLC data read (demand+prefetch) misses per txn", + "BriefDescription": "LLC data read (demand+prefetch) misses per transaction", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "d" + } + ], + "Formula": "(a + b + c) / d", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "package_power", + "LegacyName": "metric_package power (watts)", + "BriefDescription": "Package power consumption in watts", + "Events": [ + { + "Name": "power/energy-pkg/", + "Alias": "a" + } + ], + "Constants": [ + ], + "Formula": "a", + "ResolutionLevels": "SOCKET, SYSTEM" + }, + { + "MetricName": "dram_power", + "LegacyName": "metric_DRAM power (watts)", + "BriefDescription": "DRAM power consumption in watts", + "Events": [ + { + "Name": "power/energy-ram/", + "Alias": "a" + } + ], + "Constants": [ + ], + "Formula": "a", + "ResolutionLevels": "SOCKET, SYSTEM" + }, + { + "MetricName": "core_c6_residency", + "LegacyName": "metric_core c6 residency %", + "BriefDescription": "Core C6 state residency percentage", + "Events": [ + { + "Name": "cstate_core/c6-residency/", + "Alias": "a" + }, + { + "Name": "TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "ResolutionLevels": "CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "package_c6_residency", + "LegacyName": "metric_package c6 residency %", + "BriefDescription": "Package C6 state residency percentage", + "Events": [ + { + "Name": "cstate_pkg/c6-residency/", + "Alias": "a" + }, + { + "Name": "TSC", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "CORES_PER_SOCKET", + "Alias": "c" + } + ], + "Formula": "100 * a * c / b", + "ResolutionLevels": "SOCKET, SYSTEM" + }, + { + "MetricName": "itlb_misses_per_txn", + "LegacyName": "metric_ITLB (2nd level) misses per txn", + "BriefDescription": "ITLB (2nd level) misses per transaction", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "dtlb_load_misses_per_txn", + "LegacyName": "metric_DTLB (2nd level) load misses per txn", + "BriefDescription": "DTLB (2nd level) load misses per transaction", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "dtlb_store_misses_per_txn", + "LegacyName": "metric_DTLB (2nd level) store misses per txn", + "BriefDescription": "DTLB (2nd level) store misses per transaction", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + } + ], + "AlternateTMAMetrics": [ + { + "MetricName": "Frontend_Bound", + "LegacyName": "metric_TMA_Frontend_Bound(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ_BUBBLES.CORE", + "Alias": "a" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a - b ) / c )", + "BaseFormula": "100 * ( ( [IDQ_BUBBLES.CORE] - [INT_MISC.UOP_DROPPING] ) / [TOPDOWN.SLOTS_P] )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 15", + "BaseFormula": "metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvFB;BvIO;TmaL1;PGO", + "LocateWith": " FRONTEND_RETIRED.LATENCY_GE_4" + }, + { + "MetricName": "Fetch_Latency", + "LegacyName": "metric_TMA_..Fetch_Latency(%)", + "ParentCategory": "Frontend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "a" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a * ( 6 ) - b ) / c )", + "BaseFormula": " ( 100 * ( ( [IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE] * ( 6 ) - [INT_MISC.UOP_DROPPING] ) / [TOPDOWN.SLOTS_P] ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 15", + "BaseFormula": "metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Frontend;TmaL2", + "LocateWith": " FRONTEND_RETIRED.LATENCY_GE_16;FRONTEND_RETIRED.LATENCY_GE_8" + }, + { + "MetricName": "Fetch_Bandwidth", + "LegacyName": "metric_TMA_..Fetch_Bandwidth(%)", + "ParentCategory": "Frontend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CORE", + "Alias": "a" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "c" + }, + { + "Name": "IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( ( a - b ) / ( c ) ) - ( ( d * ( 6 ) - b ) / ( c ) ) ) )", + "BaseFormula": "max( 0 , tma_frontend_bound - tma_fetch_latency )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Fetch_Bandwidth(%)" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_..Fetch_Bandwidth(%) > 20", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchBW;Frontend;TmaL2", + "LocateWith": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1;FRONTEND_RETIRED.LATENCY_GE_1;FRONTEND_RETIRED.LATENCY_GE_2" + }, + { + "MetricName": "Bad_Speculation", + "LegacyName": "metric_TMA_Bad_Speculation(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ_BUBBLES.CORE", + "Alias": "a" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "c" + }, + { + "Name": "TOPDOWN.BACKEND_BOUND_SLOTS", + "Alias": "d" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( max( 1 - ( ( ( a - b ) / c ) + ( d / c ) + ( e / c ) ) , 0 ) )", + "BaseFormula": " 100 * ( max( 1 - ( ( ( [IDQ_BUBBLES.CORE] - [INT_MISC.UOP_DROPPING] ) / [TOPDOWN.SLOTS_P] ) + ( [TOPDOWN.BACKEND_BOUND_SLOTS] / [TOPDOWN.SLOTS_P] ) + ( [UOPS_RETIRED.SLOTS] / [TOPDOWN.SLOTS_P] ) ) , 0 ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 15", + "BaseFormula": "metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "TmaL1", + "LocateWith": "#NA" + }, + { + "MetricName": "Branch_Mispredicts", + "LegacyName": "metric_TMA_..Branch_Mispredicts(%)", + "ParentCategory": "Bad_Speculation", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN.BR_MISPREDICT_SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "perf_metrics.branch_mispredicts / ( perf_metrics.frontend_bound + perf_metrics.bad_speculation + perf_metrics.retiring + perf_metrics.backend_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Branch_Mispredicts(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 10 & b > 15", + "BaseFormula": "metric_TMA_..Branch_Mispredicts(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "$issueBM" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2", + "LocateWith": "TOPDOWN.BR_MISPREDICT_SLOTS" + }, + { + "MetricName": "Machine_Clears", + "LegacyName": "metric_TMA_..Machine_Clears(%)", + "ParentCategory": "Bad_Speculation", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CORE", + "Alias": "a" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "c" + }, + { + "Name": "TOPDOWN.BACKEND_BOUND_SLOTS", + "Alias": "d" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "e" + }, + { + "Name": "TOPDOWN.BR_MISPREDICT_SLOTS", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( max( 1 - ( ( ( a - b ) / ( c ) ) + ( d / ( c ) ) + ( e / ( c ) ) ) , 0 ) ) - ( f / ( c ) ) ) )", + "BaseFormula": "max( 0 , tma_bad_speculation - tma_branch_mispredicts )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Machine_Clears(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 10 & b > 15", + "BaseFormula": "metric_TMA_..Machine_Clears(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "$issueMC, $issueSyncxn" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2", + "LocateWith": "MACHINE_CLEARS.COUNT" + }, + { + "MetricName": "Backend_Bound", + "LegacyName": "metric_TMA_Backend_Bound(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN.BACKEND_BOUND_SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / b )", + "BaseFormula": " 100 * ( [TOPDOWN.BACKEND_BOUND_SLOTS] / [TOPDOWN.SLOTS_P] )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvOB;TmaL1", + "LocateWith": " TOPDOWN.BACKEND_BOUND_SLOTS" + }, + { + "MetricName": "Memory_Bound", + "LegacyName": "metric_TMA_..Memory_Bound(%)", + "ParentCategory": "Backend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN.MEMORY_BOUND_SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / b )", + "BaseFormula": " 100 * ( [TOPDOWN.MEMORY_BOUND_SLOTS] / [TOPDOWN.SLOTS_P] )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20", + "BaseFormula": "metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Backend;TmaL2", + "LocateWith": "#NA" + }, + { + "MetricName": "Core_Bound", + "LegacyName": "metric_TMA_..Core_Bound(%)", + "ParentCategory": "Backend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN.BACKEND_BOUND_SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + }, + { + "Name": "TOPDOWN.MEMORY_BOUND_SLOTS", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b ) ) - ( c / ( b ) ) ) )", + "BaseFormula": "max( 0 , tma_backend_bound - tma_memory_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 20", + "BaseFormula": "metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Backend;TmaL2;Compute", + "LocateWith": "" + }, + { + "MetricName": "Retiring", + "LegacyName": "metric_TMA_Retiring(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / b )", + "BaseFormula": " 100 * ( [UOPS_RETIRED.SLOTS] / [TOPDOWN.SLOTS_P] )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Retiring(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 70 | b > 10", + "BaseFormula": "metric_TMA_Retiring(%) > 70 | metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvUW;TmaL1", + "LocateWith": " UOPS_RETIRED.SLOTS" + }, + { + "MetricName": "Light_Operations", + "LegacyName": "metric_TMA_..Light_Operations(%)", + "ParentCategory": "Retiring", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations , instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + }, + { + "Name": "UOPS_RETIRED.HEAVY", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b ) ) - ( c / ( b ) ) ) )", + "BaseFormula": "max( 0 , tma_retiring - tma_heavy_operations )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Retire;TmaL2", + "LocateWith": "INST_RETIRED.PREC_DIST" + }, + { + "MetricName": "Memory_Operations", + "LegacyName": "metric_TMA_....Memory_Operations(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations , uops for memory load or store accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + }, + { + "Name": "UOPS_RETIRED.HEAVY", + "Alias": "c" + }, + { + "Name": "MEM_UOP_RETIRED.ANY", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b ) ) - ( c / ( b ) ) ) ) * d / ( ( a / ( b ) ) * ( b ) ) )", + "BaseFormula": "tma_light_operations * mem_uop_retired.any / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Memory_Operations(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 60", + "BaseFormula": "metric_TMA_....Memory_Operations(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Fused_Instructions", + "LegacyName": "metric_TMA_....Fused_Instructions(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions , where one uop can represent multiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Other_Light_Ops in MTL!)}", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + }, + { + "Name": "UOPS_RETIRED.HEAVY", + "Alias": "c" + }, + { + "Name": "INST_RETIRED.MACRO_FUSED", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b ) ) - ( c / ( b ) ) ) ) * d / ( ( a / ( b ) ) * ( b ) ) )", + "BaseFormula": "tma_light_operations * inst_retired.macro_fused / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Fused_Instructions(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 60", + "BaseFormula": "metric_TMA_....Fused_Instructions(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;BvBO;Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Non_Fused_Branches", + "LegacyName": "metric_TMA_....Non_Fused_Branches(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + }, + { + "Name": "UOPS_RETIRED.HEAVY", + "Alias": "c" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "d" + }, + { + "Name": "INST_RETIRED.MACRO_FUSED", + "Alias": "e" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "f" + }, + { + "Name": "INST_RETIRED.MACRO_FUSED", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b ) ) - ( c / ( b ) ) ) ) * ( d - e ) / ( ( a / ( b ) ) * ( b ) ) )", + "BaseFormula": "tma_light_operations * ( br_inst_retired.all_branches - inst_retired.macro_fused ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Non_Fused_Branches(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 60", + "BaseFormula": "metric_TMA_....Non_Fused_Branches(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;BvBO;Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Heavy_Operations", + "LegacyName": "metric_TMA_..Heavy_Operations(%)", + "ParentCategory": "Retiring", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations , instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.([ICL+] Note this may overcount due to approximation using indirect events; [ADL+])", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.HEAVY", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / b )", + "BaseFormula": " 100 * ( [UOPS_RETIRED.HEAVY] / [TOPDOWN.SLOTS_P] )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Retire;TmaL2", + "LocateWith": " UOPS_RETIRED.HEAVY" + }, + { + "MetricName": "Few_Uops_Instructions", + "LegacyName": "metric_TMA_....Few_Uops_Instructions(%)", + "ParentCategory": "Heavy_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or more uops. This highly-correlates with the number of uops in such instructions.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.HEAVY", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + }, + { + "Name": "UOPS_RETIRED.MS", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b ) ) - ( c / ( b ) ) ) )", + "BaseFormula": "max( 0 , tma_heavy_operations - tma_microcode_sequencer )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Few_Uops_Instructions(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 5 & b > 10", + "BaseFormula": "metric_TMA_....Few_Uops_Instructions(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "$issueD0" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "Microcode_Sequencer", + "LegacyName": "metric_TMA_....Microcode_Sequencer(%)", + "ParentCategory": "Heavy_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.MS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "uops_retired.ms / tma_info_thread_slots", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Microcode_Sequencer(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 5 & b > 10", + "BaseFormula": "metric_TMA_....Microcode_Sequencer(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "$issueMC, $issueMS" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq", + "LocateWith": "UOPS_RETIRED.MS" + } + ] +} diff --git a/cmd/metrics/resources/perfmon/gnr/graniterapids_core.json b/cmd/metrics/resources/perfmon/gnr/graniterapids_core.json new file mode 100644 index 00000000..1a163ec7 --- /dev/null +++ b/cmd/metrics/resources/perfmon/gnr/graniterapids_core.json @@ -0,0 +1,9536 @@ +{ + "Header": { + "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with P-cores - V1.10", + "DatePublished": "05/16/2025", + "Version": "1.10", + "Legend": "" + }, + "Events": [ + { + "EventCode": "0x00", + "UMask": "0x01", + "EventName": "INST_RETIRED.ANY", + "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event", + "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", + "Counter": "Fixed counter 0", + "PEBScounters": "32", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "32", + "Speculative": "0" + }, + { + "EventCode": "0x00", + "UMask": "0x01", + "EventName": "INST_RETIRED.PREC_DIST", + "BriefDescription": "Precise instruction retired with PEBS precise-distribution", + "PublicDescription": "A version of INST_RETIRED that allows for a precise distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR++) feature to fix bias in how retired instructions get sampled. Use on Fixed Counter 0.", + "Counter": "Fixed counter 0", + "PEBScounters": "32", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "32", + "Speculative": "0" + }, + { + "EventCode": "0x00", + "UMask": "0x02", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "BriefDescription": "Core cycles when the thread is not in halt state", + "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.", + "Counter": "Fixed counter 1", + "PEBScounters": "33", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x00", + "UMask": "0x03", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "BriefDescription": "Reference cycles when the core is not in halt state.", + "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", + "Counter": "Fixed counter 2", + "PEBScounters": "34", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x00", + "UMask": "0x04", + "EventName": "TOPDOWN.SLOTS", + "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", + "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", + "Counter": "Fixed counter 3", + "PEBScounters": "35", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x03", + "UMask": "0x04", + "EventName": "LD_BLOCKS.ADDRESS_ALIAS", + "BriefDescription": "False dependencies in MOB due to partial compare on address.", + "PublicDescription": "Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x03", + "UMask": "0x82", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", + "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x03", + "UMask": "0x88", + "EventName": "LD_BLOCKS.NO_SR", + "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x11", + "UMask": "0x02", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", + "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x11", + "UMask": "0x04", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", + "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x11", + "UMask": "0x0e", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", + "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x11", + "UMask": "0x10", + "EventName": "ITLB_MISSES.WALK_ACTIVE", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.", + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x11", + "UMask": "0x10", + "EventName": "ITLB_MISSES.WALK_PENDING", + "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.", + "PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x11", + "UMask": "0x20", + "EventName": "ITLB_MISSES.STLB_HIT", + "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.", + "PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x12", + "UMask": "0x02", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Page walks completed due to a demand data load to a 4K page.", + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x12", + "UMask": "0x04", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.", + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x12", + "UMask": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "BriefDescription": "Page walks completed due to a demand data load to a 1G page.", + "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x12", + "UMask": "0x0e", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x12", + "UMask": "0x10", + "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.", + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x12", + "UMask": "0x10", + "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", + "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.", + "PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x12", + "UMask": "0x20", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "BriefDescription": "Loads that miss the DTLB and hit the STLB.", + "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x13", + "UMask": "0x02", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Page walks completed due to a demand data store to a 4K page.", + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x13", + "UMask": "0x04", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.", + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x13", + "UMask": "0x08", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "BriefDescription": "Page walks completed due to a demand data store to a 1G page.", + "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x13", + "UMask": "0x0e", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x13", + "UMask": "0x10", + "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.", + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x13", + "UMask": "0x10", + "EventName": "DTLB_STORE_MISSES.WALK_PENDING", + "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.", + "PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x13", + "UMask": "0x20", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "BriefDescription": "Stores that miss the DTLB and hit the STLB.", + "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x01", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "BriefDescription": "Cycles where at least 1 outstanding demand data read request is pending.", + "PublicDescription": "Cycles where at least 1 outstanding demand data read request is pending.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x01", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "BriefDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.", + "PublicDescription": "For every cycle, increments by the number of outstanding demand data read requests pending. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x02", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", + "BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.", + "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x02", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.", + "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x04", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.", + "PublicDescription": "Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x04", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "BriefDescription": "Store Read transactions pending for off-core. Highly correlated.", + "PublicDescription": "Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x08", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "PublicDescription": "Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x08", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "PublicDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x10", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", + "BriefDescription": "Cycles where data return is pending for a Demand Data Read request who miss L3 cache.", + "PublicDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x10", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", + "BriefDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.", + "PublicDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known by the requesting core to have missed the L3 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x21", + "UMask": "0x01", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "BriefDescription": "Demand Data Read requests sent to uncore", + "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x21", + "UMask": "0x02", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "BriefDescription": "Cacheable and Non-Cacheable code read requests", + "PublicDescription": "Counts both cacheable and Non-Cacheable code read requests.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x21", + "UMask": "0x04", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", + "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x21", + "UMask": "0x08", + "EventName": "OFFCORE_REQUESTS.DATA_RD", + "BriefDescription": "Demand and prefetch data reads", + "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x21", + "UMask": "0x10", + "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "BriefDescription": "Counts demand data read requests that miss the L3 cache.", + "PublicDescription": "Counts demand data read requests that miss the L3 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x21", + "UMask": "0x20", + "EventName": "OFFCORE_REQUESTS.MEM_UC", + "BriefDescription": "Offcore Uncacheable memory data read transactions.", + "PublicDescription": "This event counts noncacheable memory data read transactions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x21", + "UMask": "0x80", + "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", + "BriefDescription": "Any memory transaction that reached the SQ.", + "PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x23", + "UMask": "0x40", + "EventName": "L2_TRANS.L2_WB", + "BriefDescription": "L2 writebacks that access L2 cache", + "PublicDescription": "Counts L2 writebacks that access L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x21", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "BriefDescription": "Demand Data Read miss L2 cache", + "PublicDescription": "Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x22", + "EventName": "L2_RQSTS.RFO_MISS", + "BriefDescription": "RFO requests that miss L2 cache", + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "BriefDescription": "L2 cache misses when fetching instructions", + "PublicDescription": "Counts L2 cache misses when fetching instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x27", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "BriefDescription": "Demand requests that miss L2 cache", + "PublicDescription": "Counts demand requests that miss L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x28", + "EventName": "L2_RQSTS.SWPF_MISS", + "BriefDescription": "SW prefetch requests that miss L2 cache.", + "PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x30", + "EventName": "L2_RQSTS.HWPF_MISS", + "BriefDescription": "L2_RQSTS.HWPF_MISS", + "PublicDescription": "L2_RQSTS.HWPF_MISS", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x3f", + "EventName": "L2_RQSTS.MISS", + "BriefDescription": "Read requests with true-miss in L2 cache [This event is alias to L2_REQUEST.MISS]", + "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.MISS]", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x3f", + "EventName": "L2_REQUEST.MISS", + "BriefDescription": "Read requests with true-miss in L2 cache [This event is alias to L2_RQSTS.MISS]", + "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.MISS]", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xc1", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "BriefDescription": "Demand Data Read requests that hit L2 cache", + "PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xc2", + "EventName": "L2_RQSTS.RFO_HIT", + "BriefDescription": "RFO requests that hit L2 cache", + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xc4", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xc8", + "EventName": "L2_RQSTS.SWPF_HIT", + "BriefDescription": "SW prefetch requests that hit L2 cache.", + "PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xdf", + "EventName": "L2_RQSTS.HIT", + "BriefDescription": "All requests that hit L2 cache. [This event is alias to L2_REQUEST.HIT]", + "PublicDescription": "Counts all requests that hit L2 cache. [This event is alias to L2_REQUEST.HIT]", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xdf", + "EventName": "L2_REQUEST.HIT", + "BriefDescription": "All requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT]", + "PublicDescription": "Counts all requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT]", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xe1", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "BriefDescription": "Demand Data Read access L2 cache", + "PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xe2", + "EventName": "L2_RQSTS.ALL_RFO", + "BriefDescription": "RFO requests to L2 cache", + "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xe4", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "BriefDescription": "L2 code requests", + "PublicDescription": "Counts the total number of L2 code requests.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xe7", + "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", + "BriefDescription": "Demand requests to L2 cache", + "PublicDescription": "Counts demand requests to L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xf0", + "EventName": "L2_RQSTS.ALL_HWPF", + "BriefDescription": "L2_RQSTS.ALL_HWPF", + "PublicDescription": "L2_RQSTS.ALL_HWPF", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xff", + "EventName": "L2_RQSTS.REFERENCES", + "BriefDescription": "All accesses to L2 cache [This event is alias to L2_REQUEST.ALL]", + "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.ALL]", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xff", + "EventName": "L2_REQUEST.ALL", + "BriefDescription": "All accesses to L2 cache [This event is alias to L2_RQSTS.REFERENCES]", + "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES]", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x25", + "UMask": "0x1f", + "EventName": "L2_LINES_IN.ALL", + "BriefDescription": "L2 cache lines filling L2", + "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x26", + "UMask": "0x01", + "EventName": "L2_LINES_OUT.SILENT", + "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache.", + "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache. These lines are typically in Shared or Exclusive state. A non-threaded event.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x26", + "UMask": "0x02", + "EventName": "L2_LINES_OUT.NON_SILENT", + "BriefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill.", + "PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x26", + "UMask": "0x04", + "EventName": "L2_LINES_OUT.USELESS_HWPF", + "BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses", + "PublicDescription": "Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x2c", + "UMask": "0x10", + "EventName": "SQ_MISC.BUS_LOCK", + "BriefDescription": "Counts bus locks, accounts for cache line split locks and UC locks.", + "PublicDescription": "Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically. Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x2d", + "UMask": "0x01", + "EventName": "XQ.FULL_CYCLES", + "BriefDescription": "Cycles the uncore cannot take further requests", + "PublicDescription": "number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x2e", + "UMask": "0x41", + "EventName": "LONGEST_LAT_CACHE.MISS", + "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)", + "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x2e", + "UMask": "0x4f", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)", + "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x3c", + "UMask": "0x00", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "BriefDescription": "Thread cycles when thread is not in halt state", + "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x3c", + "UMask": "0x01", + "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", + "BriefDescription": "Reference cycles when the core is not in halt state.", + "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x3c", + "UMask": "0x02", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.", + "PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "25003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x3c", + "UMask": "0x08", + "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.", + "PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x40", + "UMask": "0x01", + "EventName": "SW_PREFETCH_ACCESS.NTA", + "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x40", + "UMask": "0x02", + "EventName": "SW_PREFETCH_ACCESS.T0", + "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x40", + "UMask": "0x04", + "EventName": "SW_PREFETCH_ACCESS.T1_T2", + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x40", + "UMask": "0x08", + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", + "BriefDescription": "Number of PREFETCHW instructions executed.", + "PublicDescription": "Counts the number of PREFETCHW instructions executed.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x40", + "UMask": "0xF", + "EventName": "SW_PREFETCH_ACCESS.ANY", + "BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.", + "PublicDescription": "Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x43", + "UMask": "0xfd", + "EventName": "MEM_LOAD_COMPLETED.L1_MISS_ANY", + "BriefDescription": "Completed demand load uops that miss the L1 d-cache.", + "PublicDescription": "Number of completed demand load requests that missed the L1 data cache including shadow misses (FB hits, merge to an ongoing L1D miss)", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x44", + "UMask": "0x01", + "EventName": "MEM_STORE_RETIRED.L2_HIT", + "BriefDescription": "MEM_STORE_RETIRED.L2_HIT", + "PublicDescription": "MEM_STORE_RETIRED.L2_HIT", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x47", + "UMask": "0x02", + "EventName": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "PublicDescription": "Cycles while L1 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "2", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x47", + "UMask": "0x03", + "EventName": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "PublicDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "3", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x47", + "UMask": "0x05", + "EventName": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "BriefDescription": "Execution stalls while L2 cache miss demand cacheable load request is outstanding.", + "PublicDescription": "Execution stalls while L2 cache miss demand cacheable load request is outstanding (will not count for uncacheable demand requests e.g. bus lock).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "5", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x47", + "UMask": "0x09", + "EventName": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "BriefDescription": "Execution stalls while L3 cache miss demand cacheable load request is outstanding.", + "PublicDescription": "Execution stalls while L3 cache miss demand cacheable load request is outstanding (will not count for uncacheable demand requests e.g. bus lock).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "9", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x48", + "UMask": "0x01", + "EventName": "L1D_PEND_MISS.PENDING", + "BriefDescription": "Number of L1D misses that are outstanding", + "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x48", + "UMask": "0x01", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "PublicDescription": "Counts duration of L1D miss outstanding in cycles.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x48", + "UMask": "0x02", + "EventName": "L1D_PEND_MISS.FB_FULL", + "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.", + "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x48", + "UMask": "0x02", + "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS", + "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.", + "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x48", + "UMask": "0x04", + "EventName": "L1D_PEND_MISS.L2_STALLS", + "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", + "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x4c", + "UMask": "0x01", + "EventName": "LOAD_HIT_PREFETCH.SWPF", + "BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.", + "PublicDescription": "Counts all software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x51", + "UMask": "0x01", + "EventName": "L1D.REPLACEMENT", + "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.", + "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x51", + "UMask": "0x20", + "EventName": "L1D.HWPF_MISS", + "BriefDescription": "L1D.HWPF_MISS", + "PublicDescription": "L1D.HWPF_MISS", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x54", + "UMask": "0x01", + "EventName": "TX_MEM.ABORT_CONFLICT", + "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", + "PublicDescription": "Counts the number of times a TSX line had a cache conflict.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x54", + "UMask": "0x02", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.", + "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x54", + "UMask": "0x80", + "EventName": "TX_MEM.ABORT_CAPACITY_READ", + "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads", + "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x60", + "UMask": "0x01", + "EventName": "BACLEARS.ANY", + "BriefDescription": "Clears due to Unknown Branches.", + "PublicDescription": "Number of times the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x61", + "UMask": "0x02", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "BriefDescription": "DSB-to-MITE switch true penalty cycles.", + "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x75", + "UMask": "0x01", + "EventName": "INST_DECODED.DECODERS", + "BriefDescription": "Instruction decoders utilized in a cycle", + "PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x76", + "UMask": "0x01", + "EventName": "UOPS_DECODED.DEC0_UOPS", + "BriefDescription": "Number of non dec-by-all uops decoded by decoder", + "PublicDescription": "This event counts the number of not dec-by-all uops decoded by decoder 0.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x04", + "EventName": "IDQ.MITE_CYCLES_ANY", + "BriefDescription": "Cycles MITE is delivering any Uop", + "PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x04", + "EventName": "IDQ.MITE_CYCLES_OK", + "BriefDescription": "Cycles MITE is delivering optimal number of Uops", + "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "6", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x04", + "EventName": "IDQ.MITE_UOPS", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x08", + "EventName": "IDQ.DSB_CYCLES_ANY", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", + "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x08", + "EventName": "IDQ.DSB_CYCLES_OK", + "BriefDescription": "Cycles DSB is delivering optimal number of Uops", + "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode Stream Buffer) path. Count includes uops that may 'bypass' the IDQ.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "6", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x08", + "EventName": "IDQ.DSB_UOPS", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", + "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x20", + "EventName": "IDQ.MS_CYCLES_ANY", + "BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy", + "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x20", + "EventName": "IDQ.MS_SWITCHES", + "BriefDescription": "Number of switches from DSB or MITE to the MS", + "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x20", + "EventName": "IDQ.MS_UOPS", + "BriefDescription": "Uops initiated by MITE or Decode Stream Buffer (DSB) and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", + "PublicDescription": "Counts the number of uops initiated by MITE or Decode Stream Buffer (DSB) and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x80", + "UMask": "0x04", + "EventName": "ICACHE_DATA.STALLS", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.", + "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The decode pipeline works at a 32 Byte granularity.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x80", + "UMask": "0x04", + "EventName": "ICACHE_DATA.STALL_PERIODS", + "BriefDescription": "ICACHE_DATA.STALL_PERIODS", + "PublicDescription": "ICACHE_DATA.STALL_PERIODS", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x83", + "UMask": "0x04", + "EventName": "ICACHE_TAG.STALLS", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.", + "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x87", + "UMask": "0x01", + "EventName": "DECODE.LCP", + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x87", + "UMask": "0x02", + "EventName": "DECODE.MS_BUSY", + "BriefDescription": "Cycles the Microcode Sequencer is busy.", + "PublicDescription": "Cycles the Microcode Sequencer is busy.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x9c", + "UMask": "0x01", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled", + "PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x9c", + "UMask": "0x01", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE]", + "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "6", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x9c", + "UMask": "0x01", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_FE_WAS_OK]", + "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CYCLES_FE_WAS_OK]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x9c", + "UMask": "0x01", + "EventName": "IDQ_BUBBLES.CORE", + "BriefDescription": "This event counts a subset of the Topdown Slots event that when no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations.", + "PublicDescription": "This event counts a subset of the Topdown Slots event that when no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations. The count may be distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the numerator for the Frontend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x9c", + "UMask": "0x01", + "EventName": "IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE", + "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE]", + "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "6", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x9c", + "UMask": "0x01", + "EventName": "IDQ_BUBBLES.CYCLES_FE_WAS_OK", + "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK]", + "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa2", + "UMask": "0x02", + "EventName": "RESOURCE_STALLS.SCOREBOARD", + "BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.", + "PublicDescription": "Counts cycles where the pipeline is stalled due to serializing operations.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa2", + "UMask": "0x08", + "EventName": "RESOURCE_STALLS.SB", + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x01", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", + "PublicDescription": "Cycles while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x02", + "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", + "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", + "PublicDescription": "Cycles while L3 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "2", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x04", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", + "BriefDescription": "Total execution stalls.", + "PublicDescription": "Total execution stalls.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "4", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x05", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "PublicDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "5", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x06", + "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", + "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", + "PublicDescription": "Execution stalls while L3 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "6", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x08", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "PublicDescription": "Cycles while L1 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "8", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x0c", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "PublicDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "12", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x10", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "PublicDescription": "Cycles while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "16", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa4", + "UMask": "0x01", + "EventName": "TOPDOWN.SLOTS_P", + "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", + "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa4", + "UMask": "0x02", + "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", + "BriefDescription": "This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions.", + "PublicDescription": "This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the numerator for the Backend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa4", + "UMask": "0x04", + "EventName": "TOPDOWN.BAD_SPEC_SLOTS", + "BriefDescription": "TMA slots wasted due to incorrect speculations.", + "PublicDescription": "Number of slots of TMA method that were wasted due to incorrect speculation. It covers all types of control-flow or data-related mis-speculations.", + "Counter": "0", + "PEBScounters": "0", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa4", + "UMask": "0x08", + "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", + "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", + "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by (any type of) branch mispredictions. This event estimates number of speculative operations that were issued but not retired as well as the out-of-order engine recovery past a branch misprediction.", + "Counter": "0", + "PEBScounters": "0", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa4", + "UMask": "0x10", + "EventName": "TOPDOWN.MEMORY_BOUND_SLOTS", + "BriefDescription": "TOPDOWN.MEMORY_BOUND_SLOTS", + "PublicDescription": "TOPDOWN.MEMORY_BOUND_SLOTS", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa5", + "UMask": "0x01", + "EventName": "RS.EMPTY_RESOURCE", + "BriefDescription": "Cycles when RS was empty and a resource allocation stall is asserted", + "PublicDescription": "Cycles when RS was empty and a resource allocation stall is asserted", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa5", + "UMask": "0x07", + "EventName": "RS.EMPTY", + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.", + "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses)", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa5", + "UMask": "0x07", + "EventName": "RS.EMPTY_COUNT", + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.", + "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x02", + "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", + "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.", + "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x04", + "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", + "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.", + "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x08", + "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", + "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.", + "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x10", + "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", + "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.", + "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x21", + "EventName": "EXE_ACTIVITY.BOUND_ON_LOADS", + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "PublicDescription": "Execution stalls while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "5", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x40", + "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", + "BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.", + "PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "2", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x80", + "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "BriefDescription": "Cycles no uop executed while RS was not empty, the SB was not full and there was no outstanding load.", + "PublicDescription": "Number of cycles total of 0 uops executed on all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) was not full and there was no outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0xC", + "EventName": "EXE_ACTIVITY.2_3_PORTS_UTIL", + "BriefDescription": "Cycles total of 2 or 3 uops are executed on all ports and Reservation Station (RS) was not empty.", + "PublicDescription": "Cycles total of 2 or 3 uops are executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa8", + "UMask": "0x01", + "EventName": "LSD.CYCLES_ACTIVE", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa8", + "UMask": "0x01", + "EventName": "LSD.CYCLES_OK", + "BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.", + "PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "6", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa8", + "UMask": "0x01", + "EventName": "LSD.UOPS", + "BriefDescription": "Number of Uops delivered by the LSD.", + "PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xad", + "UMask": "0x01", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread", + "PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xad", + "UMask": "0x01", + "EventName": "INT_MISC.CLEARS_COUNT", + "BriefDescription": "Clears speculative count", + "PublicDescription": "Counts the number of speculative clears due to any type of branch misprediction or machine clears", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xad", + "UMask": "0x10", + "EventName": "INT_MISC.UOP_DROPPING", + "BriefDescription": "TMA slots where uops got dropped", + "PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xad", + "UMask": "0x20", + "EventName": "INT_MISC.MBA_STALLS", + "BriefDescription": "INT_MISC.MBA_STALLS", + "PublicDescription": "INT_MISC.MBA_STALLS", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xad", + "UMask": "0x40", + "EventName": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "BriefDescription": "Bubble cycles of BAClear (Unknown Branch).", + "PublicDescription": "Bubble cycles of BAClear (Unknown Branch).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x3F7", + "MSRValue": "0x7", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xad", + "UMask": "0x80", + "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", + "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", + "PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xae", + "UMask": "0x01", + "EventName": "UOPS_ISSUED.ANY", + "BriefDescription": "Uops that RAT issues to RS", + "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xae", + "UMask": "0x01", + "EventName": "UOPS_ISSUED.CYCLES", + "BriefDescription": "UOPS_ISSUED.CYCLES", + "PublicDescription": "UOPS_ISSUED.CYCLES", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb0", + "UMask": "0x01", + "EventName": "ARITH.FPDIV_ACTIVE", + "BriefDescription": "This event counts the cycles the floating point divider is busy.", + "PublicDescription": "This event counts the cycles the floating point divider is busy.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb0", + "UMask": "0x08", + "EventName": "ARITH.IDIV_ACTIVE", + "BriefDescription": "This event counts the cycles the integer divider is busy.", + "PublicDescription": "This event counts the cycles the integer divider is busy.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb0", + "UMask": "0x09", + "EventName": "ARITH.DIV_ACTIVE", + "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.", + "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1", + "BriefDescription": "Cycles where at least 1 uop was executed per-thread", + "PublicDescription": "Cycles where at least 1 uop was executed per-thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2", + "BriefDescription": "Cycles where at least 2 uops were executed per-thread", + "PublicDescription": "Cycles where at least 2 uops were executed per-thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "2", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3", + "BriefDescription": "Cycles where at least 3 uops were executed per-thread", + "PublicDescription": "Cycles where at least 3 uops were executed per-thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "3", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4", + "BriefDescription": "Cycles where at least 4 uops were executed per-thread", + "PublicDescription": "Cycles where at least 4 uops were executed per-thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "4", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.THREAD", + "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", + "PublicDescription": "Counts the number of uops to be executed per-thread each cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.STALLS", + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE", + "BriefDescription": "Number of uops executed on the core.", + "PublicDescription": "Counts the number of uops executed from any thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "2", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "3", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "4", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x10", + "EventName": "UOPS_EXECUTED.X87", + "BriefDescription": "Counts the number of x87 uops dispatched.", + "PublicDescription": "Counts the number of x87 uops executed.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb2", + "UMask": "0x01", + "EventName": "UOPS_DISPATCHED.PORT_0", + "BriefDescription": "Uops executed on port 0", + "PublicDescription": "Number of uops dispatch to execution port 0.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb2", + "UMask": "0x02", + "EventName": "UOPS_DISPATCHED.PORT_1", + "BriefDescription": "Uops executed on port 1", + "PublicDescription": "Number of uops dispatch to execution port 1.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb2", + "UMask": "0x04", + "EventName": "UOPS_DISPATCHED.PORT_2_3_10", + "BriefDescription": "Uops executed on ports 2, 3 and 10", + "PublicDescription": "Number of uops dispatch to execution ports 2, 3 and 10", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb2", + "UMask": "0x10", + "EventName": "UOPS_DISPATCHED.PORT_4_9", + "BriefDescription": "Uops executed on ports 4 and 9", + "PublicDescription": "Number of uops dispatch to execution ports 4 and 9", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb2", + "UMask": "0x20", + "EventName": "UOPS_DISPATCHED.PORT_5_11", + "BriefDescription": "Uops executed on ports 5 and 11", + "PublicDescription": "Number of uops dispatch to execution ports 5 and 11", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb2", + "UMask": "0x40", + "EventName": "UOPS_DISPATCHED.PORT_6", + "BriefDescription": "Uops executed on port 6", + "PublicDescription": "Number of uops dispatch to execution port 6.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb2", + "UMask": "0x80", + "EventName": "UOPS_DISPATCHED.PORT_7_8", + "BriefDescription": "Uops executed on ports 7 and 8", + "PublicDescription": "Number of uops dispatch to execution ports 7 and 8.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb3", + "UMask": "0x01", + "EventName": "FP_ARITH_DISPATCHED.PORT_0", + "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0]", + "PublicDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb3", + "UMask": "0x01", + "EventName": "FP_ARITH_DISPATCHED.V0", + "BriefDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0]", + "PublicDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb3", + "UMask": "0x02", + "EventName": "FP_ARITH_DISPATCHED.PORT_1", + "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1]", + "PublicDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb3", + "UMask": "0x02", + "EventName": "FP_ARITH_DISPATCHED.V1", + "BriefDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1]", + "PublicDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb3", + "UMask": "0x04", + "EventName": "FP_ARITH_DISPATCHED.PORT_5", + "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2]", + "PublicDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb3", + "UMask": "0x04", + "EventName": "FP_ARITH_DISPATCHED.V2", + "BriefDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5]", + "PublicDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb7", + "UMask": "0x02", + "EventName": "EXE.AMX_BUSY", + "BriefDescription": "Counts the cycles where the AMX (Advance Matrix Extension) unit is busy performing an operation.", + "PublicDescription": "Counts the cycles where the AMX (Advance Matrix Extension) unit is busy performing an operation.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xc0", + "UMask": "0x00", + "EventName": "INST_RETIRED.ANY_P", + "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc0", + "UMask": "0x02", + "EventName": "INST_RETIRED.NOP", + "BriefDescription": "Retired NOP instructions.", + "PublicDescription": "Counts all retired NOP or ENDBR32/64 or PREFETCHIT0/1 instructions", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc0", + "UMask": "0x08", + "EventName": "INST_RETIRED.REP_ITERATION", + "BriefDescription": "Iterations of Repeat string retired instructions.", + "PublicDescription": "Number of iterations of Repeat (REP) string retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, and doubleword version and string instructions can be repeated using a repetition prefix, REP, that allows their architectural execution to be repeated a number of times as specified by the RCX register. Note the number of iterations is implementation-dependent.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc0", + "UMask": "0x10", + "EventName": "INST_RETIRED.MACRO_FUSED", + "BriefDescription": "INST_RETIRED.MACRO_FUSED", + "PublicDescription": "INST_RETIRED.MACRO_FUSED", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc1", + "UMask": "0x02", + "EventName": "ASSISTS.FP", + "BriefDescription": "Counts all microcode FP assists.", + "PublicDescription": "Counts all microcode Floating Point assists.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xc1", + "UMask": "0x04", + "EventName": "ASSISTS.HARDWARE", + "BriefDescription": "Count all other hardware assists or traps that are not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and A/D assists who are counted by dedicated sub-events. the event also counts for Machine Ordering count.", + "PublicDescription": "Count all other hardware assists or traps that are not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and A/D assists who are counted by dedicated sub-events. This includes, but not limited to, assists at EXE or MEM uop writeback like AVX* load/store/gather/scatter (non-FP GSSE-assist ) , assists generated by ROB like PEBS and RTIT, Uncore trap, RAR (Remote Action Request) and CET (Control flow Enforcement Technology) assists. the event also counts for Machine Ordering count.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xc1", + "UMask": "0x08", + "EventName": "ASSISTS.PAGE_FAULT", + "BriefDescription": "ASSISTS.PAGE_FAULT", + "PublicDescription": "ASSISTS.PAGE_FAULT", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xc1", + "UMask": "0x10", + "EventName": "ASSISTS.SSE_AVX_MIX", + "BriefDescription": "ASSISTS.SSE_AVX_MIX", + "PublicDescription": "ASSISTS.SSE_AVX_MIX", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xc1", + "UMask": "0x1b", + "EventName": "ASSISTS.ANY", + "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.", + "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware. Examples include AD (page Access Dirty), FP and AVX related assists.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xc2", + "UMask": "0x01", + "EventName": "UOPS_RETIRED.HEAVY", + "BriefDescription": "Retired uops except the last uop of each instruction.", + "PublicDescription": "Counts the number of retired micro-operations (uops) except the last uop of each instruction. An instruction that is decoded into less than two uops does not contribute to the count.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x02", + "EventName": "UOPS_RETIRED.SLOTS", + "BriefDescription": "This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance for example, as measured by the instructions-per-cycle metric.", + "PublicDescription": "This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance for example, as measured by the instructions-per-cycle metric. Software can use this event as the numerator for the Retiring metric (or top-level category) of the Top-down Microarchitecture Analysis method.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x02", + "EventName": "UOPS_RETIRED.STALLS", + "BriefDescription": "Cycles without actually retired uops.", + "PublicDescription": "This event counts cycles without actually retired uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x02", + "EventName": "UOPS_RETIRED.CYCLES", + "BriefDescription": "Cycles with retired uop(s).", + "PublicDescription": "Counts cycles where at least one uop has retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x04", + "EventName": "UOPS_RETIRED.MS", + "BriefDescription": "UOPS_RETIRED.MS", + "PublicDescription": "UOPS_RETIRED.MS", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x3F7", + "MSRValue": "0x8", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc3", + "UMask": "0x01", + "EventName": "MACHINE_CLEARS.COUNT", + "BriefDescription": "Number of machine clears (nukes) of any type.", + "PublicDescription": "Counts the number of machine clears (nukes) of any type.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xc3", + "UMask": "0x02", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "BriefDescription": "Number of machine clears due to memory ordering conflicts.", + "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xc3", + "UMask": "0x04", + "EventName": "MACHINE_CLEARS.SMC", + "BriefDescription": "Self-modifying code (SMC) detected.", + "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xc4", + "UMask": "0x00", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "BriefDescription": "All branch instructions retired.", + "PublicDescription": "Counts all branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x01", + "EventName": "BR_INST_RETIRED.COND_TAKEN", + "BriefDescription": "Taken conditional branch instructions retired.", + "PublicDescription": "Counts taken conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x02", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "BriefDescription": "Direct and indirect near call instructions retired.", + "PublicDescription": "Counts both direct and indirect near call instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x08", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "BriefDescription": "Return instructions retired.", + "PublicDescription": "Counts return instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x10", + "EventName": "BR_INST_RETIRED.COND_NTAKEN", + "BriefDescription": "Not taken branch instructions retired.", + "PublicDescription": "Counts not taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x11", + "EventName": "BR_INST_RETIRED.COND", + "BriefDescription": "Conditional branch instructions retired.", + "PublicDescription": "Counts conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x20", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "BriefDescription": "Taken branch instructions retired.", + "PublicDescription": "Counts taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x40", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "BriefDescription": "Far branch instructions retired.", + "PublicDescription": "Counts far branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x80", + "EventName": "BR_INST_RETIRED.INDIRECT", + "BriefDescription": "Indirect near branch instructions retired (excluding returns)", + "PublicDescription": "Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x00", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "BriefDescription": "All mispredicted branch instructions retired.", + "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x01", + "EventName": "BR_MISP_RETIRED.COND_TAKEN", + "BriefDescription": "number of branch instructions retired that were mispredicted and taken.", + "PublicDescription": "Counts taken conditional mispredicted branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x02", + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", + "BriefDescription": "Mispredicted indirect CALL retired.", + "PublicDescription": "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x08", + "EventName": "BR_MISP_RETIRED.RET", + "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x10", + "EventName": "BR_MISP_RETIRED.COND_NTAKEN", + "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", + "PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x11", + "EventName": "BR_MISP_RETIRED.COND", + "BriefDescription": "Mispredicted conditional branch instructions retired.", + "PublicDescription": "Counts mispredicted conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x20", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", + "PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x41", + "EventName": "BR_MISP_RETIRED.COND_TAKEN_COST", + "BriefDescription": "Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "PublicDescription": "Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x42", + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL_COST", + "BriefDescription": "Mispredicted indirect CALL retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "PublicDescription": "Mispredicted indirect CALL retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x44", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_COST", + "BriefDescription": "All mispredicted branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "PublicDescription": "All mispredicted branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x48", + "EventName": "BR_MISP_RETIRED.RET_COST", + "BriefDescription": "Mispredicted ret instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "PublicDescription": "Mispredicted ret instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x50", + "EventName": "BR_MISP_RETIRED.COND_NTAKEN_COST", + "BriefDescription": "Mispredicted non-taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "PublicDescription": "Mispredicted non-taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x51", + "EventName": "BR_MISP_RETIRED.COND_COST", + "BriefDescription": "Mispredicted conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "PublicDescription": "Mispredicted conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x60", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN_COST", + "BriefDescription": "Mispredicted taken near branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "PublicDescription": "Mispredicted taken near branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x80", + "EventName": "BR_MISP_RETIRED.INDIRECT", + "BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)", + "PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0xc0", + "EventName": "BR_MISP_RETIRED.INDIRECT_COST", + "BriefDescription": "Mispredicted near indirect branch instructions retired (excluding returns). This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "PublicDescription": "Mispredicted near indirect branch instructions retired (excluding returns). This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x02", + "EventName": "FRONTEND_RETIRED.MISP_ANT", + "BriefDescription": "Mispredicted Retired ANT branches", + "PublicDescription": "ANT retired branches that got just mispredicted", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x9", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "EventName": "FRONTEND_RETIRED.DSB_MISS", + "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", + "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x11", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "EventName": "FRONTEND_RETIRED.ITLB_MISS", + "BriefDescription": "Retired Instructions who experienced iTLB true miss.", + "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x14", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "EventName": "FRONTEND_RETIRED.L1I_MISS", + "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", + "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x12", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "EventName": "FRONTEND_RETIRED.L2_MISS", + "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", + "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x13", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", + "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x600106", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x608006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x601006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", + "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x600206", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x100206", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x610006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x602006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x600406", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x620006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x604006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x600806", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "EventName": "FRONTEND_RETIRED.STLB_MISS", + "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.", + "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x15", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "EventName": "FRONTEND_RETIRED.UNKNOWN_BRANCH", + "BriefDescription": "FRONTEND_RETIRED.UNKNOWN_BRANCH", + "PublicDescription": "FRONTEND_RETIRED.UNKNOWN_BRANCH", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x17", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "EventName": "FRONTEND_RETIRED.MS_FLOWS", + "BriefDescription": "FRONTEND_RETIRED.MS_FLOWS", + "PublicDescription": "FRONTEND_RETIRED.MS_FLOWS", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x8", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", + "BriefDescription": "Retired Instructions who experienced DSB miss.", + "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x1", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "EventName": "FRONTEND_RETIRED.ANY_ANT", + "BriefDescription": "Retired ANT branches", + "PublicDescription": "Always Not Taken (ANT) conditional retired branches (no BTB entry and not mispredicted)", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x9", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x03", + "EventName": "FRONTEND_RETIRED.LATE_SWPF", + "BriefDescription": "I-Cache miss too close to Code Prefetch Instruction", + "PublicDescription": "Number of Instruction Cache demand miss in shadow of an on-going i-fetch cache-line triggered by PREFETCHIT0/1 instructions", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0xA", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x01", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x02", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x03", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR", + "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x04", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x08", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x10", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x18", + "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x20", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x40", + "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x60", + "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x80", + "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0xfc", + "EventName": "FP_ARITH_INST_RETIRED.VECTOR", + "BriefDescription": "Number of any Vector retired FP arithmetic instructions", + "PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x01", + "EventName": "RTM_RETIRED.START", + "BriefDescription": "Number of times an RTM execution started.", + "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x02", + "EventName": "RTM_RETIRED.COMMIT", + "BriefDescription": "Number of times an RTM execution successfully committed", + "PublicDescription": "Counts the number of times RTM commit succeeded.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x04", + "EventName": "RTM_RETIRED.ABORTED", + "BriefDescription": "Number of times an RTM execution aborted.", + "PublicDescription": "Counts the number of times RTM abort was triggered.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x08", + "EventName": "RTM_RETIRED.ABORTED_MEM", + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", + "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x20", + "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", + "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", + "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x40", + "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", + "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", + "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x80", + "EventName": "RTM_RETIRED.ABORTED_EVENTS", + "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 3 categories (e.g. interrupt)", + "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 3 categories (e.g. interrupt).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcc", + "UMask": "0x20", + "EventName": "MISC_RETIRED.LBR_INSERTS", + "BriefDescription": "Increments whenever there is an update to the LBR array.", + "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "1009", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "20011", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "503", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "101", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "2003", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "53", + "MSRIndex": "0x3F6", + "MSRValue": "0x400", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_2048", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "23", + "MSRIndex": "0x3F6", + "MSRValue": "0x800", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x02", + "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE", + "BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.", + "PublicDescription": "Counts Retired memory accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) trigger covering all stores uops for sampling by the PEBS Store Latency Facility. The facility is described in Intel SDM Volume 3 section 19.9.8", + "Counter": "0", + "PEBScounters": "0", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcf", + "UMask": "0x01", + "EventName": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", + "BriefDescription": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", + "PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcf", + "UMask": "0x02", + "EventName": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", + "BriefDescription": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", + "PublicDescription": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcf", + "UMask": "0x03", + "EventName": "FP_ARITH_INST_RETIRED2.SCALAR", + "BriefDescription": "Number of all Scalar Half-Precision FP arithmetic instructions(1) retired - regular and complex.", + "PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcf", + "UMask": "0x04", + "EventName": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", + "BriefDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", + "PublicDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcf", + "UMask": "0x08", + "EventName": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", + "BriefDescription": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", + "PublicDescription": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcf", + "UMask": "0x10", + "EventName": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", + "BriefDescription": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", + "PublicDescription": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcf", + "UMask": "0x1c", + "EventName": "FP_ARITH_INST_RETIRED2.VECTOR", + "BriefDescription": "Number of all Vector (also called packed) Half-Precision FP arithmetic instructions(1) retired.", + "PublicDescription": "FP_ARITH_INST_RETIRED2.VECTOR", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x09", + "EventName": "MEM_INST_RETIRED.STLB_HIT_LOADS", + "BriefDescription": "Retired load instructions that hit the STLB.", + "PublicDescription": "Number of retired load instructions with a clean hit in the 2nd-level TLB (STLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x0a", + "EventName": "MEM_INST_RETIRED.STLB_HIT_STORES", + "BriefDescription": "Retired store instructions that hit the STLB.", + "PublicDescription": "Number of retired store instructions that hit in the 2nd-level TLB (STLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x11", + "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", + "BriefDescription": "Retired load instructions that miss the STLB.", + "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x12", + "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", + "BriefDescription": "Retired store instructions that miss the STLB.", + "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x21", + "EventName": "MEM_INST_RETIRED.LOCK_LOADS", + "BriefDescription": "Retired load instructions with locked access.", + "PublicDescription": "Counts retired load instructions with locked access.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x41", + "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", + "BriefDescription": "Retired load instructions that split across a cacheline boundary.", + "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x42", + "EventName": "MEM_INST_RETIRED.SPLIT_STORES", + "BriefDescription": "Retired store instructions that split across a cacheline boundary.", + "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x81", + "EventName": "MEM_INST_RETIRED.ALL_LOADS", + "BriefDescription": "Retired load instructions.", + "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x82", + "EventName": "MEM_INST_RETIRED.ALL_STORES", + "BriefDescription": "Retired store instructions.", + "PublicDescription": "Counts all retired store instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x83", + "EventName": "MEM_INST_RETIRED.ANY", + "BriefDescription": "All retired memory instructions.", + "PublicDescription": "Counts all retired memory instructions - loads and stores.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x01", + "EventName": "MEM_LOAD_RETIRED.L1_HIT", + "BriefDescription": "Retired load instructions with L1 cache hits as data sources", + "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x02", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "BriefDescription": "Retired load instructions with L2 cache hits as data sources", + "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x04", + "EventName": "MEM_LOAD_RETIRED.L3_HIT", + "BriefDescription": "Retired load instructions with L3 cache hits as data sources", + "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x08", + "EventName": "MEM_LOAD_RETIRED.L1_MISS", + "BriefDescription": "Retired load instructions missed L1 cache as data sources", + "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x10", + "EventName": "MEM_LOAD_RETIRED.L2_MISS", + "BriefDescription": "Retired load instructions missed L2 cache as data sources", + "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x20", + "EventName": "MEM_LOAD_RETIRED.L3_MISS", + "BriefDescription": "Retired load instructions missed L3 cache as data sources", + "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "50021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x40", + "EventName": "MEM_LOAD_RETIRED.FB_HIT", + "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.", + "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd2", + "UMask": "0x01", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd2", + "UMask": "0x02", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache", + "PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd2", + "UMask": "0x04", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", + "PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd2", + "UMask": "0x08", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", + "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required", + "PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd3", + "UMask": "0x01", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", + "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram", + "PublicDescription": "Retired load instructions which data sources missed L3 but serviced from local DRAM.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd3", + "UMask": "0x02", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "BriefDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "PublicDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd3", + "UMask": "0x04", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "BriefDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "PublicDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd3", + "UMask": "0x08", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "BriefDescription": "Retired load instructions whose data sources was forwarded from a remote cache", + "PublicDescription": "Retired load instructions whose data sources was forwarded from a remote cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd4", + "UMask": "0x04", + "EventName": "MEM_LOAD_MISC_RETIRED.UC", + "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.", + "PublicDescription": "Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xe0", + "UMask": "0x20", + "EventName": "MISC2_RETIRED.LFENCE", + "BriefDescription": "LFENCE instructions retired", + "PublicDescription": "number of LFENCE retired instructions", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xe5", + "UMask": "0x03", + "EventName": "MEM_UOP_RETIRED.ANY", + "BriefDescription": "Retired memory uops for any access", + "PublicDescription": "Number of retired micro-operations (uops) for load or store memory accesses", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xe7", + "UMask": "0x03", + "EventName": "INT_VEC_RETIRED.ADD_128", + "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.", + "PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vector instructions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xe7", + "UMask": "0x0c", + "EventName": "INT_VEC_RETIRED.ADD_256", + "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.", + "PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vector instructions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xe7", + "UMask": "0x10", + "EventName": "INT_VEC_RETIRED.VNNI_128", + "BriefDescription": "INT_VEC_RETIRED.VNNI_128", + "PublicDescription": "INT_VEC_RETIRED.VNNI_128", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xe7", + "UMask": "0x13", + "EventName": "INT_VEC_RETIRED.128BIT", + "BriefDescription": "INT_VEC_RETIRED.128BIT", + "PublicDescription": "INT_VEC_RETIRED.128BIT", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xe7", + "UMask": "0x20", + "EventName": "INT_VEC_RETIRED.VNNI_256", + "BriefDescription": "INT_VEC_RETIRED.VNNI_256", + "PublicDescription": "INT_VEC_RETIRED.VNNI_256", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xe7", + "UMask": "0x40", + "EventName": "INT_VEC_RETIRED.SHUFFLES", + "BriefDescription": "INT_VEC_RETIRED.SHUFFLES", + "PublicDescription": "INT_VEC_RETIRED.SHUFFLES", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xe7", + "UMask": "0x80", + "EventName": "INT_VEC_RETIRED.MUL_256", + "BriefDescription": "INT_VEC_RETIRED.MUL_256", + "PublicDescription": "INT_VEC_RETIRED.MUL_256", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xe7", + "UMask": "0xac", + "EventName": "INT_VEC_RETIRED.256BIT", + "BriefDescription": "INT_VEC_RETIRED.256BIT", + "PublicDescription": "INT_VEC_RETIRED.256BIT", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xec", + "UMask": "0x02", + "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", + "BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.", + "PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xec", + "UMask": "0x10", + "EventName": "CPU_CLK_UNHALTED.C01", + "BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state.", + "PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xec", + "UMask": "0x20", + "EventName": "CPU_CLK_UNHALTED.C02", + "BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state.", + "PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xec", + "UMask": "0x40", + "EventName": "CPU_CLK_UNHALTED.PAUSE", + "BriefDescription": "CPU_CLK_UNHALTED.PAUSE", + "PublicDescription": "CPU_CLK_UNHALTED.PAUSE", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xec", + "UMask": "0x40", + "EventName": "CPU_CLK_UNHALTED.PAUSE_INST", + "BriefDescription": "CPU_CLK_UNHALTED.PAUSE_INST", + "PublicDescription": "CPU_CLK_UNHALTED.PAUSE_INST", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0xec", + "UMask": "0x70", + "EventName": "CPU_CLK_UNHALTED.C0_WAIT", + "BriefDescription": "Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 ACPI state.", + "PublicDescription": "Counts core clocks when the thread is in the C0.1 or C0.2 power saving optimized states (TPAUSE or UMWAIT instructions) or running the PAUSE instruction.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "1" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F3FFC0002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.L3_HIT", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.L3_MISS", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F3FC00002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104000002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.DRAM", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C000002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "BriefDescription": "Counts demand data reads that have any type of response.", + "PublicDescription": "Counts demand data reads that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", + "BriefDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.", + "PublicDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", + "BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", + "PublicDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", + "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "PublicDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.REMOTE_DRAM", + "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to another socket.", + "PublicDescription": "Counts demand data reads that were supplied by DRAM attached to another socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x730000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.DRAM", + "BriefDescription": "Counts demand data reads that were supplied by DRAM.", + "PublicDescription": "Counts demand data reads that were supplied by DRAM.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HITM", + "BriefDescription": "Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HIT_WITH_FWD", + "BriefDescription": "Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x808000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104000004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.DRAM", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C000004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", + "BriefDescription": "Counts streaming stores that have any type of response.", + "PublicDescription": "Counts streaming stores that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10800", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F3FFC4477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.L3_HIT", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F003C4477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F04C04477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.REMOTE", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F33004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.L3_MISS", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F3FC04477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.REMOTE_DRAM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x730004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.DRAM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HITM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HIT_WITH_FWD", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x808004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_DRAM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x70C004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster. It does not count misses to the L3 which go to Local CXL Type 2 Memory or Local Non DRAM.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster. It does not count misses to the L3 which go to Local CXL Type 2 Memory or Local Non DRAM.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x70CC04477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.REMOTE_MEMORY", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x733004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.RFO_TO_CORE.L3_HIT_M", + "BriefDescription": "Counts demand reads for ownership (RFO), hardware prefetch RFOs (which bring data to L2), and software prefetches for exclusive ownership (PREFETCHW) that hit to a (M)odified cacheline in the L3 or snoop filter.", + "PublicDescription": "Counts demand reads for ownership (RFO), hardware prefetch RFOs (which bring data to L2), and software prefetches for exclusive ownership (PREFETCHW) that hit to a (M)odified cacheline in the L3 or snoop filter.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F80040022", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.MODIFIED_WRITE.ANY_RESPONSE", + "BriefDescription": "Counts writebacks of modified cachelines and streaming stores that have any type of response.", + "PublicDescription": "Counts writebacks of modified cachelines and streaming stores that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10808", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.WRITE_ESTIMATE.MEMORY", + "BriefDescription": "Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM)", + "PublicDescription": "Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM)", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFBFF80822", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data.", + "PublicDescription": "Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "PublicDescription": "Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "BriefDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "PublicDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HIT_WITH_FWD", + "BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "PublicDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x830000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HITM", + "BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.", + "PublicDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1030000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C4477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x830004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1030004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified).", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified).", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1830004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + } + ] +} \ No newline at end of file diff --git a/cmd/metrics/resources/perfmon/gnr/graniterapids_metrics.json b/cmd/metrics/resources/perfmon/gnr/graniterapids_metrics.json new file mode 100644 index 00000000..647e55e4 --- /dev/null +++ b/cmd/metrics/resources/perfmon/gnr/graniterapids_metrics.json @@ -0,0 +1,15158 @@ +{ + "Header": { + "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Metrics for Intel(R) Xeon(R) 6 Processor with P-cores0", + "DatePublished": "05/28/2025", + "Version": "1.02", + "Legend": "", + "TmaVersion": "5.01", + "TmaFlavor": "Full" + }, + "Metrics": [ + { + "MetricName": "cpu_operating_frequency", + "LegacyName": "metric_CPU operating frequency (in GHz)", + "Level": 1, + "BriefDescription": "CPU operating frequency (in GHz)", + "UnitOfMeasure": "GHz", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + } + ], + "Formula": "(a / b * c) / 1000000000", + "Category": "Freq", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "uncore_frequency", + "LegacyName": "metric_uncore frequency GHz", + "Level": 1, + "BriefDescription": "Uncore operating frequency in GHz", + "UnitOfMeasure": "GHz", + "Events": [ + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "b" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "(a / (b * socket_count) / 1000000000) / DURATIONTIMEINSECONDS", + "Category": "Freq", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "cpu_utilization", + "LegacyName": "metric_CPU utilization %", + "Level": 1, + "BriefDescription": "Percentage of time spent in the active CPU power state C0", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + }, + { + "Name": "TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "Category": "Util", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "cpi", + "LegacyName": "metric_CPI", + "Level": 1, + "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "CPI", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l1d_mpi", + "LegacyName": "metric_L1D MPI (includes data+rfo w/ prefetches)", + "Level": 1, + "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "L1D.REPLACEMENT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_mpi", + "LegacyName": "metric_L2 MPI (includes code+data+rfo w/ prefetches)", + "Level": 1, + "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "L2_LINES_IN.ALL", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "numa_reads_addressed_to_local_dram", + "LegacyName": "metric_NUMA %_Reads addressed to local DRAM", + "Level": 1, + "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", + "Alias": "c" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (a + b) / (a + b + c + d)", + "Category": "NUMA", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "numa_reads_addressed_to_remote_dram", + "LegacyName": "metric_NUMA %_Reads addressed to remote DRAM", + "Level": 1, + "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", + "Alias": "c" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (c + d) / (a + b + c + d)", + "Category": "NUMA", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_bandwidth_read", + "LegacyName": "metric_memory bandwidth read (MB/sec)", + "Level": 1, + "BriefDescription": "DDR memory read bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT_SCH0.RD", + "Alias": "a" + }, + { + "Name": "UNC_M_CAS_COUNT_SCH1.RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, MC", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_bandwidth_write", + "LegacyName": "metric_memory bandwidth write (MB/sec)", + "Level": 1, + "BriefDescription": "DDR memory write bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT_SCH0.WR", + "Alias": "a" + }, + { + "Name": "UNC_M_CAS_COUNT_SCH1.WR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, MC", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_bandwidth_total", + "LegacyName": "metric_memory bandwidth total (MB/sec)", + "Level": 1, + "BriefDescription": "DDR memory bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT_SCH0.RD", + "Alias": "a" + }, + { + "Name": "UNC_M_CAS_COUNT_SCH1.RD", + "Alias": "b" + }, + { + "Name": "UNC_M_CAS_COUNT_SCH0.WR", + "Alias": "c" + }, + { + "Name": "UNC_M_CAS_COUNT_SCH1.WR", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "((a + b + c + d) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, MC", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "upi_data_transmit_bw", + "LegacyName": "metric_UPI Data transmit BW (MB/sec) (only data)", + "Level": 1, + "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_UPI_TxL_FLITS.ALL_DATA", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * (64 / 9.0) / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW", + "ResolutionLevels": "UPI, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "loads_per_instr", + "LegacyName": "metric_loads per instr", + "Level": 1, + "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "stores_per_instr", + "LegacyName": "metric_stores per instr", + "Level": 1, + "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l1d_demand_data_read_hits_per_instr", + "LegacyName": "metric_L1D demand data read hits per instr", + "Level": 1, + "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L1_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", + "LegacyName": "metric_L1-I code read misses (w/ prefetches) per instr", + "Level": 1, + "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "L2_RQSTS.ALL_CODE_RD", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, I-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_demand_data_read_hits_per_instr", + "LegacyName": "metric_L2 demand data read hits per instr", + "Level": 1, + "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_demand_data_read_mpi", + "LegacyName": "metric_L2 demand data read MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_demand_code_mpi", + "LegacyName": "metric_L2 demand code MPI", + "Level": 1, + "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "L2_RQSTS.CODE_RD_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, I-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_data_read_mpi_demand_plus_prefetch", + "LegacyName": "metric_LLC data read MPI (demand+prefetch)", + "Level": 1, + "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF", + "Alias": "c" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "(a + b + c) / d", + "Category": "MPI, D-side", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_code_read_mpi_demand_plus_prefetch", + "LegacyName": "metric_LLC code read MPI (demand+prefetch)", + "Level": 1, + "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "Alias": "b" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "b / d", + "Category": "MPI, I-side", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_latency", + "LegacyName": "metric_Average LLC demand data read miss latency (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "Latency", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_latency_for_local_requests", + "LegacyName": "metric_Average LLC demand data read miss latency for LOCAL requests (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to local memory in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "Latency", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_latency_for_remote_requests", + "LegacyName": "metric_Average LLC demand data read miss latency for REMOTE requests (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to remote memory in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "Latency", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_to_dram_latency", + "LegacyName": "metric_Average LLC demand data read miss to DRAM latency (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to DRAM in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "Latency", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "itlb_2nd_level_mpi", + "LegacyName": "metric_ITLB (2nd level) MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, I-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "dtlb_2nd_level_load_mpi", + "LegacyName": "metric_DTLB (2nd level) load MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "dtlb_2nd_level_store_mpi", + "LegacyName": "metric_DTLB (2nd level) store MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_read", + "LegacyName": "metric_IO_bandwidth_disk_or_network_writes (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_write", + "LegacyName": "metric_IO_bandwidth_disk_or_network_reads (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_read_l3_miss", + "LegacyName": "metric_IO % of inbound reads that miss L3", + "Level": 1, + "BriefDescription": "The percent of inbound reads initiated by IO that miss the L3 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_partial_write_l3_miss", + "LegacyName": "metric_IO % of inbound partial writes that miss L3", + "Level": 1, + "BriefDescription": "The percent of inbound partial writes initiated by IO that miss the L3 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_RFO", + "Alias": "c" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ((b + d) / (a + c) )", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_full_write_l3_miss", + "LegacyName": "metric_IO % of inbound full writes that miss L3", + "Level": 1, + "BriefDescription": "The percent of inbound full cache line writes initiated by IO that miss the L3 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * (b / a)", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "percent_uops_delivered_from_decoded_icache", + "LegacyName": "metric_% Uops delivered from decoded Icache (DSB)", + "Level": 1, + "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "LSD.UOPS", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (a / (a + b + c + d) )", + "Category": "I-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline", + "LegacyName": "metric_% Uops delivered from legacy decode pipeline (MITE)", + "Level": 1, + "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "LSD.UOPS", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (b / (a + b + c + d) )", + "Category": "I-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "percent_uops_delivered_from_microcode_sequencer", + "LegacyName": "metric_% Uops delivered from microcode sequencer (MS)", + "Level": 1, + "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "LSD.UOPS", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (c / (a + b + c + d) )", + "Category": "I-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_read_local", + "LegacyName": "metric_IO bandwidth read local (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the local CPU socket.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_read_remote", + "LegacyName": "metric_IO bandwidth read remote (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from a remote CPU socket.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_write_local", + "LegacyName": "metric_IO bandwidth write local (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the local CPU socket.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_write_remote", + "LegacyName": "metric_IO bandwidth write remote (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to a remote CPU socket.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_msi", + "LegacyName": "metric_IO MSI per sec", + "Level": 1, + "BriefDescription": "Message Signaled Interrupts (MSI) per second sent by the integrated I/O traffic controller (IIO) to System Configuration Controller (Ubox).", + "UnitOfMeasure": "per second", + "Events": [ + { + "Name": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX_POSTED", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a) / DURATIONTIMEINSECONDS", + "Category": "IO", + "ResolutionLevels": "IIO, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_miss_local_memory_bandwidth_read", + "LegacyName": "metric_llc_miss_local_memory_bandwidth_read_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.READS_LOCAL", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_miss_local_memory_bandwidth_write", + "LegacyName": "metric_llc_miss_local_memory_bandwidth_write_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.WRITES_LOCAL", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_miss_remote_memory_bandwidth_read", + "LegacyName": "metric_llc_miss_remote_memory_bandwidth_read_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.READS_REMOTE", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_miss_remote_memory_bandwidth_write", + "LegacyName": "metric_llc_miss_remote_memory_bandwidth_write_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.WRITES_REMOTE", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "upi_data_receive_bw", + "LegacyName": "metric_UPI Data receive BW (MB/sec) (only data)", + "Level": 1, + "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data receive bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_UPI_RxL_FLITS.ALL_DATA", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * (64 / 9.0) / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW", + "ResolutionLevels": "UPI, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "iio_bandwidth_read", + "LegacyName": "metric_IIO_bandwidth_read (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth observed by the integrated I/O traffic controller (IIO) of IO reads that are initiated by end device controllers that are requesting memory from the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 4 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "IO, BW", + "ResolutionLevels": "IIO, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "iio_bandwidth_write", + "LegacyName": "metric_IIO_bandwidth_write (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth observed by the integrated I/O traffic controller (IIO) of IO writes that are initiated by end device controllers that are writing memory to the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 4 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "IO, BW", + "ResolutionLevels": "IIO, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "cpu_cstate_c0", + "LegacyName": "metric_CPU_cstate_C0", + "Level": 1, + "BriefDescription": "The average number of cores that are in cstate C0 as observed by the power control unit (PCU).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_P_CLOCKTICKS", + "Alias": "a" + }, + { + "Name": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C0", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "(b / a[0]) * socket_count", + "Category": "Power", + "ResolutionLevels": "SOCKET, SYSTEM, PCU", + "MetricGroup": "cpu_cstate" + }, + { + "MetricName": "cpu_cstate_c6", + "LegacyName": "metric_CPU_cstate_C6", + "Level": 1, + "BriefDescription": "The average number of cores are in cstate C6 as observed by the power control unit (PCU).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_P_CLOCKTICKS", + "Alias": "a" + }, + { + "Name": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C6", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "(b / a[0]) * socket_count", + "Category": "Power", + "ResolutionLevels": "SOCKET, SYSTEM, PCU", + "MetricGroup": "cpu_cstate" + }, + { + "MetricName": "io_bandwidth_read_l3_miss", + "LegacyName": "metric_IO_bandwidth_read_L3_miss (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of inbound IO reads that are initiated by end device controllers that are requesting memory from the CPU and miss the L3 cache.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_write_l3_miss", + "LegacyName": "metric_IO_bandwidth_write_L3_miss (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of inbound IO writes that are initiated by end device controllers that are writing memory to the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Bottleneck_Mispredictions", + "LegacyName": "metric_TMA_Bottleneck_Mispredictions", + "Level": 1, + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.MS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "h" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "i" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "j" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "k" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "l" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "m" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "n" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "o" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "p" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "q" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "r" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "s" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "t" + }, + { + "Name": "DECODE.LCP", + "Alias": "u" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "v" + } + ], + "Constants": [], + "Formula": "100 * ( 1 - ( 10 * ( a / ( b ) ) * ( max( ( c / ( d + e + f + g ) ) * ( 1 - h / ( i - j ) ) , 0.0001 ) ) / ( c / ( d + e + f + g ) ) ) ) * ( ( c / ( d + e + f + g ) ) + ( ( k / ( d + e + f + g ) - l / ( b ) ) ) * ( ( ( c / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - l / ( b ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) * m / ( n ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) )", + "BaseFormula": " 100 * ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * ( tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Mispredictions" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Mispredictions > 20", + "ThresholdIssues": "$issueBM" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BadSpec;BrMispredicts;BvMP", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Big_Code", + "LegacyName": "metric_TMA_Bottleneck_Big_Code", + "Level": 1, + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "j" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "k" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "l" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "m" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "n" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "o" + }, + { + "Name": "DECODE.LCP", + "Alias": "p" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "q" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( h / ( i ) ) + ( j / ( i ) ) + ( k / ( i ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) )", + "BaseFormula": " 100 * tma_fetch_latency * ( tma_itlb_misses + tma_icache_misses + tma_unknown_branches ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Big_Code" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Big_Code > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvBC;BigFootprint;Fed;Frontend;IcMiss;MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Instruction_Fetch_BW", + "LegacyName": "metric_TMA_Bottleneck_Instruction_Fetch_BW", + "Level": 1, + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_CYCLES_ANY", + "Alias": "a_a" + }, + { + "Name": "IDQ.MITE_CYCLES_OK", + "Alias": "a_b" + }, + { + "Name": "IDQ.DSB_CYCLES_ANY", + "Alias": "a_c" + }, + { + "Name": "IDQ.DSB_CYCLES_OK", + "Alias": "a_d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "UOPS_RETIRED.MS", + "Alias": "g" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "h" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "i" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "j" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "k" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "l" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "m" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "n" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "o" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "p" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "q" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "r" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "s" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "t" + }, + { + "Name": "DECODE.LCP", + "Alias": "u" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "v" + }, + { + "Name": "INST_RETIRED.REP_ITERATION", + "Alias": "w" + }, + { + "Name": "UOPS_RETIRED.MS:c1", + "Alias": "x" + }, + { + "Name": "IDQ.MS_CYCLES_ANY", + "Alias": "y" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a / ( a + b + c + d ) - e / ( f ) ) - ( 1 - ( 10 * ( g / ( f ) ) * ( max( ( h / ( a + b + c + d ) ) * ( 1 - i / ( j - k ) ) , 0.0001 ) ) / ( h / ( a + b + c + d ) ) ) ) * ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) - ( ( 1 - w / x ) * ( ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) * ( ( ( 1 - ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * m / ( n ) ) + ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) * ( max( ( h / ( a + b + c + d ) ) * ( 1 - i / ( j - k ) ) , 0.0001 ) ) / ( h / ( a + b + c + d ) ) ) / ( ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) + ( ( 1 - ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * m / ( n ) ) + ( q / ( n ) ) ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) + ( max( 0 , ( a / ( a + b + c + d ) - e / ( f ) ) - ( ( l / ( a + b + c + d ) - e / ( f ) ) ) ) ) * ( max( y , x / ( s / t ) ) / ( z if smt_on else ( n ) ) / 2 ) / ( ( ( a_a - a_b ) / ( z if smt_on else ( n ) ) / 2 ) + ( ( a_c - a_d ) / ( z if smt_on else ( n ) ) / 2 ) + ( max( y , x / ( s / t ) ) / ( z if smt_on else ( n ) ) / 2 ) ) ) ) ) - ( 100 * ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( p / ( n ) ) + ( o / ( n ) ) + ( q / ( n ) ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) )", + "BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - inst_retired.rep_iteration / uops_retired.ms:c1 ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_ms ) ) ) ) - tma_bottleneck_big_code", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Instruction_Fetch_BW" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Instruction_Fetch_BW > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvFB;Fed;FetchBW;Frontend", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Cache_Memory_Bandwidth", + "LegacyName": "metric_TMA_Bottleneck_Cache_Memory_Bandwidth", + "Level": 1, + "BriefDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "Alias": "a_a" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD:retire_latency", + "Alias": "a_b" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Alias": "a_c" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT:retire_latency", + "Alias": "a_d" + }, + { + "Name": "L1D_PEND_MISS.FB_FULL", + "Alias": "a_e" + }, + { + "Name": "MEM_INST_RETIRED.STLB_HIT_LOADS", + "Alias": "a_f" + }, + { + "Name": "MEM_INST_RETIRED.STLB_HIT_LOADS:retire_latency", + "Alias": "a_g" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a_h" + }, + { + "Name": "LD_BLOCKS.STORE_FORWARD", + "Alias": "a_i" + }, + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "a_j" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "a_l" + }, + { + "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "a_m" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a_n" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS:retire_latency", + "Alias": "a_o" + }, + { + "Name": "MEM_INST_RETIRED.SPLIT_LOADS", + "Alias": "a_p" + }, + { + "Name": "MEM_INST_RETIRED.SPLIT_LOADS:retire_latency", + "Alias": "a_q" + }, + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a_r" + }, + { + "Name": "MEM_LOAD_COMPLETED.L1_MISS_ANY", + "Alias": "a_s" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "h" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Alias": "i" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "k" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD:c4", + "Alias": "l" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "m" + }, + { + "Name": "XQ.FULL_CYCLES", + "Alias": "n" + }, + { + "Name": "L1D_PEND_MISS.L2_STALLS", + "Alias": "o" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Alias": "p" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS:retire_latency", + "Alias": "q" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "r" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Alias": "u" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD:retire_latency", + "Alias": "v" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "w" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "x" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "y" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": "20", + "Alias": "dependentloadsweight" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + }, + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "s" + } + ], + "Formula": "100 * ( ( ( a / ( b + c + d + e ) ) * ( ( ( f / ( g ) ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( min( g , l ) ) / ( g ) ) / ( ( ( min( g , l ) ) / ( g ) ) + ( ( min( g , m ) ) / ( g ) - ( ( min( g , l ) ) / ( g ) ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( ( j - f ) / ( g ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( n + o ) / ( g ) ) / ( ( ( ( min( ( p * q ) , p * ( 79 * ( ( ( g ) / r ) * s / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / r ) * s / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( q > = 0 ) else ( p * ( 79 * ( ( ( g ) / r ) * s / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / r ) * s / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( u * v ) , u * ( 81 * ( ( ( g ) / r ) * s / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / r ) * s / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( v > = 0 ) else ( u * ( 81 * ( ( ( g ) / r ) * s / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / r ) * s / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( w / ( w + x ) ) ) * ( 1 + ( y / z ) / 2 ) / ( g ) ) + ( ( ( min( ( a_a * a_b ) , a_a * ( 79 * ( ( ( g ) / r ) * s / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / r ) * s / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_b > = 0 ) else ( a_a * ( 79 * ( ( ( g ) / r ) * s / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / r ) * s / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( u * v ) , u * ( 79 * ( ( ( g ) / r ) * s / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / r ) * s / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( v > = 0 ) else ( u * ( 79 * ( ( ( g ) / r ) * s / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / r ) * s / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 - ( w / ( w + x ) ) ) ) * ( 1 + ( y / z ) / 2 ) / ( g ) ) + ( ( min( ( a_c * a_d ) , a_c * ( 37 * ( ( ( g ) / r ) * s / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / r ) * s / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_d > = 0 ) else ( a_c * ( 37 * ( ( ( g ) / r ) * s / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / r ) * s / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 + ( y / z ) / 2 ) / ( g ) ) + ( ( n + o ) / ( g ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( max( ( h - i ) / ( g ) , 0 ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( a_e / ( g ) ) / ( ( ( min( ( a_f * a_g ) , a_f * ( 7 ) ) if ( a_g > = 0 ) else ( a_f * ( 7 ) ) ) / ( g ) + ( a_h / ( g ) ) ) + ( 13 * a_i / ( g ) ) + ( min( 2 * ( a_j - y - z ) * dependentloadsweight / 100 , max( a_l - a_m , 0 ) ) / ( g ) ) + ( ( a_n * a_o ) / ( g ) ) + ( ( min( ( a_p * a_q ) , a_p * ( a_r / a_s ) ) if ( a_q > = 0 ) else ( a_p * ( a_r / a_s ) ) ) / ( g ) ) + ( a_e / ( g ) ) ) ) ) )", + "BaseFormula": " 100 * ( ( tma_memory_bound * ( tma_dram_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_mem_bandwidth / ( tma_mem_bandwidth + tma_mem_latency ) ) ) + ( tma_memory_bound * ( tma_l3_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_sq_full / ( tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full ) ) ) + ( tma_memory_bound * ( tma_l1_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_fb_full / ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_fb_full ) ) ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Cache_Memory_Bandwidth" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Cache_Memory_Bandwidth > 20", + "ThresholdIssues": "$issueBW" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMB;Mem;MemoryBW;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Cache_Memory_Latency", + "LegacyName": "metric_TMA_Bottleneck_Cache_Memory_Latency", + "Level": 1, + "BriefDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "Alias": "a_a" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD:retire_latency", + "Alias": "a_b" + }, + { + "Name": "XQ.FULL_CYCLES", + "Alias": "a_c" + }, + { + "Name": "L1D_PEND_MISS.L2_STALLS", + "Alias": "a_d" + }, + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "a_e" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "a_g" + }, + { + "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "a_h" + }, + { + "Name": "MEM_INST_RETIRED.STLB_HIT_LOADS", + "Alias": "a_i" + }, + { + "Name": "MEM_INST_RETIRED.STLB_HIT_LOADS:retire_latency", + "Alias": "a_j" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a_k" + }, + { + "Name": "LD_BLOCKS.STORE_FORWARD", + "Alias": "a_l" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a_m" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS:retire_latency", + "Alias": "a_n" + }, + { + "Name": "MEM_INST_RETIRED.SPLIT_LOADS", + "Alias": "a_o" + }, + { + "Name": "MEM_INST_RETIRED.SPLIT_LOADS:retire_latency", + "Alias": "a_p" + }, + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a_q" + }, + { + "Name": "MEM_LOAD_COMPLETED.L1_MISS_ANY", + "Alias": "a_r" + }, + { + "Name": "L1D_PEND_MISS.FB_FULL", + "Alias": "a_s" + }, + { + "Name": "MEM_INST_RETIRED.SPLIT_STORES", + "Alias": "a_t" + }, + { + "Name": "MEM_INST_RETIRED.SPLIT_STORES:retire_latency", + "Alias": "a_u" + }, + { + "Name": "MEM_STORE_RETIRED.L2_HIT", + "Alias": "a_v" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "a_w" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "a_x" + }, + { + "Name": "OCR.DEMAND_RFO.L3_MISS:ocr_msr_val=0x103b800002", + "Alias": "a_y" + }, + { + "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "Alias": "a_z" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "OCR.STREAMING_WR.ANY_RESPONSE", + "Alias": "b_a" + }, + { + "Name": "MEM_INST_RETIRED.STLB_HIT_STORES", + "Alias": "b_b" + }, + { + "Name": "MEM_INST_RETIRED.STLB_HIT_STORES:retire_latency", + "Alias": "b_c" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "b_d" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b_e" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "h" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Alias": "i" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "k" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "l" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD:c4", + "Alias": "m" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Alias": "n" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT:retire_latency", + "Alias": "o" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "p" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "s" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "t" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Alias": "u" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS:retire_latency", + "Alias": "v" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Alias": "w" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD:retire_latency", + "Alias": "x" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "y" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": "20", + "Alias": "dependentloadsweight" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + }, + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "q" + }, + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( ( a / ( b + c + d + e ) ) * ( ( ( f / ( g ) ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( min( g , l ) ) / ( g ) - ( ( min( g , m ) ) / ( g ) ) ) / ( ( ( min( g , m ) ) / ( g ) ) + ( ( min( g , l ) ) / ( g ) - ( ( min( g , m ) ) / ( g ) ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( ( j - f ) / ( g ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( min( ( n * o ) , n * ( 37 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( o > = 0 ) else ( n * ( 37 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 + ( s / t ) / 2 ) / ( g ) ) / ( ( ( ( min( ( u * v ) , u * ( 79 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( v > = 0 ) else ( u * ( 79 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( w * x ) , w * ( 81 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( x > = 0 ) else ( w * ( 81 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( y / ( y + z ) ) ) * ( 1 + ( s / t ) / 2 ) / ( g ) ) + ( ( ( min( ( a_a * a_b ) , a_a * ( 79 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_b > = 0 ) else ( a_a * ( 79 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( w * x ) , w * ( 79 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( x > = 0 ) else ( w * ( 79 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 - ( y / ( y + z ) ) ) ) * ( 1 + ( s / t ) / 2 ) / ( g ) ) + ( ( min( ( n * o ) , n * ( 37 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( o > = 0 ) else ( n * ( 37 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 + ( s / t ) / 2 ) / ( g ) ) + ( ( a_c + a_d ) / ( g ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( i - j ) / ( g ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( max( ( h - i ) / ( g ) , 0 ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( min( 2 * ( a_e - s - t ) * dependentloadsweight / 100 , max( a_g - a_h , 0 ) ) / ( g ) ) / ( ( ( min( ( a_i * a_j ) , a_i * ( 7 ) ) if ( a_j > = 0 ) else ( a_i * ( 7 ) ) ) / ( g ) + ( a_k / ( g ) ) ) + ( 13 * a_l / ( g ) ) + ( min( 2 * ( a_e - s - t ) * dependentloadsweight / 100 , max( a_g - a_h , 0 ) ) / ( g ) ) + ( ( a_m * a_n ) / ( g ) ) + ( ( min( ( a_o * a_p ) , a_o * ( a_q / a_r ) ) if ( a_p > = 0 ) else ( a_o * ( a_q / a_r ) ) ) / ( g ) ) + ( a_s / ( g ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( max( ( h - i ) / ( g ) , 0 ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( a_m * a_n ) / ( g ) ) / ( ( ( min( ( a_i * a_j ) , a_i * ( 7 ) ) if ( a_j > = 0 ) else ( a_i * ( 7 ) ) ) / ( g ) + ( a_k / ( g ) ) ) + ( 13 * a_l / ( g ) ) + ( min( 2 * ( a_e - s - t ) * dependentloadsweight / 100 , max( a_g - a_h , 0 ) ) / ( g ) ) + ( ( a_m * a_n ) / ( g ) ) + ( ( min( ( a_o * a_p ) , a_o * ( a_q / a_r ) ) if ( a_p > = 0 ) else ( a_o * ( a_q / a_r ) ) ) / ( g ) ) + ( a_s / ( g ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( max( ( h - i ) / ( g ) , 0 ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( min( ( a_o * a_p ) , a_o * ( a_q / a_r ) ) if ( a_p > = 0 ) else ( a_o * ( a_q / a_r ) ) ) / ( g ) ) / ( ( ( min( ( a_i * a_j ) , a_i * ( 7 ) ) if ( a_j > = 0 ) else ( a_i * ( 7 ) ) ) / ( g ) + ( a_k / ( g ) ) ) + ( 13 * a_l / ( g ) ) + ( min( 2 * ( a_e - s - t ) * dependentloadsweight / 100 , max( a_g - a_h , 0 ) ) / ( g ) ) + ( ( a_m * a_n ) / ( g ) ) + ( ( min( ( a_o * a_p ) , a_o * ( a_q / a_r ) ) if ( a_p > = 0 ) else ( a_o * ( a_q / a_r ) ) ) / ( g ) ) + ( a_s / ( g ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( k / ( g ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( min( ( a_t * a_u ) , a_t * 1 ) if ( a_u > = 0 ) else ( a_t * 1 ) ) / ( g ) ) / ( ( ( ( a_v * ( 10 ) * ( 1 - ( a_m / a_w ) ) ) + ( 1 - ( a_m / a_w ) ) * ( min( g , a_x ) ) ) / ( g ) ) + ( ( ( 170 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_y + ( 81 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_z ) / ( g ) ) + ( ( min( ( a_t * a_u ) , a_t * 1 ) if ( a_u > = 0 ) else ( a_t * 1 ) ) / ( g ) ) + ( 9 * b_a / ( g ) ) + ( ( min( ( b_b * b_c ) , b_b * ( 7 ) ) if ( b_c > = 0 ) else ( b_b * ( 7 ) ) ) / ( g ) + ( b_d / ( b_e if smt_on else ( g ) ) ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( k / ( g ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( ( a_v * ( 10 ) * ( 1 - ( a_m / a_w ) ) ) + ( 1 - ( a_m / a_w ) ) * ( min( g , a_x ) ) ) / ( g ) ) / ( ( ( ( a_v * ( 10 ) * ( 1 - ( a_m / a_w ) ) ) + ( 1 - ( a_m / a_w ) ) * ( min( g , a_x ) ) ) / ( g ) ) + ( ( ( 170 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_y + ( 81 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_z ) / ( g ) ) + ( ( min( ( a_t * a_u ) , a_t * 1 ) if ( a_u > = 0 ) else ( a_t * 1 ) ) / ( g ) ) + ( 9 * b_a / ( g ) ) + ( ( min( ( b_b * b_c ) , b_b * ( 7 ) ) if ( b_c > = 0 ) else ( b_b * ( 7 ) ) ) / ( g ) + ( b_d / ( b_e if smt_on else ( g ) ) ) ) ) ) ) )", + "BaseFormula": " 100 * ( ( tma_memory_bound * ( tma_dram_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_mem_latency / ( tma_mem_bandwidth + tma_mem_latency ) ) ) + ( tma_memory_bound * ( tma_l3_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_l3_hit_latency / ( tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full ) ) ) + ( tma_memory_bound * tma_l2_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) + ( tma_memory_bound * ( tma_l1_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_l1_latency_dependency / ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_fb_full ) ) ) + ( tma_memory_bound * ( tma_l1_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_lock_latency / ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_fb_full ) ) ) + ( tma_memory_bound * ( tma_l1_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_split_loads / ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_fb_full ) ) ) + ( tma_memory_bound * ( tma_store_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_split_stores / ( tma_store_latency + tma_false_sharing + tma_split_stores + tma_streaming_stores + tma_dtlb_store ) ) ) + ( tma_memory_bound * ( tma_store_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_store_latency / ( tma_store_latency + tma_false_sharing + tma_split_stores + tma_streaming_stores + tma_dtlb_store ) ) ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Cache_Memory_Latency" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Cache_Memory_Latency > 20", + "ThresholdIssues": "$issueLat" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvML;Mem;MemoryLat;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Memory_Data_TLBs", + "LegacyName": "metric_TMA_Bottleneck_Memory_Data_TLBs", + "Level": 1, + "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_COMPLETED.L1_MISS_ANY", + "Alias": "a_a" + }, + { + "Name": "L1D_PEND_MISS.FB_FULL", + "Alias": "a_b" + }, + { + "Name": "MEM_INST_RETIRED.STLB_HIT_STORES", + "Alias": "a_c" + }, + { + "Name": "MEM_INST_RETIRED.STLB_HIT_STORES:retire_latency", + "Alias": "a_d" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a_e" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "a_f" + }, + { + "Name": "MEM_STORE_RETIRED.L2_HIT", + "Alias": "a_g" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "a_h" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "a_i" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a_j" + }, + { + "Name": "OCR.DEMAND_RFO.L3_MISS:ocr_msr_val=0x103b800002", + "Alias": "a_m" + }, + { + "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "Alias": "a_n" + }, + { + "Name": "MEM_INST_RETIRED.SPLIT_STORES", + "Alias": "a_o" + }, + { + "Name": "MEM_INST_RETIRED.SPLIT_STORES:retire_latency", + "Alias": "a_p" + }, + { + "Name": "OCR.STREAMING_WR.ANY_RESPONSE", + "Alias": "a_q" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "f" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Alias": "g" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "h" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Alias": "i" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "k" + }, + { + "Name": "MEM_INST_RETIRED.STLB_HIT_LOADS", + "Alias": "l" + }, + { + "Name": "MEM_INST_RETIRED.STLB_HIT_LOADS:retire_latency", + "Alias": "m" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "n" + }, + { + "Name": "LD_BLOCKS.STORE_FORWARD", + "Alias": "o" + }, + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "p" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "q" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "r" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "t" + }, + { + "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "u" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "v" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS:retire_latency", + "Alias": "w" + }, + { + "Name": "MEM_INST_RETIRED.SPLIT_LOADS", + "Alias": "x" + }, + { + "Name": "MEM_INST_RETIRED.SPLIT_LOADS:retire_latency", + "Alias": "y" + }, + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "a_k" + }, + { + "Name": "20", + "Alias": "dependentloadsweight" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + }, + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( ( a / ( b + c + d + e ) ) * ( ( max( ( f - g ) / ( h ) , 0 ) ) / ( ( max( ( f - g ) / ( h ) , 0 ) ) + ( ( g - i ) / ( h ) ) + ( ( i - j ) / ( h ) ) + ( ( j / ( h ) ) ) + ( k / ( h ) ) ) ) * ( ( ( min( ( l * m ) , l * ( 7 ) ) if ( m > = 0 ) else ( l * ( 7 ) ) ) / ( h ) + ( n / ( h ) ) ) / ( ( ( min( ( l * m ) , l * ( 7 ) ) if ( m > = 0 ) else ( l * ( 7 ) ) ) / ( h ) + ( n / ( h ) ) ) + ( 13 * o / ( h ) ) + ( min( 2 * ( p - q - r ) * dependentloadsweight / 100 , max( t - u , 0 ) ) / ( h ) ) + ( ( v * w ) / ( h ) ) + ( ( min( ( x * y ) , x * ( z / a_a ) ) if ( y > = 0 ) else ( x * ( z / a_a ) ) ) / ( h ) ) + ( a_b / ( h ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( k / ( h ) ) / ( ( max( ( f - g ) / ( h ) , 0 ) ) + ( ( g - i ) / ( h ) ) + ( ( i - j ) / ( h ) ) + ( ( j / ( h ) ) ) + ( k / ( h ) ) ) ) * ( ( ( min( ( a_c * a_d ) , a_c * ( 7 ) ) if ( a_d > = 0 ) else ( a_c * ( 7 ) ) ) / ( h ) + ( a_e / ( a_f if smt_on else ( h ) ) ) ) / ( ( ( ( a_g * ( 10 ) * ( 1 - ( v / a_h ) ) ) + ( 1 - ( v / a_h ) ) * ( min( h , a_i ) ) ) / ( h ) ) + ( ( ( 170 * ( ( ( h ) / a_j ) * a_k / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_m + ( 81 * ( ( ( h ) / a_j ) * a_k / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_n ) / ( h ) ) + ( ( min( ( a_o * a_p ) , a_o * 1 ) if ( a_p > = 0 ) else ( a_o * 1 ) ) / ( h ) ) + ( 9 * a_q / ( h ) ) + ( ( min( ( a_c * a_d ) , a_c * ( 7 ) ) if ( a_d > = 0 ) else ( a_c * ( 7 ) ) ) / ( h ) + ( a_e / ( a_f if smt_on else ( h ) ) ) ) ) ) ) )", + "BaseFormula": " 100 * ( ( tma_memory_bound * ( tma_l1_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_dtlb_load / ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_fb_full ) ) ) + ( tma_memory_bound * ( tma_store_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_dtlb_store / ( tma_store_latency + tma_false_sharing + tma_split_stores + tma_streaming_stores + tma_dtlb_store ) ) ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Memory_Data_TLBs" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Memory_Data_TLBs > 20", + "ThresholdIssues": "$issueTLB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMT;Mem;MemoryTLB;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Memory_Synchronization", + "LegacyName": "metric_TMA_Bottleneck_Memory_Synchronization", + "Level": 1, + "BriefDescription": "Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Alias": "a_c" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD:retire_latency", + "Alias": "a_d" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "a_e" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "a_f" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "Alias": "a_g" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD:retire_latency", + "Alias": "a_h" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Alias": "a_i" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT:retire_latency", + "Alias": "a_j" + }, + { + "Name": "XQ.FULL_CYCLES", + "Alias": "a_k" + }, + { + "Name": "L1D_PEND_MISS.L2_STALLS", + "Alias": "a_l" + }, + { + "Name": "OCR.DEMAND_RFO.L3_MISS:ocr_msr_val=0x103b800002", + "Alias": "a_m" + }, + { + "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "Alias": "a_n" + }, + { + "Name": "MEM_STORE_RETIRED.L2_HIT", + "Alias": "a_o" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a_p" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "a_q" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "a_r" + }, + { + "Name": "MEM_INST_RETIRED.SPLIT_STORES", + "Alias": "a_s" + }, + { + "Name": "MEM_INST_RETIRED.SPLIT_STORES:retire_latency", + "Alias": "a_t" + }, + { + "Name": "OCR.STREAMING_WR.ANY_RESPONSE", + "Alias": "a_u" + }, + { + "Name": "MEM_INST_RETIRED.STLB_HIT_STORES", + "Alias": "a_v" + }, + { + "Name": "MEM_INST_RETIRED.STLB_HIT_STORES:retire_latency", + "Alias": "a_w" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a_x" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "a_y" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "a_z" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b_a" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "b_b" + }, + { + "Name": "MACHINE_CLEARS.MEMORY_ORDERING", + "Alias": "b_c" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "b_d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "h" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Alias": "i" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "k" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "l" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD:c4", + "Alias": "m" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Alias": "n" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM:retire_latency", + "Alias": "o" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "Alias": "p" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD:retire_latency", + "Alias": "q" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "r" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "s" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", + "Alias": "t" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM:retire_latency", + "Alias": "u" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "Alias": "v" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM:retire_latency", + "Alias": "w" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Alias": "x" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS:retire_latency", + "Alias": "y" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "a_a" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + }, + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a / ( b + c + d + e ) ) * ( ( ( ( f / ( g ) ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( min( g , l ) ) / ( g ) - ( ( min( g , m ) ) / ( g ) ) ) / ( ( ( min( g , m ) ) / ( g ) ) + ( ( min( g , l ) ) / ( g ) - ( ( min( g , m ) ) / ( g ) ) ) ) ) * ( ( ( n * o ) + ( p * q ) ) * ( 1 + ( r / s ) / 2 ) / ( g ) ) / ( ( ( t * u ) * ( 1 + ( r / s ) / 2 ) / ( g ) ) + ( ( v * w ) * ( 1 + ( r / s ) / 2 ) / ( g ) ) + ( ( ( n * o ) + ( p * q ) ) * ( 1 + ( r / s ) / 2 ) / ( g ) ) ) + ( ( ( j - f ) / ( g ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( ( min( ( x * y ) , x * ( 79 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( y > = 0 ) else ( x * ( 79 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_c * a_d ) , a_c * ( 81 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_d > = 0 ) else ( a_c * ( 81 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( a_e / ( a_e + a_f ) ) ) * ( 1 + ( r / s ) / 2 ) / ( g ) ) + ( ( ( min( ( a_g * a_h ) , a_g * ( 79 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_h > = 0 ) else ( a_g * ( 79 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_c * a_d ) , a_c * ( 79 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_d > = 0 ) else ( a_c * ( 79 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 - ( a_e / ( a_e + a_f ) ) ) ) * ( 1 + ( r / s ) / 2 ) / ( g ) ) ) / ( ( ( ( min( ( x * y ) , x * ( 79 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( y > = 0 ) else ( x * ( 79 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_c * a_d ) , a_c * ( 81 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_d > = 0 ) else ( a_c * ( 81 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( a_e / ( a_e + a_f ) ) ) * ( 1 + ( r / s ) / 2 ) / ( g ) ) + ( ( ( min( ( a_g * a_h ) , a_g * ( 79 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_h > = 0 ) else ( a_g * ( 79 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_c * a_d ) , a_c * ( 79 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_d > = 0 ) else ( a_c * ( 79 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 - ( a_e / ( a_e + a_f ) ) ) ) * ( 1 + ( r / s ) / 2 ) / ( g ) ) + ( ( min( ( a_i * a_j ) , a_i * ( 37 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_j > = 0 ) else ( a_i * ( 37 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 + ( r / s ) / 2 ) / ( g ) ) + ( ( a_k + a_l ) / ( g ) ) ) + ( ( k / ( g ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( 170 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_m + ( 81 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_n ) / ( g ) ) / ( ( ( ( ( a_o * ( 10 ) * ( 1 - ( a_p / a_q ) ) ) + ( 1 - ( a_p / a_q ) ) * ( min( g , a_r ) ) ) / ( g ) ) + ( ( ( 170 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_m + ( 81 * ( ( ( g ) / z ) * a_a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_n ) / ( g ) ) + ( ( min( ( a_s * a_t ) , a_s * 1 ) if ( a_t > = 0 ) else ( a_s * 1 ) ) / ( g ) ) + ( 9 * a_u / ( g ) ) + ( ( min( ( a_v * a_w ) , a_v * ( 7 ) ) if ( a_w > = 0 ) else ( a_v * ( 7 ) ) ) / ( g ) + ( a_x / ( a_y if smt_on else ( g ) ) ) ) ) - ( ( ( a_o * ( 10 ) * ( 1 - ( a_p / a_q ) ) ) + ( 1 - ( a_p / a_q ) ) * ( min( g , a_r ) ) ) / ( g ) ) ) ) + ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - a_z / ( b_a ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( b_b / ( b + c + d + e ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - a_z / ( b_a ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( b_b / ( b + c + d + e ) ) ) ) * ( 1 - b_c / b_d ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - a_z / ( b_a ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( b_b / ( b + c + d + e ) ) ) ) * ( 1 - b_c / b_d ) , 0.0001 ) ) ) ) )", + "BaseFormula": " 100 * ( tma_memory_bound * ( ( tma_dram_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_mem_latency / ( tma_mem_bandwidth + tma_mem_latency ) ) * tma_remote_cache / ( tma_local_mem + tma_remote_mem + tma_remote_cache ) + ( tma_l3_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_contested_accesses + tma_data_sharing ) / ( tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full ) + ( tma_store_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * tma_false_sharing / ( ( tma_store_latency + tma_false_sharing + tma_split_stores + tma_streaming_stores + tma_dtlb_store ) - tma_store_latency ) ) + tma_machine_clears * ( 1 - tma_other_nukes / ( tma_other_nukes ) ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Memory_Synchronization" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_Bottleneck_Memory_Synchronization > 10", + "ThresholdIssues": "$issueSyncxn" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMS;LockCont;Mem;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Compute_Bound_Est", + "LegacyName": "metric_TMA_Bottleneck_Compute_Bound_Est", + "Level": 1, + "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "e" + }, + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + }, + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.C02", + "Alias": "i" + }, + { + "Name": "EXE.AMX_BUSY", + "Alias": "j" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "k" + }, + { + "Name": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "Alias": "l" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "m" + }, + { + "Name": "EXE_ACTIVITY.2_3_PORTS_UTIL", + "Alias": "n" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "o" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "p" + }, + { + "Name": "UOPS_EXECUTED.CYCLES_GE_3", + "Alias": "q" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "r" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) * ( f / ( g ) ) / ( ( f / ( g ) ) + ( h / ( g ) + ( i / ( g ) ) ) + ( j / ( k if smt_on else ( g ) ) ) + ( ( ( max( l - h , 0 ) / ( g ) ) * ( g ) + ( m + ( d / ( b + c + d + a ) ) * n ) ) / ( g ) if ( f < ( o - p ) ) else ( m + ( d / ( b + c + d + a ) ) * n ) / ( g ) ) ) ) + ( ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) * ( j / ( k if smt_on else ( g ) ) ) / ( ( f / ( g ) ) + ( h / ( g ) + ( i / ( g ) ) ) + ( j / ( k if smt_on else ( g ) ) ) + ( ( ( max( l - h , 0 ) / ( g ) ) * ( g ) + ( m + ( d / ( b + c + d + a ) ) * n ) ) / ( g ) if ( f < ( o - p ) ) else ( m + ( d / ( b + c + d + a ) ) * n ) / ( g ) ) ) ) + ( ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) * ( ( ( ( max( l - h , 0 ) / ( g ) ) * ( g ) + ( m + ( d / ( b + c + d + a ) ) * n ) ) / ( g ) if ( f < ( o - p ) ) else ( m + ( d / ( b + c + d + a ) ) * n ) / ( g ) ) / ( ( f / ( g ) ) + ( h / ( g ) + ( i / ( g ) ) ) + ( j / ( k if smt_on else ( g ) ) ) + ( ( ( max( l - h , 0 ) / ( g ) ) * ( g ) + ( m + ( d / ( b + c + d + a ) ) * n ) ) / ( g ) if ( f < ( o - p ) ) else ( m + ( d / ( b + c + d + a ) ) * n ) / ( g ) ) ) ) * ( ( q / ( g ) ) / ( ( max( l - h , 0 ) / ( g ) ) + ( m / ( g ) ) + ( r / ( g ) ) + ( q / ( g ) ) ) ) ) )", + "BaseFormula": " 100 * ( ( tma_core_bound * tma_divider / ( tma_divider + tma_serializing_operation + tma_amx_busy + tma_ports_utilization ) ) + ( tma_core_bound * tma_amx_busy / ( tma_divider + tma_serializing_operation + tma_amx_busy + tma_ports_utilization ) ) + ( tma_core_bound * ( tma_ports_utilization / ( tma_divider + tma_serializing_operation + tma_amx_busy + tma_ports_utilization ) ) * ( tma_ports_utilized_3m / ( tma_ports_utilized_0 + tma_ports_utilized_1 + tma_ports_utilized_2 + tma_ports_utilized_3m ) ) ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Compute_Bound_Est" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Compute_Bound_Est > 20", + "ThresholdIssues": "$issueComp" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvCB;Cor", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Irregular_Overhead", + "LegacyName": "metric_TMA_Bottleneck_Irregular_Overhead", + "Level": 1, + "BriefDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.REP_ITERATION", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_CYCLES_OK", + "Alias": "a_a" + }, + { + "Name": "IDQ.DSB_CYCLES_ANY", + "Alias": "a_b" + }, + { + "Name": "IDQ.DSB_CYCLES_OK", + "Alias": "a_c" + }, + { + "Name": "UOPS_RETIRED.MS", + "Alias": "a_d" + }, + { + "Name": "MACHINE_CLEARS.MEMORY_ORDERING", + "Alias": "a_e" + }, + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "a_f" + }, + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "a_g" + }, + { + "Name": "CPU_CLK_UNHALTED.C02", + "Alias": "a_h" + }, + { + "Name": "RS.EMPTY_RESOURCE", + "Alias": "a_i" + }, + { + "Name": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "Alias": "a_j" + }, + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "a_k" + }, + { + "Name": "EXE.AMX_BUSY", + "Alias": "a_l" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "a_m" + }, + { + "Name": "EXE_ACTIVITY.2_3_PORTS_UTIL", + "Alias": "a_n" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "a_o" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "a_p" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "a_q" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "a_r" + }, + { + "Name": "UOPS_RETIRED.MS:c1", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "h" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "i" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "j" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "k" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "l" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "m" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "n" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "o" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "p" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "q" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "r" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "s" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "t" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "u" + }, + { + "Name": "DECODE.LCP", + "Alias": "v" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "w" + }, + { + "Name": "IDQ.MS_CYCLES_ANY", + "Alias": "x" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "y" + }, + { + "Name": "IDQ.MITE_CYCLES_ANY", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( ( 1 - a / b ) * ( ( ( c / ( d + e + f + g ) - h / ( i ) ) ) * ( ( ( 3 ) * j / ( k / l ) / ( m ) ) + ( n / ( m ) + ( o / ( m ) ) ) * ( ( ( 1 - ( ( p / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) ) * n / ( m ) ) + ( ( ( p / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) * n / ( m ) ) * ( max( ( p / ( d + e + f + g ) ) * ( 1 - q / ( r - s ) ) , 0.0001 ) ) / ( p / ( d + e + f + g ) ) ) / ( ( ( ( p / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) * n / ( m ) ) + ( ( 1 - ( ( p / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) ) * n / ( m ) ) + ( o / ( m ) ) ) ) / ( ( t / ( m ) ) + ( u / ( m ) ) + ( n / ( m ) + ( o / ( m ) ) ) + ( ( 3 ) * j / ( k / l ) / ( m ) ) + ( v / ( m ) ) + ( w / ( m ) ) ) + ( max( 0 , ( d / ( d + e + f + g ) - h / ( i ) ) - ( ( c / ( d + e + f + g ) - h / ( i ) ) ) ) ) * ( max( x , b / ( k / l ) ) / ( y if smt_on else ( m ) ) / 2 ) / ( ( ( z - a_a ) / ( y if smt_on else ( m ) ) / 2 ) + ( ( a_b - a_c ) / ( y if smt_on else ( m ) ) / 2 ) + ( max( x , b / ( k / l ) ) / ( y if smt_on else ( m ) ) / 2 ) ) ) ) + ( 10 * ( a_d / ( i ) ) * ( max( ( p / ( d + e + f + g ) ) * ( 1 - q / ( r - s ) ) , 0.0001 ) ) / ( p / ( d + e + f + g ) ) ) * ( p / ( d + e + f + g ) ) + ( ( max( 0 , ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) - ( p / ( d + e + f + g ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) - ( p / ( d + e + f + g ) ) ) ) * ( 1 - a_e / s ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) - ( p / ( d + e + f + g ) ) ) ) * ( 1 - a_e / s ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( g / ( d + e + f + g ) ) - ( a_f / ( d + e + f + g ) ) ) ) * ( ( a_g / ( m ) + ( a_h / ( m ) ) ) + a_i / ( m ) * ( max( a_j - a_g , 0 ) / ( m ) ) ) / ( ( a_k / ( m ) ) + ( a_g / ( m ) + ( a_h / ( m ) ) ) + ( a_l / ( y if smt_on else ( m ) ) ) + ( ( ( max( a_j - a_g , 0 ) / ( m ) ) * ( m ) + ( a_m + ( f / ( d + e + f + g ) ) * a_n ) ) / ( m ) if ( a_k < ( a_o - a_p ) ) else ( a_m + ( f / ( d + e + f + g ) ) * a_n ) / ( m ) ) ) ) + ( ( ( ( a_d / ( i ) ) / ( ( max( 0 , ( a_q / ( d + e + f + g ) ) - ( a_d / ( i ) ) ) ) + ( a_d / ( i ) ) ) ) * ( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * a_r / ( i ) ) / ( a_d / ( i ) ) ) ) * ( a_q / ( d + e + f + g ) ) ) )", + "BaseFormula": " 100 * ( ( ( 1 - inst_retired.rep_iteration / uops_retired.ms:c1 ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_ms ) ) ) + ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) * tma_branch_mispredicts + ( tma_machine_clears * tma_other_nukes / ( tma_other_nukes ) ) + ( tma_core_bound * ( tma_serializing_operation + rs.empty_resource / tma_info_thread_clks * tma_ports_utilized_0 ) / ( tma_divider + tma_serializing_operation + tma_amx_busy + tma_ports_utilization ) ) + ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * tma_heavy_operations ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Irregular_Overhead" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_Bottleneck_Irregular_Overhead > 10", + "ThresholdIssues": "$issueMS" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BvIO;Cor;Ret", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Other_Bottlenecks", + "LegacyName": "metric_TMA_Bottleneck_Other_Bottlenecks", + "Level": 1, + "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end. Examples include data-dependencies (Core Bound when Low ILP) and other unlisted memory-related stalls.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_CYCLES_ANY", + "Alias": "a_a" + }, + { + "Name": "IDQ.MITE_CYCLES_OK", + "Alias": "a_b" + }, + { + "Name": "IDQ.DSB_CYCLES_ANY", + "Alias": "a_c" + }, + { + "Name": "IDQ.DSB_CYCLES_OK", + "Alias": "a_d" + }, + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "a_e" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "a_f" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "a_g" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Alias": "a_h" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Alias": "a_i" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "a_j" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD:c4", + "Alias": "a_k" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "a_l" + }, + { + "Name": "XQ.FULL_CYCLES", + "Alias": "a_m" + }, + { + "Name": "L1D_PEND_MISS.L2_STALLS", + "Alias": "a_n" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Alias": "a_o" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS:retire_latency", + "Alias": "a_p" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a_q" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Alias": "a_t" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD:retire_latency", + "Alias": "a_u" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "a_v" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "a_w" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "a_x" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "a_y" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "Alias": "a_z" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": 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durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b_c > = 0 ) else ( b_b * ( 37 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) / ( ( ( ( min( ( a_o * a_p ) , a_o * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_p > = 0 ) else ( a_o * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_t * a_u ) , a_t * ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) 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i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_u > = 0 ) else ( a_t * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 - ( a_v / ( a_v + a_w ) ) ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( min( ( b_b * b_c ) , b_b * ( 37 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b_c > = 0 ) else ( b_b * ( 37 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( a_m + a_n ) / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( a_h - a_i ) / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( min( 2 * ( b_i - a_x - a_y ) * dependentloadsweight / 100 , max( b_k - b_l , 0 ) ) / ( i ) ) / ( ( ( min( ( b_e * b_f ) , b_e * ( 7 ) ) if ( b_f > = 0 ) else ( b_e * ( 7 ) ) ) / ( i ) + ( b_g / ( i ) ) ) + ( 13 * b_h / ( i ) ) + ( min( 2 * ( b_i - a_x - a_y ) * dependentloadsweight / 100 , max( b_k - b_l , 0 ) ) / ( i ) ) + ( ( b_m * b_n ) / ( i ) ) + ( ( min( ( b_o * b_p ) , b_o * ( b_q / b_r ) ) if ( b_p > = 0 ) else ( b_o * ( b_q / b_r ) ) ) / ( i ) ) + ( b_d / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( b_m * b_n ) / ( i ) ) / ( ( ( min( ( b_e * b_f ) , b_e * ( 7 ) ) if ( b_f > = 0 ) else ( b_e * ( 7 ) ) ) / ( i ) + ( b_g / ( i ) ) ) + ( 13 * b_h / ( i ) ) + ( min( 2 * ( b_i - a_x - a_y ) * dependentloadsweight / 100 , max( b_k - b_l , 0 ) ) / ( i ) ) + ( ( b_m * b_n ) / ( i ) ) + ( ( min( ( b_o * b_p ) , b_o * ( b_q / b_r ) ) if ( b_p > = 0 ) else ( b_o * ( b_q / b_r ) ) ) / ( i ) ) + ( b_d / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( min( ( b_o * b_p ) , b_o * ( b_q / b_r ) ) if ( b_p > = 0 ) else ( b_o * ( b_q / b_r ) ) ) / ( i ) ) / ( ( ( min( ( b_e * b_f ) , b_e * ( 7 ) ) if ( b_f > = 0 ) else ( b_e * ( 7 ) ) ) / ( i ) + ( b_g / ( i ) ) ) + ( 13 * b_h / ( i ) ) + ( min( 2 * ( b_i - a_x - a_y ) * dependentloadsweight / 100 , max( b_k - b_l , 0 ) ) / ( i ) ) + ( ( b_m * b_n ) / ( i ) ) + ( ( min( ( b_o * b_p ) , b_o * ( b_q / b_r ) ) if ( b_p > = 0 ) else ( b_o * ( b_q / b_r ) ) ) / ( i ) ) + ( b_d / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( a_j / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( min( ( b_s * b_t ) , b_s * 1 ) if ( b_t > = 0 ) else ( b_s * 1 ) ) / ( i ) ) / ( ( ( ( b_u * ( 10 ) * ( 1 - ( b_m / b_v ) ) ) + ( 1 - ( b_m / b_v ) ) * ( min( i , b_w ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_x + ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_y ) / ( i ) ) + ( ( min( ( b_s * b_t ) , b_s * 1 ) if ( b_t > = 0 ) else ( b_s * 1 ) ) / ( i ) ) + ( 9 * b_z / ( i ) ) + ( ( min( ( c_a * c_b ) , c_a * ( 7 ) ) if ( c_b > = 0 ) else ( c_a * ( 7 ) ) ) / ( i ) + ( c_c / ( z if smt_on else ( i ) ) ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( a_j / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( ( b_u * ( 10 ) * ( 1 - ( b_m / b_v ) ) ) + ( 1 - ( b_m / b_v ) ) * ( min( i , b_w ) ) ) / ( i ) ) / ( ( ( ( b_u * ( 10 ) * ( 1 - ( b_m / b_v ) ) ) + ( 1 - ( b_m / b_v ) ) * ( min( i , b_w ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_x + ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_y ) / ( i ) ) + ( ( min( ( b_s * b_t ) , b_s * 1 ) if ( b_t > = 0 ) else ( b_s * 1 ) ) / ( i ) ) + ( 9 * b_z / ( i ) ) + ( ( min( ( c_a * c_b ) , c_a * ( 7 ) ) if ( c_b > = 0 ) else ( c_a * ( 7 ) ) ) / ( i ) + ( c_c / ( z if smt_on else ( i ) ) ) ) ) ) ) ) ) + ( 100 * ( ( ( a_e / ( b + c + d + e ) ) * ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( min( ( b_e * b_f ) , b_e * ( 7 ) ) if ( b_f > = 0 ) else ( b_e * ( 7 ) ) ) / ( i ) + ( b_g / ( i ) ) ) / ( ( ( min( ( b_e * b_f ) , b_e * ( 7 ) ) if ( b_f > = 0 ) else ( b_e * ( 7 ) ) ) / ( i ) + ( b_g / ( i ) ) ) + ( 13 * b_h / ( i ) ) + ( min( 2 * ( b_i - a_x - a_y ) * dependentloadsweight / 100 , max( b_k - b_l , 0 ) ) / ( i ) ) + ( ( b_m * b_n ) / ( i ) ) + ( ( min( ( b_o * b_p ) , b_o * ( b_q / b_r ) ) if ( b_p > = 0 ) else ( b_o * ( b_q / b_r ) ) ) / ( i ) ) + ( b_d / ( i ) ) ) ) ) + ( ( a_e / ( b + c + d + e ) ) * ( ( a_j / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( min( ( c_a * c_b ) , c_a * ( 7 ) ) if ( c_b > = 0 ) else ( c_a * ( 7 ) ) ) / ( i ) + ( c_c / ( z if smt_on else ( i ) ) ) ) / ( ( ( ( b_u * ( 10 ) * ( 1 - ( b_m / b_v ) ) ) + ( 1 - ( b_m / b_v ) ) * ( min( i , b_w ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_x + ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_y ) / ( i ) ) + ( ( min( ( b_s * b_t ) , b_s * 1 ) if ( b_t > = 0 ) else ( b_s * 1 ) ) / ( i ) ) + ( 9 * b_z / ( i ) ) + ( ( min( ( c_a * c_b ) , c_a * ( 7 ) ) if ( c_b > = 0 ) else ( c_a * ( 7 ) ) ) / ( i ) + ( c_c / ( z if smt_on else ( i ) ) ) ) ) ) ) ) ) + ( 100 * ( ( a_e / ( b + c + d + e ) ) * ( ( ( ( a_f / ( i ) ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( min( i , a_l ) ) / ( i ) - ( ( min( i , a_k ) ) / ( i ) ) ) / ( ( ( min( i , a_k ) ) / ( i ) ) + ( ( min( i , a_l ) ) / ( i ) - ( ( min( i , a_k ) ) / ( i ) ) ) ) ) * ( ( ( c_d * c_e ) + ( c_f * c_g ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) / ( ( ( c_h * c_i ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( c_j * c_k ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( ( c_d * c_e ) + ( c_f * c_g ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) ) + ( ( ( a_i - a_f ) / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( ( min( ( a_o * a_p ) , a_o * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_p > = 0 ) else ( a_o * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_t * a_u ) , a_t * ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_u > = 0 ) else ( a_t * ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( a_v / ( a_v + a_w ) ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( ( min( ( a_z * b_a ) , a_z * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b_a > = 0 ) else ( a_z * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_t * a_u ) , a_t * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_u > = 0 ) else ( a_t * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 - ( a_v / ( a_v + a_w ) ) ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) ) / ( ( ( ( min( ( a_o * a_p ) , a_o * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_p > = 0 ) else ( a_o * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_t * a_u ) , a_t * ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_u > = 0 ) else ( a_t * ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( a_v / ( a_v + a_w ) ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( ( min( ( a_z * b_a ) , a_z * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b_a > = 0 ) else ( a_z * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( a_t * a_u ) , a_t * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( a_u > = 0 ) else ( a_t * ( 79 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 - ( a_v / ( a_v + a_w ) ) ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( min( ( b_b * b_c ) , b_b * ( 37 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b_c > = 0 ) else ( b_b * ( 37 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 + ( a_x / a_y ) / 2 ) / ( i ) ) + ( ( a_m + a_n ) / ( i ) ) ) + ( ( a_j / ( i ) ) / ( ( max( ( a_g - a_h ) / ( i ) , 0 ) ) + ( ( a_h - a_i ) / ( i ) ) + ( ( a_i - a_f ) / ( i ) ) + ( ( a_f / ( i ) ) ) + ( a_j / ( i ) ) ) ) * ( ( ( 170 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_x + ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_y ) / ( i ) ) / ( ( ( ( ( b_u * ( 10 ) * ( 1 - ( b_m / b_v ) ) ) + ( 1 - ( b_m / b_v ) ) * ( min( i , b_w ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_x + ( 81 * ( ( ( i ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_y ) / ( i ) ) + ( ( min( ( b_s * b_t ) , b_s * 1 ) if ( b_t > = 0 ) else ( b_s * 1 ) ) / ( i ) ) + ( 9 * b_z / ( i ) ) + ( ( min( ( c_a * c_b ) , c_a * ( 7 ) ) if ( c_b > = 0 ) else ( c_a * ( 7 ) ) ) / ( i ) + ( c_c / ( z if smt_on else ( i ) ) ) ) ) - ( ( ( b_u * ( 10 ) * ( 1 - ( b_m / b_v ) ) ) + ( 1 - ( b_m / b_v ) ) * ( min( i , b_w ) ) ) / ( i ) ) ) ) + ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - c_l / v ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - c_l / v ) , 0.0001 ) ) ) ) ) ) + ( 100 * ( ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_e / ( b + c + d + e ) ) ) ) * ( c_m / ( i ) ) / ( ( c_m / ( i ) ) + ( c_n / ( i ) + ( c_o / ( i ) ) ) + ( c_p / ( z if smt_on else ( i ) ) ) + ( ( ( max( c_q - c_n , 0 ) / ( i ) ) * ( i ) + ( c_r + ( d / ( b + c + d + e ) ) * c_s ) ) / ( i ) if ( c_m < ( c_t - a_g ) ) else ( c_r + ( d / ( b + c + d + e ) ) * c_s ) / ( i ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_e / ( b + c + d + e ) ) ) ) * ( c_p / ( z if smt_on else ( i ) ) ) / ( ( c_m / ( i ) ) + ( c_n / ( i ) + ( c_o / ( i ) ) ) + ( c_p / ( z if smt_on else ( i ) ) ) + ( ( ( max( c_q - c_n , 0 ) / ( i ) ) * ( i ) + ( c_r + ( d / ( b + c + d + e ) ) * c_s ) ) / ( i ) if ( c_m < ( c_t - a_g ) ) else ( c_r + ( d / ( b + c + d + e ) ) * c_s ) / ( i ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_e / ( b + c + d + e ) ) ) ) * ( ( ( ( max( c_q - c_n , 0 ) / ( i ) ) * ( i ) + ( c_r + ( d / ( b + c + d + e ) ) * c_s ) ) / ( i ) if ( c_m < ( c_t - a_g ) ) else ( c_r + ( d / ( b + c + d + e ) ) * c_s ) / ( i ) ) / ( ( c_m / ( i ) ) + ( c_n / ( i ) + ( c_o / ( i ) ) ) + ( c_p / ( z if smt_on else ( i ) ) ) + ( ( ( max( c_q - c_n , 0 ) / ( i ) ) * ( i ) + ( c_r + ( d / ( b + c + d + e ) ) * c_s ) ) / ( i ) if ( c_m < ( c_t - a_g ) ) else ( c_r + ( d / ( b + c + d + e ) ) * c_s ) / ( i ) ) ) ) * ( ( c_u / ( i ) ) / ( ( max( c_q - c_n , 0 ) / ( i ) ) + ( c_r / ( i ) ) + ( c_v / ( i ) ) + ( c_u / ( i ) ) ) ) ) ) ) + ( 100 * ( ( ( 1 - w / x ) * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) * ( ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) / ( ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) + ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( k / ( i ) ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) + ( max( 0 , ( b / ( b + c + d + e ) - f / ( g ) ) - ( ( a / ( b + c + d + e ) - f / ( g ) ) ) ) ) * ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) / ( ( ( a_a - a_b ) / ( z if smt_on else ( i ) ) / 2 ) + ( ( a_c - a_d ) / ( z if smt_on else ( i ) ) / 2 ) + ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2 ) ) ) ) + ( 10 * ( r / ( g ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) * ( s / ( b + c + d + e ) ) + ( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - c_l / v ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - c_l / v ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_e / ( b + c + d + e ) ) ) ) * ( ( c_n / ( i ) + ( c_o / ( i ) ) ) + c_w / ( i ) * ( max( c_q - c_n , 0 ) / ( i ) ) ) / ( ( c_m / ( i ) ) + ( c_n / ( i ) + ( c_o / ( i ) ) ) + ( c_p / ( z if smt_on else ( i ) ) ) + ( ( ( max( c_q - c_n , 0 ) / ( i ) ) * ( i ) + ( c_r + ( d / ( b + c + d + e ) ) * c_s ) ) / ( i ) if ( c_m < ( c_t - a_g ) ) else ( c_r + ( d / ( b + c + d + e ) ) * c_s ) / ( i ) ) ) ) + ( ( ( ( r / ( g ) ) / ( ( max( 0 , ( c_x / ( b + c + d + e ) ) - ( r / ( g ) ) ) ) + ( r / ( g ) ) ) ) * ( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c_y / ( g ) ) / ( r / ( g ) ) ) ) * ( c_x / ( b + c + d + e ) ) ) ) ) + ( 100 * ( ( c_z + 2 * d_a + d_b ) / ( g ) ) ) + ( 100 * ( ( d / ( b + c + d + e ) ) - ( ( c_z + 2 * d_a + d_b ) / ( g ) ) - ( ( ( ( r / ( g ) ) / ( ( max( 0 , ( c_x / ( b + c + d + e ) ) - ( r / ( g ) ) ) ) + ( r / ( g ) ) ) ) * ( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c_y / ( g ) ) / ( r / ( g ) ) ) ) * ( c_x / ( b + c + d + e ) ) ) ) ) )", + "BaseFormula": " 100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Other_Bottlenecks" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Other_Bottlenecks > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvOB;Cor;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Branching_Overhead", + "LegacyName": "metric_TMA_Bottleneck_Branching_Overhead", + "Level": 1, + "BriefDescription": "Total pipeline cost of instructions used for program control-flow - a subset of the Retiring category in TMA. Examples include function calls; loops and alignments. (A lower bound)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "b" + }, + { + "Name": "INST_RETIRED.NOP", + "Alias": "c" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + 2 * b + c ) / ( d ) )", + "BaseFormula": " 100 * ( ( br_inst_retired.all_branches + 2 * br_inst_retired.near_call + inst_retired.nop ) / tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Branching_Overhead" + } + ], + "Formula": "a > 5", + "BaseFormula": "metric_TMA_Bottleneck_Branching_Overhead > 5", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvBO;Ret", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Useful_Work", + "LegacyName": "metric_TMA_Bottleneck_Useful_Work", + "Level": 1, + "BriefDescription": "Total pipeline cost of \"useful operations\" - the portion of Retiring category not covered by Branching_Overhead nor Irregular_Overhead.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "e" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "f" + }, + { + "Name": "INST_RETIRED.NOP", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + }, + { + "Name": "UOPS_RETIRED.MS", + "Alias": "i" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "j" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "k" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b + c + a + d ) ) - ( ( e + 2 * f + g ) / ( h ) ) - ( ( ( ( i / ( h ) ) / ( ( max( 0 , ( j / ( b + c + a + d ) ) - ( i / ( h ) ) ) ) + ( i / ( h ) ) ) ) * ( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * k / ( h ) ) / ( i / ( h ) ) ) ) * ( j / ( b + c + a + d ) ) ) )", + "BaseFormula": " 100 * ( tma_retiring - ( ( br_inst_retired.all_branches + 2 * br_inst_retired.near_call + inst_retired.nop ) / tma_info_thread_slots ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * tma_heavy_operations ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Useful_Work" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Useful_Work > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvUW;Ret", + "LocateWith": "" + }, + { + "MetricName": "Frontend_Bound", + "LegacyName": "metric_TMA_Frontend_Bound(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( a + b + c + d ) - e / ( f ) )", + "BaseFormula": " perf_metrics.frontend_bound / ( perf_metrics.frontend_bound + perf_metrics.bad_speculation + perf_metrics.retiring + perf_metrics.backend_bound ) - int_misc.uop_dropping / tma_info_thread_slots", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 15", + "BaseFormula": "metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvFB;BvIO;TmaL1;PGO", + "LocateWith": " FRONTEND_RETIRED.LATENCY_GE_4" + }, + { + "MetricName": "Fetch_Latency", + "LegacyName": "metric_TMA_..Fetch_Latency(%)", + "ParentCategory": "Frontend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b + c + d + e ) - f / ( g ) ) )", + "BaseFormula": " ( perf_metrics.fetch_latency / ( perf_metrics.frontend_bound + perf_metrics.bad_speculation + perf_metrics.retiring + perf_metrics.backend_bound ) - int_misc.uop_dropping / tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 15", + "BaseFormula": "metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Frontend;TmaL2", + "LocateWith": " FRONTEND_RETIRED.LATENCY_GE_16;FRONTEND_RETIRED.LATENCY_GE_8" + }, + { + "MetricName": "ICache_Misses", + "LegacyName": "metric_TMA_....ICache_Misses(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": " icache_data.stalls / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....ICache_Misses(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....ICache_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss", + "LocateWith": " FRONTEND_RETIRED.L2_MISS;FRONTEND_RETIRED.L1I_MISS" + }, + { + "MetricName": "Code_L2_Hit", + "LegacyName": "metric_TMA_......Code_L2_Hit(%)", + "ParentCategory": "ICache_Misses", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles the CPU was stalled due to instruction cache misses that hit in the L2 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FRONTEND_RETIRED.L1I_MISS", + "Alias": "a" + }, + { + "Name": "FRONTEND_RETIRED.L1I_MISS:retire_latency", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "FRONTEND_RETIRED.L2_MISS", + "Alias": "d" + }, + { + "Name": "FRONTEND_RETIRED.L2_MISS:retire_latency", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a * b ) / ( c ) - ( ( d * e ) / ( c ) ) ) )", + "BaseFormula": " max( 0 , ( frontend_retired.l1i_miss * frontend_retired.l1i_miss:retire_latency ) / tma_info_thread_clks - tma_code_l2_miss )", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Code_L2_Hit(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....ICache_Misses(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 15", + "BaseFormula": "metric_TMA_......Code_L2_Hit(%) > 5 & metric_TMA_....ICache_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "IcMiss;FetchLat;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Code_L2_Miss", + "LegacyName": "metric_TMA_......Code_L2_Miss(%)", + "ParentCategory": "ICache_Misses", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles the CPU was stalled due to instruction cache misses that miss in the L2 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FRONTEND_RETIRED.L2_MISS", + "Alias": "a" + }, + { + "Name": "FRONTEND_RETIRED.L2_MISS:retire_latency", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a * b ) / ( c ) )", + "BaseFormula": " ( frontend_retired.l2_miss * frontend_retired.l2_miss:retire_latency ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Code_L2_Miss(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....ICache_Misses(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 15", + "BaseFormula": "metric_TMA_......Code_L2_Miss(%) > 5 & metric_TMA_....ICache_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "IcMiss;FetchLat;Offcore", + "LocateWith": "" + }, + { + "MetricName": "ITLB_Misses", + "LegacyName": "metric_TMA_....ITLB_Misses(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": " icache_tag.stalls / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....ITLB_Misses(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....ITLB_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB", + "LocateWith": " FRONTEND_RETIRED.STLB_MISS;FRONTEND_RETIRED.ITLB_MISS" + }, + { + "MetricName": "Code_STLB_Hit", + "LegacyName": "metric_TMA_......Code_STLB_Hit(%)", + "ParentCategory": "ITLB_Misses", + "Level": 4, + "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) ITLB was missed by instructions fetches, that later on hit in second-level TLB (STLB)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FRONTEND_RETIRED.ITLB_MISS", + "Alias": "a" + }, + { + "Name": "FRONTEND_RETIRED.ITLB_MISS:retire_latency", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "FRONTEND_RETIRED.STLB_MISS", + "Alias": "d" + }, + { + "Name": "FRONTEND_RETIRED.STLB_MISS:retire_latency", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a * b ) / ( c ) - ( ( d * e ) / ( c ) ) ) )", + "BaseFormula": " max( 0 , ( frontend_retired.itlb_miss * frontend_retired.itlb_miss:retire_latency ) / tma_info_thread_clks - tma_code_stlb_miss )", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Code_STLB_Hit(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....ITLB_Misses(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 15", + "BaseFormula": "metric_TMA_......Code_STLB_Hit(%) > 5 & metric_TMA_....ITLB_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat;MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Code_STLB_Miss", + "LegacyName": "metric_TMA_......Code_STLB_Miss(%)", + "ParentCategory": "ITLB_Misses", + "Level": 4, + "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by instruction fetches, performing a hardware page walk", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FRONTEND_RETIRED.STLB_MISS", + "Alias": "a" + }, + { + "Name": "FRONTEND_RETIRED.STLB_MISS:retire_latency", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a * b ) / ( c ) )", + "BaseFormula": " ( frontend_retired.stlb_miss * frontend_retired.stlb_miss:retire_latency ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Code_STLB_Miss(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....ITLB_Misses(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 15", + "BaseFormula": "metric_TMA_......Code_STLB_Miss(%) > 5 & metric_TMA_....ITLB_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat;MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Code_STLB_Miss_4K", + "LegacyName": "metric_TMA_........Code_STLB_Miss_4K(%)", + "ParentCategory": "Code_STLB_Miss", + "Level": 5, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 4 KB pages for (instruction) code accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "ITLB_MISSES.WALK_COMPLETED_4K", + "Alias": "c" + }, + { + "Name": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) * c / ( c + d ) )", + "BaseFormula": " itlb_misses.walk_active / tma_info_thread_clks * itlb_misses.walk_completed_4k / ( itlb_misses.walk_completed_4k + itlb_misses.walk_completed_2m_4m )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Code_STLB_Miss_4K(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......Code_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....ITLB_Misses(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 5 & d > 10 & e > 15", + "BaseFormula": "metric_TMA_........Code_STLB_Miss_4K(%) > 5 & metric_TMA_......Code_STLB_Miss(%) > 5 & metric_TMA_....ITLB_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat;MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Code_STLB_Miss_2M", + "LegacyName": "metric_TMA_........Code_STLB_Miss_2M(%)", + "ParentCategory": "Code_STLB_Miss", + "Level": 5, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 2 or 4 MB pages for (instruction) code accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "c" + }, + { + "Name": "ITLB_MISSES.WALK_COMPLETED_4K", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) * c / ( d + c ) )", + "BaseFormula": " itlb_misses.walk_active / tma_info_thread_clks * itlb_misses.walk_completed_2m_4m / ( itlb_misses.walk_completed_4k + itlb_misses.walk_completed_2m_4m )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Code_STLB_Miss_2M(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......Code_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....ITLB_Misses(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 5 & d > 10 & e > 15", + "BaseFormula": "metric_TMA_........Code_STLB_Miss_2M(%) > 5 & metric_TMA_......Code_STLB_Miss(%) > 5 & metric_TMA_....ITLB_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat;MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Branch_Resteers", + "LegacyName": "metric_TMA_....Branch_Resteers(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) + ( c / ( b ) ) )", + "BaseFormula": " int_misc.clear_resteer_cycles / tma_info_thread_clks + tma_unknown_branches", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Branch_Resteers(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....Branch_Resteers(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "~overlap" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat", + "LocateWith": "BR_MISP_RETIRED.ALL_BRANCHES" + }, + { + "MetricName": "Mispredicts_Resteers", + "LegacyName": "metric_TMA_......Mispredicts_Resteers(%)", + "ParentCategory": "Branch_Resteers", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * h / ( i ) )", + "BaseFormula": " ( tma_branch_mispredicts / tma_bad_speculation ) * int_misc.clear_resteer_cycles / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Mispredicts_Resteers(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Branch_Resteers(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 15", + "BaseFormula": "metric_TMA_......Mispredicts_Resteers(%) > 5 & metric_TMA_....Branch_Resteers(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "$issueBM" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP", + "LocateWith": " INT_MISC.CLEAR_RESTEER_CYCLES" + }, + { + "MetricName": "Clears_Resteers", + "LegacyName": "metric_TMA_......Clears_Resteers(%)", + "ParentCategory": "Branch_Resteers", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + } + ], + "Constants": [], + "Formula": "100 * ( ( 1 - ( ( a / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * h / ( i ) )", + "BaseFormula": " ( 1 - ( tma_branch_mispredicts / tma_bad_speculation ) ) * int_misc.clear_resteer_cycles / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Clears_Resteers(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Branch_Resteers(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 15", + "BaseFormula": "metric_TMA_......Clears_Resteers(%) > 5 & metric_TMA_....Branch_Resteers(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "$issueMC" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;MachineClears", + "LocateWith": " INT_MISC.CLEAR_RESTEER_CYCLES" + }, + { + "MetricName": "Unknown_Branches", + "LegacyName": "metric_TMA_......Unknown_Branches(%)", + "ParentCategory": "Branch_Resteers", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": " int_misc.unknown_branch_cycles / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Unknown_Branches(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Branch_Resteers(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 15", + "BaseFormula": "metric_TMA_......Unknown_Branches(%) > 5 & metric_TMA_....Branch_Resteers(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;BvBC;FetchLat", + "LocateWith": " FRONTEND_RETIRED.UNKNOWN_BRANCH" + }, + { + "MetricName": "MS_Switches", + "LegacyName": "metric_TMA_....MS_Switches(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "a" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "b" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( 3 ) * a / ( b / c ) / ( d ) )", + "BaseFormula": " ( 3 ) * uops_retired.ms:c1:e1 / ( uops_retired.slots / uops_issued.any ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....MS_Switches(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....MS_Switches(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "$issueMC, $issueMS, $issueMV, $issueSO" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat;MicroSeq", + "LocateWith": " IDQ.MS_SWITCHES" + }, + { + "MetricName": "LCP", + "LegacyName": "metric_TMA_....LCP(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DECODE.LCP", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": " decode.lcp / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....LCP(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....LCP(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat", + "LocateWith": "" + }, + { + "MetricName": "DSB_Switches", + "LegacyName": "metric_TMA_....DSB_Switches(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": " dsb2mite_switches.penalty_cycles / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....DSB_Switches(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....DSB_Switches(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;FetchLat", + "LocateWith": " FRONTEND_RETIRED.DSB_MISS" + }, + { + "MetricName": "Fetch_Bandwidth", + "LegacyName": "metric_TMA_..Fetch_Bandwidth(%)", + "ParentCategory": "Frontend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( a + b + c + d ) - e / ( f ) ) - ( ( g / ( a + b + c + d ) - e / ( f ) ) ) ) )", + "BaseFormula": " max( 0 , tma_frontend_bound - tma_fetch_latency )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Fetch_Bandwidth(%)" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_..Fetch_Bandwidth(%) > 20", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchBW;Frontend;TmaL2", + "LocateWith": " FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1;FRONTEND_RETIRED.LATENCY_GE_1;FRONTEND_RETIRED.LATENCY_GE_2" + }, + { + "MetricName": "MITE", + "LegacyName": "metric_TMA_....MITE(%)", + "ParentCategory": "Fetch_Bandwidth", + "Level": 3, + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.MITE_CYCLES_ANY", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_CYCLES_OK", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a - b ) / ( c if smt_on else ( d ) ) / 2 )", + "BaseFormula": " ( idq.mite_cycles_any - idq.mite_cycles_ok ) / tma_info_core_core_clks / 2", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....MITE(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Bandwidth(%)" + } + ], + "Formula": "a > 10 & b > 20", + "BaseFormula": "metric_TMA_....MITE(%) > 10 & metric_TMA_..Fetch_Bandwidth(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;FetchBW", + "LocateWith": " FRONTEND_RETIRED.ANY_DSB_MISS" + }, + { + "MetricName": "Decoder0_Alone", + "LegacyName": "metric_TMA_......Decoder0_Alone(%)", + "ParentCategory": "MITE", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INST_DECODED.DECODERS:c1", + "Alias": "a" + }, + { + "Name": "INST_DECODED.DECODERS:c2", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a - b ) / ( c if smt_on else ( d ) ) / 2 )", + "BaseFormula": " ( inst_decoded.decoders:c1 - inst_decoded.decoders:c2 ) / tma_info_core_core_clks / 2", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Decoder0_Alone(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....MITE(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Bandwidth(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20", + "BaseFormula": "metric_TMA_......Decoder0_Alone(%) > 10 & metric_TMA_....MITE(%) > 10 & metric_TMA_..Fetch_Bandwidth(%) > 20", + "ThresholdIssues": "$issueD0" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "DSB", + "LegacyName": "metric_TMA_....DSB(%)", + "ParentCategory": "Fetch_Bandwidth", + "Level": 3, + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.DSB_CYCLES_ANY", + "Alias": "a" + }, + { + "Name": "IDQ.DSB_CYCLES_OK", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a - b ) / ( c if smt_on else ( d ) ) / 2 )", + "BaseFormula": " ( idq.dsb_cycles_any - idq.dsb_cycles_ok ) / tma_info_core_core_clks / 2", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....DSB(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Bandwidth(%)" + } + ], + "Formula": "a > 15 & b > 20", + "BaseFormula": "metric_TMA_....DSB(%) > 15 & metric_TMA_..Fetch_Bandwidth(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSB;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "MS", + "LegacyName": "metric_TMA_....MS(%)", + "ParentCategory": "Fetch_Bandwidth", + "Level": 3, + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the Microcode Sequencer (MS) unit - see Microcode_Sequencer node for details.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.MS_CYCLES_ANY", + "Alias": "a" + }, + { + "Name": "UOPS_RETIRED.MS:c1", + "Alias": "b" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "c" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "e" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "f" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( max( a , b / ( c / d ) ) / ( e if smt_on else ( f ) ) / 2 )", + "BaseFormula": " max( idq.ms_cycles_any , uops_retired.ms:c1 / ( uops_retired.slots / uops_issued.any ) ) / tma_info_core_core_clks / 2", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....MS(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Bandwidth(%)" + } + ], + "Formula": "a > 5 & b > 20", + "BaseFormula": "metric_TMA_....MS(%) > 5 & metric_TMA_..Fetch_Bandwidth(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq", + "LocateWith": "" + }, + { + "MetricName": "Bad_Speculation", + "LegacyName": "metric_TMA_Bad_Speculation(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) )", + "BaseFormula": " max( 1 - ( tma_frontend_bound + tma_backend_bound + tma_retiring ) , 0 )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 15", + "BaseFormula": "metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "TmaL1", + "LocateWith": "#NA" + }, + { + "MetricName": "Branch_Mispredicts", + "LegacyName": "metric_TMA_..Branch_Mispredicts(%)", + "ParentCategory": "Bad_Speculation", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b + c + d + e ) )", + "BaseFormula": " perf_metrics.branch_mispredicts / ( perf_metrics.frontend_bound + perf_metrics.bad_speculation + perf_metrics.retiring + perf_metrics.backend_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Branch_Mispredicts(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 10 & b > 15", + "BaseFormula": "metric_TMA_..Branch_Mispredicts(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "$issueBM" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2", + "LocateWith": " TOPDOWN.BR_MISPREDICT_SLOTS" + }, + { + "MetricName": "Cond_NT_Mispredicts", + "LegacyName": "metric_TMA_....Cond_NT_Mispredicts(%)", + "ParentCategory": "Branch_Mispredicts", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to retired misprediction by non-taken conditional branches.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "BR_MISP_RETIRED.COND_NTAKEN_COST", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.COND_NTAKEN_COST:retire_latency", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a * b ) / ( c ) )", + "BaseFormula": " ( br_misp_retired.cond_ntaken_cost * br_misp_retired.cond_ntaken_cost:retire_latency ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Cond_NT_Mispredicts(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Branch_Mispredicts(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....Cond_NT_Mispredicts(%) > 5 & metric_TMA_..Branch_Mispredicts(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BrMispredicts", + "LocateWith": "" + }, + { + "MetricName": "Cond_TK_Mispredicts", + "LegacyName": "metric_TMA_....Cond_TK_Mispredicts(%)", + "ParentCategory": "Branch_Mispredicts", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to misprediction by taken conditional branches.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "BR_MISP_RETIRED.COND_TAKEN_COST", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.COND_TAKEN_COST:retire_latency", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a * b ) / ( c ) )", + "BaseFormula": " ( br_misp_retired.cond_taken_cost * br_misp_retired.cond_taken_cost:retire_latency ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Cond_TK_Mispredicts(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Branch_Mispredicts(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....Cond_TK_Mispredicts(%) > 5 & metric_TMA_..Branch_Mispredicts(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BrMispredicts", + "LocateWith": "" + }, + { + "MetricName": "Ind_Call_Mispredicts", + "LegacyName": "metric_TMA_....Ind_Call_Mispredicts(%)", + "ParentCategory": "Branch_Mispredicts", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to retired misprediction by indirect CALL instructions.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "BR_MISP_RETIRED.INDIRECT_CALL_COST", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.INDIRECT_CALL_COST:retire_latency", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a * b ) / ( c ) )", + "BaseFormula": " ( br_misp_retired.indirect_call_cost * br_misp_retired.indirect_call_cost:retire_latency ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Ind_Call_Mispredicts(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Branch_Mispredicts(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....Ind_Call_Mispredicts(%) > 5 & metric_TMA_..Branch_Mispredicts(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BrMispredicts", + "LocateWith": "" + }, + { + "MetricName": "Ind_Jump_Mispredicts", + "LegacyName": "metric_TMA_....Ind_Jump_Mispredicts(%)", + "ParentCategory": "Branch_Mispredicts", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to retired misprediction by indirect JMP instructions.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "BR_MISP_RETIRED.INDIRECT_COST", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.INDIRECT_COST:retire_latency", + "Alias": "b" + }, + { + "Name": "BR_MISP_RETIRED.INDIRECT_CALL_COST", + "Alias": "c" + }, + { + "Name": "BR_MISP_RETIRED.INDIRECT_CALL_COST:retire_latency", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( max( ( ( a * b ) - ( c * d ) ) / ( e ) , 0 ) )", + "BaseFormula": " max( ( ( br_misp_retired.indirect_cost * br_misp_retired.indirect_cost:retire_latency ) - ( br_misp_retired.indirect_call_cost * br_misp_retired.indirect_call_cost:retire_latency ) ) / tma_info_thread_clks , 0 )", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Ind_Jump_Mispredicts(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Branch_Mispredicts(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....Ind_Jump_Mispredicts(%) > 5 & metric_TMA_..Branch_Mispredicts(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BrMispredicts", + "LocateWith": "" + }, + { + "MetricName": "Ret_Mispredicts", + "LegacyName": "metric_TMA_....Ret_Mispredicts(%)", + "ParentCategory": "Branch_Mispredicts", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to retired misprediction by (indirect) RET instructions.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "BR_MISP_RETIRED.RET_COST", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.RET_COST:retire_latency", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a * b ) / ( c ) )", + "BaseFormula": " ( br_misp_retired.ret_cost * br_misp_retired.ret_cost:retire_latency ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Ret_Mispredicts(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Branch_Mispredicts(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....Ret_Mispredicts(%) > 5 & metric_TMA_..Branch_Mispredicts(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BrMispredicts", + "LocateWith": "" + }, + { + "MetricName": "Other_Mispredicts", + "LegacyName": "metric_TMA_....Other_Mispredicts(%)", + "ParentCategory": "Branch_Mispredicts", + "Level": 3, + "BriefDescription": "This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "f" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "g" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( max( ( a / ( b + c + d + e ) ) * ( 1 - f / ( g - h ) ) , 0.0001 ) )", + "BaseFormula": " max( tma_branch_mispredicts * ( 1 - br_misp_retired.all_branches / ( int_misc.clears_count - machine_clears.count ) ) , 0.0001 )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Other_Mispredicts(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Branch_Mispredicts(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....Other_Mispredicts(%) > 5 & metric_TMA_..Branch_Mispredicts(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvIO;BrMispredicts", + "LocateWith": "" + }, + { + "MetricName": "Machine_Clears", + "LegacyName": "metric_TMA_..Machine_Clears(%)", + "ParentCategory": "Bad_Speculation", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) - ( g / ( a + b + c + d ) ) ) )", + "BaseFormula": " max( 0 , tma_bad_speculation - tma_branch_mispredicts )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Machine_Clears(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 10 & b > 15", + "BaseFormula": "metric_TMA_..Machine_Clears(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "$issueMC, $issueSyncxn" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2", + "LocateWith": "MACHINE_CLEARS.COUNT" + }, + { + "MetricName": "Other_Nukes", + "LegacyName": "metric_TMA_....Other_Nukes(%)", + "ParentCategory": "Machine_Clears", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "g" + }, + { + "Name": "MACHINE_CLEARS.MEMORY_ORDERING", + "Alias": "h" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "i" + } + ], + "Constants": [], + "Formula": "100 * ( max( ( max( 0 , ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) - ( g / ( a + b + c + d ) ) ) ) * ( 1 - h / i ) , 0.0001 ) )", + "BaseFormula": " max( tma_machine_clears * ( 1 - machine_clears.memory_ordering / machine_clears.count ) , 0.0001 )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Other_Nukes(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Machine_Clears(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....Other_Nukes(%) > 5 & metric_TMA_..Machine_Clears(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvIO;Machine_Clears", + "LocateWith": "" + }, + { + "MetricName": "Backend_Bound", + "LegacyName": "metric_TMA_Backend_Bound(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b + c + d + a ) )", + "BaseFormula": " perf_metrics.backend_bound / ( perf_metrics.frontend_bound + perf_metrics.bad_speculation + perf_metrics.retiring + perf_metrics.backend_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvOB;TmaL1", + "LocateWith": " TOPDOWN.BACKEND_BOUND_SLOTS" + }, + { + "MetricName": "Memory_Bound", + "LegacyName": "metric_TMA_..Memory_Bound(%)", + "ParentCategory": "Backend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b + c + d + e ) )", + "BaseFormula": " perf_metrics.memory_bound / ( perf_metrics.frontend_bound + perf_metrics.bad_speculation + perf_metrics.retiring + perf_metrics.backend_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20", + "BaseFormula": "metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Backend;TmaL2", + "LocateWith": "#NA" + }, + { + "MetricName": "L1_Bound", + "LegacyName": "metric_TMA_....L1_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 Data (L1D) cache. The L1D cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1D. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "a" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( max( ( a - b ) / ( c ) , 0 ) )", + "BaseFormula": " max( ( exe_activity.bound_on_loads - memory_activity.stalls_l1d_miss ) / tma_info_thread_clks , 0 )", + "Category": "TMA", + "CountDomain": "Stalls", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 20", + "BaseFormula": "metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueL1, $issueMC" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem", + "LocateWith": " MEM_LOAD_RETIRED.L1_HIT" + }, + { + "MetricName": "DTLB_Load", + "LegacyName": "metric_TMA_......DTLB_Load(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_INST_RETIRED.STLB_HIT_LOADS", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.STLB_HIT_LOADS:retire_latency", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( min( ( a * b ) , a * ( 7 ) ) if ( b > = 0 ) else ( a * ( 7 ) ) ) / ( c ) + ( d / ( c ) ) )", + "BaseFormula": " ( min( ( mem_inst_retired.stlb_hit_loads * mem_inst_retired.stlb_hit_loads:retire_latency ) , mem_inst_retired.stlb_hit_loads * ( 7 ) ) if ( mem_inst_retired.stlb_hit_loads:retire_latency >= 0 ) else ( mem_inst_retired.stlb_hit_loads * ( 7 ) ) ) / tma_info_thread_clks + tma_load_stlb_miss", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......DTLB_Load(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......DTLB_Load(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueTLB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMT;MemoryTLB", + "LocateWith": " MEM_INST_RETIRED.STLB_MISS_LOADS" + }, + { + "MetricName": "Load_STLB_Hit", + "LegacyName": "metric_TMA_........Load_STLB_Hit(%)", + "ParentCategory": "DTLB_Load", + "Level": 5, + "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_INST_RETIRED.STLB_HIT_LOADS", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.STLB_HIT_LOADS:retire_latency", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( ( min( ( a * b ) , a * ( 7 ) ) if ( b > = 0 ) else ( a * ( 7 ) ) ) / ( c ) + ( d / ( c ) ) ) - ( d / ( c ) ) ) )", + "BaseFormula": " max( 0 , tma_dtlb_load - tma_load_stlb_miss )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Load_STLB_Hit(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......DTLB_Load(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 10 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........Load_STLB_Hit(%) > 5 & metric_TMA_......DTLB_Load(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Load_STLB_Miss", + "LegacyName": "metric_TMA_........Load_STLB_Miss(%)", + "ParentCategory": "DTLB_Load", + "Level": 5, + "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": " dtlb_load_misses.walk_active / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Calculated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Load_STLB_Miss(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......DTLB_Load(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 10 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........Load_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Load(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Load_STLB_Miss_4K", + "LegacyName": "metric_TMA_..........Load_STLB_Miss_4K(%)", + "ParentCategory": "Load_STLB_Miss", + "Level": 6, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 4 KB pages for data load accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "Alias": "c" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "d" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b ) ) * c / ( c + d + e ) )", + "BaseFormula": " tma_load_stlb_miss * dtlb_load_misses.walk_completed_4k / ( dtlb_load_misses.walk_completed_4k + dtlb_load_misses.walk_completed_2m_4m + dtlb_load_misses.walk_completed_1g )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Load_STLB_Miss_4K(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_........Load_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_......DTLB_Load(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "f", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 10 & e > 20 & f > 20", + "BaseFormula": "metric_TMA_..........Load_STLB_Miss_4K(%) > 5 & metric_TMA_........Load_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Load(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Load_STLB_Miss_2M", + "LegacyName": "metric_TMA_..........Load_STLB_Miss_2M(%)", + "ParentCategory": "Load_STLB_Miss", + "Level": 6, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 2 or 4 MB pages for data load accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "c" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "Alias": "d" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b ) ) * c / ( d + c + e ) )", + "BaseFormula": " tma_load_stlb_miss * dtlb_load_misses.walk_completed_2m_4m / ( dtlb_load_misses.walk_completed_4k + dtlb_load_misses.walk_completed_2m_4m + dtlb_load_misses.walk_completed_1g )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Load_STLB_Miss_2M(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_........Load_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_......DTLB_Load(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "f", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 10 & e > 20 & f > 20", + "BaseFormula": "metric_TMA_..........Load_STLB_Miss_2M(%) > 5 & metric_TMA_........Load_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Load(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Load_STLB_Miss_1G", + "LegacyName": "metric_TMA_..........Load_STLB_Miss_1G(%)", + "ParentCategory": "Load_STLB_Miss", + "Level": 6, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 1 GB pages for data load accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "Alias": "c" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "Alias": "d" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b ) ) * c / ( d + e + c ) )", + "BaseFormula": " tma_load_stlb_miss * dtlb_load_misses.walk_completed_1g / ( dtlb_load_misses.walk_completed_4k + dtlb_load_misses.walk_completed_2m_4m + dtlb_load_misses.walk_completed_1g )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Load_STLB_Miss_1G(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_........Load_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_......DTLB_Load(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "f", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 10 & e > 20 & f > 20", + "BaseFormula": "metric_TMA_..........Load_STLB_Miss_1G(%) > 5 & metric_TMA_........Load_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Load(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Store_Fwd_Blk", + "LegacyName": "metric_TMA_......Store_Fwd_Blk(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "LD_BLOCKS.STORE_FORWARD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 13 * a / ( b ) )", + "BaseFormula": " 13 * ld_blocks.store_forward / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Store_Fwd_Blk(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Store_Fwd_Blk(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "L1_Latency_Dependency", + "LegacyName": "metric_TMA_......L1_Latency_Dependency(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric([SKL+] roughly; [LNL]) estimates fraction of cycles with demand load accesses that hit the L1D cache. The short latency of the L1D cache may be exposed in pointer-chasing memory access patterns as an example.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "c" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "e" + }, + { + "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + } + ], + "Constants": [ + { + "Name": "20", + "Alias": "dependentloadsweight" + } + ], + "Formula": "100 * ( min( 2 * ( a - b - c ) * dependentloadsweight / 100 , max( e - f , 0 ) ) / ( g ) )", + "BaseFormula": " min( 2 * ( mem_inst_retired.all_loads - mem_load_retired.fb_hit - mem_load_retired.l1_miss ) * 20 / 100 , max( cycle_activity.cycles_mem_any - memory_activity.cycles_l1d_miss , 0 ) ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......L1_Latency_Dependency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......L1_Latency_Dependency(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvML;MemoryLat", + "LocateWith": " MEM_LOAD_RETIRED.L1_HIT" + }, + { + "MetricName": "Lock_Latency", + "LegacyName": "metric_TMA_......Lock_Latency(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS:retire_latency", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a * b ) / ( c ) )", + "BaseFormula": " ( mem_inst_retired.lock_loads * mem_inst_retired.lock_loads:retire_latency ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Lock_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Lock_Latency(%) > 20 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueRFO" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "LockCont;Offcore", + "LocateWith": " MEM_INST_RETIRED.LOCK_LOADS" + }, + { + "MetricName": "Split_Loads", + "LegacyName": "metric_TMA_......Split_Loads(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_INST_RETIRED.SPLIT_LOADS", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.SPLIT_LOADS:retire_latency", + "Alias": "b" + }, + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "c" + }, + { + "Name": "MEM_LOAD_COMPLETED.L1_MISS_ANY", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( ( min( ( a * b ) , a * ( c / d ) ) if ( b > = 0 ) else ( a * ( c / d ) ) ) / ( e ) )", + "BaseFormula": " ( min( ( mem_inst_retired.split_loads * mem_inst_retired.split_loads:retire_latency ) , mem_inst_retired.split_loads * tma_info_memory_load_miss_real_latency ) if ( mem_inst_retired.split_loads:retire_latency >= 0 ) else ( mem_inst_retired.split_loads * tma_info_memory_load_miss_real_latency ) ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Calculated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Split_Loads(%)" + } + ], + "Formula": "a > 30", + "BaseFormula": "metric_TMA_......Split_Loads(%) > 30", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": " MEM_INST_RETIRED.SPLIT_LOADS" + }, + { + "MetricName": "FB_Full", + "LegacyName": "metric_TMA_......FB_Full(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "L1D_PEND_MISS.FB_FULL", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": " l1d_pend_miss.fb_full / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Calculated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......FB_Full(%)" + } + ], + "Formula": "a > 30", + "BaseFormula": "metric_TMA_......FB_Full(%) > 30", + "ThresholdIssues": "$issueBW, $issueSL, $issueSmSt" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMB;MemoryBW", + "LocateWith": "" + }, + { + "MetricName": "L2_Bound", + "LegacyName": "metric_TMA_....L2_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Alias": "a" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a - b ) / ( c ) )", + "BaseFormula": " ( memory_activity.stalls_l1d_miss - memory_activity.stalls_l2_miss ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Stalls", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....L2_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 20 & c > 20", + "BaseFormula": "metric_TMA_....L2_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvML;CacheHits;MemoryBound;TmaL3mem", + "LocateWith": " MEM_LOAD_RETIRED.L2_HIT" + }, + { + "MetricName": "L2_Hit_Latency", + "LegacyName": "metric_TMA_......L2_Hit_Latency(%)", + "ParentCategory": "L2_Bound", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L2 cache under unloaded scenarios (possibly L2 latency limited). Avoiding L1 cache misses (i.e. L1 misses/L2 hits) will improve the latency.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_HIT", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_RETIRED.L2_HIT:retire_latency", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "d" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "g" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "h" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + }, + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "e" + } + ], + "Formula": "100 * ( ( min( ( a * b ) , a * ( 4.4 * ( ( ( c ) / d ) * e / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b > = 0 ) else ( a * ( 4.4 * ( ( ( c ) / d ) * e / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 + ( g / h ) / 2 ) / ( c ) )", + "BaseFormula": " ( min( ( mem_load_retired.l2_hit * mem_load_retired.l2_hit:retire_latency ) , mem_load_retired.l2_hit * ( 4.4 * tma_info_system_core_frequency ) ) if ( mem_load_retired.l2_hit:retire_latency >= 0 ) else ( mem_load_retired.l2_hit * ( 4.4 * tma_info_system_core_frequency ) ) ) * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) / 2 ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......L2_Hit_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L2_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......L2_Hit_Latency(%) > 5 & metric_TMA_....L2_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryLat", + "LocateWith": " MEM_LOAD_RETIRED.L2_HIT" + }, + { + "MetricName": "L3_Bound", + "LegacyName": "metric_TMA_....L3_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Alias": "a" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a - b ) / ( c ) )", + "BaseFormula": " ( memory_activity.stalls_l2_miss - memory_activity.stalls_l3_miss ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Stalls", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....L3_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 20 & c > 20", + "BaseFormula": "metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem", + "LocateWith": " MEM_LOAD_RETIRED.L3_HIT" + }, + { + "MetricName": "Contested_Accesses", + "LegacyName": "metric_TMA_......Contested_Accesses(%)", + "ParentCategory": "L3_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS:retire_latency", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "d" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Alias": "g" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD:retire_latency", + "Alias": "h" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "i" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "j" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "k" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "l" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + }, + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "e" + } + ], + "Formula": "100 * ( ( ( min( ( a * b ) , a * ( 79 * ( ( ( c ) / d ) * e / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( c ) / d ) * e / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b > = 0 ) else ( a * ( 79 * ( ( ( c ) / d ) * e / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( c ) / d ) * e / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( g * h ) , g * ( 81 * ( ( ( c ) / d ) * e / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( c ) / d ) * e / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( h > = 0 ) else ( g * ( 81 * ( ( ( c ) / d ) * e / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( c ) / d ) * e / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( i / ( i + j ) ) ) * ( 1 + ( k / l ) / 2 ) / ( c ) )", + "BaseFormula": " ( ( min( ( mem_load_l3_hit_retired.xsnp_miss * mem_load_l3_hit_retired.xsnp_miss:retire_latency ) , mem_load_l3_hit_retired.xsnp_miss * ( 79 * tma_info_system_core_frequency ) - ( 4.4 * tma_info_system_core_frequency ) ) if ( mem_load_l3_hit_retired.xsnp_miss:retire_latency >= 0 ) else ( mem_load_l3_hit_retired.xsnp_miss * ( 79 * tma_info_system_core_frequency ) - ( 4.4 * tma_info_system_core_frequency ) ) ) + ( min( ( mem_load_l3_hit_retired.xsnp_fwd * mem_load_l3_hit_retired.xsnp_fwd:retire_latency ) , mem_load_l3_hit_retired.xsnp_fwd * ( 81 * tma_info_system_core_frequency ) - ( 4.4 * tma_info_system_core_frequency ) ) if ( mem_load_l3_hit_retired.xsnp_fwd:retire_latency >= 0 ) else ( mem_load_l3_hit_retired.xsnp_fwd * ( 81 * tma_info_system_core_frequency ) - ( 4.4 * tma_info_system_core_frequency ) ) ) * ( ocr.demand_data_rd.l3_hit.snoop_hitm / ( ocr.demand_data_rd.l3_hit.snoop_hitm + ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd ) ) ) * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) / 2 ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Contested_Accesses(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L3_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Contested_Accesses(%) > 5 & metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSyncxn" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMS;DataSharing;LockCont;Offcore;Snoop", + "LocateWith": " MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS" + }, + { + "MetricName": "Data_Sharing", + "LegacyName": "metric_TMA_......Data_Sharing(%)", + "ParentCategory": "L3_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD:retire_latency", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "d" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Alias": "g" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD:retire_latency", + "Alias": "h" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "i" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "j" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "k" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "l" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + }, + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "e" + } + ], + "Formula": "100 * ( ( ( min( ( a * b ) , a * ( 79 * ( ( ( c ) / d ) * e / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( c ) / d ) * e / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b > = 0 ) else ( a * ( 79 * ( ( ( c ) / d ) * e / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( c ) / d ) * e / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) + ( min( ( g * h ) , g * ( 79 * ( ( ( c ) / d ) * e / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( c ) / d ) * e / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( h > = 0 ) else ( g * ( 79 * ( ( ( c ) / d ) * e / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( c ) / d ) * e / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 - ( i / ( i + j ) ) ) ) * ( 1 + ( k / l ) / 2 ) / ( c ) )", + "BaseFormula": " ( ( min( ( mem_load_l3_hit_retired.xsnp_no_fwd * mem_load_l3_hit_retired.xsnp_no_fwd:retire_latency ) , mem_load_l3_hit_retired.xsnp_no_fwd * ( 79 * tma_info_system_core_frequency ) - ( 4.4 * tma_info_system_core_frequency ) ) if ( mem_load_l3_hit_retired.xsnp_no_fwd:retire_latency >= 0 ) else ( mem_load_l3_hit_retired.xsnp_no_fwd * ( 79 * tma_info_system_core_frequency ) - ( 4.4 * tma_info_system_core_frequency ) ) ) + ( min( ( mem_load_l3_hit_retired.xsnp_fwd * mem_load_l3_hit_retired.xsnp_fwd:retire_latency ) , mem_load_l3_hit_retired.xsnp_fwd * ( 79 * tma_info_system_core_frequency ) - ( 4.4 * tma_info_system_core_frequency ) ) if ( mem_load_l3_hit_retired.xsnp_fwd:retire_latency >= 0 ) else ( mem_load_l3_hit_retired.xsnp_fwd * ( 79 * tma_info_system_core_frequency ) - ( 4.4 * tma_info_system_core_frequency ) ) ) * ( 1 - ( ocr.demand_data_rd.l3_hit.snoop_hitm / ( ocr.demand_data_rd.l3_hit.snoop_hitm + ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd ) ) ) ) * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) / 2 ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Data_Sharing(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L3_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Data_Sharing(%) > 5 & metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSyncxn" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMS;Offcore;Snoop", + "LocateWith": " MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD" + }, + { + "MetricName": "L3_Hit_Latency", + "LegacyName": "metric_TMA_......L3_Hit_Latency(%)", + "ParentCategory": "L3_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT:retire_latency", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "d" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "g" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "h" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + }, + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "e" + } + ], + "Formula": "100 * ( ( min( ( a * b ) , a * ( 37 * ( ( ( c ) / d ) * e / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( c ) / d ) * e / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) if ( b > = 0 ) else ( a * ( 37 * ( ( ( c ) / d ) * e / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( c ) / d ) * e / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) ) * ( 1 + ( g / h ) / 2 ) / ( c ) )", + "BaseFormula": " ( min( ( mem_load_retired.l3_hit * mem_load_retired.l3_hit:retire_latency ) , mem_load_retired.l3_hit * ( 37 * tma_info_system_core_frequency ) - ( 4.4 * tma_info_system_core_frequency ) ) if ( mem_load_retired.l3_hit:retire_latency >= 0 ) else ( mem_load_retired.l3_hit * ( 37 * tma_info_system_core_frequency ) - ( 4.4 * tma_info_system_core_frequency ) ) ) * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) / 2 ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......L3_Hit_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L3_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 5 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......L3_Hit_Latency(%) > 10 & metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueLat, ~overlap" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvML;MemoryLat", + "LocateWith": " MEM_LOAD_RETIRED.L3_HIT" + }, + { + "MetricName": "SQ_Full", + "LegacyName": "metric_TMA_......SQ_Full(%)", + "ParentCategory": "L3_Bound", + "Level": 4, + "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "XQ.FULL_CYCLES", + "Alias": "a" + }, + { + "Name": "L1D_PEND_MISS.L2_STALLS", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b ) / ( c ) )", + "BaseFormula": " ( xq.full_cycles + l1d_pend_miss.l2_stalls ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......SQ_Full(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L3_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 30 & b > 5 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......SQ_Full(%) > 30 & metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueBW" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMB;MemoryBW;Offcore", + "LocateWith": "" + }, + { + "MetricName": "DRAM_Bound", + "LegacyName": "metric_TMA_....DRAM_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b ) ) )", + "BaseFormula": " ( memory_activity.stalls_l3_miss / tma_info_thread_clks )", + "Category": "TMA", + "CountDomain": "Stalls", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 20", + "BaseFormula": "metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBound;TmaL3mem", + "LocateWith": " MEM_LOAD_RETIRED.L3_MISS" + }, + { + "MetricName": "MEM_Bandwidth", + "LegacyName": "metric_TMA_......MEM_Bandwidth(%)", + "ParentCategory": "DRAM_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD:c4", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( ( min( a , b ) ) / ( a ) )", + "BaseFormula": " ( min( cpu_clk_unhalted.thread , offcore_requests_outstanding.data_rd:c4 ) ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......MEM_Bandwidth(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......MEM_Bandwidth(%) > 20 & metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueBW" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMB;MemoryBW;Offcore", + "LocateWith": "" + }, + { + "MetricName": "MBA_Stalls", + "LegacyName": "metric_TMA_........MBA_Stalls(%)", + "ParentCategory": "MEM_Bandwidth", + "Level": 5, + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to memory bandwidth Allocation feature (RDT's memory bandwidth throttling).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_MISC.MBA_STALLS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": " int_misc.mba_stalls / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........MBA_Stalls(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......MEM_Bandwidth(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 10 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........MBA_Stalls(%) > 10 & metric_TMA_......MEM_Bandwidth(%) > 20 & metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBW;Offcore;Server", + "LocateWith": "" + }, + { + "MetricName": "MEM_Latency", + "LegacyName": "metric_TMA_......MEM_Latency(%)", + "ParentCategory": "DRAM_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "b" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD:c4", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( min( a , b ) ) / ( a ) - ( ( min( a , c ) ) / ( a ) ) )", + "BaseFormula": " ( min( cpu_clk_unhalted.thread , offcore_requests_outstanding.cycles_with_data_rd ) ) / tma_info_thread_clks - tma_mem_bandwidth", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......MEM_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......MEM_Latency(%) > 10 & metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueLat" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvML;MemoryLat;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Local_MEM", + "LegacyName": "metric_TMA_........Local_MEM(%)", + "ParentCategory": "MEM_Latency", + "Level": 5, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM:retire_latency", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "c" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( ( a * b ) * ( 1 + ( c / d ) / 2 ) / ( e ) )", + "BaseFormula": " ( mem_load_l3_miss_retired.local_dram * mem_load_l3_miss_retired.local_dram:retire_latency ) * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) / 2 ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Local_MEM(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......MEM_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 10 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........Local_MEM(%) > 10 & metric_TMA_......MEM_Latency(%) > 10 & metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Server", + "LocateWith": " MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM" + }, + { + "MetricName": "Remote_MEM", + "LegacyName": "metric_TMA_........Remote_MEM(%)", + "ParentCategory": "MEM_Latency", + "Level": 5, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM:retire_latency", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "c" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( ( a * b ) * ( 1 + ( c / d ) / 2 ) / ( e ) )", + "BaseFormula": " ( mem_load_l3_miss_retired.remote_dram * mem_load_l3_miss_retired.remote_dram:retire_latency ) * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) / 2 ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Remote_MEM(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......MEM_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 10 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........Remote_MEM(%) > 10 & metric_TMA_......MEM_Latency(%) > 10 & metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Server;Snoop", + "LocateWith": " MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM" + }, + { + "MetricName": "Remote_Cache", + "LegacyName": "metric_TMA_........Remote_Cache(%)", + "ParentCategory": "MEM_Latency", + "Level": 5, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM:retire_latency", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "Alias": "c" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD:retire_latency", + "Alias": "d" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a * b ) + ( c * d ) ) * ( 1 + ( e / f ) / 2 ) / ( g ) )", + "BaseFormula": " ( ( mem_load_l3_miss_retired.remote_hitm * mem_load_l3_miss_retired.remote_hitm:retire_latency ) + ( mem_load_l3_miss_retired.remote_fwd * mem_load_l3_miss_retired.remote_fwd:retire_latency ) ) * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) / 2 ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Remote_Cache(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......MEM_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 10 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........Remote_Cache(%) > 5 & metric_TMA_......MEM_Latency(%) > 10 & metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSyncxn" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Offcore;Server;Snoop", + "LocateWith": " MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD" + }, + { + "MetricName": "Store_Bound", + "LegacyName": "metric_TMA_....Store_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": " exe_activity.bound_on_stores / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Stalls", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20 & c > 20", + "BaseFormula": "metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBound;TmaL3mem", + "LocateWith": " MEM_INST_RETIRED.ALL_STORES" + }, + { + "MetricName": "Store_Latency", + "LegacyName": "metric_TMA_......Store_Latency(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_STORE_RETIRED.L2_HIT", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "b" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a * ( 10 ) * ( 1 - ( b / c ) ) ) + ( 1 - ( b / c ) ) * ( min( d , e ) ) ) / ( d ) )", + "BaseFormula": " ( ( mem_store_retired.l2_hit * ( 10 ) * ( 1 - ( mem_inst_retired.lock_loads / mem_inst_retired.all_stores ) ) ) + ( 1 - ( mem_inst_retired.lock_loads / mem_inst_retired.all_stores ) ) * ( min( cpu_clk_unhalted.thread , offcore_requests_outstanding.cycles_with_demand_rfo ) ) ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Store_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Store_Latency(%) > 10 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueRFO, $issueSL, ~overlap" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvML;LockCont;MemoryLat;Offcore", + "LocateWith": "" + }, + { + "MetricName": "False_Sharing", + "LegacyName": "metric_TMA_......False_Sharing(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "OCR.DEMAND_RFO.L3_MISS:ocr_msr_val=0x103b800002", + "Alias": "e" + }, + { + "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "Alias": "f" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( ( ( 170 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * e + ( 81 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * f ) / ( a ) )", + "BaseFormula": " ( ( 170 * tma_info_system_core_frequency ) * ocr.demand_rfo.l3_miss:ocr_msr_val=0x103b800002 + ( 81 * tma_info_system_core_frequency ) * ocr.demand_rfo.l3_hit.snoop_hitm ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......False_Sharing(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 20 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......False_Sharing(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSyncxn" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMS;DataSharing;LockCont;Offcore;Snoop", + "LocateWith": " OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM" + }, + { + "MetricName": "Split_Stores", + "LegacyName": "metric_TMA_......Split_Stores(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_INST_RETIRED.SPLIT_STORES", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.SPLIT_STORES:retire_latency", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( min( ( a * b ) , a * 1 ) if ( b > = 0 ) else ( a * 1 ) ) / ( c ) )", + "BaseFormula": " ( min( ( mem_inst_retired.split_stores * mem_inst_retired.split_stores:retire_latency ) , mem_inst_retired.split_stores * 1 ) if ( mem_inst_retired.split_stores:retire_latency >= 0 ) else ( mem_inst_retired.split_stores * 1 ) ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Core_Utilization", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Split_Stores(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Split_Stores(%) > 20 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSpSt" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": " MEM_INST_RETIRED.SPLIT_STORES" + }, + { + "MetricName": "Streaming_Stores", + "LegacyName": "metric_TMA_......Streaming_Stores(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "OCR.STREAMING_WR.ANY_RESPONSE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 9 * a / ( b ) )", + "BaseFormula": " 9 * ocr.streaming_wr.any_response / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Streaming_Stores(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Streaming_Stores(%) > 20 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSmSt" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBW;Offcore", + "LocateWith": " OCR.STREAMING_WR.ANY_RESPONSE" + }, + { + "MetricName": "DTLB_Store", + "LegacyName": "metric_TMA_......DTLB_Store(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_INST_RETIRED.STLB_HIT_STORES", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.STLB_HIT_STORES:retire_latency", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "e" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( min( ( a * b ) , a * ( 7 ) ) if ( b > = 0 ) else ( a * ( 7 ) ) ) / ( c ) + ( d / ( e if smt_on else ( c ) ) ) )", + "BaseFormula": " ( min( ( mem_inst_retired.stlb_hit_stores * mem_inst_retired.stlb_hit_stores:retire_latency ) , mem_inst_retired.stlb_hit_stores * ( 7 ) ) if ( mem_inst_retired.stlb_hit_stores:retire_latency >= 0 ) else ( mem_inst_retired.stlb_hit_stores * ( 7 ) ) ) / tma_info_thread_clks + tma_store_stlb_miss", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......DTLB_Store(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 20 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......DTLB_Store(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueTLB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMT;MemoryTLB", + "LocateWith": " MEM_INST_RETIRED.STLB_MISS_STORES" + }, + { + "MetricName": "Store_STLB_Hit", + "LegacyName": "metric_TMA_........Store_STLB_Hit(%)", + "ParentCategory": "DTLB_Store", + "Level": 5, + "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_INST_RETIRED.STLB_HIT_STORES", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.STLB_HIT_STORES:retire_latency", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "e" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( max( 0 , ( ( min( ( a * b ) , a * ( 7 ) ) if ( b > = 0 ) else ( a * ( 7 ) ) ) / ( c ) + ( d / ( e if smt_on else ( c ) ) ) ) - ( d / ( e if smt_on else ( c ) ) ) ) )", + "BaseFormula": " max( 0 , tma_dtlb_store - tma_store_stlb_miss )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Store_STLB_Hit(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......DTLB_Store(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 20 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........Store_STLB_Hit(%) > 5 & metric_TMA_......DTLB_Store(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Store_STLB_Miss", + "LegacyName": "metric_TMA_........Store_STLB_Miss(%)", + "ParentCategory": "DTLB_Store", + "Level": 5, + "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( a / ( b if smt_on else ( c ) ) )", + "BaseFormula": " dtlb_store_misses.walk_active / tma_info_core_core_clks", + "Category": "TMA", + "CountDomain": "Clocks_Calculated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Store_STLB_Miss(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......DTLB_Store(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 20 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........Store_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Store(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Store_STLB_Miss_4K", + "LegacyName": "metric_TMA_..........Store_STLB_Miss_4K(%)", + "ParentCategory": "Store_STLB_Miss", + "Level": 6, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 4 KB pages for data store accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "Alias": "d" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "e" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "Alias": "f" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a / ( b if smt_on else ( c ) ) ) * d / ( d + e + f ) )", + "BaseFormula": " tma_store_stlb_miss * dtlb_store_misses.walk_completed_4k / ( dtlb_store_misses.walk_completed_4k + dtlb_store_misses.walk_completed_2m_4m + dtlb_store_misses.walk_completed_1g )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Store_STLB_Miss_4K(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_........Store_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_......DTLB_Store(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "f", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 5 & d > 20 & e > 20 & f > 20", + "BaseFormula": "metric_TMA_..........Store_STLB_Miss_4K(%) > 5 & metric_TMA_........Store_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Store(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Store_STLB_Miss_2M", + "LegacyName": "metric_TMA_..........Store_STLB_Miss_2M(%)", + "ParentCategory": "Store_STLB_Miss", + "Level": 6, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 2 or 4 MB pages for data store accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "d" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "Alias": "e" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "Alias": "f" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a / ( b if smt_on else ( c ) ) ) * d / ( e + d + f ) )", + "BaseFormula": " tma_store_stlb_miss * dtlb_store_misses.walk_completed_2m_4m / ( dtlb_store_misses.walk_completed_4k + dtlb_store_misses.walk_completed_2m_4m + dtlb_store_misses.walk_completed_1g )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Store_STLB_Miss_2M(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_........Store_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_......DTLB_Store(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "f", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 5 & d > 20 & e > 20 & f > 20", + "BaseFormula": "metric_TMA_..........Store_STLB_Miss_2M(%) > 5 & metric_TMA_........Store_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Store(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Store_STLB_Miss_1G", + "LegacyName": "metric_TMA_..........Store_STLB_Miss_1G(%)", + "ParentCategory": "Store_STLB_Miss", + "Level": 6, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 1 GB pages for data store accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "Alias": "d" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "Alias": "e" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "f" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a / ( b if smt_on else ( c ) ) ) * d / ( e + f + d ) )", + "BaseFormula": " tma_store_stlb_miss * dtlb_store_misses.walk_completed_1g / ( dtlb_store_misses.walk_completed_4k + dtlb_store_misses.walk_completed_2m_4m + dtlb_store_misses.walk_completed_1g )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Store_STLB_Miss_1G(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_........Store_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_......DTLB_Store(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "f", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 5 & d > 20 & e > 20 & f > 20", + "BaseFormula": "metric_TMA_..........Store_STLB_Miss_1G(%) > 5 & metric_TMA_........Store_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Store(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Core_Bound", + "LegacyName": "metric_TMA_..Core_Bound(%)", + "ParentCategory": "Backend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) )", + "BaseFormula": " max( 0 , tma_backend_bound - tma_memory_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 20", + "BaseFormula": "metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Backend;TmaL2;Compute", + "LocateWith": "" + }, + { + "MetricName": "Divider", + "LegacyName": "metric_TMA_....Divider(%)", + "ParentCategory": "Core_Bound", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": " arith.div_active / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Divider(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 10 & c > 20", + "BaseFormula": "metric_TMA_....Divider(%) > 20 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvCB", + "LocateWith": " ARITH.DIV_ACTIVE" + }, + { + "MetricName": "FP_Divider", + "LegacyName": "metric_TMA_......FP_Divider(%)", + "ParentCategory": "Divider", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles where the Floating-Point Divider unit was active.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ARITH.FPDIV_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": " arith.fpdiv_active / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......FP_Divider(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Divider(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......FP_Divider(%) > 20 & metric_TMA_....Divider(%) > 20 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "INT_Divider", + "LegacyName": "metric_TMA_......INT_Divider(%)", + "ParentCategory": "Divider", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles where the Integer Divider unit was active.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "ARITH.FPDIV_ACTIVE", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b ) ) - ( c / ( b ) ) )", + "BaseFormula": " tma_divider - tma_fp_divider", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......INT_Divider(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Divider(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......INT_Divider(%) > 20 & metric_TMA_....Divider(%) > 20 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "Serializing_Operation", + "LegacyName": "metric_TMA_....Serializing_Operation(%)", + "ParentCategory": "Core_Bound", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.C02", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) + ( c / ( b ) ) )", + "BaseFormula": " resource_stalls.scoreboard / tma_info_thread_clks + tma_c02_wait", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Serializing_Operation(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20", + "BaseFormula": "metric_TMA_....Serializing_Operation(%) > 10 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSO" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvIO;PortsUtil", + "LocateWith": " RESOURCE_STALLS.SCOREBOARD" + }, + { + "MetricName": "Slow_Pause", + "LegacyName": "metric_TMA_......Slow_Pause(%)", + "ParentCategory": "Serializing_Operation", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.PAUSE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": " cpu_clk_unhalted.pause / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Slow_Pause(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Serializing_Operation(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......Slow_Pause(%) > 5 & metric_TMA_....Serializing_Operation(%) > 10 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": " CPU_CLK_UNHALTED.PAUSE_INST" + }, + { + "MetricName": "C01_Wait", + "LegacyName": "metric_TMA_......C01_Wait(%)", + "ParentCategory": "Serializing_Operation", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due staying in C0.1 power-performance optimized state (Faster wakeup time; Smaller power savings).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.C01", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": " cpu_clk_unhalted.c01 / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......C01_Wait(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Serializing_Operation(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......C01_Wait(%) > 5 & metric_TMA_....Serializing_Operation(%) > 10 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "C0Wait", + "LocateWith": "" + }, + { + "MetricName": "C02_Wait", + "LegacyName": "metric_TMA_......C02_Wait(%)", + "ParentCategory": "Serializing_Operation", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due staying in C0.2 power-performance optimized state (Slower wakeup time; Larger power savings).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.C02", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": " cpu_clk_unhalted.c02 / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......C02_Wait(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Serializing_Operation(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......C02_Wait(%) > 5 & metric_TMA_....Serializing_Operation(%) > 10 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "C0Wait", + "LocateWith": "" + }, + { + "MetricName": "Memory_Fence", + "LegacyName": "metric_TMA_......Memory_Fence(%)", + "ParentCategory": "Serializing_Operation", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to LFENCE Instructions.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MISC2_RETIRED.LFENCE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 13 * a / ( b ) )", + "BaseFormula": " 13 * misc2_retired.lfence / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Memory_Fence(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Serializing_Operation(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......Memory_Fence(%) > 5 & metric_TMA_....Serializing_Operation(%) > 10 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "AMX_Busy", + "LegacyName": "metric_TMA_....AMX_Busy(%)", + "ParentCategory": "Core_Bound", + "Level": 3, + "BriefDescription": "This metric estimates fraction of cycles where the Advanced Matrix eXtensions (AMX) execution engine was busy with tile (arithmetic) operations", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE.AMX_BUSY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( a / ( b if smt_on else ( c ) ) )", + "BaseFormula": " exe.amx_busy / tma_info_core_core_clks", + "Category": "TMA", + "CountDomain": "Core_Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....AMX_Busy(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 50 & b > 10 & c > 20", + "BaseFormula": "metric_TMA_....AMX_Busy(%) > 50 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvCB;Compute;HPC;Server", + "LocateWith": "" + }, + { + "MetricName": "Ports_Utilization", + "LegacyName": "metric_TMA_....Ports_Utilization(%)", + "ParentCategory": "Core_Bound", + "Level": 3, + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "Alias": "a" + }, + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "g" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "h" + }, + { + "Name": "EXE_ACTIVITY.2_3_PORTS_UTIL", + "Alias": "i" + }, + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "j" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "k" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "l" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( max( a - b , 0 ) / ( c ) ) * ( c ) + ( d + ( e / ( f + g + e + h ) ) * i ) ) / ( c ) if ( j < ( k - l ) ) else ( d + ( e / ( f + g + e + h ) ) * i ) / ( c ) )", + "BaseFormula": " ( tma_ports_utilized_0 * tma_info_thread_clks + ( exe_activity.1_ports_util + tma_retiring * exe_activity.2_3_ports_util ) ) / tma_info_thread_clks if ( arith.div_active < ( cycle_activity.stalls_total - exe_activity.bound_on_loads ) ) else ( exe_activity.1_ports_util + tma_retiring * exe_activity.2_3_ports_util ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Ports_Utilization(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 15 & b > 10 & c > 20", + "BaseFormula": "metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil", + "LocateWith": "" + }, + { + "MetricName": "Ports_Utilized_0", + "LegacyName": "metric_TMA_......Ports_Utilized_0(%)", + "ParentCategory": "Ports_Utilization", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "Alias": "a" + }, + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( max( a - b , 0 ) / ( c ) )", + "BaseFormula": " max( exe_activity.exe_bound_0_ports - resource_stalls.scoreboard , 0 ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Ports_Utilized_0(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Ports_Utilization(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 15 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......Ports_Utilized_0(%) > 20 & metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil", + "LocateWith": "" + }, + { + "MetricName": "Mixing_Vectors", + "LegacyName": "metric_TMA_........Mixing_Vectors(%)", + "ParentCategory": "Ports_Utilized_0", + "Level": 5, + "BriefDescription": "This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued , the Count Domain; [ADL+] cycles). Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ASSISTS.SSE_AVX_MIX", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 160 * a / ( b ) )", + "BaseFormula": " 160 * assists.sse_avx_mix / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Mixing_Vectors(%)" + } + ], + "Formula": "a > 5", + "BaseFormula": "metric_TMA_........Mixing_Vectors(%) > 5", + "ThresholdIssues": "$issueMV" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "Ports_Utilized_1", + "LegacyName": "metric_TMA_......Ports_Utilized_1(%)", + "ParentCategory": "Ports_Utilization", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": " exe_activity.1_ports_util / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Ports_Utilized_1(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Ports_Utilization(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 15 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......Ports_Utilized_1(%) > 20 & metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueL1" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil", + "LocateWith": " EXE_ACTIVITY.1_PORTS_UTIL" + }, + { + "MetricName": "Ports_Utilized_2", + "LegacyName": "metric_TMA_......Ports_Utilized_2(%)", + "ParentCategory": "Ports_Utilization", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": " exe_activity.2_ports_util / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Ports_Utilized_2(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Ports_Utilization(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 15 & b > 15 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......Ports_Utilized_2(%) > 15 & metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil", + "LocateWith": " EXE_ACTIVITY.2_PORTS_UTIL" + }, + { + "MetricName": "Ports_Utilized_3m", + "LegacyName": "metric_TMA_......Ports_Utilized_3m(%)", + "ParentCategory": "Ports_Utilization", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_EXECUTED.CYCLES_GE_3", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": " uops_executed.cycles_ge_3 / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Ports_Utilized_3m(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Ports_Utilization(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 40 & b > 15 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......Ports_Utilized_3m(%) > 40 & metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvCB;PortsUtil", + "LocateWith": " UOPS_EXECUTED.CYCLES_GE_3" + }, + { + "MetricName": "ALU_Op_Utilization", + "LegacyName": "metric_TMA_........ALU_Op_Utilization(%)", + "ParentCategory": "Ports_Utilized_3m", + "Level": 5, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_0", + "Alias": "a" + }, + { + "Name": "UOPS_DISPATCHED.PORT_1", + "Alias": "b" + }, + { + "Name": "UOPS_DISPATCHED.PORT_5_11", + "Alias": "c" + }, + { + "Name": "UOPS_DISPATCHED.PORT_6", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "e" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "f" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a + b + c + d ) / ( 5 * ( e if smt_on else ( f ) ) ) )", + "BaseFormula": " ( uops_dispatched.port_0 + uops_dispatched.port_1 + uops_dispatched.port_5_11 + uops_dispatched.port_6 ) / ( 5 * tma_info_core_core_clks )", + "Category": "TMA", + "CountDomain": "Core_Execution", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........ALU_Op_Utilization(%)" + } + ], + "Formula": "a > 40", + "BaseFormula": "metric_TMA_........ALU_Op_Utilization(%) > 40", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "Port_0", + "LegacyName": "metric_TMA_..........Port_0(%)", + "ParentCategory": "ALU_Op_Utilization", + "Level": 6, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_0", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( a / ( b if smt_on else ( c ) ) )", + "BaseFormula": " uops_dispatched.port_0 / tma_info_core_core_clks", + "Category": "TMA", + "CountDomain": "Core_Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Port_0(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..........Port_0(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute", + "LocateWith": " UOPS_DISPATCHED.PORT_0 " + }, + { + "MetricName": "Port_1", + "LegacyName": "metric_TMA_..........Port_1(%)", + "ParentCategory": "ALU_Op_Utilization", + "Level": 6, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_1", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( a / ( b if smt_on else ( c ) ) )", + "BaseFormula": " uops_dispatched.port_1 / tma_info_core_core_clks", + "Category": "TMA", + "CountDomain": "Core_Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Port_1(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..........Port_1(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": " UOPS_DISPATCHED.PORT_1 " + }, + { + "MetricName": "Port_6", + "LegacyName": "metric_TMA_..........Port_6(%)", + "ParentCategory": "ALU_Op_Utilization", + "Level": 6, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_6", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( a / ( b if smt_on else ( c ) ) )", + "BaseFormula": " uops_dispatched.port_6 / tma_info_core_core_clks", + "Category": "TMA", + "CountDomain": "Core_Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Port_6(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..........Port_6(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": " UOPS_DISPATCHED.PORT_1 " + }, + { + "MetricName": "Load_Op_Utilization", + "LegacyName": "metric_TMA_........Load_Op_Utilization(%)", + "ParentCategory": "Ports_Utilized_3m", + "Level": 5, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_2_3_10", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( a / ( 3 * ( b if smt_on else ( c ) ) ) )", + "BaseFormula": " uops_dispatched.port_2_3_10 / ( 3 * tma_info_core_core_clks )", + "Category": "TMA", + "CountDomain": "Core_Execution", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Load_Op_Utilization(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_........Load_Op_Utilization(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": " UOPS_DISPATCHED.PORT_2_3_10" + }, + { + "MetricName": "Store_Op_Utilization", + "LegacyName": "metric_TMA_........Store_Op_Utilization(%)", + "ParentCategory": "Ports_Utilized_3m", + "Level": 5, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_4_9", + "Alias": "a" + }, + { + "Name": "UOPS_DISPATCHED.PORT_7_8", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a + b ) / ( 4 * ( c if smt_on else ( d ) ) ) )", + "BaseFormula": " ( uops_dispatched.port_4_9 + uops_dispatched.port_7_8 ) / ( 4 * tma_info_core_core_clks )", + "Category": "TMA", + "CountDomain": "Core_Execution", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Store_Op_Utilization(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_........Store_Op_Utilization(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": " UOPS_DISPATCHED.PORT_7_8" + }, + { + "MetricName": "Retiring", + "LegacyName": "metric_TMA_Retiring(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b + c + a + d ) )", + "BaseFormula": " perf_metrics.retiring / ( perf_metrics.frontend_bound + perf_metrics.bad_speculation + perf_metrics.retiring + perf_metrics.backend_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Retiring(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 70 | b > 10", + "BaseFormula": "metric_TMA_Retiring(%) > 70 | metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvUW;TmaL1", + "LocateWith": " UOPS_RETIRED.SLOTS" + }, + { + "MetricName": "Light_Operations", + "LegacyName": "metric_TMA_..Light_Operations(%)", + "ParentCategory": "Retiring", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations , instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) )", + "BaseFormula": " max( 0 , tma_retiring - tma_heavy_operations )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Retire;TmaL2", + "LocateWith": "INST_RETIRED.PREC_DIST" + }, + { + "MetricName": "FP_Arith", + "LegacyName": "metric_TMA_....FP_Arith(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "UOPS_EXECUTED.X87", + "Alias": "e" + }, + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "f" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "g" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR", + "Alias": "h" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "i" + }, + { + "Name": "FP_ARITH_INST_RETIRED.VECTOR", + "Alias": "j" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.VECTOR", + "Alias": "k" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a / ( b + c + a + d ) ) * e / f ) + ( ( g + h ) / ( ( a / ( b + c + a + d ) ) * ( i ) ) ) + ( ( j + k ) / ( ( a / ( b + c + a + d ) ) * ( i ) ) ) )", + "BaseFormula": " tma_x87_use + tma_fp_scalar + tma_fp_vector", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....FP_Arith(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 20 & b > 60", + "BaseFormula": "metric_TMA_....FP_Arith(%) > 20 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC", + "LocateWith": "" + }, + { + "MetricName": "X87_Use", + "LegacyName": "metric_TMA_......X87_Use(%)", + "ParentCategory": "FP_Arith", + "Level": 4, + "BriefDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "UOPS_EXECUTED.X87", + "Alias": "e" + }, + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b + c + a + d ) ) * e / f )", + "BaseFormula": " tma_retiring * uops_executed.x87 / uops_executed.thread", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......X87_Use(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....FP_Arith(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 60", + "BaseFormula": "metric_TMA_......X87_Use(%) > 10 & metric_TMA_....FP_Arith(%) > 20 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute", + "LocateWith": "" + }, + { + "MetricName": "FP_Scalar", + "LegacyName": "metric_TMA_......FP_Scalar(%)", + "ParentCategory": "FP_Arith", + "Level": 4, + "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) )", + "BaseFormula": " ( fp_arith_inst_retired.scalar + fp_arith_inst_retired2.scalar ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......FP_Scalar(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....FP_Arith(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 60", + "BaseFormula": "metric_TMA_......FP_Scalar(%) > 10 & metric_TMA_....FP_Arith(%) > 20 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops", + "LocateWith": "" + }, + { + "MetricName": "FP_Vector", + "LegacyName": "metric_TMA_......FP_Vector(%)", + "ParentCategory": "FP_Arith", + "Level": 4, + "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.VECTOR", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.VECTOR", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) )", + "BaseFormula": " ( fp_arith_inst_retired.vector + fp_arith_inst_retired2.vector ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......FP_Vector(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....FP_Arith(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 60", + "BaseFormula": "metric_TMA_......FP_Vector(%) > 10 & metric_TMA_....FP_Arith(%) > 20 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops", + "LocateWith": "" + }, + { + "MetricName": "FP_Vector_128b", + "LegacyName": "metric_TMA_........FP_Vector_128b(%)", + "ParentCategory": "FP_Vector", + "Level": 5, + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting prior to LNL.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b + c ) / ( ( d / ( e + f + d + g ) ) * ( h ) ) )", + "BaseFormula": " ( fp_arith_inst_retired.128b_packed_double + fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired2.128b_packed_half ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........FP_Vector_128b(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......FP_Vector(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....FP_Arith(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 60", + "BaseFormula": "metric_TMA_........FP_Vector_128b(%) > 10 & metric_TMA_......FP_Vector(%) > 10 & metric_TMA_....FP_Arith(%) > 20 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops", + "LocateWith": "" + }, + { + "MetricName": "FP_Vector_256b", + "LegacyName": "metric_TMA_........FP_Vector_256b(%)", + "ParentCategory": "FP_Vector", + "Level": 5, + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting prior to LNL.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b + c ) / ( ( d / ( e + f + d + g ) ) * ( h ) ) )", + "BaseFormula": " ( fp_arith_inst_retired.256b_packed_double + fp_arith_inst_retired.256b_packed_single + fp_arith_inst_retired2.256b_packed_half ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........FP_Vector_256b(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......FP_Vector(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....FP_Arith(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 60", + "BaseFormula": "metric_TMA_........FP_Vector_256b(%) > 10 & metric_TMA_......FP_Vector(%) > 10 & metric_TMA_....FP_Arith(%) > 20 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops", + "LocateWith": "" + }, + { + "MetricName": "FP_Vector_512b", + "LegacyName": "metric_TMA_........FP_Vector_512b(%)", + "ParentCategory": "FP_Vector", + "Level": 5, + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b + c ) / ( ( d / ( e + f + d + g ) ) * ( h ) ) )", + "BaseFormula": " ( fp_arith_inst_retired.512b_packed_double + fp_arith_inst_retired.512b_packed_single + fp_arith_inst_retired2.512b_packed_half ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........FP_Vector_512b(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......FP_Vector(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....FP_Arith(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 60", + "BaseFormula": "metric_TMA_........FP_Vector_512b(%) > 10 & metric_TMA_......FP_Vector(%) > 10 & metric_TMA_....FP_Arith(%) > 20 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops", + "LocateWith": "" + }, + { + "MetricName": "Int_Operations", + "LegacyName": "metric_TMA_....Int_Operations(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired). Vector/Matrix Int operations and shuffles are counted. Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_VEC_RETIRED.ADD_128", + "Alias": "a" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_128", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "INT_VEC_RETIRED.ADD_256", + "Alias": "h" + }, + { + "Name": "INT_VEC_RETIRED.MUL_256", + "Alias": "i" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_256", + "Alias": "j" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) ) + ( ( h + i + j ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) ) )", + "BaseFormula": " tma_int_vector_128b + tma_int_vector_256b", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Int_Operations(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 60", + "BaseFormula": "metric_TMA_....Int_Operations(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Int_Vector_128b", + "LegacyName": "metric_TMA_......Int_Vector_128b(%)", + "ParentCategory": "Int_Operations", + "Level": 4, + "BriefDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_VEC_RETIRED.ADD_128", + "Alias": "a" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_128", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) )", + "BaseFormula": " ( int_vec_retired.add_128 + int_vec_retired.vnni_128 ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Int_Vector_128b(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Int_Operations(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 60", + "BaseFormula": "metric_TMA_......Int_Vector_128b(%) > 10 & metric_TMA_....Int_Operations(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;IntVector;Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Int_Vector_256b", + "LegacyName": "metric_TMA_......Int_Vector_256b(%)", + "ParentCategory": "Int_Operations", + "Level": 4, + "BriefDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_VEC_RETIRED.ADD_256", + "Alias": "a" + }, + { + "Name": "INT_VEC_RETIRED.MUL_256", + "Alias": "b" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_256", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b + c ) / ( ( d / ( e + f + d + g ) ) * ( h ) ) )", + "BaseFormula": " ( int_vec_retired.add_256 + int_vec_retired.mul_256 + int_vec_retired.vnni_256 ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Int_Vector_256b(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Int_Operations(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 60", + "BaseFormula": "metric_TMA_......Int_Vector_256b(%) > 10 & metric_TMA_....Int_Operations(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;IntVector;Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Memory_Operations", + "LegacyName": "metric_TMA_....Memory_Operations(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations , uops for memory load or store accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "MEM_UOP_RETIRED.ANY", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * f / ( ( a / ( b + c + a + d ) ) * ( g ) ) )", + "BaseFormula": " tma_light_operations * mem_uop_retired.any / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Memory_Operations(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 60", + "BaseFormula": "metric_TMA_....Memory_Operations(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Fused_Instructions", + "LegacyName": "metric_TMA_....Fused_Instructions(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions , where one uop can represent multiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Other_Light_Ops in MTL!)}", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "INST_RETIRED.MACRO_FUSED", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * f / ( ( a / ( b + c + a + d ) ) * ( g ) ) )", + "BaseFormula": " tma_light_operations * inst_retired.macro_fused / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Fused_Instructions(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 60", + "BaseFormula": "metric_TMA_....Fused_Instructions(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;BvBO;Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Non_Fused_Branches", + "LegacyName": "metric_TMA_....Non_Fused_Branches(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "f" + }, + { + "Name": "INST_RETIRED.MACRO_FUSED", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * ( f - g ) / ( ( a / ( b + c + a + d ) ) * ( h ) ) )", + "BaseFormula": " tma_light_operations * ( br_inst_retired.all_branches - inst_retired.macro_fused ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Non_Fused_Branches(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 60", + "BaseFormula": "metric_TMA_....Non_Fused_Branches(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;BvBO;Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Other_Light_Ops", + "LegacyName": "metric_TMA_....Other_Light_Ops(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "UOPS_EXECUTED.X87", + "Alias": "f" + }, + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "g" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "h" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR", + "Alias": "i" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "j" + }, + { + "Name": "FP_ARITH_INST_RETIRED.VECTOR", + "Alias": "k" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.VECTOR", + "Alias": "l" + }, + { + "Name": "INT_VEC_RETIRED.ADD_128", + "Alias": "m" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_128", + "Alias": "n" + }, + { + "Name": "INT_VEC_RETIRED.ADD_256", + "Alias": "o" + }, + { + "Name": "INT_VEC_RETIRED.MUL_256", + "Alias": "p" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_256", + "Alias": "q" + }, + { + "Name": "MEM_UOP_RETIRED.ANY", + "Alias": "r" + }, + { + "Name": "INST_RETIRED.MACRO_FUSED", + "Alias": "s" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "t" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) - ( ( ( ( a / ( b + c + a + d ) ) * f / g ) + ( ( h + i ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( ( k + l ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) ) + ( ( ( m + n ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( ( o + p + q ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * r / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * s / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * ( t - s ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) ) ) )", + "BaseFormula": " max( 0 , tma_light_operations - ( tma_fp_arith + tma_int_operations + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Other_Light_Ops(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 30 & b > 60", + "BaseFormula": "metric_TMA_....Other_Light_Ops(%) > 30 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Nop_Instructions", + "LegacyName": "metric_TMA_......Nop_Instructions(%)", + "ParentCategory": "Other_Light_Ops", + "Level": 4, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "INST_RETIRED.NOP", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * f / ( ( a / ( b + c + a + d ) ) * ( g ) ) )", + "BaseFormula": " tma_light_operations * inst_retired.nop / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Nop_Instructions(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Other_Light_Ops(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 30 & c > 60", + "BaseFormula": "metric_TMA_......Nop_Instructions(%) > 10 & metric_TMA_....Other_Light_Ops(%) > 30 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvBO;Pipeline", + "LocateWith": " INST_RETIRED.NOP" + }, + { + "MetricName": "Shuffles_256b", + "LegacyName": "metric_TMA_......Shuffles_256b(%)", + "ParentCategory": "Other_Light_Ops", + "Level": 4, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP or Integer). Shuffles may incur slow cross \"vector lane\" data transfers.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "INT_VEC_RETIRED.SHUFFLES", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * f / ( ( a / ( b + c + a + d ) ) * ( g ) ) )", + "BaseFormula": " tma_light_operations * int_vec_retired.shuffles / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Shuffles_256b(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Other_Light_Ops(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 30 & c > 60", + "BaseFormula": "metric_TMA_......Shuffles_256b(%) > 10 & metric_TMA_....Other_Light_Ops(%) > 30 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Heavy_Operations", + "LegacyName": "metric_TMA_..Heavy_Operations(%)", + "ParentCategory": "Retiring", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations , instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.([ICL+] Note this may overcount due to approximation using indirect events; [ADL+])", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b + c + d + e ) )", + "BaseFormula": " perf_metrics.heavy_operations / ( perf_metrics.frontend_bound + perf_metrics.bad_speculation + perf_metrics.retiring + perf_metrics.backend_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Retire;TmaL2", + "LocateWith": " UOPS_RETIRED.HEAVY" + }, + { + "MetricName": "Few_Uops_Instructions", + "LegacyName": "metric_TMA_....Few_Uops_Instructions(%)", + "ParentCategory": "Heavy_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or more uops. This highly-correlates with the number of uops in such instructions.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "UOPS_RETIRED.MS", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b + c + d + e ) ) - ( f / ( g ) ) ) )", + "BaseFormula": " max( 0 , tma_heavy_operations - tma_microcode_sequencer )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Few_Uops_Instructions(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 5 & b > 10", + "BaseFormula": "metric_TMA_....Few_Uops_Instructions(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "$issueD0" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "Microcode_Sequencer", + "LegacyName": "metric_TMA_....Microcode_Sequencer(%)", + "ParentCategory": "Heavy_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.MS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": " uops_retired.ms / tma_info_thread_slots", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Microcode_Sequencer(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 5 & b > 10", + "BaseFormula": "metric_TMA_....Microcode_Sequencer(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "$issueMC, $issueMS" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq", + "LocateWith": " UOPS_RETIRED.MS" + }, + { + "MetricName": "Assists", + "LegacyName": "metric_TMA_......Assists(%)", + "ParentCategory": "Microcode_Sequencer", + "Level": 4, + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ASSISTS.ANY", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * a / ( b ) )", + "BaseFormula": " ( ( 99 *3 + 63 + 30 ) / 5 ) * assists.any / tma_info_thread_slots", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Assists(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Microcode_Sequencer(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 10 & b > 5 & c > 10", + "BaseFormula": "metric_TMA_......Assists(%) > 10 & metric_TMA_....Microcode_Sequencer(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvIO", + "LocateWith": " ASSISTS.ANY" + }, + { + "MetricName": "Page_Faults", + "LegacyName": "metric_TMA_........Page_Faults(%)", + "ParentCategory": "Assists", + "Level": 5, + "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults. A Page Fault may apply on first application access to a memory page. Note operating system handling of page faults accounts for the majority of its cost.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ASSISTS.PAGE_FAULT", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 99 * a / ( b ) )", + "BaseFormula": " 99 * assists.page_fault / tma_info_thread_slots", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Page_Faults(%)" + } + ], + "Formula": "a > 5", + "BaseFormula": "metric_TMA_........Page_Faults(%) > 5", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "FP_Assists", + "LegacyName": "metric_TMA_........FP_Assists(%)", + "ParentCategory": "Assists", + "Level": 5, + "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ASSISTS.FP", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 30 * a / ( b ) )", + "BaseFormula": " 30 * assists.fp / tma_info_thread_slots", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........FP_Assists(%)" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_........FP_Assists(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC", + "LocateWith": "" + }, + { + "MetricName": "AVX_Assists", + "LegacyName": "metric_TMA_........AVX_Assists(%)", + "ParentCategory": "Assists", + "Level": 5, + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists. ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ASSISTS.SSE_AVX_MIX", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 63 * a / ( b ) )", + "BaseFormula": " 63 * assists.sse_avx_mix / tma_info_thread_slots", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........AVX_Assists(%)" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_........AVX_Assists(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC", + "LocateWith": "" + }, + { + "MetricName": "CISC", + "LegacyName": "metric_TMA_......CISC(%)", + "ParentCategory": "Microcode_Sequencer", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.MS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b ) ) - ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c / ( b ) ) ) )", + "BaseFormula": " max( 0 , tma_microcode_sequencer - tma_assists )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......CISC(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Microcode_Sequencer(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 10 & b > 5 & c > 10", + "BaseFormula": "metric_TMA_......CISC(%) > 10 & metric_TMA_....Microcode_Sequencer(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": " #NA" + }, + { + "MetricName": "Info_Botlnk_L0_Core_Bound_Likely", + "LegacyName": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely", + "Level": 1, + "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "e" + }, + { + "Name": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "Alias": "f" + }, + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "g" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "h" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "i" + }, + { + "Name": "EXE_ACTIVITY.2_3_PORTS_UTIL", + "Alias": "j" + }, + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "k" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "l" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "m" + }, + { + "Name": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "Alias": "n" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "Alias": "o" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( 1 - ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) / ( ( ( max( f - g , 0 ) / ( h ) ) * ( h ) + ( i + ( d / ( b + c + d + a ) ) * j ) ) / ( h ) if ( k < ( l - m ) ) else ( i + ( d / ( b + c + d + a ) ) * j ) / ( h ) ) if ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) < ( ( ( max( f - g , 0 ) / ( h ) ) * ( h ) + ( i + ( d / ( b + c + d + a ) ) * j ) ) / ( h ) if ( k < ( l - m ) ) else ( i + ( d / ( b + c + d + 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Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.VECTOR", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.VECTOR", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "a / ( ( b + c ) + ( d + e ) )", + "BaseFormula": " inst_retired.any / ( ( fp_arith_inst_retired.scalar + fp_arith_inst_retired2.scalar ) + ( fp_arith_inst_retired.vector + fp_arith_inst_retired2.vector ) )", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpArith" + } + ], + "Formula": "a < 10", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpArith < 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_Scalar_HP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_HP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Half-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " inst_retired.any / fp_arith_inst_retired2.scalar", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_HP" + } + ], + "Formula": "a < 10", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_HP < 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpScalar;InsType;Server", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_Scalar_SP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_SP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " inst_retired.any / fp_arith_inst_retired.scalar_single", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_SP" + } + ], + "Formula": "a < 10", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_SP < 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpScalar;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_Scalar_DP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_DP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " inst_retired.any / fp_arith_inst_retired.scalar_double", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_DP" + } + ], + "Formula": "a < 10", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_DP < 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpScalar;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX128", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX128", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "a / ( b + c + d )", + "BaseFormula": " inst_retired.any / ( fp_arith_inst_retired.128b_packed_double + fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired2.128b_packed_half )", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpArith_AVX128" + } + ], + "Formula": "a < 10", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpArith_AVX128 < 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX256", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX256", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "a / ( b + c + d )", + "BaseFormula": " inst_retired.any / ( fp_arith_inst_retired.256b_packed_double + fp_arith_inst_retired.256b_packed_single + fp_arith_inst_retired2.256b_packed_half )", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpArith_AVX256" + } + ], + "Formula": "a < 10", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpArith_AVX256 < 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX512", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX512", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "a / ( b + c + d )", + "BaseFormula": " inst_retired.any / ( fp_arith_inst_retired.512b_packed_double + fp_arith_inst_retired.512b_packed_single + fp_arith_inst_retired2.512b_packed_half )", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpArith_AVX512" + } + ], + "Formula": "a < 10", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpArith_AVX512 < 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpPause", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpPause", + "Level": 1, + "BriefDescription": "Instructions per PAUSE (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.PAUSE_INST", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "BaseFormula": " tma_info_inst_mix_instructions / cpu_clk_unhalted.pause_inst", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpSWPF", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpSWPF", + "Level": 1, + "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "SW_PREFETCH_ACCESS.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " inst_retired.any / sw_prefetch_access.any", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpSWPF" + } + ], + "Formula": "a < 100", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpSWPF < 100", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Prefetches", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_Instructions", + "LegacyName": "metric_TMA_Info_Inst_Mix_Instructions", + "Level": 1, + "BriefDescription": "Total number of retired Instructions", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "BaseFormula": " inst_retired.any", + "Category": "TMA", + "CountDomain": "Count", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary;TmaL1", + "LocateWith": "INST_RETIRED.PREC_DIST" + }, + { + "MetricName": "Info_Pipeline_Retire", + "LegacyName": "metric_TMA_Info_Pipeline_Retire", + "Level": 1, + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "e" + }, + { + "Name": "UOPS_RETIRED.SLOTS:c1", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "( ( a / ( b + c + a + d ) ) * ( e ) ) / f", + "BaseFormula": " ( tma_retiring * tma_info_thread_slots ) / uops_retired.slots:c1", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline;Ret", + "LocateWith": "" + }, + { + "MetricName": "Info_Pipeline_Strings_Cycles", + "LegacyName": "metric_TMA_Info_Pipeline_Strings_Cycles", + "Level": 1, + "BriefDescription": "Estimated fraction of retirement-cycles dealing with repeat instructions", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.REP_ITERATION", + "Alias": "a" + }, + { + "Name": "UOPS_RETIRED.SLOTS:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " inst_retired.rep_iteration / uops_retired.slots:c1", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Pipeline_Strings_Cycles" + } + ], + "Formula": "a > 0.1", + "BaseFormula": "metric_TMA_Info_Pipeline_Strings_Cycles > 0.1", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq;Pipeline;Ret", + "LocateWith": "" + }, + { + "MetricName": "Info_Pipeline_IpAssist", + "LegacyName": "metric_TMA_Info_Pipeline_IpAssist", + "Level": 1, + "BriefDescription": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " inst_retired.any / assists.any", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Pipeline_IpAssist" + } + ], + "Formula": "a < 100000", + "BaseFormula": "metric_TMA_Info_Pipeline_IpAssist < 100000", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq;Pipeline;Ret;Retire", + "LocateWith": "" + }, + { + "MetricName": "Info_Pipeline_Execute", + "LegacyName": "metric_TMA_Info_Pipeline_Execute", + "Level": 1, + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per core", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "Alias": "b" + }, + { + "Name": "UOPS_EXECUTED.THREAD:c1", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "a / ( ( b / 2 ) if smt_on else c )", + "BaseFormula": " uops_executed.thread / ( ( uops_executed.core_cycles_ge_1 / 2 ) if smt_on else uops_executed.thread:c1 )", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "LocateWith": "" + }, + { + "MetricName": "Info_Pipeline_Fetch_DSB", + "LegacyName": "metric_TMA_Info_Pipeline_Fetch_DSB", + "Level": 1, + "BriefDescription": "Average number of uops fetched from DSB per cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.DSB_CYCLES_ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " idq.dsb_uops / idq.dsb_cycles_any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Pipeline_Fetch_MITE", + "LegacyName": "metric_TMA_Info_Pipeline_Fetch_MITE", + "Level": 1, + "BriefDescription": "Average number of uops fetched from MITE per cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ.MITE_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_CYCLES_ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " idq.mite_uops / idq.mite_cycles_any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_Fetch_UpC", + "LegacyName": "metric_TMA_Info_Frontend_Fetch_UpC", + "Level": 1, + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " uops_issued.any / uops_issued.any:c1", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_DSB_Coverage", + "LegacyName": "metric_TMA_Info_Frontend_DSB_Coverage", + "Level": 1, + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "BaseFormula": " idq.dsb_uops / ( uops_issued.any )", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Frontend_DSB_Coverage" + }, + { + "Alias": "b", + "Value": "metric_TMA_Info_Thread_IPC" + } + ], + "Formula": "a < 0.7 & b / 6 > 0.35", + "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & metric_TMA_Info_Thread_IPC / 6 > 0.35", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSB;Fed;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_Unknown_Branch_Cost", + "LegacyName": "metric_TMA_Info_Frontend_Unknown_Branch_Cost", + "Level": 1, + "BriefDescription": "Average number of cycles the front-end was delayed due to an Unknown Branch detection. See Unknown_Branches node.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "a" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES:c1:e1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " int_misc.unknown_branch_cycles / int_misc.unknown_branch_cycles:c1:e1", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_DSB_Switch_Cost", + "LegacyName": "metric_TMA_Info_Frontend_DSB_Switch_Cost", + "Level": 1, + "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "a" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES:c1:e1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " dsb2mite_switches.penalty_cycles / dsb2mite_switches.penalty_cycles:c1:e1", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_TBpC", + "LegacyName": "metric_TMA_Info_Frontend_TBpC", + "Level": 1, + "BriefDescription": "Taken Branches retired Per Cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "BaseFormula": " br_inst_retired.near_taken / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_DSB_Switches_Ret", + "LegacyName": "metric_TMA_Info_Frontend_DSB_Switches_Ret", + "Level": 1, + "BriefDescription": "This metric represents fraction of cycles the CPU retirement was stalled likely due to retired DSB misses", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FRONTEND_RETIRED.ANY_DSB_MISS", + "Alias": "a" + }, + { + "Name": "FRONTEND_RETIRED.ANY_DSB_MISS:retire_latency", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "( a * b ) / ( c )", + "BaseFormula": " ( frontend_retired.any_dsb_miss * frontend_retired.any_dsb_miss:retire_latency ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Frontend_DSB_Switches_Ret" + } + ], + "Formula": "a > 0.05", + "BaseFormula": "metric_TMA_Info_Frontend_DSB_Switches_Ret > 0.05", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;Fed;FetchLat", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_MS_Latency_Ret", + "LegacyName": "metric_TMA_Info_Frontend_MS_Latency_Ret", + "Level": 1, + "BriefDescription": "This metric represents fraction of cycles the CPU retirement was stalled likely due to retired operations that invoke the Microcode Sequencer", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FRONTEND_RETIRED.MS_FLOWS", + "Alias": "a" + }, + { + "Name": "FRONTEND_RETIRED.MS_FLOWS:retire_latency", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "( a * b ) / ( c )", + "BaseFormula": " ( frontend_retired.ms_flows * frontend_retired.ms_flows:retire_latency ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Frontend_MS_Latency_Ret" + } + ], + "Formula": "a > 0.05", + "BaseFormula": "metric_TMA_Info_Frontend_MS_Latency_Ret > 0.05", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchLat;MicroSeq", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_Unknown_Branches_Ret", + "LegacyName": "metric_TMA_Info_Frontend_Unknown_Branches_Ret", + "Level": 1, + "BriefDescription": "This metric represents fraction of cycles the CPU retirement was stalled likely due to retired branches who got branch address clears", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FRONTEND_RETIRED.UNKNOWN_BRANCH", + "Alias": "a" + }, + { + "Name": "FRONTEND_RETIRED.UNKNOWN_BRANCH:retire_latency", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "( a * b ) / ( c )", + "BaseFormula": " ( frontend_retired.unknown_branch * frontend_retired.unknown_branch:retire_latency ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchLat", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_ICache_Miss_Latency", + "LegacyName": "metric_TMA_Info_Frontend_ICache_Miss_Latency", + "Level": 1, + "BriefDescription": "Average Latency for L1 instruction cache misses", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "a" + }, + { + "Name": "ICACHE_DATA.STALL_PERIODS", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " icache_data.stalls / icache_data.stall_periods", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchLat;IcMiss", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_IpDSB_Miss_Ret", + "LegacyName": "metric_TMA_Info_Frontend_IpDSB_Miss_Ret", + "Level": 1, + "BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FRONTEND_RETIRED.ANY_DSB_MISS", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " inst_retired.any / frontend_retired.any_dsb_miss", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Frontend_IpDSB_Miss_Ret" + } + ], + "Formula": "a < 50", + "BaseFormula": "metric_TMA_Info_Frontend_IpDSB_Miss_Ret < 50", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;Fed", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_IpUnknown_Branch", + "LegacyName": "metric_TMA_Info_Frontend_IpUnknown_Branch", + "Level": 1, + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "BaseFormula": " tma_info_inst_mix_instructions / baclears.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_L2MPKI_Code", + "LegacyName": "metric_TMA_Info_Frontend_L2MPKI_Code", + "Level": 1, + "BriefDescription": "L2 cache true code cacheline misses per kilo instruction ", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FRONTEND_RETIRED.L2_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": " 1000 * frontend_retired.l2_miss / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "IcMiss", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_L2MPKI_Code_All", + "LegacyName": "metric_TMA_Info_Frontend_L2MPKI_Code_All", + "Level": 1, + "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction ", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.CODE_RD_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": " 1000 * l2_rqsts.code_rd_miss / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "IcMiss", + "LocateWith": "" + }, + { + "MetricName": "Info_Botlnk_L2_DSB_Misses", + "LegacyName": "metric_TMA_Info_Botlnk_L2_DSB_Misses", + "Level": 1, + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "j" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "k" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "l" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "m" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "n" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "o" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "p" + }, + { + "Name": "DECODE.LCP", + "Alias": "q" + }, + { + "Name": "IDQ.MITE_CYCLES_ANY", + "Alias": "r" + }, + { + "Name": "IDQ.MITE_CYCLES_OK", + "Alias": "s" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "t" + }, + { + "Name": "IDQ.DSB_CYCLES_ANY", + "Alias": "u" + }, + { + "Name": "IDQ.DSB_CYCLES_OK", + "Alias": "v" + }, + { + "Name": "IDQ.MS_CYCLES_ANY", + "Alias": "w" + }, + { + "Name": "UOPS_RETIRED.MS:c1", + "Alias": "x" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( h / ( i ) ) / ( ( j / ( i ) ) + ( k / ( i ) ) + ( l / ( i ) + ( m / ( i ) ) ) + ( ( 3 ) * n / ( o / p ) / ( i ) ) + ( q / ( i ) ) + ( h / ( i ) ) ) + ( max( 0 , ( b / ( b + c + d + e ) - f / ( g ) ) - ( ( a / ( b + c + d + e ) - f / ( g ) ) ) ) ) * ( ( r - s ) / ( t if smt_on else ( i ) ) / 2 ) / ( ( ( r - s ) / ( t if smt_on else ( i ) ) / 2 ) + ( ( u - v ) / ( t if smt_on else ( i ) ) / 2 ) + ( max( w , x / ( o / p ) ) / ( t if smt_on else ( i ) ) / 2 ) ) )", + "BaseFormula": " 100 * ( tma_fetch_latency * tma_dsb_switches / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_mite / ( tma_mite + tma_dsb + tma_ms ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Misses" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Misses > 10", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;Fed", + "LocateWith": "" + }, + { + "MetricName": "Info_Botlnk_L2_DSB_Bandwidth", + "LegacyName": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth", + "Level": 1, + "BriefDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "g" + }, + { + "Name": "IDQ.DSB_CYCLES_ANY", + "Alias": "h" + }, + { + "Name": "IDQ.DSB_CYCLES_OK", + "Alias": "i" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "j" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "k" + }, + { + "Name": "IDQ.MITE_CYCLES_ANY", + "Alias": "l" + }, + { + "Name": "IDQ.MITE_CYCLES_OK", + "Alias": "m" + }, + { + "Name": "IDQ.MS_CYCLES_ANY", + "Alias": "n" + }, + { + "Name": "UOPS_RETIRED.MS:c1", + "Alias": "o" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "p" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "q" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a / ( a + b + c + d ) - e / ( f ) ) * ( ( max( 0 , ( a / ( a + b + c + d ) - e / ( f ) ) - ( ( g / ( a + b + c + d ) - e / ( f ) ) ) ) ) / ( ( ( g / ( a + b + c + d ) - e / ( f ) ) ) + ( max( 0 , ( a / ( a + b + c + d ) - e / ( f ) ) - ( ( g / ( a + b + c + d ) - e / ( f ) ) ) ) ) ) ) * ( ( ( h - i ) / ( j if smt_on else ( k ) ) / 2 ) / ( ( ( l - m ) / ( j if smt_on else ( k ) ) / 2 ) + ( ( h - i ) / ( j if smt_on else ( k ) ) / 2 ) + ( max( n , o / ( p / q ) ) / ( j if smt_on else ( k ) ) / 2 ) ) ) )", + "BaseFormula": " 100 * ( tma_frontend_bound * ( tma_fetch_bandwidth / ( tma_fetch_latency + tma_fetch_bandwidth ) ) * ( tma_dsb / ( tma_mite + tma_dsb + tma_ms ) ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth > 10", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSB;Fed;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Botlnk_L2_IC_Misses", + "LegacyName": "metric_TMA_Info_Botlnk_L2_IC_Misses", + "Level": 1, + "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "j" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "k" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "l" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "m" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "n" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "o" + }, + { + "Name": "DECODE.LCP", + "Alias": "p" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "q" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( h / ( i ) ) / ( ( h / ( i ) ) + ( j / ( i ) ) + ( k / ( i ) + ( l / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) )", + "BaseFormula": " 100 * ( tma_fetch_latency * tma_icache_misses / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Botlnk_L2_IC_Misses" + } + ], + "Formula": "a > 5", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_IC_Misses > 5", + "ThresholdIssues": "$issueFL" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchLat;IcMiss", + "LocateWith": "" + }, + { + "MetricName": "Info_Bad_Spec_IpMispredict", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMispredict", + "Level": 1, + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " inst_retired.any / br_misp_retired.all_branches", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Bad_Spec_IpMispredict" + } + ], + "Formula": "a < 200", + "BaseFormula": "metric_TMA_Info_Bad_Spec_IpMispredict < 200", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "LocateWith": "" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Cond_Ntaken", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Cond_Ntaken", + "Level": 1, + "BriefDescription": "Instructions per retired Mispredicts for conditional non-taken branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.COND_NTAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " inst_retired.any / br_misp_retired.cond_ntaken", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Bad_Spec_IpMisp_Cond_Ntaken" + } + ], + "Formula": "a < 200", + "BaseFormula": "metric_TMA_Info_Bad_Spec_IpMisp_Cond_Ntaken < 200", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts", + "LocateWith": "" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Cond_Taken", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Cond_Taken", + "Level": 1, + "BriefDescription": "Instructions per retired Mispredicts for conditional taken branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.COND_TAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " inst_retired.any / br_misp_retired.cond_taken", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Bad_Spec_IpMisp_Cond_Taken" + } + ], + "Formula": "a < 200", + "BaseFormula": "metric_TMA_Info_Bad_Spec_IpMisp_Cond_Taken < 200", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts", + "LocateWith": "" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Ret", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Ret", + "Level": 1, + "BriefDescription": "Instructions per retired Mispredicts for return branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.RET", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " inst_retired.any / br_misp_retired.ret", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Bad_Spec_IpMisp_Ret" + } + ], + "Formula": "a < 500", + "BaseFormula": "metric_TMA_Info_Bad_Spec_IpMisp_Ret < 500", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts", + "LocateWith": "" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Indirect", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Indirect", + "Level": 1, + "BriefDescription": "Instructions per retired Mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.INDIRECT", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " inst_retired.any / br_misp_retired.indirect", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Bad_Spec_IpMisp_Indirect" + } + ], + "Formula": "a < 1000", + "BaseFormula": "metric_TMA_Info_Bad_Spec_IpMisp_Indirect < 1000", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts", + "LocateWith": "" + }, + { + "MetricName": "Info_Bad_Spec_Branch_Misprediction_Cost", + "LegacyName": "metric_TMA_Info_Bad_Spec_Branch_Misprediction_Cost", + "Level": 1, + "BriefDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.MS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "h" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "i" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "j" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "k" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "l" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "m" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "n" + }, + { + "Name": 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) ) ) ) * ( b ) / ( 6 ) / h / 100", + "BaseFormula": " tma_bottleneck_mispredictions * tma_info_thread_slots / ( 6 ) / br_misp_retired.all_branches / 100", + "Category": "TMA", + "CountDomain": "Core_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "$issueBM" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts", + "LocateWith": "" + }, + { + "MetricName": "Info_Bad_Spec_Spec_Clears_Ratio", + "LegacyName": "metric_TMA_Info_Bad_Spec_Spec_Clears_Ratio", + "Level": 1, + "BriefDescription": "Speculative to Retired ratio of all clears (covering Mispredicts and nukes)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "b" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "BaseFormula": " int_misc.clears_count / ( br_misp_retired.all_branches + machine_clears.count )", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BrMispredicts", + "LocateWith": "" + }, + { + "MetricName": "Info_Branches_Cond_NT", + "LegacyName": "metric_TMA_Info_Branches_Cond_NT", + "Level": 1, + "BriefDescription": "Fraction of branches that are non-taken conditionals", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.COND_NTAKEN", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " br_inst_retired.cond_ntaken / br_inst_retired.all_branches", + "Category": "TMA", + "CountDomain": "Fraction", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "LocateWith": "" + }, + { + "MetricName": "Info_Branches_Cond_TK", + "LegacyName": "metric_TMA_Info_Branches_Cond_TK", + "Level": 1, + "BriefDescription": "Fraction of branches that are taken conditionals", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.COND_TAKEN", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " br_inst_retired.cond_taken / br_inst_retired.all_branches", + "Category": "TMA", + "CountDomain": "Fraction", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "LocateWith": "" + }, + { + "MetricName": "Info_Branches_CallRet", + "LegacyName": "metric_TMA_Info_Branches_CallRet", + "Level": 1, + "BriefDescription": "Fraction of branches that are CALL or RET", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_RETURN", + "Alias": "b" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "( a + b ) / c", + "BaseFormula": " ( br_inst_retired.near_call + br_inst_retired.near_return ) / br_inst_retired.all_branches", + "Category": "TMA", + "CountDomain": "Fraction", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches", + "LocateWith": "" + }, + { + "MetricName": "Info_Branches_Jump", + "LegacyName": "metric_TMA_Info_Branches_Jump", + "Level": 1, + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.COND_TAKEN", + "Alias": "b" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "c" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "( a - b - 2 * c ) / d", + "BaseFormula": " ( br_inst_retired.near_taken - br_inst_retired.cond_taken - 2 * br_inst_retired.near_call ) / br_inst_retired.all_branches", + "Category": "TMA", + "CountDomain": "Fraction", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches", + "LocateWith": "" + }, + { + "MetricName": "Info_Branches_Other_Branches", + "LegacyName": "metric_TMA_Info_Branches_Other_Branches", + "Level": 1, + "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.COND_NTAKEN", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + }, + { + "Name": "BR_INST_RETIRED.COND_TAKEN", + "Alias": "c" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "d" + }, + { + "Name": "BR_INST_RETIRED.NEAR_RETURN", + "Alias": "e" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "1 - ( ( a / b ) + ( c / b ) + ( ( d + e ) / b ) + ( ( f - c - 2 * d ) / b ) )", + "BaseFormula": " 1 - ( tma_info_branches_cond_nt + tma_info_branches_cond_tk + tma_info_branches_callret + tma_info_branches_jump )", + "Category": "TMA", + "CountDomain": "Fraction", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Load_Miss_Real_Latency", + "LegacyName": "metric_TMA_Info_Memory_Load_Miss_Real_Latency", + "Level": 1, + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_COMPLETED.L1_MISS_ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " l1d_pend_miss.pending / mem_load_completed.l1_miss_any", + "Category": "TMA", + "CountDomain": "Clocks_Latency", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_MLP", + "LegacyName": "metric_TMA_Info_Memory_MLP", + "Level": 1, + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a" + }, + { + "Name": "L1D_PEND_MISS.PENDING_CYCLES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " l1d_pend_miss.pending / l1d_pend_miss.pending_cycles", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBound;MemoryBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_L1MPKI", + "LegacyName": "metric_TMA_Info_Memory_L1MPKI", + "Level": 1, + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": " 1000 * mem_load_retired.l1_miss / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_L1MPKI_Load", + "LegacyName": "metric_TMA_Info_Memory_L1MPKI_Load", + "Level": 1, + "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": " 1000 * l2_rqsts.all_demand_data_rd / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_L2MPKI", + "LegacyName": "metric_TMA_Info_Memory_L2MPKI", + "Level": 1, + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": " 1000 * mem_load_retired.l2_miss / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;Backend;CacheHits", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_L2MPKI_All", + "LegacyName": "metric_TMA_Info_Memory_L2MPKI_All", + "Level": 1, + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": " 1000 * l2_rqsts.miss / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_L2MPKI_Load", + "LegacyName": "metric_TMA_Info_Memory_L2MPKI_Load", + "Level": 1, + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": " 1000 * l2_rqsts.demand_data_rd_miss / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_L2MPKI_RFO", + "LegacyName": "metric_TMA_Info_Memory_L2MPKI_RFO", + "Level": 1, + "BriefDescription": "Offcore requests (L2 cache miss) per kilo instruction for demand RFOs", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.RFO_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": " 1000 * l2_rqsts.rfo_miss / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheMisses;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_L2HPKI_All", + "LegacyName": "metric_TMA_Info_Memory_L2HPKI_All", + "Level": 1, + "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.REFERENCES", + "Alias": "a" + }, + { + "Name": "L2_RQSTS.MISS", + "Alias": "b" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "1000 * ( a - b ) / c", + "BaseFormula": " 1000 * ( l2_rqsts.references - l2_rqsts.miss ) / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_L2HPKI_Load", + "LegacyName": "metric_TMA_Info_Memory_L2HPKI_Load", + "Level": 1, + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": " 1000 * l2_rqsts.demand_data_rd_hit / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_L3MPKI", + "LegacyName": "metric_TMA_Info_Memory_L3MPKI", + "Level": 1, + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L3_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": " 1000 * mem_load_retired.l3_miss / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_FB_HPKI", + "LegacyName": "metric_TMA_Info_Memory_FB_HPKI", + "Level": 1, + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": " 1000 * mem_load_retired.fb_hit / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Mem", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_L1D_Cache_Fill_BW", + "LegacyName": "metric_TMA_Info_Memory_L1D_Cache_Fill_BW", + "Level": 1, + "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D.REPLACEMENT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": " 64 * l1d.replacement / ( 1000000000 ) / tma_info_system_time", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_L2_Cache_Fill_BW", + "LegacyName": "metric_TMA_Info_Memory_L2_Cache_Fill_BW", + "Level": 1, + "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_IN.ALL", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": " 64 * l2_lines_in.all / ( 1000000000 ) / tma_info_system_time", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_L3_Cache_Fill_BW", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Fill_BW", + "Level": 1, + "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "LONGEST_LAT_CACHE.MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": " 64 * longest_lat_cache.miss / ( 1000000000 ) / tma_info_system_time", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_L3_Cache_Access_BW", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Access_BW", + "Level": 1, + "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS.ALL_REQUESTS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": " 64 * offcore_requests.all_requests / ( 1000000000 ) / tma_info_system_time", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_TLB_Page_Walks_Utilization", + "LegacyName": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization", + "Level": 1, + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_PENDING", + "Alias": "a" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_PENDING", + "Alias": "b" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_PENDING", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "( a + b + c ) / ( 4 * ( d if smt_on else ( e ) ) )", + "BaseFormula": " ( itlb_misses.walk_pending + dtlb_load_misses.walk_pending + dtlb_store_misses.walk_pending ) / ( 4 * tma_info_core_core_clks )", + "Category": "TMA", + "CountDomain": "Core_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization" + } + ], + "Formula": "a > 0.5", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization > 0.5", + "ThresholdIssues": "" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_TLB_Code_STLB_MPKI", + "LegacyName": "metric_TMA_Info_Memory_TLB_Code_STLB_MPKI", + "Level": 1, + "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": " 1000 * itlb_misses.walk_completed / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_TLB_Load_STLB_MPKI", + "LegacyName": "metric_TMA_Info_Memory_TLB_Load_STLB_MPKI", + "Level": 1, + "BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": " 1000 * dtlb_load_misses.walk_completed / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_TLB_Store_STLB_MPKI", + "LegacyName": "metric_TMA_Info_Memory_TLB_Store_STLB_MPKI", + "Level": 1, + "BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": " 1000 * dtlb_store_misses.walk_completed / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_TLB_Load_STLB_Miss_Ret", + "LegacyName": "metric_TMA_Info_Memory_TLB_Load_STLB_Miss_Ret", + "Level": 1, + "BriefDescription": "This metric represents fraction of cycles the CPU retirement was stalled likely due to STLB misses by demand loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_INST_RETIRED.STLB_MISS_LOADS", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.STLB_MISS_LOADS:retire_latency", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "( a * b ) / ( c )", + "BaseFormula": " ( mem_inst_retired.stlb_miss_loads * mem_inst_retired.stlb_miss_loads:retire_latency ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Memory_TLB_Load_STLB_Miss_Ret" + } + ], + "Formula": "a > 0.05", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Load_STLB_Miss_Ret > 0.05", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_TLB_Store_STLB_Miss_Ret", + "LegacyName": "metric_TMA_Info_Memory_TLB_Store_STLB_Miss_Ret", + "Level": 1, + "BriefDescription": "This metric represents fraction of cycles the CPU retirement was stalled likely due to STLB misses by demand stores", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_INST_RETIRED.STLB_MISS_STORES", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.STLB_MISS_STORES:retire_latency", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "( a * b ) / ( c )", + "BaseFormula": " ( mem_inst_retired.stlb_miss_stores * mem_inst_retired.stlb_miss_stores:retire_latency ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Memory_TLB_Store_STLB_Miss_Ret" + } + ], + "Formula": "a > 0.05", + "BaseFormula": "metric_TMA_Info_Memory_TLB_Store_STLB_Miss_Ret > 0.05", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Core_L1D_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_Core_L1D_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D.REPLACEMENT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "BaseFormula": " tma_info_memory_l1d_cache_fill_bw", + "Category": "TMA", + "CountDomain": "Core_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Core_L2_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_Core_L2_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_IN.ALL", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "BaseFormula": " tma_info_memory_l2_cache_fill_bw", + "Category": "TMA", + "CountDomain": "Core_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Core_L3_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_Core_L3_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "LONGEST_LAT_CACHE.MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "BaseFormula": " tma_info_memory_l3_cache_fill_bw", + "Category": "TMA", + "CountDomain": "Core_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Core_L3_Cache_Access_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_Core_L3_Cache_Access_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS.ALL_REQUESTS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "BaseFormula": " tma_info_memory_l3_cache_access_bw", + "Category": "TMA", + "CountDomain": "Core_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Core_L2_Evictions_Silent_PKI", + "LegacyName": "metric_TMA_Info_Memory_Core_L2_Evictions_Silent_PKI", + "Level": 1, + "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_OUT.SILENT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "BaseFormula": " 1000 * l2_lines_out.silent / tma_info_inst_mix_instructions", + "Category": "TMA", + "CountDomain": "Core_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "L2Evicts;Mem;Server", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Core_L2_Evictions_NonSilent_PKI", + "LegacyName": "metric_TMA_Info_Memory_Core_L2_Evictions_NonSilent_PKI", + "Level": 1, + "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_OUT.NON_SILENT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "BaseFormula": " 1000 * l2_lines_out.non_silent / tma_info_inst_mix_instructions", + "Category": "TMA", + "CountDomain": "Core_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "L2Evicts;Mem;Server", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Prefetches_Useless_HWPF", + "LegacyName": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF", + "Level": 1, + "BriefDescription": "Rate of L2 HW prefetched lines that were not used by demand accesses", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_OUT.USELESS_HWPF", + "Alias": "a" + }, + { + "Name": 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Accounts for demand loads and L1/L2 prefetches", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " unc_cha_tor_occupancy.ia_miss_drd / unc_cha_tor_occupancy.ia_miss_drd:c1", + "Category": "TMA", + "CountDomain": "System_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SYSTEM", + "MetricGroup": "Mem;MemoryBW;SoC", + "LocateWith": "" + }, + { + "MetricName": "Info_System_MEM_DRAM_Read_Latency", + "LegacyName": "metric_TMA_Info_System_MEM_DRAM_Read_Latency", + "Level": 1, + "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "( 1000000000 ) * ( a / b ) / c", + "BaseFormula": " ( 1000000000 ) * ( unc_cha_tor_occupancy.ia_miss_drd_ddr / unc_cha_tor_inserts.ia_miss_drd_ddr ) / unc_cha_clockticks:one_unit", + "Category": "TMA", + "CountDomain": "NanoSeconds", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SYSTEM", + "MetricGroup": "MemOffcore;MemoryLat;SoC;Server", + "LocateWith": "" + }, + { + "MetricName": "Info_System_IO_Read_BW", + "LegacyName": "metric_TMA_Info_System_IO_Read_BW", + "Level": 1, + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]. Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "a * 64 / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": " unc_cha_tor_inserts.io_pcirdcur * 64 / ( 1000000000 ) / tma_info_system_time", + "Category": "TMA", + "CountDomain": "GB/sec", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "IoBW;MemOffcore;SoC;Server", + "LocateWith": "" + }, + { + "MetricName": "Info_System_IO_Write_BW", + "LegacyName": "metric_TMA_Info_System_IO_Write_BW", + "Level": 1, + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]. Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a + b ) * 64 / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": " ( unc_cha_tor_inserts.io_itom + unc_cha_tor_inserts.io_itomcachenear ) * 64 / ( 1000000000 ) / tma_info_system_time", + "Category": "TMA", + "CountDomain": "GB/sec", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "IoBW;MemOffcore;SoC;Server", + "LocateWith": "" + }, + { + "MetricName": "Info_System_UPI_Data_Transmit_BW", + "LegacyName": "metric_TMA_Info_System_UPI_Data_Transmit_BW", + "Level": 1, + "BriefDescription": "Cross-socket Ultra Path Interconnect (UPI) data transmit bandwidth for data only [MB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_UPI_TxL_FLITS.ALL_DATA", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a * 64 / 9 / 1000000", + "BaseFormula": " unc_upi_txl_flits.all_data * 64 / 9 / 1000000", + "Category": "TMA", + "CountDomain": "MB/sec", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "UPI, SOCKET, SYSTEM", + "MetricGroup": "SoC;Server", + "LocateWith": "" + }, + { + "MetricName": "Info_System_Power", + "LegacyName": "metric_TMA_Info_System_Power", + "Level": 1, + "BriefDescription": "Total package Power in Watts", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FREERUN_PKG_ENERGY_STATUS", + "Alias": "a" + }, + { + "Name": "FREERUN_DRAM_ENERGY_STATUS", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a * ( 61 ) + 15.6 * b ) / ( ( durationtimeinmilliseconds / 1000 ) * ( 1000000 ) )", + "BaseFormula": " ( freerun_pkg_energy_status * ( 61 ) + 15.6 * freerun_dram_energy_status ) / ( ( duration_time ) * ( 1000000 ) )", + "Category": "TMA", + "CountDomain": "System_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SYSTEM", + "MetricGroup": "Power;SoC", + "LocateWith": "" + }, + { + "MetricName": "Info_System_Time", + "LegacyName": "metric_TMA_Info_System_Time", + "Level": 1, + "BriefDescription": "Run duration time in seconds", + "UnitOfMeasure": "", + "Events": [], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( durationtimeinmilliseconds / 1000 )", + "BaseFormula": " duration_time", + "Category": "TMA", + "CountDomain": "Seconds", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_System_Time" + } + ], + "Formula": "a < 1", + "BaseFormula": "metric_TMA_Info_System_Time < 1", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Summary", + "LocateWith": "" + }, + { + "MetricName": "Info_System_MUX", + "LegacyName": "metric_TMA_Info_System_MUX", + "Level": 1, + "BriefDescription": "PerfMon Event Multiplexing accuracy indicator", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " cpu_clk_unhalted.thread_p / cpu_clk_unhalted.thread", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_System_MUX" + } + ], + "Formula": "a > 1.1 | a < 0.9", + "BaseFormula": "metric_TMA_Info_System_MUX > 1.1 | metric_TMA_Info_System_MUX < 0.9", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary", + "LocateWith": "" + }, + { + "MetricName": "Info_System_Socket_CLKS", + "LegacyName": "metric_TMA_Info_System_Socket_CLKS", + "Level": 1, + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "BaseFormula": " unc_cha_clockticks:one_unit", + "Category": "TMA", + "CountDomain": "Count", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SYSTEM", + "MetricGroup": "SoC", + "LocateWith": "" + }, + { + "MetricName": "Info_System_IpFarBranch", + "LegacyName": "metric_TMA_Info_System_IpFarBranch", + "Level": 1, + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.FAR_BRANCH:USER", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " inst_retired.any / br_inst_retired.far_branch:user", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_System_IpFarBranch" + } + ], + "Formula": "a < 1000000", + "BaseFormula": "metric_TMA_Info_System_IpFarBranch < 1000000", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;OS", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_SoC_R2C_Offcore_BW", + "LegacyName": "metric_TMA_Info_Memory_SoC_R2C_Offcore_BW", + "Level": 1, + "BriefDescription": "Average Off-core access BW for Reads-to-Core (R2C). R2C account for demand or prefetch load/RFO/code access that fill data into the Core caches.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.READS_TO_CORE.ANY_RESPONSE", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / 1e9 / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": " 64 * ocr.reads_to_core.any_response / 1e9 / tma_info_system_time", + "Category": "TMA", + "CountDomain": "GB/sec", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_SoC_R2C_L3M_BW", + "LegacyName": "metric_TMA_Info_Memory_SoC_R2C_L3M_BW", + "Level": 1, + "BriefDescription": "Average L3-cache miss BW for Reads-to-Core (R2C). This covering going to DRAM or other memory off-chip memory tears. See R2C_Offcore_BW.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.READS_TO_CORE.L3_MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / 1e9 / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": " 64 * ocr.reads_to_core.l3_miss / 1e9 / tma_info_system_time", + "Category": "TMA", + "CountDomain": "GB/sec", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_SoC_R2C_DRAM_BW", + "LegacyName": "metric_TMA_Info_Memory_SoC_R2C_DRAM_BW", + "Level": 1, + "BriefDescription": "Average DRAM BW for Reads-to-Core (R2C) covering for memory attached to local- and remote-socket. See R2C_Offcore_BW.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.READS_TO_CORE.DRAM", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / 1e9 / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": " 64 * ocr.reads_to_core.dram / 1e9 / tma_info_system_time", + "Category": "TMA", + "CountDomain": "GB/sec", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", + "LocateWith": "" + } + ] +} \ No newline at end of file diff --git a/cmd/metrics/resources/metrics/x86_64/GenuineIntel/gnr_retire_latency.json b/cmd/metrics/resources/perfmon/gnr/graniterapids_retire_latency.json similarity index 100% rename from cmd/metrics/resources/metrics/x86_64/GenuineIntel/gnr_retire_latency.json rename to cmd/metrics/resources/perfmon/gnr/graniterapids_retire_latency.json diff --git a/cmd/metrics/resources/perfmon/gnr/graniterapids_uncore.json b/cmd/metrics/resources/perfmon/gnr/graniterapids_uncore.json new file mode 100644 index 00000000..1af58d0d --- /dev/null +++ b/cmd/metrics/resources/perfmon/gnr/graniterapids_uncore.json @@ -0,0 +1,6545 @@ +{ + "Header": { + "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with P-cores - V1.10", + "DatePublished": "05/16/2025", + "Version": "1.10", + "Legend": "" + }, + "Events": [ + { + "Unit": "B2CMI", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_CLOCKTICKS", + "BriefDescription": "Clockticks of the mesh to memory (B2CMI)", + "PublicDescription": "Clockticks of the mesh to memory (B2CMI)", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x24", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000001", + "EventName": "UNC_B2CMI_IMC_READS.NORMAL", + "BriefDescription": "Counts normal reads issue to CMI", + "PublicDescription": "Counts normal reads issue to CMI", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x24", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000001", + "EventName": "UNC_B2CMI_IMC_READS.ALL", + "BriefDescription": "Counts any read", + "PublicDescription": "Counts any read", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x25", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000001", + "EventName": "UNC_B2CMI_IMC_WRITES.FULL", + "BriefDescription": "Full Non-ISOCH - All Channels", + "PublicDescription": "Full Non-ISOCH - All Channels", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x25", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000001", + "EventName": "UNC_B2CMI_IMC_WRITES.PARTIAL", + "BriefDescription": "Partial Non-ISOCH - All Channels", + "PublicDescription": "Partial Non-ISOCH - All Channels", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x25", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000001", + "EventName": "UNC_B2CMI_IMC_WRITES.ALL", + "BriefDescription": "All Writes - All Channels", + "PublicDescription": "All Writes - All Channels", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x33", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_TRACKER_OCCUPANCY.CH0", + "BriefDescription": "Tracker Occupancy : Channel 0", + "PublicDescription": "Tracker Occupancy : Channel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x4B", + "UMask": "0x05", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_TAG_MISS.CLEAN", + "BriefDescription": "Counts the 2lm second way read miss for a WrNI", + "PublicDescription": "Counts the 2lm second way read miss for a WrNI", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x4B", + "UMask": "0x0A", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_TAG_MISS.DIRTY", + "BriefDescription": "Counts the 2lm second way read miss for a WrNI", + "PublicDescription": "Counts the 2lm second way read miss for a WrNI", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x56", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_PREFCAM_INSERTS.UPI_ALLCH", + "BriefDescription": "Prefetch CAM Inserts : UPI - All Channels", + "PublicDescription": "Prefetch CAM Inserts : UPI - All Channels", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x56", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_PREFCAM_INSERTS.XPT_ALLCH", + "BriefDescription": "Prefetch CAM Inserts : XPT -All Channels", + "PublicDescription": "Prefetch CAM Inserts : XPT - All Channels", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x1F", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_TAG_HIT.RD_CLEAN", + "BriefDescription": "Counts the 2lm reads which were a hit clean", + "PublicDescription": "Counts the 2lm reads which were a hit clean", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x1F", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_TAG_HIT.RD_DIRTY", + "BriefDescription": "Counts the 2lm reads which were a hit dirty", + "PublicDescription": "Counts the 2lm reads which were a hit dirty", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x21", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000003", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.ANY", + "BriefDescription": "Counts cisgress directory updates", + "PublicDescription": "Counts cisgress directory updates", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x21", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000003", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.I2S", + "BriefDescription": "Any I2S Transition", + "PublicDescription": "Any I2S Transition", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x21", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000003", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.I2A", + "BriefDescription": "Any I2A Transition", + "PublicDescription": "Any I2A Transition", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x21", + "UMask": "0x20", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000003", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.A2I", + "BriefDescription": "Any A2I Transition", + "PublicDescription": "Any A2I Transition", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x21", + "UMask": "0x40", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000003", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.A2S", + "BriefDescription": "Any A2S Transition", + "PublicDescription": "Any A2S Transition", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x20", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECTORY_LOOKUP.ANY", + "BriefDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with any directory to non persistent memory", + "PublicDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with any directory to non persistent memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x20", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECTORY_LOOKUP.STATE_I", + "BriefDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with directory I to non persistent memory", + "PublicDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with directory I to non persistent memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x20", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECTORY_LOOKUP.STATE_S", + "BriefDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with directory S to non persistent memory", + "PublicDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with directory S to non persistent memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x20", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECTORY_LOOKUP.STATE_A", + "BriefDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with directory A to non persistent memory", + "PublicDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with directory A to non persistent memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x1A", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECT2UPI_NOT_TAKEN_DIRSTATE.EGRESS", + "BriefDescription": "Cycles when Direct2UPI was Disabled : Egress Ignored D2U : Counts the number of time D2K was not honoured by egress due to directory state constraints", + "PublicDescription": "Cycles when Direct2UPI was Disabled : Egress Ignored D2U", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x1B", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECT2UPI_NOT_TAKEN_CREDITS.EGRESS", + "BriefDescription": "Direct to UPI Transactions - Ignored due to lack of credits : All : Counts the number of d2k wasn't done due to credit constraints", + "PublicDescription": "Direct to UPI Transactions - Ignored due to lack of credits : All", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x18", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECT2CORE_TXN_OVERRIDE", + "BriefDescription": "Counts the number of times D2C wasn't honoured even though the incoming request had d2c set for non cisgress txn", + "PublicDescription": "Counts the number of times D2C wasn't honoured even though the incoming request had d2c set for non cisgress txn", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_CLOCKTICKS", + "BriefDescription": "Number of CHA clock cycles while the event is enabled", + "PublicDescription": "Clockticks of the uncore caching and home agent (CHA)", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C80FFD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", + "BriefDescription": "Code read from local IA that hit the cache", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C817FD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD", + "BriefDescription": "Data read from local IA that hit the cache", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCC7FD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO", + "BriefDescription": "Last level cache prefetch read for ownership from local IA that hit the cache", + "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C807FD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", + "BriefDescription": "Read for ownership from local IA that hit the cache", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C001FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", + "BriefDescription": "All locally initiated requests from IA Cores which miss the cache", + "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C80FFE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "BriefDescription": "Code read from local IA that miss the cache", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C817FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "BriefDescription": "Data read from local IA that miss the cache", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCC7FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO", + "BriefDescription": "Last level cache prefetch read for ownership from local IA that miss the cache", + "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C807FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", + "BriefDescription": "Read for ownership from local IA that miss the cache", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC43FE", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "BriefDescription": "All TOR ItoM inserts from local IO devices which miss the cache", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C803FE", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "BriefDescription": "All TOR RFO inserts from local IO devices which miss the cache", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C88FFD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF", + "BriefDescription": "Code read prefetch from local IA that hit the cache", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C897FD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF", + "BriefDescription": "Data read prefetch from local IA that hit the cache", + "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C887FD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF", + "BriefDescription": "Read for ownership prefetch from local IA that hit the cache", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C88FFE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", + "BriefDescription": "Code read prefetch from local IA that miss the cache", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C897FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF", + "BriefDescription": "Data read prefetch from local IA that miss the cache", + "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C887FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", + "BriefDescription": "Read for ownership prefetch from local IA that miss the cache", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC43FD", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", + "BriefDescription": "ItoMs from local IO devices which hit the cache", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C803FD", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO", + "BriefDescription": "RFOs from local IO devices which hit the cache", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C803FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO", + "BriefDescription": "RFOs from local IO devices", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC43FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "BriefDescription": "All TOR ItoM inserts from local IO devices", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C887FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF", + "BriefDescription": "Read for ownership prefetch from local IA", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C807FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO", + "BriefDescription": "Read for ownership from local IA", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCC7FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO", + "BriefDescription": "Last level cache prefetch read for ownership from local IA", + "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C817FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD", + "BriefDescription": "Data read from local IA", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C897FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF", + "BriefDescription": "Data read prefetch from local IA", + "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C88FFF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF", + "BriefDescription": "Code read prefetch from local IA that miss the cache", + "PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C80FFF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD", + "BriefDescription": "Code read from local IA", + "PublicDescription": "TOR Inserts : CRDs issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C816FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", + "BriefDescription": "Data read from local IA that miss the cache and targets local memory", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8177E", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", + "BriefDescription": "Data read from local IA that miss the cache and targets remote memory", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C896FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL", + "BriefDescription": "Data read prefetch from local IA that miss the cache and targets local memory", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target local memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8977E", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE", + "BriefDescription": "Data read prefetch from local IA that miss the cache and targets remote memory", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target remote memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C806FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL", + "BriefDescription": "Read for ownership from local IA that miss the LLC targeting local memory", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8077E", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE", + "BriefDescription": "Read for ownership from local IA that miss the LLC targeting remote memory", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C886FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL", + "BriefDescription": "Read for ownership prefetch from local IA that miss the LLC targeting local memory", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8877E", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE", + "BriefDescription": "Read for ownership prefetch from local IA that miss the LLC targeting remote memory", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8C7FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH", + "BriefDescription": "CLFlush events that are initiated from the Core", + "PublicDescription": "TOR Inserts : CLFlushes issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC47FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOM", + "BriefDescription": "ItoM events that are initiated from the Core", + "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC57FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM", + "BriefDescription": "SpecItoM events that are initiated from the Core", + "PublicDescription": "TOR Inserts : SpecItoMs issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C81786", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", + "BriefDescription": "DRds issued by iA Cores targeting DDR Mem that Missed the LLC", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD43FD", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", + "BriefDescription": "ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD43FE", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "BriefDescription": "ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C837FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE", + "BriefDescription": "DRd PTEs issued by iA Cores due to a page walk that missed the LLC", + "PublicDescription": "TOR Inserts : DRdPte issued by iA Cores due to a page walk that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C837FD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE", + "BriefDescription": "DRd PTEs issued by iA Cores due to page walks that hit the LLC", + "PublicDescription": "TOR Inserts : DRdPte issued by iA Cores due to a page walk that hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C837FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE", + "BriefDescription": "DRd PTEs issued by iA Cores due to a page walk", + "PublicDescription": "TOR Inserts : DRdPte issued by iA Cores due to a page walk", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC3FFF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE", + "BriefDescription": "WbEFtoEs issued by iA Cores. (Non Modified Write Backs)", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8F3FD", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR", + "BriefDescription": "PCIRDCURs issued by IO devices which hit the LLC", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8F3FE", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "BriefDescription": "PCIRDCURs issued by IO devices which miss the LLC", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8F3FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "BriefDescription": "PCIRDCURs issued by IO devices", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCCFFD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE", + "BriefDescription": "Last level cache prefetch code read from local IA that hit the cache", + "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCD7FD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA", + "BriefDescription": "Last level cache prefetch data read from local IA that hit the cache", + "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCD7FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA", + "BriefDescription": "Last level cache prefetch data read from local IA.", + "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCCFFE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE", + "BriefDescription": "Last level cache prefetch code read from local IA that miss the cache", + "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCD7FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", + "BriefDescription": "Last level cache prefetch data read from local IA that miss the cache", + "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCCFFF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE", + "BriefDescription": "Last level cache prefetch code read from local IA.", + "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD43FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "BriefDescription": "ItoMCacheNears, indicating a partial write request, from IO Devices", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C81686", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR", + "BriefDescription": "DRds from local IA cores to locally homed DDR addresses that miss the cache", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C81706", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR", + "BriefDescription": "DRds from local IA cores to remotely homed DDR addresses that miss the cache", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C89786", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_DDR", + "BriefDescription": "DRd Prefetches from local IA cores to DDR addresses that miss the cache", + "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C89686", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_DDR", + "BriefDescription": "DRd Prefetches from local IA cores to locally homed DDR addresses that miss the cache", + "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C89706", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_DDR", + "BriefDescription": "DRd Prefetches from local IA cores to remotely homed DDR addresses that miss the cache", + "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C80EFE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL", + "BriefDescription": "CRDs from local IA cores to locally homed memory", + "PublicDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C80F7E", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_REMOTE", + "BriefDescription": "CRDs from local IA cores to remotely homed memory", + "PublicDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C88EFE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL", + "BriefDescription": "CRD Prefetches from local IA cores to locally homed memory", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C88F7E", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_REMOTE", + "BriefDescription": "CRD Prefetches from local IA cores to remotely homed memory", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD47FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR", + "BriefDescription": "ItoMCacheNear requests from local IA cores", + "PublicDescription": "TOR Inserts : ItoMCacheNears issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC27FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI", + "BriefDescription": "WbMtoI requests from local IA cores", + "PublicDescription": "TOR Inserts : WbMtoIs issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC47FD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_ITOM", + "BriefDescription": "ItoM requests from local IA cores that hit the cache", + "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores that Hit LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC47FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_ITOM", + "BriefDescription": "ItoM requests from local IA cores that miss the cache", + "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores that Missed LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C877DE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF", + "BriefDescription": "UCRDF requests from local IA cores that miss the cache", + "PublicDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C87FDE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL", + "BriefDescription": "WIL requests from local IA cores that miss the cache", + "PublicDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C867FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF", + "BriefDescription": "WCILF requests from local IA core", + "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C867FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF", + "BriefDescription": "WCILF requests from local IA core that miss the cache", + "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86786", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR", + "BriefDescription": "WCILF requests from local IA cores to DDR homed addresses which miss the cache", + "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86686", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR", + "BriefDescription": "WCILF requests from local IA cores to locally homed DDR addresses that miss the cache", + "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86706", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR", + "BriefDescription": "WCILF requests from local IA cores to remotely homed DDR addresses that miss the cache", + "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86FFF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL", + "BriefDescription": "WCIL requests from a local IA core", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86FFE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL", + "BriefDescription": "WCIL requests from a local IA core that miss the cache", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86F86", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR", + "BriefDescription": "WCIL requests from local IA cores to DDR homed addresses which miss the cache", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86E86", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR", + "BriefDescription": "WCIL requests from local IA cores to locally homed DDR addresses that miss the cache", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86F06", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR", + "BriefDescription": "WCIL requests from local IA cores to remotely homed DDR addresses that miss the cache", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC23FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI", + "BriefDescription": "WBMtoI requests from IO devices", + "PublicDescription": "TOR Inserts : WbMtoIs issued by IO Devices", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8C3FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH", + "BriefDescription": "CLFlush requests from IO devices", + "PublicDescription": "TOR Inserts : CLFlushes issued by IO Devices", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC2FFF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE", + "BriefDescription": "WbMtoEs issued by iA Cores . (Modified Write Backs)", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC37FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI", + "BriefDescription": "WbEFtoIs issued by iA Cores . (Non Modified Write Backs)", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC67FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI", + "BriefDescription": "WbStoIs issued by iA Cores . (Non Modified Write Backs)", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C81782", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_ACC", + "BriefDescription": "DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card.", + "PublicDescription": "DRds issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C80782", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_ACC", + "BriefDescription": "RFOs issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "RFOs issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C88782", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO_CXL_ACC", + "BriefDescription": "L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10CCC782", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_CXL_ACC", + "BriefDescription": "LLC RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "LLC RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C89782", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_CXL_ACC", + "BriefDescription": "L2 data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "L2 data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10CCD782", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA_CXL_ACC", + "BriefDescription": "LLC data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "LLC data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C00182", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CXL_ACC", + "BriefDescription": "All requests issued from IA cores to CXL accelerator memory regions that miss the LLC.", + "PublicDescription": "All requests issued from IA cores to CXL accelerator memory regions that miss the LLC.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C00181", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CXL_ACC", + "BriefDescription": "All requests issued from IA cores to CXL accelerator memory regions that hit the LLC.", + "PublicDescription": "All requests issued from IA cores to CXL accelerator memory regions that hit the LLC.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C80FFD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", + "BriefDescription": "TOR Occupancy for Code read from local IA that hit the cache", + "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C817FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", + "BriefDescription": "TOR Occupancy for Data read from local IA that hit the cache", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCC7FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO", + "BriefDescription": "TOR Occupancy for Last level cache prefetch read for ownership from local IA that hit the cache", + "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C807FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "BriefDescription": "TOR Occupancy for Read for ownership from local IA that hit the cache", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": 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Occupancy : PCIRdCurs issued by IO Devices that hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8F3FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR", + "BriefDescription": "TOR Occupancy for PCIRDCURs issued by IO devices which miss the LLC", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8F3FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR", + "BriefDescription": "TOR Occupancy for PCIRDCURs issued by IO devices", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCCFFD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE", + "BriefDescription": "TOR Occupancy for Last level cache prefetch code read from local IA that hit the cache", + "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCD7FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA", + "BriefDescription": "TOR Occupancy for Last level cache prefetch data read from local IA that hit the cache", + "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCD7FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA", + "BriefDescription": "TOR Occupancy for Last level cache prefetch data read from local IA.", + "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCCFFE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE", + "BriefDescription": "TOR Occupancy for Last level cache prefetch code read from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCD7FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA", + "BriefDescription": "TOR Occupancy for Last level cache prefetch data read from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCCFFF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE", + "BriefDescription": "TOR Occupancy for Last level cache prefetch code read from local IA.", + "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C81686", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_DDR", + "BriefDescription": "TOR Occupancy for DRds from local IA cores to locally homed DDR addresses that miss the cache", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C81706", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_DDR", + "BriefDescription": "TOR Occupancy for DRds from local IA cores to remotely homed DDR addresses that miss the cache", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C89786", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_DDR", + "BriefDescription": "TOR Occupancy for DRd Prefetches from local IA cores to DDR addresses that miss the cache", + "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C89686", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_DDR", + "BriefDescription": "TOR Occupancy for DRd Prefetches from local IA cores to locally homed DDR addresses that miss the cache", + "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C89706", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_DDR", + "BriefDescription": "TOR Occupancy for DRd Prefetches from local IA cores to remotely homed DDR addresses that miss the cache", + "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C80EFE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL", + "BriefDescription": "TOR Occupancy for CRDs from local IA cores to locally homed memory", + "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C80F7E", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_REMOTE", + "BriefDescription": "TOR Occupancy for CRDs from local IA cores to remotely homed memory", + "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C88EFE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL", + "BriefDescription": "TOR Occupancy for CRD Prefetches from local IA cores to locally homed memory", + "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C88F7E", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_REMOTE", + "BriefDescription": "TOR Occupancy for CRD Prefetches from local IA cores to remotely homed memory", + "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8C7FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH", + "BriefDescription": "TOR Occupancy for CLFlush events that are initiated from the Core", + "PublicDescription": "TOR Occupancy : CLFlushes issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD47FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR", + "BriefDescription": "TOR Occupancy for ItoMCacheNear requests from local IA cores", + "PublicDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC57FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM", + "BriefDescription": "TOR Occupancy for SpecItoM events that are initiated from the Core", + "PublicDescription": "TOR Occupancy : SpecItoMs issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC27FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI", + "BriefDescription": "TOR Occupancy for WbMtoI requests from local IA cores", + "PublicDescription": "TOR Occupancy : WbMtoIs issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC47FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOM", + "BriefDescription": "TOR Occupancy for ItoM events that are initiated from the Core", + "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC47FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM", + "BriefDescription": "TOR Occupancy for ItoM requests from local IA cores that hit the cache", + "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC47FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM", + "BriefDescription": "TOR Occupancy for ItoM requests from local IA cores that miss the cache", + "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C877DE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF", + "BriefDescription": "TOR Occupancy for UCRDF requests from local IA cores that miss the cache", + "PublicDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C87FDE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL", + "BriefDescription": "TOR Occupancy for WIL requests from local IA cores that miss the cache", + "PublicDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C867FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF", + "BriefDescription": "TOR Occupancy for WCILF requests from local IA core", + "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C867FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF", + "BriefDescription": "TOR Occupancy for WCILF requests from local IA core that miss the cache", + "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86786", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR", + "BriefDescription": "TOR Occupancy for WCILF requests from local IA cores to DDR homed addresses which miss the cache", + "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86686", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR", + "BriefDescription": "TOR Occupancy for WCILF requests from local IA cores to locally homed DDR addresses that miss the cache", + "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86706", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_DDR", + "BriefDescription": "TOR Occupancy for WCILF requests from local IA cores to remotely homed DDR addresses that miss the cache", + "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86FFF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL", + "BriefDescription": "TOR Occupancy for WCIL requests from a local IA core", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86FFE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL", + "BriefDescription": "TOR Occupancy for WCIL requests from a local IA core that miss the cache", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86F86", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR", + "BriefDescription": "TOR Occupancy for WCIL requests from local IA cores to DDR homed addresses which miss the cache", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86E86", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR", + "BriefDescription": "TOR Occupancy for WCIL requests from local IA cores to locally homed DDR addresses that miss the cache", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86F06", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_DDR", + "BriefDescription": "TOR Occupancy for WCIL requests from local IA cores to remotely homed DDR addresses that miss the cache", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC23FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI", + "BriefDescription": "TOR Occupancy for WBMtoI requests from IO devices", + "PublicDescription": "TOR Occupancy : WbMtoIs issued by IO Devices", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8C3FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH", + "BriefDescription": "TOR Occupancy for CLFlush requests from IO devices", + "PublicDescription": "TOR Occupancy : CLFlushes issued by IO Devices", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD43FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR", + "BriefDescription": "TOR Occupancy for ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD43FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR", + "BriefDescription": "TOR Occupancy for ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C837FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRDPTE", + "BriefDescription": "TOR Occupancy for DRd PTEs issued by iA Cores due to a page walk", + "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C837FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRDPTE", + "BriefDescription": "TOR Occupancy for DRd PTEs issued by iA Cores due to page walks that hit the LLC", + "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C837FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDPTE", + "BriefDescription": "TOR Occupancy for DRd PTEs issued by iA Cores due to a page walk that missed the LLC", + "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD43FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR", + "BriefDescription": "TOR Occupancy for ItoMCacheNears, indicating a partial write request, from IO Devices", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C80782", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_ACC", + "BriefDescription": "TOR Occupancy for RFOs issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "TOR Occupancy for RFOs issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C81782", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_ACC", + "BriefDescription": "TOR Occupancy for DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card.", + "PublicDescription": "TOR Occupancy for DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C89782", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_CXL_ACC", + "BriefDescription": "TOR Occupancy for L2 data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "TOR Occupancy for L2 data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10CCD782", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA_CXL_ACC", + "BriefDescription": "TOR Occupancy for LLC data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "TOR Occupancy for LLC data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C88782", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO_CXL_ACC", + "BriefDescription": "TOR Occupancy for L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "TOR Occupancy for L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10CCC782", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_CXL_ACC", + "BriefDescription": "TOR Occupancy for LLC RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "TOR Occupancy for LLC RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C00182", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CXL_ACC", + "BriefDescription": "TOR Occupancy for All requests issued from IA cores to CXL accelerator memory regions that miss the LLC.", + "PublicDescription": "TOR Occupancy for All requests issued from IA cores to CXL accelerator memory regions that miss the LLC.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C00181", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CXL_ACC", + "BriefDescription": "TOR Occupancy for All requests issued from IA cores to CXL accelerator memory regions that hit the LLC.", + "PublicDescription": "TOR Occupancy for All requests issued from IA cores to CXL accelerator memory regions that hit the LLC.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x39", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_MISC.RFO_HIT_S", + "BriefDescription": "Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state.", + "PublicDescription": "Cbo Misc : RFO HitS", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x3d", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_SF_EVICTION.M_STATE", + "BriefDescription": "Counts snoop filter capacity evictions for entries tracking modified lines in the core's cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a core's cache replaces a tracked cacheline with a new cacheline.", + "PublicDescription": "Snoop Filter Capacity Evictions : M state", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", + "BriefDescription": "Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", + "PublicDescription": "Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.READS_REMOTE", + "BriefDescription": "Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", + "PublicDescription": "Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL", + "BriefDescription": "Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", + "PublicDescription": "Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", + "BriefDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).", + "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", + "BriefDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x20", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE", + "BriefDescription": "Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "PublicDescription": "Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x30", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.INVITOE", + "BriefDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "PublicDescription": "HA Read and Write Requests : InvalItoE", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x03", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.READS", + "BriefDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) .", + "PublicDescription": "HA Read and Write Requests : Reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x0C", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.WRITES", + "BriefDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", + "PublicDescription": "HA Read and Write Requests : Writes", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x55", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_OSB.RFO_HITS_SNP_BCAST", + "BriefDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcast : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.", + "PublicDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcast", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x01", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CLOCKTICKS", + "BriefDescription": "Number of DRAM DCLK clock cycles while the event is enabled. DCLK is 1/4 of DRAM data rate.", + "PublicDescription": "DRAM Clockticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x02", + "UMask": "0xF7", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_ACT_COUNT.ALL", + "BriefDescription": "DRAM Activate Count : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.", + "PublicDescription": "DRAM Activate Count", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x03", + "UMask": "0xF8", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_PRE_COUNT.PGT", + "BriefDescription": "DRAM Precharge commands. : Precharge due to (?) : Counts the number of DRAM Precharge commands sent on this channel.", + "PublicDescription": "DRAM Precharge commands.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x05", + "UMask": "0xC1", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH0.RD_REG", + "BriefDescription": "CAS count for SubChannel 0 regular reads", + "PublicDescription": "CAS count for SubChannel 0 regular reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x05", + "UMask": "0xC4", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH0.RD_UNDERFILL", + "BriefDescription": "CAS count for SubChannel 0 underfill reads", + "PublicDescription": "CAS count for SubChannel 0 underfill reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x05", + "UMask": "0xCF", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH0.RD", + "BriefDescription": "CAS count for SubChannel 0, all reads", + "PublicDescription": "CAS count for SubChannel 0, all reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x05", + "UMask": "0xF0", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH0.WR", + "BriefDescription": "CAS count for SubChannel 0, all writes", + "PublicDescription": "CAS count for SubChannel 0, all writes", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x05", + "UMask": "0xFF", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH0.ALL", + "BriefDescription": "CAS count for SubChannel 0, all CAS operations", + "PublicDescription": "CAS count for SubChannel 0, all CAS operations", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x06", + "UMask": "0xC1", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH1.RD_REG", + "BriefDescription": "CAS count for SubChannel 1 regular reads", + "PublicDescription": "CAS count for SubChannel 1 regular reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x06", + "UMask": "0xC4", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH1.RD_UNDERFILL", + "BriefDescription": "CAS count for SubChannel 1 underfill reads", + "PublicDescription": "CAS count for SubChannel 1 underfill reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x06", + "UMask": "0xCF", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH1.RD", + "BriefDescription": "CAS count for SubChannel 1, all reads", + "PublicDescription": "CAS count for SubChannel 1, all reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x06", + "UMask": "0xF0", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH1.WR", + "BriefDescription": "CAS count for SubChannel 1, all writes", + "PublicDescription": "CAS count for SubChannel 1, all writes", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x06", + "UMask": "0xFF", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH1.ALL", + "BriefDescription": "CAS count for SubChannel 1, all CAS operations", + "PublicDescription": "CAS count for SubChannel 1, all CAS operations", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x17", + "UMask": "0x40", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RDB_INSERTS.SCH0", + "BriefDescription": "Read buffer inserts on subchannel 0", + "PublicDescription": "Read buffer inserts on subchannel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x17", + "UMask": "0x80", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RDB_INSERTS.SCH1", + "BriefDescription": "Read buffer inserts on subchannel 1", + "PublicDescription": "Read buffer inserts on subchannel 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x1a", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RDB_OCCUPANCY_SCH0", + "BriefDescription": "Read buffer occupancy on subchannel 0", + "PublicDescription": "Read buffer occupancy on subchannel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x1b", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RDB_OCCUPANCY_SCH1", + "BriefDescription": "Read buffer occupancy on subchannel 1", + "PublicDescription": "Read buffer occupancy on subchannel 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x80", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_OCCUPANCY_SCH0_PCH0", + "BriefDescription": "Read pending queue occupancy for subchannel 0, pseudochannel 0", + "PublicDescription": "Read pending queue occupancy for subchannel 0, pseudochannel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x81", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_OCCUPANCY_SCH0_PCH1", + "BriefDescription": "Read pending queue occupancy for subchannel 0, pseudochannel 1", + "PublicDescription": "Read pending queue occupancy for subchannel 0, pseudochannel 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x82", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_OCCUPANCY_SCH1_PCH0", + "BriefDescription": "Read pending queue occupancy for subchannel 1, pseudochannel 0", + "PublicDescription": "Read pending queue occupancy for subchannel 1, pseudochannel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x83", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_OCCUPANCY_SCH1_PCH1", + "BriefDescription": "Read pending queue occupancy for subchannel 1, pseudochannel 1", + "PublicDescription": "Read pending queue occupancy for subchannel 1, pseudochannel 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x84", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_OCCUPANCY_SCH0_PCH0", + "BriefDescription": "Write pending queue occupancy for subchannel 0, pseudochannel 0", + "PublicDescription": "Write pending queue occupancy for subchannel 0, pseudochannel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x85", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_OCCUPANCY_SCH0_PCH1", + "BriefDescription": "Write pending queue occupancy for subchannel 0, pseudochannel 1", + "PublicDescription": "Write pending queue occupancy for subchannel 0, pseudochannel 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x86", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_OCCUPANCY_SCH1_PCH0", + "BriefDescription": "Write pending queue occupancy for subchannel 1, pseudochannel 0", + "PublicDescription": "Write pending queue occupancy for subchannel 1, pseudochannel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x87", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_OCCUPANCY_SCH1_PCH1", + "BriefDescription": "Write pending queue occupancy for subchannel 1, pseudochannel 1", + "PublicDescription": "Write pending queue occupancy for subchannel 1, pseudochannel 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CXLCM", + "EventCode": "0x41", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_DATA", + "BriefDescription": "Number of Allocation to Mem Data Packing buffer", + "PublicDescription": "Number of Allocation to Mem Data Packing buffer", + "Counter": "4,5,6,7", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CXLDP", + "EventCode": "0x02", + "UMask": "0x20", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.M2S_DATA", + "BriefDescription": "Number of Allocation to M2S Data AGF", + "PublicDescription": "Number of Allocation to M2S Data AGF", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2HOT", + "EventCode": "0x01", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2HOT_CLOCKTICKS", + "BriefDescription": "UNC_B2HOT_CLOCKTICKS", + "PublicDescription": "Clockticks for the B2HOT unit", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x000", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_CLOCKTICKS", + "BriefDescription": "IIO Clockticks", + "PublicDescription": "IIO Clockticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x001", + "FCMask": "0x07", + "UMaskExt": "0x00070010", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x001", + "FCMask": "0x07", + "UMaskExt": "0x00070010", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x0FF", + "FCMask": "0x07", + "UMaskExt": "0x00070FF0", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS", + "BriefDescription": "Counts once for every 4 bytes read from this card to memory. This event does include reads to IO.", + "PublicDescription": "Counts once for every 4 bytes read from this card to memory. This event does include reads to IO.", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x0FF", + "FCMask": "0x07", + "UMaskExt": "0x00070FF0", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS", + "BriefDescription": "Counts once for every 4 bytes written from this card to memory. This event does include writes to IO.", + "PublicDescription": "Counts once for every 4 bytes written from this card to memory. This event does include writes to IO.", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x001", + "FCMask": "0x07", + "UMaskExt": "0x00070010", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x001", + "FCMask": "0x07", + "UMaskExt": "0x00070010", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x01", + "PortMask": "0x001", + "FCMask": "0x07", + "UMaskExt": "0x00070010", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x01", + "PortMask": "0x001", + "FCMask": "0x07", + "UMaskExt": "0x00070010", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x04", + "PortMask": "0x001", + "FCMask": "0x07", + "UMaskExt": "0x00070010", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_CLOCKTICKS", + "BriefDescription": "IRP Clockticks", + "PublicDescription": "IRP Clockticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x11", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "BriefDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.", + "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x18", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_FAF_INSERTS", + "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue", + "PublicDescription": "Inbound read requests received by the IRP and inserted into the FAF queue", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_CLOCKTICKS", + "BriefDescription": "Number of UPI LL clock cycles while the event is enabled", + "PublicDescription": "Number of kfclks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x02", + "UMask": "0x0F", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", + "BriefDescription": "Valid Flits Sent : All Data : Counts number of data flits across this UPI link.", + "PublicDescription": "Valid Flits Sent : All Data", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x02", + "UMask": "0x27", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", + "BriefDescription": "All Null Flits", + "PublicDescription": "Valid Flits Sent : Idle", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x02", + "UMask": "0x47", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_TxL_FLITS.IDLE", + "BriefDescription": "Valid Flits Sent : Idle : Shows legal flit time (hides impact of L0p and L0c).", + "PublicDescription": "Valid Flits Sent", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x02", + "UMask": "0x97", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", + "BriefDescription": "Valid Flits Sent : All Non Data : Shows legal flit time (hides impact of L0p and L0c).", + "PublicDescription": "Valid Flits Sent : Null FLITs transmitted to any slot", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x03", + "UMask": "0x0F", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", + "BriefDescription": "Valid Flits Received : All Data : Shows legal flit time (hides impact of L0p and L0c).", + "PublicDescription": "Valid Flits Received : All Data", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x03", + "UMask": "0x97", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", + "BriefDescription": "Valid Flits Received : All Non Data : Shows legal flit time (hides impact of L0p and L0c).", + "PublicDescription": "Valid Flits Received : All Non Data", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x05", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", + "BriefDescription": "Matches on Receive path of a UPI Port : Request", + "PublicDescription": "Matches on Receive path of a UPI Port : Request", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x05", + "UMask": "0x0D", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB", + "BriefDescription": "Matches on Receive path of a UPI Port : Writeback", + "PublicDescription": "Matches on Receive path of a UPI Port : Writeback", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2UPI", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2UPI_CLOCKTICKS", + "BriefDescription": "Number of uclks in domain", + "PublicDescription": "Number of uclks in domain", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CXL", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x000", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CXL_CLOCKTICKS", + "BriefDescription": "B2CXL Clockticks", + "PublicDescription": "B2CXL Clockticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UBOX", + "EventCode": "0x42", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", + "BriefDescription": "Message Received : MSI", + "PublicDescription": "Message Received : MSI : Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only)", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "PCU", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_P_CLOCKTICKS", + "BriefDescription": "PCU Clockticks", + "PublicDescription": "PCU Clockticks: The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "PCU", + "EventCode": "0x35", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C0", + "BriefDescription": "Number of cores in C0", + "PublicDescription": "Number of cores in C0 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "PCU", + "EventCode": "0x37", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C6", + "BriefDescription": "Number of cores in C6", + "PublicDescription": "Number of cores in C6 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x03", + "UMask": "0xFF", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_PRE_COUNT.ALL", + "BriefDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", + "PublicDescription": "DRAM Precharge commands.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x32", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000001", + "EventName": "UNC_B2CMI_TRACKER_INSERTS.CH0", + "BriefDescription": "Tracker Inserts : Channel 0", + "PublicDescription": "Tracker Inserts : Channel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x19", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECT2UPI_TAKEN", + "BriefDescription": "Counts the number of times egress did D2K (Direct to KTI)", + "PublicDescription": "Counts the number of times egress did D2K (Direct to KTI)", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x1A", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECT2UPI_NOT_TAKEN_DIRSTATE", + "BriefDescription": "Counts the number of time D2K was not honoured by egress due to directory state constraints", + "PublicDescription": "Counts the number of time D2K was not honoured by egress due to directory state constraints", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x1B", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECT2UPI_NOT_TAKEN_CREDITS", + "BriefDescription": "Counts the number of d2k wasn't done due to credit constraints", + "PublicDescription": "Counts the number of d2k wasn't done due to credit constraints", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x1C", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECT2UPI_TXN_OVERRIDE", + "BriefDescription": "Counts the number of times D2K wasn't honoured even though the incoming request had d2k set for non cisgress txn", + "PublicDescription": "Counts the number of times D2K wasn't honoured even though the incoming request had d2k set for non cisgress txn", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x16", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECT2CORE_TAKEN", + "BriefDescription": "Counts the number of times B2CMI egress did D2C (direct to core)", + "PublicDescription": "Counts the number of times B2CMI egress did D2C (direct to core)", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x17", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECT2CORE_NOT_TAKEN_DIRSTATE", + "BriefDescription": "Counts the number of time D2C was not honoured by egress due to directory state constraints", + "PublicDescription": "Counts the number of time D2C was not honoured by egress due to directory state constraints", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x02", + "FCMask": "0x07", + "UMaskExt": "0x00070020", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x04", + "FCMask": "0x07", + "UMaskExt": "0x00070040", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x08", + "FCMask": "0x07", + "UMaskExt": "0x00070080", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x10", + "FCMask": "0x07", + "UMaskExt": "0x00070100", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x20", + "FCMask": "0x07", + "UMaskExt": "0x00070200", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x40", + "FCMask": "0x07", + "UMaskExt": "0x00070400", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x80", + "FCMask": "0x07", + "UMaskExt": "0x00070800", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x02", + "FCMask": "0x07", + "UMaskExt": "0x00070020", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x04", + "FCMask": "0x07", + "UMaskExt": "0x00070040", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x08", + "FCMask": "0x07", + "UMaskExt": "0x00070080", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x10", + "FCMask": "0x07", + "UMaskExt": "0x00070100", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x20", + "FCMask": "0x07", + "UMaskExt": "0x00070200", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x40", + "FCMask": "0x07", + "UMaskExt": "0x00070400", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x80", + "FCMask": "0x07", + "UMaskExt": "0x00070800", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x1F", + "UMask": "0x0F", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_TAG_HIT.ALL", + "BriefDescription": "Counts the 2lm reads and WRNI which were a hit", + "PublicDescription": "Counts the 2lm reads and WRNI which were a hit", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x59", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_IRQ", + "BriefDescription": "Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in IRQ (immediate cause for triggering).", + "PublicDescription": "Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in IRQ (immediate cause for triggering).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x59", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_TOR", + "BriefDescription": "Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in TOR (immediate cause for triggering).", + "PublicDescription": "Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in TOR (immediate cause for triggering).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x59", + "UMask": "0x03", + "PortMask": "0x000", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_ANY", + "BriefDescription": "Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in TOR or IRQ (immediate cause for triggering).", + "PublicDescription": "Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in TOR or IRQ (immediate cause for triggering).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHACMS", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x000", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHACMS_CLOCKTICKS", + "BriefDescription": "Clockticks for CMS units attached to CHA", + "PublicDescription": "UNC_CHACMS_CLOCKTICKS", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x002", + "FCMask": "0x07", + "UMaskExt": "0x00070020", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number 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"Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x01", + "PortMask": "0x080", + "FCMask": "0x07", + "UMaskExt": "0x00070800", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x04", + "PortMask": "0x080", + "FCMask": "0x07", + "UMaskExt": "0x00070800", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x01", + "PortMask": "0x0FF", + "FCMask": "0x07", + "UMaskExt": "0x00070FF0", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.ALL_PARTS", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x02", + "PortMask": "0x0FF", + "FCMask": "0x07", + "UMaskExt": "0x00070FF0", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.ALL_PARTS", + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x04", + "PortMask": "0x0FF", + "FCMask": "0x07", + "UMaskExt": "0x00070FF0", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.ALL_PARTS", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x08", + "PortMask": "0x0FF", + "FCMask": "0x07", + "UMaskExt": "0x00070FF0", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.ALL_PARTS", + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x10", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_INSERTS.SCH0_PCH0", + "BriefDescription": "Read Pending Queue inserts for subchannel 0, pseudochannel 0", + "PublicDescription": "Read Pending Queue inserts for subchannel 0, pseudochannel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x10", + "UMask": "0x20", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_INSERTS.SCH0_PCH1", + "BriefDescription": "Read Pending Queue inserts for subchannel 0, pseudochannel 1", + "PublicDescription": "Read Pending Queue inserts for subchannel 0, pseudochannel 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x10", + "UMask": "0x40", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_INSERTS.SCH1_PCH0", + "BriefDescription": "Read Pending Queue inserts for subchannel 1, pseudochannel 0", + "PublicDescription": "Read Pending Queue inserts for subchannel 1, pseudochannel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x10", + "UMask": "0x80", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_INSERTS.SCH1_PCH1", + "BriefDescription": "Read Pending Queue inserts for subchannel 1, pseudochannel 1", + "PublicDescription": "Read Pending Queue inserts for subchannel 1, pseudochannel 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x22", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_INSERTS.SCH0_PCH0", + "BriefDescription": "Write Pending Queue inserts for subchannel 0, pseudochannel 0", + "PublicDescription": "Write Pending Queue inserts for subchannel 0, pseudochannel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x22", + "UMask": "0x20", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_INSERTS.SCH0_PCH1", + "BriefDescription": "Write Pending Queue inserts for subchannel 0, pseudochannel 1", + "PublicDescription": "Write Pending Queue inserts for subchannel 0, pseudochannel 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x22", + "UMask": "0x40", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_INSERTS.SCH1_PCH0", + "BriefDescription": "Write Pending Queue inserts for subchannel 1, pseudochannel 0", + "PublicDescription": "Write Pending Queue inserts for subchannel 1, pseudochannel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x22", + "UMask": "0x80", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_INSERTS.SCH1_PCH1", + "BriefDescription": "Write Pending Queue inserts for subchannel 1, pseudochannel 1", + "PublicDescription": "Write Pending Queue inserts for subchannel 1, pseudochannel 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C001FF", + "EventName": "UNC_CHA_TOR_INSERTS.LLC_OR_SF_EVICTIONS", + "BriefDescription": "TOR Inserts for SF or LLC Evictions", + "PublicDescription": "TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x69", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REMOTE_SF.MISS", + "BriefDescription": "UNC_CHA_REMOTE_SF.MISS", + "PublicDescription": "UNC_CHA_REMOTE_SF.MISS", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "MDF", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_MDF_CLOCKTICKS", + "BriefDescription": "MDF Clockticks", + "PublicDescription": "MDF Clockticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD42FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL", + "BriefDescription": "ItoMCacheNear (partial write) transactions from an IO device that addresses memory on the local socket", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that address memory on the local socket", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD437F", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE", + "BriefDescription": "ItoMCacheNear (partial write) transactions from an IO device that addresses memory on a remote socket", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that address memory on a remote socket", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC42FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL", + "BriefDescription": "ItoM (write) transactions from an IO device that addresses memory on the local socket", + "PublicDescription": "TOR Inserts : ItoM, indicating a write request, from IO Devices that address memory on the local socket", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC437F", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE", + "BriefDescription": "ItoM (write) transactions from an IO device that addresses memory on a remote socket", + "PublicDescription": "TOR Inserts : ItoM, indicating a write request, from IO Devices that address memory on a remote socket", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8F2FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL", + "BriefDescription": "PCIRDCUR (read) transactions from an IO device that addresses memory on the local socket", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that addresses memory on the local socket", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8F37F", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE", + "BriefDescription": "PCIRDCUR (read) transactions from an IO device that addresses memory on a remote socket", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that addresses memory on a remote socket", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x8e", + "UMask": "0x04", + "PortMask": "0x0FF", + "FCMask": "0x01", + "UMaskExt": "0x00010FF0", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX_POSTED", + "BriefDescription": "Posted requests sent by the integrated IO (IIO) controller to the Ubox, useful for counting message signaled interrupts (MSI).", + "PublicDescription": "-", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + } + ] +} \ No newline at end of file diff --git a/cmd/metrics/resources/perfmon/icx/icelakex_core.json b/cmd/metrics/resources/perfmon/icx/icelakex_core.json new file mode 100644 index 00000000..7f50a48d --- /dev/null +++ b/cmd/metrics/resources/perfmon/icx/icelakex_core.json @@ -0,0 +1,8723 @@ +{ + "Header": { + "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for 3rd Generation Intel(R) Xeon(R) Processor Scalable Family based on Ice Lake microarchitecture - V1.28", + "DatePublished": "04/18/2025", + "Version": "1.28", + "Legend": "" + }, + "Events": [ + { + "EventCode": "0x00", + "UMask": "0x01", + "EventName": "INST_RETIRED.ANY", + "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event", + "PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", + "Counter": "Fixed counter 0", + "PEBScounters": "32", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0x00", + "UMask": "0x01", + "EventName": "INST_RETIRED.PREC_DIST", + "BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution", + "PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0.", + "Counter": "Fixed counter 0", + "PEBScounters": "32", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0x00", + "UMask": "0x02", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "BriefDescription": "Core cycles when the thread is not in halt state", + "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.", + "Counter": "Fixed counter 1", + "PEBScounters": "33", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x00", + "UMask": "0x03", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "BriefDescription": "Reference cycles when the core is not in halt state.", + "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", + "Counter": "Fixed counter 2", + "PEBScounters": "34", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x00", + "UMask": "0x04", + "EventName": "TOPDOWN.SLOTS", + "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", + "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", + "Counter": "Fixed counter 3", + "PEBScounters": "35", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x03", + "UMask": "0x02", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", + "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x03", + "UMask": "0x08", + "EventName": "LD_BLOCKS.NO_SR", + "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x07", + "UMask": "0x01", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "BriefDescription": "False dependencies due to partial compare on address.", + "PublicDescription": "Counts the number of times a load got blocked due to false dependencies due to partial compare on address.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x08", + "UMask": "0x02", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Page walks completed due to a demand data load to a 4K page.", + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x08", + "UMask": "0x04", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.", + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x08", + "UMask": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "BriefDescription": "Page walks completed due to a demand data load to a 1G page.", + "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x08", + "UMask": "0x0e", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x08", + "UMask": "0x10", + "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", + "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.", + "PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x08", + "UMask": "0x10", + "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.", + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x08", + "UMask": "0x20", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "BriefDescription": "Loads that miss the DTLB and hit the STLB.", + "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x0D", + "UMask": "0x01", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread", + "PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x0D", + "UMask": "0x01", + "EventName": "INT_MISC.CLEARS_COUNT", + "BriefDescription": "Clears speculative count", + "PublicDescription": "Counts the number of speculative clears due to any type of branch misprediction or machine clears", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x0D", + "UMask": "0x03", + "EventName": "INT_MISC.ALL_RECOVERY_CYCLES", + "BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.", + "PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x0d", + "UMask": "0x10", + "EventName": "INT_MISC.UOP_DROPPING", + "BriefDescription": "TMA slots where uops got dropped", + "PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x0d", + "UMask": "0x80", + "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", + "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", + "PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x0e", + "UMask": "0x01", + "EventName": "UOPS_ISSUED.ANY", + "BriefDescription": "Uops that RAT issues to RS", + "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x0E", + "UMask": "0x01", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "BriefDescription": "Cycles when RAT does not issue Uops to RS for the thread", + "PublicDescription": "Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x0e", + "UMask": "0x02", + "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", + "BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.", + "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to 'Mixing Intel AVX and Intel SSE Code' section of the Optimization Guide.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x14", + "UMask": "0x01", + "EventName": "ARITH.FP_DIVIDER_ACTIVE", + "BriefDescription": "ARITH.FP_DIVIDER_ACTIVE", + "PublicDescription": "ARITH.FP_DIVIDER_ACTIVE", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x14", + "UMask": "0x09", + "EventName": "ARITH.DIVIDER_ACTIVE", + "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.", + "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x21", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "BriefDescription": "Demand Data Read miss L2, no rejects", + "PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x22", + "EventName": "L2_RQSTS.RFO_MISS", + "BriefDescription": "RFO requests that miss L2 cache", + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "BriefDescription": "L2 cache misses when fetching instructions", + "PublicDescription": "Counts L2 cache misses when fetching instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x27", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "BriefDescription": "Demand requests that miss L2 cache", + "PublicDescription": "Counts demand requests that miss L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x28", + "EventName": "L2_RQSTS.SWPF_MISS", + "BriefDescription": "SW prefetch requests that miss L2 cache.", + "PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xc1", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "BriefDescription": "Demand Data Read requests that hit L2 cache", + "PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xc2", + "EventName": "L2_RQSTS.RFO_HIT", + "BriefDescription": "RFO requests that hit L2 cache", + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xc4", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xc8", + "EventName": "L2_RQSTS.SWPF_HIT", + "BriefDescription": "SW prefetch requests that hit L2 cache.", + "PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xE1", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "BriefDescription": "Demand Data Read requests", + "PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xE2", + "EventName": "L2_RQSTS.ALL_RFO", + "BriefDescription": "RFO requests to L2 cache", + "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xE4", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "BriefDescription": "L2 code requests", + "PublicDescription": "Counts the total number of L2 code requests.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x28", + "UMask": "0x07", + "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", + "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", + "PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x28", + "UMask": "0x18", + "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", + "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.", + "PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x28", + "UMask": "0x20", + "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", + "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", + "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchitecture). This includes high current AVX 512-bit instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x2e", + "UMask": "0x41", + "EventName": "LONGEST_LAT_CACHE.MISS", + "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)", + "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x2e", + "UMask": "0x4f", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)", + "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x32", + "UMask": "0x01", + "EventName": "SW_PREFETCH_ACCESS.NTA", + "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x32", + "UMask": "0x02", + "EventName": "SW_PREFETCH_ACCESS.T0", + "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x32", + "UMask": "0x04", + "EventName": "SW_PREFETCH_ACCESS.T1_T2", + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x32", + "UMask": "0x08", + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", + "BriefDescription": "Number of PREFETCHW instructions executed.", + "PublicDescription": "Counts the number of PREFETCHW instructions executed.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x32", + "UMask": "0x0F", + "EventName": "SW_PREFETCH_ACCESS.ANY", + "BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.", + "PublicDescription": "Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x3C", + "UMask": "0x00", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "BriefDescription": "Thread cycles when thread is not in halt state", + "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x3C", + "UMask": "0x01", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", + "PublicDescription": "Counts core crystal clock cycles when the thread is unhalted.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "25003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x3C", + "UMask": "0x02", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.", + "PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "25003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x3c", + "UMask": "0x08", + "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.", + "PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x48", + "UMask": "0x01", + "EventName": "L1D_PEND_MISS.PENDING", + "BriefDescription": "Number of L1D misses that are outstanding", + "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x48", + "UMask": "0x01", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "PublicDescription": "Counts duration of L1D miss outstanding in cycles.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x48", + "UMask": "0x02", + "EventName": "L1D_PEND_MISS.FB_FULL", + "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.", + "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x48", + "UMask": "0x02", + "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS", + "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.", + "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x48", + "UMask": "0x04", + "EventName": "L1D_PEND_MISS.L2_STALL", + "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", + "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x49", + "UMask": "0x02", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Page walks completed due to a demand data store to a 4K page.", + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x49", + "UMask": "0x04", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.", + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x49", + "UMask": "0x08", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "BriefDescription": "Page walks completed due to a demand data store to a 1G page.", + "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x49", + "UMask": "0x0e", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x49", + "UMask": "0x10", + "EventName": "DTLB_STORE_MISSES.WALK_PENDING", + "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.", + "PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x49", + "UMask": "0x10", + "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.", + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x49", + "UMask": "0x20", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "BriefDescription": "Stores that miss the DTLB and hit the STLB.", + "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x4c", + "UMask": "0x01", + "EventName": "LOAD_HIT_PREFETCH.SWPF", + "BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.", + "PublicDescription": "Counts all software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x51", + "UMask": "0x01", + "EventName": "L1D.REPLACEMENT", + "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.", + "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x54", + "UMask": "0x01", + "EventName": "TX_MEM.ABORT_CONFLICT", + "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", + "PublicDescription": "Counts the number of times a TSX line had a cache conflict.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x54", + "UMask": "0x02", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.", + "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x54", + "UMask": "0x80", + "EventName": "TX_MEM.ABORT_CAPACITY_READ", + "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads", + "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x55", + "UMask": "0x01", + "EventName": "INST_DECODED.DECODERS", + "BriefDescription": "Instruction decoders utilized in a cycle", + "PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x56", + "UMask": "0x01", + "EventName": "UOPS_DECODED.DEC0", + "BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0", + "PublicDescription": "Uops exclusively fetched by decoder 0", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x5d", + "UMask": "0x02", + "EventName": "TX_EXEC.MISC2", + "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region", + "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x5d", + "UMask": "0x04", + "EventName": "TX_EXEC.MISC3", + "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded", + "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x5e", + "UMask": "0x01", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", + "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses)", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x5E", + "UMask": "0x01", + "EventName": "RS_EVENTS.EMPTY_END", + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.", + "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x60", + "UMask": "0x01", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "BriefDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.", + "PublicDescription": "For every cycle, increments by the number of outstanding demand data read requests pending. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x60", + "UMask": "0x02", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "BriefDescription": "For every cycle, increments by the number of outstanding code read requests pending.", + "PublicDescription": "For every cycle, increments by the number of outstanding code read requests pending. Code Read requests include both cacheable and non-cacheable Code Reads. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x60", + "UMask": "0x02", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", + "BriefDescription": "Cycles with outstanding code read requests pending.", + "PublicDescription": "Cycles with outstanding code read requests pending. Code Read requests include both cacheable and non-cacheable Code Reads. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x60", + "UMask": "0x04", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "BriefDescription": "Cycles where at least 1 outstanding Demand RFO request is pending.", + "PublicDescription": "Cycles where at least 1 outstanding Demand RFO request is pending. RFOs are initiated by a core as part of a data store operation. Demand RFO requests include RFOs, locks, and ItoM transactions. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x60", + "UMask": "0x08", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "BriefDescription": "For every cycle, increments by the number of outstanding data read requests pending.", + "PublicDescription": "For every cycle, increments by the number of outstanding data read requests pending. Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3. Reads due to page walks resulting from any request type will also be counted. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x60", + "UMask": "0x08", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "BriefDescription": "Cycles where at least 1 outstanding data read request is pending.", + "PublicDescription": "Cycles where at least 1 outstanding data read request is pending. Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3. Reads due to page walks resulting from any request type will also be counted. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x60", + "UMask": "0x10", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", + "BriefDescription": "This event is deprecated.", + "PublicDescription": "This event is deprecated.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "Speculative": "1" + }, + { + "EventCode": "0x60", + "UMask": "0x10", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", + "BriefDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending.", + "PublicDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x60", + "UMask": "0x10", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6", + "BriefDescription": "Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache.", + "PublicDescription": "Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache. Note that this event does not capture all elapsed cycles while the requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "6", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x04", + "EventName": "IDQ.MITE_UOPS", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x04", + "EventName": "IDQ.MITE_CYCLES_OK", + "BriefDescription": "Cycles MITE is delivering optimal number of Uops", + "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "5", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x04", + "EventName": "IDQ.MITE_CYCLES_ANY", + "BriefDescription": "Cycles MITE is delivering any Uop", + "PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x08", + "EventName": "IDQ.DSB_UOPS", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", + "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x08", + "EventName": "IDQ.DSB_CYCLES_OK", + "BriefDescription": "Cycles DSB is delivering optimal number of Uops", + "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode Stream Buffer) path. Count includes uops that may 'bypass' the IDQ.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "5", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x08", + "EventName": "IDQ.DSB_CYCLES_ANY", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", + "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x30", + "EventName": "IDQ.MS_SWITCHES", + "BriefDescription": "Number of switches from DSB or MITE to the MS", + "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x30", + "EventName": "IDQ.MS_UOPS", + "BriefDescription": "Uops delivered to IDQ while MS is busy", + "PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x80", + "UMask": "0x04", + "EventName": "ICACHE_16B.IFDATA_STALL", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss. [This event is alias to ICACHE_DATA.STALLS]", + "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity. [This event is alias to ICACHE_DATA.STALLS]", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x80", + "UMask": "0x04", + "EventName": "ICACHE_DATA.STALLS", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss. [This event is alias to ICACHE_16B.IFDATA_STALL]", + "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity. [This event is alias to ICACHE_16B.IFDATA_STALL]", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x83", + "UMask": "0x01", + "EventName": "ICACHE_64B.IFTAG_HIT", + "BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "PublicDescription": "Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x83", + "UMask": "0x02", + "EventName": "ICACHE_64B.IFTAG_MISS", + "BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "PublicDescription": "Counts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x83", + "UMask": "0x04", + "EventName": "ICACHE_64B.IFTAG_STALL", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]", + "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x83", + "UMask": "0x04", + "EventName": "ICACHE_TAG.STALLS", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]", + "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x85", + "UMask": "0x02", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", + "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x85", + "UMask": "0x04", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", + "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x85", + "UMask": "0x0e", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", + "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x85", + "UMask": "0x10", + "EventName": "ITLB_MISSES.WALK_PENDING", + "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.", + "PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x85", + "UMask": "0x10", + "EventName": "ITLB_MISSES.WALK_ACTIVE", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.", + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x85", + "UMask": "0x20", + "EventName": "ITLB_MISSES.STLB_HIT", + "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.", + "PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x87", + "UMask": "0x01", + "EventName": "ILD_STALL.LCP", + "BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to DECODE.LCP]", + "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to DECODE.LCP]", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x87", + "UMask": "0x01", + "EventName": "DECODE.LCP", + "BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to ILD_STALL.LCP]", + "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to ILD_STALL.LCP]", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x9c", + "UMask": "0x01", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled", + "PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x9c", + "UMask": "0x01", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled", + "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "5", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0x9C", + "UMask": "0x01", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled", + "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa1", + "UMask": "0x01", + "EventName": "UOPS_DISPATCHED.PORT_0", + "BriefDescription": "Number of uops executed on port 0", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa1", + "UMask": "0x02", + "EventName": "UOPS_DISPATCHED.PORT_1", + "BriefDescription": "Number of uops executed on port 1", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa1", + "UMask": "0x04", + "EventName": "UOPS_DISPATCHED.PORT_2_3", + "BriefDescription": "Number of uops executed on port 2 and 3", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa1", + "UMask": "0x10", + "EventName": "UOPS_DISPATCHED.PORT_4_9", + "BriefDescription": "Number of uops executed on port 4 and 9", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa1", + "UMask": "0x20", + "EventName": "UOPS_DISPATCHED.PORT_5", + "BriefDescription": "Number of uops executed on port 5", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa1", + "UMask": "0x40", + "EventName": "UOPS_DISPATCHED.PORT_6", + "BriefDescription": "Number of uops executed on port 6", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa1", + "UMask": "0x80", + "EventName": "UOPS_DISPATCHED.PORT_7_8", + "BriefDescription": "Number of uops executed on port 7 and 8", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa2", + "UMask": "0x02", + "EventName": "RESOURCE_STALLS.SCOREBOARD", + "BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.", + "PublicDescription": "Counts cycles where the pipeline is stalled due to serializing operations.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa2", + "UMask": "0x08", + "EventName": "RESOURCE_STALLS.SB", + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xA3", + "UMask": "0x01", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", + "PublicDescription": "Cycles while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x04", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", + "BriefDescription": "Total execution stalls.", + "PublicDescription": "Total execution stalls.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "4", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x05", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "PublicDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "5", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x06", + "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", + "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", + "PublicDescription": "Execution stalls while L3 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "6", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xA3", + "UMask": "0x08", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "PublicDescription": "Cycles while L1 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "8", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xA3", + "UMask": "0x0C", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "PublicDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "12", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xA3", + "UMask": "0x10", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "PublicDescription": "Cycles while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "16", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x14", + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "PublicDescription": "Execution stalls while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "20", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa4", + "UMask": "0x01", + "EventName": "TOPDOWN.SLOTS_P", + "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", + "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa4", + "UMask": "0x02", + "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", + "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", + "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x02", + "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", + "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.", + "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x04", + "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", + "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.", + "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x08", + "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", + "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.", + "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x10", + "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", + "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.", + "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xA6", + "UMask": "0x40", + "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", + "BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.", + "PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "2", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa8", + "UMask": "0x01", + "EventName": "LSD.UOPS", + "BriefDescription": "Number of Uops delivered by the LSD.", + "PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xA8", + "UMask": "0x01", + "EventName": "LSD.CYCLES_ACTIVE", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xa8", + "UMask": "0x01", + "EventName": "LSD.CYCLES_OK", + "BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.", + "PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "5", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xab", + "UMask": "0x02", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "BriefDescription": "DSB-to-MITE switch true penalty cycles.", + "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xab", + "UMask": "0x02", + "EventName": "DSB2MITE_SWITCHES.COUNT", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", + "PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb0", + "UMask": "0x01", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "BriefDescription": "Demand Data Read requests sent to uncore", + "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb0", + "UMask": "0x02", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "BriefDescription": "Counts cacheable and non-cacheable code reads to the core.", + "PublicDescription": "Counts both cacheable and non-cacheable code reads to the core.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb0", + "UMask": "0x04", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", + "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xB0", + "UMask": "0x08", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "BriefDescription": "Demand and prefetch data reads", + "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb0", + "UMask": "0x10", + "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "BriefDescription": "Counts demand data read requests that miss the L3 cache.", + "PublicDescription": "Counts demand data read requests that miss the L3 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xB0", + "UMask": "0x80", + "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", + "BriefDescription": "Counts memory transactions sent to the uncore.", + "PublicDescription": "Counts memory transactions sent to the uncore including requests initiated by the core, all L3 prefetches, reads resulting from page walks, and snoop responses.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.THREAD", + "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", + "PublicDescription": "Counts the number of uops to be executed per-thread each cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xB1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1", + "BriefDescription": "Cycles where at least 1 uop was executed per-thread", + "PublicDescription": "Cycles where at least 1 uop was executed per-thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2", + "BriefDescription": "Cycles where at least 2 uops were executed per-thread", + "PublicDescription": "Cycles where at least 2 uops were executed per-thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "2", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3", + "BriefDescription": "Cycles where at least 3 uops were executed per-thread", + "PublicDescription": "Cycles where at least 3 uops were executed per-thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "3", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4", + "BriefDescription": "Cycles where at least 4 uops were executed per-thread", + "PublicDescription": "Cycles where at least 4 uops were executed per-thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "4", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xB1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xB1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "2", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xB1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "3", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xB1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "4", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xB1", + "UMask": "0x10", + "EventName": "UOPS_EXECUTED.X87", + "BriefDescription": "Counts the number of x87 uops dispatched.", + "PublicDescription": "Counts the number of x87 uops executed.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xBD", + "UMask": "0x01", + "EventName": "TLB_FLUSH.DTLB_THREAD", + "BriefDescription": "DTLB flush attempts of the thread-specific entries", + "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xBD", + "UMask": "0x20", + "EventName": "TLB_FLUSH.STLB_ANY", + "BriefDescription": "STLB flush attempts", + "PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xc0", + "UMask": "0x00", + "EventName": "INST_RETIRED.ANY_P", + "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc0", + "UMask": "0x02", + "EventName": "INST_RETIRED.NOP", + "BriefDescription": "Number of all retired NOP instructions.", + "PublicDescription": "Number of all retired NOP instructions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc1", + "UMask": "0x02", + "EventName": "ASSISTS.FP", + "BriefDescription": "Counts all microcode FP assists.", + "PublicDescription": "Counts all microcode Floating Point assists.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xc1", + "UMask": "0x07", + "EventName": "ASSISTS.ANY", + "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.", + "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xc2", + "UMask": "0x02", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "BriefDescription": "Cycles without actually retired uops.", + "PublicDescription": "This event counts cycles without actually retired uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xc2", + "UMask": "0x02", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "BriefDescription": "Cycles with less than 10 actually retired uops.", + "PublicDescription": "Counts the number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "10", + "Invert": "1", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x02", + "EventName": "UOPS_RETIRED.SLOTS", + "BriefDescription": "Retirement slots used.", + "PublicDescription": "Counts the retirement slots used each cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc3", + "UMask": "0x01", + "EventName": "MACHINE_CLEARS.COUNT", + "BriefDescription": "Number of machine clears (nukes) of any type.", + "PublicDescription": "Counts the number of machine clears (nukes) of any type.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xc3", + "UMask": "0x02", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "BriefDescription": "Number of machine clears due to memory ordering conflicts.", + "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xc3", + "UMask": "0x04", + "EventName": "MACHINE_CLEARS.SMC", + "BriefDescription": "Self-modifying code (SMC) detected.", + "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xc4", + "UMask": "0x00", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "BriefDescription": "All branch instructions retired.", + "PublicDescription": "Counts all branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x01", + "EventName": "BR_INST_RETIRED.COND_TAKEN", + "BriefDescription": "Taken conditional branch instructions retired.", + "PublicDescription": "Counts taken conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x02", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "BriefDescription": "Direct and indirect near call instructions retired.", + "PublicDescription": "Counts both direct and indirect near call instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x08", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "BriefDescription": "Return instructions retired.", + "PublicDescription": "Counts return instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x10", + "EventName": "BR_INST_RETIRED.COND_NTAKEN", + "BriefDescription": "Not taken branch instructions retired.", + "PublicDescription": "Counts not taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x11", + "EventName": "BR_INST_RETIRED.COND", + "BriefDescription": "Conditional branch instructions retired.", + "PublicDescription": "Counts conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x20", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "BriefDescription": "Taken branch instructions retired.", + "PublicDescription": "Counts taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x40", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "BriefDescription": "Far branch instructions retired.", + "PublicDescription": "Counts far branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x80", + "EventName": "BR_INST_RETIRED.INDIRECT", + "BriefDescription": "Indirect near branch instructions retired (excluding returns)", + "PublicDescription": "Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x00", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "BriefDescription": "All mispredicted branch instructions retired.", + "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x01", + "EventName": "BR_MISP_RETIRED.COND_TAKEN", + "BriefDescription": "number of branch instructions retired that were mispredicted and taken.", + "PublicDescription": "Counts taken conditional mispredicted branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x02", + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", + "BriefDescription": "Mispredicted indirect CALL instructions retired.", + "PublicDescription": "Counts retired mispredicted indirect (near taken) calls, including both register and memory indirect.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x08", + "EventName": "BR_MISP_RETIRED.RET", + "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x10", + "EventName": "BR_MISP_RETIRED.COND_NTAKEN", + "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", + "PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x11", + "EventName": "BR_MISP_RETIRED.COND", + "BriefDescription": "Mispredicted conditional branch instructions retired.", + "PublicDescription": "Counts mispredicted conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x20", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", + "PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x80", + "EventName": "BR_MISP_RETIRED.INDIRECT", + "BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", + "PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.DSB_MISS", + "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", + "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x11", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.L1I_MISS", + "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", + "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x12", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.L2_MISS", + "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", + "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x13", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.ITLB_MISS", + "BriefDescription": "Retired Instructions who experienced iTLB true miss.", + "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x14", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.STLB_MISS", + "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.", + "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x15", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", + "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x500206", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x500406", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x500806", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x501006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x502006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x504006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x508006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x510006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x520006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x100206", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", + "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x500106", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", + "BriefDescription": "Retired Instructions who experienced DSB miss.", + "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x1", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x01", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x02", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x03", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR", + "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x04", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x08", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x10", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x18", + "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x20", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x40", + "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x60", + "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x80", + "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0xfc", + "EventName": "FP_ARITH_INST_RETIRED.VECTOR", + "BriefDescription": "Number of any Vector retired FP arithmetic instructions", + "PublicDescription": "Number of any Vector retired FP arithmetic instructions", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x01", + "EventName": "RTM_RETIRED.START", + "BriefDescription": "Number of times an RTM execution started.", + "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x02", + "EventName": "RTM_RETIRED.COMMIT", + "BriefDescription": "Number of times an RTM execution successfully committed", + "PublicDescription": "Counts the number of times RTM commit succeeded.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x04", + "EventName": "RTM_RETIRED.ABORTED", + "BriefDescription": "Number of times an RTM execution aborted.", + "PublicDescription": "Counts the number of times RTM abort was triggered.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x08", + "EventName": "RTM_RETIRED.ABORTED_MEM", + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", + "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x20", + "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", + "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", + "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x40", + "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", + "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", + "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x80", + "EventName": "RTM_RETIRED.ABORTED_EVENTS", + "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 3 categories (e.g. interrupt)", + "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 3 categories (e.g. interrupt).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcc", + "UMask": "0x20", + "EventName": "MISC_RETIRED.LBR_INSERTS", + "BriefDescription": "Increments whenever there is an update to the LBR array.", + "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR to be enabled properly.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcc", + "UMask": "0x40", + "EventName": "MISC_RETIRED.PAUSE_INST", + "BriefDescription": "Number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.", + "PublicDescription": "Counts number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0", + "MSRValue": "0", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "20011", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2003", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1009", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "503", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "101", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x11", + "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", + "BriefDescription": "Retired load instructions that miss the STLB.", + "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x12", + "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", + "BriefDescription": "Retired store instructions that miss the STLB.", + "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x21", + "EventName": "MEM_INST_RETIRED.LOCK_LOADS", + "BriefDescription": "Retired load instructions with locked access.", + "PublicDescription": "Counts retired load instructions with locked access.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x41", + "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", + "BriefDescription": "Retired load instructions that split across a cacheline boundary.", + "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x42", + "EventName": "MEM_INST_RETIRED.SPLIT_STORES", + "BriefDescription": "Retired store instructions that split across a cacheline boundary.", + "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x81", + "EventName": "MEM_INST_RETIRED.ALL_LOADS", + "BriefDescription": "Retired load instructions.", + "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x82", + "EventName": "MEM_INST_RETIRED.ALL_STORES", + "BriefDescription": "Retired store instructions.", + "PublicDescription": "Counts all retired store instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x83", + "EventName": "MEM_INST_RETIRED.ANY", + "BriefDescription": "All retired memory instructions.", + "PublicDescription": "Counts all retired memory instructions - loads and stores.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x01", + "EventName": "MEM_LOAD_RETIRED.L1_HIT", + "BriefDescription": "Retired load instructions with L1 cache hits as data sources", + "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x02", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "BriefDescription": "Retired load instructions with L2 cache hits as data sources", + "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x04", + "EventName": "MEM_LOAD_RETIRED.L3_HIT", + "BriefDescription": "Retired load instructions with L3 cache hits as data sources", + "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x08", + "EventName": "MEM_LOAD_RETIRED.L1_MISS", + "BriefDescription": "Retired load instructions missed L1 cache as data sources", + "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x10", + "EventName": "MEM_LOAD_RETIRED.L2_MISS", + "BriefDescription": "Retired load instructions missed L2 cache as data sources", + "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x20", + "EventName": "MEM_LOAD_RETIRED.L3_MISS", + "BriefDescription": "Retired load instructions missed L3 cache as data sources", + "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "50021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x40", + "EventName": "MEM_LOAD_RETIRED.FB_HIT", + "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.", + "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x80", + "EventName": "MEM_LOAD_RETIRED.LOCAL_PMM", + "BriefDescription": "Retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.", + "PublicDescription": "Counts retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd2", + "UMask": "0x01", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd2", + "UMask": "0x02", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", + "BriefDescription": "This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "PublicDescription": "This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "Speculative": "0" + }, + { + "EventCode": "0xd2", + "UMask": "0x02", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache", + "PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd2", + "UMask": "0x04", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", + "BriefDescription": "This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "PublicDescription": "This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "Speculative": "0" + }, + { + "EventCode": "0xd2", + "UMask": "0x04", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", + "PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd2", + "UMask": "0x08", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", + "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required", + "PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd3", + "UMask": "0x01", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", + "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram", + "PublicDescription": "Retired load instructions which data sources missed L3 but serviced from local DRAM.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd3", + "UMask": "0x02", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from remote dram", + "PublicDescription": "Retired load instructions which data sources missed L3 but serviced from remote dram", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd3", + "UMask": "0x04", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "BriefDescription": "Retired load instructions whose data sources was remote HITM", + "PublicDescription": "Retired load instructions whose data sources was remote HITM.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd3", + "UMask": "0x08", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "BriefDescription": "Retired load instructions whose data sources was forwarded from a remote cache", + "PublicDescription": "Retired load instructions whose data sources was forwarded from a remote cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd3", + "UMask": "0x10", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM", + "BriefDescription": "Retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.", + "PublicDescription": "Counts retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd4", + "UMask": "0x04", + "EventName": "MEM_LOAD_MISC_RETIRED.UC", + "BriefDescription": "Retired instructions with at least 1 uncacheable load or Bus Lock.", + "PublicDescription": "Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xe6", + "UMask": "0x01", + "EventName": "BACLEARS.ANY", + "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", + "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xec", + "UMask": "0x02", + "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", + "BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.", + "PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xef", + "UMask": "0x01", + "EventName": "CORE_SNOOP_RESPONSE.MISS", + "BriefDescription": "Line not found snoop reply", + "PublicDescription": "Counts responses to snoops indicating that the data was not found (IHitI) in this core's caches. A single snoop response from the core counts on all hyperthreads of the Core.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xef", + "UMask": "0x02", + "EventName": "CORE_SNOOP_RESPONSE.I_HIT_FSE", + "BriefDescription": "Hit snoop reply without sending the data, line invalidated.", + "PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated in this core's caches without being forwarded back to the requestor. The line was in Forward, Shared or Exclusive (FSE) state in this cores caches. A single snoop response from the core counts on all hyperthreads of the core.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xef", + "UMask": "0x04", + "EventName": "CORE_SNOOP_RESPONSE.S_HIT_FSE", + "BriefDescription": "Hit snoop reply without sending the data, line kept in Shared state.", + "PublicDescription": "Counts responses to snoops indicating the line was kept on this core in the (S)hared state, and that the data was found unmodified but not forwarded back to the requestor, initially the data was found in the cache in the (FSE) Forward, Shared state or Exclusive state. A single snoop response from the core counts on all hyperthreads of the core.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xef", + "UMask": "0x08", + "EventName": "CORE_SNOOP_RESPONSE.S_FWD_M", + "BriefDescription": "HitM snoop reply with data, line kept in Shared state", + "PublicDescription": "Counts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (M)odified state. A single snoop response from the core counts on all hyperthreads of the core.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xef", + "UMask": "0x10", + "EventName": "CORE_SNOOP_RESPONSE.I_FWD_M", + "BriefDescription": "HitM snoop reply with data, line invalidated.", + "PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's caches, after the data is forwarded back to the requestor, and indicating the data was found modified(M) in this cores caches cache (aka HitM response). A single snoop response from the core counts on all hyperthreads of the core.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xef", + "UMask": "0x20", + "EventName": "CORE_SNOOP_RESPONSE.I_FWD_FE", + "BriefDescription": "Hit snoop reply with data, line invalidated.", + "PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's cache, after the data is forwarded back to the requestor and indicating the data was found unmodified in the (FE) Forward or Exclusive State in this cores caches cache. A single snoop response from the core counts on all hyperthreads of the core.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xef", + "UMask": "0x40", + "EventName": "CORE_SNOOP_RESPONSE.S_FWD_FE", + "BriefDescription": "Hit snoop reply with data, line kept in Shared state.", + "PublicDescription": "Counts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (FS) Forward or Shared state. A single snoop response from the core counts on all hyperthreads of the core.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xF0", + "UMask": "0x40", + "EventName": "L2_TRANS.L2_WB", + "BriefDescription": "L2 writebacks that access L2 cache", + "PublicDescription": "Counts L2 writebacks that access L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xF1", + "UMask": "0x1F", + "EventName": "L2_LINES_IN.ALL", + "BriefDescription": "L2 cache lines filling L2", + "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xF2", + "UMask": "0x01", + "EventName": "L2_LINES_OUT.SILENT", + "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache.", + "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache. These lines are typically in Shared or Exclusive state. A non-threaded event.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xF2", + "UMask": "0x02", + "EventName": "L2_LINES_OUT.NON_SILENT", + "BriefDescription": "Cache lines that are evicted by L2 cache when triggered by an L2 cache fill.", + "PublicDescription": "Counts the number of lines that are evicted by the L2 cache due to L2 cache fills. Evicted lines are delivered to the L3, which may or may not cache them, according to system load and priorities.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xf2", + "UMask": "0x04", + "EventName": "L2_LINES_OUT.USELESS_HWPF", + "BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses", + "PublicDescription": "Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xf4", + "UMask": "0x04", + "EventName": "SQ_MISC.SQ_FULL", + "BriefDescription": "Cycles the queue waiting for offcore responses is full.", + "PublicDescription": "Counts the cycles for which the thread is active and the queue waiting for responses from the uncore cannot take any more entries.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xF4", + "UMask": "0x10", + "EventName": "SQ_MISC.BUS_LOCK", + "BriefDescription": "Counts bus locks, accounts for cache line split locks and UC locks.", + "PublicDescription": "Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically. Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "Speculative": "1" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data.", + "PublicDescription": "Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "BriefDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "PublicDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "PublicDescription": "Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "BriefDescription": "Counts demand data reads that have any type of response.", + "PublicDescription": "Counts demand data reads that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", + "BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", + "PublicDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", + "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "PublicDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104000002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104000004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS", + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", + "PublicDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00400", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM", + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "PublicDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104000400", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", + "BriefDescription": "Counts streaming stores that have any type of response.", + "PublicDescription": "Counts streaming stores that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10800", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.OTHER.ANY_RESPONSE", + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.", + "PublicDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x18000", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.OTHER.L3_MISS", + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches.", + "PublicDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC08000", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L3.ANY_RESPONSE", + "BriefDescription": "Counts hardware prefetches to the L3 only that have any type of response.", + "PublicDescription": "Counts hardware prefetches to the L3 only that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x12380", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.REMOTE_DRAM", + "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to another socket.", + "PublicDescription": "Counts demand data reads that were supplied by DRAM attached to another socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x730000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HITM", + "BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.", + "PublicDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1030000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HIT_WITH_FWD", + "BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "PublicDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x830000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.DRAM", + "BriefDescription": "Counts demand data reads that were supplied by DRAM.", + "PublicDescription": "Counts demand data reads that were supplied by DRAM.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.REMOTE_PMM", + "BriefDescription": "Counts demand data reads that were supplied by PMM attached to another socket.", + "PublicDescription": "Counts demand data reads that were supplied by PMM attached to another socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x703000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL", + "BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "PublicDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F84400001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.LOCAL_PMM", + "BriefDescription": "Counts demand data reads that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.", + "PublicDescription": "Counts demand data reads that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100400001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.PMM", + "BriefDescription": "Counts demand data reads that were supplied by PMM.", + "PublicDescription": "Counts demand data reads that were supplied by PMM.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x703C00001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.DRAM", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C000002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.REMOTE_PMM", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to another socket.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to another socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x703000002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.LOCAL_PMM", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100400002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.PMM", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x703C00002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.DRAM", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C000004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F84400004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM", + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM.", + "PublicDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C000400", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS_LOCAL", + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "PublicDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F84400400", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.OTHER.L3_MISS_LOCAL", + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "PublicDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F84408000", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.SNC_PMM", + "BriefDescription": "Counts demand data reads that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand data reads that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x700800001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.SNC_PMM", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x700800002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", + "BriefDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.", + "PublicDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.L3_HIT", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT", + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.", + "PublicDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0400", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1030000477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x830000477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified).", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified).", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1830000477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.DRAM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C000477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104000477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.REMOTE_DRAM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x730000477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.REMOTE_PMM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to another socket.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to another socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x703000477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.LOCAL_PMM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100400477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.SNC_PMM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x700800477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.SNC_DRAM", + "BriefDescription": "Counts demand data reads that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand data reads that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x708000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.SNC_DRAM", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x708000002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.SNC_DRAM", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x708000004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.SNC_DRAM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x708000477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F3FFC0002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F3FFC0477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.STREAMING_WR.L3_HIT", + "BriefDescription": "Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket.", + "PublicDescription": "Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80080800", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L3.L3_HIT", + "BriefDescription": "Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket.", + "PublicDescription": "Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80082380", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.L3_HIT", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F003C0477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F04400002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F04400477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL", + "BriefDescription": "Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "PublicDescription": "Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x84000800", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L3.L3_MISS_LOCAL", + "BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "PublicDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x84002380", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.ITOM.L3_MISS_LOCAL", + "BriefDescription": "Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "PublicDescription": "Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x84000002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.REMOTE", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F33000477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L3.REMOTE", + "BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.", + "PublicDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x90002380", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.ITOM.REMOTE", + "BriefDescription": "Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.", + "PublicDescription": "Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x90000002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.L3_MISS", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F3FC00002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.L3_MISS", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F3FC00477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.STREAMING_WR.L3_MISS", + "BriefDescription": "Counts streaming stores that missed the local socket's L1, L2, and L3 caches.", + "PublicDescription": "Counts streaming stores that missed the local socket's L1, L2, and L3 caches.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x94000800", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L3.L3_MISS", + "BriefDescription": "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.", + "PublicDescription": "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x94002380", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.PREFETCHES.L3_MISS_LOCAL", + "BriefDescription": "Counts hardware and software prefetches to all cache levels that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "PublicDescription": "Counts hardware and software prefetches to all cache levels that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F844027F0", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.PREFETCHES.L3_HIT", + "BriefDescription": "Counts hardware and software prefetches to all cache levels that hit in the L3 or were snooped from another core's caches on the same socket.", + "PublicDescription": "Counts hardware and software prefetches to all cache levels that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C27F0", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HIT_WITH_FWD", + "BriefDescription": "Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x808000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.SNC_CACHE.HIT_WITH_FWD", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x808000002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HIT_WITH_FWD", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x808000004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HIT_WITH_FWD", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x808000477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HITM", + "BriefDescription": "Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.SNC_CACHE.HITM", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008000002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HITM", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008000004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HITM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008000477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x70CC00477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_DRAM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x70C000477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_PMM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x700C00477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.HWPF_L2.ANY_RESPONSE", + "BriefDescription": "Counts hardware prefetch (which bring data to L2) that have any type of response.", + "PublicDescription": "Counts hardware prefetch (which bring data to L2) that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10070", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.REMOTE_MEMORY", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x731800477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7, 0xBB", + "UMask": "0x01", + "EventName": "OCR.WRITE_ESTIMATE.MEMORY", + "BriefDescription": "Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM)", + "PublicDescription": "Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM)", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFBFF80822", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "Speculative": "0" + } + ] +} \ No newline at end of file diff --git a/cmd/metrics/resources/perfmon/icx/icelakex_metrics.json b/cmd/metrics/resources/perfmon/icx/icelakex_metrics.json new file mode 100644 index 00000000..3ef9b5fa --- /dev/null +++ b/cmd/metrics/resources/perfmon/icx/icelakex_metrics.json @@ -0,0 +1,13995 @@ +{ + "Header": { + "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Metrics for 3rd Generation Intel(R) Xeon(R) Processor Scalable Family based on Ice Lake microarchitecture0", + "DatePublished": "06/17/2025", + "Version": "1.1", + "Legend": "", + "TmaVersion": "5.1", + "TmaFlavor": "Full" + }, + "Metrics": [ + { + "MetricName": "cpu_operating_frequency", + "LegacyName": "metric_CPU operating frequency (in GHz)", + "Level": 1, + "BriefDescription": "CPU operating frequency (in GHz)", + "UnitOfMeasure": "GHz", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + } + ], + "Formula": "(a / b * c) / 1000000000", + "Category": "Freq", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "cpu_utilization", + "LegacyName": "metric_CPU utilization %", + "Level": 1, + "BriefDescription": "Percentage of time spent in the active CPU power state C0", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + }, + { + "Name": "TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "Category": "Util", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "cpi", + "LegacyName": "metric_CPI", + "Level": 1, + "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "CPI", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "loads_per_instr", + "LegacyName": "metric_loads per instr", + "Level": 1, + "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "stores_per_instr", + "LegacyName": "metric_stores per instr", + "Level": 1, + "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l1d_mpi", + "LegacyName": "metric_L1D MPI (includes data+rfo w/ prefetches)", + "Level": 1, + "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "L1D.REPLACEMENT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l1d_demand_data_read_hits_per_instr", + "LegacyName": "metric_L1D demand data read hits per instr", + "Level": 1, + "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L1_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", + "LegacyName": "metric_L1-I code read misses (w/ prefetches) per instr", + "Level": 1, + "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "L2_RQSTS.ALL_CODE_RD", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, I-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_demand_data_read_hits_per_instr", + "LegacyName": "metric_L2 demand data read hits per instr", + "Level": 1, + "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_mpi", + "LegacyName": "metric_L2 MPI (includes code+data+rfo w/ prefetches)", + "Level": 1, + "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "L2_LINES_IN.ALL", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_demand_data_read_mpi", + "LegacyName": "metric_L2 demand data read MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_demand_code_mpi", + "LegacyName": "metric_L2 demand code MPI", + "Level": 1, + "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "L2_RQSTS.CODE_RD_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, I-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_data_read_mpi_demand_plus_prefetch", + "LegacyName": "metric_LLC data read MPI (demand+prefetch)", + "Level": 1, + "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF", + "Alias": "c" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "(a + b + c) / d", + "Category": "MPI, D-side", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_code_read_mpi_demand_plus_prefetch", + "LegacyName": "metric_LLC code read MPI (demand+prefetch)", + "Level": 1, + "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", + "Alias": "c" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "(b + c) / d", + "Category": "MPI, I-side", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_latency", + "LegacyName": "metric_Average LLC demand data read miss latency (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "Latency", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_latency_for_local_requests", + "LegacyName": "metric_Average LLC demand data read miss latency for LOCAL requests (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to local memory in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "Latency", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_latency_for_remote_requests", + "LegacyName": "metric_Average LLC demand data read miss latency for REMOTE requests (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to remote memory in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "Latency", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_to_pmem_latency", + "LegacyName": "metric_Average LLC demand data read miss to DCPMEM latency (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to Intel(R) Optane(TM) Persistent Memory(PMEM) in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "Latency", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_to_dram_latency", + "LegacyName": "metric_Average LLC demand data read miss to DRAM latency (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to DRAM in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "Latency", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "itlb_2nd_level_mpi", + "LegacyName": "metric_ITLB (2nd level) MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, I-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "itlb_2nd_level_large_page_mpi", + "LegacyName": "metric_ITLB (2nd level) large page MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "dtlb_2nd_level_load_mpi", + "LegacyName": "metric_DTLB (2nd level) load MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi", + "LegacyName": "metric_DTLB (2nd level) 2MB large page load MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "dtlb_2nd_level_store_mpi", + "LegacyName": "metric_DTLB (2nd level) store MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "numa_reads_addressed_to_local_dram", + "LegacyName": "metric_NUMA %_Reads addressed to local DRAM", + "Level": 1, + "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", + "Alias": "c" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (a + b) / (a + b + c + d)", + "Category": "NUMA", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "numa_reads_addressed_to_remote_dram", + "LegacyName": "metric_NUMA %_Reads addressed to remote DRAM", + "Level": 1, + "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", + "Alias": "c" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (c + d) / (a + b + c + d)", + "Category": "NUMA", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "uncore_frequency", + "LegacyName": "metric_uncore frequency GHz", + "Level": 1, + "BriefDescription": "Uncore operating frequency in GHz", + "UnitOfMeasure": "GHz", + "Events": [ + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "b" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "(a / (b * socket_count) / 1000000000) / DURATIONTIMEINSECONDS", + "Category": "Freq", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "upi_data_transmit_bw", + "LegacyName": "metric_UPI Data transmit BW (MB/sec) (only data)", + "Level": 1, + "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_UPI_TxL_FLITS.ALL_DATA", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * (64 / 9.0) / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW", + "ResolutionLevels": "UPI, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_bandwidth_read", + "LegacyName": "metric_memory bandwidth read (MB/sec)", + "Level": 1, + "BriefDescription": "DDR memory read bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT.RD", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, MC", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_bandwidth_write", + "LegacyName": "metric_memory bandwidth write (MB/sec)", + "Level": 1, + "BriefDescription": "DDR memory write bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT.WR", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, MC", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_bandwidth_total", + "LegacyName": "metric_memory bandwidth total (MB/sec)", + "Level": 1, + "BriefDescription": "DDR memory bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT.RD", + "Alias": "a" + }, + { + "Name": "UNC_M_CAS_COUNT.WR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, MC", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_extra_write_bw_due_to_directory_updates", + "LegacyName": "metric_memory extra write b/w due to directory updates (MB/sec)", + "Level": 1, + "BriefDescription": "Memory write bandwidth (MB/sec) caused by directory updates; includes DDR and Intel(R) Optane(TM) Persistent Memory(PMEM).", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_DIR_UPDATE.HA", + "Alias": "a" + }, + { + "Name": "UNC_CHA_DIR_UPDATE.TOR", + "Alias": "b" + }, + { + "Name": "UNC_M2M_DIRECTORY_UPDATE.ANY", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "((a + b + c) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, MC", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "pmem_memory_bandwidth_read", + "LegacyName": "metric_3DXP_memory bandwidth read (MB/sec)", + "Level": 1, + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory read bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_PMM_RPQ_INSERTS", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "pmem_memory_bandwidth_write", + "LegacyName": "metric_3DXP_memory bandwidth write (MB/sec)", + "Level": 1, + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory write bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_PMM_WPQ_INSERTS", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "pmem_memory_bandwidth_total", + "LegacyName": "metric_3DXP_memory bandwidth total (MB/sec)", + "Level": 1, + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_PMM_RPQ_INSERTS", + "Alias": "a" + }, + { + "Name": "UNC_M_PMM_WPQ_INSERTS", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_read", + "LegacyName": "metric_IO_bandwidth_disk_or_network_writes (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_write", + "LegacyName": "metric_IO_bandwidth_disk_or_network_reads (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", + "Alias": "c" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "((a + b + c + d) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_read_l3_miss", + "LegacyName": "metric_IO % of inbound reads that miss L3", + "Level": 1, + "BriefDescription": "The percent of inbound reads initiated by IO that miss the L3 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_partial_write_l3_miss", + "LegacyName": "metric_IO % of inbound partial writes that miss L3", + "Level": 1, + "BriefDescription": "The percent of inbound partial writes initiated by IO that miss the L3 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_RFO", + "Alias": "c" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ((b + d) / (a + c) )", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_full_write_l3_miss", + "LegacyName": "metric_IO % of inbound full writes that miss L3", + "Level": 1, + "BriefDescription": "The percent of inbound full cache line writes initiated by IO that miss the L3 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * (b / a)", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "percent_uops_delivered_from_decoded_icache", + "LegacyName": "metric_% Uops delivered from decoded Icache (DSB)", + "Level": 1, + "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "LSD.UOPS", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (a / (a + b + c + d) )", + "Category": "I-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline", + "LegacyName": "metric_% Uops delivered from legacy decode pipeline (MITE)", + "Level": 1, + "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "LSD.UOPS", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (b / (a + b + c + d) )", + "Category": "I-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "percent_uops_delivered_from_microcode_sequencer", + "LegacyName": "metric_% Uops delivered from microcode sequencer (MS)", + "Level": 1, + "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "LSD.UOPS", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (c / (a + b + c + d) )", + "Category": "I-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_read_local", + "LegacyName": "metric_IO bandwidth read local (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the local CPU socket.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW,IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_read_remote", + "LegacyName": "metric_IO bandwidth read remote (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from a remote CPU socket.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW,IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_write_local", + "LegacyName": "metric_IO bandwidth write local (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the local CPU socket.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW,IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_write_remote", + "LegacyName": "metric_IO bandwidth write remote (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to a remote CPU socket.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW,IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_miss_local_memory_bandwidth_read", + "LegacyName": "metric_llc_miss_local_memory_bandwidth_read_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.READS_LOCAL", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_miss_local_memory_bandwidth_write", + "LegacyName": "metric_llc_miss_local_memory_bandwidth_write_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.WRITES_LOCAL", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_miss_remote_memory_bandwidth_read", + "LegacyName": "metric_llc_miss_remote_memory_bandwidth_read_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.READS_REMOTE", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_miss_remote_memory_bandwidth_write", + "LegacyName": "metric_llc_miss_remote_memory_bandwidth_write_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.WRITES_REMOTE", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "upi_data_receive_bw", + "LegacyName": "metric_UPI Data receive BW (MB/sec) (only data)", + "Level": 1, + "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data receive bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_UPI_RxL_FLITS.ALL_DATA", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * (64 / 9.0) / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW", + "ResolutionLevels": "UPI, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_read_l3_miss", + "LegacyName": "metric_IO_bandwidth_read_L3_miss (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of inbound IO reads that are initiated by end device controllers that are requesting memory from the CPU and miss the L3 cache.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_write_l3_miss", + "LegacyName": "metric_IO_bandwidth_write_L3_miss (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of inbound IO writes that are initiated by end device controllers that are writing memory to the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Bottleneck_Mispredictions", + "LegacyName": "metric_TMA_Bottleneck_Mispredictions", + "Level": 1, + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "d" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "e" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "g" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "h" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "i" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "j" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "k" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "l" + }, + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "m" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "n" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "o" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "p" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "q" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "r" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "s" + }, + { + "Name": "DECODE.LCP", + "Alias": "t" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "u" + } + ], + "Constants": [], + "Formula": "100 * ( 1 - ( 10 * ( ( a / b ) * c / ( d ) ) * ( max( ( ( e / ( e + f ) ) * ( max( 1 - ( ( g / ( g + h + i + j ) - k / ( d ) ) + ( j / ( g + h + i + j ) + ( ( 5 ) * l ) / ( d ) ) + ( i / ( g + h + i + j ) ) ) , 0 ) ) ) * ( 1 - e / ( l - f ) ) , 0.0001 ) ) / ( ( e / ( e + f ) ) * ( max( 1 - ( ( g / ( g + h + i + j ) - k / ( d ) ) + ( j / ( g + h + i + j ) + ( ( 5 ) * l ) / ( d ) ) + ( i / ( g + h + i + j ) ) ) , 0 ) ) ) ) ) * ( ( ( e / ( e + f ) ) * ( max( 1 - ( ( g / ( g + h + i + j ) - k / ( d ) ) + ( j / ( g + h + i + j ) + ( ( 5 ) * l ) / ( d ) ) + ( i / ( g + h + i + j ) ) ) , 0 ) ) ) + ( ( ( 5 ) * m - k ) / ( d ) ) * ( ( e / ( e + f ) ) * n / ( o ) ) / ( ( p / ( o ) ) + ( q / ( o ) ) + ( n / ( o ) + ( 10 ) * r / ( o ) ) + ( ( 3 ) * s / ( o ) ) + ( t / ( o ) ) + ( u / ( o ) ) ) )", + "BaseFormula": "100 * ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * ( tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Mispredictions" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Mispredictions > 20", + "ThresholdIssues": "$issueBM" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BadSpec;BrMispredicts;BvMP", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Big_Code", + "LegacyName": "metric_TMA_Bottleneck_Big_Code", + "Level": 1, + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "a" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "c" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "f" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "g" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "h" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "i" + }, + { + "Name": "DECODE.LCP", + "Alias": "j" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "k" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( d / ( e ) ) + ( f / ( e ) ) + ( ( 10 ) * g / ( e ) ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) + ( ( 3 ) * i / ( e ) ) + ( j / ( e ) ) + ( k / ( e ) ) )", + "BaseFormula": "100 * tma_fetch_latency * ( tma_itlb_misses + tma_icache_misses + tma_unknown_branches ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Big_Code" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Big_Code > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvBC;BigFootprint;Fed;Frontend;IcMiss;MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Instruction_Fetch_BW", + "LegacyName": "metric_TMA_Bottleneck_Instruction_Fetch_BW", + "Level": 1, + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "a_a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "g" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "h" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "i" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "j" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "k" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "l" + }, + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "m" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "n" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "o" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "p" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "q" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "r" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "s" + }, + { + "Name": "DECODE.LCP", + "Alias": "t" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "u" + }, + { + "Name": "UOPS_DECODED.DEC0", + "Alias": "v" + }, + { + "Name": "UOPS_DECODED.DEC0:c1", + "Alias": "w" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "x" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "y" + }, + { + "Name": "IDQ.MS_UOPS:c1", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a / ( a + b + c + d ) - e / ( f ) ) - ( 1 - ( 10 * ( ( g / h ) * i / ( f ) ) * ( max( ( ( j / ( j + k ) ) * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * l ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * ( 1 - j / ( l - k ) ) , 0.0001 ) ) / ( ( j / ( j + k ) ) * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * l ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) ) * ( ( ( 5 ) * m - e ) / ( f ) ) * ( ( j / ( j + k ) ) * n / ( o ) ) / ( ( p / ( o ) ) + ( q / ( o ) ) + ( n / ( o ) + ( 10 ) * r / ( o ) ) + ( ( 3 ) * s / ( o ) ) + ( t / ( o ) ) + ( u / ( o ) ) ) - ( ( ( ( ( g / h ) * i / ( f ) ) / ( ( ( ( ( g / h ) * i / ( f ) ) + ( c / ( a + b + c + d ) ) * ( v - w ) / x ) - ( ( g / h ) * i / ( f ) ) ) + ( ( g / h ) * i / ( f ) ) ) ) * ( ( ( 34 ) * y / ( f ) ) / ( ( g / h ) * i / ( f ) ) ) ) * ( ( ( ( 5 ) * m - e ) / ( f ) ) * ( ( ( 3 ) * s / ( o ) ) + ( n / ( o ) + ( 10 ) * r / ( o ) ) * ( ( ( 1 - ( j / ( j + k ) ) ) * n / ( o ) ) + ( 10 * ( ( g / h ) * i / ( f ) ) * ( max( ( ( j / ( j + k ) ) * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * l ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * ( 1 - j / ( l - k ) ) , 0.0001 ) ) / ( ( j / ( j + k ) ) * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * l ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * ( ( j / ( j + k ) ) * n / ( o ) ) ) / ( ( ( j / ( j + k ) ) * n / ( o ) ) + ( ( 1 - ( j / ( j + k ) ) ) * n / ( o ) ) + ( ( 10 ) * r / ( o ) ) ) ) / ( ( p / ( o ) ) + ( q / ( o ) ) + ( n / ( o ) + ( 10 ) * r / ( o ) ) + ( ( 3 ) * s / ( o ) ) + ( t / ( o ) ) + ( u / ( o ) ) ) + ( z / ( a_a if smt_on else ( o ) ) / 3.3 ) ) ) ) - ( 100 * ( ( ( 5 ) * m - e ) / ( f ) ) * ( ( q / ( o ) ) + ( p / ( o ) ) + ( ( 10 ) * r / ( o ) ) ) / ( ( p / ( o ) ) + ( q / ( o ) ) + ( n / ( o ) + ( 10 ) * r / ( o ) ) + ( ( 3 ) * s / ( o ) ) + ( t / ( o ) ) + ( u / ( o ) ) ) )", + "BaseFormula": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) * tma_mispredicts_resteers ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_ms ) ) ) - tma_bottleneck_big_code", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Instruction_Fetch_BW" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Instruction_Fetch_BW > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvFB;Fed;FetchBW;Frontend", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Data_Cache_Memory_Bandwidth", + "LegacyName": "metric_TMA_Bottleneck_Data_Cache_Memory_Bandwidth", + "Level": 1, + "BriefDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Alias": "a" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "a_a" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "a_b" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Alias": "a_c" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", + "Alias": "a_d" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Alias": "a_e" + }, + { + "Name": "L1D_PEND_MISS.FB_FULL", + "Alias": "a_f" + }, + { + "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", + "Alias": "a_g" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a_h" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "a_i" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "a_j" + }, + { + "Name": "LD_BLOCKS.STORE_FORWARD", + "Alias": "a_k" + }, + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "a_l" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "a_m" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "a_n" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a_p" + }, + { + "Name": "L2_RQSTS.ALL_RFO", + "Alias": "a_q" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "a_r" + }, + { + "Name": "L2_RQSTS.RFO_HIT", + "Alias": "a_s" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "a_t" + }, + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a_u" + }, + { + "Name": "LD_BLOCKS.NO_SR", + "Alias": "a_v" + }, + { + "Name": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "Alias": "a_w" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "b" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "c" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "g" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "h" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "i" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "j" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "k" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L3_MISS", + "Alias": "l" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "m" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "Alias": "n" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "Alias": "o" + }, + { + "Name": "MEM_LOAD_RETIRED.L2_HIT", + "Alias": "p" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "q" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "r" + }, + { + "Name": "L1D_PEND_MISS.FB_FULL_PERIODS", + "Alias": "s" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Alias": "t" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "u" + }, + { + "Name": "L1D_PEND_MISS.L2_STALL", + "Alias": "v" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "w" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": "20", + "Alias": "dependentloadsweight" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + }, + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "x" + } + ], + "Formula": "100 * ( ( ( ( ( a + b ) / ( c + ( d + ( e / ( f + g + e + h ) ) * i ) + b ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) ) * ( ( ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) / ( ( max( ( a - n ) / ( m ) , 0 ) ) + ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) + ( ( o - l ) / ( m ) ) + ( ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) + ( b / ( m ) ) ) ) * ( ( ( min( m , t ) ) / ( m ) ) / ( ( ( min( m , t ) ) / ( m ) ) + ( ( min( m , u ) ) / ( m ) - ( ( min( m , t ) ) / ( m ) ) ) ) ) ) + ( ( ( ( a + b ) / ( c + ( d + ( e / ( f + g + e + h ) ) * i ) + b ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) ) * ( ( ( o - l ) / ( m ) ) / ( ( max( ( a - n ) / ( m ) , 0 ) ) + ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) + ( ( o - l ) / ( m ) ) + ( ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) + ( b / ( m ) ) ) ) * ( ( v / ( m ) ) / ( ( ( ( ( 48 * ( ( ( m ) / w ) * x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( m ) / w ) * x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( z * ( a_a / ( a_a + a_b ) ) ) + ( ( 47.5 * ( ( ( m ) / w ) * x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( m ) / w ) * x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_c ) ) * ( 1 + ( q / r ) / 2 ) / ( m ) ) + ( ( ( 47.5 * ( ( ( m ) / w ) * x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( m ) / w ) * x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_d + z * ( 1 - ( a_a / ( a_a + a_b ) ) ) ) * ( 1 + ( q / r ) / 2 ) / ( m ) ) + ( ( ( 23 * ( ( ( m ) / w ) * x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( m ) / w ) * x / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_e * ( 1 + ( q / r ) / 2 ) ) / ( m ) ) + ( v / ( m ) ) ) ) ) + ( ( ( ( a + b ) / ( c + ( d + ( e / ( f + g + e + h ) ) * i ) + b ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) ) * ( ( max( ( a - n ) / ( m ) , 0 ) ) / ( ( max( ( a - n ) / ( m ) , 0 ) ) + ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) + ( ( o - l ) / ( m ) ) + ( ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) + ( b / ( m ) ) ) ) * ( ( a_f / ( m ) ) / ( ( min( ( 7 ) * a_g + a_h , max( a_i - a_j , 0 ) ) / ( m ) ) + ( 13 * a_k / ( m ) ) + ( min( 2 * ( a_l - a_m - a_n ) * dependentloadsweight / 100 , max( a_i - a_j , 0 ) ) / ( m ) ) + ( ( 16 * max( 0 , a_p - a_q ) + ( a_p / a_r ) * ( ( 10 ) * a_s + ( min( m , a_t ) ) ) ) / ( m ) ) + ( ( a_u / ( a_n + a_m ) ) * a_v / ( m ) ) + ( a_w / ( m ) ) + ( a_f / ( m ) ) ) ) ) )", + "BaseFormula": "100 * ( ( tma_memory_bound * ( tma_dram_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_mem_bandwidth / ( tma_mem_bandwidth + tma_mem_latency ) ) ) + ( tma_memory_bound * ( tma_l3_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_sq_full / ( tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full ) ) ) + ( tma_memory_bound * ( tma_l1_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_fb_full / ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_4k_aliasing + tma_fb_full ) ) ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Data_Cache_Memory_Bandwidth" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Data_Cache_Memory_Bandwidth > 20", + "ThresholdIssues": "$issueBW" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMB;Mem;MemoryBW;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Data_Cache_Memory_Latency", + "LegacyName": "metric_TMA_Bottleneck_Data_Cache_Memory_Latency", + "Level": 1, + "BriefDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Alias": "a" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "a_a" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "a_b" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Alias": "a_c" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", + "Alias": "a_d" + }, + { + "Name": "L1D_PEND_MISS.L2_STALL", + "Alias": "a_e" + }, + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "a_f" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "a_g" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "a_h" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "a_j" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "a_k" + }, + { + "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", + "Alias": "a_l" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a_m" + }, + { + "Name": "LD_BLOCKS.STORE_FORWARD", + "Alias": "a_n" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a_o" + }, + { + "Name": "L2_RQSTS.ALL_RFO", + "Alias": "a_p" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "a_q" + }, + { + "Name": "L2_RQSTS.RFO_HIT", + "Alias": "a_r" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "a_s" + }, + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a_t" + }, + { + "Name": "LD_BLOCKS.NO_SR", + "Alias": "a_u" + }, + { + "Name": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "Alias": "a_v" + }, + { + "Name": "L1D_PEND_MISS.FB_FULL", + "Alias": "a_w" + }, + { + "Name": "MEM_INST_RETIRED.SPLIT_STORES", + "Alias": "a_x" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "a_y" + }, + { + "Name": "OCR.DEMAND_RFO.L3_MISS:ocr_msr_val=0x103b800002", + "Alias": "a_z" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "b" + }, + { + "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "Alias": "b_a" + }, + { + "Name": "OCR.STREAMING_WR.ANY_RESPONSE", + "Alias": "b_b" + }, + { + "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", + "Alias": "b_c" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "b_d" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "c" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "g" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "h" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "i" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "j" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "k" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L3_MISS", + "Alias": "l" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "m" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "Alias": "n" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "Alias": "o" + }, + { + "Name": "MEM_LOAD_RETIRED.L2_HIT", + "Alias": "p" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "q" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "r" + }, + { + "Name": "L1D_PEND_MISS.FB_FULL_PERIODS", + "Alias": "s" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "t" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Alias": "u" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "v" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Alias": "y" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": "20", + "Alias": "dependentloadsweight" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + }, + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + }, + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "w" + } + ], + "Formula": "100 * ( ( ( ( ( a + b ) / ( c + ( d + ( e / ( f + g + e + h ) ) * i ) + b ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) ) * ( ( ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) / ( ( max( ( a - n ) / ( m ) , 0 ) ) + ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) + ( ( o - l ) / ( m ) ) + ( ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) + ( b / ( m ) ) ) ) * ( ( ( min( m , t ) ) / ( m ) - ( ( min( m , u ) ) / ( m ) ) ) / ( ( ( min( m , u ) ) / ( m ) ) + ( ( min( m , t ) ) / ( m ) - ( ( min( m , u ) ) / ( m ) ) ) ) ) ) + ( ( ( ( a + b ) / ( c + ( d + ( e / ( f + g + e + h ) ) * i ) + b ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) ) * ( ( ( o - l ) / ( m ) ) / ( ( max( ( a - n ) / ( m ) , 0 ) ) + ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) + ( ( o - l ) / ( m ) ) + ( ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) + ( b / ( m ) ) ) ) * ( ( ( ( 23 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( y * ( 1 + ( q / r ) / 2 ) ) / ( m ) ) / ( ( ( ( ( 48 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( z * ( a_a / ( a_a + a_b ) ) ) + ( ( 47.5 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_c ) ) * ( 1 + ( q / r ) / 2 ) / ( m ) ) + ( ( ( 47.5 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_d + z * ( 1 - ( a_a / ( a_a + a_b ) ) ) ) * ( 1 + ( q / r ) / 2 ) / ( m ) ) + ( ( ( 23 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( y * ( 1 + ( q / r ) / 2 ) ) / ( m ) ) + ( a_e / ( m ) ) ) ) ) + ( ( ( ( a + b ) / ( c + ( d + ( e / ( f + g + e + h ) ) * i ) + b ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) ) * ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) / ( ( max( ( a - n ) / ( m ) , 0 ) ) + ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) + ( ( o - l ) / ( m ) ) + ( ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) + ( b / ( m ) ) ) ) + ( ( ( ( a + b ) / ( c + ( d + ( e / ( f + g + e + h ) ) * i ) + b ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) ) * ( ( max( ( a - n ) / ( m ) , 0 ) ) / ( ( max( ( a - n ) / ( m ) , 0 ) ) + ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) + ( ( o - l ) / ( m ) ) + ( ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) + ( b / ( m ) ) ) ) * ( ( min( 2 * ( a_f - a_g - a_h ) * dependentloadsweight / 100 , max( a_j - a_k , 0 ) ) / ( m ) ) / ( ( min( ( 7 ) * a_l + a_m , max( a_j - a_k , 0 ) ) / ( m ) ) + ( 13 * a_n / ( m ) ) + ( min( 2 * ( a_f - a_g - a_h ) * dependentloadsweight / 100 , max( a_j - a_k , 0 ) ) / ( m ) ) + ( ( 16 * max( 0 , a_o - a_p ) + ( a_o / a_q ) * ( ( 10 ) * a_r + ( min( m , a_s ) ) ) ) / ( m ) ) + ( ( a_t / ( a_h + a_g ) ) * a_u / ( m ) ) + ( a_v / ( m ) ) + ( a_w / ( m ) ) ) ) ) + ( ( ( ( a + b ) / ( c + ( d + ( e / ( f + g + e + h ) ) * i ) + b ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) ) * ( ( max( ( a - n ) / ( m ) , 0 ) ) / ( ( max( ( a - n ) / ( m ) , 0 ) ) + ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) + ( ( o - l ) / ( m ) ) + ( ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) + ( b / ( m ) ) ) ) * ( ( ( 16 * max( 0 , a_o - a_p ) + ( a_o / a_q ) * ( ( 10 ) * a_r + ( min( m , a_s ) ) ) ) / ( m ) ) / ( ( min( ( 7 ) * a_l + a_m , max( a_j - a_k , 0 ) ) / ( m ) ) + ( 13 * a_n / ( m ) ) + ( min( 2 * ( a_f - a_g - a_h ) * dependentloadsweight / 100 , max( a_j - a_k , 0 ) ) / ( m ) ) + ( ( 16 * max( 0 , a_o - a_p ) + ( a_o / a_q ) * ( ( 10 ) * a_r + ( min( m , a_s ) ) ) ) / ( m ) ) + ( ( a_t / ( a_h + a_g ) ) * a_u / ( m ) ) + ( a_v / ( m ) ) + ( a_w / ( m ) ) ) ) ) + ( ( ( ( a + b ) / ( c + ( d + ( e / ( f + g + e + h ) ) * i ) + b ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) ) * ( ( max( ( a - n ) / ( m ) , 0 ) ) / ( ( max( ( a - n ) / ( m ) , 0 ) ) + ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) + ( ( o - l ) / ( m ) ) + ( ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) + ( b / ( m ) ) ) ) * ( ( ( a_t / ( a_h + a_g ) ) * a_u / ( m ) ) / ( ( min( ( 7 ) * a_l + a_m , max( a_j - a_k , 0 ) ) / ( m ) ) + ( 13 * a_n / ( m ) ) + ( min( 2 * ( a_f - a_g - a_h ) * dependentloadsweight / 100 , max( a_j - a_k , 0 ) ) / ( m ) ) + ( ( 16 * max( 0 , a_o - a_p ) + ( a_o / a_q ) * ( ( 10 ) * a_r + ( min( m , a_s ) ) ) ) / ( m ) ) + ( ( a_t / ( a_h + a_g ) ) * a_u / ( m ) ) + ( a_v / ( m ) ) + ( a_w / ( m ) ) ) ) ) + ( ( ( ( a + b ) / ( c + ( d + ( e / ( f + g + e + h ) ) * i ) + b ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) ) * ( ( b / ( m ) ) / ( ( max( ( a - n ) / ( m ) , 0 ) ) + ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) + ( ( o - l ) / ( m ) ) + ( ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) + ( b / ( m ) ) ) ) * ( ( a_x / ( a_y if smt_on else ( m ) ) ) / ( ( ( ( a_r * ( 10 ) * ( 1 - ( a_o / a_q ) ) ) + ( 1 - ( a_o / a_q ) ) * ( min( m , a_s ) ) ) / ( m ) ) + ( ( ( 120 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_z + ( 48 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_a ) / ( m ) ) + ( a_x / ( a_y if smt_on else ( m ) ) ) + ( 9 * b_b / ( m ) ) + ( ( ( 7 ) * b_c + b_d ) / ( a_y if smt_on else ( m ) ) ) ) ) ) + ( ( ( ( a + b ) / ( c + ( d + ( e / ( f + g + e + h ) ) * i ) + b ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) ) * ( ( b / ( m ) ) / ( ( max( ( a - n ) / ( m ) , 0 ) ) + ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) + ( ( o - l ) / ( m ) ) + ( ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) + ( b / ( m ) ) ) ) * ( ( ( ( a_r * ( 10 ) * ( 1 - ( a_o / a_q ) ) ) + ( 1 - ( a_o / a_q ) ) * ( min( m , a_s ) ) ) / ( m ) ) / ( ( ( ( a_r * ( 10 ) * ( 1 - ( a_o / a_q ) ) ) + ( 1 - ( a_o / a_q ) ) * ( min( m , a_s ) ) ) / ( m ) ) + ( ( ( 120 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_z + ( 48 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_a ) / ( m ) ) + ( a_x / ( a_y if smt_on else ( m ) ) ) + ( 9 * b_b / ( m ) ) + ( ( ( 7 ) * b_c + b_d ) / ( a_y if smt_on else ( m ) ) ) ) ) ) )", + "BaseFormula": "100 * ( ( tma_memory_bound * ( tma_dram_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_mem_latency / ( tma_mem_bandwidth + tma_mem_latency ) ) ) + ( tma_memory_bound * ( tma_l3_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_l3_hit_latency / ( tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full ) ) ) + ( tma_memory_bound * tma_l2_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) + ( tma_memory_bound * ( tma_l1_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_l1_latency_dependency / ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_4k_aliasing + tma_fb_full ) ) ) + ( tma_memory_bound * ( tma_l1_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_lock_latency / ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_4k_aliasing + tma_fb_full ) ) ) + ( tma_memory_bound * ( tma_l1_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_split_loads / ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_4k_aliasing + tma_fb_full ) ) ) + ( tma_memory_bound * ( tma_store_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_split_stores / ( tma_store_latency + tma_false_sharing + tma_split_stores + tma_streaming_stores + tma_dtlb_store ) ) ) + ( tma_memory_bound * ( tma_store_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_store_latency / ( tma_store_latency + tma_false_sharing + tma_split_stores + tma_streaming_stores + tma_dtlb_store ) ) ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Data_Cache_Memory_Latency" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Data_Cache_Memory_Latency > 20", + "ThresholdIssues": "$issueLat" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvML;Mem;MemoryLat;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Memory_Data_TLBs", + "LegacyName": "metric_TMA_Bottleneck_Memory_Data_TLBs", + "Level": 1, + "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "a_a" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a_c" + }, + { + "Name": "L2_RQSTS.ALL_RFO", + "Alias": "a_d" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "a_e" + }, + { + "Name": "L2_RQSTS.RFO_HIT", + "Alias": "a_f" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "a_g" + }, + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a_h" + }, + { + "Name": "LD_BLOCKS.NO_SR", + "Alias": "a_i" + }, + { + "Name": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "Alias": "a_j" + }, + { + "Name": "L1D_PEND_MISS.FB_FULL", + "Alias": "a_k" + }, + { + "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", + "Alias": "a_l" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a_m" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "a_n" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a_o" + }, + { + "Name": "OCR.DEMAND_RFO.L3_MISS:ocr_msr_val=0x103b800002", + "Alias": "a_r" + }, + { + "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "Alias": "a_s" + }, + { + "Name": "MEM_INST_RETIRED.SPLIT_STORES", + "Alias": "a_t" + }, + { + "Name": "OCR.STREAMING_WR.ANY_RESPONSE", + "Alias": "a_u" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "b" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "c" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "g" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "h" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "i" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "j" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "k" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "Alias": "l" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "m" + }, + { + "Name": "MEM_LOAD_RETIRED.L2_HIT", + "Alias": "n" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "o" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "p" + }, + { + "Name": "L1D_PEND_MISS.FB_FULL_PERIODS", + "Alias": "q" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "Alias": "r" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L3_MISS", + "Alias": "s" + }, + { + "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", + "Alias": "t" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "u" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "v" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "w" + }, + { + "Name": "LD_BLOCKS.STORE_FORWARD", + "Alias": "x" + }, + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "y" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "a_p" + }, + { + "Name": "20", + "Alias": "dependentloadsweight" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + }, + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( ( ( a + b ) / ( c + ( d + ( e / ( f + g + e + h ) ) * i ) + b ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) ) * ( ( max( ( a - l ) / ( m ) , 0 ) ) / max( ( ( ( a + b ) / ( c + ( d + ( e / ( f + g + e + h ) ) * i ) + b ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) ) , ( ( max( ( a - l ) / ( m ) , 0 ) ) + ( ( ( n * ( 1 + ( o / p ) ) ) / ( ( n * ( 1 + ( o / p ) ) ) + q ) ) * ( ( l - r ) / ( m ) ) ) + ( ( r - s ) / ( m ) ) + ( ( s / ( m ) + ( ( l - r ) / ( m ) ) - ( ( ( n * ( 1 + ( o / p ) ) ) / ( ( n * ( 1 + ( o / p ) ) ) + q ) ) * ( ( l - r ) / ( m ) ) ) ) ) + ( b / ( m ) ) ) ) ) * ( ( min( ( 7 ) * t + u , max( v - w , 0 ) ) / ( m ) ) / max( ( max( ( a - l ) / ( m ) , 0 ) ) , ( ( min( ( 7 ) * t + u , max( v - w , 0 ) ) / ( m ) ) + ( 13 * x / ( m ) ) + ( min( 2 * ( y - z - a_a ) * dependentloadsweight / 100 , max( v - w , 0 ) ) / ( m ) ) + ( ( 16 * max( 0 , a_c - a_d ) + ( a_c / a_e ) * ( ( 10 ) * a_f + ( min( m , a_g ) ) ) ) / ( m ) ) + ( ( a_h / ( a_a + z ) ) * a_i / ( m ) ) + ( a_j / ( m ) ) + ( a_k / ( m ) ) ) ) ) + ( ( ( ( a + b ) / ( c + ( d + ( e / ( f + g + e + h ) ) * i ) + b ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) ) * ( ( b / ( m ) ) / ( ( max( ( a - l ) / ( m ) , 0 ) ) + ( ( ( n * ( 1 + ( o / p ) ) ) / ( ( n * ( 1 + ( o / p ) ) ) + q ) ) * ( ( l - r ) / ( m ) ) ) + ( ( r - s ) / ( m ) ) + ( ( s / ( m ) + ( ( l - r ) / ( m ) ) - ( ( ( n * ( 1 + ( o / p ) ) ) / ( ( n * ( 1 + ( o / p ) ) ) + q ) ) * ( ( l - r ) / ( m ) ) ) ) ) + ( b / ( m ) ) ) ) * ( ( ( ( 7 ) * a_l + a_m ) / ( a_n if smt_on else ( m ) ) ) / ( ( ( ( a_f * ( 10 ) * ( 1 - ( a_c / a_e ) ) ) + ( 1 - ( a_c / a_e ) ) * ( min( m , a_g ) ) ) / ( m ) ) + ( ( ( 120 * ( ( ( m ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_r + ( 48 * ( ( ( m ) / a_o ) * a_p / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_s ) / ( m ) ) + ( a_t / ( a_n if smt_on else ( m ) ) ) + ( 9 * a_u / ( m ) ) + ( ( ( 7 ) * a_l + a_m ) / ( a_n if smt_on else ( m ) ) ) ) ) ) )", + "BaseFormula": "100 * ( tma_memory_bound * ( tma_l1_bound / max( tma_memory_bound , ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) ) * ( tma_dtlb_load / max( tma_l1_bound , ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_4k_aliasing + tma_fb_full ) ) ) + ( tma_memory_bound * ( tma_store_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_dtlb_store / ( tma_store_latency + tma_false_sharing + tma_split_stores + tma_streaming_stores + tma_dtlb_store ) ) ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Memory_Data_TLBs" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Memory_Data_TLBs > 20", + "ThresholdIssues": "$issueTLB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMT;Mem;MemoryTLB;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Memory_Synchronization", + "LegacyName": "metric_TMA_Bottleneck_Memory_Synchronization", + "Level": 1, + "BriefDescription": "Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", + "Alias": "a_a" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "Alias": "a_b" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", + "Alias": "a_c" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "a_d" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "a_e" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Alias": "a_f" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", + "Alias": "a_g" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Alias": "a_h" + }, + { + "Name": "L1D_PEND_MISS.L2_STALL", + "Alias": "a_i" + }, + { + "Name": "OCR.DEMAND_RFO.L3_MISS:ocr_msr_val=0x103b800002", + "Alias": "a_j" + }, + { + "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "Alias": "a_k" + }, + { + "Name": "L2_RQSTS.RFO_HIT", + "Alias": "a_l" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a_m" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "a_n" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "a_o" + }, + { + "Name": "MEM_INST_RETIRED.SPLIT_STORES", + "Alias": "a_p" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "a_q" + }, + { + "Name": "OCR.STREAMING_WR.ANY_RESPONSE", + "Alias": "a_r" + }, + { + "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", + "Alias": "a_s" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a_t" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "a_u" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "a_v" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "a_w" + }, + { + "Name": "MACHINE_CLEARS.MEMORY_ORDERING", + "Alias": "a_x" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "b" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "c" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "g" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "h" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "i" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "j" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "k" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L3_MISS", + "Alias": "l" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "m" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "Alias": "n" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "Alias": "o" + }, + { + "Name": "MEM_LOAD_RETIRED.L2_HIT", + "Alias": "p" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "q" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "r" + }, + { + "Name": "L1D_PEND_MISS.FB_FULL_PERIODS", + "Alias": "s" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "t" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Alias": "u" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "v" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Alias": "y" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + }, + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + }, + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "w" + } + ], + "Formula": "100 * ( ( ( ( a + b ) / ( c + ( d + ( e / ( f + g + e + h ) ) * i ) + b ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) ) * ( ( ( ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) / ( ( max( ( a - n ) / ( m ) , 0 ) ) + ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) + ( ( o - l ) / ( m ) ) + ( ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) + ( b / ( m ) ) ) ) * ( ( ( min( m , t ) ) / ( m ) - ( ( min( m , u ) ) / ( m ) ) ) / ( ( ( min( m , u ) ) / ( m ) ) + ( ( min( m , t ) ) / ( m ) - ( ( min( m , u ) ) / ( m ) ) ) ) ) * ( ( ( ( 120 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 23 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * y + ( ( 120 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 23 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * z ) * ( 1 + ( q / r ) / 2 ) / ( m ) ) / ( ( ( ( 66.5 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 23 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * a_a * ( 1 + ( q / r ) / 2 ) / ( m ) ) + ( ( ( 131 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 23 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * a_b * ( 1 + ( q / r ) / 2 ) / ( m ) ) + ( ( ( ( 120 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 23 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * y + ( ( 120 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 23 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * z ) * ( 1 + ( q / r ) / 2 ) / ( m ) ) ) + ( ( ( o - l ) / ( m ) ) / ( ( max( ( a - n ) / ( m ) , 0 ) ) + ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) + ( ( o - l ) / ( m ) ) + ( ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) + ( b / ( m ) ) ) ) * ( ( ( ( ( 48 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_c * ( a_d / ( a_d + a_e ) ) ) + ( ( 47.5 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_f ) ) * ( 1 + ( q / r ) / 2 ) / ( m ) ) + ( ( ( 47.5 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_g + a_c * ( 1 - ( a_d / ( a_d + a_e ) ) ) ) * ( 1 + ( q / r ) / 2 ) / ( m ) ) ) / ( ( ( ( ( 48 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_c * ( a_d / ( a_d + a_e ) ) ) + ( ( 47.5 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_f ) ) * ( 1 + ( q / r ) / 2 ) / ( m ) ) + ( ( ( 47.5 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_g + a_c * ( 1 - ( a_d / ( a_d + a_e ) ) ) ) * ( 1 + ( q / r ) / 2 ) / ( m ) ) + ( ( ( 23 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_h * ( 1 + ( q / r ) / 2 ) ) / ( m ) ) + ( a_i / ( m ) ) ) + ( ( b / ( m ) ) / ( ( max( ( a - n ) / ( m ) , 0 ) ) + ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) + ( ( o - l ) / ( m ) ) + ( ( l / ( m ) + ( ( n - o ) / ( m ) ) - ( ( ( p * ( 1 + ( q / r ) ) ) / ( ( p * ( 1 + ( q / r ) ) ) + s ) ) * ( ( n - o ) / ( m ) ) ) ) ) + ( b / ( m ) ) ) ) * ( ( ( 120 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_j + ( 48 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_k ) / ( m ) ) / ( ( ( ( ( a_l * ( 10 ) * ( 1 - ( a_m / a_n ) ) ) + ( 1 - ( a_m / a_n ) ) * ( min( m , a_o ) ) ) / ( m ) ) + ( ( ( 120 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_j + ( 48 * ( ( ( m ) / v ) * w / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_k ) / ( m ) ) + ( a_p / ( a_q if smt_on else ( m ) ) ) + ( 9 * a_r / ( m ) ) + ( ( ( 7 ) * a_s + a_t ) / ( a_q if smt_on else ( m ) ) ) ) - ( ( ( a_l * ( 10 ) * ( 1 - ( a_m / a_n ) ) ) + ( 1 - ( a_m / a_n ) ) * ( min( m , a_o ) ) ) / ( m ) ) ) ) + ( max( 0 , ( max( 1 - ( ( f / ( f + g + e + h ) - a_u / ( k ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) - ( ( a_v / ( a_v + a_w ) ) * ( max( 1 - ( ( f / ( f + g + e + h ) - a_u / ( k ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( f / ( f + g + e + h ) - a_u / ( k ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) - ( ( a_v / ( a_v + a_w ) ) * ( max( 1 - ( ( f / ( f + g + e + h ) - a_u / ( k ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) ) ) ) * ( 1 - a_x / a_w ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( f / ( f + g + e + h ) - a_u / ( k ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) - ( ( a_v / ( a_v + a_w ) ) * ( max( 1 - ( ( f / ( f + g + e + h ) - a_u / ( k ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) ) ) ) * ( 1 - a_x / a_w ) , 0.0001 ) ) ) ) )", + "BaseFormula": "100 * ( tma_memory_bound * ( ( tma_dram_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_mem_latency / ( tma_mem_bandwidth + tma_mem_latency ) ) * tma_remote_cache / ( tma_local_mem + tma_remote_mem + tma_remote_cache ) + ( tma_l3_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_contested_accesses + tma_data_sharing ) / ( tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full ) + ( tma_store_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * tma_false_sharing / ( ( tma_store_latency + tma_false_sharing + tma_split_stores + tma_streaming_stores + tma_dtlb_store ) - tma_store_latency ) ) + tma_machine_clears * ( 1 - tma_other_nukes / ( tma_other_nukes ) ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Memory_Synchronization" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_Bottleneck_Memory_Synchronization > 10", + "ThresholdIssues": "$issueSyncxn" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMS;LockCont;Mem;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Compute_Bound_Est", + "LegacyName": "metric_TMA_Bottleneck_Compute_Bound_Est", + "Level": 1, + "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Alias": "g" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "h" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "i" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "k" + }, + { + "Name": "ARITH.DIVIDER_ACTIVE", + "Alias": "l" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "m" + }, + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "n" + }, + { + "Name": "EXE_ACTIVITY.3_PORTS_UTIL:u0x80", + "Alias": "o" + }, + { + "Name": "UOPS_EXECUTED.CYCLES_GE_3", + "Alias": "p" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( max( 0 , ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) - ( ( ( g + h ) / ( i + ( j + ( d / ( b + c + d + a ) ) * k ) + h ) ) * ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) ) ) ) * ( l / ( m ) ) / ( ( l / ( m ) ) + ( n / ( m ) ) + ( ( ( o / ( m ) ) * ( m ) + ( j + ( d / ( b + c + d + a ) ) * k ) ) / ( m ) if ( l < ( i - g ) ) else ( j + ( d / ( b + c + d + a ) ) * k ) / ( m ) ) ) ) + ( ( max( 0 , ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) - ( ( ( g + h ) / ( i + ( j + ( d / ( b + c + d + a ) ) * k ) + h ) ) * ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) ) ) ) * ( ( ( ( o / ( m ) ) * ( m ) + ( j + ( d / ( b + c + d + a ) ) * k ) ) / ( m ) if ( l < ( i - g ) ) else ( j + ( d / ( b + c + d + a ) ) * k ) / ( m ) ) / ( ( l / ( m ) ) + ( n / ( m ) ) + ( ( ( o / ( m ) ) * ( m ) + ( j + ( d / ( b + c + d + a ) ) * k ) ) / ( m ) if ( l < ( i - g ) ) else ( j + ( d / ( b + c + d + a ) ) * k ) / ( m ) ) ) ) * ( ( p / ( m ) ) / ( ( o / ( m ) ) + ( j / ( m ) ) + ( k / ( m ) ) + ( p / ( m ) ) ) ) ) )", + "BaseFormula": "100 * ( ( tma_core_bound * tma_divider / ( tma_divider + tma_serializing_operation + tma_ports_utilization ) ) + ( tma_core_bound * ( tma_ports_utilization / ( tma_divider + tma_serializing_operation + tma_ports_utilization ) ) * ( tma_ports_utilized_3m / ( tma_ports_utilized_0 + tma_ports_utilized_1 + tma_ports_utilized_2 + tma_ports_utilized_3m ) ) ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Compute_Bound_Est" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Compute_Bound_Est > 20", + "ThresholdIssues": "$issueComp" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvCB;Cor", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Irregular_Overhead", + "LegacyName": "metric_TMA_Bottleneck_Irregular_Overhead", + "Level": 1, + "BriefDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "a_a" + }, + { + "Name": "MACHINE_CLEARS.MEMORY_ORDERING", + "Alias": "a_b" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Alias": "a_c" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "a_d" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "a_e" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "a_f" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "a_g" + }, + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "a_h" + }, + { + "Name": "RS_EVENTS.EMPTY_CYCLES", + "Alias": "a_i" + }, + { + "Name": "EXE_ACTIVITY.3_PORTS_UTIL:u0x80", + "Alias": "a_j" + }, + { + "Name": "ARITH.DIVIDER_ACTIVE", + "Alias": "a_k" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "g" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "h" + }, + { + "Name": "UOPS_DECODED.DEC0", + "Alias": "i" + }, + { + "Name": "UOPS_DECODED.DEC0:c1", + "Alias": "j" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "k" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "l" + }, + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "m" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "n" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "o" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "p" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "q" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "r" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "s" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "t" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "u" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "v" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "w" + }, + { + "Name": "DECODE.LCP", + "Alias": "x" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "y" + }, + { + "Name": "IDQ.MS_UOPS:c1", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( ( ( ( ( a / b ) * c / ( d ) ) / ( ( ( ( ( a / b ) * c / ( d ) ) + ( e / ( f + g + e + h ) ) * ( i - j ) / k ) - ( ( a / b ) * c / ( d ) ) ) + ( ( a / b ) * c / ( d ) ) ) ) * ( ( ( 34 ) * l / ( d ) ) / ( ( a / b ) * c / ( d ) ) ) ) * ( ( ( ( 5 ) * m - n ) / ( d ) ) * ( ( ( 3 ) * o / ( p ) ) + ( q / ( p ) + ( 10 ) * r / ( p ) ) * ( ( ( 1 - ( s / ( s + t ) ) ) * q / ( p ) ) + ( 10 * ( ( a / b ) * c / ( d ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( f / ( f + g + e + h ) - n / ( d ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( f / ( f + g + e + h ) - n / ( d ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) ) ) * ( ( s / ( s + t ) ) * q / ( p ) ) ) / ( ( ( s / ( s + t ) ) * q / ( p ) ) + ( ( 1 - ( s / ( s + t ) ) ) * q / ( p ) ) + ( ( 10 ) * r / ( p ) ) ) ) / ( ( v / ( p ) ) + ( w / ( p ) ) + ( q / ( p ) + ( 10 ) * r / ( p ) ) + ( ( 3 ) * o / ( p ) ) + ( x / ( p ) ) + ( y / ( p ) ) ) + ( z / ( a_a if smt_on else ( p ) ) / 3.3 ) ) ) + ( 10 * ( ( a / b ) * c / ( d ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( f / ( f + g + e + h ) - n / ( d ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( f / ( f + g + e + h ) - n / ( d ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) ) ) * ( ( s / ( s + t ) ) * ( max( 1 - ( ( f / ( f + g + e + h ) - n / ( d ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) ) + ( ( max( 0 , ( max( 1 - ( ( f / ( f + g + e + h ) - n / ( d ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( f / ( f + g + e + h ) - n / ( d ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( f / ( f + g + e + h ) - n / ( d ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( f / ( f + g + e + h ) - n / ( d ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) ) ) ) * ( 1 - a_b / t ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( f / ( f + g + e + h ) - n / ( d ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( f / ( f + g + e + h ) - n / ( d ) ) + ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) + ( e / ( f + g + e + h ) ) ) , 0 ) ) ) ) ) * ( 1 - a_b / t ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) - ( ( ( a_c + a_d ) / ( a_e + ( a_f + ( e / ( f + g + e + h ) ) * a_g ) + a_d ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) ) ) ) * ( ( a_h / ( p ) ) + ( max( 0 , ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) - ( ( ( a_c + a_d ) / ( a_e + ( a_f + ( e / ( f + g + e + h ) ) * a_g ) + a_d ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * u ) / ( d ) ) ) ) ) * a_i / ( p ) * ( a_j / ( p ) ) ) / ( ( a_k / ( p ) ) + ( a_h / ( p ) ) + ( ( ( a_j / ( p ) ) * ( p ) + ( a_f + ( e / ( f + g + e + h ) ) * a_g ) ) / ( p ) if ( a_k < ( a_e - a_c ) ) else ( a_f + ( e / ( f + g + e + h ) ) * a_g ) / ( p ) ) ) ) + ( ( ( ( ( a / b ) * c / ( d ) ) / ( ( ( ( ( a / b ) * c / ( d ) ) + ( e / ( f + g + e + h ) ) * ( i - j ) / k ) - ( ( a / b ) * c / ( d ) ) ) + ( ( a / b ) * c / ( d ) ) ) ) * ( ( ( 34 ) * l / ( d ) ) / ( ( a / b ) * c / ( d ) ) ) ) * ( ( ( a / b ) * c / ( d ) ) + ( e / ( f + g + e + h ) ) * ( i - j ) / k ) ) )", + "BaseFormula": "100 * ( ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) * tma_mispredicts_resteers ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_ms ) ) + ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) * tma_branch_mispredicts + ( tma_machine_clears * tma_other_nukes / ( tma_other_nukes ) ) + ( tma_core_bound * ( tma_serializing_operation + tma_core_bound * rs_events.empty_cycles / tma_info_thread_clks * tma_ports_utilized_0 ) / ( tma_divider + tma_serializing_operation + tma_ports_utilization ) ) + ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * tma_heavy_operations ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Irregular_Overhead" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_Bottleneck_Irregular_Overhead > 10", + "ThresholdIssues": "$issueMS" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BvIO;Cor;Ret", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Other_Bottlenecks", + "LegacyName": "metric_TMA_Bottleneck_Other_Bottlenecks", + "Level": 1, + "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end. Examples include data-dependencies (Core Bound when Low ILP) and other unlisted memory-related stalls.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "a_a" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Alias": "a_b" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "a_c" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "a_d" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "a_e" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "a_f" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L3_MISS", + "Alias": "a_g" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "Alias": "a_h" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "Alias": "a_i" + }, + { + "Name": "MEM_LOAD_RETIRED.L2_HIT", + "Alias": "a_j" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "a_k" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "a_l" + }, + { + "Name": "L1D_PEND_MISS.FB_FULL_PERIODS", + "Alias": "a_m" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Alias": "a_n" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "a_o" + }, + { + "Name": "L1D_PEND_MISS.L2_STALL", + "Alias": "a_p" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a_q" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", + "Alias": "a_t" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "a_u" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "a_v" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Alias": "a_w" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", + "Alias": "a_x" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Alias": "a_y" + }, + { + "Name": "L1D_PEND_MISS.FB_FULL", + "Alias": "a_z" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "b" + }, + { + "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", + "Alias": "b_a" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "b_b" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "b_c" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "b_d" + }, + { + "Name": "LD_BLOCKS.STORE_FORWARD", + "Alias": "b_e" + }, + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "b_f" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "b_g" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "b_h" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "b_j" + }, + { + "Name": "L2_RQSTS.ALL_RFO", + "Alias": "b_k" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "b_l" + }, + { + "Name": "L2_RQSTS.RFO_HIT", + "Alias": "b_m" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "b_n" + }, + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "b_o" + }, + { + "Name": "LD_BLOCKS.NO_SR", + "Alias": "b_p" + }, + { + "Name": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "Alias": "b_q" + }, + { + "Name": "MEM_INST_RETIRED.SPLIT_STORES", + "Alias": "b_r" + }, + { + "Name": "OCR.DEMAND_RFO.L3_MISS:ocr_msr_val=0x103b800002", + "Alias": "b_s" + }, + { + "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "Alias": "b_t" + }, + { + "Name": "OCR.STREAMING_WR.ANY_RESPONSE", + "Alias": "b_u" + }, + { + "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", + "Alias": "b_v" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "b_w" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Alias": "b_x" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "Alias": "b_y" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", + "Alias": "b_z" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "c" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "Alias": "c_a" + }, + { + "Name": "MACHINE_CLEARS.MEMORY_ORDERING", + "Alias": "c_b" + }, + { + "Name": "ARITH.DIVIDER_ACTIVE", + "Alias": "c_c" + }, + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "c_d" + }, + { + "Name": "EXE_ACTIVITY.3_PORTS_UTIL:u0x80", + "Alias": "c_e" + }, + { + "Name": "UOPS_EXECUTED.CYCLES_GE_3", + "Alias": "c_f" + }, + { + "Name": "RS_EVENTS.EMPTY_CYCLES", + "Alias": "c_g" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "c_h" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "c_i" + }, + { + "Name": "INST_RETIRED.NOP", + "Alias": "c_j" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "f" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "g" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "h" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "i" + }, + { + "Name": "DECODE.LCP", + "Alias": "j" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "k" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "l" + }, + { + "Name": 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a_c ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( a_c / ( e ) ) / ( ( max( ( a_b - a_h ) / ( e ) , 0 ) ) + ( ( ( a_j * ( 1 + ( a_k / a_l ) ) ) / ( ( a_j * ( 1 + ( a_k / a_l ) ) ) + a_m ) ) * ( ( a_h - a_i ) / ( e ) ) ) + ( ( a_i - a_g ) / ( e ) ) + ( ( a_g / ( e ) + ( ( a_h - a_i ) / ( e ) ) - ( ( ( a_j * ( 1 + ( a_k / a_l ) ) ) / ( ( a_j * ( 1 + ( a_k / a_l ) ) ) + a_m ) ) * ( ( a_h - a_i ) / ( e ) ) ) ) ) + ( a_c / ( e ) ) ) ) * ( ( b_r / ( a_a if smt_on else ( e ) ) ) / ( ( ( ( b_m * ( 10 ) * ( 1 - ( b_j / b_l ) ) ) + ( 1 - ( b_j / b_l ) ) * ( min( e , b_n ) ) ) / ( e ) ) + ( ( ( 120 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_s + ( 48 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_t ) / ( e ) ) + ( b_r / ( a_a if smt_on else ( e ) ) ) + ( 9 * b_u / ( e ) ) + ( ( ( 7 ) * b_v + b_w ) / ( a_a if smt_on else ( e ) ) ) ) ) ) + ( ( ( ( a_b + a_c ) / ( a_d + ( a_e + ( n / ( l + m + n + o ) ) * a_f ) + a_c ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( a_c / ( e ) ) / ( ( max( ( a_b - a_h ) / ( e ) , 0 ) ) + ( ( ( a_j * ( 1 + ( a_k / a_l ) ) ) / ( ( a_j * ( 1 + ( a_k / a_l ) ) ) + a_m ) ) * ( ( a_h - a_i ) / ( e ) ) ) + ( ( a_i - a_g ) / ( e ) ) + ( ( a_g / ( e ) + ( ( a_h - a_i ) / ( e ) ) - ( ( ( a_j * ( 1 + ( a_k / a_l ) ) ) / ( ( a_j * ( 1 + ( a_k / a_l ) ) ) + a_m ) ) * ( ( a_h - a_i ) / ( e ) ) ) ) ) + ( a_c / ( e ) ) ) ) * ( ( ( ( b_m * ( 10 ) * ( 1 - ( b_j / b_l ) ) ) + ( 1 - ( b_j / b_l ) ) * ( min( e , b_n ) ) ) / ( e ) ) / ( ( ( ( b_m * ( 10 ) * ( 1 - ( b_j / b_l ) ) ) + ( 1 - ( b_j / b_l ) ) * ( min( e , b_n ) ) ) / ( e ) ) + ( ( ( 120 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_s + ( 48 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_t ) / ( e ) ) + ( b_r / ( a_a if smt_on else ( e ) ) ) + ( 9 * b_u / ( e ) ) + ( ( ( 7 ) * b_v + b_w ) / ( a_a if smt_on else ( e ) ) ) ) ) ) ) ) + ( 100 * ( ( ( ( a_b + a_c ) / ( a_d + ( a_e + ( n / ( l + m + n + o ) ) * a_f ) + a_c ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( max( ( a_b - a_h ) / ( e ) , 0 ) ) / max( ( ( ( a_b + a_c ) / ( a_d + ( a_e + ( n / ( l + m + n + o ) ) * a_f ) + a_c ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) , ( ( max( ( a_b - a_h ) / ( e ) , 0 ) ) + ( ( ( a_j * ( 1 + ( a_k / a_l ) ) ) / ( ( a_j * ( 1 + ( a_k / a_l ) ) ) + a_m ) ) * ( ( a_h - a_i ) / ( e ) ) ) + ( ( a_i - a_g ) / ( e ) ) + ( ( a_g / ( e ) + ( ( a_h - a_i ) / ( e ) ) - ( ( ( a_j * ( 1 + ( a_k / a_l ) ) ) / ( ( a_j * ( 1 + ( a_k / a_l ) ) ) + a_m ) ) * ( ( a_h - a_i ) / ( e ) ) ) ) ) + ( a_c / ( e ) ) ) ) ) * ( ( min( ( 7 ) * b_a + b_b , max( b_c - b_d , 0 ) ) / ( e ) ) / max( ( max( ( a_b - a_h ) / ( e ) , 0 ) ) , ( ( min( ( 7 ) * b_a + b_b , max( b_c - b_d , 0 ) ) / ( e ) ) + ( 13 * b_e / ( e ) ) + ( min( 2 * ( b_f - b_g - b_h ) * dependentloadsweight / 100 , max( b_c - b_d , 0 ) ) / ( e ) ) + ( ( 16 * max( 0 , b_j - b_k ) + ( b_j / b_l ) * ( ( 10 ) * b_m + ( min( e , b_n ) ) ) ) / ( e ) ) + ( ( b_o / ( b_h + b_g ) ) * b_p / ( e ) ) + ( b_q / ( e ) ) + ( a_z / ( e ) ) ) ) ) + ( ( ( ( a_b + a_c ) / ( a_d + ( a_e + ( n / ( l + m + n + o ) ) * a_f ) + a_c ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( a_c / ( e ) ) / ( ( max( ( a_b - a_h ) / ( e ) , 0 ) ) + ( ( ( a_j * ( 1 + ( a_k / a_l ) ) ) / ( ( a_j * ( 1 + ( a_k / a_l ) ) ) + a_m ) ) * ( ( a_h - a_i ) / ( e ) ) ) + ( ( a_i - a_g ) / ( e ) ) + ( ( a_g / ( e ) + ( ( a_h - a_i ) / ( e ) ) - ( ( ( a_j * ( 1 + ( a_k / a_l ) ) ) / ( ( a_j * ( 1 + ( a_k / a_l ) ) ) + a_m ) ) * ( ( a_h - a_i ) / ( e ) ) ) ) ) + ( a_c / ( e ) ) ) ) * ( ( ( ( 7 ) * b_v + b_w ) / ( a_a if smt_on else ( e ) ) ) / ( ( ( ( b_m * ( 10 ) * ( 1 - ( b_j / b_l ) ) ) + ( 1 - ( b_j / b_l ) ) * ( min( e , b_n ) ) ) / ( e ) ) + ( ( ( 120 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_s + ( 48 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_t ) / ( e ) ) + ( b_r / ( a_a if smt_on else ( e ) ) ) + ( 9 * b_u / ( e ) ) + ( ( ( 7 ) * b_v + b_w ) / ( a_a if smt_on else ( e ) ) ) ) ) ) ) ) + ( 100 * ( ( ( ( a_b + a_c ) / ( a_d + ( a_e + ( n / ( l + m + n + o ) ) * a_f ) + a_c ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) * ( ( ( ( a_g / ( e ) + ( ( a_h - a_i ) / ( e ) ) - ( ( ( a_j * ( 1 + ( a_k / a_l ) ) ) / ( ( a_j * ( 1 + ( a_k / a_l ) ) ) + a_m ) ) * ( ( a_h - a_i ) / ( e ) ) ) ) ) / ( ( max( ( a_b - a_h ) / ( e ) , 0 ) ) + ( ( ( a_j * ( 1 + ( a_k / a_l ) ) ) / ( ( a_j * ( 1 + ( a_k / a_l ) ) ) + a_m ) ) * ( ( a_h - a_i ) / ( e ) ) ) + ( ( a_i - a_g ) / ( e ) ) + ( ( a_g / ( e ) + ( ( a_h - a_i ) / ( e ) ) - ( ( ( a_j * ( 1 + ( a_k / a_l ) ) ) / ( ( a_j * ( 1 + ( a_k / a_l ) ) ) + a_m ) ) * ( ( a_h - a_i ) / ( e ) ) ) ) ) + ( a_c / ( e ) ) ) ) * ( ( ( min( e , a_o ) ) / ( e ) - ( ( min( e , a_n ) ) / ( e ) ) ) / ( ( ( min( e , a_n ) ) / ( e ) ) + ( ( min( e , a_o ) ) / ( e ) - ( ( min( e , a_n ) ) / ( e ) ) ) ) ) * ( ( ( ( 120 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 23 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_x + ( ( 120 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 23 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_y ) * ( 1 + ( a_k / a_l ) / 2 ) / ( e ) ) / ( ( ( ( 66.5 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 23 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_z * ( 1 + ( a_k / a_l ) / 2 ) / ( e ) ) + ( ( ( 131 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 23 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * c_a * ( 1 + ( a_k / a_l ) / 2 ) / ( e ) ) + ( ( ( ( 120 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 23 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_x + ( ( 120 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 23 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_y ) * ( 1 + ( a_k / a_l ) / 2 ) / ( e ) ) ) + ( ( ( a_i - a_g ) / ( e ) ) / ( ( max( ( a_b - a_h ) / ( e ) , 0 ) ) + ( ( ( a_j * ( 1 + ( a_k / a_l ) ) ) / ( ( a_j * ( 1 + ( a_k / a_l ) ) ) + a_m ) ) * ( ( a_h - a_i ) / ( e ) ) ) + ( ( a_i - a_g ) / ( e ) ) + ( ( a_g / ( e ) + ( ( a_h - a_i ) / ( e ) ) - ( ( ( a_j * ( 1 + ( a_k / a_l ) ) ) / ( ( a_j * ( 1 + ( a_k / a_l ) ) ) + a_m ) ) * ( ( a_h - a_i ) / ( e ) ) ) ) ) + ( a_c / ( e ) ) ) ) * ( ( ( ( ( 48 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_t * ( a_u / ( a_u + a_v ) ) ) + ( ( 47.5 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_w ) ) * ( 1 + ( a_k / a_l ) / 2 ) / ( e ) ) + ( ( ( 47.5 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_x + a_t * ( 1 - ( a_u / ( a_u + a_v ) ) ) ) * ( 1 + ( a_k / a_l ) / 2 ) / ( e ) ) ) / ( ( ( ( ( 48 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_t * ( a_u / ( a_u + a_v ) ) ) + ( ( 47.5 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_w ) ) * ( 1 + ( a_k / a_l ) / 2 ) / ( e ) ) + ( ( ( 47.5 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_x + a_t * ( 1 - ( a_u / ( a_u + a_v ) ) ) ) * ( 1 + ( a_k / a_l ) / 2 ) / ( e ) ) + ( ( ( 23 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_y * ( 1 + ( a_k / a_l ) / 2 ) ) / ( e ) ) + ( a_p / ( e ) ) ) + ( ( a_c / ( e ) ) / ( ( max( ( a_b - a_h ) / ( e ) , 0 ) ) + ( ( ( a_j * ( 1 + ( a_k / a_l ) ) ) / ( ( a_j * ( 1 + ( a_k / a_l ) ) ) + a_m ) ) * ( ( a_h - a_i ) / ( e ) ) ) + ( ( a_i - a_g ) / ( e ) ) + ( ( a_g / ( e ) + ( ( a_h - a_i ) / ( e ) ) - ( ( ( a_j * ( 1 + ( a_k / a_l ) ) ) / ( ( a_j * ( 1 + ( a_k / a_l ) ) ) + a_m ) ) * ( ( a_h - a_i ) / ( e ) ) ) ) ) + ( a_c / ( e ) ) ) ) * ( ( ( 120 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_s + ( 48 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_t ) / ( e ) ) / ( ( ( ( ( b_m * ( 10 ) * ( 1 - ( b_j / b_l ) ) ) + ( 1 - ( b_j / b_l ) ) * ( min( e , b_n ) ) ) / ( e ) ) + ( ( ( 120 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_s + ( 48 * ( ( ( e ) / a_q ) * a_r / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_t ) / ( e ) ) + ( b_r / ( a_a if smt_on else ( e ) ) ) + ( 9 * b_u / ( e ) ) + ( ( ( 7 ) * b_v + b_w ) / ( a_a if smt_on else ( e ) ) ) ) - ( ( ( b_m * ( 10 ) * ( 1 - ( b_j / b_l ) ) ) + ( 1 - ( b_j / b_l ) ) * ( min( e , b_n ) ) ) / ( e ) ) ) ) + ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - c_b / t ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - c_b / t ) , 0.0001 ) ) ) ) ) ) + ( 100 * ( ( ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( a_b + a_c ) / ( a_d + ( a_e + ( n / ( l + m + n + o ) ) * a_f ) + a_c ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * ( c_c / ( e ) ) / ( ( c_c / ( e ) ) + ( c_d / ( e ) ) + ( ( ( c_e / ( e ) ) * ( e ) + ( a_e + ( n / ( l + m + n + o ) ) * a_f ) ) / ( e ) if ( c_c < ( a_d - a_b ) ) else ( a_e + ( n / ( l + m + n + o ) ) * a_f ) / ( e ) ) ) ) + ( ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( a_b + a_c ) / ( a_d + ( a_e + ( n / ( l + m + n + o ) ) * a_f ) + a_c ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * ( ( ( ( c_e / ( e ) ) * ( e ) + ( a_e + ( n / ( l + m + n + o ) ) * a_f ) ) / ( e ) if ( c_c < ( a_d - a_b ) ) else ( a_e + ( n / ( l + m + n + o ) ) * a_f ) / ( e ) ) / ( ( c_c / ( e ) ) + ( c_d / ( e ) ) + ( ( ( c_e / ( e ) ) * ( e ) + ( a_e + ( n / ( l + m + n + o ) ) * a_f ) ) / ( e ) if ( c_c < ( a_d - a_b ) ) else ( a_e + ( n / ( l + m + n + o ) ) * a_f ) / ( e ) ) ) ) * ( ( c_f / ( e ) ) / ( ( c_e / ( e ) ) + ( a_e / ( e ) ) + ( a_f / ( e ) ) + ( c_f / ( e ) ) ) ) ) ) ) + ( 100 * ( ( ( ( ( ( p / q ) * r / ( c ) ) / ( ( ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) - ( ( p / q ) * r / ( c ) ) ) + ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( 34 ) * y / ( c ) ) / ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( ( 5 ) * a - b ) / ( c ) ) * ( ( ( 3 ) * i / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) * ( ( ( 1 - ( s / ( s + t ) ) ) * h / ( e ) ) + ( 10 * ( ( p / q ) * r / ( c ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) * ( ( s / ( s + t ) ) * h / ( e ) ) ) / ( ( ( s / ( s + t ) ) * h / ( e ) ) + ( ( 1 - ( s / ( s + t ) ) ) * h / ( e ) ) + ( ( 10 ) * g / ( e ) ) ) ) / ( ( f / ( e ) ) + ( d / ( e ) ) + ( h / ( e ) + ( 10 ) * g / ( e ) ) + ( ( 3 ) * i / ( e ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) + ( z / ( a_a if smt_on else ( e ) ) / 3.3 ) ) ) + ( 10 * ( ( p / q ) * r / ( c ) ) * ( max( ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) * ( 1 - s / ( u - t ) ) , 0.0001 ) ) / ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) * ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) + ( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - c_b / t ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) - ( ( s / ( s + t ) ) * ( max( 1 - ( ( l / ( l + m + n + o ) - b / ( c ) ) + ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) + ( n / ( l + m + n + o ) ) ) , 0 ) ) ) ) ) * ( 1 - c_b / t ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( a_b + a_c ) / ( a_d + ( a_e + ( n / ( l + m + n + o ) ) * a_f ) + a_c ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * ( ( c_d / ( e ) ) + ( max( 0 , ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) - ( ( ( a_b + a_c ) / ( a_d + ( a_e + ( n / ( l + m + n + o ) ) * a_f ) + a_c ) ) * ( o / ( l + m + n + o ) + ( ( 5 ) * u ) / ( c ) ) ) ) ) * c_g / ( e ) * ( c_e / ( e ) ) ) / ( ( c_c / ( e ) ) + ( c_d / ( e ) ) + ( ( ( c_e / ( e ) ) * ( e ) + ( a_e + ( n / ( l + m + n + o ) ) * a_f ) ) / ( e ) if ( c_c < ( a_d - a_b ) ) else ( a_e + ( n / ( l + m + n + o ) ) * a_f ) / ( e ) ) ) ) + ( ( ( ( ( p / q ) * r / ( c ) ) / ( ( ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) - ( ( p / q ) * r / ( c ) ) ) + ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( 34 ) * y / ( c ) ) / ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) ) ) ) + ( 100 * ( ( c_h + 2 * c_i + c_j ) / ( c ) ) ) + ( 100 * ( ( n / ( l + m + n + o ) ) - ( ( c_h + 2 * c_i + c_j ) / ( c ) ) - ( ( ( ( ( p / q ) * r / ( c ) ) / ( ( ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) - ( ( p / q ) * r / ( c ) ) ) + ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( 34 ) * y / ( c ) ) / ( ( p / q ) * r / ( c ) ) ) ) * ( ( ( p / q ) * r / ( c ) ) + ( n / ( l + m + n + o ) ) * ( v - w ) / x ) ) ) ) )", + "BaseFormula": "100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_data_cache_memory_bandwidth + tma_bottleneck_data_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Other_Bottlenecks" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Other_Bottlenecks > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvOB;Cor;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Branching_Overhead", + "LegacyName": "metric_TMA_Bottleneck_Branching_Overhead", + "Level": 1, + "BriefDescription": "Total pipeline cost of instructions used for program control-flow - a subset of the Retiring category in TMA. Examples include function calls; loops and alignments. (A lower bound)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "b" + }, + { + "Name": "INST_RETIRED.NOP", + "Alias": "c" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + 2 * b + c ) / ( d ) )", + "BaseFormula": "100 * ( ( br_inst_retired.all_branches + 2 * br_inst_retired.near_call + inst_retired.nop ) / tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Branching_Overhead" + } + ], + "Formula": "a > 5", + "BaseFormula": "metric_TMA_Bottleneck_Branching_Overhead > 5", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvBO;Ret", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Useful_Work", + "LegacyName": "metric_TMA_Bottleneck_Useful_Work", + "Level": 1, + "BriefDescription": "Total pipeline cost of \"useful operations\" - the portion of Retiring category not covered by Branching_Overhead nor Irregular_Overhead.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "e" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "f" + }, + { + "Name": "INST_RETIRED.NOP", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "i" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "j" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "k" + }, + { + "Name": "UOPS_DECODED.DEC0", + "Alias": "l" + }, + { + "Name": "UOPS_DECODED.DEC0:c1", + "Alias": "m" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "n" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "o" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b + c + a + d ) ) - ( ( e + 2 * f + g ) / ( h ) ) - ( ( ( ( ( i / j ) * k / ( h ) ) / ( ( ( ( ( i / j ) * k / ( h ) ) + ( a / ( b + c + a + d ) ) * ( l - m ) / n ) - ( ( i / j ) * k / ( h ) ) ) + ( ( i / j ) * k / ( h ) ) ) ) * ( ( ( 34 ) * o / ( h ) ) / ( ( i / j ) * k / ( h ) ) ) ) * ( ( ( i / j ) * k / ( h ) ) + ( a / ( b + c + a + d ) ) * ( l - m ) / n ) ) )", + "BaseFormula": "100 * ( tma_retiring - ( ( br_inst_retired.all_branches + 2 * br_inst_retired.near_call + inst_retired.nop ) / tma_info_thread_slots ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * tma_heavy_operations ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Useful_Work" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Useful_Work > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvUW;Ret", + "LocateWith": "" + }, + { + "MetricName": "Frontend_Bound", + "LegacyName": "metric_TMA_Frontend_Bound(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( a + b + c + d ) - e / ( f ) )", + "BaseFormula": "perf_metrics.frontend_bound / ( perf_metrics.frontend_bound + perf_metrics.bad_speculation + perf_metrics.retiring + perf_metrics.backend_bound ) - int_misc.uop_dropping / tma_info_thread_slots", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 15", + "BaseFormula": "metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvFB;BvIO;TmaL1;PGO", + "LocateWith": "FRONTEND_RETIRED.LATENCY_GE_4" + }, + { + "MetricName": "Fetch_Latency", + "LegacyName": "metric_TMA_..Fetch_Latency(%)", + "ParentCategory": "Frontend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "a" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( 5 ) * a - b ) / ( c ) )", + "BaseFormula": "( ( 5 ) * idq_uops_not_delivered.cycles_0_uops_deliv.core - int_misc.uop_dropping ) / tma_info_thread_slots", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 15", + "BaseFormula": "metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Frontend;TmaL2", + "LocateWith": "FRONTEND_RETIRED.LATENCY_GE_16;FRONTEND_RETIRED.LATENCY_GE_8" + }, + { + "MetricName": "ICache_Misses", + "LegacyName": "metric_TMA_....ICache_Misses(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "icache_data.stalls / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....ICache_Misses(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....ICache_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss", + "LocateWith": "FRONTEND_RETIRED.L2_MISS;FRONTEND_RETIRED.L1I_MISS" + }, + { + "MetricName": "Code_L2_Hit", + "LegacyName": "metric_TMA_......Code_L2_Hit(%)", + "ParentCategory": "ICache_Misses", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles the CPU was stalled due to instruction cache misses that hit in the L2 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b ) ) - ( c / ( b ) ) ) )", + "BaseFormula": "max( 0 , tma_icache_misses - tma_code_l2_miss )", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Code_L2_Hit(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....ICache_Misses(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 15", + "BaseFormula": "metric_TMA_......Code_L2_Hit(%) > 5 & metric_TMA_....ICache_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "IcMiss;FetchLat;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Code_L2_Miss", + "LegacyName": "metric_TMA_......Code_L2_Miss(%)", + "ParentCategory": "ICache_Misses", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles the CPU was stalled due to instruction cache misses that miss in the L2 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "offcore_requests_outstanding.cycles_with_demand_code_rd / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Code_L2_Miss(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....ICache_Misses(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 15", + "BaseFormula": "metric_TMA_......Code_L2_Miss(%) > 5 & metric_TMA_....ICache_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "IcMiss;FetchLat;Offcore", + "LocateWith": "" + }, + { + "MetricName": "ITLB_Misses", + "LegacyName": "metric_TMA_....ITLB_Misses(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "icache_tag.stalls / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....ITLB_Misses(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....ITLB_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB", + "LocateWith": "FRONTEND_RETIRED.STLB_MISS;FRONTEND_RETIRED.ITLB_MISS" + }, + { + "MetricName": "Code_STLB_Hit", + "LegacyName": "metric_TMA_......Code_STLB_Hit(%)", + "ParentCategory": "ITLB_Misses", + "Level": 4, + "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) ITLB was missed by instructions fetches, that later on hit in second-level TLB (STLB)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "ITLB_MISSES.WALK_ACTIVE", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b ) ) - ( c / ( b ) ) ) )", + "BaseFormula": "max( 0 , tma_itlb_misses - tma_code_stlb_miss )", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Code_STLB_Hit(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....ITLB_Misses(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 15", + "BaseFormula": "metric_TMA_......Code_STLB_Hit(%) > 5 & metric_TMA_....ITLB_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat;MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Code_STLB_Miss", + "LegacyName": "metric_TMA_......Code_STLB_Miss(%)", + "ParentCategory": "ITLB_Misses", + "Level": 4, + "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by instruction fetches, performing a hardware page walk", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "itlb_misses.walk_active / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Code_STLB_Miss(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....ITLB_Misses(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 15", + "BaseFormula": "metric_TMA_......Code_STLB_Miss(%) > 5 & metric_TMA_....ITLB_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat;MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Code_STLB_Miss_4K", + "LegacyName": "metric_TMA_........Code_STLB_Miss_4K(%)", + "ParentCategory": "Code_STLB_Miss", + "Level": 5, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 4 KB pages for (instruction) code accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "ITLB_MISSES.WALK_COMPLETED_4K", + "Alias": "c" + }, + { + "Name": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b ) ) * c / ( c + d ) )", + "BaseFormula": "tma_code_stlb_miss * itlb_misses.walk_completed_4k / ( itlb_misses.walk_completed_4k + itlb_misses.walk_completed_2m_4m )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Code_STLB_Miss_4K(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......Code_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....ITLB_Misses(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 5 & d > 10 & e > 15", + "BaseFormula": "metric_TMA_........Code_STLB_Miss_4K(%) > 5 & metric_TMA_......Code_STLB_Miss(%) > 5 & metric_TMA_....ITLB_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat;MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Code_STLB_Miss_2M", + "LegacyName": "metric_TMA_........Code_STLB_Miss_2M(%)", + "ParentCategory": "Code_STLB_Miss", + "Level": 5, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 2 or 4 MB pages for (instruction) code accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "c" + }, + { + "Name": "ITLB_MISSES.WALK_COMPLETED_4K", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b ) ) * c / ( d + c ) )", + "BaseFormula": "tma_code_stlb_miss * itlb_misses.walk_completed_2m_4m / ( itlb_misses.walk_completed_4k + itlb_misses.walk_completed_2m_4m )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Code_STLB_Miss_2M(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......Code_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....ITLB_Misses(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 5 & d > 10 & e > 15", + "BaseFormula": "metric_TMA_........Code_STLB_Miss_2M(%) > 5 & metric_TMA_......Code_STLB_Miss(%) > 5 & metric_TMA_....ITLB_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat;MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Branch_Resteers", + "LegacyName": "metric_TMA_....Branch_Resteers(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) + ( 10 ) * c / ( b ) )", + "BaseFormula": "int_misc.clear_resteer_cycles / tma_info_thread_clks + ( 10 ) * baclears.any / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Branch_Resteers(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....Branch_Resteers(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "~overlap" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat", + "LocateWith": "BR_MISP_RETIRED.ALL_BRANCHES" + }, + { + "MetricName": "Mispredicts_Resteers", + "LegacyName": "metric_TMA_......Mispredicts_Resteers(%)", + "ParentCategory": "Branch_Resteers", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "b" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( a + b ) ) * c / ( d ) )", + "BaseFormula": "( br_misp_retired.all_branches / ( br_misp_retired.all_branches + machine_clears.count ) ) * int_misc.clear_resteer_cycles / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Mispredicts_Resteers(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Branch_Resteers(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 15", + "BaseFormula": "metric_TMA_......Mispredicts_Resteers(%) > 5 & metric_TMA_....Branch_Resteers(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "$issueBM" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP", + "LocateWith": "INT_MISC.CLEAR_RESTEER_CYCLES" + }, + { + "MetricName": "Clears_Resteers", + "LegacyName": "metric_TMA_......Clears_Resteers(%)", + "ParentCategory": "Branch_Resteers", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "b" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( 1 - ( a / ( a + b ) ) ) * c / ( d ) )", + "BaseFormula": "( 1 - ( br_misp_retired.all_branches / ( br_misp_retired.all_branches + machine_clears.count ) ) ) * int_misc.clear_resteer_cycles / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Clears_Resteers(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Branch_Resteers(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 15", + "BaseFormula": "metric_TMA_......Clears_Resteers(%) > 5 & metric_TMA_....Branch_Resteers(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "$issueMC" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;MachineClears", + "LocateWith": "INT_MISC.CLEAR_RESTEER_CYCLES" + }, + { + "MetricName": "Unknown_Branches", + "LegacyName": "metric_TMA_......Unknown_Branches(%)", + "ParentCategory": "Branch_Resteers", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "BACLEARS.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( ( 10 ) * a / ( b ) )", + "BaseFormula": "( 10 ) * baclears.any / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Unknown_Branches(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Branch_Resteers(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 15", + "BaseFormula": "metric_TMA_......Unknown_Branches(%) > 5 & metric_TMA_....Branch_Resteers(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;BvBC;FetchLat", + "LocateWith": "BACLEARS.ANY" + }, + { + "MetricName": "MS_Switches", + "LegacyName": "metric_TMA_....MS_Switches(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( ( 3 ) * a / ( b ) )", + "BaseFormula": "( 3 ) * idq.ms_switches / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....MS_Switches(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....MS_Switches(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "$issueMC, $issueMS, $issueMV, $issueSO" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat;MicroSeq", + "LocateWith": "IDQ.MS_SWITCHES" + }, + { + "MetricName": "LCP", + "LegacyName": "metric_TMA_....LCP(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DECODE.LCP", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "decode.lcp / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....LCP(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....LCP(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat", + "LocateWith": "" + }, + { + "MetricName": "DSB_Switches", + "LegacyName": "metric_TMA_....DSB_Switches(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "dsb2mite_switches.penalty_cycles / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....DSB_Switches(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....DSB_Switches(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;FetchLat", + "LocateWith": "FRONTEND_RETIRED.DSB_MISS" + }, + { + "MetricName": "Fetch_Bandwidth", + "LegacyName": "metric_TMA_..Fetch_Bandwidth(%)", + "ParentCategory": "Frontend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( a + b + c + d ) - e / ( f ) ) - ( ( ( 5 ) * g - e ) / ( f ) ) ) )", + "BaseFormula": "max( 0 , tma_frontend_bound - tma_fetch_latency )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Fetch_Bandwidth(%)" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_..Fetch_Bandwidth(%) > 20", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchBW;Frontend;TmaL2", + "LocateWith": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1;FRONTEND_RETIRED.LATENCY_GE_1;FRONTEND_RETIRED.LATENCY_GE_2" + }, + { + "MetricName": "MITE", + "LegacyName": "metric_TMA_....MITE(%)", + "ParentCategory": "Fetch_Bandwidth", + "Level": 3, + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.MITE_CYCLES_ANY", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_CYCLES_OK", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a - b ) / ( c if smt_on else ( d ) ) / 2 )", + "BaseFormula": "( idq.mite_cycles_any - idq.mite_cycles_ok ) / tma_info_core_core_clks / 2", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....MITE(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Bandwidth(%)" + } + ], + "Formula": "a > 10 & b > 20", + "BaseFormula": "metric_TMA_....MITE(%) > 10 & metric_TMA_..Fetch_Bandwidth(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;FetchBW", + "LocateWith": "FRONTEND_RETIRED.ANY_DSB_MISS" + }, + { + "MetricName": "Decoder0_Alone", + "LegacyName": "metric_TMA_......Decoder0_Alone(%)", + "ParentCategory": "MITE", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INST_DECODED.DECODERS:c1", + "Alias": "a" + }, + { + "Name": "INST_DECODED.DECODERS:c2", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a - b ) / ( c if smt_on else ( d ) ) / 2 )", + "BaseFormula": "( inst_decoded.decoders:c1 - inst_decoded.decoders:c2 ) / tma_info_core_core_clks / 2", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Decoder0_Alone(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....MITE(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Bandwidth(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20", + "BaseFormula": "metric_TMA_......Decoder0_Alone(%) > 10 & metric_TMA_....MITE(%) > 10 & metric_TMA_..Fetch_Bandwidth(%) > 20", + "ThresholdIssues": "$issueD0" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "MITE_4wide", + "LegacyName": "metric_TMA_......MITE_4wide(%)", + "ParentCategory": "MITE", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles where (only) 4 uops were delivered by the MITE pipeline", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.MITE_UOPS:c4", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_UOPS:c5", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a - b ) / ( c ) )", + "BaseFormula": "( idq.mite_uops:c4 - idq.mite_uops:c5 ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Core_Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......MITE_4wide(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....MITE(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Bandwidth(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 20", + "BaseFormula": "metric_TMA_......MITE_4wide(%) > 5 & metric_TMA_....MITE(%) > 10 & metric_TMA_..Fetch_Bandwidth(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "DSB", + "LegacyName": "metric_TMA_....DSB(%)", + "ParentCategory": "Fetch_Bandwidth", + "Level": 3, + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.DSB_CYCLES_ANY", + "Alias": "a" + }, + { + "Name": "IDQ.DSB_CYCLES_OK", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a - b ) / ( c if smt_on else ( d ) ) / 2 )", + "BaseFormula": "( idq.dsb_cycles_any - idq.dsb_cycles_ok ) / tma_info_core_core_clks / 2", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....DSB(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Bandwidth(%)" + } + ], + "Formula": "a > 15 & b > 20", + "BaseFormula": "metric_TMA_....DSB(%) > 15 & metric_TMA_..Fetch_Bandwidth(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSB;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "MS", + "LegacyName": "metric_TMA_....MS(%)", + "ParentCategory": "Fetch_Bandwidth", + "Level": 3, + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the Microcode Sequencer (MS) unit - see Microcode_Sequencer node for details.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.MS_UOPS:c1", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( a / ( b if smt_on else ( c ) ) / 3.3 )", + "BaseFormula": "idq.ms_uops:c1 / tma_info_core_core_clks / 3.3", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....MS(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Bandwidth(%)" + } + ], + "Formula": "a > 5 & b > 20", + "BaseFormula": "metric_TMA_....MS(%) > 5 & metric_TMA_..Fetch_Bandwidth(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq", + "LocateWith": "" + }, + { + "MetricName": "Bad_Speculation", + "LegacyName": "metric_TMA_Bad_Speculation(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * g ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) )", + "BaseFormula": "max( 1 - ( tma_frontend_bound + tma_backend_bound + tma_retiring ) , 0 )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 15", + "BaseFormula": "metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "TmaL1", + "LocateWith": "#NA" + }, + { + "MetricName": "Branch_Mispredicts", + "LegacyName": "metric_TMA_..Branch_Mispredicts(%)", + "ParentCategory": "Bad_Speculation", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "f" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "i" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( a + b ) ) * ( max( 1 - ( ( c / ( c + d + e + f ) - g / ( h ) ) + ( f / ( c + d + e + f ) + ( ( 5 ) * i ) / ( h ) ) + ( e / ( c + d + e + f ) ) ) , 0 ) ) )", + "BaseFormula": "( br_misp_retired.all_branches / ( br_misp_retired.all_branches + machine_clears.count ) ) * tma_bad_speculation", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Branch_Mispredicts(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 10 & b > 15", + "BaseFormula": "metric_TMA_..Branch_Mispredicts(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "$issueBM" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2", + "LocateWith": "BR_MISP_RETIRED.ALL_BRANCHES" + }, + { + "MetricName": "Other_Mispredicts", + "LegacyName": "metric_TMA_....Other_Mispredicts(%)", + "ParentCategory": "Branch_Mispredicts", + "Level": 3, + "BriefDescription": "This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "f" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "i" + } + ], + "Constants": [], + "Formula": "100 * ( max( ( ( a / ( a + b ) ) * ( max( 1 - ( ( c / ( c + d + e + f ) - g / ( h ) ) + ( f / ( c + d + e + f ) + ( ( 5 ) * i ) / ( h ) ) + ( e / ( c + d + e + f ) ) ) , 0 ) ) ) * ( 1 - a / ( i - b ) ) , 0.0001 ) )", + "BaseFormula": "max( tma_branch_mispredicts * ( 1 - br_misp_retired.all_branches / ( int_misc.clears_count - machine_clears.count ) ) , 0.0001 )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Other_Mispredicts(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Branch_Mispredicts(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....Other_Mispredicts(%) > 5 & metric_TMA_..Branch_Mispredicts(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvIO;BrMispredicts", + "LocateWith": "" + }, + { + "MetricName": "Machine_Clears", + "LegacyName": "metric_TMA_..Machine_Clears(%)", + "ParentCategory": "Bad_Speculation", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "g" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "h" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "i" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * g ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) - ( ( h / ( h + i ) ) * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * g ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) )", + "BaseFormula": "max( 0 , tma_bad_speculation - tma_branch_mispredicts )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Machine_Clears(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 10 & b > 15", + "BaseFormula": "metric_TMA_..Machine_Clears(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "$issueMC, $issueSyncxn" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2", + "LocateWith": "MACHINE_CLEARS.COUNT" + }, + { + "MetricName": "Other_Nukes", + "LegacyName": "metric_TMA_....Other_Nukes(%)", + "ParentCategory": "Machine_Clears", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "g" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "h" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "i" + }, + { + "Name": "MACHINE_CLEARS.MEMORY_ORDERING", + "Alias": "j" + } + ], + "Constants": [], + "Formula": "100 * ( max( ( max( 0 , ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * g ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) - ( ( h / ( h + i ) ) * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) + ( ( 5 ) * g ) / ( f ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) ) * ( 1 - j / i ) , 0.0001 ) )", + "BaseFormula": "max( tma_machine_clears * ( 1 - machine_clears.memory_ordering / machine_clears.count ) , 0.0001 )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Other_Nukes(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Machine_Clears(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....Other_Nukes(%) > 5 & metric_TMA_..Machine_Clears(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvIO;Machine_Clears", + "LocateWith": "" + }, + { + "MetricName": "Backend_Bound", + "LegacyName": "metric_TMA_Backend_Bound(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) )", + "BaseFormula": "perf_metrics.backend_bound / ( perf_metrics.frontend_bound + perf_metrics.bad_speculation + perf_metrics.retiring + perf_metrics.backend_bound ) + ( ( 5 ) * int_misc.clears_count ) / tma_info_thread_slots", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvOB;TmaL1", + "LocateWith": "TOPDOWN.BACKEND_BOUND_SLOTS" + }, + { + "MetricName": "Memory_Bound", + "LegacyName": "metric_TMA_..Memory_Bound(%)", + "ParentCategory": "Backend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Alias": "a" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "b" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "c" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "g" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "h" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "i" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "j" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "k" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a + b ) / ( c + ( d + ( e / ( f + g + e + h ) ) * i ) + b ) ) * ( h / ( f + g + e + h ) + ( ( 5 ) * j ) / ( k ) ) )", + "BaseFormula": "( ( cycle_activity.stalls_mem_any + exe_activity.bound_on_stores ) / ( cycle_activity.stalls_total + ( exe_activity.1_ports_util + tma_retiring * exe_activity.2_ports_util ) + exe_activity.bound_on_stores ) ) * tma_backend_bound", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20", + "BaseFormula": "metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Backend;TmaL2", + "LocateWith": "#NA" + }, + { + "MetricName": "L1_Bound", + "LegacyName": "metric_TMA_....L1_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 Data (L1D) cache. The L1D cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1D. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Alias": "a" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( max( ( a - b ) / ( c ) , 0 ) )", + "BaseFormula": "max( ( cycle_activity.stalls_mem_any - cycle_activity.stalls_l1d_miss ) / tma_info_thread_clks , 0 )", + "Category": "TMA", + "CountDomain": "Stalls", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 20", + "BaseFormula": "metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueL1, $issueMC" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem", + "LocateWith": "MEM_LOAD_RETIRED.L1_HIT" + }, + { + "MetricName": "DTLB_Load", + "LegacyName": "metric_TMA_......DTLB_Load(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", + "Alias": "a" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "b" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "c" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( 7 ) * a + b , max( c - d , 0 ) ) / ( e ) )", + "BaseFormula": "min( ( 7 ) * dtlb_load_misses.stlb_hit:c1 + dtlb_load_misses.walk_active , max( cycle_activity.cycles_mem_any - cycle_activity.cycles_l1d_miss , 0 ) ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......DTLB_Load(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......DTLB_Load(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueTLB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMT;MemoryTLB", + "LocateWith": "MEM_INST_RETIRED.STLB_MISS_LOADS" + }, + { + "MetricName": "Load_STLB_Hit", + "LegacyName": "metric_TMA_........Load_STLB_Hit(%)", + "ParentCategory": "DTLB_Load", + "Level": 5, + "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", + "Alias": "a" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "b" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "c" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( ( min( ( 7 ) * a + b , max( c - d , 0 ) ) / ( e ) ) - ( b / ( e ) ) )", + "BaseFormula": "tma_dtlb_load - tma_load_stlb_miss", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Load_STLB_Hit(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......DTLB_Load(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 10 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........Load_STLB_Hit(%) > 5 & metric_TMA_......DTLB_Load(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Load_STLB_Miss", + "LegacyName": "metric_TMA_........Load_STLB_Miss(%)", + "ParentCategory": "DTLB_Load", + "Level": 5, + "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "dtlb_load_misses.walk_active / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Calculated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Load_STLB_Miss(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......DTLB_Load(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 10 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........Load_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Load(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Load_STLB_Miss_4K", + "LegacyName": "metric_TMA_..........Load_STLB_Miss_4K(%)", + "ParentCategory": "Load_STLB_Miss", + "Level": 6, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 4 KB pages for data load accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "Alias": "c" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "d" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b ) ) * c / ( c + d + e ) )", + "BaseFormula": "tma_load_stlb_miss * dtlb_load_misses.walk_completed_4k / ( dtlb_load_misses.walk_completed_4k + dtlb_load_misses.walk_completed_2m_4m + dtlb_load_misses.walk_completed_1g )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Load_STLB_Miss_4K(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_........Load_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_......DTLB_Load(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "f", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 10 & e > 20 & f > 20", + "BaseFormula": "metric_TMA_..........Load_STLB_Miss_4K(%) > 5 & metric_TMA_........Load_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Load(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Load_STLB_Miss_2M", + "LegacyName": "metric_TMA_..........Load_STLB_Miss_2M(%)", + "ParentCategory": "Load_STLB_Miss", + "Level": 6, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 2 or 4 MB pages for data load accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "c" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "Alias": "d" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b ) ) * c / ( d + c + e ) )", + "BaseFormula": "tma_load_stlb_miss * dtlb_load_misses.walk_completed_2m_4m / ( dtlb_load_misses.walk_completed_4k + dtlb_load_misses.walk_completed_2m_4m + dtlb_load_misses.walk_completed_1g )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Load_STLB_Miss_2M(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_........Load_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_......DTLB_Load(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "f", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 10 & e > 20 & f > 20", + "BaseFormula": "metric_TMA_..........Load_STLB_Miss_2M(%) > 5 & metric_TMA_........Load_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Load(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Load_STLB_Miss_1G", + "LegacyName": "metric_TMA_..........Load_STLB_Miss_1G(%)", + "ParentCategory": "Load_STLB_Miss", + "Level": 6, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 1 GB pages for data load accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "Alias": "c" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "Alias": "d" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b ) ) * c / ( d + e + c ) )", + "BaseFormula": "tma_load_stlb_miss * dtlb_load_misses.walk_completed_1g / ( dtlb_load_misses.walk_completed_4k + dtlb_load_misses.walk_completed_2m_4m + dtlb_load_misses.walk_completed_1g )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Load_STLB_Miss_1G(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_........Load_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_......DTLB_Load(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "f", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 10 & e > 20 & f > 20", + "BaseFormula": "metric_TMA_..........Load_STLB_Miss_1G(%) > 5 & metric_TMA_........Load_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Load(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Store_Fwd_Blk", + "LegacyName": "metric_TMA_......Store_Fwd_Blk(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "LD_BLOCKS.STORE_FORWARD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 13 * a / ( b ) )", + "BaseFormula": "13 * ld_blocks.store_forward / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Store_Fwd_Blk(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Store_Fwd_Blk(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "L1_Latency_Dependency", + "LegacyName": "metric_TMA_......L1_Latency_Dependency(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric ([SKL+] roughly; [LNL]) estimates fraction of cycles with demand load accesses that hit the L1D cache. The short latency of the L1D cache may be exposed in pointer-chasing memory access patterns as an example.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "c" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "e" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + } + ], + "Constants": [ + { + "Name": "20", + "Alias": "dependentloadsweight" + } + ], + "Formula": "100 * ( min( 2 * ( a - b - c ) * dependentloadsweight / 100 , max( e - f , 0 ) ) / ( g ) )", + "BaseFormula": "min( 2 * ( mem_inst_retired.all_loads - mem_load_retired.fb_hit - mem_load_retired.l1_miss ) * 20 / 100 , max( cycle_activity.cycles_mem_any - cycle_activity.cycles_l1d_miss , 0 ) ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......L1_Latency_Dependency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......L1_Latency_Dependency(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvML;MemoryLat", + "LocateWith": "MEM_LOAD_RETIRED.L1_HIT" + }, + { + "MetricName": "Lock_Latency", + "LegacyName": "metric_TMA_......Lock_Latency(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a" + }, + { + "Name": "L2_RQSTS.ALL_RFO", + "Alias": "b" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "c" + }, + { + "Name": "L2_RQSTS.RFO_HIT", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( ( 16 * max( 0 , a - b ) + ( a / c ) * ( ( 10 ) * d + ( min( e , f ) ) ) ) / ( e ) )", + "BaseFormula": "( 16 * max( 0 , mem_inst_retired.lock_loads - l2_rqsts.all_rfo ) + ( mem_inst_retired.lock_loads / mem_inst_retired.all_stores ) * ( ( 10 ) * l2_rqsts.rfo_hit + ( min( cpu_clk_unhalted.thread , offcore_requests_outstanding.cycles_with_demand_rfo ) ) ) ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Lock_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Lock_Latency(%) > 20 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueRFO" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "LockCont;Offcore", + "LocateWith": "MEM_INST_RETIRED.LOCK_LOADS" + }, + { + "MetricName": "Split_Loads", + "LegacyName": "metric_TMA_......Split_Loads(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "c" + }, + { + "Name": "LD_BLOCKS.NO_SR", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b + c ) ) * d / ( e ) )", + "BaseFormula": "tma_info_memory_load_miss_real_latency * ld_blocks.no_sr / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Calculated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Split_Loads(%)" + } + ], + "Formula": "a > 30", + "BaseFormula": "metric_TMA_......Split_Loads(%) > 30", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "MEM_INST_RETIRED.SPLIT_LOADS" + }, + { + "MetricName": "4K_Aliasing", + "LegacyName": "metric_TMA_......4K_Aliasing(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "ld_blocks_partial.address_alias / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......4K_Aliasing(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......4K_Aliasing(%) > 20 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "FB_Full", + "LegacyName": "metric_TMA_......FB_Full(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "L1D_PEND_MISS.FB_FULL", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "l1d_pend_miss.fb_full / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Calculated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......FB_Full(%)" + } + ], + "Formula": "a > 30", + "BaseFormula": "metric_TMA_......FB_Full(%) > 30", + "ThresholdIssues": "$issueBW, $issueSL, $issueSmSt" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMB;MemoryBW", + "LocateWith": "" + }, + { + "MetricName": "L2_Bound", + "LegacyName": "metric_TMA_....L2_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_HIT", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "c" + }, + { + "Name": "L1D_PEND_MISS.FB_FULL_PERIODS", + "Alias": "d" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "Alias": "e" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a * ( 1 + ( b / c ) ) ) / ( ( a * ( 1 + ( b / c ) ) ) + d ) ) * ( ( e - f ) / ( g ) ) )", + "BaseFormula": "( ( mem_load_retired.l2_hit * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) ) ) / ( ( mem_load_retired.l2_hit * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) ) ) + l1d_pend_miss.fb_full_periods ) ) * ( ( cycle_activity.stalls_l1d_miss - cycle_activity.stalls_l2_miss ) / tma_info_thread_clks )", + "Category": "TMA", + "CountDomain": "Stalls", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....L2_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 20 & c > 20", + "BaseFormula": "metric_TMA_....L2_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvML;CacheHits;MemoryBound;TmaL3mem", + "LocateWith": "MEM_LOAD_RETIRED.L2_HIT" + }, + { + "MetricName": "L2_Hit_Latency", + "LegacyName": "metric_TMA_......L2_Hit_Latency(%)", + "ParentCategory": "L2_Bound", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L2 cache under unloaded scenarios (possibly L2 latency limited). Avoiding L1 cache misses (i.e. L1 misses/L2 hits) will improve the latency.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_RETIRED.L2_HIT", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "f" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "g" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) )", + "BaseFormula": "( 4 * tma_info_system_core_frequency ) * mem_load_retired.l2_hit * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) / 2 ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......L2_Hit_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L2_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......L2_Hit_Latency(%) > 5 & metric_TMA_....L2_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryLat", + "LocateWith": "MEM_LOAD_RETIRED.L2_HIT" + }, + { + "MetricName": "L3_Bound", + "LegacyName": "metric_TMA_....L3_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "Alias": "a" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L3_MISS", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a - b ) / ( c ) )", + "BaseFormula": "( cycle_activity.stalls_l2_miss - cycle_activity.stalls_l3_miss ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Stalls", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....L3_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 20 & c > 20", + "BaseFormula": "metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem", + "LocateWith": "MEM_LOAD_RETIRED.L3_HIT" + }, + { + "MetricName": "Contested_Accesses", + "LegacyName": "metric_TMA_......Contested_Accesses(%)", + "ParentCategory": "L3_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", + "Alias": "e" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "f" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "g" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Alias": "h" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "i" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "j" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( ( ( ( 48 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( e * ( f / ( f + g ) ) ) + ( ( 47.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( h ) ) * ( 1 + ( i / j ) / 2 ) / ( a ) )", + "BaseFormula": "( ( ( 48 * tma_info_system_core_frequency ) - ( 4 * tma_info_system_core_frequency ) ) * ( mem_load_l3_hit_retired.xsnp_hitm * ( ocr.demand_data_rd.l3_hit.snoop_hitm / ( ocr.demand_data_rd.l3_hit.snoop_hitm + ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd ) ) ) + ( ( 47.5 * tma_info_system_core_frequency ) - ( 4 * tma_info_system_core_frequency ) ) * ( mem_load_l3_hit_retired.xsnp_miss ) ) * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) / 2 ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Contested_Accesses(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L3_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Contested_Accesses(%) > 5 & metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSyncxn" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMS;DataSharing;LockCont;Offcore;Snoop", + "LocateWith": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS" + }, + { + "MetricName": "Data_Sharing", + "LegacyName": "metric_TMA_......Data_Sharing(%)", + "ParentCategory": "L3_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", + "Alias": "f" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "g" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "h" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "i" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "j" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( ( ( 47.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( e + f * ( 1 - ( g / ( g + h ) ) ) ) * ( 1 + ( i / j ) / 2 ) / ( a ) )", + "BaseFormula": "( ( 47.5 * tma_info_system_core_frequency ) - ( 4 * tma_info_system_core_frequency ) ) * ( mem_load_l3_hit_retired.xsnp_hit + mem_load_l3_hit_retired.xsnp_hitm * ( 1 - ( ocr.demand_data_rd.l3_hit.snoop_hitm / ( ocr.demand_data_rd.l3_hit.snoop_hitm + ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd ) ) ) ) * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) / 2 ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Data_Sharing(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L3_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Data_Sharing(%) > 5 & metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSyncxn" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMS;Offcore;Snoop", + "LocateWith": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT" + }, + { + "MetricName": "L3_Hit_Latency", + "LegacyName": "metric_TMA_......L3_Hit_Latency(%)", + "ParentCategory": "L3_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "f" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "g" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( ( ( 23 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( e * ( 1 + ( f / g ) / 2 ) ) / ( a ) )", + "BaseFormula": "( ( 23 * tma_info_system_core_frequency ) - ( 4 * tma_info_system_core_frequency ) ) * ( mem_load_retired.l3_hit * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) / 2 ) ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......L3_Hit_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L3_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 5 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......L3_Hit_Latency(%) > 10 & metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueLat, ~overlap" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvML;MemoryLat", + "LocateWith": "MEM_LOAD_RETIRED.L3_HIT" + }, + { + "MetricName": "SQ_Full", + "LegacyName": "metric_TMA_......SQ_Full(%)", + "ParentCategory": "L3_Bound", + "Level": 4, + "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "L1D_PEND_MISS.L2_STALL", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "l1d_pend_miss.l2_stall / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......SQ_Full(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L3_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 30 & b > 5 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......SQ_Full(%) > 30 & metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueBW" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMB;MemoryBW;Offcore", + "LocateWith": "" + }, + { + "MetricName": "DRAM_Bound", + "LegacyName": "metric_TMA_....DRAM_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CYCLE_ACTIVITY.STALLS_L3_MISS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "Alias": "c" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "Alias": "d" + }, + { + "Name": "MEM_LOAD_RETIRED.L2_HIT", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "f" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "g" + }, + { + "Name": "L1D_PEND_MISS.FB_FULL_PERIODS", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b ) + ( ( c - d ) / ( b ) ) - ( ( ( e * ( 1 + ( f / g ) ) ) / ( ( e * ( 1 + ( f / g ) ) ) + h ) ) * ( ( c - d ) / ( b ) ) ) ) )", + "BaseFormula": "( cycle_activity.stalls_l3_miss / tma_info_thread_clks + ( ( cycle_activity.stalls_l1d_miss - cycle_activity.stalls_l2_miss ) / tma_info_thread_clks ) - tma_l2_bound )", + "Category": "TMA", + "CountDomain": "Stalls", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 20", + "BaseFormula": "metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBound;TmaL3mem", + "LocateWith": "MEM_LOAD_RETIRED.L3_MISS" + }, + { + "MetricName": "MEM_Bandwidth", + "LegacyName": "metric_TMA_......MEM_Bandwidth(%)", + "ParentCategory": "DRAM_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( ( min( a , b ) ) / ( a ) )", + "BaseFormula": "( min( cpu_clk_unhalted.thread , offcore_requests_outstanding.all_data_rd:c4 ) ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......MEM_Bandwidth(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......MEM_Bandwidth(%) > 20 & metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueBW" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMB;MemoryBW;Offcore", + "LocateWith": "" + }, + { + "MetricName": "MEM_Latency", + "LegacyName": "metric_TMA_......MEM_Latency(%)", + "ParentCategory": "DRAM_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "b" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( min( a , b ) ) / ( a ) - ( ( min( a , c ) ) / ( a ) ) )", + "BaseFormula": "( min( cpu_clk_unhalted.thread , offcore_requests_outstanding.cycles_with_data_rd ) ) / tma_info_thread_clks - tma_mem_bandwidth", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......MEM_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......MEM_Latency(%) > 10 & metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueLat" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvML;MemoryLat;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Local_MEM", + "LegacyName": "metric_TMA_........Local_MEM(%)", + "ParentCategory": "MEM_Latency", + "Level": 5, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "f" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "g" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( ( ( 66.5 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 23 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) )", + "BaseFormula": "( ( 66.5 * tma_info_system_core_frequency ) - ( 23 * tma_info_system_core_frequency ) ) * mem_load_l3_miss_retired.local_dram * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) / 2 ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Local_MEM(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......MEM_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 10 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........Local_MEM(%) > 10 & metric_TMA_......MEM_Latency(%) > 10 & metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Server", + "LocateWith": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM" + }, + { + "MetricName": "Remote_MEM", + "LegacyName": "metric_TMA_........Remote_MEM(%)", + "ParentCategory": "MEM_Latency", + "Level": 5, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "f" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "g" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( ( ( 131 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 23 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) )", + "BaseFormula": "( ( 131 * tma_info_system_core_frequency ) - ( 23 * tma_info_system_core_frequency ) ) * mem_load_l3_miss_retired.remote_dram * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) / 2 ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Remote_MEM(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......MEM_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 10 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........Remote_MEM(%) > 10 & metric_TMA_......MEM_Latency(%) > 10 & metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Server;Snoop", + "LocateWith": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM" + }, + { + "MetricName": "Remote_Cache", + "LegacyName": "metric_TMA_........Remote_Cache(%)", + "ParentCategory": "MEM_Latency", + "Level": 5, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "Alias": "f" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "g" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "h" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( ( ( ( 120 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 23 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * e + ( ( 120 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 23 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * f ) * ( 1 + ( g / h ) / 2 ) / ( a ) )", + "BaseFormula": "( ( ( 120 * tma_info_system_core_frequency ) - ( 23 * tma_info_system_core_frequency ) ) * mem_load_l3_miss_retired.remote_hitm + ( ( 120 * tma_info_system_core_frequency ) - ( 23 * tma_info_system_core_frequency ) ) * mem_load_l3_miss_retired.remote_fwd ) * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) / 2 ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Remote_Cache(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......MEM_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 10 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........Remote_Cache(%) > 5 & metric_TMA_......MEM_Latency(%) > 10 & metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSyncxn" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Offcore;Server;Snoop", + "LocateWith": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD" + }, + { + "MetricName": "Store_Bound", + "LegacyName": "metric_TMA_....Store_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "exe_activity.bound_on_stores / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Stalls", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20 & c > 20", + "BaseFormula": "metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBound;TmaL3mem", + "LocateWith": "MEM_INST_RETIRED.ALL_STORES" + }, + { + "MetricName": "Store_Latency", + "LegacyName": "metric_TMA_......Store_Latency(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "L2_RQSTS.RFO_HIT", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "b" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a * ( 10 ) * ( 1 - ( b / c ) ) ) + ( 1 - ( b / c ) ) * ( min( d , e ) ) ) / ( d ) )", + "BaseFormula": "( ( l2_rqsts.rfo_hit * ( 10 ) * ( 1 - ( mem_inst_retired.lock_loads / mem_inst_retired.all_stores ) ) ) + ( 1 - ( mem_inst_retired.lock_loads / mem_inst_retired.all_stores ) ) * ( min( cpu_clk_unhalted.thread , offcore_requests_outstanding.cycles_with_demand_rfo ) ) ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Store_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Store_Latency(%) > 10 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueRFO, $issueSL, ~overlap" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvML;LockCont;MemoryLat;Offcore", + "LocateWith": "" + }, + { + "MetricName": "False_Sharing", + "LegacyName": "metric_TMA_......False_Sharing(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "OCR.DEMAND_RFO.L3_MISS:ocr_msr_val=0x103b800002", + "Alias": "e" + }, + { + "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "Alias": "f" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( ( ( 120 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * e + ( 48 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * f ) / ( a ) )", + "BaseFormula": "( ( 120 * tma_info_system_core_frequency ) * ocr.demand_rfo.l3_miss:ocr_msr_val=0x103b800002 + ( 48 * tma_info_system_core_frequency ) * ocr.demand_rfo.l3_hit.snoop_hitm ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......False_Sharing(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 20 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......False_Sharing(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSyncxn" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMS;DataSharing;LockCont;Offcore;Snoop", + "LocateWith": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM" + }, + { + "MetricName": "Split_Stores", + "LegacyName": "metric_TMA_......Split_Stores(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_INST_RETIRED.SPLIT_STORES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( a / ( b if smt_on else ( c ) ) )", + "BaseFormula": "mem_inst_retired.split_stores / tma_info_core_core_clks", + "Category": "TMA", + "CountDomain": "Core_Utilization", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Split_Stores(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Split_Stores(%) > 20 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSpSt" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "MEM_INST_RETIRED.SPLIT_STORES" + }, + { + "MetricName": "Streaming_Stores", + "LegacyName": "metric_TMA_......Streaming_Stores(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "OCR.STREAMING_WR.ANY_RESPONSE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 9 * a / ( b ) )", + "BaseFormula": "9 * ocr.streaming_wr.any_response / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Streaming_Stores(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Streaming_Stores(%) > 20 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSmSt" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBW;Offcore", + "LocateWith": "OCR.STREAMING_WR.ANY_RESPONSE" + }, + { + "MetricName": "DTLB_Store", + "LegacyName": "metric_TMA_......DTLB_Store(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", + "Alias": "a" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( ( 7 ) * a + b ) / ( c if smt_on else ( d ) ) )", + "BaseFormula": "( ( 7 ) * dtlb_store_misses.stlb_hit:c1 + dtlb_store_misses.walk_active ) / tma_info_core_core_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......DTLB_Store(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 20 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......DTLB_Store(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueTLB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMT;MemoryTLB", + "LocateWith": "MEM_INST_RETIRED.STLB_MISS_STORES" + }, + { + "MetricName": "Store_STLB_Hit", + "LegacyName": "metric_TMA_........Store_STLB_Hit(%)", + "ParentCategory": "DTLB_Store", + "Level": 5, + "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", + "Alias": "a" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( ( ( 7 ) * a + b ) / ( c if smt_on else ( d ) ) ) - ( b / ( c if smt_on else ( d ) ) ) )", + "BaseFormula": "tma_dtlb_store - tma_store_stlb_miss", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Store_STLB_Hit(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......DTLB_Store(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 20 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........Store_STLB_Hit(%) > 5 & metric_TMA_......DTLB_Store(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Store_STLB_Miss", + "LegacyName": "metric_TMA_........Store_STLB_Miss(%)", + "ParentCategory": "DTLB_Store", + "Level": 5, + "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( a / ( b if smt_on else ( c ) ) )", + "BaseFormula": "dtlb_store_misses.walk_active / tma_info_core_core_clks", + "Category": "TMA", + "CountDomain": "Clocks_Calculated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Store_STLB_Miss(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......DTLB_Store(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 20 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........Store_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Store(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Store_STLB_Miss_4K", + "LegacyName": "metric_TMA_..........Store_STLB_Miss_4K(%)", + "ParentCategory": "Store_STLB_Miss", + "Level": 6, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 4 KB pages for data store accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "Alias": "d" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "e" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "Alias": "f" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a / ( b if smt_on else ( c ) ) ) * d / ( d + e + f ) )", + "BaseFormula": "tma_store_stlb_miss * dtlb_store_misses.walk_completed_4k / ( dtlb_store_misses.walk_completed_4k + dtlb_store_misses.walk_completed_2m_4m + dtlb_store_misses.walk_completed_1g )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Store_STLB_Miss_4K(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_........Store_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_......DTLB_Store(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "f", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 5 & d > 20 & e > 20 & f > 20", + "BaseFormula": "metric_TMA_..........Store_STLB_Miss_4K(%) > 5 & metric_TMA_........Store_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Store(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Store_STLB_Miss_2M", + "LegacyName": "metric_TMA_..........Store_STLB_Miss_2M(%)", + "ParentCategory": "Store_STLB_Miss", + "Level": 6, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 2 or 4 MB pages for data store accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "d" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "Alias": "e" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "Alias": "f" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a / ( b if smt_on else ( c ) ) ) * d / ( e + d + f ) )", + "BaseFormula": "tma_store_stlb_miss * dtlb_store_misses.walk_completed_2m_4m / ( dtlb_store_misses.walk_completed_4k + dtlb_store_misses.walk_completed_2m_4m + dtlb_store_misses.walk_completed_1g )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Store_STLB_Miss_2M(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_........Store_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_......DTLB_Store(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "f", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 5 & d > 20 & e > 20 & f > 20", + "BaseFormula": "metric_TMA_..........Store_STLB_Miss_2M(%) > 5 & metric_TMA_........Store_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Store(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Store_STLB_Miss_1G", + "LegacyName": "metric_TMA_..........Store_STLB_Miss_1G(%)", + "ParentCategory": "Store_STLB_Miss", + "Level": 6, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 1 GB pages for data store accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "Alias": "d" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "Alias": "e" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "f" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a / ( b if smt_on else ( c ) ) ) * d / ( e + f + d ) )", + "BaseFormula": "tma_store_stlb_miss * dtlb_store_misses.walk_completed_1g / ( dtlb_store_misses.walk_completed_4k + dtlb_store_misses.walk_completed_2m_4m + dtlb_store_misses.walk_completed_1g )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Store_STLB_Miss_1G(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_........Store_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_......DTLB_Store(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "f", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 5 & d > 20 & e > 20 & f > 20", + "BaseFormula": "metric_TMA_..........Store_STLB_Miss_1G(%) > 5 & metric_TMA_........Store_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Store(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Core_Bound", + "LegacyName": "metric_TMA_..Core_Bound(%)", + "ParentCategory": "Backend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Alias": "g" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "h" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "i" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "k" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) - ( ( ( g + h ) / ( i + ( j + ( d / ( b + c + d + a ) ) * k ) + h ) ) * ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) ) ) )", + "BaseFormula": "max( 0 , tma_backend_bound - tma_memory_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 20", + "BaseFormula": "metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Backend;TmaL2;Compute", + "LocateWith": "" + }, + { + "MetricName": "Divider", + "LegacyName": "metric_TMA_....Divider(%)", + "ParentCategory": "Core_Bound", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ARITH.DIVIDER_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "arith.divider_active / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Divider(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 10 & c > 20", + "BaseFormula": "metric_TMA_....Divider(%) > 20 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvCB", + "LocateWith": "ARITH.DIVIDER_ACTIVE" + }, + { + "MetricName": "FP_Divider", + "LegacyName": "metric_TMA_......FP_Divider(%)", + "ParentCategory": "Divider", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles where the Floating-Point Divider unit was active.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ARITH.FP_DIVIDER_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "arith.fp_divider_active / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......FP_Divider(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Divider(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......FP_Divider(%) > 20 & metric_TMA_....Divider(%) > 20 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "INT_Divider", + "LegacyName": "metric_TMA_......INT_Divider(%)", + "ParentCategory": "Divider", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles where the Integer Divider unit was active.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ARITH.DIVIDER_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "ARITH.FP_DIVIDER_ACTIVE", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b ) ) - ( c / ( b ) ) )", + "BaseFormula": "tma_divider - tma_fp_divider", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......INT_Divider(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Divider(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......INT_Divider(%) > 20 & metric_TMA_....Divider(%) > 20 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "Serializing_Operation", + "LegacyName": "metric_TMA_....Serializing_Operation(%)", + "ParentCategory": "Core_Bound", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "resource_stalls.scoreboard / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Serializing_Operation(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20", + "BaseFormula": "metric_TMA_....Serializing_Operation(%) > 10 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSO" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvIO;PortsUtil", + "LocateWith": "RESOURCE_STALLS.SCOREBOARD" + }, + { + "MetricName": "Slow_Pause", + "LegacyName": "metric_TMA_......Slow_Pause(%)", + "ParentCategory": "Serializing_Operation", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MISC_RETIRED.PAUSE_INST", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 37 * a / ( b ) )", + "BaseFormula": "37 * misc_retired.pause_inst / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Slow_Pause(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Serializing_Operation(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......Slow_Pause(%) > 5 & metric_TMA_....Serializing_Operation(%) > 10 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "MISC_RETIRED.PAUSE_INST" + }, + { + "MetricName": "Ports_Utilization", + "LegacyName": "metric_TMA_....Ports_Utilization(%)", + "ParentCategory": "Core_Bound", + "Level": 3, + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.3_PORTS_UTIL:u0x80", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "h" + }, + { + "Name": "ARITH.DIVIDER_ACTIVE", + "Alias": "i" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "j" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Alias": "k" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a / ( b ) ) * ( b ) + ( c + ( d / ( e + f + d + g ) ) * h ) ) / ( b ) if ( i < ( j - k ) ) else ( c + ( d / ( e + f + d + g ) ) * h ) / ( b ) )", + "BaseFormula": "( tma_ports_utilized_0 * tma_info_thread_clks + ( exe_activity.1_ports_util + tma_retiring * exe_activity.2_ports_util ) ) / tma_info_thread_clks if ( arith.divider_active < ( cycle_activity.stalls_total - cycle_activity.stalls_mem_any ) ) else ( exe_activity.1_ports_util + tma_retiring * exe_activity.2_ports_util ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Ports_Utilization(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 15 & b > 10 & c > 20", + "BaseFormula": "metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil", + "LocateWith": "" + }, + { + "MetricName": "Ports_Utilized_0", + "LegacyName": "metric_TMA_......Ports_Utilized_0(%)", + "ParentCategory": "Ports_Utilization", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.3_PORTS_UTIL:u0x80", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "exe_activity.3_ports_util:u0x80 / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Ports_Utilized_0(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Ports_Utilization(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 15 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......Ports_Utilized_0(%) > 20 & metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil", + "LocateWith": "" + }, + { + "MetricName": "Mixing_Vectors", + "LegacyName": "metric_TMA_........Mixing_Vectors(%)", + "ParentCategory": "Ports_Utilized_0", + "Level": 5, + "BriefDescription": "This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued , the Count Domain; [ADL+] cycles). Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / b )", + "BaseFormula": "uops_issued.vector_width_mismatch / uops_issued.any", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Mixing_Vectors(%)" + } + ], + "Formula": "a > 5", + "BaseFormula": "metric_TMA_........Mixing_Vectors(%) > 5", + "ThresholdIssues": "$issueMV" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "Ports_Utilized_1", + "LegacyName": "metric_TMA_......Ports_Utilized_1(%)", + "ParentCategory": "Ports_Utilization", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "exe_activity.1_ports_util / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Ports_Utilized_1(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Ports_Utilization(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 15 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......Ports_Utilized_1(%) > 20 & metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueL1" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil", + "LocateWith": "EXE_ACTIVITY.1_PORTS_UTIL" + }, + { + "MetricName": "Ports_Utilized_2", + "LegacyName": "metric_TMA_......Ports_Utilized_2(%)", + "ParentCategory": "Ports_Utilization", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "exe_activity.2_ports_util / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Ports_Utilized_2(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Ports_Utilization(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 15 & b > 15 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......Ports_Utilized_2(%) > 15 & metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil", + "LocateWith": "EXE_ACTIVITY.2_PORTS_UTIL" + }, + { + "MetricName": "Ports_Utilized_3m", + "LegacyName": "metric_TMA_......Ports_Utilized_3m(%)", + "ParentCategory": "Ports_Utilization", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_EXECUTED.CYCLES_GE_3", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "uops_executed.cycles_ge_3 / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Ports_Utilized_3m(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Ports_Utilization(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 40 & b > 15 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......Ports_Utilized_3m(%) > 40 & metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvCB;PortsUtil", + "LocateWith": "UOPS_EXECUTED.CYCLES_GE_3" + }, + { + "MetricName": "ALU_Op_Utilization", + "LegacyName": "metric_TMA_........ALU_Op_Utilization(%)", + "ParentCategory": "Ports_Utilized_3m", + "Level": 5, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_0", + "Alias": "a" + }, + { + "Name": "UOPS_DISPATCHED.PORT_1", + "Alias": "b" + }, + { + "Name": "UOPS_DISPATCHED.PORT_5", + "Alias": "c" + }, + { + "Name": "UOPS_DISPATCHED.PORT_6", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "e" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "f" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a + b + c + d ) / ( 4 * ( e if smt_on else ( f ) ) ) )", + "BaseFormula": "( uops_dispatched.port_0 + uops_dispatched.port_1 + uops_dispatched.port_5 + uops_dispatched.port_6 ) / ( 4 * tma_info_core_core_clks )", + "Category": "TMA", + "CountDomain": "Core_Execution", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........ALU_Op_Utilization(%)" + } + ], + "Formula": "a > 40", + "BaseFormula": "metric_TMA_........ALU_Op_Utilization(%) > 40", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "Port_0", + "LegacyName": "metric_TMA_..........Port_0(%)", + "ParentCategory": "ALU_Op_Utilization", + "Level": 6, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_0", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( a / ( b if smt_on else ( c ) ) )", + "BaseFormula": "uops_dispatched.port_0 / tma_info_core_core_clks", + "Category": "TMA", + "CountDomain": "Core_Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Port_0(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..........Port_0(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute", + "LocateWith": "UOPS_DISPATCHED.PORT_0" + }, + { + "MetricName": "Port_1", + "LegacyName": "metric_TMA_..........Port_1(%)", + "ParentCategory": "ALU_Op_Utilization", + "Level": 6, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_1", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( a / ( b if smt_on else ( c ) ) )", + "BaseFormula": "uops_dispatched.port_1 / tma_info_core_core_clks", + "Category": "TMA", + "CountDomain": "Core_Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Port_1(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..........Port_1(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "UOPS_DISPATCHED.PORT_1" + }, + { + "MetricName": "Port_5", + "LegacyName": "metric_TMA_..........Port_5(%)", + "ParentCategory": "ALU_Op_Utilization", + "Level": 6, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_5", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( a / ( b if smt_on else ( c ) ) )", + "BaseFormula": "uops_dispatched.port_5 / tma_info_core_core_clks", + "Category": "TMA", + "CountDomain": "Core_Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Port_5(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..........Port_5(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "UOPS_DISPATCHED.PORT_5" + }, + { + "MetricName": "Port_6", + "LegacyName": "metric_TMA_..........Port_6(%)", + "ParentCategory": "ALU_Op_Utilization", + "Level": 6, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_6", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( a / ( b if smt_on else ( c ) ) )", + "BaseFormula": "uops_dispatched.port_6 / tma_info_core_core_clks", + "Category": "TMA", + "CountDomain": "Core_Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Port_6(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..........Port_6(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "UOPS_DISPATCHED.PORT_1" + }, + { + "MetricName": "Load_Op_Utilization", + "LegacyName": "metric_TMA_........Load_Op_Utilization(%)", + "ParentCategory": "Ports_Utilized_3m", + "Level": 5, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_2_3", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( a / ( 2 * ( b if smt_on else ( c ) ) ) )", + "BaseFormula": "uops_dispatched.port_2_3 / ( 2 * tma_info_core_core_clks )", + "Category": "TMA", + "CountDomain": "Core_Execution", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Load_Op_Utilization(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_........Load_Op_Utilization(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "UOPS_DISPATCHED.PORT_2_3" + }, + { + "MetricName": "Store_Op_Utilization", + "LegacyName": "metric_TMA_........Store_Op_Utilization(%)", + "ParentCategory": "Ports_Utilized_3m", + "Level": 5, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_4_9", + "Alias": "a" + }, + { + "Name": "UOPS_DISPATCHED.PORT_7_8", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a + b ) / ( 4 * ( c if smt_on else ( d ) ) ) )", + "BaseFormula": "( uops_dispatched.port_4_9 + uops_dispatched.port_7_8 ) / ( 4 * tma_info_core_core_clks )", + "Category": "TMA", + "CountDomain": "Core_Execution", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Store_Op_Utilization(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_........Store_Op_Utilization(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "UOPS_DISPATCHED.PORT_7_8" + }, + { + "MetricName": "Retiring", + "LegacyName": "metric_TMA_Retiring(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b + c + a + d ) )", + "BaseFormula": "perf_metrics.retiring / ( perf_metrics.frontend_bound + perf_metrics.bad_speculation + perf_metrics.retiring + perf_metrics.backend_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Retiring(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 70 | b > 10", + "BaseFormula": "metric_TMA_Retiring(%) > 70 | metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvUW;TmaL1", + "LocateWith": "UOPS_RETIRED.SLOTS" + }, + { + "MetricName": "Light_Operations", + "LegacyName": "metric_TMA_..Light_Operations(%)", + "ParentCategory": "Retiring", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations , instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "e" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "f" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + }, + { + "Name": "UOPS_DECODED.DEC0", + "Alias": "i" + }, + { + "Name": "UOPS_DECODED.DEC0:c1", + "Alias": "j" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "k" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b + c + a + d ) ) - ( ( ( e / f ) * g / ( h ) ) + ( a / ( b + c + a + d ) ) * ( i - j ) / k ) ) )", + "BaseFormula": "max( 0 , tma_retiring - tma_heavy_operations )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Retire;TmaL2", + "LocateWith": "INST_RETIRED.PREC_DIST" + }, + { + "MetricName": "FP_Arith", + "LegacyName": "metric_TMA_....FP_Arith(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "UOPS_EXECUTED.X87", + "Alias": "e" + }, + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "f" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + }, + { + "Name": "FP_ARITH_INST_RETIRED.VECTOR", + "Alias": "i" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a / ( b + c + a + d ) ) * e / f ) + ( ( g ) / ( ( a / ( b + c + a + d ) ) * ( h ) ) ) + ( ( i ) / ( ( a / ( b + c + a + d ) ) * ( h ) ) ) )", + "BaseFormula": "tma_x87_use + tma_fp_scalar + tma_fp_vector", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....FP_Arith(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 20 & b > 60", + "BaseFormula": "metric_TMA_....FP_Arith(%) > 20 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC", + "LocateWith": "" + }, + { + "MetricName": "X87_Use", + "LegacyName": "metric_TMA_......X87_Use(%)", + "ParentCategory": "FP_Arith", + "Level": 4, + "BriefDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "UOPS_EXECUTED.X87", + "Alias": "e" + }, + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b + c + a + d ) ) * e / f )", + "BaseFormula": "tma_retiring * uops_executed.x87 / uops_executed.thread", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......X87_Use(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....FP_Arith(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 60", + "BaseFormula": "metric_TMA_......X87_Use(%) > 10 & metric_TMA_....FP_Arith(%) > 20 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute", + "LocateWith": "" + }, + { + "MetricName": "FP_Scalar", + "LegacyName": "metric_TMA_......FP_Scalar(%)", + "ParentCategory": "FP_Arith", + "Level": 4, + "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( ( a ) / ( ( b / ( c + d + b + e ) ) * ( f ) ) )", + "BaseFormula": "( fp_arith_inst_retired.scalar ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......FP_Scalar(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....FP_Arith(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 60", + "BaseFormula": "metric_TMA_......FP_Scalar(%) > 10 & metric_TMA_....FP_Arith(%) > 20 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops", + "LocateWith": "" + }, + { + "MetricName": "FP_Vector", + "LegacyName": "metric_TMA_......FP_Vector(%)", + "ParentCategory": "FP_Arith", + "Level": 4, + "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.VECTOR", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( ( a ) / ( ( b / ( c + d + b + e ) ) * ( f ) ) )", + "BaseFormula": "( fp_arith_inst_retired.vector ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......FP_Vector(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....FP_Arith(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 60", + "BaseFormula": "metric_TMA_......FP_Vector(%) > 10 & metric_TMA_....FP_Arith(%) > 20 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops", + "LocateWith": "" + }, + { + "MetricName": "FP_Vector_128b", + "LegacyName": "metric_TMA_........FP_Vector_128b(%)", + "ParentCategory": "FP_Vector", + "Level": 5, + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting prior to LNL.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) )", + "BaseFormula": "( fp_arith_inst_retired.128b_packed_double + fp_arith_inst_retired.128b_packed_single ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........FP_Vector_128b(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......FP_Vector(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....FP_Arith(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 60", + "BaseFormula": "metric_TMA_........FP_Vector_128b(%) > 10 & metric_TMA_......FP_Vector(%) > 10 & metric_TMA_....FP_Arith(%) > 20 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops", + "LocateWith": "" + }, + { + "MetricName": "FP_Vector_256b", + "LegacyName": "metric_TMA_........FP_Vector_256b(%)", + "ParentCategory": "FP_Vector", + "Level": 5, + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting prior to LNL.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) )", + "BaseFormula": "( fp_arith_inst_retired.256b_packed_double + fp_arith_inst_retired.256b_packed_single ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........FP_Vector_256b(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......FP_Vector(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....FP_Arith(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 60", + "BaseFormula": "metric_TMA_........FP_Vector_256b(%) > 10 & metric_TMA_......FP_Vector(%) > 10 & metric_TMA_....FP_Arith(%) > 20 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops", + "LocateWith": "" + }, + { + "MetricName": "FP_Vector_512b", + "LegacyName": "metric_TMA_........FP_Vector_512b(%)", + "ParentCategory": "FP_Vector", + "Level": 5, + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) )", + "BaseFormula": "( fp_arith_inst_retired.512b_packed_double + fp_arith_inst_retired.512b_packed_single ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........FP_Vector_512b(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......FP_Vector(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....FP_Arith(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 60", + "BaseFormula": "metric_TMA_........FP_Vector_512b(%) > 10 & metric_TMA_......FP_Vector(%) > 10 & metric_TMA_....FP_Arith(%) > 20 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops", + "LocateWith": "" + }, + { + "MetricName": "Memory_Operations", + "LegacyName": "metric_TMA_....Memory_Operations(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations , uops for memory load or store accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "e" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "f" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + }, + { + "Name": "UOPS_DECODED.DEC0", + "Alias": "i" + }, + { + "Name": "UOPS_DECODED.DEC0:c1", + "Alias": "j" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "k" + }, + { + "Name": "MEM_INST_RETIRED.ANY", + "Alias": "l" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "m" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( ( ( e / f ) * g / ( h ) ) + ( a / ( b + c + a + d ) ) * ( i - j ) / k ) ) ) * l / m )", + "BaseFormula": "tma_light_operations * mem_inst_retired.any / inst_retired.any", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Memory_Operations(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 60", + "BaseFormula": "metric_TMA_....Memory_Operations(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Branch_Instructions", + "LegacyName": "metric_TMA_....Branch_Instructions(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "e" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "f" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + }, + { + "Name": "UOPS_DECODED.DEC0", + "Alias": "i" + }, + { + "Name": "UOPS_DECODED.DEC0:c1", + "Alias": "j" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "k" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "l" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( ( ( e / f ) * g / ( h ) ) + ( a / ( b + c + a + d ) ) * ( i - j ) / k ) ) ) * l / ( ( a / ( b + c + a + d ) ) * ( h ) ) )", + "BaseFormula": "tma_light_operations * br_inst_retired.all_branches / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Branch_Instructions(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 60", + "BaseFormula": "metric_TMA_....Branch_Instructions(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;BvBO;Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Other_Light_Ops", + "LegacyName": "metric_TMA_....Other_Light_Ops(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "e" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "f" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + }, + { + "Name": "UOPS_DECODED.DEC0", + "Alias": "i" + }, + { + "Name": "UOPS_DECODED.DEC0:c1", + "Alias": "j" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "k" + }, + { + "Name": "UOPS_EXECUTED.X87", + "Alias": "l" + }, + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "m" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "n" + }, + { + "Name": "FP_ARITH_INST_RETIRED.VECTOR", + "Alias": "o" + }, + { + "Name": "MEM_INST_RETIRED.ANY", + "Alias": "p" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "q" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "r" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( max( 0 , ( a / ( b + c + a + d ) ) - ( ( ( e / f ) * g / ( h ) ) + ( a / ( b + c + a + d ) ) * ( i - j ) / k ) ) ) - ( ( ( ( a / ( b + c + a + d ) ) * l / m ) + ( ( n ) / ( ( a / ( b + c + a + d ) ) * ( h ) ) ) + ( ( o ) / ( ( a / ( b + c + a + d ) ) * ( h ) ) ) ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( ( ( e / f ) * g / ( h ) ) + ( a / ( b + c + a + d ) ) * ( i - j ) / k ) ) ) * p / q ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( ( ( e / f ) * g / ( h ) ) + ( a / ( b + c + a + d ) ) * ( i - j ) / k ) ) ) * r / ( ( a / ( b + c + a + d ) ) * ( h ) ) ) ) ) )", + "BaseFormula": "max( 0 , tma_light_operations - ( tma_fp_arith + tma_memory_operations + tma_branch_instructions ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Other_Light_Ops(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 30 & b > 60", + "BaseFormula": "metric_TMA_....Other_Light_Ops(%) > 30 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Nop_Instructions", + "LegacyName": "metric_TMA_......Nop_Instructions(%)", + "ParentCategory": "Other_Light_Ops", + "Level": 4, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "e" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "f" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + }, + { + "Name": "UOPS_DECODED.DEC0", + "Alias": "i" + }, + { + "Name": "UOPS_DECODED.DEC0:c1", + "Alias": "j" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "k" + }, + { + "Name": "INST_RETIRED.NOP", + "Alias": "l" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( ( ( e / f ) * g / ( h ) ) + ( a / ( b + c + a + d ) ) * ( i - j ) / k ) ) ) * l / ( ( a / ( b + c + a + d ) ) * ( h ) ) )", + "BaseFormula": "tma_light_operations * inst_retired.nop / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Nop_Instructions(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Other_Light_Ops(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 30 & c > 60", + "BaseFormula": "metric_TMA_......Nop_Instructions(%) > 10 & metric_TMA_....Other_Light_Ops(%) > 30 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvBO;Pipeline", + "LocateWith": "INST_RETIRED.NOP" + }, + { + "MetricName": "Heavy_Operations", + "LegacyName": "metric_TMA_..Heavy_Operations(%)", + "ParentCategory": "Retiring", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations , instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.([ICL+] Note this may overcount due to approximation using indirect events; [ADL+])", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "g" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "h" + }, + { + "Name": "UOPS_DECODED.DEC0", + "Alias": "i" + }, + { + "Name": "UOPS_DECODED.DEC0:c1", + "Alias": "j" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "k" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a / b ) * c / ( d ) ) + ( e / ( f + g + e + h ) ) * ( i - j ) / k )", + "BaseFormula": "tma_microcode_sequencer + tma_retiring * ( uops_decoded.dec0 - uops_decoded.dec0:c1 ) / idq.mite_uops", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Retire;TmaL2", + "LocateWith": "#NA" + }, + { + "MetricName": "Few_Uops_Instructions", + "LegacyName": "metric_TMA_....Few_Uops_Instructions(%)", + "ParentCategory": "Heavy_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or more uops. This highly-correlates with the number of uops in such instructions.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "g" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "h" + }, + { + "Name": "UOPS_DECODED.DEC0", + "Alias": "i" + }, + { + "Name": "UOPS_DECODED.DEC0:c1", + "Alias": "j" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "k" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( ( a / b ) * c / ( d ) ) + ( e / ( f + g + e + h ) ) * ( i - j ) / k ) - ( ( a / b ) * c / ( d ) ) )", + "BaseFormula": "tma_heavy_operations - tma_microcode_sequencer", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Few_Uops_Instructions(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 5 & b > 10", + "BaseFormula": "metric_TMA_....Few_Uops_Instructions(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "$issueD0" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "Microcode_Sequencer", + "LegacyName": "metric_TMA_....Microcode_Sequencer(%)", + "ParentCategory": "Heavy_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / b ) * c / ( d ) )", + "BaseFormula": "( uops_retired.slots / uops_issued.any ) * idq.ms_uops / tma_info_thread_slots", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Microcode_Sequencer(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 5 & b > 10", + "BaseFormula": "metric_TMA_....Microcode_Sequencer(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "$issueMC, $issueMS" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq", + "LocateWith": "IDQ.MS_UOPS" + }, + { + "MetricName": "Assists", + "LegacyName": "metric_TMA_......Assists(%)", + "ParentCategory": "Microcode_Sequencer", + "Level": 4, + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ASSISTS.ANY", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( ( 34 ) * a / ( b ) )", + "BaseFormula": "( 34 ) * assists.any / tma_info_thread_slots", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Assists(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Microcode_Sequencer(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 10 & b > 5 & c > 10", + "BaseFormula": "metric_TMA_......Assists(%) > 10 & metric_TMA_....Microcode_Sequencer(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvIO", + "LocateWith": "ASSISTS.ANY" + }, + { + "MetricName": "FP_Assists", + "LegacyName": "metric_TMA_........FP_Assists(%)", + "ParentCategory": "Assists", + "Level": 5, + "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ASSISTS.FP", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 34 * a / ( b ) )", + "BaseFormula": "34 * assists.fp / tma_info_thread_slots", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........FP_Assists(%)" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_........FP_Assists(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC", + "LocateWith": "" + }, + { + "MetricName": "CISC", + "LegacyName": "metric_TMA_......CISC(%)", + "ParentCategory": "Microcode_Sequencer", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "d" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( ( a / b ) * c / ( d ) ) - ( ( 34 ) * e / ( d ) ) ) )", + "BaseFormula": "max( 0 , tma_microcode_sequencer - tma_assists )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......CISC(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Microcode_Sequencer(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 10 & b > 5 & c > 10", + "BaseFormula": "metric_TMA_......CISC(%) > 10 & metric_TMA_....Microcode_Sequencer(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "#NA" + }, + { + "MetricName": "Info_Botlnk_L0_Core_Bound_Likely", + "LegacyName": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely", + "Level": 1, + "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Alias": "g" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "h" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "i" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "k" + }, + { + "Name": "EXE_ACTIVITY.3_PORTS_UTIL:u0x80", + "Alias": "l" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "m" + }, + { + "Name": "ARITH.DIVIDER_ACTIVE", + "Alias": "n" + }, + { + "Name": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "Alias": "o" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "Alias": "p" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( 1 - ( max( 0 , ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) - ( ( ( g + h ) / ( i + ( j + ( d / ( b + c + d + a ) ) * k ) + h ) ) * ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) ) ) ) / ( ( ( l / ( m ) ) * ( m ) + ( j + ( d / ( b + c + d + a ) ) * k ) ) / ( m ) if ( n < ( i - g ) ) else ( j + ( d / ( b + c + d + a ) ) * k ) / ( m ) ) if ( max( 0 , ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) - ( ( ( g + h ) / ( i + ( j + ( d / ( b + c + d + a ) ) * k ) + h ) ) * ( a / ( b + c + d + a ) + ( ( 5 ) * e ) / ( f ) ) ) ) ) < ( ( ( l / ( m ) ) * ( m ) + ( j + ( d / ( b + c + d + a ) ) * k ) ) / ( m ) if ( n < ( i - g ) ) else ( j + ( d / ( b + c + d + a ) ) * k ) / ( m ) ) else 1 ) if ( 1 - o / p if smt_on else 0 ) > 0.5 else 0", + "BaseFormula": "100 * ( 1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1 ) if tma_info_system_smt_2t_utilization > 0.5 else 0", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely" + } + ], + "Formula": "a > 0.5", + "BaseFormula": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely > 0.5", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;SMT", + "LocateWith": "" + }, + { + "MetricName": "Info_Thread_IPC", + "LegacyName": "metric_TMA_Info_Thread_IPC", + "Level": 1, + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "BaseFormula": "inst_retired.any / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD", + "MetricGroup": "Ret;Summary", + "LocateWith": "" + }, + { + "MetricName": "Info_Thread_UopPI", + "LegacyName": "metric_TMA_Info_Thread_UopPI", + "Level": 1, + "BriefDescription": "Uops Per Instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "e" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "( ( a / ( b + c + a + d ) ) * ( e ) ) / f", + "BaseFormula": "( tma_retiring * tma_info_thread_slots ) / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Thread_UopPI" + } + ], + "Formula": "a > 1.05", + "BaseFormula": "metric_TMA_Info_Thread_UopPI > 1.05", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD", + "MetricGroup": "Pipeline;Ret;Retire", + "LocateWith": "" + }, + { + "MetricName": "Info_Thread_UpTB", + "LegacyName": "metric_TMA_Info_Thread_UpTB", + "Level": 1, + "BriefDescription": "Uops per taken branch", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "e" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "( ( a / ( b + c + a + d ) ) * ( e ) ) / f", + "BaseFormula": "( tma_retiring * tma_info_thread_slots ) / br_inst_retired.near_taken", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Thread_UpTB" + } + ], + "Formula": "a < 5 * 1.5", + "BaseFormula": "metric_TMA_Info_Thread_UpTB < 5 * 1.5", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD", + "MetricGroup": "Branches;Fed;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Thread_CPI", + "LegacyName": "metric_TMA_Info_Thread_CPI", + "Level": 1, + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1 / ( a / ( b ) )", + "BaseFormula": "1 / tma_info_thread_ipc", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD", + "MetricGroup": "Pipeline;Mem", + "LocateWith": "" + }, + { + "MetricName": "Info_Thread_CLKS", + "LegacyName": "metric_TMA_Info_Thread_CLKS", + "Level": 1, + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "BaseFormula": "cpu_clk_unhalted.thread", + "Category": "TMA", + "CountDomain": "Count", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD", + "MetricGroup": "Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Info_Thread_SLOTS", + "LegacyName": "metric_TMA_Info_Thread_SLOTS", + "Level": 1, + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "BaseFormula": "topdown.slots:perf_metrics", + "Category": "TMA", + "CountDomain": "Count", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD", + "MetricGroup": "TmaL1", + "LocateWith": "" + }, + { + "MetricName": "Info_Thread_Slots_Utilization", + "LegacyName": "metric_TMA_Info_Thread_Slots_Utilization", + "Level": 1, + "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:percore", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "( a ) / ( b / 2 ) if smt_on else 1", + "BaseFormula": "tma_info_thread_slots / ( topdown.slots:percore / 2 ) if smt_on else 1", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD", + "MetricGroup": "SMT;TmaL1", + "LocateWith": "" + }, + { + "MetricName": "Info_Thread_Execute_per_Issue", + "LegacyName": "metric_TMA_Info_Thread_Execute_per_Issue", + "Level": 1, + "BriefDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "uops_executed.thread / uops_issued.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD", + "MetricGroup": "Cor;Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Info_Core_CoreIPC", + "LegacyName": "metric_TMA_Info_Core_CoreIPC", + "Level": 1, + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "a / ( b if smt_on else ( c ) )", + "BaseFormula": "inst_retired.any / tma_info_core_core_clks", + "Category": "TMA", + "CountDomain": "Core_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "CORE", + "MetricGroup": "Ret;SMT;TmaL1", + "LocateWith": "" + }, + { + "MetricName": "Info_Core_FLOPc", + "LegacyName": "metric_TMA_Info_Core_FLOPc", + "Level": 1, + "BriefDescription": "Floating Point Operations Per Cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.4_FLOPS", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.8_FLOPS", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "e" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "( a + 2 * b + 4 * c + 8 * d + 16 * e ) / ( f if smt_on else ( g ) )", + "BaseFormula": "( fp_arith_inst_retired.scalar + 2 * fp_arith_inst_retired.128b_packed_double + 4 * fp_arith_inst_retired.4_flops + 8 * fp_arith_inst_retired.8_flops + 16 * fp_arith_inst_retired.512b_packed_single ) / tma_info_core_core_clks", + "Category": "TMA", + "CountDomain": "Core_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "CORE", + "MetricGroup": "Ret;Flops", + "LocateWith": "" + }, + { + "MetricName": "Info_Core_FP_Arith_Utilization", + "LegacyName": "metric_TMA_Info_Core_FP_Arith_Utilization", + "Level": 1, + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.VECTOR", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "( ( a ) + ( b ) ) / ( 2 * ( c if smt_on else ( d ) ) )", + "BaseFormula": "( ( fp_arith_inst_retired.scalar ) + ( fp_arith_inst_retired.vector ) ) / ( 2 * tma_info_core_core_clks )", + "Category": "TMA", + "CountDomain": "Core_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "CORE", + "MetricGroup": "Cor;Flops;HPC", + "LocateWith": "" + }, + { + "MetricName": "Info_Core_ILP", + "LegacyName": "metric_TMA_Info_Core_ILP", + "Level": 1, + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per thread (logical-processor)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "UOPS_EXECUTED.THREAD:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "uops_executed.thread / uops_executed.thread:c1", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "CORE", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", + "LocateWith": "" + }, + { + "MetricName": "Info_Core_EPC", + "LegacyName": "metric_TMA_Info_Core_EPC", + "Level": 1, + "BriefDescription": "uops Executed per Cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "BaseFormula": "uops_executed.thread / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "CORE", + "MetricGroup": "Power", + "LocateWith": "" + }, + { + "MetricName": "Info_Core_CORE_CLKS", + "LegacyName": "metric_TMA_Info_Core_CORE_CLKS", + "Level": 1, + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "a if smt_on else ( b )", + "BaseFormula": "cpu_clk_unhalted.distributed if smt_on else tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Count", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "CORE", + "MetricGroup": "SMT", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpLoad", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpLoad", + "Level": 1, + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / mem_inst_retired.all_loads", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpLoad" + } + ], + "Formula": "a < 3", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpLoad < 3", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpStore", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpStore", + "Level": 1, + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / mem_inst_retired.all_stores", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpStore" + } + ], + "Formula": "a < 8", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpStore < 8", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpBranch", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpBranch", + "Level": 1, + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / br_inst_retired.all_branches", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpBranch" + } + ], + "Formula": "a < 8", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpBranch < 8", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpCall", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpCall", + "Level": 1, + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / br_inst_retired.near_call", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpCall" + } + ], + "Formula": "a < 200", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpCall < 200", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;PGO", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpTB", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpTB", + "Level": 1, + "BriefDescription": "Instructions per taken branch", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / br_inst_retired.near_taken", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpTB" + } + ], + "Formula": "a < 5 * 2 + 1", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpTB < 5 * 2 + 1", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_BpTkBranch", + "LegacyName": "metric_TMA_Info_Inst_Mix_BpTkBranch", + "Level": 1, + "BriefDescription": "Branch instructions per taken branch.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "br_inst_retired.all_branches / br_inst_retired.near_taken", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;PGO", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpFLOP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpFLOP", + "Level": 1, + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.4_FLOPS", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED.8_FLOPS", + "Alias": "e" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "a / ( b + 2 * c + 4 * d + 8 * e + 16 * f )", + "BaseFormula": "inst_retired.any / ( fp_arith_inst_retired.scalar + 2 * fp_arith_inst_retired.128b_packed_double + 4 * fp_arith_inst_retired.4_flops + 8 * fp_arith_inst_retired.8_flops + 16 * fp_arith_inst_retired.512b_packed_single )", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpFLOP" + } + ], + "Formula": "a < 10", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpFLOP < 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpArith", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. 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Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / fp_arith_inst_retired.scalar_single", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_SP" + } + ], + "Formula": "a < 10", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_SP < 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpScalar;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_Scalar_DP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_DP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). 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Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "BaseFormula": "inst_retired.any / ( fp_arith_inst_retired.128b_packed_double + fp_arith_inst_retired.128b_packed_single )", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpArith_AVX128" + } + ], + "Formula": "a < 10", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpArith_AVX128 < 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX256", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX256", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "BaseFormula": "inst_retired.any / ( fp_arith_inst_retired.256b_packed_double + fp_arith_inst_retired.256b_packed_single )", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpArith_AVX256" + } + ], + "Formula": "a < 10", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpArith_AVX256 < 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX512", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX512", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "BaseFormula": "inst_retired.any / ( fp_arith_inst_retired.512b_packed_double + fp_arith_inst_retired.512b_packed_single )", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpArith_AVX512" + } + ], + "Formula": "a < 10", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpArith_AVX512 < 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpPause", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpPause", + "Level": 1, + "BriefDescription": "Instructions per PAUSE (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "MISC_RETIRED.PAUSE_INST", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "BaseFormula": "tma_info_inst_mix_instructions / misc_retired.pause_inst", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpSWPF", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpSWPF", + "Level": 1, + "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "SW_PREFETCH_ACCESS.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / sw_prefetch_access.any", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpSWPF" + } + ], + "Formula": "a < 100", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpSWPF < 100", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Prefetches", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_Instructions", + "LegacyName": "metric_TMA_Info_Inst_Mix_Instructions", + "Level": 1, + "BriefDescription": "Total number of retired Instructions", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "BaseFormula": "inst_retired.any", + "Category": "TMA", + "CountDomain": "Count", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary;TmaL1", + "LocateWith": "INST_RETIRED.PREC_DIST" + }, + { + "MetricName": "Info_Pipeline_Retire", + "LegacyName": "metric_TMA_Info_Pipeline_Retire", + "Level": 1, + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "e" + }, + { + "Name": "UOPS_RETIRED.SLOTS:c1", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "( ( a / ( b + c + a + d ) ) * ( e ) ) / f", + "BaseFormula": "( tma_retiring * tma_info_thread_slots ) / uops_retired.slots:c1", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline;Ret", + "LocateWith": "" + }, + { + "MetricName": "Info_Pipeline_IpAssist", + "LegacyName": "metric_TMA_Info_Pipeline_IpAssist", + "Level": 1, + "BriefDescription": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / assists.any", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Pipeline_IpAssist" + } + ], + "Formula": "a < 100000", + "BaseFormula": "metric_TMA_Info_Pipeline_IpAssist < 100000", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq;Pipeline;Ret;Retire", + "LocateWith": "" + }, + { + "MetricName": "Info_Pipeline_Execute", + "LegacyName": "metric_TMA_Info_Pipeline_Execute", + "Level": 1, + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per physical core", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "Alias": "b" + }, + { + "Name": "UOPS_EXECUTED.THREAD:c1", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "a / ( ( b / 2 ) if smt_on else c )", + "BaseFormula": "uops_executed.thread / ( ( uops_executed.core_cycles_ge_1 / 2 ) if smt_on else uops_executed.thread:c1 )", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "LocateWith": "" + }, + { + "MetricName": "Info_Pipeline_Fetch_DSB", + "LegacyName": "metric_TMA_Info_Pipeline_Fetch_DSB", + "Level": 1, + "BriefDescription": "Average number of uops fetched from DSB per cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.DSB_CYCLES_ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "idq.dsb_uops / idq.dsb_cycles_any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Pipeline_Fetch_MITE", + "LegacyName": "metric_TMA_Info_Pipeline_Fetch_MITE", + "Level": 1, + "BriefDescription": "Average number of uops fetched from MITE per cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ.MITE_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_CYCLES_ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "idq.mite_uops / idq.mite_cycles_any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Pipeline_Fetch_MS", + "LegacyName": "metric_TMA_Info_Pipeline_Fetch_MS", + "Level": 1, + "BriefDescription": "Average number of uops fetched from MS per cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ.MS_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.MS_UOPS:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "idq.ms_uops / idq.ms_uops:c1", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchLat;MicroSeq", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_Fetch_UpC", + "LegacyName": "metric_TMA_Info_Frontend_Fetch_UpC", + "Level": 1, + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "uops_issued.any / uops_issued.any:c1", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_DSB_Coverage", + "LegacyName": "metric_TMA_Info_Frontend_DSB_Coverage", + "Level": 1, + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "BaseFormula": "idq.dsb_uops / ( uops_issued.any )", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Frontend_DSB_Coverage" + }, + { + "Alias": "b", + "Value": "metric_TMA_Info_Thread_IPC" + } + ], + "Formula": "a < 0.7 & b / 5 > 0.35", + "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & metric_TMA_Info_Thread_IPC / 5 > 0.35", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSB;Fed;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_DSB_Switch_Cost", + "LegacyName": "metric_TMA_Info_Frontend_DSB_Switch_Cost", + "Level": 1, + "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "a" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES:c1:e1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "dsb2mite_switches.penalty_cycles / dsb2mite_switches.penalty_cycles:c1:e1", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_TBpC", + "LegacyName": "metric_TMA_Info_Frontend_TBpC", + "Level": 1, + "BriefDescription": "Taken Branches retired Per Cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "BaseFormula": "br_inst_retired.near_taken / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_ICache_Miss_Latency", + "LegacyName": "metric_TMA_Info_Frontend_ICache_Miss_Latency", + "Level": 1, + "BriefDescription": "Average Latency for L1 instruction cache misses", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ICACHE_16B.IFDATA_STALL", + "Alias": "a" + }, + { + "Name": "ICACHE_16B.IFDATA_STALL:c1:e1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "icache_16b.ifdata_stall / icache_16b.ifdata_stall:c1:e1", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchLat;IcMiss", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_IpDSB_Miss_Ret", + "LegacyName": "metric_TMA_Info_Frontend_IpDSB_Miss_Ret", + "Level": 1, + "BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FRONTEND_RETIRED.ANY_DSB_MISS", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / frontend_retired.any_dsb_miss", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Frontend_IpDSB_Miss_Ret" + } + ], + "Formula": "a < 50", + "BaseFormula": "metric_TMA_Info_Frontend_IpDSB_Miss_Ret < 50", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;Fed", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_IpUnknown_Branch", + "LegacyName": "metric_TMA_Info_Frontend_IpUnknown_Branch", + "Level": 1, + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "BaseFormula": "tma_info_inst_mix_instructions / baclears.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_L2MPKI_Code", + "LegacyName": "metric_TMA_Info_Frontend_L2MPKI_Code", + "Level": 1, + "BriefDescription": "L2 cache true code cacheline misses per kilo instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FRONTEND_RETIRED.L2_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": "1000 * frontend_retired.l2_miss / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "IcMiss", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_L2MPKI_Code_All", + "LegacyName": "metric_TMA_Info_Frontend_L2MPKI_Code_All", + "Level": 1, + "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.CODE_RD_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": "1000 * l2_rqsts.code_rd_miss / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "IcMiss", + "LocateWith": "" + }, + { + "MetricName": "Info_Botlnk_L2_DSB_Misses", + "LegacyName": "metric_TMA_Info_Botlnk_L2_DSB_Misses", + "Level": 1, + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "a" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "c" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "f" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "g" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "h" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "i" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "j" + }, + { + "Name": "DECODE.LCP", + "Alias": "k" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "l" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "m" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "n" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "o" + }, + { + "Name": "IDQ.MITE_CYCLES_ANY", + "Alias": "p" + }, + { + "Name": "IDQ.MITE_CYCLES_OK", + "Alias": "q" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "r" + }, + { + "Name": "IDQ.DSB_CYCLES_ANY", + "Alias": "s" + }, + { + "Name": "IDQ.DSB_CYCLES_OK", + "Alias": "t" + }, + { + "Name": "IDQ.MS_UOPS:c1", + "Alias": "u" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( ( ( 5 ) * a - b ) / ( c ) ) * ( d / ( e ) ) / ( ( f / ( e ) ) + ( g / ( e ) ) + ( h / ( e ) + ( 10 ) * i / ( e ) ) + ( ( 3 ) * j / ( e ) ) + ( k / ( e ) ) + ( d / ( e ) ) ) + ( max( 0 , ( l / ( l + m + n + o ) - b / ( c ) ) - ( ( ( 5 ) * a - b ) / ( c ) ) ) ) * ( ( p - q ) / ( r if smt_on else ( e ) ) / 2 ) / ( ( ( p - q ) / ( r if smt_on else ( e ) ) / 2 ) + ( ( s - t ) / ( r if smt_on else ( e ) ) / 2 ) + ( u / ( r if smt_on else ( e ) ) / 3.3 ) ) )", + "BaseFormula": "100 * ( tma_fetch_latency * tma_dsb_switches / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_mite / ( tma_mite + tma_dsb + tma_ms ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Misses" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Misses > 10", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;Fed", + "LocateWith": "" + }, + { + "MetricName": "Info_Botlnk_L2_DSB_Bandwidth", + "LegacyName": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth", + "Level": 1, + "BriefDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "g" + }, + { + "Name": "IDQ.DSB_CYCLES_ANY", + "Alias": "h" + }, + { + "Name": "IDQ.DSB_CYCLES_OK", + "Alias": "i" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "j" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "k" + }, + { + "Name": "IDQ.MITE_CYCLES_ANY", + "Alias": "l" + }, + { + "Name": "IDQ.MITE_CYCLES_OK", + "Alias": "m" + }, + { + "Name": "IDQ.MS_UOPS:c1", + "Alias": "n" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a / ( a + b + c + d ) - e / ( f ) ) * ( ( max( 0 , ( a / ( a + b + c + d ) - e / ( f ) ) - ( ( ( 5 ) * g - e ) / ( f ) ) ) ) / ( ( ( ( 5 ) * g - e ) / ( f ) ) + ( max( 0 , ( a / ( a + b + c + d ) - e / ( f ) ) - ( ( ( 5 ) * g - e ) / ( f ) ) ) ) ) ) * ( ( ( h - i ) / ( j if smt_on else ( k ) ) / 2 ) / ( ( ( l - m ) / ( j if smt_on else ( k ) ) / 2 ) + ( ( h - i ) / ( j if smt_on else ( k ) ) / 2 ) + ( n / ( j if smt_on else ( k ) ) / 3.3 ) ) ) )", + "BaseFormula": "100 * ( tma_frontend_bound * ( tma_fetch_bandwidth / ( tma_fetch_latency + tma_fetch_bandwidth ) ) * ( tma_dsb / ( tma_mite + tma_dsb + tma_ms ) ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth > 10", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSB;Fed;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Botlnk_L2_IC_Misses", + "LegacyName": "metric_TMA_Info_Botlnk_L2_IC_Misses", + "Level": 1, + "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "a" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "c" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "f" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "g" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "h" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "i" + }, + { + "Name": "DECODE.LCP", + "Alias": "j" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "k" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( ( 5 ) * a - b ) / ( c ) ) * ( d / ( e ) ) / ( ( d / ( e ) ) + ( f / ( e ) ) + ( g / ( e ) + ( 10 ) * h / ( e ) ) + ( ( 3 ) * i / ( e ) ) + ( j / ( e ) ) + ( k / ( e ) ) ) )", + "BaseFormula": "100 * ( tma_fetch_latency * tma_icache_misses / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Botlnk_L2_IC_Misses" + } + ], + "Formula": "a > 5", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_IC_Misses > 5", + "ThresholdIssues": "$issueFL" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchLat;IcMiss", + "LocateWith": "" + }, + { + "MetricName": "Info_Bad_Spec_IpMispredict", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMispredict", + "Level": 1, + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / br_misp_retired.all_branches", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Bad_Spec_IpMispredict" + } + ], + "Formula": "a < 200", + "BaseFormula": "metric_TMA_Info_Bad_Spec_IpMispredict < 200", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "LocateWith": "" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Cond_Ntaken", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Cond_Ntaken", + "Level": 1, + "BriefDescription": "Instructions per retired Mispredicts for conditional non-taken branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.COND_NTAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / br_misp_retired.cond_ntaken", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Bad_Spec_IpMisp_Cond_Ntaken" + } + ], + "Formula": "a < 200", + "BaseFormula": "metric_TMA_Info_Bad_Spec_IpMisp_Cond_Ntaken < 200", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts", + "LocateWith": "" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Cond_Taken", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Cond_Taken", + "Level": 1, + "BriefDescription": "Instructions per retired Mispredicts for conditional taken branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.COND_TAKEN", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / br_misp_retired.cond_taken", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Bad_Spec_IpMisp_Cond_Taken" + } + ], + "Formula": "a < 200", + "BaseFormula": "metric_TMA_Info_Bad_Spec_IpMisp_Cond_Taken < 200", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts", + "LocateWith": "" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Ret", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Ret", + "Level": 1, + "BriefDescription": "Instructions per retired Mispredicts for return branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.RET", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / br_misp_retired.ret", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Bad_Spec_IpMisp_Ret" + } + ], + "Formula": "a < 500", + "BaseFormula": "metric_TMA_Info_Bad_Spec_IpMisp_Ret < 500", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts", + "LocateWith": "" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Indirect", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Indirect", + "Level": 1, + "BriefDescription": "Instructions per retired Mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.INDIRECT", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / br_misp_retired.indirect", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Bad_Spec_IpMisp_Indirect" + } + ], + "Formula": "a < 1000", + "BaseFormula": "metric_TMA_Info_Bad_Spec_IpMisp_Indirect < 1000", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts", + "LocateWith": "" + }, + { + "MetricName": "Info_Bad_Spec_Branch_Misprediction_Cost", + "LegacyName": "metric_TMA_Info_Bad_Spec_Branch_Misprediction_Cost", + "Level": 1, + "BriefDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "d" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "e" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "g" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "h" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "i" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "j" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "k" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "l" + }, + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "m" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "n" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "o" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "p" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "q" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "r" + }, + { + "Name": "IDQ.MS_SWITCHES", + "Alias": "s" + }, + { + "Name": "DECODE.LCP", + "Alias": "t" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "u" + } + ], + "Constants": [], + "Formula": "( 100 * ( 1 - ( 10 * ( ( a / b ) * c / ( d ) ) * ( max( ( ( e / ( e + f ) ) * ( max( 1 - ( ( g / ( g + h + i + j ) - k / ( d ) ) + ( j / ( g + h + i + j ) + ( ( 5 ) * l ) / ( d ) ) + ( i / ( g + h + i + j ) ) ) , 0 ) ) ) * ( 1 - e / ( l - f ) ) , 0.0001 ) ) / ( ( e / ( e + f ) ) * ( max( 1 - ( ( g / ( g + h + i + j ) - k / ( d ) ) + ( j / ( g + h + i + j ) + ( ( 5 ) * l ) / ( d ) ) + ( i / ( g + h + i + j ) ) ) , 0 ) ) ) ) ) * ( ( ( e / ( e + f ) ) * ( max( 1 - ( ( g / ( g + h + i + j ) - k / ( d ) ) + ( j / ( g + h + i + j ) + ( ( 5 ) * l ) / ( d ) ) + ( i / ( g + h + i + j ) ) ) , 0 ) ) ) + ( ( ( 5 ) * m - k ) / ( d ) ) * ( ( e / ( e + f ) ) * n / ( o ) ) / ( ( p / ( o ) ) + ( q / ( o ) ) + ( n / ( o ) + ( 10 ) * r / ( o ) ) + ( ( 3 ) * s / ( o ) ) + ( t / ( o ) ) + ( u / ( o ) ) ) ) ) * ( d ) / ( 5 ) / e / 100", + "BaseFormula": "tma_bottleneck_mispredictions * tma_info_thread_slots / ( 5 ) / br_misp_retired.all_branches / 100", + "Category": "TMA", + "CountDomain": "Core_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "$issueBM" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts", + "LocateWith": "" + }, + { + "MetricName": "Info_Bad_Spec_Spec_Clears_Ratio", + "LegacyName": "metric_TMA_Info_Bad_Spec_Spec_Clears_Ratio", + "Level": 1, + "BriefDescription": "Speculative to Retired ratio of all clears (covering Mispredicts and nukes)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "b" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "BaseFormula": "int_misc.clears_count / ( br_misp_retired.all_branches + machine_clears.count )", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BrMispredicts", + "LocateWith": "" + }, + { + "MetricName": "Info_Branches_Cond_NT", + "LegacyName": "metric_TMA_Info_Branches_Cond_NT", + "Level": 1, + "BriefDescription": "Fraction of branches that are non-taken conditionals", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.COND_NTAKEN", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "br_inst_retired.cond_ntaken / br_inst_retired.all_branches", + "Category": "TMA", + "CountDomain": "Fraction", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "LocateWith": "" + }, + { + "MetricName": "Info_Branches_Cond_TK", + "LegacyName": "metric_TMA_Info_Branches_Cond_TK", + "Level": 1, + "BriefDescription": "Fraction of branches that are taken conditionals", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.COND_TAKEN", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "br_inst_retired.cond_taken / br_inst_retired.all_branches", + "Category": "TMA", + "CountDomain": "Fraction", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "LocateWith": "" + }, + { + "MetricName": "Info_Branches_CallRet", + "LegacyName": "metric_TMA_Info_Branches_CallRet", + "Level": 1, + "BriefDescription": "Fraction of branches that are CALL or RET", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_RETURN", + "Alias": "b" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "( a + b ) / c", + "BaseFormula": "( br_inst_retired.near_call + br_inst_retired.near_return ) / br_inst_retired.all_branches", + "Category": "TMA", + "CountDomain": "Fraction", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches", + "LocateWith": "" + }, + { + "MetricName": "Info_Branches_Jump", + "LegacyName": "metric_TMA_Info_Branches_Jump", + "Level": 1, + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.COND_TAKEN", + "Alias": "b" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "c" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "( a - b - 2 * c ) / d", + "BaseFormula": "( br_inst_retired.near_taken - br_inst_retired.cond_taken - 2 * br_inst_retired.near_call ) / br_inst_retired.all_branches", + "Category": "TMA", + "CountDomain": "Fraction", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;Branches", + "LocateWith": "" + }, + { + "MetricName": "Info_Branches_Other_Branches", + "LegacyName": "metric_TMA_Info_Branches_Other_Branches", + "Level": 1, + "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.COND_NTAKEN", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + }, + { + "Name": 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"UnitOfMeasure": "", + "Events": [ + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "BaseFormula": "l1d_pend_miss.pending / ( mem_load_retired.l1_miss + mem_load_retired.fb_hit )", + "Category": "TMA", + "CountDomain": "Clocks_Latency", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_MLP", + "LegacyName": "metric_TMA_Info_Memory_MLP", + "Level": 1, + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. 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"ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Summary;Power", + "LocateWith": "" + }, + { + "MetricName": "Info_System_Uncore_Frequency", + "LegacyName": "metric_TMA_Info_System_Uncore_Frequency", + "Level": 1, + "BriefDescription": "Measured Average Uncore Frequency for the SoC [GHz]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a ) / 1e9 / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": "tma_info_system_socket_clks / 1e9 / tma_info_system_time", + "Category": "TMA", + "CountDomain": "System_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "SoC", + "LocateWith": "" + }, + { + "MetricName": "Info_System_GFLOPs", + "LegacyName": "metric_TMA_Info_System_GFLOPs", + "Level": 1, + "BriefDescription": "Giga Floating Point Operations Per Second. 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Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 1000000000 ) * ( a / b ) / ( ( c ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "BaseFormula": "( 1000000000 ) * ( unc_cha_tor_occupancy.ia_miss_drd / unc_cha_tor_inserts.ia_miss_drd ) / ( tma_info_system_socket_clks / tma_info_system_time )", + "Category": "TMA", + "CountDomain": "NanoSeconds", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryLat;SoC", + "LocateWith": "" + }, + { + "MetricName": "Info_System_MEM_Parallel_Reads", + "LegacyName": "metric_TMA_Info_System_MEM_Parallel_Reads", + "Level": 1, + "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "unc_cha_tor_occupancy.ia_miss_drd / unc_cha_tor_occupancy.ia_miss_drd:c1", + "Category": "TMA", + "CountDomain": "System_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;SoC", + "LocateWith": "" + }, + { + "MetricName": "Info_System_MEM_DRAM_Read_Latency", + "LegacyName": "metric_TMA_Info_System_MEM_DRAM_Read_Latency", + "Level": 1, + "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "( 1000000000 ) * ( a / b ) / c", + "BaseFormula": "( 1000000000 ) * ( unc_cha_tor_occupancy.ia_miss_drd_ddr / unc_cha_tor_inserts.ia_miss_drd_ddr ) / unc_cha_clockticks:one_unit", + "Category": "TMA", + "CountDomain": "NanoSeconds", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "MemOffcore;MemoryLat;SoC;Server", + "LocateWith": "" + }, + { + "MetricName": "Info_System_IO_Read_BW", + "LegacyName": "metric_TMA_Info_System_IO_Read_BW", + "Level": 1, + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]. Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "a * 64 / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": "unc_cha_tor_inserts.io_pcirdcur * 64 / ( 1000000000 ) / tma_info_system_time", + "Category": "TMA", + "CountDomain": "GB/sec", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "IoBW;MemOffcore;SoC;Server", + "LocateWith": "" + }, + { + "MetricName": "Info_System_IO_Write_BW", + "LegacyName": "metric_TMA_Info_System_IO_Write_BW", + "Level": 1, + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]. Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", + "Alias": "c" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a + b + c + d ) * 64 / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": "( unc_cha_tor_inserts.io_hit_itom + unc_cha_tor_inserts.io_miss_itom + unc_cha_tor_inserts.io_hit_itomcachenear + unc_cha_tor_inserts.io_miss_itomcachenear ) * 64 / ( 1000000000 ) / tma_info_system_time", + "Category": "TMA", + "CountDomain": "GB/sec", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "IoBW;MemOffcore;SoC;Server", + "LocateWith": "" + }, + { + "MetricName": "Info_System_Power", + "LegacyName": "metric_TMA_Info_System_Power", + "Level": 1, + "BriefDescription": "Total package Power in Watts", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FREERUN_PKG_ENERGY_STATUS", + "Alias": "a" + }, + { + "Name": "FREERUN_DRAM_ENERGY_STATUS", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a * ( 61 ) + 15.6 * b ) / ( ( durationtimeinmilliseconds / 1000 ) * ( 1000000 ) )", + "BaseFormula": "( freerun_pkg_energy_status * ( 61 ) + 15.6 * freerun_dram_energy_status ) / ( ( duration_time ) * ( 1000000 ) )", + "Category": "TMA", + "CountDomain": "System_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Power;SoC", + "LocateWith": "" + }, + { + "MetricName": "Info_System_Time", + "LegacyName": "metric_TMA_Info_System_Time", + "Level": 1, + "BriefDescription": "Run duration time in seconds", + "UnitOfMeasure": "", + "Events": [], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( durationtimeinmilliseconds / 1000 )", + "BaseFormula": "duration_time", + "Category": "TMA", + "CountDomain": "Seconds", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_System_Time" + } + ], + "Formula": "a < 1", + "BaseFormula": "metric_TMA_Info_System_Time < 1", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Summary", + "LocateWith": "" + }, + { + "MetricName": "Info_System_MUX", + "LegacyName": "metric_TMA_Info_System_MUX", + "Level": 1, + "BriefDescription": "PerfMon Event Multiplexing accuracy indicator", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "cpu_clk_unhalted.thread_p / cpu_clk_unhalted.thread", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_System_MUX" + } + ], + "Formula": "a > 1.1 | a < 0.9", + "BaseFormula": "metric_TMA_Info_System_MUX > 1.1 | metric_TMA_Info_System_MUX < 0.9", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary", + "LocateWith": "" + }, + { + "MetricName": "Info_System_Socket_CLKS", + "LegacyName": "metric_TMA_Info_System_Socket_CLKS", + "Level": 1, + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "BaseFormula": "unc_cha_clockticks:one_unit", + "Category": "TMA", + "CountDomain": "Count", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "SoC", + "LocateWith": "" + }, + { + "MetricName": "Info_System_IpFarBranch", + "LegacyName": "metric_TMA_Info_System_IpFarBranch", + "Level": 1, + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.FAR_BRANCH:USER", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / br_inst_retired.far_branch:user", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_System_IpFarBranch" + } + ], + "Formula": "a < 1000000", + "BaseFormula": "metric_TMA_Info_System_IpFarBranch < 1000000", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;OS", + "LocateWith": "" + } + ] +} \ No newline at end of file diff --git a/cmd/metrics/resources/perfmon/icx/icelakex_uncore.json b/cmd/metrics/resources/perfmon/icx/icelakex_uncore.json new file mode 100644 index 00000000..04329668 --- /dev/null +++ b/cmd/metrics/resources/perfmon/icx/icelakex_uncore.json @@ -0,0 +1,4889 @@ +{ + "Header": { + "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for 3rd Generation Intel(R) Xeon(R) Processor Scalable Family based on Ice Lake microarchitecture - V1.28", + "DatePublished": "04/18/2025", + "Version": "1.28", + "Legend": "" + }, + "Events": [ + { + "Unit": "CHA", + "EventCode": "0x54", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_CHA_DIR_UPDATE.HA", + "BriefDescription": "Multi-socket cacheline directory state updates; memory write due to directory update from the home agent (HA) pipe", + "PublicDescription": "Counts only multi-socket cacheline directory state updates memory writes issued from the home agent (HA) pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x54", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_CHA_DIR_UPDATE.TOR", + "BriefDescription": "Multi-socket cacheline directory state updates; memory write due to directory update from (table of requests) TOR pipe", + "PublicDescription": "Counts only multi-socket cacheline directory state updates due to memory writes issued from the table of requests (TOR) pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", + "BriefDescription": "Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and are sent to the CHA's home agent", + "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x20", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE", + "BriefDescription": "Remote INVITOE requests (exclusive ownership of a cache line without receiving data) sent to the CHA's home agent", + "PublicDescription": "Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", + "BriefDescription": "Local read requests that miss the SF/LLC and are sent to the CHA's home agent", + "PublicDescription": "Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_CHA_REQUESTS.READS_REMOTE", + "BriefDescription": "Remote read requests sent to the CHA's home agent", + "PublicDescription": "Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL", + "BriefDescription": "Local write requests that miss the SF/LLC and are sent to the CHA's home agent", + "PublicDescription": "Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", + "BriefDescription": "Remote write requests sent to the CHA's home agent", + "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x00", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_CHA_CLOCKTICKS", + "BriefDescription": "Clockticks of the uncore caching and home agent (CHA)", + "PublicDescription": "Clockticks of the uncore caching and home agent (CHA)", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x59", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", + "BriefDescription": "Normal priority reads issued to the memory controller from the CHA", + "PublicDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x5B", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", + "BriefDescription": "CHA to iMC Full Line Writes Issued : Full Line Non-ISOCH", + "PublicDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA to any of the memory controller channels.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x37", + "UMask": "0x0F", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_CHA_LLC_VICTIMS.ALL", + "BriefDescription": "Lines Victimized : All Lines Victimized", + "PublicDescription": "Lines Victimized : All Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x03", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_CHA_REQUESTS.READS", + "BriefDescription": "Local read requests that miss the SF/LLC and remote read requests sent to the CHA's home agent", + "PublicDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) .", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x0c", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_CHA_REQUESTS.WRITES", + "BriefDescription": "Local write requests that miss the SF/LLC and remote write requests sent to the CHA's home agent", + "PublicDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x3D", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_CHA_SF_EVICTION.E_STATE", + "BriefDescription": "Snoop filter capacity evictions for E-state entries.", + "PublicDescription": "Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x3D", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_CHA_SF_EVICTION.M_STATE", + "BriefDescription": "Snoop filter capacity evictions for M-state entries.", + "PublicDescription": "Counts snoop filter capacity evictions for entries tracking modified lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x3D", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_CHA_SF_EVICTION.S_STATE", + "BriefDescription": "Snoop filter capacity evictions for S-state entries.", + "PublicDescription": "Counts snoop filter capacity evictions for entries tracking shared lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC001FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA", + "BriefDescription": "TOR Inserts : All requests from iA Cores", + "PublicDescription": "TOR Inserts : All requests from iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC001FD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", + "BriefDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC", + "PublicDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC80FFD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", + "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC817FD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD", + "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xCCC7FD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO", + "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC", + "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC807FD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC001FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", + "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC", + "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC80FFE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC817FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xCCC7FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO", + "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC", + "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC807FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC001FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO", + "BriefDescription": "TOR Inserts : All requests from IO Devices", + "PublicDescription": "TOR Inserts : All requests from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC001FD", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", + "BriefDescription": "TOR Inserts : All requests from IO Devices that hit the LLC", + "PublicDescription": "TOR Inserts : All requests from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC001FE", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", + "BriefDescription": "TOR Inserts : All requests from IO Devices that missed the LLC", + "PublicDescription": "TOR Inserts : All requests from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC001FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", + "BriefDescription": "TOR Occupancy : All requests from iA Cores", + "PublicDescription": "TOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC001FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", + "BriefDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC", + "PublicDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC001FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", + "BriefDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC", + "PublicDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC80FFE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", + "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC", + "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC817FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC807FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC001FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", + "BriefDescription": "TOR Occupancy : All requests from IO Devices", + "PublicDescription": "TOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC001FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", + "BriefDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC", + "PublicDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC001FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", + "BriefDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC", + "PublicDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xCC43FE", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xc803fe", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_CLOCKTICKS", + "BriefDescription": "Clockticks of the integrated IO (IIO) traffic controller", + "PublicDescription": "Clockticks of the integrated IO (IIO) traffic controller : Increments counter once every Traffic Controller clock, the LSCLK (500MHz)", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x01", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x02", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x04", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x08", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x01", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x02", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x04", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x08", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x80", + "PortMask": "0x01", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0", + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x80", + "PortMask": "0x02", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1", + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x80", + "PortMask": "0x04", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2", + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x80", + "PortMask": "0x08", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3", + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x01", + "PortMask": "0x01", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x01", + "PortMask": "0x02", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x01", + "PortMask": "0x04", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x01", + "PortMask": "0x08", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x04", + "PortMask": "0x01", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x04", + "PortMask": "0x02", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x04", + "PortMask": "0x04", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x04", + "PortMask": "0x08", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x01", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x02", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x04", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x08", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x01", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x02", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x04", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x08", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x80", + "PortMask": "0x01", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0", + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x80", + "PortMask": "0x02", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1", + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x80", + "PortMask": "0x04", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2", + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x80", + "PortMask": "0x08", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3", + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x01", + "PortMask": "0x01", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x01", + "PortMask": "0x02", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x01", + "PortMask": "0x04", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x01", + "PortMask": "0x08", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x04", + "PortMask": "0x01", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x04", + "PortMask": "0x02", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x04", + "PortMask": "0x04", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x04", + "PortMask": "0x08", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x1F", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_I_MISC1.LOST_FWD", + "BriefDescription": "Misc Events - Set 1 : Lost Forward", + "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x10", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_I_COHERENT_OPS.PCITOM", + "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.", + "PublicDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache.", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x10", + "UMask": "0x40", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_I_COHERENT_OPS.WBMTOI", + "BriefDescription": "Coherent Ops : WbMtoI", + "PublicDescription": "Coherent Ops : WbMtoI : Counts the number of coherency related operations serviced by the IRP", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xD3", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_TAGCHK.HIT", + "BriefDescription": "2LM Tag Check : Hit in Near Memory Cache", + "PublicDescription": "2LM Tag Check : Hit in Near Memory Cache", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xD3", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_TAGCHK.MISS_CLEAN", + "BriefDescription": "2LM Tag Check : Miss, no data in this line", + "PublicDescription": "2LM Tag Check : Miss, no data in this line", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xD3", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_TAGCHK.MISS_DIRTY", + "BriefDescription": "2LM Tag Check : Miss, existing data may be evicted to Far Memory", + "PublicDescription": "2LM Tag Check : Miss, existing data may be evicted to Far Memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xD3", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_TAGCHK.NM_RD_HIT", + "BriefDescription": "2LM Tag Check : Read Hit in Near Memory Cache", + "PublicDescription": "2LM Tag Check : Read Hit in Near Memory Cache", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xD3", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_TAGCHK.NM_WR_HIT", + "BriefDescription": "2LM Tag Check : Write Hit in Near Memory Cache", + "PublicDescription": "2LM Tag Check : Write Hit in Near Memory Cache", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x02", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_PRE_COUNT.RD", + "BriefDescription": "DRAM Precharge commands. : Precharge due to read", + "PublicDescription": "DRAM Precharge commands. : Precharge due to read : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from read bank scheduler", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x02", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_PRE_COUNT.WR", + "BriefDescription": "DRAM Precharge commands. : Precharge due to write", + "PublicDescription": "DRAM Precharge commands. : Precharge due to write : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from write bank scheduler", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x04", + "UMask": "0x0f", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_CAS_COUNT.RD", + "BriefDescription": "All DRAM read CAS commands issued (including underfills)", + "PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issued on this channel. This includes underfills.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x04", + "UMask": "0x30", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_CAS_COUNT.WR", + "BriefDescription": "All DRAM write CAS commands issued", + "PublicDescription": "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x04", + "UMask": "0x3f", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_CAS_COUNT.ALL", + "BriefDescription": "All DRAM CAS commands issued", + "PublicDescription": "Counts the total number of DRAM CAS commands issued on this channel.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x2D", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY", + "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in any state", + "PublicDescription": "Multi-socket cacheline Directory Lookups : Found in any state", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x2D", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A", + "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in A state", + "PublicDescription": "Multi-socket cacheline Directory Lookups : Found in A state", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x2D", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I", + "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in I state", + "PublicDescription": "Multi-socket cacheline Directory Lookups : Found in I state", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x2D", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S", + "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in S state", + "PublicDescription": "Multi-socket cacheline Directory Lookups : Found in S state", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x2e", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY", + "BriefDescription": "Multi-socket cacheline Directory Updates : From/to any state. Note: event counts are incorrect in 2LM mode.", + "PublicDescription": "Multi-socket cacheline Directory Updates : From/to any state. Note: event counts are incorrect in 2LM mode.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x2C", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN", + "BriefDescription": "Tag Hit : Clean NearMem Read Hit", + "PublicDescription": "Tag Hit : Clean NearMem Read Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts clean full line read hits (reads and RFOs).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x2C", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY", + "BriefDescription": "Tag Hit : Dirty NearMem Read Hit", + "PublicDescription": "Tag Hit : Dirty NearMem Read Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts dirty full line read hits (reads and RFOs).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x00", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M2M_CLOCKTICKS", + "BriefDescription": "Clockticks of the mesh to memory (M2M)", + "PublicDescription": "Clockticks of the mesh to memory (M2M)", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x01", + "PortMask": "0x10", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4", + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x01", + "PortMask": "0x20", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5", + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x01", + "PortMask": "0x40", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6", + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x01", + "PortMask": "0x80", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7", + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x04", + "PortMask": "0x10", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4", + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x04", + "PortMask": "0x20", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5", + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x04", + "PortMask": "0x40", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6", + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x04", + "PortMask": "0x80", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7", + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x10", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x20", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x40", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x80", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x10", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x20", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x40", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x80", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x80", + "PortMask": "0x10", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4", + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x80", + "PortMask": "0x20", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5", + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x80", + "PortMask": "0x40", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6", + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x80", + "PortMask": "0x80", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7", + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x85", + "UMask": "0x01", + "PortMask": "0xFF", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL", + "BriefDescription": "Number requests PCIe makes of the main die : All", + "PublicDescription": "Number requests PCIe makes of the main die : All : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x01", + "PortMask": "0x10", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x01", + "PortMask": "0x20", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x01", + "PortMask": "0x40", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x01", + "PortMask": "0x80", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x04", + "PortMask": "0x10", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x04", + "PortMask": "0x20", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x04", + "PortMask": "0x40", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x04", + "PortMask": "0x80", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x10", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x20", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x40", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x80", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x10", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x20", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x40", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x80", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x80", + "PortMask": "0x10", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4", + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x80", + "PortMask": "0x20", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5", + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x80", + "PortMask": "0x40", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6", + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x80", + "PortMask": "0x80", + "FCMask": "0x07", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7", + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x0f", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", + "BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory.", + "PublicDescription": "Total IRP occupancy of inbound read and write requests to coherent memory. This is effectively the sum of read occupancy and write occupancy.", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x20", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", + "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)", + "PublicDescription": ": All Inserts Inbound (p2p + faf + cset)", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x11", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "BriefDescription": "Inbound write (fast path) requests received by the IRP.", + "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x03", + "UMask": "0x0F", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", + "BriefDescription": "Valid Flits Received : All Data", + "PublicDescription": "Valid Flits Received : All Data : Shows legal flit time (hides impact of L0p and L0c).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x03", + "UMask": "0x97", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", + "BriefDescription": "Valid Flits Received : All Non Data", + "PublicDescription": "Valid Flits Received : All Non Data : Shows legal flit time (hides impact of L0p and L0c).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x02", + "UMask": "0x0F", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", + "BriefDescription": "Valid Flits Sent : All Data", + "PublicDescription": "Valid Flits Sent : All Data : Shows legal flit time (hides impact of L0p and L0c).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x02", + "UMask": "0x97", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", + "BriefDescription": "Valid Flits Sent : All Non Data", + "PublicDescription": "Valid Flits Sent : All Non Data : Shows legal flit time (hides impact of L0p and L0c).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x45", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_DRAM_REFRESH.OPPORTUNISTIC", + "BriefDescription": "Number of DRAM Refreshes Issued", + "PublicDescription": "Number of DRAM Refreshes Issued : Counts the number of refreshes issued.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x45", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_DRAM_REFRESH.PANIC", + "BriefDescription": "Number of DRAM Refreshes Issued", + "PublicDescription": "Number of DRAM Refreshes Issued : Counts the number of refreshes issued.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x45", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_DRAM_REFRESH.HIGH", + "BriefDescription": "Number of DRAM Refreshes Issued", + "PublicDescription": "Number of DRAM Refreshes Issued : Counts the number of refreshes issued.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x10", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_RPQ_INSERTS.PCH0", + "BriefDescription": "Read Pending Queue Allocations", + "PublicDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x10", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_RPQ_INSERTS.PCH1", + "BriefDescription": "Read Pending Queue Allocations", + "PublicDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x20", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_WPQ_INSERTS.PCH0", + "BriefDescription": "Write Pending Queue Allocations", + "PublicDescription": "Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x20", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_WPQ_INSERTS.PCH1", + "BriefDescription": "Write Pending Queue Allocations", + "PublicDescription": "Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x02", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_PRE_COUNT.PGT", + "BriefDescription": "DRAM Precharge commands. : Precharge due to page table", + "PublicDescription": "DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel. : Precharges from Page Table", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0xc0", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_CHA_CMS_CLOCKTICKS", + "BriefDescription": "CMS Clockticks", + "PublicDescription": "CMS Clockticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_I_CLOCKTICKS", + "BriefDescription": "Clockticks of the IO coherency tracker (IRP)", + "PublicDescription": "Clockticks of the IO coherency tracker (IRP)", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x17", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_I_FAF_FULL", + "BriefDescription": "FAF RF full", + "PublicDescription": "FAF RF full", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x18", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_I_FAF_INSERTS", + "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.", + "PublicDescription": "Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP.", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x19", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_I_FAF_OCCUPANCY", + "BriefDescription": "Occupancy of the IRP FAF queue.", + "PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP.", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x16", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_I_FAF_TRANSACTIONS", + "BriefDescription": "FAF allocation -- sent to ADQ", + "PublicDescription": "FAF allocation -- sent to ADQ", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0xc0", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M2M_CMS_CLOCKTICKS", + "BriefDescription": "CMS Clockticks", + "PublicDescription": "CMS Clockticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2PCIe", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M2P_CLOCKTICKS", + "BriefDescription": "Clockticks of the mesh to PCI (M2P)", + "PublicDescription": "Clockticks of the mesh to PCI (M2P) : Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2PCIe", + "EventCode": "0xc0", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M2P_CMS_CLOCKTICKS", + "BriefDescription": "CMS Clockticks", + "PublicDescription": "CMS Clockticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M3UPI", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M3UPI_CLOCKTICKS", + "BriefDescription": "Clockticks of the mesh to UPI (M3UPI)", + "PublicDescription": "Clockticks of the mesh to UPI (M3UPI) : Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "PCU", + "EventCode": "0x00", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_P_CLOCKTICKS", + "BriefDescription": "Clockticks of the power control unit (PCU)", + "PublicDescription": "Clockticks of the power control unit (PCU) : The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_UPI_CLOCKTICKS", + "BriefDescription": "Number of kfclks", + "PublicDescription": "Number of kfclks : Counts the number of clocks in the UPI LL. This clock runs at 1/8th the GT/s speed of the UPI link. For example, a 8GT/s link will have qfclk or 1GHz. Current products do not support dynamic link speeds, so this frequency is fixed.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x21", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_UPI_L1_POWER_CYCLES", + "BriefDescription": "Cycles in L1", + "PublicDescription": "Cycles in L1 : Number of UPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a UPI link. Use edge detect to count the number of instances when the UPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x27", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES", + "BriefDescription": "Cycles in L0p", + "PublicDescription": "Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses. Use edge detect to count the number of instances when the UPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x00", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_CLOCKTICKS", + "BriefDescription": "DRAM Clockticks", + "PublicDescription": "DRAM Clockticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC88FFD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF", + "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC897FD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF", + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC", + "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC887FD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF", + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC88FFE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", + "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC897FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF", + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC", + "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC887FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xCC43FD", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UBOX", + "EventCode": "0x00", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_U_CLOCKTICKS", + "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter", + "PublicDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter", + "Counter": "FIXED", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "FIXED" + }, + { + "Unit": "iMC", + "EventCode": "0x00", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_HCLOCKTICKS", + "BriefDescription": "Half clockticks for IMC", + "PublicDescription": "Half clockticks for IMC", + "Counter": "FIXED", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "FIXED" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC803FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO", + "BriefDescription": "TOR Inserts : RFOs issued by IO Devices", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xCC43FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC887FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF", + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC807FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO", + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xCCC7FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO", + "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores", + "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC897FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF", + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores", + "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC80FFF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD", + "BriefDescription": "TOR Inserts : CRDs issued by iA Cores", + "PublicDescription": "TOR Inserts : CRDs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC807FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO", + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC817FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD", + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC80FFF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD", + "BriefDescription": "TOR Occupancy : CRDs issued by iA Cores", + "PublicDescription": "TOR Occupancy : CRDs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x02", + "UMask": "0x27", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", + "BriefDescription": "Valid Flits Sent : Null FLITs transmitted to any slot", + "PublicDescription": "Valid Flits Sent : Null FLITs transmitted to any slot : Shows legal flit time (hides impact of L0p and L0c).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x03", + "UMask": "0x27", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", + "BriefDescription": "Valid Flits Received : Null FLITs received from any slot", + "PublicDescription": "Valid Flits Received : Null FLITs received from any slot : Shows legal flit time (hides impact of L0p and L0c).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x80", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0", + "BriefDescription": "Read Pending Queue Occupancy", + "PublicDescription": "Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x81", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1", + "BriefDescription": "Read Pending Queue Occupancy", + "PublicDescription": "Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x82", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0", + "BriefDescription": "Write Pending Queue Occupancy", + "PublicDescription": "Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x83", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1", + "BriefDescription": "Write Pending Queue Occupancy", + "PublicDescription": "Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x01", + "UMask": "0x0B", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_ACT_COUNT.ALL", + "BriefDescription": "DRAM Activate Count : All Activates", + "PublicDescription": "DRAM Activate Count : All Activates : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x02", + "UMask": "0x1C", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_PRE_COUNT.ALL", + "BriefDescription": "DRAM Precharge commands.", + "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC816FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL", + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC8177E", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE", + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC816FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", + "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC8177E", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", + "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC896FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL", + "BriefDescription": "TOR Inserts; DRd Pref misses from local IA", + "PublicDescription": "TOR Inserts; Data read prefetch from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC8977E", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE", + "BriefDescription": "TOR Inserts; DRd Pref misses from local IA", + "PublicDescription": "TOR Inserts; Data read prefetch from remote IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC806FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL", + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC8077E", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE", + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC886FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL", + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC8877E", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE", + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC8C7FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH", + "BriefDescription": "TOR Inserts : CLFlushes issued by iA Cores", + "PublicDescription": "TOR Inserts : CLFlushes issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xCC57FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM", + "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores", + "PublicDescription": "TOR Inserts : SpecItoMs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xCD43FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xCD43FD", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xCD43FE", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC8178A", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM", + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC8168A", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM", + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC8170A", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM", + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xc867fe", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR", + "BriefDescription": "TOR Inserts; WCiLF misses from local IA", + "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xc86ffe", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR", + "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC8178A", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM", + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x00", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_CLOCKTICKS_FREERUN", + "BriefDescription": "Free running counter that increments for IIO clocktick", + "PublicDescription": "Free running counter that increments for integrated IO (IIO) traffic controller clockticks", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "FREERUN" + }, + { + "Unit": "iMC", + "EventCode": "0xE0", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL", + "BriefDescription": "PMM Read Pending Queue Occupancy", + "PublicDescription": "PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xE3", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_PMM_RPQ_INSERTS", + "BriefDescription": "PMM Read Queue Inserts", + "PublicDescription": "PMM Read Queue Inserts : Counts number of read requests allocated in the PMM Read Pending Queue. This includes both ISOCH and non-ISOCH requests.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xE7", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_PMM_WPQ_INSERTS", + "BriefDescription": "PMM Write Queue Inserts", + "PublicDescription": "PMM Write Queue Inserts : Counts number of write requests allocated in the PMM Write Pending Queue.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xEA", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_PMM_CMD1.ALL", + "BriefDescription": "PMM Commands : All", + "PublicDescription": "PMM Commands : All : Counts all commands issued to PMM", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xEA", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_PMM_CMD1.RD", + "BriefDescription": "PMM Commands : Reads - RPQ", + "PublicDescription": "PMM Commands : Reads - RPQ : Counts read requests issued to the PMM RPQ", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xEA", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_PMM_CMD1.WR", + "BriefDescription": "PMM Commands : Writes", + "PublicDescription": "PMM Commands : Writes : Counts write commands issued to PMM", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xEA", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_PMM_CMD1.UFILL_RD", + "BriefDescription": "PMM Commands : Underfill reads", + "PublicDescription": "PMM Commands : Underfill reads : Counts underfill read commands, due to a partial write, issued to PMM", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xE4", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL", + "BriefDescription": "PMM Write Pending Queue Occupancy", + "PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x37", + "UMask": "0x20", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x07", + "EventName": "UNC_M2M_IMC_READS.TO_PMM", + "BriefDescription": "M2M Reads Issued to iMC : PMM - All Channels", + "PublicDescription": "M2M Reads Issued to iMC : PMM - All Channels", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x38", + "UMask": "0x80", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x1C", + "EventName": "UNC_M2M_IMC_WRITES.TO_PMM", + "BriefDescription": "M2M Writes Issued to iMC : PMM - All Channels", + "PublicDescription": "M2M Writes Issued to iMC : PMM - All Channels", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xCCD7FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", + "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC", + "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC8F3FE", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xc8f3fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR", + "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC81786", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC81686", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR", + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC81706", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR", + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC81786", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR", + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC8F3FD", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR", + "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC8F3FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xCCD7FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA", + "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores", + "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC8F3FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR", + "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x34", + "UMask": "0xFF", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x1BC1", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ", + "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc2", + "UMask": "0x03", + "PortMask": "0x01", + "FCMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc2", + "UMask": "0x03", + "PortMask": "0x02", + "FCMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc2", + "UMask": "0x03", + "PortMask": "0x04", + "FCMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc2", + "UMask": "0x03", + "PortMask": "0x08", + "FCMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc2", + "UMask": "0x03", + "PortMask": "0x10", + "FCMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4", + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc2", + "UMask": "0x03", + "PortMask": "0x20", + "FCMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5", + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 5", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc2", + "UMask": "0x03", + "PortMask": "0x40", + "FCMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6", + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 6", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc2", + "UMask": "0x03", + "PortMask": "0x80", + "FCMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7", + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 7", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xd5", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xd5", + "UMask": "0x80", + "PortMask": "0x00", + "FCMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7", + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 7", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 7 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xd5", + "UMask": "0x40", + "PortMask": "0x00", + "FCMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6", + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 6", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 6 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xd5", + "UMask": "0x20", + "PortMask": "0x00", + "FCMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5", + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 5", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 5 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xd5", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4", + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 4", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 4 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xd5", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 3", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 3 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xd5", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 2", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xd5", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x12", + "UMask": "0x78", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", + "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc2", + "UMask": "0x03", + "PortMask": "0xff", + "FCMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xd5", + "UMask": "0xff", + "PortMask": "0x00", + "FCMask": "0x04", + "UMaskExt": "0x00", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xCC42FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL", + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to locally HOMed memory", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xCC437F", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE", + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to remotely HOMed memory", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xCD42FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL", + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to locally HOMed memory", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xCD437F", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE", + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to remotely HOMed memory", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC8F37F", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE", + "BriefDescription": "PCIRDCUR (read) transactions from an IO device that addresses memory on a remote socket", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices and targets remote memory : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0xC8F2FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL", + "BriefDescription": "PCIRDCUR (read) transactions from an IO device that addresses memory on the local socket", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices and targets local memory : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + } + ] +} \ No newline at end of file diff --git a/cmd/metrics/resources/perfmon/icx/icx.json b/cmd/metrics/resources/perfmon/icx/icx.json new file mode 100644 index 00000000..495f3ae9 --- /dev/null +++ b/cmd/metrics/resources/perfmon/icx/icx.json @@ -0,0 +1,1917 @@ +{ + "Header": { + "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", + "Info": "PerfSpect Performance Monitoring Metrics for Intel(R) 3rd Generation Xeon(R) (Ice Lake)" + }, + "PerfmonMetricsFile": "icelakex_metrics.json", + "PerfmonCoreEventsFile": "icelakex_core.json", + "PerfmonUncoreEventsFile": "icelakex_uncore.json", + "PerfmonRetireLatencyFile": "", + "ReportMetrics": [ + { + "MetricName": "cpu_operating_frequency", + "LegacyName": "metric_CPU operating frequency (in GHz)", + "Origin": "perfmon" + }, + { + "MetricName": "cpu_utilization", + "LegacyName": "metric_CPU utilization %", + "Origin": "perfmon" + }, + { + "MetricName": "cpu_util_kernel", + "LegacyName": "metric_CPU utilization % in kernel mode", + "Origin": "perfspect" + }, + { + "MetricName": "cpi", + "LegacyName": "metric_CPI", + "Origin": "perfmon" + }, + { + "MetricName": "cycles_per_txn", + "LegacyName": "metric_cycles per txn", + "Origin": "perfspect" + }, + { + "MetricName": "kernel_cpi", + "LegacyName": "metric_kernel_CPI", + "Origin": "perfspect" + }, + { + "MetricName": "kernel_cycles_per_txn", + "LegacyName": "metric_kernel_cycles per txn", + "Origin": "perfspect" + }, + { + "MetricName": "ipc", + "LegacyName": "metric_IPC", + "Origin": "perfspect" + }, + { + "MetricName": "giga_instructions_per_sec", + "LegacyName": "metric_giga_instructions_per_sec", + "Origin": "perfspect" + }, + { + "MetricName": "branch_misprediction_ratio", + "LegacyName": "metric_branch misprediction ratio", + "Origin": "perfspect" + }, + { + "MetricName": "locks_retired_per_instr", + "LegacyName": "metric_locks retired per instr", + "Origin": "perfspect" + }, + { + "MetricName": "locks_retired_per_txn", + "LegacyName": "metric_locks retired per txn", + "Origin": "perfspect" + }, + { + "MetricName": "l1d_mpi", + "LegacyName": "metric_L1D MPI (includes data+rfo w/ prefetches)", + "Origin": "perfmon" + }, + { + "MetricName": "l1d_misses_per_txn", + "LegacyName": "metric_L1D misses per txn (includes data+rfo w/ prefetches)", + "Origin": "perfspect" + }, + { + "MetricName": "l1d_demand_data_read_hits_per_instr", + "LegacyName": "metric_L1D demand data read hits per instr", + "Origin": "perfmon" + }, + { + "MetricName": "l1d_demand_data_read_hits_per_txn", + "LegacyName": "metric_L1D demand data read hits per txn", + "Origin": "perfspect" + }, + { + "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", + "LegacyName": "metric_L1-I code read misses (w/ prefetches) per instr", + "Origin": "perfmon" + }, + { + "MetricName": "l1i_code_read_misses_per_txn", + "LegacyName": "metric_L1I code read misses (includes prefetches) per txn", + "Origin": "perfspect" + }, + { + "MetricName": "l2_demand_data_read_hits_per_instr", + "LegacyName": "metric_L2 demand data read hits per instr", + "Origin": "perfmon" + }, + { + "MetricName": "l2_demand_data_read_hits_per_txn", + "LegacyName": "metric_L2 demand data read hits per txn", + "Origin": "perfspect" + }, + { + "MetricName": "l2_mpi", + "LegacyName": "metric_L2 MPI (includes code+data+rfo w/ prefetches)", + "Origin": "perfmon" + }, + { + "MetricName": "l2_misses_per_txn", + "LegacyName": "metric_L2 misses per txn (includes code+data+rfo w/ prefetches)", + "Origin": "perfspect" + }, + { + "MetricName": "l2_demand_data_read_mpi", + "LegacyName": "metric_L2 demand data read MPI", + "Origin": "perfmon" + }, + { + "MetricName": "l2_demand_data_read_misses_per_txn", + "LegacyName": "metric_L2 demand data read misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "l2_demand_code_mpi", + "LegacyName": "metric_L2 demand code MPI", + "Origin": "perfmon" + }, + { + "MetricName": "l2_demand_code_misses_per_txn", + "LegacyName": "metric_L2 demand code misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "llc_code_read_mpi_demand_plus_prefetch", + "LegacyName": "metric_LLC code read MPI (demand+prefetch)", + "Origin": "perfmon" + }, + { + "MetricName": "llc_code_read_misses_per_txn", + "LegacyName": "metric_LLC code read (demand+prefetch) misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "llc_data_read_mpi_demand_plus_prefetch", + "LegacyName": "metric_LLC data read MPI (demand+prefetch)", + "Origin": "perfmon" + }, + { + "MetricName": "llc_data_read_misses_per_txn", + "LegacyName": "metric_LLC data read (demand+prefetch) misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "llc_demand_data_read_miss_latency", + "LegacyName": "metric_Average LLC demand data read miss latency (in ns)", + "Origin": "perfmon" + }, + { + "MetricName": "llc_demand_data_read_miss_latency_for_local_requests", + "LegacyName": "metric_Average LLC demand data read miss latency for LOCAL requests (in ns)", + "Origin": "perfmon" + }, + { + "MetricName": "llc_demand_data_read_miss_latency_for_remote_requests", + "LegacyName": "metric_Average LLC demand data read miss latency for REMOTE requests (in ns)", + "Origin": "perfmon" + }, + { + "MetricName": "upi_data_transmit_bw", + "LegacyName": "metric_UPI Data transmit BW (MB/sec) (only data)", + "Origin": "perfmon" + }, + { + "MetricName": "package_power", + "LegacyName": "metric_package power (watts)", + "Origin": "perfspect" + }, + { + "MetricName": "dram_power", + "LegacyName": "metric_DRAM power (watts)", + "Origin": "perfspect" + }, + { + "MetricName": "core_c6_residency", + "LegacyName": "metric_core c6 residency %", + "Origin": "perfspect" + }, + { + "MetricName": "package_c6_residency", + "LegacyName": "metric_package c6 residency %", + "Origin": "perfspect" + }, + { + "MetricName": "percent_uops_delivered_from_decoded_icache", + "LegacyName": "metric_% Uops delivered from decoded Icache (DSB)", + "Origin": "perfmon" + }, + { + "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline", + "LegacyName": "metric_% Uops delivered from legacy decode pipeline (MITE)", + "Origin": "perfmon" + }, + { + "MetricName": "memory_bandwidth_read", + "LegacyName": "metric_memory bandwidth read (MB/sec)", + "Origin": "perfmon" + }, + { + "MetricName": "memory_bandwidth_write", + "LegacyName": "metric_memory bandwidth write (MB/sec)", + "Origin": "perfmon" + }, + { + "MetricName": "memory_bandwidth_total", + "LegacyName": "metric_memory bandwidth total (MB/sec)", + "Origin": "perfmon" + }, + { + "MetricName": "itlb_2nd_level_mpi", + "LegacyName": "metric_ITLB (2nd level) MPI", + "Origin": "perfmon" + }, + { + "MetricName": "itlb_misses_per_txn", + "LegacyName": "metric_ITLB (2nd level) misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "dtlb_2nd_level_load_mpi", + "LegacyName": "metric_DTLB (2nd level) load MPI", + "Origin": "perfmon" + }, + { + "MetricName": "dtlb_load_misses_per_txn", + "LegacyName": "metric_DTLB (2nd level) load misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "dtlb_2nd_level_store_mpi", + "LegacyName": "metric_DTLB (2nd level) store MPI", + "Origin": "perfmon" + }, + { + "MetricName": "dtlb_store_misses_per_txn", + "LegacyName": "metric_DTLB (2nd level) store misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "numa_reads_addressed_to_local_dram", + "LegacyName": "metric_NUMA %_Reads addressed to local DRAM", + "Origin": "perfmon" + }, + { + "MetricName": "numa_reads_addressed_to_remote_dram", + "LegacyName": "metric_NUMA %_Reads addressed to remote DRAM", + "Origin": "perfmon" + }, + { + "MetricName": "uncore_frequency", + "LegacyName": "metric_uncore frequency GHz", + "Origin": "perfmon" + }, + { + "MetricName": "io_bandwidth_write", + "LegacyName": "metric_IO_bandwidth_disk_or_network_writes (MB/sec)", + "Origin": "perfmon" + }, + { + "MetricName": "io_bandwidth_read", + "LegacyName": "metric_IO_bandwidth_disk_or_network_reads (MB/sec)", + "Origin": "perfmon" + }, + { + "MetricName": "Frontend_Bound", + "LegacyName": "metric_TMA_Frontend_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Fetch_Latency", + "LegacyName": "metric_TMA_..Fetch_Latency(%)", + "Origin": "perfmon" + }, + { + "MetricName": "ICache_Misses", + "LegacyName": "metric_TMA_....ICache_Misses(%)", + "Origin": "perfmon" + }, + { + "MetricName": "ITLB_Misses", + "LegacyName": "metric_TMA_....ITLB_Misses(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Branch_Resteers", + "LegacyName": "metric_TMA_....Branch_Resteers(%)", + "Origin": "perfmon" + }, + { + "MetricName": "MS_Switches", + "LegacyName": "metric_TMA_....MS_Switches(%)", + "Origin": "perfmon" + }, + { + "MetricName": "LCP", + "LegacyName": "metric_TMA_....LCP(%)", + "Origin": "perfmon" + }, + { + "MetricName": "DSB_Switches", + "LegacyName": "metric_TMA_....DSB_Switches(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Fetch_Bandwidth", + "LegacyName": "metric_TMA_..Fetch_Bandwidth(%)", + "Origin": "perfmon" + }, + { + "MetricName": "MITE", + "LegacyName": "metric_TMA_....MITE(%)", + "Origin": "perfmon" + }, + { + "MetricName": "DSB", + "LegacyName": "metric_TMA_....DSB(%)", + "Origin": "perfmon" + }, + { + "MetricName": "MS", + "LegacyName": "metric_TMA_....MS(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Bad_Speculation", + "LegacyName": "metric_TMA_Bad_Speculation(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Branch_Mispredicts", + "LegacyName": "metric_TMA_..Branch_Mispredicts(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Other_Mispredicts", + "LegacyName": "metric_TMA_....Other_Mispredicts(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Machine_Clears", + "LegacyName": "metric_TMA_..Machine_Clears(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Other_Nukes", + "LegacyName": "metric_TMA_....Other_Nukes(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Backend_Bound", + "LegacyName": "metric_TMA_Backend_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Memory_Bound", + "LegacyName": "metric_TMA_..Memory_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "L1_Bound", + "LegacyName": "metric_TMA_....L1_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "DTLB_Load", + "LegacyName": "metric_TMA_......DTLB_Load(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Store_Fwd_Blk", + "LegacyName": "metric_TMA_......Store_Fwd_Blk(%)", + "Origin": "perfmon" + }, + { + "MetricName": "L1_Latency_Dependency", + "LegacyName": "metric_TMA_......L1_Latency_Dependency(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Lock_Latency", + "LegacyName": "metric_TMA_......Lock_Latency(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Split_Loads", + "LegacyName": "metric_TMA_......Split_Loads(%)", + "Origin": "perfmon" + }, + { + "MetricName": "FB_Full", + "LegacyName": "metric_TMA_......FB_Full(%)", + "Origin": "perfmon" + }, + { + "MetricName": "L2_Bound", + "LegacyName": "metric_TMA_....L2_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "L3_Bound", + "LegacyName": "metric_TMA_....L3_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Contested_Accesses", + "LegacyName": "metric_TMA_......Contested_Accesses(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Data_Sharing", + "LegacyName": "metric_TMA_......Data_Sharing(%)", + "Origin": "perfmon" + }, + { + "MetricName": "L3_Hit_Latency", + "LegacyName": "metric_TMA_......L3_Hit_Latency(%)", + "Origin": "perfmon" + }, + { + "MetricName": "SQ_Full", + "LegacyName": "metric_TMA_......SQ_Full(%)", + "Origin": "perfmon" + }, + { + "MetricName": "DRAM_Bound", + "LegacyName": "metric_TMA_....DRAM_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "MEM_Bandwidth", + "LegacyName": "metric_TMA_......MEM_Bandwidth(%)", + "Origin": "perfmon" + }, + { + "MetricName": "MEM_Latency", + "LegacyName": "metric_TMA_......MEM_Latency(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Store_Bound", + "LegacyName": "metric_TMA_....Store_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Store_Latency", + "LegacyName": "metric_TMA_......Store_Latency(%)", + "Origin": "perfmon" + }, + { + "MetricName": "False_Sharing", + "LegacyName": "metric_TMA_......False_Sharing(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Split_Stores", + "LegacyName": "metric_TMA_......Split_Stores(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Streaming_Stores", + "LegacyName": "metric_TMA_......Streaming_Stores(%)", + "Origin": "perfmon" + }, + { + "MetricName": "DTLB_Store", + "LegacyName": "metric_TMA_......DTLB_Store(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Core_Bound", + "LegacyName": "metric_TMA_..Core_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Divider", + "LegacyName": "metric_TMA_....Divider(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Serializing_Operation", + "LegacyName": "metric_TMA_....Serializing_Operation(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Ports_Utilization", + "LegacyName": "metric_TMA_....Ports_Utilization(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Retiring", + "LegacyName": "metric_TMA_Retiring(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Light_Operations", + "LegacyName": "metric_TMA_..Light_Operations(%)", + "Origin": "perfmon" + }, + { + "MetricName": "FP_Arith", + "LegacyName": "metric_TMA_....FP_Arith(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Memory_Operations", + "LegacyName": "metric_TMA_....Memory_Operations(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Branch_Instructions", + "LegacyName": "metric_TMA_....Branch_Instructions(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Other_Light_Ops", + "LegacyName": "metric_TMA_....Other_Light_Ops(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Heavy_Operations", + "LegacyName": "metric_TMA_..Heavy_Operations(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Few_Uops_Instructions", + "LegacyName": "metric_TMA_....Few_Uops_Instructions(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Microcode_Sequencer", + "LegacyName": "metric_TMA_....Microcode_Sequencer(%)", + "Origin": "perfmon" + } +], + "Metrics": [ + { + "MetricName": "cpu_util_kernel", + "LegacyName": "metric_CPU utilization % in kernel mode", + "BriefDescription": "CPU utilization percentage in kernel mode", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + }, + { + "Name": "TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * (a / b)", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "cycles_per_txn", + "LegacyName": "metric_cycles per txn", + "BriefDescription": "Number of cycles per transaction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "kernel_cpi", + "LegacyName": "metric_kernel_CPI", + "BriefDescription": "Kernel cycles per instruction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "kernel_cycles_per_txn", + "LegacyName": "metric_kernel_cycles per txn", + "BriefDescription": "Number of kernel cycles per transaction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "ipc", + "LegacyName": "metric_IPC", + "BriefDescription": "Instructions per cycle", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "giga_instructions_per_sec", + "LegacyName": "metric_giga_instructions_per_sec", + "BriefDescription": "Billions of instructions per second", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + } + ], + "Constants": [ + ], + "Formula": "a / 1000000000", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "branch_misprediction_ratio", + "LegacyName": "metric_branch misprediction ratio", + "BriefDescription": "Ratio of branch mispredictions to the total number of branches retired.", + "Events": [ + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "locks_retired_per_instr", + "LegacyName": "metric_locks retired per instr", + "BriefDescription": "Locks retired per instruction", + "Events": [ + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "locks_retired_per_txn", + "LegacyName": "metric_locks retired per txn", + "BriefDescription": "Locks retired per transaction", + "Events": [ + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l1d_misses_per_txn", + "LegacyName": "metric_L1D misses per txn (includes data+rfo w/ prefetches)", + "BriefDescription": "L1D misses per transaction (includes data+rfo with prefetches)", + "Events": [ + { + "Name": "L1D.REPLACEMENT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l1d_demand_data_read_hits_per_txn", + "LegacyName": "metric_L1D demand data read hits per txn", + "BriefDescription": "L1D demand data read hits per transaction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L1_HIT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l1i_code_read_misses_per_txn", + "LegacyName": "metric_L1I code read misses (includes prefetches) per txn", + "BriefDescription": "L1I code read misses (includes prefetches) per transaction", + "Events": [ + { + "Name": "L2_RQSTS.ALL_CODE_RD", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l2_demand_data_read_hits_per_txn", + "LegacyName": "metric_L2 demand data read hits per txn", + "BriefDescription": "L2 demand data read hits per transaction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_HIT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l2_misses_per_txn", + "LegacyName": "metric_L2 misses per txn (includes code+data+rfo w/ prefetches)", + "BriefDescription": "L2 misses per transaction (includes code+data+rfo with prefetches)", + "Events": [ + { + "Name": "L2_LINES_IN.ALL", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l2_demand_data_read_misses_per_txn", + "LegacyName": "metric_L2 demand data read misses per txn", + "BriefDescription": "L2 demand data read misses per transaction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l2_demand_code_misses_per_txn", + "LegacyName": "metric_L2 demand code misses per txn", + "BriefDescription": "L2 demand code misses per transaction", + "Events": [ + { + "Name": "L2_RQSTS.CODE_RD_MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "llc_code_read_misses_per_txn", + "LegacyName": "metric_LLC code read (demand+prefetch) misses per txn", + "BriefDescription": "LLC code read (demand+prefetch) misses per transaction", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "llc_data_read_misses_per_txn", + "LegacyName": "metric_LLC data read (demand+prefetch) misses per txn", + "BriefDescription": "LLC data read (demand+prefetch) misses per transaction", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "d" + } + ], + "Formula": "(a + b + c) / d", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "package_power", + "LegacyName": "metric_package power (watts)", + "BriefDescription": "Package power consumption in watts", + "Events": [ + { + "Name": "power/energy-pkg/", + "Alias": "a" + } + ], + "Constants": [ + ], + "Formula": "a", + "ResolutionLevels": "SOCKET, SYSTEM" + }, + { + "MetricName": "dram_power", + "LegacyName": "metric_DRAM power (watts)", + "BriefDescription": "DRAM power consumption in watts", + "Events": [ + { + "Name": "power/energy-ram/", + "Alias": "a" + } + ], + "Constants": [ + ], + "Formula": "a", + "ResolutionLevels": "SOCKET, SYSTEM" + }, + { + "MetricName": "core_c6_residency", + "LegacyName": "metric_core c6 residency %", + "BriefDescription": "Core C6 state residency percentage", + "Events": [ + { + "Name": "cstate_core/c6-residency/", + "Alias": "a" + }, + { + "Name": "TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "ResolutionLevels": "CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "package_c6_residency", + "LegacyName": "metric_package c6 residency %", + "BriefDescription": "Package C6 state residency percentage", + "Events": [ + { + "Name": "cstate_pkg/c6-residency/", + "Alias": "a" + }, + { + "Name": "TSC", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "CORES_PER_SOCKET", + "Alias": "c" + } + ], + "Formula": "100 * a * c / b", + "ResolutionLevels": "SOCKET, SYSTEM" + }, + { + "MetricName": "itlb_misses_per_txn", + "LegacyName": "metric_ITLB (2nd level) misses per txn", + "BriefDescription": "ITLB (2nd level) misses per transaction", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "dtlb_load_misses_per_txn", + "LegacyName": "metric_DTLB (2nd level) load misses per txn", + "BriefDescription": "DTLB (2nd level) load misses per transaction", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "dtlb_store_misses_per_txn", + "LegacyName": "metric_DTLB (2nd level) store misses per txn", + "BriefDescription": "DTLB (2nd level) store misses per transaction", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + } + ], + "AlternateTMAMetrics": [ + { + "MetricName": "Frontend_Bound", + "LegacyName": "metric_TMA_Frontend_Bound(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CORE", + "Alias": "a" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a - b ) / c )", + "BaseFormula": "100 * ( ( [IDQ_UOPS_NOT_DELIVERED.CORE] - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS_P] ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 15", + "BaseFormula": "metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvFB;BvIO;TmaL1;PGO", + "LocateWith": " FRONTEND_RETIRED.LATENCY_GE_4" + }, + { + "MetricName": "Fetch_Latency", + "LegacyName": "metric_TMA_..Fetch_Latency(%)", + "ParentCategory": "Frontend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "a" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( 5 ) * a - b ) / ( c ) )", + "BaseFormula": "100 * ( ( ( 5 ) * [IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE] - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS_P] ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 15", + "BaseFormula": "metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Frontend;TmaL2", + "LocateWith": " FRONTEND_RETIRED.LATENCY_GE_16;FRONTEND_RETIRED.LATENCY_GE_8" + }, + { + "MetricName": "Fetch_Bandwidth", + "LegacyName": "metric_TMA_..Fetch_Bandwidth(%)", + "ParentCategory": "Frontend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CORE", + "Alias": "a" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "c" + }, + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( ( a - b ) / ( c ) ) - ( ( ( 5 ) * d - b ) / ( c ) ) ) )", + "BaseFormula": "100 * ( max( 0 , ( ( [IDQ_UOPS_NOT_DELIVERED.CORE] - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS_P] ) ) - ( ( ( 5 ) * [IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE] - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS_P] ) ) ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Fetch_Bandwidth(%)" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_..Fetch_Bandwidth(%) > 20", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchBW;Frontend;TmaL2", + "LocateWith": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1;FRONTEND_RETIRED.LATENCY_GE_1;FRONTEND_RETIRED.LATENCY_GE_2" + }, + { + "MetricName": "Bad_Speculation", + "LegacyName": "metric_TMA_Bad_Speculation(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CORE", + "Alias": "a" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "c" + }, + { + "Name": "TOPDOWN.BACKEND_BOUND_SLOTS", + "Alias": "d" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "e" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( max( 1 - ( ( ( a - b ) / ( c ) ) + ( ( d + ( 5 ) * e ) / ( c ) ) + ( f / ( c ) ) ) , 0 ) )", + "BaseFormula": "100 * ( max( 1 - ( ( ( [IDQ_UOPS_NOT_DELIVERED.CORE] - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS_P] ) ) + ( ( [TOPDOWN.BACKEND_BOUND_SLOTS] + ( 5 ) * [INT_MISC.CLEARS_COUNT] ) / ( [TOPDOWN.SLOTS_P] ) ) + ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) ) , 0 ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 15", + "BaseFormula": "metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "TmaL1", + "LocateWith": "#NA" + }, + { + "MetricName": "Branch_Mispredicts", + "LegacyName": "metric_TMA_..Branch_Mispredicts(%)", + "ParentCategory": "Bad_Speculation", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "b" + }, + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CORE", + "Alias": "c" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "d" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "e" + }, + { + "Name": "TOPDOWN.BACKEND_BOUND_SLOTS", + "Alias": "f" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "g" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( a + b ) ) * ( max( 1 - ( ( ( c - d ) / ( e ) ) + ( ( f + ( 5 ) * g ) / ( e ) ) + ( h / ( e ) ) ) , 0 ) ) )", + "BaseFormula": "100 * ( ( [BR_MISP_RETIRED.ALL_BRANCHES] / ( [BR_MISP_RETIRED.ALL_BRANCHES] + [MACHINE_CLEARS.COUNT] ) ) * ( max( 1 - ( ( ( [IDQ_UOPS_NOT_DELIVERED.CORE] - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS_P] ) ) + ( ( [TOPDOWN.BACKEND_BOUND_SLOTS] + ( 5 ) * [INT_MISC.CLEARS_COUNT] ) / ( [TOPDOWN.SLOTS_P] ) ) + ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) ) , 0 ) ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Branch_Mispredicts(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 10 & b > 15", + "BaseFormula": "metric_TMA_..Branch_Mispredicts(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "$issueBM" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2", + "LocateWith": "TOPDOWN.BR_MISPREDICT_SLOTS" + }, + { + "MetricName": "Machine_Clears", + "LegacyName": "metric_TMA_..Machine_Clears(%)", + "ParentCategory": "Bad_Speculation", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CORE", + "Alias": "a" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "c" + }, + { + "Name": "TOPDOWN.BACKEND_BOUND_SLOTS", + "Alias": "d" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "e" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "f" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "g" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( max( 1 - ( ( ( a - b ) / ( c ) ) + ( ( d + ( 5 ) * e ) / ( c ) ) + ( f / ( c ) ) ) , 0 ) ) - ( ( g / ( g + h ) ) * ( max( 1 - ( ( ( a - b ) / ( c ) ) + ( ( d + ( 5 ) * e ) / ( c ) ) + ( f / ( c ) ) ) , 0 ) ) ) ) )", + "BaseFormula": "100 * ( max( 0 , ( max( 1 - ( ( ( [IDQ_UOPS_NOT_DELIVERED.CORE] - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS_P] ) ) + ( ( [TOPDOWN.BACKEND_BOUND_SLOTS] + ( 5 ) * [INT_MISC.CLEARS_COUNT] ) / ( [TOPDOWN.SLOTS_P] ) ) + ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) ) , 0 ) ) - ( ( [BR_MISP_RETIRED.ALL_BRANCHES] / ( [BR_MISP_RETIRED.ALL_BRANCHES] + [MACHINE_CLEARS.COUNT] ) ) * ( max( 1 - ( ( ( [IDQ_UOPS_NOT_DELIVERED.CORE] - [INT_MISC.UOP_DROPPING] ) / ( [TOPDOWN.SLOTS_P] ) ) + ( ( [TOPDOWN.BACKEND_BOUND_SLOTS] + ( 5 ) * [INT_MISC.CLEARS_COUNT] ) / ( [TOPDOWN.SLOTS_P] ) ) + ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) ) , 0 ) ) ) ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Machine_Clears(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 10 & b > 15", + "BaseFormula": "metric_TMA_..Machine_Clears(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "$issueMC, $issueSyncxn" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2", + "LocateWith": "MACHINE_CLEARS.COUNT" + }, + { + "MetricName": "Backend_Bound", + "LegacyName": "metric_TMA_Backend_Bound(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN.BACKEND_BOUND_SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / b )", + "BaseFormula": " 100 * ( [TOPDOWN.BACKEND_BOUND_SLOTS] / [TOPDOWN.SLOTS_P] )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvOB;TmaL1", + "LocateWith": " TOPDOWN.BACKEND_BOUND_SLOTS" + }, + { + "MetricName": "Memory_Bound", + "LegacyName": "metric_TMA_..Memory_Bound(%)", + "ParentCategory": "Backend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Alias": "a" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "b" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "c" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "d" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "f" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "g" + }, + { + "Name": "TOPDOWN.BACKEND_BOUND_SLOTS", + "Alias": "h" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "i" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a + b ) / ( c + ( d + ( e / ( f ) ) * g ) + b ) ) * ( ( h + ( 5 ) * i ) / ( f ) ) )", + "BaseFormula": "100 * ( ( ( [CYCLE_ACTIVITY.STALLS_MEM_ANY] + [EXE_ACTIVITY.BOUND_ON_STORES] ) / ( [CYCLE_ACTIVITY.STALLS_TOTAL] + ( [EXE_ACTIVITY.1_PORTS_UTIL] + ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) * [EXE_ACTIVITY.2_PORTS_UTIL] ) + [EXE_ACTIVITY.BOUND_ON_STORES] ) ) * ( ( [TOPDOWN.BACKEND_BOUND_SLOTS] + ( 5 ) * [INT_MISC.CLEARS_COUNT] ) / ( [TOPDOWN.SLOTS_P] ) ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20", + "BaseFormula": "metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Backend;TmaL2", + "LocateWith": "#NA" + }, + { + "MetricName": "Core_Bound", + "LegacyName": "metric_TMA_..Core_Bound(%)", + "ParentCategory": "Backend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN.BACKEND_BOUND_SLOTS", + "Alias": "a" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "c" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "Alias": "d" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "e" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "f" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "g" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "h" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "i" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( ( a + ( 5 ) * b ) / ( c ) ) - ( ( ( d + e ) / ( f + ( g + ( h / ( c ) ) * i ) + e ) ) * ( ( a + ( 5 ) * b ) / ( c ) ) ) ) )", + "BaseFormula": "100 * ( max( 0 , ( ( [TOPDOWN.BACKEND_BOUND_SLOTS] + ( 5 ) * [INT_MISC.CLEARS_COUNT] ) / ( [TOPDOWN.SLOTS_P] ) ) - ( ( ( [CYCLE_ACTIVITY.STALLS_MEM_ANY] + [EXE_ACTIVITY.BOUND_ON_STORES] ) / ( [CYCLE_ACTIVITY.STALLS_TOTAL] + ( [EXE_ACTIVITY.1_PORTS_UTIL] + ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) * [EXE_ACTIVITY.2_PORTS_UTIL] ) + [EXE_ACTIVITY.BOUND_ON_STORES] ) ) * ( ( [TOPDOWN.BACKEND_BOUND_SLOTS] + ( 5 ) * [INT_MISC.CLEARS_COUNT] ) / ( [TOPDOWN.SLOTS_P] ) ) ) ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 20", + "BaseFormula": "metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Backend;TmaL2;Compute", + "LocateWith": "" + }, + { + "MetricName": "Retiring", + "LegacyName": "metric_TMA_Retiring(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / b )", + "BaseFormula": " 100 * ( [UOPS_RETIRED.SLOTS] / [TOPDOWN.SLOTS_P] )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Retiring(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 70 | b > 10", + "BaseFormula": "metric_TMA_Retiring(%) > 70 | metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvUW;TmaL1", + "LocateWith": " UOPS_RETIRED.SLOTS" + }, + { + "MetricName": "Light_Operations", + "LegacyName": "metric_TMA_..Light_Operations(%)", + "ParentCategory": "Retiring", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations , instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "c" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "d" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "e" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "f" + }, + { + "Name": "UOPS_DECODED.DEC0", + "Alias": "g" + }, + { + "Name": "UOPS_DECODED.DEC0:c1", + "Alias": "h" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "i" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b ) ) - ( ( ( a / c ) * d / ( e ) ) + ( f / ( e ) ) * ( g - h ) / i ) ) )", + "BaseFormula": "100 * ( max( 0 , ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) - ( ( ( [UOPS_RETIRED.SLOTS] / [UOPS_ISSUED.ANY] ) * [IDQ.MS_UOPS] / ( [TOPDOWN.SLOTS_P] ) ) + ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) * ( [UOPS_DECODED.DEC0] - [UOPS_DECODED.DEC0:c1] ) / [IDQ.MITE_UOPS] ) ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Retire;TmaL2", + "LocateWith": "INST_RETIRED.PREC_DIST" + }, + { + "MetricName": "Memory_Operations", + "LegacyName": "metric_TMA_....Memory_Operations(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations , uops for memory load or store accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "c" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "d" + }, + { + "Name": "UOPS_DECODED.DEC0", + "Alias": "e" + }, + { + "Name": "UOPS_DECODED.DEC0:c1", + "Alias": "f" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "g" + }, + { + "Name": "MEM_INST_RETIRED.ANY", + "Alias": "h" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "i" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b ) ) - ( ( ( a / c ) * d / ( b ) ) + ( a / ( b ) ) * ( e - f ) / g ) ) ) * h / i )", + "BaseFormula": "100 * ( ( max( 0 , ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) - ( ( ( [UOPS_RETIRED.SLOTS] / [UOPS_ISSUED.ANY] ) * [IDQ.MS_UOPS] / ( [TOPDOWN.SLOTS_P] ) ) + ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) * ( [UOPS_DECODED.DEC0] - [UOPS_DECODED.DEC0:c1] ) / [IDQ.MITE_UOPS] ) ) ) * [MEM_INST_RETIRED.ANY] / [instructions] )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Memory_Operations(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 60", + "BaseFormula": "metric_TMA_....Memory_Operations(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Branch_Instructions", + "LegacyName": "metric_TMA_....Branch_Instructions(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "c" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "d" + }, + { + "Name": "UOPS_DECODED.DEC0", + "Alias": "e" + }, + { + "Name": "UOPS_DECODED.DEC0:c1", + "Alias": "f" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "g" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b ) ) - ( ( ( a / c ) * d / ( b ) ) + ( a / ( b ) ) * ( e - e ) / g ) ) ) * h / ( ( a / ( b ) ) * ( b ) ) )", + "BaseFormula": "100 * ( ( max( 0 , ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) - ( ( ( [UOPS_RETIRED.SLOTS] / [UOPS_ISSUED.ANY] ) * [IDQ.MS_UOPS] / ( [TOPDOWN.SLOTS_P] ) ) + ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) * ( [UOPS_DECODED.DEC0] - [UOPS_DECODED.DEC0:c1] ) / [IDQ.MITE_UOPS] ) ) ) * [BR_INST_RETIRED.ALL_BRANCHES] / ( ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) * ( [TOPDOWN.SLOTS_P] ) ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Branch_Instructions(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 60", + "BaseFormula": "metric_TMA_....Branch_Instructions(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;BvBO;Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Heavy_Operations", + "LegacyName": "metric_TMA_..Heavy_Operations(%)", + "ParentCategory": "Retiring", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations , instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.([ICL+] Note this may overcount due to approximation using indirect events; [ADL+])", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "d" + }, + { + "Name": "UOPS_DECODED.DEC0", + "Alias": "e" + }, + { + "Name": "UOPS_DECODED.DEC0:c1", + "Alias": "f" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a / b ) * c / ( d ) ) + ( a / ( d ) ) * ( e - f ) / g )", + "BaseFormula": "100 * ( ( ( [UOPS_RETIRED.SLOTS] / [UOPS_ISSUED.ANY] ) * [IDQ.MS_UOPS] / ( [TOPDOWN.SLOTS_P] ) ) + ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) * ( [UOPS_DECODED.DEC0] - [UOPS_DECODED.DEC0:c1] ) / [IDQ.MITE_UOPS] )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Retire;TmaL2", + "LocateWith": " UOPS_RETIRED.HEAVY" + }, + { + "MetricName": "Few_Uops_Instructions", + "LegacyName": "metric_TMA_....Few_Uops_Instructions(%)", + "ParentCategory": "Heavy_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or more uops. This highly-correlates with the number of uops in such instructions.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "d" + }, + { + "Name": "UOPS_DECODED.DEC0", + "Alias": "e" + }, + { + "Name": "UOPS_DECODED.DEC0:c1", + "Alias": "f" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( ( a / b ) * c / ( d ) ) + ( a / ( d ) ) * ( e - f ) / g ) - ( ( a / b ) * c / ( d ) ) )", + "BaseFormula": "100 * ( ( ( ( [UOPS_RETIRED.SLOTS] / [UOPS_ISSUED.ANY] ) * [IDQ.MS_UOPS] / ( [TOPDOWN.SLOTS_P] ) ) + ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) * ( [UOPS_DECODED.DEC0] - [UOPS_DECODED.DEC0:c1] ) / [IDQ.MITE_UOPS] ) - ( ( [UOPS_RETIRED.SLOTS] / [UOPS_ISSUED.ANY] ) * [IDQ.MS_UOPS] / ( [TOPDOWN.SLOTS_P] ) ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Few_Uops_Instructions(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 5 & b > 10", + "BaseFormula": "metric_TMA_....Few_Uops_Instructions(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "$issueD0" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "Microcode_Sequencer", + "LegacyName": "metric_TMA_....Microcode_Sequencer(%)", + "ParentCategory": "Heavy_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / b ) * c / ( d ) )", + "BaseFormula": "100 * ( ( [UOPS_RETIRED.SLOTS] / [UOPS_ISSUED.ANY] ) * [IDQ.MS_UOPS] / ( [TOPDOWN.SLOTS_P] ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Microcode_Sequencer(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 5 & b > 10", + "BaseFormula": "metric_TMA_....Microcode_Sequencer(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "$issueMC, $issueMS" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq", + "LocateWith": "UOPS_RETIRED.MS" + } + ] +} diff --git a/cmd/metrics/resources/perfmon/spr/sapphirerapids_core.json b/cmd/metrics/resources/perfmon/spr/sapphirerapids_core.json new file mode 100644 index 00000000..49399319 --- /dev/null +++ b/cmd/metrics/resources/perfmon/spr/sapphirerapids_core.json @@ -0,0 +1,9986 @@ +{ + "Header": { + "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture - V1.30", + "DatePublished": "07/03/2025", + "Version": "1.30", + "Legend": "" + }, + "Events": [ + { + "EventCode": "0x00", + "UMask": "0x01", + "EventName": "INST_RETIRED.ANY", + "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event", + "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", + "Counter": "Fixed counter 0", + "PEBScounters": "32", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "32", + "Speculative": "0" + }, + { + "EventCode": "0x00", + "UMask": "0x01", + "EventName": "INST_RETIRED.PREC_DIST", + "BriefDescription": "Precise instruction retired with PEBS precise-distribution", + "PublicDescription": "A version of INST_RETIRED that allows for a precise distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR++) feature to fix bias in how retired instructions get sampled. Use on Fixed Counter 0.", + "Counter": "Fixed counter 0", + "PEBScounters": "32", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "32", + "Speculative": "0" + }, + { + "EventCode": "0x00", + "UMask": "0x02", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "BriefDescription": "Core cycles when the thread is not in halt state", + "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.", + "Counter": "Fixed counter 1", + "PEBScounters": "33", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x00", + "UMask": "0x03", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "BriefDescription": "Reference cycles when the core is not in halt state.", + "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", + "Counter": "Fixed counter 2", + "PEBScounters": "34", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x00", + "UMask": "0x04", + "EventName": "TOPDOWN.SLOTS", + "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", + "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", + "Counter": "Fixed counter 3", + "PEBScounters": "35", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x03", + "UMask": "0x04", + "EventName": "LD_BLOCKS.ADDRESS_ALIAS", + "BriefDescription": "False dependencies in MOB due to partial compare on address.", + "PublicDescription": "Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x03", + "UMask": "0x82", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", + "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x03", + "UMask": "0x88", + "EventName": "LD_BLOCKS.NO_SR", + "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x11", + "UMask": "0x02", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", + "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x11", + "UMask": "0x04", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", + "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x11", + "UMask": "0x0e", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", + "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x11", + "UMask": "0x10", + "EventName": "ITLB_MISSES.WALK_ACTIVE", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.", + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x11", + "UMask": "0x10", + "EventName": "ITLB_MISSES.WALK_PENDING", + "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.", + "PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x11", + "UMask": "0x20", + "EventName": "ITLB_MISSES.STLB_HIT", + "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.", + "PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x12", + "UMask": "0x02", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Page walks completed due to a demand data load to a 4K page.", + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x12", + "UMask": "0x04", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.", + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x12", + "UMask": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "BriefDescription": "Page walks completed due to a demand data load to a 1G page.", + "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x12", + "UMask": "0x0e", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x12", + "UMask": "0x10", + "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.", + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x12", + "UMask": "0x10", + "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", + "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.", + "PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x12", + "UMask": "0x20", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "BriefDescription": "Loads that miss the DTLB and hit the STLB.", + "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x13", + "UMask": "0x02", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Page walks completed due to a demand data store to a 4K page.", + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x13", + "UMask": "0x04", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.", + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x13", + "UMask": "0x08", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "BriefDescription": "Page walks completed due to a demand data store to a 1G page.", + "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x13", + "UMask": "0x0e", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x13", + "UMask": "0x10", + "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.", + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x13", + "UMask": "0x10", + "EventName": "DTLB_STORE_MISSES.WALK_PENDING", + "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.", + "PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x13", + "UMask": "0x20", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "BriefDescription": "Stores that miss the DTLB and hit the STLB.", + "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x01", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "BriefDescription": "Cycles where at least 1 outstanding demand data read request is pending.", + "PublicDescription": "Cycles where at least 1 outstanding demand data read request is pending.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x01", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "BriefDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.", + "PublicDescription": "For every cycle, increments by the number of outstanding demand data read requests pending. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x02", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", + "BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.", + "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x02", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.", + "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x04", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "PublicDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x08", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "BriefDescription": "This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "PublicDescription": "This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x08", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "PublicDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x08", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "PublicDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x20", + "UMask": "0x10", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", + "BriefDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.", + "PublicDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known by the requesting core to have missed the L3 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x21", + "UMask": "0x01", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "BriefDescription": "Demand Data Read requests sent to uncore", + "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x21", + "UMask": "0x02", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "BriefDescription": "Cacheable and noncacheable code read requests", + "PublicDescription": "Counts both cacheable and non-cacheable code read requests.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x21", + "UMask": "0x04", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", + "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x21", + "UMask": "0x08", + "EventName": "OFFCORE_REQUESTS.DATA_RD", + "BriefDescription": "Demand and prefetch data reads", + "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x21", + "UMask": "0x10", + "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "BriefDescription": "Counts demand data read requests that miss the L3 cache.", + "PublicDescription": "Counts demand data read requests that miss the L3 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x21", + "UMask": "0x80", + "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", + "BriefDescription": "OFFCORE_REQUESTS.ALL_REQUESTS", + "PublicDescription": "OFFCORE_REQUESTS.ALL_REQUESTS", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x23", + "UMask": "0x40", + "EventName": "L2_TRANS.L2_WB", + "BriefDescription": "L2 writebacks that access L2 cache", + "PublicDescription": "Counts L2 writebacks that access L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x21", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "BriefDescription": "Demand Data Read miss L2 cache", + "PublicDescription": "Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x22", + "EventName": "L2_RQSTS.RFO_MISS", + "BriefDescription": "RFO requests that miss L2 cache", + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "BriefDescription": "L2 cache misses when fetching instructions", + "PublicDescription": "Counts L2 cache misses when fetching instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x27", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "BriefDescription": "Demand requests that miss L2 cache", + "PublicDescription": "Counts demand requests that miss L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x28", + "EventName": "L2_RQSTS.SWPF_MISS", + "BriefDescription": "SW prefetch requests that miss L2 cache.", + "PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x30", + "EventName": "L2_RQSTS.HWPF_MISS", + "BriefDescription": "L2_RQSTS.HWPF_MISS", + "PublicDescription": "L2_RQSTS.HWPF_MISS", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x3f", + "EventName": "L2_RQSTS.MISS", + "BriefDescription": "Read requests with true-miss in L2 cache. [This event is alias to L2_REQUEST.MISS]", + "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.MISS]", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x3f", + "EventName": "L2_REQUEST.MISS", + "BriefDescription": "Read requests with true-miss in L2 cache. [This event is alias to L2_RQSTS.MISS]", + "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.MISS]", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xc1", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "BriefDescription": "Demand Data Read requests that hit L2 cache", + "PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xc2", + "EventName": "L2_RQSTS.RFO_HIT", + "BriefDescription": "RFO requests that hit L2 cache", + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xc4", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xc8", + "EventName": "L2_RQSTS.SWPF_HIT", + "BriefDescription": "SW prefetch requests that hit L2 cache.", + "PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xe1", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "BriefDescription": "Demand Data Read access L2 cache", + "PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xe2", + "EventName": "L2_RQSTS.ALL_RFO", + "BriefDescription": "RFO requests to L2 cache", + "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xe4", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "BriefDescription": "L2 code requests", + "PublicDescription": "Counts the total number of L2 code requests.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xe7", + "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", + "BriefDescription": "Demand requests to L2 cache", + "PublicDescription": "Counts demand requests to L2 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xf0", + "EventName": "L2_RQSTS.ALL_HWPF", + "BriefDescription": "L2_RQSTS.ALL_HWPF", + "PublicDescription": "L2_RQSTS.ALL_HWPF", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xff", + "EventName": "L2_RQSTS.REFERENCES", + "BriefDescription": "All accesses to L2 cache [This event is alias to L2_REQUEST.ALL]", + "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.ALL]", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0xff", + "EventName": "L2_REQUEST.ALL", + "BriefDescription": "All accesses to L2 cache [This event is alias to L2_RQSTS.REFERENCES]", + "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES]", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x25", + "UMask": "0x1f", + "EventName": "L2_LINES_IN.ALL", + "BriefDescription": "L2 cache lines filling L2", + "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x26", + "UMask": "0x01", + "EventName": "L2_LINES_OUT.SILENT", + "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache.", + "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache. These lines are typically in Shared or Exclusive state. A non-threaded event.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x26", + "UMask": "0x02", + "EventName": "L2_LINES_OUT.NON_SILENT", + "BriefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill.", + "PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x26", + "UMask": "0x04", + "EventName": "L2_LINES_OUT.USELESS_HWPF", + "BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses", + "PublicDescription": "Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x2c", + "UMask": "0x10", + "EventName": "SQ_MISC.BUS_LOCK", + "BriefDescription": "Counts bus locks, accounts for cache line split locks and UC locks.", + "PublicDescription": "Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically. Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x2d", + "UMask": "0x01", + "EventName": "XQ.FULL_CYCLES", + "BriefDescription": "Cycles the uncore cannot take further requests", + "PublicDescription": "number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x2e", + "UMask": "0x41", + "EventName": "LONGEST_LAT_CACHE.MISS", + "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)", + "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x2e", + "UMask": "0x4f", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)", + "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x3c", + "UMask": "0x00", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "BriefDescription": "Thread cycles when thread is not in halt state", + "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x3c", + "UMask": "0x01", + "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", + "BriefDescription": "Reference cycles when the core is not in halt state.", + "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x3c", + "UMask": "0x02", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.", + "PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "25003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x3c", + "UMask": "0x08", + "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.", + "PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x40", + "UMask": "0x01", + "EventName": "SW_PREFETCH_ACCESS.NTA", + "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x40", + "UMask": "0x02", + "EventName": "SW_PREFETCH_ACCESS.T0", + "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x40", + "UMask": "0x04", + "EventName": "SW_PREFETCH_ACCESS.T1_T2", + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x40", + "UMask": "0x08", + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", + "BriefDescription": "Number of PREFETCHW instructions executed.", + "PublicDescription": "Counts the number of PREFETCHW instructions executed.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x40", + "UMask": "0xF", + "EventName": "SW_PREFETCH_ACCESS.ANY", + "BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.", + "PublicDescription": "Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x43", + "UMask": "0xfd", + "EventName": "MEM_LOAD_COMPLETED.L1_MISS_ANY", + "BriefDescription": "Completed demand load uops that miss the L1 d-cache.", + "PublicDescription": "Number of completed demand load requests that missed the L1 data cache including shadow misses (FB hits, merge to an ongoing L1D miss)", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x44", + "UMask": "0x01", + "EventName": "MEM_STORE_RETIRED.L2_HIT", + "BriefDescription": "MEM_STORE_RETIRED.L2_HIT", + "PublicDescription": "MEM_STORE_RETIRED.L2_HIT", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0x47", + "UMask": "0x02", + "EventName": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "PublicDescription": "Cycles while L1 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "2", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x47", + "UMask": "0x03", + "EventName": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "PublicDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "3", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x47", + "UMask": "0x05", + "EventName": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "BriefDescription": "Execution stalls while L2 cache miss demand cacheable load request is outstanding.", + "PublicDescription": "Execution stalls while L2 cache miss demand cacheable load request is outstanding (will not count for uncacheable demand requests e.g. bus lock).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "5", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x47", + "UMask": "0x09", + "EventName": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "BriefDescription": "Execution stalls while L3 cache miss demand cacheable load request is outstanding.", + "PublicDescription": "Execution stalls while L3 cache miss demand cacheable load request is outstanding (will not count for uncacheable demand requests e.g. bus lock).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "9", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x48", + "UMask": "0x01", + "EventName": "L1D_PEND_MISS.PENDING", + "BriefDescription": "Number of L1D misses that are outstanding", + "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x48", + "UMask": "0x01", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "PublicDescription": "Counts duration of L1D miss outstanding in cycles.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x48", + "UMask": "0x02", + "EventName": "L1D_PEND_MISS.FB_FULL", + "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.", + "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x48", + "UMask": "0x02", + "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS", + "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.", + "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x48", + "UMask": "0x04", + "EventName": "L1D_PEND_MISS.L2_STALL", + "BriefDescription": "This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS", + "PublicDescription": "This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x48", + "UMask": "0x04", + "EventName": "L1D_PEND_MISS.L2_STALLS", + "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", + "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x4c", + "UMask": "0x01", + "EventName": "LOAD_HIT_PREFETCH.SWPF", + "BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.", + "PublicDescription": "Counts all software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x51", + "UMask": "0x01", + "EventName": "L1D.REPLACEMENT", + "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.", + "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x51", + "UMask": "0x20", + "EventName": "L1D.HWPF_MISS", + "BriefDescription": "L1D.HWPF_MISS", + "PublicDescription": "L1D.HWPF_MISS", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x54", + "UMask": "0x01", + "EventName": "TX_MEM.ABORT_CONFLICT", + "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", + "PublicDescription": "Counts the number of times a TSX line had a cache conflict.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x54", + "UMask": "0x02", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.", + "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x54", + "UMask": "0x80", + "EventName": "TX_MEM.ABORT_CAPACITY_READ", + "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads", + "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x60", + "UMask": "0x01", + "EventName": "BACLEARS.ANY", + "BriefDescription": "Clears due to Unknown Branches.", + "PublicDescription": "Number of times the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x61", + "UMask": "0x02", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "BriefDescription": "DSB-to-MITE switch true penalty cycles.", + "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x75", + "UMask": "0x01", + "EventName": "INST_DECODED.DECODERS", + "BriefDescription": "Instruction decoders utilized in a cycle", + "PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x76", + "UMask": "0x01", + "EventName": "UOPS_DECODED.DEC0_UOPS", + "BriefDescription": "UOPS_DECODED.DEC0_UOPS", + "PublicDescription": "UOPS_DECODED.DEC0_UOPS", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x04", + "EventName": "IDQ.MITE_CYCLES_ANY", + "BriefDescription": "Cycles MITE is delivering any Uop", + "PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x04", + "EventName": "IDQ.MITE_CYCLES_OK", + "BriefDescription": "Cycles MITE is delivering optimal number of Uops", + "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "6", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x04", + "EventName": "IDQ.MITE_UOPS", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x08", + "EventName": "IDQ.DSB_CYCLES_ANY", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", + "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x08", + "EventName": "IDQ.DSB_CYCLES_OK", + "BriefDescription": "Cycles DSB is delivering optimal number of Uops", + "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode Stream Buffer) path. Count includes uops that may 'bypass' the IDQ.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "6", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x08", + "EventName": "IDQ.DSB_UOPS", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", + "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x20", + "EventName": "IDQ.MS_CYCLES_ANY", + "BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy", + "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x20", + "EventName": "IDQ.MS_SWITCHES", + "BriefDescription": "Number of switches from DSB or MITE to the MS", + "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x79", + "UMask": "0x20", + "EventName": "IDQ.MS_UOPS", + "BriefDescription": "Uops delivered to IDQ while MS is busy", + "PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x80", + "UMask": "0x04", + "EventName": "ICACHE_DATA.STALLS", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.", + "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The decode pipeline works at a 32 Byte granularity.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x80", + "UMask": "0x04", + "EventName": "ICACHE_DATA.STALL_PERIODS", + "BriefDescription": "ICACHE_DATA.STALL_PERIODS", + "PublicDescription": "ICACHE_DATA.STALL_PERIODS", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x83", + "UMask": "0x04", + "EventName": "ICACHE_TAG.STALLS", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.", + "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x87", + "UMask": "0x01", + "EventName": "DECODE.LCP", + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x87", + "UMask": "0x02", + "EventName": "DECODE.MS_BUSY", + "BriefDescription": "Cycles the Microcode Sequencer is busy.", + "PublicDescription": "Cycles the Microcode Sequencer is busy.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x9c", + "UMask": "0x01", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CORE]", + "PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CORE]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x9c", + "UMask": "0x01", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE]", + "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "6", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x9c", + "UMask": "0x01", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_FE_WAS_OK]", + "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CYCLES_FE_WAS_OK]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x9c", + "UMask": "0x01", + "EventName": "IDQ_BUBBLES.CORE", + "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CORE]", + "PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CORE]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x9c", + "UMask": "0x01", + "EventName": "IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE", + "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE]", + "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "6", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x9c", + "UMask": "0x01", + "EventName": "IDQ_BUBBLES.CYCLES_FE_WAS_OK", + "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK]", + "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa2", + "UMask": "0x02", + "EventName": "RESOURCE_STALLS.SCOREBOARD", + "BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.", + "PublicDescription": "Counts cycles where the pipeline is stalled due to serializing operations.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa2", + "UMask": "0x08", + "EventName": "RESOURCE_STALLS.SB", + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x01", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", + "PublicDescription": "Cycles while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x04", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", + "BriefDescription": "Total execution stalls.", + "PublicDescription": "Total execution stalls.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "4", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x05", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "PublicDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "5", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x06", + "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", + "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", + "PublicDescription": "Execution stalls while L3 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "6", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x08", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "PublicDescription": "Cycles while L1 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "8", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x0c", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "PublicDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "12", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa3", + "UMask": "0x10", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "PublicDescription": "Cycles while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "16", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa4", + "UMask": "0x01", + "EventName": "TOPDOWN.SLOTS_P", + "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", + "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa4", + "UMask": "0x02", + "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", + "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", + "PublicDescription": "Number of slots in TMA method where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa4", + "UMask": "0x04", + "EventName": "TOPDOWN.BAD_SPEC_SLOTS", + "BriefDescription": "TMA slots wasted due to incorrect speculations.", + "PublicDescription": "Number of slots of TMA method that were wasted due to incorrect speculation. It covers all types of control-flow or data-related mis-speculations.", + "Counter": "0", + "PEBScounters": "0", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa4", + "UMask": "0x08", + "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", + "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", + "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by (any type of) branch mispredictions. This event estimates number of speculative operations that were issued but not retired as well as the out-of-order engine recovery past a branch misprediction.", + "Counter": "0", + "PEBScounters": "0", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa4", + "UMask": "0x10", + "EventName": "TOPDOWN.MEMORY_BOUND_SLOTS", + "BriefDescription": "TOPDOWN.MEMORY_BOUND_SLOTS", + "PublicDescription": "TOPDOWN.MEMORY_BOUND_SLOTS", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "10000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa5", + "UMask": "0x01", + "EventName": "RS.EMPTY_RESOURCE", + "BriefDescription": "Cycles when Reservation Station (RS) is empty due to a resource in the back-end", + "PublicDescription": "Cycles when Reservation Station (RS) is empty due to a resource in the back-end", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa5", + "UMask": "0x07", + "EventName": "RS_EMPTY.COUNT", + "BriefDescription": "This event is deprecated. Refer to new event RS.EMPTY_COUNT", + "PublicDescription": "This event is deprecated. Refer to new event RS.EMPTY_COUNT", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa5", + "UMask": "0x07", + "EventName": "RS_EMPTY.CYCLES", + "BriefDescription": "This event is deprecated. Refer to new event RS.EMPTY", + "PublicDescription": "This event is deprecated. Refer to new event RS.EMPTY", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa5", + "UMask": "0x07", + "EventName": "RS.EMPTY", + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.", + "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses)", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa5", + "UMask": "0x07", + "EventName": "RS.EMPTY_COUNT", + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.", + "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x02", + "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", + "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.", + "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x04", + "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", + "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.", + "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x08", + "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", + "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.", + "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x10", + "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", + "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.", + "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x21", + "EventName": "EXE_ACTIVITY.BOUND_ON_LOADS", + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "PublicDescription": "Execution stalls while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "5", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x40", + "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", + "BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.", + "PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "2", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0x80", + "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "BriefDescription": "Cycles no uop executed while RS was not empty, the SB was not full and there was no outstanding load.", + "PublicDescription": "Number of cycles total of 0 uops executed on all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) was not full and there was no outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa6", + "UMask": "0xC", + "EventName": "EXE_ACTIVITY.2_3_PORTS_UTIL", + "BriefDescription": "Cycles total of 2 or 3 uops are executed on all ports and Reservation Station (RS) was not empty.", + "PublicDescription": "Cycles total of 2 or 3 uops are executed on all ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa8", + "UMask": "0x01", + "EventName": "LSD.CYCLES_ACTIVE", + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa8", + "UMask": "0x01", + "EventName": "LSD.CYCLES_OK", + "BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.", + "PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "6", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xa8", + "UMask": "0x01", + "EventName": "LSD.UOPS", + "BriefDescription": "Number of Uops delivered by the LSD.", + "PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xad", + "UMask": "0x01", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread", + "PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xad", + "UMask": "0x01", + "EventName": "INT_MISC.CLEARS_COUNT", + "BriefDescription": "Clears speculative count", + "PublicDescription": "Counts the number of speculative clears due to any type of branch misprediction or machine clears", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xad", + "UMask": "0x10", + "EventName": "INT_MISC.UOP_DROPPING", + "BriefDescription": "TMA slots where uops got dropped", + "PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xad", + "UMask": "0x20", + "EventName": "INT_MISC.MBA_STALLS", + "BriefDescription": "INT_MISC.MBA_STALLS", + "PublicDescription": "INT_MISC.MBA_STALLS", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xad", + "UMask": "0x40", + "EventName": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "BriefDescription": "Bubble cycles of BAClear (Unknown Branch).", + "PublicDescription": "Bubble cycles of BAClear (Unknown Branch).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x3F7", + "MSRValue": "0x7", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xad", + "UMask": "0x80", + "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", + "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", + "PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "500009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xae", + "UMask": "0x01", + "EventName": "UOPS_ISSUED.ANY", + "BriefDescription": "Uops that RAT issues to RS", + "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xae", + "UMask": "0x01", + "EventName": "UOPS_ISSUED.CYCLES", + "BriefDescription": "UOPS_ISSUED.CYCLES", + "PublicDescription": "UOPS_ISSUED.CYCLES", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb0", + "UMask": "0x01", + "EventName": "ARITH.FP_DIVIDER_ACTIVE", + "BriefDescription": "This event is deprecated. Refer to new event ARITH.FPDIV_ACTIVE", + "PublicDescription": "This event is deprecated. Refer to new event ARITH.FPDIV_ACTIVE", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb0", + "UMask": "0x01", + "EventName": "ARITH.FPDIV_ACTIVE", + "BriefDescription": "ARITH.FPDIV_ACTIVE", + "PublicDescription": "ARITH.FPDIV_ACTIVE", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb0", + "UMask": "0x08", + "EventName": "ARITH.IDIV_ACTIVE", + "BriefDescription": "This event counts the cycles the integer divider is busy.", + "PublicDescription": "This event counts the cycles the integer divider is busy.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb0", + "UMask": "0x08", + "EventName": "ARITH.INT_DIVIDER_ACTIVE", + "BriefDescription": "This event is deprecated. Refer to new event ARITH.IDIV_ACTIVE", + "PublicDescription": "This event is deprecated. Refer to new event ARITH.IDIV_ACTIVE", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb0", + "UMask": "0x09", + "EventName": "ARITH.DIVIDER_ACTIVE", + "BriefDescription": "This event is deprecated. Refer to new event ARITH.DIV_ACTIVE", + "PublicDescription": "This event is deprecated. Refer to new event ARITH.DIV_ACTIVE", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb0", + "UMask": "0x09", + "EventName": "ARITH.DIV_ACTIVE", + "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.", + "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1", + "BriefDescription": "Cycles where at least 1 uop was executed per-thread", + "PublicDescription": "Cycles where at least 1 uop was executed per-thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2", + "BriefDescription": "Cycles where at least 2 uops were executed per-thread", + "PublicDescription": "Cycles where at least 2 uops were executed per-thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "2", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3", + "BriefDescription": "Cycles where at least 3 uops were executed per-thread", + "PublicDescription": "Cycles where at least 3 uops were executed per-thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "3", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4", + "BriefDescription": "Cycles where at least 4 uops were executed per-thread", + "PublicDescription": "Cycles where at least 4 uops were executed per-thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "4", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "BriefDescription": "This event is deprecated. Refer to new event UOPS_EXECUTED.STALLS", + "PublicDescription": "This event is deprecated. Refer to new event UOPS_EXECUTED.STALLS", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.THREAD", + "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", + "PublicDescription": "Counts the number of uops to be executed per-thread each cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x01", + "EventName": "UOPS_EXECUTED.STALLS", + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE", + "BriefDescription": "Number of uops executed on the core.", + "PublicDescription": "Counts the number of uops executed from any thread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "2", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "3", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x02", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "4", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb1", + "UMask": "0x10", + "EventName": "UOPS_EXECUTED.X87", + "BriefDescription": "Counts the number of x87 uops dispatched.", + "PublicDescription": "Counts the number of x87 uops executed.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb2", + "UMask": "0x01", + "EventName": "UOPS_DISPATCHED.PORT_0", + "BriefDescription": "Uops executed on port 0", + "PublicDescription": "Number of uops dispatch to execution port 0.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb2", + "UMask": "0x02", + "EventName": "UOPS_DISPATCHED.PORT_1", + "BriefDescription": "Uops executed on port 1", + "PublicDescription": "Number of uops dispatch to execution port 1.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb2", + "UMask": "0x04", + "EventName": "UOPS_DISPATCHED.PORT_2_3_10", + "BriefDescription": "Uops executed on ports 2, 3 and 10", + "PublicDescription": "Number of uops dispatch to execution ports 2, 3 and 10", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb2", + "UMask": "0x10", + "EventName": "UOPS_DISPATCHED.PORT_4_9", + "BriefDescription": "Uops executed on ports 4 and 9", + "PublicDescription": "Number of uops dispatch to execution ports 4 and 9", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb2", + "UMask": "0x20", + "EventName": "UOPS_DISPATCHED.PORT_5_11", + "BriefDescription": "Uops executed on ports 5 and 11", + "PublicDescription": "Number of uops dispatch to execution ports 5 and 11", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb2", + "UMask": "0x40", + "EventName": "UOPS_DISPATCHED.PORT_6", + "BriefDescription": "Uops executed on port 6", + "PublicDescription": "Number of uops dispatch to execution port 6.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb2", + "UMask": "0x80", + "EventName": "UOPS_DISPATCHED.PORT_7_8", + "BriefDescription": "Uops executed on ports 7 and 8", + "PublicDescription": "Number of uops dispatch to execution ports 7 and 8.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb3", + "UMask": "0x01", + "EventName": "FP_ARITH_DISPATCHED.PORT_0", + "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0]", + "PublicDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb3", + "UMask": "0x01", + "EventName": "FP_ARITH_DISPATCHED.V0", + "BriefDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0]", + "PublicDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb3", + "UMask": "0x02", + "EventName": "FP_ARITH_DISPATCHED.PORT_1", + "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1]", + "PublicDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb3", + "UMask": "0x02", + "EventName": "FP_ARITH_DISPATCHED.V1", + "BriefDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1]", + "PublicDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb3", + "UMask": "0x04", + "EventName": "FP_ARITH_DISPATCHED.PORT_5", + "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2]", + "PublicDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb3", + "UMask": "0x04", + "EventName": "FP_ARITH_DISPATCHED.V2", + "BriefDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5]", + "PublicDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xb7", + "UMask": "0x02", + "EventName": "EXE.AMX_BUSY", + "BriefDescription": "Counts the cycles where the AMX (Advance Matrix Extension) unit is busy performing an operation.", + "PublicDescription": "Counts the cycles where the AMX (Advance Matrix Extension) unit is busy performing an operation.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc0", + "UMask": "0x00", + "EventName": "INST_RETIRED.ANY_P", + "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc0", + "UMask": "0x02", + "EventName": "INST_RETIRED.NOP", + "BriefDescription": "Retired NOP instructions.", + "PublicDescription": "Counts all retired NOP or ENDBR32/64 instructions", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc0", + "UMask": "0x08", + "EventName": "INST_RETIRED.REP_ITERATION", + "BriefDescription": "Iterations of Repeat string retired instructions.", + "PublicDescription": "Number of iterations of Repeat (REP) string retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, and doubleword version and string instructions can be repeated using a repetition prefix, REP, that allows their architectural execution to be repeated a number of times as specified by the RCX register. Note the number of iterations is implementation-dependent.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc0", + "UMask": "0x10", + "EventName": "INST_RETIRED.MACRO_FUSED", + "BriefDescription": "INST_RETIRED.MACRO_FUSED", + "PublicDescription": "INST_RETIRED.MACRO_FUSED", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc1", + "UMask": "0x02", + "EventName": "ASSISTS.FP", + "BriefDescription": "Counts all microcode FP assists.", + "PublicDescription": "Counts all microcode Floating Point assists.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc1", + "UMask": "0x08", + "EventName": "ASSISTS.PAGE_FAULT", + "BriefDescription": "ASSISTS.PAGE_FAULT", + "PublicDescription": "ASSISTS.PAGE_FAULT", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc1", + "UMask": "0x10", + "EventName": "ASSISTS.SSE_AVX_MIX", + "BriefDescription": "ASSISTS.SSE_AVX_MIX", + "PublicDescription": "ASSISTS.SSE_AVX_MIX", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc1", + "UMask": "0x1b", + "EventName": "ASSISTS.ANY", + "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.", + "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware. Examples include AD (page Access Dirty), FP and AVX related assists.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc2", + "UMask": "0x01", + "EventName": "UOPS_RETIRED.HEAVY", + "BriefDescription": "Retired uops except the last uop of each instruction.", + "PublicDescription": "Counts the number of retired micro-operations (uops) except the last uop of each instruction. An instruction that is decoded into less than two uops does not contribute to the count.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x02", + "EventName": "UOPS_RETIRED.SLOTS", + "BriefDescription": "Retirement slots used.", + "PublicDescription": "Counts the retirement slots used each cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x02", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "BriefDescription": "This event is deprecated. Refer to new event UOPS_RETIRED.STALLS", + "PublicDescription": "This event is deprecated. Refer to new event UOPS_RETIRED.STALLS", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x02", + "EventName": "UOPS_RETIRED.STALLS", + "BriefDescription": "Cycles without actually retired uops.", + "PublicDescription": "This event counts cycles without actually retired uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "1", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x02", + "EventName": "UOPS_RETIRED.CYCLES", + "BriefDescription": "Cycles with retired uop(s).", + "PublicDescription": "Counts cycles where at least one uop has retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x04", + "EventName": "UOPS_RETIRED.MS", + "BriefDescription": "UOPS_RETIRED.MS", + "PublicDescription": "UOPS_RETIRED.MS", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x3F7", + "MSRValue": "0x8", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc3", + "UMask": "0x01", + "EventName": "MACHINE_CLEARS.COUNT", + "BriefDescription": "Number of machine clears (nukes) of any type.", + "PublicDescription": "Counts the number of machine clears (nukes) of any type.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc3", + "UMask": "0x02", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "BriefDescription": "Number of machine clears due to memory ordering conflicts.", + "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc3", + "UMask": "0x04", + "EventName": "MACHINE_CLEARS.SMC", + "BriefDescription": "Self-modifying code (SMC) detected.", + "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc4", + "UMask": "0x00", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "BriefDescription": "All branch instructions retired.", + "PublicDescription": "Counts all branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x01", + "EventName": "BR_INST_RETIRED.COND_TAKEN", + "BriefDescription": "Taken conditional branch instructions retired.", + "PublicDescription": "Counts taken conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x02", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "BriefDescription": "Direct and indirect near call instructions retired.", + "PublicDescription": "Counts both direct and indirect near call instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x08", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "BriefDescription": "Return instructions retired.", + "PublicDescription": "Counts return instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x10", + "EventName": "BR_INST_RETIRED.COND_NTAKEN", + "BriefDescription": "Not taken branch instructions retired.", + "PublicDescription": "Counts not taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x11", + "EventName": "BR_INST_RETIRED.COND", + "BriefDescription": "Conditional branch instructions retired.", + "PublicDescription": "Counts conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x20", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "BriefDescription": "Taken branch instructions retired.", + "PublicDescription": "Counts taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x40", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "BriefDescription": "Far branch instructions retired.", + "PublicDescription": "Counts far branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x80", + "EventName": "BR_INST_RETIRED.INDIRECT", + "BriefDescription": "Indirect near branch instructions retired (excluding returns)", + "PublicDescription": "Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x00", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "BriefDescription": "All mispredicted branch instructions retired.", + "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x01", + "EventName": "BR_MISP_RETIRED.COND_TAKEN", + "BriefDescription": "number of branch instructions retired that were mispredicted and taken.", + "PublicDescription": "Counts taken conditional mispredicted branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x02", + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", + "BriefDescription": "Mispredicted indirect CALL retired.", + "PublicDescription": "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x08", + "EventName": "BR_MISP_RETIRED.RET", + "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x10", + "EventName": "BR_MISP_RETIRED.COND_NTAKEN", + "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", + "PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x11", + "EventName": "BR_MISP_RETIRED.COND", + "BriefDescription": "Mispredicted conditional branch instructions retired.", + "PublicDescription": "Counts mispredicted conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x20", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", + "PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x80", + "EventName": "BR_MISP_RETIRED.INDIRECT", + "BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)", + "PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.DSB_MISS", + "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", + "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x11", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.ITLB_MISS", + "BriefDescription": "Retired Instructions who experienced iTLB true miss.", + "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x14", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.L1I_MISS", + "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", + "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x12", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.L2_MISS", + "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", + "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x13", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", + "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x600106", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x608006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x601006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", + "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x600206", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x100206", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x610006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x602006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x600406", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x620006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x604006", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x600806", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.STLB_MISS", + "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.", + "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x15", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.UNKNOWN_BRANCH", + "BriefDescription": "FRONTEND_RETIRED.UNKNOWN_BRANCH", + "PublicDescription": "FRONTEND_RETIRED.UNKNOWN_BRANCH", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x17", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.MS_FLOWS", + "BriefDescription": "FRONTEND_RETIRED.MS_FLOWS", + "PublicDescription": "FRONTEND_RETIRED.MS_FLOWS", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x8", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", + "BriefDescription": "Retired Instructions who experienced DSB miss.", + "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F7", + "MSRValue": "0x1", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x01", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x02", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x03", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR", + "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x04", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x08", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x10", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x18", + "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x20", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x40", + "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x60", + "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x80", + "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0xfc", + "EventName": "FP_ARITH_INST_RETIRED.VECTOR", + "BriefDescription": "Number of any Vector retired FP arithmetic instructions", + "PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x01", + "EventName": "RTM_RETIRED.START", + "BriefDescription": "Number of times an RTM execution started.", + "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x02", + "EventName": "RTM_RETIRED.COMMIT", + "BriefDescription": "Number of times an RTM execution successfully committed", + "PublicDescription": "Counts the number of times RTM commit succeeded.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x04", + "EventName": "RTM_RETIRED.ABORTED", + "BriefDescription": "Number of times an RTM execution aborted.", + "PublicDescription": "Counts the number of times RTM abort was triggered.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x08", + "EventName": "RTM_RETIRED.ABORTED_MEM", + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", + "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x20", + "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", + "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", + "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x40", + "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", + "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", + "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc9", + "UMask": "0x80", + "EventName": "RTM_RETIRED.ABORTED_EVENTS", + "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 3 categories (e.g. interrupt)", + "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 3 categories (e.g. interrupt).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcb", + "UMask": "0x01", + "EventName": "HW_INTERRUPTS.RECEIVED", + "BriefDescription": "Number of hardware interrupts received by the processor.", + "PublicDescription": "Counts the number of hardware interruptions received by the processor.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "203", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xcb", + "UMask": "0x02", + "EventName": "HW_INTERRUPTS.MASKED", + "BriefDescription": "HW_INTERRUPTS.MASKED", + "PublicDescription": "HW_INTERRUPTS.MASKED", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xcb", + "UMask": "0x04", + "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED", + "BriefDescription": "HW_INTERRUPTS.PENDING_AND_MASKED", + "PublicDescription": "HW_INTERRUPTS.PENDING_AND_MASKED", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xcc", + "UMask": "0x20", + "EventName": "MISC_RETIRED.LBR_INSERTS", + "BriefDescription": "Increments whenever there is an update to the LBR array.", + "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "1009", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "20011", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "503", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "101", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "2003", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x01", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "1,2,3,4,5,6,7", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "53", + "MSRIndex": "0x3F6", + "MSRValue": "0x400", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x02", + "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE", + "BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.", + "PublicDescription": "Counts Retired memory accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) trigger covering all stores uops for sampling by the PEBS Store Latency Facility. The facility is described in Intel SDM Volume 3 section 19.9.8", + "Counter": "0", + "PEBScounters": "0", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xcf", + "UMask": "0x01", + "EventName": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", + "BriefDescription": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", + "PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcf", + "UMask": "0x02", + "EventName": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", + "BriefDescription": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", + "PublicDescription": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcf", + "UMask": "0x03", + "EventName": "FP_ARITH_INST_RETIRED2.SCALAR", + "BriefDescription": "Number of all Scalar Half-Precision FP arithmetic instructions(1) retired - regular and complex.", + "PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcf", + "UMask": "0x04", + "EventName": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", + "BriefDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", + "PublicDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcf", + "UMask": "0x08", + "EventName": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", + "BriefDescription": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", + "PublicDescription": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcf", + "UMask": "0x10", + "EventName": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", + "BriefDescription": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", + "PublicDescription": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcf", + "UMask": "0x1c", + "EventName": "FP_ARITH_INST_RETIRED2.VECTOR", + "BriefDescription": "Number of all Vector (also called packed) Half-Precision FP arithmetic instructions(1) retired.", + "PublicDescription": "FP_ARITH_INST_RETIRED2.VECTOR", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x11", + "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", + "BriefDescription": "Retired load instructions that miss the STLB.", + "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x12", + "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", + "BriefDescription": "Retired store instructions that miss the STLB.", + "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x21", + "EventName": "MEM_INST_RETIRED.LOCK_LOADS", + "BriefDescription": "Retired load instructions with locked access.", + "PublicDescription": "Counts retired load instructions with locked access.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x41", + "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", + "BriefDescription": "Retired load instructions that split across a cacheline boundary.", + "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x42", + "EventName": "MEM_INST_RETIRED.SPLIT_STORES", + "BriefDescription": "Retired store instructions that split across a cacheline boundary.", + "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x81", + "EventName": "MEM_INST_RETIRED.ALL_LOADS", + "BriefDescription": "Retired load instructions.", + "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x82", + "EventName": "MEM_INST_RETIRED.ALL_STORES", + "BriefDescription": "Retired store instructions.", + "PublicDescription": "Counts all retired store instructions.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x83", + "EventName": "MEM_INST_RETIRED.ANY", + "BriefDescription": "All retired memory instructions.", + "PublicDescription": "Counts all retired memory instructions - loads and stores.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x01", + "EventName": "MEM_LOAD_RETIRED.L1_HIT", + "BriefDescription": "Retired load instructions with L1 cache hits as data sources", + "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x02", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "BriefDescription": "Retired load instructions with L2 cache hits as data sources", + "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x04", + "EventName": "MEM_LOAD_RETIRED.L3_HIT", + "BriefDescription": "Retired load instructions with L3 cache hits as data sources", + "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x08", + "EventName": "MEM_LOAD_RETIRED.L1_MISS", + "BriefDescription": "Retired load instructions missed L1 cache as data sources", + "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x10", + "EventName": "MEM_LOAD_RETIRED.L2_MISS", + "BriefDescription": "Retired load instructions missed L2 cache as data sources", + "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x20", + "EventName": "MEM_LOAD_RETIRED.L3_MISS", + "BriefDescription": "Retired load instructions missed L3 cache as data sources", + "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "50021", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x40", + "EventName": "MEM_LOAD_RETIRED.FB_HIT", + "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.", + "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x80", + "EventName": "MEM_LOAD_RETIRED.LOCAL_PMM", + "BriefDescription": "Retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.", + "PublicDescription": "Counts retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd2", + "UMask": "0x01", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd2", + "UMask": "0x02", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache", + "PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd2", + "UMask": "0x04", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", + "PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd2", + "UMask": "0x08", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", + "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required", + "PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd3", + "UMask": "0x01", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", + "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram", + "PublicDescription": "Retired load instructions which data sources missed L3 but serviced from local DRAM.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd3", + "UMask": "0x02", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "BriefDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "PublicDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd3", + "UMask": "0x04", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "BriefDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "PublicDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd3", + "UMask": "0x08", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "BriefDescription": "Retired load instructions whose data sources was forwarded from a remote cache", + "PublicDescription": "Retired load instructions whose data sources was forwarded from a remote cache.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd3", + "UMask": "0x10", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM", + "BriefDescription": "Retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.", + "PublicDescription": "Counts retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3.", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xd4", + "UMask": "0x04", + "EventName": "MEM_LOAD_MISC_RETIRED.UC", + "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.", + "PublicDescription": "Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock).", + "Counter": "0,1,2,3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xe0", + "UMask": "0x20", + "EventName": "MISC2_RETIRED.LFENCE", + "BriefDescription": "LFENCE instructions retired", + "PublicDescription": "number of LFENCE retired instructions", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xe5", + "UMask": "0x03", + "EventName": "MEM_UOP_RETIRED.ANY", + "BriefDescription": "Retired memory uops for any access", + "PublicDescription": "Number of retired micro-operations (uops) for load or store memory accesses", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe7", + "UMask": "0x03", + "EventName": "INT_VEC_RETIRED.ADD_128", + "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.", + "PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vector instructions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe7", + "UMask": "0x0c", + "EventName": "INT_VEC_RETIRED.ADD_256", + "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.", + "PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vector instructions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe7", + "UMask": "0x10", + "EventName": "INT_VEC_RETIRED.VNNI_128", + "BriefDescription": "INT_VEC_RETIRED.VNNI_128", + "PublicDescription": "INT_VEC_RETIRED.VNNI_128", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe7", + "UMask": "0x13", + "EventName": "INT_VEC_RETIRED.128BIT", + "BriefDescription": "INT_VEC_RETIRED.128BIT", + "PublicDescription": "INT_VEC_RETIRED.128BIT", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe7", + "UMask": "0x20", + "EventName": "INT_VEC_RETIRED.VNNI_256", + "BriefDescription": "INT_VEC_RETIRED.VNNI_256", + "PublicDescription": "INT_VEC_RETIRED.VNNI_256", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe7", + "UMask": "0x40", + "EventName": "INT_VEC_RETIRED.SHUFFLES", + "BriefDescription": "INT_VEC_RETIRED.SHUFFLES", + "PublicDescription": "INT_VEC_RETIRED.SHUFFLES", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe7", + "UMask": "0x80", + "EventName": "INT_VEC_RETIRED.MUL_256", + "BriefDescription": "INT_VEC_RETIRED.MUL_256", + "PublicDescription": "INT_VEC_RETIRED.MUL_256", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe7", + "UMask": "0xac", + "EventName": "INT_VEC_RETIRED.256BIT", + "BriefDescription": "INT_VEC_RETIRED.256BIT", + "PublicDescription": "INT_VEC_RETIRED.256BIT", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xec", + "UMask": "0x02", + "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", + "BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.", + "PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xec", + "UMask": "0x10", + "EventName": "CPU_CLK_UNHALTED.C01", + "BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state.", + "PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xec", + "UMask": "0x20", + "EventName": "CPU_CLK_UNHALTED.C02", + "BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state.", + "PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xec", + "UMask": "0x40", + "EventName": "CPU_CLK_UNHALTED.PAUSE", + "BriefDescription": "CPU_CLK_UNHALTED.PAUSE", + "PublicDescription": "CPU_CLK_UNHALTED.PAUSE", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xec", + "UMask": "0x40", + "EventName": "CPU_CLK_UNHALTED.PAUSE_INST", + "BriefDescription": "CPU_CLK_UNHALTED.PAUSE_INST", + "PublicDescription": "CPU_CLK_UNHALTED.PAUSE_INST", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "1", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xec", + "UMask": "0x70", + "EventName": "CPU_CLK_UNHALTED.C0_WAIT", + "BriefDescription": "Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 ACPI state.", + "PublicDescription": "Counts core clocks when the thread is in the C0.1 or C0.2 power saving optimized states (TPAUSE or UMWAIT instructions) or running the PAUSE instruction.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "BriefDescription": "Counts demand data reads that have any type of response.", + "PublicDescription": "Counts demand data reads that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F3FFC0002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.HWPF_L1D.ANY_RESPONSE", + "BriefDescription": "Counts data load hardware prefetch requests to the L1 data cache that have any type of response.", + "PublicDescription": "Counts data load hardware prefetch requests to the L1 data cache that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10400", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", + "BriefDescription": "Counts streaming stores that have any type of response.", + "PublicDescription": "Counts streaming stores that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10800", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F3FFC4477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.HWPF_L3.ANY_RESPONSE", + "BriefDescription": "Counts hardware prefetches to the L3 only that have any type of response.", + "PublicDescription": "Counts hardware prefetches to the L3 only that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x12380", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", + "BriefDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.", + "PublicDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.L3_HIT", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.L3_HIT", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F003C4477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.STREAMING_WR.L3_HIT", + "BriefDescription": "Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket.", + "PublicDescription": "Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80080800", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.HWPF_L3.L3_HIT", + "BriefDescription": "Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket.", + "PublicDescription": "Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80082380", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL", + "BriefDescription": "Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "PublicDescription": "Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x84000800", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.HWPF_L3.L3_MISS_LOCAL", + "BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "PublicDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x84002380", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F04C04477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.REMOTE", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F33004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.HWPF_L3.REMOTE", + "BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.", + "PublicDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x90002380", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", + "BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", + "PublicDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.L3_MISS", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F3FC00002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.L3_MISS", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F3FC04477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.STREAMING_WR.L3_MISS", + "BriefDescription": "Counts streaming stores that missed the local socket's L1, L2, and L3 caches.", + "PublicDescription": "Counts streaming stores that missed the local socket's L1, L2, and L3 caches.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x94000800", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.HWPF_L3.L3_MISS", + "BriefDescription": "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.", + "PublicDescription": "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x94002380", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", + "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "PublicDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104000002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104000004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.REMOTE_DRAM", + "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to another socket.", + "PublicDescription": "Counts demand data reads that were supplied by DRAM attached to another socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x730000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.REMOTE_DRAM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x730004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.DRAM", + "BriefDescription": "Counts demand data reads that were supplied by DRAM.", + "PublicDescription": "Counts demand data reads that were supplied by DRAM.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.DRAM", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C000002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.DRAM", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C000004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.DRAM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.REMOTE_PMM", + "BriefDescription": "Counts demand data reads that were supplied by PMM attached to another socket.", + "PublicDescription": "Counts demand data reads that were supplied by PMM attached to another socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x703000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.REMOTE_PMM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to another socket.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to another socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x703004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.PMM", + "BriefDescription": "Counts demand data reads that were supplied by PMM.", + "PublicDescription": "Counts demand data reads that were supplied by PMM.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x703C00001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data.", + "PublicDescription": "Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C4477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "PublicDescription": "Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HIT_WITH_FWD", + "BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "PublicDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x830000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C4477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x830004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "BriefDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "PublicDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HITM", + "BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.", + "PublicDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1030000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C4477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1030004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.SNC_DRAM", + "BriefDescription": "Counts demand data reads that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand data reads that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x708000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.SNC_DRAM", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x708000002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.SNC_DRAM", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x708000004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.SNC_DRAM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x708004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HITM", + "BriefDescription": "Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HIT_WITH_FWD", + "BriefDescription": "Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x808000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.SNC_CACHE.HITM", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008000002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_RFO.SNC_CACHE.HIT_WITH_FWD", + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x808000002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HITM", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008000004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HIT_WITH_FWD", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x808000004", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HITM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HIT_WITH_FWD", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x808004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_DRAM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x70C004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.DEMAND_DATA_RD.LOCAL_SOCKET_PMM", + "BriefDescription": "Counts demand data reads that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster.", + "PublicDescription": "Counts demand data reads that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x700C00001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_PMM", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x700C04477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.HWPF_L2.ANY_RESPONSE", + "BriefDescription": "Counts hardware prefetches (which bring data to L2) that have any type of response.", + "PublicDescription": "Counts hardware prefetches (which bring data to L2) that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10070", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster. It does not count misses to the L3 which go to Local CXL Type 2 Memory or Local Non DRAM.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster. It does not count misses to the L3 which go to Local CXL Type 2 Memory or Local Non DRAM.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x70CC04477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified).", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified).", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1830004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.READS_TO_CORE.REMOTE_MEMORY", + "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket.", + "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x733004477", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.RFO_TO_CORE.L3_HIT_M", + "BriefDescription": "Counts demand reads for ownership (RFO), hardware prefetch RFOs (which bring data to L2), and software prefetches for exclusive ownership (PREFETCHW) that hit to a (M)odified cacheline in the L3 or snoop filter.", + "PublicDescription": "Counts demand reads for ownership (RFO), hardware prefetch RFOs (which bring data to L2), and software prefetches for exclusive ownership (PREFETCHW) that hit to a (M)odified cacheline in the L3 or snoop filter.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F80040022", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.MODIFIED_WRITE.ANY_RESPONSE", + "BriefDescription": "Counts writebacks of modified cachelines and streaming stores that have any type of response.", + "PublicDescription": "Counts writebacks of modified cachelines and streaming stores that have any type of response.", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10808", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0x2A,0x2B", + "UMask": "0x01", + "EventName": "OCR.WRITE_ESTIMATE.MEMORY", + "BriefDescription": "Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM)", + "PublicDescription": "Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM)", + "Counter": "0,1,2,3", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFBFF80822", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + } + ] +} \ No newline at end of file diff --git a/cmd/metrics/resources/perfmon/spr/sapphirerapids_metrics.json b/cmd/metrics/resources/perfmon/spr/sapphirerapids_metrics.json new file mode 100644 index 00000000..7b79dd35 --- /dev/null +++ b/cmd/metrics/resources/perfmon/spr/sapphirerapids_metrics.json @@ -0,0 +1,14709 @@ +{ + "Header": { + "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Metrics for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture0", + "DatePublished": "06/17/2025", + "Version": "1.1", + "Legend": "", + "TmaVersion": "5.1", + "TmaFlavor": "Full" + }, + "Metrics": [ + { + "MetricName": "cpu_operating_frequency", + "LegacyName": "metric_CPU operating frequency (in GHz)", + "Level": 1, + "BriefDescription": "CPU operating frequency (in GHz)", + "UnitOfMeasure": "GHz", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + } + ], + "Formula": "(a / b * c) / 1000000000", + "Category": "Freq", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "cpu_utilization", + "LegacyName": "metric_CPU utilization %", + "Level": 1, + "BriefDescription": "Percentage of time spent in the active CPU power state C0", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + }, + { + "Name": "TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "Category": "Util", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "cpi", + "LegacyName": "metric_CPI", + "Level": 1, + "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "CPI", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "loads_per_instr", + "LegacyName": "metric_loads per instr", + "Level": 1, + "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "stores_per_instr", + "LegacyName": "metric_stores per instr", + "Level": 1, + "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l1d_mpi", + "LegacyName": "metric_L1D MPI (includes data+rfo w/ prefetches)", + "Level": 1, + "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "L1D.REPLACEMENT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l1d_demand_data_read_hits_per_instr", + "LegacyName": "metric_L1D demand data read hits per instr", + "Level": 1, + "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L1_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", + "LegacyName": "metric_L1-I code read misses (w/ prefetches) per instr", + "Level": 1, + "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "L2_RQSTS.ALL_CODE_RD", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, I-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_demand_data_read_hits_per_instr", + "LegacyName": "metric_L2 demand data read hits per instr", + "Level": 1, + "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_mpi", + "LegacyName": "metric_L2 MPI (includes code+data+rfo w/ prefetches)", + "Level": 1, + "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "L2_LINES_IN.ALL", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_demand_data_read_mpi", + "LegacyName": "metric_L2 demand data read MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_demand_code_mpi", + "LegacyName": "metric_L2 demand code MPI", + "Level": 1, + "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "L2_RQSTS.CODE_RD_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, I-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_data_read_mpi_demand_plus_prefetch", + "LegacyName": "metric_LLC data read MPI (demand+prefetch)", + "Level": 1, + "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF", + "Alias": "c" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "(a + b + c) / d", + "Category": "MPI, D-side", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_code_read_mpi_demand_plus_prefetch", + "LegacyName": "metric_LLC code read MPI (demand+prefetch)", + "Level": 1, + "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "Alias": "b" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "b / d", + "Category": "MPI, I-side", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_latency", + "LegacyName": "metric_Average LLC demand data read miss latency (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "Latency", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_latency_for_local_requests", + "LegacyName": "metric_Average LLC demand data read miss latency for LOCAL requests (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to local memory in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "Latency", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_latency_for_remote_requests", + "LegacyName": "metric_Average LLC demand data read miss latency for REMOTE requests (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to remote memory in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "Latency", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_to_pmem_latency", + "LegacyName": "metric_Average LLC demand data read miss to DCPMEM latency (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to Intel(R) Optane(TM) Persistent Memory(PMEM) in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "Latency", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_to_dram_latency", + "LegacyName": "metric_Average LLC demand data read miss to DRAM latency (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to DRAM in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "Latency", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "itlb_2nd_level_mpi", + "LegacyName": "metric_ITLB (2nd level) MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, I-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "itlb_2nd_level_large_page_mpi", + "LegacyName": "metric_ITLB (2nd level) large page MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "dtlb_2nd_level_load_mpi", + "LegacyName": "metric_DTLB (2nd level) load MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi", + "LegacyName": "metric_DTLB (2nd level) 2MB large page load MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "dtlb_2nd_level_store_mpi", + "LegacyName": "metric_DTLB (2nd level) store MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, D-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "numa_reads_addressed_to_local_dram", + "LegacyName": "metric_NUMA %_Reads addressed to local DRAM", + "Level": 1, + "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", + "Alias": "c" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (a + b) / (a + b + c + d)", + "Category": "NUMA", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "numa_reads_addressed_to_remote_dram", + "LegacyName": "metric_NUMA %_Reads addressed to remote DRAM", + "Level": 1, + "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", + "Alias": "c" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (c + d) / (a + b + c + d)", + "Category": "NUMA", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "uncore_frequency", + "LegacyName": "metric_uncore frequency GHz", + "Level": 1, + "BriefDescription": "Uncore operating frequency in GHz", + "UnitOfMeasure": "GHz", + "Events": [ + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "b" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "(a / (b * socket_count) / 1000000000) / DURATIONTIMEINSECONDS", + "Category": "Freq", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "upi_data_transmit_bw", + "LegacyName": "metric_UPI Data transmit BW (MB/sec) (only data)", + "Level": 1, + "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_UPI_TxL_FLITS.ALL_DATA", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * (64 / 9.0) / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW", + "ResolutionLevels": "UPI, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_bandwidth_read", + "LegacyName": "metric_memory bandwidth read (MB/sec)", + "Level": 1, + "BriefDescription": "DDR memory read bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT.RD", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, MC", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_bandwidth_write", + "LegacyName": "metric_memory bandwidth write (MB/sec)", + "Level": 1, + "BriefDescription": "DDR memory write bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT.WR", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, MC", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_bandwidth_total", + "LegacyName": "metric_memory bandwidth total (MB/sec)", + "Level": 1, + "BriefDescription": "DDR memory bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT.RD", + "Alias": "a" + }, + { + "Name": "UNC_M_CAS_COUNT.WR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, MC", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_extra_write_bw_due_to_directory_updates", + "LegacyName": "metric_memory extra write b/w due to directory updates (MB/sec)", + "Level": 1, + "BriefDescription": "Memory write bandwidth (MB/sec) caused by directory updates; includes DDR and Intel(R) Optane(TM) Persistent Memory(PMEM).", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_DIR_UPDATE.HA", + "Alias": "a" + }, + { + "Name": "UNC_CHA_DIR_UPDATE.TOR", + "Alias": "b" + }, + { + "Name": "UNC_M2M_DIRECTORY_UPDATE.ANY", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "((a + b + c) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, MC", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "pmem_memory_bandwidth_read", + "LegacyName": "metric_DCPMEM_memory bandwidth read (MB/sec)", + "Level": 1, + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory read bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_PMM_RPQ_INSERTS", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "pmem_memory_bandwidth_write", + "LegacyName": "metric_DCPMEM_memory bandwidth write (MB/sec)", + "Level": 1, + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory write bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_PMM_WPQ_INSERTS", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "pmem_memory_bandwidth_total", + "LegacyName": "metric_DCPMEM_memory bandwidth total (MB/sec)", + "Level": 1, + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_PMM_RPQ_INSERTS", + "Alias": "a" + }, + { + "Name": "UNC_M_PMM_WPQ_INSERTS", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_read", + "LegacyName": "metric_IO_bandwidth_disk_or_network_writes (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_write", + "LegacyName": "metric_IO_bandwidth_disk_or_network_reads (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_read_l3_miss", + "LegacyName": "metric_IO % of inbound reads that miss L3", + "Level": 1, + "BriefDescription": "Percentage of inbound reads initiated by end device controllers that miss the L3 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_partial_write_l3_miss", + "LegacyName": "metric_IO % of inbound partial writes that miss L3", + "Level": 1, + "BriefDescription": "Percentage of inbound partial cacheline writes initiated by end device controllers that miss the L3 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_RFO", + "Alias": "c" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ((b + d) / (a + c) )", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_full_write_l3_miss", + "LegacyName": "metric_IO % of inbound full writes that miss L3", + "Level": 1, + "BriefDescription": "Percentage of inbound full cacheline writes initiated by end device controllers that miss the L3 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * (b / a)", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "percent_uops_delivered_from_decoded_icache", + "LegacyName": "metric_% Uops delivered from decoded Icache (DSB)", + "Level": 1, + "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "LSD.UOPS", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (a / (a + b + c + d) )", + "Category": "I-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline", + "LegacyName": "metric_% Uops delivered from legacy decode pipeline (MITE)", + "Level": 1, + "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "LSD.UOPS", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (b / (a + b + c + d) )", + "Category": "I-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "percent_uops_delivered_from_microcode_sequencer", + "LegacyName": "metric_% Uops delivered from microcode sequencer (MS)", + "Level": 1, + "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_UOPS", + "Alias": "b" + }, + { + "Name": "IDQ.MS_UOPS", + "Alias": "c" + }, + { + "Name": "LSD.UOPS", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (c / (a + b + c + d) )", + "Category": "I-side", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_read_local", + "LegacyName": "metric_IO bandwidth read local (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the local CPU socket.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_read_remote", + "LegacyName": "metric_IO bandwidth read remote (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from a remote CPU socket.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_write_local", + "LegacyName": "metric_IO bandwidth write local (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the local CPU socket.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_write_remote", + "LegacyName": "metric_IO bandwidth write remote (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to a remote CPU socket.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_miss_local_memory_bandwidth_read", + "LegacyName": "metric_llc_miss_local_memory_bandwidth_read_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.READS_LOCAL", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_miss_local_memory_bandwidth_write", + "LegacyName": "metric_llc_miss_local_memory_bandwidth_write_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.WRITES_LOCAL", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_miss_remote_memory_bandwidth_read", + "LegacyName": "metric_llc_miss_remote_memory_bandwidth_read_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.READS_REMOTE", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_miss_remote_memory_bandwidth_write", + "LegacyName": "metric_llc_miss_remote_memory_bandwidth_write_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.WRITES_REMOTE", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "upi_data_receive_bw", + "LegacyName": "metric_UPI Data receive BW (MB/sec) (only data)", + "Level": 1, + "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data receive bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_UPI_RxL_FLITS.ALL_DATA", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * (64 / 9.0) / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW", + "ResolutionLevels": "UPI, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "iio_bandwidth_read", + "LegacyName": "metric_IIO_bandwidth_read (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth observed by the integrated I/O traffic controller (IIO) of IO reads that are initiated by end device controllers that are requesting memory from the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 4 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "IO, BW", + "ResolutionLevels": "IIO, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "iio_bandwidth_write", + "LegacyName": "metric_IIO_bandwidth_write (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth observed by the integrated I/O traffic controller (IIO) of IO writes that are initiated by end device controllers that are writing memory to the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 4 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "IO, BW", + "ResolutionLevels": "IIO, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_read_l3_miss", + "LegacyName": "metric_IO_bandwidth_read_L3_miss (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of inbound IO reads that are initiated by end device controllers that are requesting memory from the CPU and miss the L3 cache.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_write_l3_miss", + "LegacyName": "metric_IO_bandwidth_write_L3_miss (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of inbound IO writes that are initiated by end device controllers that are writing memory to the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Bottleneck_Mispredictions", + "LegacyName": "metric_TMA_Bottleneck_Mispredictions", + "Level": 1, + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_RETIRED.MS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "h" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "i" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "j" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "k" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "l" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "m" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "n" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "o" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "p" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "q" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "r" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "s" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "t" + }, + { + "Name": "DECODE.LCP", + "Alias": "u" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "v" + } + ], + "Constants": [], + "Formula": "100 * ( 1 - ( 10 * ( a / ( b ) ) * ( max( ( c / ( d + e + f + g ) ) * ( 1 - h / ( i - j ) ) , 0.0001 ) ) / ( c / ( d + e + f + g ) ) ) ) * ( ( c / ( d + e + f + g ) ) + ( ( k / ( d + e + f + g ) - l / ( b ) ) ) * ( ( ( c / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - l / ( b ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) * m / ( n ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) )", + "BaseFormula": "100 * ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * ( tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Mispredictions" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Mispredictions > 20", + "ThresholdIssues": "$issueBM" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BadSpec;BrMispredicts;BvMP", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Big_Code", + "LegacyName": "metric_TMA_Bottleneck_Big_Code", + "Level": 1, + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "j" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "k" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "l" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "m" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "n" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "o" + }, + { + "Name": "DECODE.LCP", + "Alias": "p" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "q" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( h / ( i ) ) + ( j / ( i ) ) + ( k / ( i ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) )", + "BaseFormula": "100 * tma_fetch_latency * ( tma_itlb_misses + tma_icache_misses + tma_unknown_branches ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Big_Code" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Big_Code > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvBC;BigFootprint;Fed;Frontend;IcMiss;MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Instruction_Fetch_BW", + "LegacyName": "metric_TMA_Bottleneck_Instruction_Fetch_BW", + "Level": 1, + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "UOPS_RETIRED.MS", + "Alias": "g" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "h" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "i" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "j" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "k" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "l" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "m" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "n" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "o" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "p" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "q" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "r" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "s" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "t" + }, + { + "Name": "DECODE.LCP", + "Alias": "u" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "v" + }, + { + "Name": "INST_RETIRED.REP_ITERATION", + "Alias": "w" + }, + { + "Name": "UOPS_RETIRED.MS:c1", + "Alias": "x" + }, + { + "Name": "IDQ.MS_CYCLES_ANY", + "Alias": "y" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a / ( a + b + c + d ) - e / ( f ) ) - ( 1 - ( 10 * ( g / ( f ) ) * ( max( ( h / ( a + b + c + d ) ) * ( 1 - i / ( j - k ) ) , 0.0001 ) ) / ( h / ( a + b + c + d ) ) ) ) * ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) - ( ( 1 - w / x ) * ( ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) * ( ( ( 1 - ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * m / ( n ) ) + ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) * ( max( ( h / ( a + b + c + d ) ) * ( 1 - i / ( j - k ) ) , 0.0001 ) ) / ( h / ( a + b + c + d ) ) ) / ( ( ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) * m / ( n ) ) + ( ( 1 - ( ( h / ( a + b + c + d ) ) / ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) ) ) * m / ( n ) ) + ( q / ( n ) ) ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) + ( max( y , x / ( s / t ) ) / ( z if smt_on else ( n ) ) / 2.4 ) ) ) ) - ( 100 * ( ( l / ( a + b + c + d ) - e / ( f ) ) ) * ( ( p / ( n ) ) + ( o / ( n ) ) + ( q / ( n ) ) ) / ( ( o / ( n ) ) + ( p / ( n ) ) + ( m / ( n ) + ( q / ( n ) ) ) + ( ( 3 ) * r / ( s / t ) / ( n ) ) + ( u / ( n ) ) + ( v / ( n ) ) ) )", + "BaseFormula": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - inst_retired.rep_iteration / uops_retired.ms:c1 ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_ms ) ) ) - tma_bottleneck_big_code", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Instruction_Fetch_BW" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Instruction_Fetch_BW > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvFB;Fed;FetchBW;Frontend", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Data_Cache_Memory_Bandwidth", + "LegacyName": "metric_TMA_Bottleneck_Data_Cache_Memory_Bandwidth", + "Level": 1, + "BriefDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "a" + }, + { + "Name": "L1D_PEND_MISS.FB_FULL", + "Alias": "a_a" + }, + { + "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", + "Alias": "a_b" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a_c" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "a_d" + }, + { + "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "a_e" + }, + { + "Name": "LD_BLOCKS.STORE_FORWARD", + "Alias": "a_f" + }, + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "a_g" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a_i" + }, + { + "Name": "L2_RQSTS.ALL_RFO", + "Alias": "a_j" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "a_k" + }, + { + "Name": "L2_RQSTS.RFO_HIT", + "Alias": "a_l" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "a_m" + }, + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a_n" + }, + { + "Name": "MEM_LOAD_COMPLETED.L1_MISS_ANY", + "Alias": "a_o" + }, + { + "Name": "LD_BLOCKS.NO_SR", + "Alias": "a_p" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "h" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Alias": "i" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "k" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Alias": "l" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "m" + }, + { + "Name": "XQ.FULL_CYCLES", + "Alias": "n" + }, + { + "Name": "L1D_PEND_MISS.L2_STALLS", + "Alias": "o" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "p" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Alias": "s" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "t" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "u" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Alias": "v" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "w" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "x" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "Alias": "y" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": "20", + "Alias": "dependentloadsweight" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + }, + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "q" + } + ], + "Formula": "100 * ( ( ( a / ( b + c + d + e ) ) * ( ( ( f / ( g ) ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( min( g , l ) ) / ( g ) ) / ( ( ( min( g , l ) ) / ( g ) ) + ( ( min( g , m ) ) / ( g ) - ( ( min( g , l ) ) / ( g ) ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( ( j - f ) / ( g ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( n + o ) / ( g ) ) / ( ( ( ( ( 81 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( s * ( t / ( t + u ) ) ) + ( ( 79 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( v ) ) * ( 1 + ( w / x ) / 2 ) / ( g ) ) + ( ( ( 79 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( y + s * ( 1 - ( t / ( t + u ) ) ) ) * ( 1 + ( w / x ) / 2 ) / ( g ) ) + ( ( ( 37 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / p ) * q / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( z * ( 1 + ( w / x ) / 2 ) ) / ( g ) ) + ( ( n + o ) / ( g ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( max( ( h - i ) / ( g ) , 0 ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( a_a / ( g ) ) / ( ( min( ( 7 ) * a_b + a_c , max( a_d - a_e , 0 ) ) / ( g ) ) + ( 13 * a_f / ( g ) ) + ( min( 2 * ( a_g - w - x ) * dependentloadsweight / 100 , max( a_d - a_e , 0 ) ) / ( g ) ) + ( ( 16 * max( 0 , a_i - a_j ) + ( a_i / a_k ) * ( ( 10 ) * a_l + ( min( g , a_m ) ) ) ) / ( g ) ) + ( ( a_n / a_o ) * a_p / ( g ) ) + ( a_a / ( g ) ) ) ) ) )", + "BaseFormula": "100 * ( ( tma_memory_bound * ( tma_dram_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_mem_bandwidth / ( tma_mem_bandwidth + tma_mem_latency ) ) ) + ( tma_memory_bound * ( tma_l3_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_sq_full / ( tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full ) ) ) + ( tma_memory_bound * ( tma_l1_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_fb_full / ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_fb_full ) ) ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Data_Cache_Memory_Bandwidth" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Data_Cache_Memory_Bandwidth > 20", + "ThresholdIssues": "$issueBW" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMB;Mem;MemoryBW;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Data_Cache_Memory_Latency", + "LegacyName": "metric_TMA_Bottleneck_Data_Cache_Memory_Latency", + "Level": 1, + "BriefDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "a_a" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "a_c" + }, + { + "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "a_d" + }, + { + "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", + "Alias": "a_e" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a_f" + }, + { + "Name": "LD_BLOCKS.STORE_FORWARD", + "Alias": "a_g" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a_h" + }, + { + "Name": "L2_RQSTS.ALL_RFO", + "Alias": "a_i" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "a_j" + }, + { + "Name": "L2_RQSTS.RFO_HIT", + "Alias": "a_k" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "a_l" + }, + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a_m" + }, + { + "Name": "MEM_LOAD_COMPLETED.L1_MISS_ANY", + "Alias": "a_n" + }, + { + "Name": "LD_BLOCKS.NO_SR", + "Alias": "a_o" + }, + { + "Name": "L1D_PEND_MISS.FB_FULL", + "Alias": "a_p" + }, + { + "Name": "MEM_INST_RETIRED.SPLIT_STORES", + "Alias": "a_q" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "a_r" + }, + { + "Name": "MEM_STORE_RETIRED.L2_HIT", + "Alias": "a_s" + }, + { + "Name": "OCR.DEMAND_RFO.L3_MISS:ocr_msr_val=0x103b800002", + "Alias": "a_t" + }, + { + "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "Alias": "a_u" + }, + { + "Name": "OCR.STREAMING_WR.ANY_RESPONSE", + "Alias": "a_v" + }, + { + "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", + "Alias": "a_w" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a_x" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "h" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Alias": "i" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "k" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "l" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Alias": "m" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "n" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Alias": "q" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "r" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "s" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Alias": "t" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "u" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "v" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Alias": "w" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "Alias": "x" + }, + { + "Name": "XQ.FULL_CYCLES", + "Alias": "y" + }, + { + "Name": "L1D_PEND_MISS.L2_STALLS", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": "20", + "Alias": "dependentloadsweight" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + }, + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "o" + }, + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( ( a / ( b + c + d + e ) ) * ( ( ( f / ( g ) ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( min( g , l ) ) / ( g ) - ( ( min( g , m ) ) / ( g ) ) ) / ( ( ( min( g , m ) ) / ( g ) ) + ( ( min( g , l ) ) / ( g ) - ( ( min( g , m ) ) / ( g ) ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( ( j - f ) / ( g ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( ( 37 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( q * ( 1 + ( r / s ) / 2 ) ) / ( g ) ) / ( ( ( ( ( 81 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( t * ( u / ( u + v ) ) ) + ( ( 79 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( w ) ) * ( 1 + ( r / s ) / 2 ) / ( g ) ) + ( ( ( 79 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( x + t * ( 1 - ( u / ( u + v ) ) ) ) * ( 1 + ( r / s ) / 2 ) / ( g ) ) + ( ( ( 37 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( q * ( 1 + ( r / s ) / 2 ) ) / ( g ) ) + ( ( y + z ) / ( g ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( i - j ) / ( g ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( max( ( h - i ) / ( g ) , 0 ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( min( 2 * ( a_a - r - s ) * dependentloadsweight / 100 , max( a_c - a_d , 0 ) ) / ( g ) ) / ( ( min( ( 7 ) * a_e + a_f , max( a_c - a_d , 0 ) ) / ( g ) ) + ( 13 * a_g / ( g ) ) + ( min( 2 * ( a_a - r - s ) * dependentloadsweight / 100 , max( a_c - a_d , 0 ) ) / ( g ) ) + ( ( 16 * max( 0 , a_h - a_i ) + ( a_h / a_j ) * ( ( 10 ) * a_k + ( min( g , a_l ) ) ) ) / ( g ) ) + ( ( a_m / a_n ) * a_o / ( g ) ) + ( a_p / ( g ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( max( ( h - i ) / ( g ) , 0 ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( 16 * max( 0 , a_h - a_i ) + ( a_h / a_j ) * ( ( 10 ) * a_k + ( min( g , a_l ) ) ) ) / ( g ) ) / ( ( min( ( 7 ) * a_e + a_f , max( a_c - a_d , 0 ) ) / ( g ) ) + ( 13 * a_g / ( g ) ) + ( min( 2 * ( a_a - r - s ) * dependentloadsweight / 100 , max( a_c - a_d , 0 ) ) / ( g ) ) + ( ( 16 * max( 0 , a_h - a_i ) + ( a_h / a_j ) * ( ( 10 ) * a_k + ( min( g , a_l ) ) ) ) / ( g ) ) + ( ( a_m / a_n ) * a_o / ( g ) ) + ( a_p / ( g ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( max( ( h - i ) / ( g ) , 0 ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( a_m / a_n ) * a_o / ( g ) ) / ( ( min( ( 7 ) * a_e + a_f , max( a_c - a_d , 0 ) ) / ( g ) ) + ( 13 * a_g / ( g ) ) + ( min( 2 * ( a_a - r - s ) * dependentloadsweight / 100 , max( a_c - a_d , 0 ) ) / ( g ) ) + ( ( 16 * max( 0 , a_h - a_i ) + ( a_h / a_j ) * ( ( 10 ) * a_k + ( min( g , a_l ) ) ) ) / ( g ) ) + ( ( a_m / a_n ) * a_o / ( g ) ) + ( a_p / ( g ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( k / ( g ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( a_q / ( a_r if smt_on else ( g ) ) ) / ( ( ( ( a_s * ( 10 ) * ( 1 - ( a_h / a_j ) ) ) + ( 1 - ( a_h / a_j ) ) * ( min( g , a_l ) ) ) / ( g ) ) + ( ( ( 170 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_t + ( 81 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_u ) / ( g ) ) + ( a_q / ( a_r if smt_on else ( g ) ) ) + ( 9 * a_v / ( g ) ) + ( ( ( 7 ) * a_w + a_x ) / ( a_r if smt_on else ( g ) ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( k / ( g ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( ( a_s * ( 10 ) * ( 1 - ( a_h / a_j ) ) ) + ( 1 - ( a_h / a_j ) ) * ( min( g , a_l ) ) ) / ( g ) ) / ( ( ( ( a_s * ( 10 ) * ( 1 - ( a_h / a_j ) ) ) + ( 1 - ( a_h / a_j ) ) * ( min( g , a_l ) ) ) / ( g ) ) + ( ( ( 170 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_t + ( 81 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_u ) / ( g ) ) + ( a_q / ( a_r if smt_on else ( g ) ) ) + ( 9 * a_v / ( g ) ) + ( ( ( 7 ) * a_w + a_x ) / ( a_r if smt_on else ( g ) ) ) ) ) ) )", + "BaseFormula": "100 * ( ( tma_memory_bound * ( tma_dram_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_mem_latency / ( tma_mem_bandwidth + tma_mem_latency ) ) ) + ( tma_memory_bound * ( tma_l3_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_l3_hit_latency / ( tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full ) ) ) + ( tma_memory_bound * tma_l2_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) + ( tma_memory_bound * ( tma_l1_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_l1_latency_dependency / ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_fb_full ) ) ) + ( tma_memory_bound * ( tma_l1_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_lock_latency / ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_fb_full ) ) ) + ( tma_memory_bound * ( tma_l1_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_split_loads / ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_fb_full ) ) ) + ( tma_memory_bound * ( tma_store_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_split_stores / ( tma_store_latency + tma_false_sharing + tma_split_stores + tma_streaming_stores + tma_dtlb_store ) ) ) + ( tma_memory_bound * ( tma_store_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_store_latency / ( tma_store_latency + tma_false_sharing + tma_split_stores + tma_streaming_stores + tma_dtlb_store ) ) ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Data_Cache_Memory_Latency" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Data_Cache_Memory_Latency > 20", + "ThresholdIssues": "$issueLat" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvML;Mem;MemoryLat;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Memory_Data_TLBs", + "LegacyName": "metric_TMA_Bottleneck_Memory_Data_TLBs", + "Level": 1, + "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_COMPLETED.L1_MISS_ANY", + "Alias": "a_a" + }, + { + "Name": "LD_BLOCKS.NO_SR", + "Alias": "a_b" + }, + { + "Name": "L1D_PEND_MISS.FB_FULL", + "Alias": "a_c" + }, + { + "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", + "Alias": "a_d" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a_e" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "a_f" + }, + { + "Name": "MEM_STORE_RETIRED.L2_HIT", + "Alias": "a_g" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a_h" + }, + { + "Name": "OCR.DEMAND_RFO.L3_MISS:ocr_msr_val=0x103b800002", + "Alias": "a_k" + }, + { + "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "Alias": "a_l" + }, + { + "Name": "MEM_INST_RETIRED.SPLIT_STORES", + "Alias": "a_m" + }, + { + "Name": "OCR.STREAMING_WR.ANY_RESPONSE", + "Alias": "a_n" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "f" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Alias": "g" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "h" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Alias": "i" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "k" + }, + { + "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", + "Alias": "l" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "m" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "n" + }, + { + "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "o" + }, + { + "Name": "LD_BLOCKS.STORE_FORWARD", + "Alias": "p" + }, + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "q" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "r" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "s" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "u" + }, + { + "Name": "L2_RQSTS.ALL_RFO", + "Alias": "v" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "w" + }, + { + "Name": "L2_RQSTS.RFO_HIT", + "Alias": "x" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "y" + }, + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "a_i" + }, + { + "Name": "20", + "Alias": "dependentloadsweight" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + }, + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a / ( b + c + d + e ) ) * ( ( max( ( f - g ) / ( h ) , 0 ) ) / max( ( a / ( b + c + d + e ) ) , ( ( max( ( f - g ) / ( h ) , 0 ) ) + ( ( g - i ) / ( h ) ) + ( ( i - j ) / ( h ) ) + ( ( j / ( h ) ) ) + ( k / ( h ) ) ) ) ) * ( ( min( ( 7 ) * l + m , max( n - o , 0 ) ) / ( h ) ) / max( ( max( ( f - g ) / ( h ) , 0 ) ) , ( ( min( ( 7 ) * l + m , max( n - o , 0 ) ) / ( h ) ) + ( 13 * p / ( h ) ) + ( min( 2 * ( q - r - s ) * dependentloadsweight / 100 , max( n - o , 0 ) ) / ( h ) ) + ( ( 16 * max( 0 , u - v ) + ( u / w ) * ( ( 10 ) * x + ( min( h , y ) ) ) ) / ( h ) ) + ( ( z / a_a ) * a_b / ( h ) ) + ( a_c / ( h ) ) ) ) ) + ( ( a / ( b + c + d + e ) ) * ( ( k / ( h ) ) / ( ( max( ( f - g ) / ( h ) , 0 ) ) + ( ( g - i ) / ( h ) ) + ( ( i - j ) / ( h ) ) + ( ( j / ( h ) ) ) + ( k / ( h ) ) ) ) * ( ( ( ( 7 ) * a_d + a_e ) / ( a_f if smt_on else ( h ) ) ) / ( ( ( ( a_g * ( 10 ) * ( 1 - ( u / w ) ) ) + ( 1 - ( u / w ) ) * ( min( h , y ) ) ) / ( h ) ) + ( ( ( 170 * ( ( ( h ) / a_h ) * a_i / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_k + ( 81 * ( ( ( h ) / a_h ) * a_i / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_l ) / ( h ) ) + ( a_m / ( a_f if smt_on else ( h ) ) ) + ( 9 * a_n / ( h ) ) + ( ( ( 7 ) * a_d + a_e ) / ( a_f if smt_on else ( h ) ) ) ) ) ) )", + "BaseFormula": "100 * ( tma_memory_bound * ( tma_l1_bound / max( tma_memory_bound , ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) ) * ( tma_dtlb_load / max( tma_l1_bound , ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_fb_full ) ) ) + ( tma_memory_bound * ( tma_store_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_dtlb_store / ( tma_store_latency + tma_false_sharing + tma_split_stores + tma_streaming_stores + tma_dtlb_store ) ) ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Memory_Data_TLBs" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Memory_Data_TLBs > 20", + "ThresholdIssues": "$issueTLB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMT;Mem;MemoryTLB;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Memory_Synchronization", + "LegacyName": "metric_TMA_Bottleneck_Memory_Synchronization", + "Level": 1, + "BriefDescription": "Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "Alias": "a_a" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Alias": "a_b" + }, + { + "Name": "XQ.FULL_CYCLES", + "Alias": "a_c" + }, + { + "Name": "L1D_PEND_MISS.L2_STALLS", + "Alias": "a_d" + }, + { + "Name": "OCR.DEMAND_RFO.L3_MISS:ocr_msr_val=0x103b800002", + "Alias": "a_e" + }, + { + "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "Alias": "a_f" + }, + { + "Name": "MEM_STORE_RETIRED.L2_HIT", + "Alias": "a_g" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a_h" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "a_i" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "a_j" + }, + { + "Name": "MEM_INST_RETIRED.SPLIT_STORES", + "Alias": "a_k" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "a_l" + }, + { + "Name": "OCR.STREAMING_WR.ANY_RESPONSE", + "Alias": "a_m" + }, + { + "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", + "Alias": "a_n" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a_o" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "a_p" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "a_q" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "a_r" + }, + { + "Name": "MACHINE_CLEARS.MEMORY_ORDERING", + "Alias": "a_s" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "a_t" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "h" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Alias": "i" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "k" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "l" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Alias": "m" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "n" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Alias": "q" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "Alias": "r" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "s" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "t" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", + "Alias": "u" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "Alias": "v" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Alias": "w" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "x" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "y" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + }, + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "o" + }, + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a / ( b + c + d + e ) ) * ( ( ( ( f / ( g ) ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( min( g , l ) ) / ( g ) - ( ( min( g , m ) ) / ( g ) ) ) / ( ( ( min( g , m ) ) / ( g ) ) + ( ( min( g , l ) ) / ( g ) - ( ( min( g , m ) ) / ( g ) ) ) ) ) * ( ( ( ( 170 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * q + ( ( 170 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * r ) * ( 1 + ( s / t ) / 2 ) / ( g ) ) / ( ( ( ( 109 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * u * ( 1 + ( s / t ) / 2 ) / ( g ) ) + ( ( ( 190 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * v * ( 1 + ( s / t ) / 2 ) / ( g ) ) + ( ( ( ( 170 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * q + ( ( 170 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * r ) * ( 1 + ( s / t ) / 2 ) / ( g ) ) ) + ( ( ( j - f ) / ( g ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( ( ( 81 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( w * ( x / ( x + y ) ) ) + ( ( 79 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( z ) ) * ( 1 + ( s / t ) / 2 ) / ( g ) ) + ( ( ( 79 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_a + w * ( 1 - ( x / ( x + y ) ) ) ) * ( 1 + ( s / t ) / 2 ) / ( g ) ) ) / ( ( ( ( ( 81 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( w * ( x / ( x + y ) ) ) + ( ( 79 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( z ) ) * ( 1 + ( s / t ) / 2 ) / ( g ) ) + ( ( ( 79 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_a + w * ( 1 - ( x / ( x + y ) ) ) ) * ( 1 + ( s / t ) / 2 ) / ( g ) ) + ( ( ( 37 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_b * ( 1 + ( s / t ) / 2 ) ) / ( g ) ) + ( ( a_c + a_d ) / ( g ) ) ) + ( ( k / ( g ) ) / ( ( max( ( h - i ) / ( g ) , 0 ) ) + ( ( i - j ) / ( g ) ) + ( ( j - f ) / ( g ) ) + ( ( f / ( g ) ) ) + ( k / ( g ) ) ) ) * ( ( ( 170 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_e + ( 81 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_f ) / ( g ) ) / ( ( ( ( ( a_g * ( 10 ) * ( 1 - ( a_h / a_i ) ) ) + ( 1 - ( a_h / a_i ) ) * ( min( g , a_j ) ) ) / ( g ) ) + ( ( ( 170 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_e + ( 81 * ( ( ( g ) / n ) * o / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * a_f ) / ( g ) ) + ( a_k / ( a_l if smt_on else ( g ) ) ) + ( 9 * a_m / ( g ) ) + ( ( ( 7 ) * a_n + a_o ) / ( a_l if smt_on else ( g ) ) ) ) - ( ( ( a_g * ( 10 ) * ( 1 - ( a_h / a_i ) ) ) + ( 1 - ( a_h / a_i ) ) * ( min( g , a_j ) ) ) / ( g ) ) ) ) + ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - a_p / ( a_q ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( a_r / ( b + c + d + e ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - a_p / ( a_q ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( a_r / ( b + c + d + e ) ) ) ) * ( 1 - a_s / a_t ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - a_p / ( a_q ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( a_r / ( b + c + d + e ) ) ) ) * ( 1 - a_s / a_t ) , 0.0001 ) ) ) ) )", + "BaseFormula": "100 * ( tma_memory_bound * ( ( tma_dram_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_mem_latency / ( tma_mem_bandwidth + tma_mem_latency ) ) * tma_remote_cache / ( tma_local_mem + tma_remote_mem + tma_remote_cache ) + ( tma_l3_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_contested_accesses + tma_data_sharing ) / ( tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full ) + ( tma_store_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * tma_false_sharing / ( ( tma_store_latency + tma_false_sharing + tma_split_stores + tma_streaming_stores + tma_dtlb_store ) - tma_store_latency ) ) + tma_machine_clears * ( 1 - tma_other_nukes / ( tma_other_nukes ) ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Memory_Synchronization" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_Bottleneck_Memory_Synchronization > 10", + "ThresholdIssues": "$issueSyncxn" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMS;LockCont;Mem;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Compute_Bound_Est", + "LegacyName": "metric_TMA_Bottleneck_Compute_Bound_Est", + "Level": 1, + "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "e" + }, + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + }, + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.C02", + "Alias": "i" + }, + { + "Name": "EXE.AMX_BUSY", + "Alias": "j" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "k" + }, + { + "Name": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "Alias": "l" + }, + { + "Name": "RS.EMPTY_RESOURCE", + "Alias": "m" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "n" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "o" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "p" + }, + { + "Name": "EXE_ACTIVITY.2_3_PORTS_UTIL", + "Alias": "q" + }, + { + "Name": "UOPS_EXECUTED.CYCLES_GE_3", + "Alias": "r" + }, + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "s" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) * ( f / ( g ) ) / ( ( f / ( g ) ) + ( h / ( g ) + ( i / ( g ) ) ) + ( j / ( k if smt_on else ( g ) ) ) + ( ( ( ( l + max( m - h , 0 ) ) / ( g ) * ( n - o ) / ( g ) ) * ( g ) + ( p + ( d / ( b + c + d + a ) ) * q ) ) / ( g ) if ( f < ( n - o ) ) else ( p + ( d / ( b + c + d + a ) ) * q ) / ( g ) ) ) ) + ( ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) * ( j / ( k if smt_on else ( g ) ) ) / ( ( f / ( g ) ) + ( h / ( g ) + ( i / ( g ) ) ) + ( j / ( k if smt_on else ( g ) ) ) + ( ( ( ( l + max( m - h , 0 ) ) / ( g ) * ( n - o ) / ( g ) ) * ( g ) + ( p + ( d / ( b + c + d + a ) ) * q ) ) / ( g ) if ( f < ( n - o ) ) else ( p + ( d / ( b + c + d + a ) ) * q ) / ( g ) ) ) ) + ( ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) * ( ( ( ( ( l + max( m - h , 0 ) ) / ( g ) * ( n - o ) / ( g ) ) * ( g ) + ( p + ( d / ( b + c + d + a ) ) * q ) ) / ( g ) if ( f < ( n - o ) ) else ( p + ( d / ( b + c + d + a ) ) * q ) / ( g ) ) / ( ( f / ( g ) ) + ( h / ( g ) + ( i / ( g ) ) ) + ( j / ( k if smt_on else ( g ) ) ) + ( ( ( ( l + max( m - h , 0 ) ) / ( g ) * ( n - o ) / ( g ) ) * ( g ) + ( p + ( d / ( b + c + d + a ) ) * q ) ) / ( g ) if ( f < ( n - o ) ) else ( p + ( d / ( b + c + d + a ) ) * q ) / ( g ) ) ) ) * ( ( r / ( g ) ) / ( ( ( l + max( m - h , 0 ) ) / ( g ) * ( n - o ) / ( g ) ) + ( p / ( g ) ) + ( s / ( g ) ) + ( r / ( g ) ) ) ) ) )", + "BaseFormula": "100 * ( ( tma_core_bound * tma_divider / ( tma_divider + tma_serializing_operation + tma_amx_busy + tma_ports_utilization ) ) + ( tma_core_bound * tma_amx_busy / ( tma_divider + tma_serializing_operation + tma_amx_busy + tma_ports_utilization ) ) + ( tma_core_bound * ( tma_ports_utilization / ( tma_divider + tma_serializing_operation + tma_amx_busy + tma_ports_utilization ) ) * ( tma_ports_utilized_3m / ( tma_ports_utilized_0 + tma_ports_utilized_1 + tma_ports_utilized_2 + tma_ports_utilized_3m ) ) ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Compute_Bound_Est" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Compute_Bound_Est > 20", + "ThresholdIssues": "$issueComp" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvCB;Cor", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Irregular_Overhead", + "LegacyName": "metric_TMA_Bottleneck_Irregular_Overhead", + "Level": 1, + "BriefDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.REP_ITERATION", + "Alias": "a" + }, + { + "Name": "MACHINE_CLEARS.MEMORY_ORDERING", + "Alias": "a_a" + }, + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "a_b" + }, + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "a_c" + }, + { + "Name": "CPU_CLK_UNHALTED.C02", + "Alias": "a_d" + }, + { + "Name": "RS.EMPTY_RESOURCE", + "Alias": "a_e" + }, + { + "Name": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "Alias": "a_f" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "a_g" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "a_h" + }, + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "a_i" + }, + { + "Name": "EXE.AMX_BUSY", + "Alias": "a_j" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "a_k" + }, + { + "Name": "EXE_ACTIVITY.2_3_PORTS_UTIL", + "Alias": "a_l" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "a_m" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "a_n" + }, + { + "Name": "UOPS_RETIRED.MS:c1", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "h" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "i" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "j" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "k" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "l" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "m" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "n" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "o" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "p" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "q" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "r" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "s" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "t" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "u" + }, + { + "Name": "DECODE.LCP", + "Alias": "v" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "w" + }, + { + "Name": "IDQ.MS_CYCLES_ANY", + "Alias": "x" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "y" + }, + { + "Name": "UOPS_RETIRED.MS", + "Alias": "z" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( ( 1 - a / b ) * ( ( ( c / ( d + e + f + g ) - h / ( i ) ) ) * ( ( ( 3 ) * j / ( k / l ) / ( m ) ) + ( n / ( m ) + ( o / ( m ) ) ) * ( ( ( 1 - ( ( p / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) ) * n / ( m ) ) + ( ( ( p / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) * n / ( m ) ) * ( max( ( p / ( d + e + f + g ) ) * ( 1 - q / ( r - s ) ) , 0.0001 ) ) / ( p / ( d + e + f + g ) ) ) / ( ( ( ( p / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) * n / ( m ) ) + ( ( 1 - ( ( p / ( d + e + f + g ) ) / ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) ) ) * n / ( m ) ) + ( o / ( m ) ) ) ) / ( ( t / ( m ) ) + ( u / ( m ) ) + ( n / ( m ) + ( o / ( m ) ) ) + ( ( 3 ) * j / ( k / l ) / ( m ) ) + ( v / ( m ) ) + ( w / ( m ) ) ) + ( max( x , b / ( k / l ) ) / ( y if smt_on else ( m ) ) / 2.4 ) ) ) + ( 10 * ( z / ( i ) ) * ( max( ( p / ( d + e + f + g ) ) * ( 1 - q / ( r - s ) ) , 0.0001 ) ) / ( p / ( d + e + f + g ) ) ) * ( p / ( d + e + f + g ) ) + ( ( max( 0 , ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) - ( p / ( d + e + f + g ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) - ( p / ( d + e + f + g ) ) ) ) * ( 1 - a_a / s ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( d / ( d + e + f + g ) - h / ( i ) ) + ( g / ( d + e + f + g ) ) + ( f / ( d + e + f + g ) ) ) , 0 ) ) - ( p / ( d + e + f + g ) ) ) ) * ( 1 - a_a / s ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( g / ( d + e + f + g ) ) - ( a_b / ( d + e + f + g ) ) ) ) * ( ( a_c / ( m ) + ( a_d / ( m ) ) ) + a_e / ( m ) * ( ( a_f + max( a_e - a_c , 0 ) ) / ( m ) * ( a_g - a_h ) / ( m ) ) ) / ( ( a_i / ( m ) ) + ( a_c / ( m ) + ( a_d / ( m ) ) ) + ( a_j / ( y if smt_on else ( m ) ) ) + ( ( ( ( a_f + max( a_e - a_c , 0 ) ) / ( m ) * ( a_g - a_h ) / ( m ) ) * ( m ) + ( a_k + ( f / ( d + e + f + g ) ) * a_l ) ) / ( m ) if ( a_i < ( a_g - a_h ) ) else ( a_k + ( f / ( d + e + f + g ) ) * a_l ) / ( m ) ) ) ) + ( ( ( ( z / ( i ) ) / ( ( max( 0 , ( a_m / ( d + e + f + g ) ) - ( z / ( i ) ) ) ) + ( z / ( i ) ) ) ) * ( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * a_n / ( i ) ) / ( z / ( i ) ) ) ) * ( a_m / ( d + e + f + g ) ) ) )", + "BaseFormula": "100 * ( ( ( 1 - inst_retired.rep_iteration / uops_retired.ms:c1 ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_ms ) ) + ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) * tma_branch_mispredicts + ( tma_machine_clears * tma_other_nukes / ( tma_other_nukes ) ) + ( tma_core_bound * ( tma_serializing_operation + rs.empty_resource / tma_info_thread_clks * tma_ports_utilized_0 ) / ( tma_divider + tma_serializing_operation + tma_amx_busy + tma_ports_utilization ) ) + ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * tma_heavy_operations ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Irregular_Overhead" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_Bottleneck_Irregular_Overhead > 10", + "ThresholdIssues": "$issueMS" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BvIO;Cor;Ret", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Other_Bottlenecks", + "LegacyName": "metric_TMA_Bottleneck_Other_Bottlenecks", + "Level": 1, + "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end. Examples include data-dependencies (Core Bound when Low ILP) and other unlisted memory-related stalls.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "a_a" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "a_b" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "a_c" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Alias": "a_d" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Alias": "a_e" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "a_f" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Alias": "a_g" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "a_h" + }, + { + "Name": "XQ.FULL_CYCLES", + "Alias": "a_i" + }, + { + "Name": "L1D_PEND_MISS.L2_STALLS", + "Alias": "a_j" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a_k" + }, + { + "Name": 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/ ( i ) ) ) ) ) + ( ( a_a / ( b + c + d + e ) ) * ( ( max( ( a_c - a_d ) / ( i ) , 0 ) ) / ( ( max( ( a_c - a_d ) / ( i ) , 0 ) ) + ( ( a_d - a_e ) / ( i ) ) + ( ( a_e - a_b ) / ( i ) ) + ( ( a_b / ( i ) ) ) + ( a_f / ( i ) ) ) ) * ( ( ( 16 * max( 0 , b_d - b_e ) + ( b_d / b_f ) * ( ( 10 ) * b_g + ( min( i , b_h ) ) ) ) / ( i ) ) / ( ( min( ( 7 ) * a_w + a_x , max( a_y - a_z , 0 ) ) / ( i ) ) + ( 13 * b_a / ( i ) ) + ( min( 2 * ( b_b - a_r - a_s ) * dependentloadsweight / 100 , max( a_y - a_z , 0 ) ) / ( i ) ) + ( ( 16 * max( 0 , b_d - b_e ) + ( b_d / b_f ) * ( ( 10 ) * b_g + ( min( i , b_h ) ) ) ) / ( i ) ) + ( ( b_i / b_j ) * b_k / ( i ) ) + ( a_v / ( i ) ) ) ) ) + ( ( a_a / ( b + c + d + e ) ) * ( ( max( ( a_c - a_d ) / ( i ) , 0 ) ) / ( ( max( ( a_c - a_d ) / ( i ) , 0 ) ) + ( ( a_d - a_e ) / ( i ) ) + ( ( a_e - a_b ) / ( i ) ) + ( ( a_b / ( i ) ) ) + ( a_f / ( i ) ) ) ) * ( ( ( b_i / b_j ) * b_k / ( i ) ) / ( ( min( ( 7 ) * a_w + a_x , max( a_y - a_z , 0 ) ) / ( i ) ) + ( 13 * b_a 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i ) ) / ( ( max( ( a_c - a_d ) / ( i ) , 0 ) ) + ( ( a_d - a_e ) / ( i ) ) + ( ( a_e - a_b ) / ( i ) ) + ( ( a_b / ( i ) ) ) + ( a_f / ( i ) ) ) ) * ( ( ( ( b_m * ( 10 ) * ( 1 - ( b_d / b_f ) ) ) + ( 1 - ( b_d / b_f ) ) * ( min( i , b_h ) ) ) / ( i ) ) / ( ( ( ( b_m * ( 10 ) * ( 1 - ( b_d / b_f ) ) ) + ( 1 - ( b_d / b_f ) ) * ( min( i , b_h ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_n + ( 81 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_o ) / ( i ) ) + ( b_l / ( z if smt_on else ( i ) ) ) + ( 9 * b_p / ( i ) ) + ( ( ( 7 ) * b_q + b_r ) / ( z if smt_on else ( i ) ) ) ) ) ) ) ) + ( 100 * ( ( a_a / ( b + c + d + e ) ) * ( ( max( ( a_c - a_d ) / ( i ) , 0 ) ) / max( ( a_a / ( b + c + d + e ) ) , ( ( max( ( a_c - a_d ) / ( i ) , 0 ) ) + ( ( a_d - a_e ) / ( i ) ) + ( ( a_e - a_b ) / ( i ) ) + ( ( a_b / ( i ) ) ) + ( a_f / ( i ) ) ) ) ) * ( ( min( ( 7 ) * a_w + a_x , max( a_y - a_z , 0 ) ) / ( i ) ) / max( ( max( ( a_c - a_d ) / ( i ) , 0 ) ) , ( ( min( ( 7 ) * a_w + a_x , max( a_y - a_z , 0 ) ) / ( i ) ) + ( 13 * b_a / ( i ) ) + ( min( 2 * ( b_b - a_r - a_s ) * dependentloadsweight / 100 , max( a_y - a_z , 0 ) ) / ( i ) ) + ( ( 16 * max( 0 , b_d - b_e ) + ( b_d / b_f ) * ( ( 10 ) * b_g + ( min( i , b_h ) ) ) ) / ( i ) ) + ( ( b_i / b_j ) * b_k / ( i ) ) + ( a_v / ( i ) ) ) ) ) + ( ( a_a / ( b + c + d + e ) ) * ( ( a_f / ( i ) ) / ( ( max( ( a_c - a_d ) / ( i ) , 0 ) ) + ( ( a_d - a_e ) / ( i ) ) + ( ( a_e - a_b ) / ( i ) ) + ( ( a_b / ( i ) ) ) + ( a_f / ( i ) ) ) ) * ( ( ( ( 7 ) * b_q + b_r ) / ( z if smt_on else ( i ) ) ) / ( ( ( ( b_m * ( 10 ) * ( 1 - ( b_d / b_f ) ) ) + ( 1 - ( b_d / b_f ) ) * ( min( i , b_h ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_n + ( 81 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_o ) / ( i ) ) + ( b_l / ( z if smt_on else ( i ) ) ) + ( 9 * b_p / ( i ) ) + ( ( ( 7 ) * b_q + b_r ) / ( z if smt_on else ( i ) ) ) ) ) ) ) ) + ( 100 * ( ( a_a / ( b + c + d + e ) ) * ( ( ( ( a_b / ( i ) ) ) / ( ( max( ( a_c - a_d ) / ( i ) , 0 ) ) + ( ( a_d - a_e ) / ( i ) ) + ( ( a_e - a_b ) / ( i ) ) + ( ( a_b / ( i ) ) ) + ( a_f / ( i ) ) ) ) * ( ( ( min( i , a_h ) ) / ( i ) - ( ( min( i , a_g ) ) / ( i ) ) ) / ( ( ( min( i , a_g ) ) / ( i ) ) + ( ( min( i , a_h ) ) / ( i ) - ( ( min( i , a_g ) ) / ( i ) ) ) ) ) * ( ( ( ( 170 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_s + ( ( 170 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_t ) * ( 1 + ( a_r / a_s ) / 2 ) / ( i ) ) / ( ( ( ( 109 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_u * ( 1 + ( a_r / a_s ) / 2 ) / ( i ) ) + ( ( ( 190 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_v * ( 1 + ( a_r / a_s ) / 2 ) / ( i ) ) + ( ( ( ( 170 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_s + ( ( 170 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * b_t ) * ( 1 + ( a_r / a_s ) / 2 ) / ( i ) ) ) + ( ( ( a_e - a_b ) / ( i ) ) / ( ( max( ( a_c - a_d ) / ( i ) , 0 ) ) + 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( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_n * ( a_o / ( a_o + a_p ) ) ) + ( ( 79 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_q ) ) * ( 1 + ( a_r / a_s ) / 2 ) / ( i ) ) + ( ( ( 79 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_t + a_n * ( 1 - ( a_o / ( a_o + a_p ) ) ) ) * ( 1 + ( a_r / a_s ) / 2 ) / ( i ) ) + ( ( ( 37 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( a_u * ( 1 + ( a_r / a_s ) / 2 ) ) / ( i ) ) + ( ( a_i + a_j ) / ( i ) ) ) + ( ( a_f / ( i ) ) / ( ( max( ( a_c - a_d ) / ( i ) , 0 ) ) + ( ( a_d - a_e ) / ( i ) ) + ( ( a_e - a_b ) / ( i ) ) + ( ( a_b / ( i ) ) ) + ( a_f / ( i ) ) ) ) * ( ( ( 170 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_n + ( 81 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_o ) / ( i ) ) / ( ( ( ( ( b_m * ( 10 ) * ( 1 - ( b_d / b_f ) ) ) + ( 1 - ( b_d / b_f ) ) * ( min( i , b_h ) ) ) / ( i ) ) + ( ( ( 170 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_n + ( 81 * ( ( ( i ) / a_k ) * a_l / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * b_o ) / ( i ) ) + ( b_l / ( z if smt_on else ( i ) ) ) + ( 9 * b_p / ( i ) ) + ( ( ( 7 ) * b_q + b_r ) / ( z if smt_on else ( i ) ) ) ) - ( ( ( b_m * ( 10 ) * ( 1 - ( b_d / b_f ) ) ) + ( 1 - ( b_d / b_f ) ) * ( min( i , b_h ) ) ) / ( i ) ) ) ) + ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - b_w / v ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - b_w / v ) , 0.0001 ) ) ) ) ) ) + ( 100 * ( ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_a / ( b + c + d + e ) ) ) ) * ( b_x / ( i ) ) / ( ( b_x / ( i ) ) + ( b_y / ( i ) + ( b_z / ( i ) ) ) + ( c_a / ( z if smt_on else ( i ) ) ) + ( ( ( ( c_b + max( c_c - b_y , 0 ) ) / ( i ) * ( c_d - a_c ) / ( i ) ) * ( i ) + ( c_e + ( d / ( b + c + d + e ) ) * c_f ) ) / ( i ) if ( b_x < ( c_d - a_c ) ) else ( c_e + ( d / ( b + c + d + e ) ) * c_f ) / ( i ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_a / ( b + c + d + e ) ) ) ) * ( c_a / ( z if smt_on else ( i ) ) ) / ( ( b_x / ( i ) ) + ( b_y / ( i ) + ( b_z / ( i ) ) ) + ( c_a / ( z if smt_on else ( i ) ) ) + ( ( ( ( c_b + max( c_c - b_y , 0 ) ) / ( i ) * ( c_d - a_c ) / ( i ) ) * ( i ) + ( c_e + ( d / ( b + c + d + e ) ) * c_f ) ) / ( i ) if ( b_x < ( c_d - a_c ) ) else ( c_e + ( d / ( b + c + d + e ) ) * c_f ) / ( i ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_a / ( b + c + d + e ) ) ) ) * ( ( ( ( ( c_b + max( c_c - b_y , 0 ) ) / ( i ) * ( c_d - a_c ) / ( i ) ) * ( i ) + ( c_e + ( d / ( b + c + d + e ) ) * c_f ) ) / ( i ) if ( b_x < ( c_d - a_c ) ) else ( c_e + ( d / ( b + c + d + e ) ) * c_f ) / ( i ) ) / ( ( b_x / ( i ) ) + ( b_y / ( i ) + ( b_z / ( i ) ) ) + ( c_a / ( z if smt_on else ( i ) ) ) + ( ( ( ( c_b + max( c_c - b_y , 0 ) ) / ( i ) * ( c_d - a_c ) / ( i ) ) * ( i ) + ( c_e + ( d / ( b + c + d + e ) ) * c_f ) ) / ( i ) if ( b_x < ( c_d - a_c ) ) else ( c_e + ( d / ( b + c + d + e ) ) * c_f ) / ( i ) ) ) ) * ( ( c_g / ( i ) ) / ( ( ( c_b + max( c_c - b_y , 0 ) ) / ( i ) * ( c_d - a_c ) / ( i ) ) + ( c_e / ( i ) ) + ( c_h / ( i ) ) + ( c_g / ( i ) ) ) ) ) ) ) + ( 100 * ( ( ( 1 - w / x ) * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) * ( ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) / ( ( ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * l / ( i ) ) + ( ( 1 - ( ( s / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * l / ( i ) ) + ( k / ( i ) ) ) ) / ( ( j / ( i ) ) + ( h / ( i ) ) + ( l / ( i ) + ( k / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) + ( max( y , x / ( n / o ) ) / ( z if smt_on else ( i ) ) / 2.4 ) ) ) + ( 10 * ( r / ( g ) ) * ( max( ( s / ( b + c + d + e ) ) * ( 1 - t / ( u - v ) ) , 0.0001 ) ) / ( s / ( b + c + d + e ) ) ) * ( s / ( b + c + d + e ) ) + ( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - b_w / v ) , 0.0001 ) ) / ( ( max( ( max( 0 , ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) - ( s / ( b + c + d + e ) ) ) ) * ( 1 - b_w / v ) , 0.0001 ) ) ) ) + ( ( max( 0 , ( e / ( b + c + d + e ) ) - ( a_a / ( b + c + d + e ) ) ) ) * ( ( b_y / ( i ) + ( b_z / ( i ) ) ) + c_c / ( i ) * ( ( c_b + max( c_c - b_y , 0 ) ) / ( i ) * ( c_d - a_c ) / ( i ) ) ) / ( ( b_x / ( i ) ) + ( b_y / ( i ) + ( b_z / ( i ) ) ) + ( c_a / ( z if smt_on else ( i ) ) ) + ( ( ( ( c_b + max( c_c - b_y , 0 ) ) / ( i ) * ( c_d - a_c ) / ( i ) ) * ( i ) + ( c_e + ( d / ( b + c + d + e ) ) * c_f ) ) / ( i ) if ( b_x < ( c_d - a_c ) ) else ( c_e + ( d / ( b + c + d + e ) ) * c_f ) / ( i ) ) ) ) + ( ( ( ( r / ( g ) ) / ( ( max( 0 , ( c_i / ( b + c + d + e ) ) - ( r / ( g ) ) ) ) + ( r / ( g ) ) ) ) * ( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c_j / ( g ) ) / ( r / ( g ) ) ) ) * ( c_i / ( b + c + d + e ) ) ) ) ) + ( 100 * ( ( c_k + 2 * c_l + c_m ) / ( g ) ) ) + ( 100 * ( ( d / ( b + c + d + e ) ) - ( ( c_k + 2 * c_l + c_m ) / ( g ) ) - ( ( ( ( r / ( g ) ) / ( ( max( 0 , ( c_i / ( b + c + d + e ) ) - ( r / ( g ) ) ) ) + ( r / ( g ) ) ) ) * ( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c_j / ( g ) ) / ( r / ( g ) ) ) ) * ( c_i / ( b + c + d + e ) ) ) ) ) )", + "BaseFormula": "100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_data_cache_memory_bandwidth + tma_bottleneck_data_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Other_Bottlenecks" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Other_Bottlenecks > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvOB;Cor;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Branching_Overhead", + "LegacyName": "metric_TMA_Bottleneck_Branching_Overhead", + "Level": 1, + "BriefDescription": "Total pipeline cost of instructions used for program control-flow - a subset of the Retiring category in TMA. Examples include function calls; loops and alignments. (A lower bound)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "b" + }, + { + "Name": "INST_RETIRED.NOP", + "Alias": "c" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + 2 * b + c ) / ( d ) )", + "BaseFormula": "100 * ( ( br_inst_retired.all_branches + 2 * br_inst_retired.near_call + inst_retired.nop ) / tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Branching_Overhead" + } + ], + "Formula": "a > 5", + "BaseFormula": "metric_TMA_Bottleneck_Branching_Overhead > 5", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvBO;Ret", + "LocateWith": "" + }, + { + "MetricName": "Bottleneck_Useful_Work", + "LegacyName": "metric_TMA_Bottleneck_Useful_Work", + "Level": 1, + "BriefDescription": "Total pipeline cost of \"useful operations\" - the portion of Retiring category not covered by Branching_Overhead nor Irregular_Overhead.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "e" + }, + { + "Name": "BR_INST_RETIRED.NEAR_CALL", + "Alias": "f" + }, + { + "Name": "INST_RETIRED.NOP", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + }, + { + "Name": "UOPS_RETIRED.MS", + "Alias": "i" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "j" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "k" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b + c + a + d ) ) - ( ( e + 2 * f + g ) / ( h ) ) - ( ( ( ( i / ( h ) ) / ( ( max( 0 , ( j / ( b + c + a + d ) ) - ( i / ( h ) ) ) ) + ( i / ( h ) ) ) ) * ( ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * k / ( h ) ) / ( i / ( h ) ) ) ) * ( j / ( b + c + a + d ) ) ) )", + "BaseFormula": "100 * ( tma_retiring - ( ( br_inst_retired.all_branches + 2 * br_inst_retired.near_call + inst_retired.nop ) / tma_info_thread_slots ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * tma_heavy_operations ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bottleneck_Useful_Work" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Bottleneck_Useful_Work > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvUW;Ret", + "LocateWith": "" + }, + { + "MetricName": "Frontend_Bound", + "LegacyName": "metric_TMA_Frontend_Bound(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( a + b + c + d ) - e / ( f ) )", + "BaseFormula": "perf_metrics.frontend_bound / ( perf_metrics.frontend_bound + perf_metrics.bad_speculation + perf_metrics.retiring + perf_metrics.backend_bound ) - int_misc.uop_dropping / tma_info_thread_slots", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 15", + "BaseFormula": "metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvFB;BvIO;TmaL1;PGO", + "LocateWith": "FRONTEND_RETIRED.LATENCY_GE_4" + }, + { + "MetricName": "Fetch_Latency", + "LegacyName": "metric_TMA_..Fetch_Latency(%)", + "ParentCategory": "Frontend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b + c + d + e ) - f / ( g ) ) )", + "BaseFormula": "( perf_metrics.fetch_latency / ( perf_metrics.frontend_bound + perf_metrics.bad_speculation + perf_metrics.retiring + perf_metrics.backend_bound ) - int_misc.uop_dropping / tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 15", + "BaseFormula": "metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Frontend;TmaL2", + "LocateWith": "FRONTEND_RETIRED.LATENCY_GE_16;FRONTEND_RETIRED.LATENCY_GE_8" + }, + { + "MetricName": "ICache_Misses", + "LegacyName": "metric_TMA_....ICache_Misses(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "icache_data.stalls / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....ICache_Misses(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....ICache_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss", + "LocateWith": "FRONTEND_RETIRED.L2_MISS;FRONTEND_RETIRED.L1I_MISS" + }, + { + "MetricName": "Code_L2_Hit", + "LegacyName": "metric_TMA_......Code_L2_Hit(%)", + "ParentCategory": "ICache_Misses", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles the CPU was stalled due to instruction cache misses that hit in the L2 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b ) ) - ( c / ( b ) ) ) )", + "BaseFormula": "max( 0 , tma_icache_misses - tma_code_l2_miss )", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Code_L2_Hit(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....ICache_Misses(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 15", + "BaseFormula": "metric_TMA_......Code_L2_Hit(%) > 5 & metric_TMA_....ICache_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "IcMiss;FetchLat;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Code_L2_Miss", + "LegacyName": "metric_TMA_......Code_L2_Miss(%)", + "ParentCategory": "ICache_Misses", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles the CPU was stalled due to instruction cache misses that miss in the L2 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "offcore_requests_outstanding.cycles_with_demand_code_rd / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Code_L2_Miss(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....ICache_Misses(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 15", + "BaseFormula": "metric_TMA_......Code_L2_Miss(%) > 5 & metric_TMA_....ICache_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "IcMiss;FetchLat;Offcore", + "LocateWith": "" + }, + { + "MetricName": "ITLB_Misses", + "LegacyName": "metric_TMA_....ITLB_Misses(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "icache_tag.stalls / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....ITLB_Misses(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....ITLB_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB", + "LocateWith": "FRONTEND_RETIRED.STLB_MISS;FRONTEND_RETIRED.ITLB_MISS" + }, + { + "MetricName": "Code_STLB_Hit", + "LegacyName": "metric_TMA_......Code_STLB_Hit(%)", + "ParentCategory": "ITLB_Misses", + "Level": 4, + "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) ITLB was missed by instructions fetches, that later on hit in second-level TLB (STLB)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "ITLB_MISSES.WALK_ACTIVE", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b ) ) - ( c / ( b ) ) ) )", + "BaseFormula": "max( 0 , tma_itlb_misses - tma_code_stlb_miss )", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Code_STLB_Hit(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....ITLB_Misses(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 15", + "BaseFormula": "metric_TMA_......Code_STLB_Hit(%) > 5 & metric_TMA_....ITLB_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat;MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Code_STLB_Miss", + "LegacyName": "metric_TMA_......Code_STLB_Miss(%)", + "ParentCategory": "ITLB_Misses", + "Level": 4, + "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by instruction fetches, performing a hardware page walk", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "itlb_misses.walk_active / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Code_STLB_Miss(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....ITLB_Misses(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 15", + "BaseFormula": "metric_TMA_......Code_STLB_Miss(%) > 5 & metric_TMA_....ITLB_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat;MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Code_STLB_Miss_4K", + "LegacyName": "metric_TMA_........Code_STLB_Miss_4K(%)", + "ParentCategory": "Code_STLB_Miss", + "Level": 5, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 4 KB pages for (instruction) code accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "ITLB_MISSES.WALK_COMPLETED_4K", + "Alias": "c" + }, + { + "Name": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b ) ) * c / ( c + d ) )", + "BaseFormula": "tma_code_stlb_miss * itlb_misses.walk_completed_4k / ( itlb_misses.walk_completed_4k + itlb_misses.walk_completed_2m_4m )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Code_STLB_Miss_4K(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......Code_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....ITLB_Misses(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 5 & d > 10 & e > 15", + "BaseFormula": "metric_TMA_........Code_STLB_Miss_4K(%) > 5 & metric_TMA_......Code_STLB_Miss(%) > 5 & metric_TMA_....ITLB_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat;MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Code_STLB_Miss_2M", + "LegacyName": "metric_TMA_........Code_STLB_Miss_2M(%)", + "ParentCategory": "Code_STLB_Miss", + "Level": 5, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 2 or 4 MB pages for (instruction) code accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "c" + }, + { + "Name": "ITLB_MISSES.WALK_COMPLETED_4K", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b ) ) * c / ( d + c ) )", + "BaseFormula": "tma_code_stlb_miss * itlb_misses.walk_completed_2m_4m / ( itlb_misses.walk_completed_4k + itlb_misses.walk_completed_2m_4m )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Code_STLB_Miss_2M(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......Code_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....ITLB_Misses(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 5 & d > 10 & e > 15", + "BaseFormula": "metric_TMA_........Code_STLB_Miss_2M(%) > 5 & metric_TMA_......Code_STLB_Miss(%) > 5 & metric_TMA_....ITLB_Misses(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat;MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Branch_Resteers", + "LegacyName": "metric_TMA_....Branch_Resteers(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) + ( c / ( b ) ) )", + "BaseFormula": "int_misc.clear_resteer_cycles / tma_info_thread_clks + tma_unknown_branches", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Branch_Resteers(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....Branch_Resteers(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "~overlap" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat", + "LocateWith": "BR_MISP_RETIRED.ALL_BRANCHES" + }, + { + "MetricName": "Mispredicts_Resteers", + "LegacyName": "metric_TMA_......Mispredicts_Resteers(%)", + "ParentCategory": "Branch_Resteers", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) * h / ( i ) )", + "BaseFormula": "( tma_branch_mispredicts / tma_bad_speculation ) * int_misc.clear_resteer_cycles / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Mispredicts_Resteers(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Branch_Resteers(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 15", + "BaseFormula": "metric_TMA_......Mispredicts_Resteers(%) > 5 & metric_TMA_....Branch_Resteers(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "$issueBM" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP", + "LocateWith": "INT_MISC.CLEAR_RESTEER_CYCLES" + }, + { + "MetricName": "Clears_Resteers", + "LegacyName": "metric_TMA_......Clears_Resteers(%)", + "ParentCategory": "Branch_Resteers", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + } + ], + "Constants": [], + "Formula": "100 * ( ( 1 - ( ( a / ( b + c + d + e ) ) / ( max( 1 - ( ( b / ( b + c + d + e ) - f / ( g ) ) + ( e / ( b + c + d + e ) ) + ( d / ( b + c + d + e ) ) ) , 0 ) ) ) ) * h / ( i ) )", + "BaseFormula": "( 1 - ( tma_branch_mispredicts / tma_bad_speculation ) ) * int_misc.clear_resteer_cycles / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Clears_Resteers(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Branch_Resteers(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 15", + "BaseFormula": "metric_TMA_......Clears_Resteers(%) > 5 & metric_TMA_....Branch_Resteers(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "$issueMC" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;MachineClears", + "LocateWith": "INT_MISC.CLEAR_RESTEER_CYCLES" + }, + { + "MetricName": "Unknown_Branches", + "LegacyName": "metric_TMA_......Unknown_Branches(%)", + "ParentCategory": "Branch_Resteers", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit) hence called Unknown Branches", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "int_misc.unknown_branch_cycles / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Unknown_Branches(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Branch_Resteers(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 15", + "BaseFormula": "metric_TMA_......Unknown_Branches(%) > 5 & metric_TMA_....Branch_Resteers(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BigFootprint;BvBC;FetchLat", + "LocateWith": "FRONTEND_RETIRED.UNKNOWN_BRANCH" + }, + { + "MetricName": "MS_Switches", + "LegacyName": "metric_TMA_....MS_Switches(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "a" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "b" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( 3 ) * a / ( b / c ) / ( d ) )", + "BaseFormula": "( 3 ) * uops_retired.ms:c1:e1 / ( uops_retired.slots / uops_issued.any ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....MS_Switches(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....MS_Switches(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "$issueMC, $issueMS, $issueMV, $issueSO" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat;MicroSeq", + "LocateWith": "FRONTEND_RETIRED.MS_FLOWS" + }, + { + "MetricName": "LCP", + "LegacyName": "metric_TMA_....LCP(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DECODE.LCP", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "decode.lcp / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....LCP(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....LCP(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchLat", + "LocateWith": "" + }, + { + "MetricName": "DSB_Switches", + "LegacyName": "metric_TMA_....DSB_Switches(%)", + "ParentCategory": "Fetch_Latency", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "dsb2mite_switches.penalty_cycles / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....DSB_Switches(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....DSB_Switches(%) > 5 & metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;FetchLat", + "LocateWith": "FRONTEND_RETIRED.DSB_MISS" + }, + { + "MetricName": "Fetch_Bandwidth", + "LegacyName": "metric_TMA_..Fetch_Bandwidth(%)", + "ParentCategory": "Frontend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( a + b + c + d ) - e / ( f ) ) - ( ( g / ( a + b + c + d ) - e / ( f ) ) ) ) )", + "BaseFormula": "max( 0 , tma_frontend_bound - tma_fetch_latency )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Fetch_Bandwidth(%)" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_..Fetch_Bandwidth(%) > 20", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchBW;Frontend;TmaL2", + "LocateWith": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1;FRONTEND_RETIRED.LATENCY_GE_1;FRONTEND_RETIRED.LATENCY_GE_2" + }, + { + "MetricName": "MITE", + "LegacyName": "metric_TMA_....MITE(%)", + "ParentCategory": "Fetch_Bandwidth", + "Level": 3, + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.MITE_CYCLES_ANY", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_CYCLES_OK", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a - b ) / ( c if smt_on else ( d ) ) / 2 )", + "BaseFormula": "( idq.mite_cycles_any - idq.mite_cycles_ok ) / tma_info_core_core_clks / 2", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....MITE(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Bandwidth(%)" + } + ], + "Formula": "a > 10 & b > 20", + "BaseFormula": "metric_TMA_....MITE(%) > 10 & metric_TMA_..Fetch_Bandwidth(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;FetchBW", + "LocateWith": "FRONTEND_RETIRED.ANY_DSB_MISS" + }, + { + "MetricName": "Decoder0_Alone", + "LegacyName": "metric_TMA_......Decoder0_Alone(%)", + "ParentCategory": "MITE", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INST_DECODED.DECODERS:c1", + "Alias": "a" + }, + { + "Name": "INST_DECODED.DECODERS:c2", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a - b ) / ( c if smt_on else ( d ) ) / 2 )", + "BaseFormula": "( inst_decoded.decoders:c1 - inst_decoded.decoders:c2 ) / tma_info_core_core_clks / 2", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Decoder0_Alone(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....MITE(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Fetch_Bandwidth(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20", + "BaseFormula": "metric_TMA_......Decoder0_Alone(%) > 10 & metric_TMA_....MITE(%) > 10 & metric_TMA_..Fetch_Bandwidth(%) > 20", + "ThresholdIssues": "$issueD0" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "DSB", + "LegacyName": "metric_TMA_....DSB(%)", + "ParentCategory": "Fetch_Bandwidth", + "Level": 3, + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.DSB_CYCLES_ANY", + "Alias": "a" + }, + { + "Name": "IDQ.DSB_CYCLES_OK", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a - b ) / ( c if smt_on else ( d ) ) / 2 )", + "BaseFormula": "( idq.dsb_cycles_any - idq.dsb_cycles_ok ) / tma_info_core_core_clks / 2", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....DSB(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Bandwidth(%)" + } + ], + "Formula": "a > 15 & b > 20", + "BaseFormula": "metric_TMA_....DSB(%) > 15 & metric_TMA_..Fetch_Bandwidth(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSB;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "MS", + "LegacyName": "metric_TMA_....MS(%)", + "ParentCategory": "Fetch_Bandwidth", + "Level": 3, + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the Microcode Sequencer (MS) unit - see Microcode_Sequencer node for details.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ.MS_CYCLES_ANY", + "Alias": "a" + }, + { + "Name": "UOPS_RETIRED.MS:c1", + "Alias": "b" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "c" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "e" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "f" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( max( a , b / ( c / d ) ) / ( e if smt_on else ( f ) ) / 2.4 )", + "BaseFormula": "max( idq.ms_cycles_any , uops_retired.ms:c1 / ( uops_retired.slots / uops_issued.any ) ) / tma_info_core_core_clks / 2.4", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....MS(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Fetch_Bandwidth(%)" + } + ], + "Formula": "a > 5 & b > 20", + "BaseFormula": "metric_TMA_....MS(%) > 5 & metric_TMA_..Fetch_Bandwidth(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq", + "LocateWith": "" + }, + { + "MetricName": "Bad_Speculation", + "LegacyName": "metric_TMA_Bad_Speculation(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) )", + "BaseFormula": "max( 1 - ( tma_frontend_bound + tma_backend_bound + tma_retiring ) , 0 )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 15", + "BaseFormula": "metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "TmaL1", + "LocateWith": "#NA" + }, + { + "MetricName": "Branch_Mispredicts", + "LegacyName": "metric_TMA_..Branch_Mispredicts(%)", + "ParentCategory": "Bad_Speculation", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b + c + d + e ) )", + "BaseFormula": "perf_metrics.branch_mispredicts / ( perf_metrics.frontend_bound + perf_metrics.bad_speculation + perf_metrics.retiring + perf_metrics.backend_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Branch_Mispredicts(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 10 & b > 15", + "BaseFormula": "metric_TMA_..Branch_Mispredicts(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "$issueBM" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2", + "LocateWith": "TOPDOWN.BR_MISPREDICT_SLOTS" + }, + { + "MetricName": "Other_Mispredicts", + "LegacyName": "metric_TMA_....Other_Mispredicts(%)", + "ParentCategory": "Branch_Mispredicts", + "Level": 3, + "BriefDescription": "This metric estimates fraction of slots the CPU was stalled due to other cases of misprediction (non-retired x86 branches or other types).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "f" + }, + { + "Name": "INT_MISC.CLEARS_COUNT", + "Alias": "g" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( max( ( a / ( b + c + d + e ) ) * ( 1 - f / ( g - h ) ) , 0.0001 ) )", + "BaseFormula": "max( tma_branch_mispredicts * ( 1 - br_misp_retired.all_branches / ( int_misc.clears_count - machine_clears.count ) ) , 0.0001 )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Other_Mispredicts(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Branch_Mispredicts(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....Other_Mispredicts(%) > 5 & metric_TMA_..Branch_Mispredicts(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvIO;BrMispredicts", + "LocateWith": "" + }, + { + "MetricName": "Machine_Clears", + "LegacyName": "metric_TMA_..Machine_Clears(%)", + "ParentCategory": "Bad_Speculation", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) - ( g / ( a + b + c + d ) ) ) )", + "BaseFormula": "max( 0 , tma_bad_speculation - tma_branch_mispredicts )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Machine_Clears(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 10 & b > 15", + "BaseFormula": "metric_TMA_..Machine_Clears(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "$issueMC, $issueSyncxn" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2", + "LocateWith": "MACHINE_CLEARS.COUNT" + }, + { + "MetricName": "Other_Nukes", + "LegacyName": "metric_TMA_....Other_Nukes(%)", + "ParentCategory": "Machine_Clears", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Nukes (Machine Clears) not related to memory ordering.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BRANCH_MISPREDICTS", + "Alias": "g" + }, + { + "Name": "MACHINE_CLEARS.MEMORY_ORDERING", + "Alias": "h" + }, + { + "Name": "MACHINE_CLEARS.COUNT", + "Alias": "i" + } + ], + "Constants": [], + "Formula": "100 * ( max( ( max( 0 , ( max( 1 - ( ( a / ( a + b + c + d ) - e / ( f ) ) + ( d / ( a + b + c + d ) ) + ( c / ( a + b + c + d ) ) ) , 0 ) ) - ( g / ( a + b + c + d ) ) ) ) * ( 1 - h / i ) , 0.0001 ) )", + "BaseFormula": "max( tma_machine_clears * ( 1 - machine_clears.memory_ordering / machine_clears.count ) , 0.0001 )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Other_Nukes(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Machine_Clears(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 15", + "BaseFormula": "metric_TMA_....Other_Nukes(%) > 5 & metric_TMA_..Machine_Clears(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvIO;Machine_Clears", + "LocateWith": "" + }, + { + "MetricName": "Backend_Bound", + "LegacyName": "metric_TMA_Backend_Bound(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b + c + d + a ) )", + "BaseFormula": "perf_metrics.backend_bound / ( perf_metrics.frontend_bound + perf_metrics.bad_speculation + perf_metrics.retiring + perf_metrics.backend_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvOB;TmaL1", + "LocateWith": "TOPDOWN.BACKEND_BOUND_SLOTS" + }, + { + "MetricName": "Memory_Bound", + "LegacyName": "metric_TMA_..Memory_Bound(%)", + "ParentCategory": "Backend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b + c + d + e ) )", + "BaseFormula": "perf_metrics.memory_bound / ( perf_metrics.frontend_bound + perf_metrics.bad_speculation + perf_metrics.retiring + perf_metrics.backend_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20", + "BaseFormula": "metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Backend;TmaL2", + "LocateWith": "#NA" + }, + { + "MetricName": "L1_Bound", + "LegacyName": "metric_TMA_....L1_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 Data (L1D) cache. The L1D cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1D. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "a" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( max( ( a - b ) / ( c ) , 0 ) )", + "BaseFormula": "max( ( exe_activity.bound_on_loads - memory_activity.stalls_l1d_miss ) / tma_info_thread_clks , 0 )", + "Category": "TMA", + "CountDomain": "Stalls", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 20", + "BaseFormula": "metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueL1, $issueMC" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem", + "LocateWith": "MEM_LOAD_RETIRED.L1_HIT" + }, + { + "MetricName": "DTLB_Load", + "LegacyName": "metric_TMA_......DTLB_Load(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", + "Alias": "a" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "b" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "c" + }, + { + "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( min( ( 7 ) * a + b , max( c - d , 0 ) ) / ( e ) )", + "BaseFormula": "min( ( 7 ) * dtlb_load_misses.stlb_hit:c1 + dtlb_load_misses.walk_active , max( cycle_activity.cycles_mem_any - memory_activity.cycles_l1d_miss , 0 ) ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......DTLB_Load(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......DTLB_Load(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueTLB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMT;MemoryTLB", + "LocateWith": "MEM_INST_RETIRED.STLB_MISS_LOADS" + }, + { + "MetricName": "Load_STLB_Hit", + "LegacyName": "metric_TMA_........Load_STLB_Hit(%)", + "ParentCategory": "DTLB_Load", + "Level": 5, + "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.STLB_HIT:c1", + "Alias": "a" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "b" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "c" + }, + { + "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( ( min( ( 7 ) * a + b , max( c - d , 0 ) ) / ( e ) ) - ( b / ( e ) ) )", + "BaseFormula": "tma_dtlb_load - tma_load_stlb_miss", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Load_STLB_Hit(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......DTLB_Load(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 10 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........Load_STLB_Hit(%) > 5 & metric_TMA_......DTLB_Load(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Load_STLB_Miss", + "LegacyName": "metric_TMA_........Load_STLB_Miss(%)", + "ParentCategory": "DTLB_Load", + "Level": 5, + "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "dtlb_load_misses.walk_active / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Calculated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Load_STLB_Miss(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......DTLB_Load(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 10 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........Load_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Load(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Load_STLB_Miss_4K", + "LegacyName": "metric_TMA_..........Load_STLB_Miss_4K(%)", + "ParentCategory": "Load_STLB_Miss", + "Level": 6, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 4 KB pages for data load accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "Alias": "c" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "d" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b ) ) * c / ( c + d + e ) )", + "BaseFormula": "tma_load_stlb_miss * dtlb_load_misses.walk_completed_4k / ( dtlb_load_misses.walk_completed_4k + dtlb_load_misses.walk_completed_2m_4m + dtlb_load_misses.walk_completed_1g )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Load_STLB_Miss_4K(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_........Load_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_......DTLB_Load(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "f", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 10 & e > 20 & f > 20", + "BaseFormula": "metric_TMA_..........Load_STLB_Miss_4K(%) > 5 & metric_TMA_........Load_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Load(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Load_STLB_Miss_2M", + "LegacyName": "metric_TMA_..........Load_STLB_Miss_2M(%)", + "ParentCategory": "Load_STLB_Miss", + "Level": 6, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 2 or 4 MB pages for data load accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "c" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "Alias": "d" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b ) ) * c / ( d + c + e ) )", + "BaseFormula": "tma_load_stlb_miss * dtlb_load_misses.walk_completed_2m_4m / ( dtlb_load_misses.walk_completed_4k + dtlb_load_misses.walk_completed_2m_4m + dtlb_load_misses.walk_completed_1g )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Load_STLB_Miss_2M(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_........Load_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_......DTLB_Load(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "f", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 10 & e > 20 & f > 20", + "BaseFormula": "metric_TMA_..........Load_STLB_Miss_2M(%) > 5 & metric_TMA_........Load_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Load(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Load_STLB_Miss_1G", + "LegacyName": "metric_TMA_..........Load_STLB_Miss_1G(%)", + "ParentCategory": "Load_STLB_Miss", + "Level": 6, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 1 GB pages for data load accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "Alias": "c" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "Alias": "d" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b ) ) * c / ( d + e + c ) )", + "BaseFormula": "tma_load_stlb_miss * dtlb_load_misses.walk_completed_1g / ( dtlb_load_misses.walk_completed_4k + dtlb_load_misses.walk_completed_2m_4m + dtlb_load_misses.walk_completed_1g )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Load_STLB_Miss_1G(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_........Load_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_......DTLB_Load(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "f", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 10 & d > 10 & e > 20 & f > 20", + "BaseFormula": "metric_TMA_..........Load_STLB_Miss_1G(%) > 5 & metric_TMA_........Load_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Load(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Store_Fwd_Blk", + "LegacyName": "metric_TMA_......Store_Fwd_Blk(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "LD_BLOCKS.STORE_FORWARD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 13 * a / ( b ) )", + "BaseFormula": "13 * ld_blocks.store_forward / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Store_Fwd_Blk(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Store_Fwd_Blk(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "L1_Latency_Dependency", + "LegacyName": "metric_TMA_......L1_Latency_Dependency(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric ([SKL+] roughly; [LNL]) estimates fraction of cycles with demand load accesses that hit the L1D cache. The short latency of the L1D cache may be exposed in pointer-chasing memory access patterns as an example.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_INST_RETIRED.ALL_LOADS", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "c" + }, + { + "Name": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "Alias": "e" + }, + { + "Name": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "Alias": "f" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "g" + } + ], + "Constants": [ + { + "Name": "20", + "Alias": "dependentloadsweight" + } + ], + "Formula": "100 * ( min( 2 * ( a - b - c ) * dependentloadsweight / 100 , max( e - f , 0 ) ) / ( g ) )", + "BaseFormula": "min( 2 * ( mem_inst_retired.all_loads - mem_load_retired.fb_hit - mem_load_retired.l1_miss ) * 20 / 100 , max( cycle_activity.cycles_mem_any - memory_activity.cycles_l1d_miss , 0 ) ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......L1_Latency_Dependency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......L1_Latency_Dependency(%) > 10 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvML;MemoryLat", + "LocateWith": "MEM_LOAD_RETIRED.L1_HIT" + }, + { + "MetricName": "Lock_Latency", + "LegacyName": "metric_TMA_......Lock_Latency(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a" + }, + { + "Name": "L2_RQSTS.ALL_RFO", + "Alias": "b" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "c" + }, + { + "Name": "L2_RQSTS.RFO_HIT", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "e" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( ( 16 * max( 0 , a - b ) + ( a / c ) * ( ( 10 ) * d + ( min( e , f ) ) ) ) / ( e ) )", + "BaseFormula": "( 16 * max( 0 , mem_inst_retired.lock_loads - l2_rqsts.all_rfo ) + ( mem_inst_retired.lock_loads / mem_inst_retired.all_stores ) * ( ( 10 ) * l2_rqsts.rfo_hit + ( min( cpu_clk_unhalted.thread , offcore_requests_outstanding.cycles_with_demand_rfo ) ) ) ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Lock_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L1_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Lock_Latency(%) > 20 & metric_TMA_....L1_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueRFO" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "LockCont;Offcore", + "LocateWith": "MEM_INST_RETIRED.LOCK_LOADS" + }, + { + "MetricName": "Split_Loads", + "LegacyName": "metric_TMA_......Split_Loads(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "L1D_PEND_MISS.PENDING", + "Alias": "a" + }, + { + "Name": "MEM_LOAD_COMPLETED.L1_MISS_ANY", + "Alias": "b" + }, + { + "Name": "LD_BLOCKS.NO_SR", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / b ) * c / ( d ) )", + "BaseFormula": "tma_info_memory_load_miss_real_latency * ld_blocks.no_sr / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Calculated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Split_Loads(%)" + } + ], + "Formula": "a > 30", + "BaseFormula": "metric_TMA_......Split_Loads(%) > 30", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "MEM_INST_RETIRED.SPLIT_LOADS" + }, + { + "MetricName": "FB_Full", + "LegacyName": "metric_TMA_......FB_Full(%)", + "ParentCategory": "L1_Bound", + "Level": 4, + "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "L1D_PEND_MISS.FB_FULL", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "l1d_pend_miss.fb_full / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Calculated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......FB_Full(%)" + } + ], + "Formula": "a > 30", + "BaseFormula": "metric_TMA_......FB_Full(%) > 30", + "ThresholdIssues": "$issueBW, $issueSL, $issueSmSt" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMB;MemoryBW", + "LocateWith": "" + }, + { + "MetricName": "L2_Bound", + "LegacyName": "metric_TMA_....L2_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "Alias": "a" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a - b ) / ( c ) )", + "BaseFormula": "( memory_activity.stalls_l1d_miss - memory_activity.stalls_l2_miss ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Stalls", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....L2_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 20 & c > 20", + "BaseFormula": "metric_TMA_....L2_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvML;CacheHits;MemoryBound;TmaL3mem", + "LocateWith": "MEM_LOAD_RETIRED.L2_HIT" + }, + { + "MetricName": "L2_Hit_Latency", + "LegacyName": "metric_TMA_......L2_Hit_Latency(%)", + "ParentCategory": "L2_Bound", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L2 cache under unloaded scenarios (possibly L2 latency limited). Avoiding L1 cache misses (i.e. L1 misses/L2 hits) will improve the latency.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_RETIRED.L2_HIT", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "f" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "g" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( ( 4.4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) )", + "BaseFormula": "( 4.4 * tma_info_system_core_frequency ) * mem_load_retired.l2_hit * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) / 2 ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Retired", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......L2_Hit_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L2_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......L2_Hit_Latency(%) > 5 & metric_TMA_....L2_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryLat", + "LocateWith": "MEM_LOAD_RETIRED.L2_HIT" + }, + { + "MetricName": "L3_Bound", + "LegacyName": "metric_TMA_....L3_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "Alias": "a" + }, + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a - b ) / ( c ) )", + "BaseFormula": "( memory_activity.stalls_l2_miss - memory_activity.stalls_l3_miss ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Stalls", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....L3_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 20 & c > 20", + "BaseFormula": "metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem", + "LocateWith": "MEM_LOAD_RETIRED.L3_HIT" + }, + { + "MetricName": "Contested_Accesses", + "LegacyName": "metric_TMA_......Contested_Accesses(%)", + "ParentCategory": "L3_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Alias": "e" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "f" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "g" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "Alias": "h" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "i" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "j" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( ( ( ( 81 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( e * ( f / ( f + g ) ) ) + ( ( 79 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( h ) ) * ( 1 + ( i / j ) / 2 ) / ( a ) )", + "BaseFormula": "( ( ( 81 * tma_info_system_core_frequency ) - ( 4.4 * tma_info_system_core_frequency ) ) * ( mem_load_l3_hit_retired.xsnp_fwd * ( ocr.demand_data_rd.l3_hit.snoop_hitm / ( ocr.demand_data_rd.l3_hit.snoop_hitm + ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd ) ) ) + ( ( 79 * tma_info_system_core_frequency ) - ( 4.4 * tma_info_system_core_frequency ) ) * ( mem_load_l3_hit_retired.xsnp_miss ) ) * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) / 2 ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Contested_Accesses(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L3_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Contested_Accesses(%) > 5 & metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSyncxn" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMS;DataSharing;LockCont;Offcore;Snoop", + "LocateWith": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS" + }, + { + "MetricName": "Data_Sharing", + "LegacyName": "metric_TMA_......Data_Sharing(%)", + "ParentCategory": "L3_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Alias": "f" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "Alias": "g" + }, + { + "Name": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Alias": "h" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "i" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "j" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( ( ( 79 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( e + f * ( 1 - ( g / ( g + h ) ) ) ) * ( 1 + ( i / j ) / 2 ) / ( a ) )", + "BaseFormula": "( ( 79 * tma_info_system_core_frequency ) - ( 4.4 * tma_info_system_core_frequency ) ) * ( mem_load_l3_hit_retired.xsnp_no_fwd + mem_load_l3_hit_retired.xsnp_fwd * ( 1 - ( ocr.demand_data_rd.l3_hit.snoop_hitm / ( ocr.demand_data_rd.l3_hit.snoop_hitm + ocr.demand_data_rd.l3_hit.snoop_hit_with_fwd ) ) ) ) * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) / 2 ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Data_Sharing(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L3_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Data_Sharing(%) > 5 & metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSyncxn" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMS;Offcore;Snoop", + "LocateWith": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD" + }, + { + "MetricName": "L3_Hit_Latency", + "LegacyName": "metric_TMA_......L3_Hit_Latency(%)", + "ParentCategory": "L3_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_RETIRED.L3_HIT", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "f" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "g" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( ( ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 4.4 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * ( e * ( 1 + ( f / g ) / 2 ) ) / ( a ) )", + "BaseFormula": "( ( 37 * tma_info_system_core_frequency ) - ( 4.4 * tma_info_system_core_frequency ) ) * ( mem_load_retired.l3_hit * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) / 2 ) ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......L3_Hit_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L3_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 5 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......L3_Hit_Latency(%) > 10 & metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueLat, ~overlap" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvML;MemoryLat", + "LocateWith": "MEM_LOAD_RETIRED.L3_HIT" + }, + { + "MetricName": "SQ_Full", + "LegacyName": "metric_TMA_......SQ_Full(%)", + "ParentCategory": "L3_Bound", + "Level": 4, + "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "XQ.FULL_CYCLES", + "Alias": "a" + }, + { + "Name": "L1D_PEND_MISS.L2_STALLS", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b ) / ( c ) )", + "BaseFormula": "( xq.full_cycles + l1d_pend_miss.l2_stalls ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......SQ_Full(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....L3_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 30 & b > 5 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......SQ_Full(%) > 30 & metric_TMA_....L3_Bound(%) > 5 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueBW" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMB;MemoryBW;Offcore", + "LocateWith": "" + }, + { + "MetricName": "DRAM_Bound", + "LegacyName": "metric_TMA_....DRAM_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b ) ) )", + "BaseFormula": "( memory_activity.stalls_l3_miss / tma_info_thread_clks )", + "Category": "TMA", + "CountDomain": "Stalls", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 20", + "BaseFormula": "metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBound;TmaL3mem", + "LocateWith": "MEM_LOAD_RETIRED.L3_MISS" + }, + { + "MetricName": "MEM_Bandwidth", + "LegacyName": "metric_TMA_......MEM_Bandwidth(%)", + "ParentCategory": "DRAM_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( ( min( a , b ) ) / ( a ) )", + "BaseFormula": "( min( cpu_clk_unhalted.thread , offcore_requests_outstanding.all_data_rd:c4 ) ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......MEM_Bandwidth(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......MEM_Bandwidth(%) > 20 & metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueBW" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMB;MemoryBW;Offcore", + "LocateWith": "" + }, + { + "MetricName": "MBA_Stalls", + "LegacyName": "metric_TMA_........MBA_Stalls(%)", + "ParentCategory": "MEM_Bandwidth", + "Level": 5, + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to memory bandwidth Allocation feature (RDT's memory bandwidth throttling).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_MISC.MBA_STALLS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "int_misc.mba_stalls / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........MBA_Stalls(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......MEM_Bandwidth(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 10 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........MBA_Stalls(%) > 10 & metric_TMA_......MEM_Bandwidth(%) > 20 & metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBW;Offcore;Server", + "LocateWith": "" + }, + { + "MetricName": "MEM_Latency", + "LegacyName": "metric_TMA_......MEM_Latency(%)", + "ParentCategory": "DRAM_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory - DRAM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "b" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( min( a , b ) ) / ( a ) - ( ( min( a , c ) ) / ( a ) ) )", + "BaseFormula": "( min( cpu_clk_unhalted.thread , offcore_requests_outstanding.cycles_with_data_rd ) ) / tma_info_thread_clks - tma_mem_bandwidth", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......MEM_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......MEM_Latency(%) > 10 & metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueLat" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvML;MemoryLat;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Local_MEM", + "LegacyName": "metric_TMA_........Local_MEM(%)", + "ParentCategory": "MEM_Latency", + "Level": 5, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "f" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "g" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( ( ( 109 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) )", + "BaseFormula": "( ( 109 * tma_info_system_core_frequency ) - ( 37 * tma_info_system_core_frequency ) ) * mem_load_l3_miss_retired.local_dram * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) / 2 ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Local_MEM(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......MEM_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 10 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........Local_MEM(%) > 10 & metric_TMA_......MEM_Latency(%) > 10 & metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Server", + "LocateWith": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM" + }, + { + "MetricName": "Remote_MEM", + "LegacyName": "metric_TMA_........Remote_MEM(%)", + "ParentCategory": "MEM_Latency", + "Level": 5, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "f" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "g" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( ( ( 190 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * e * ( 1 + ( f / g ) / 2 ) / ( a ) )", + "BaseFormula": "( ( 190 * tma_info_system_core_frequency ) - ( 37 * tma_info_system_core_frequency ) ) * mem_load_l3_miss_retired.remote_dram * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) / 2 ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Remote_MEM(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......MEM_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 10 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........Remote_MEM(%) > 10 & metric_TMA_......MEM_Latency(%) > 10 & metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Server;Snoop", + "LocateWith": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM" + }, + { + "MetricName": "Remote_Cache", + "LegacyName": "metric_TMA_........Remote_Cache(%)", + "ParentCategory": "MEM_Latency", + "Level": 5, + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Alias": "e" + }, + { + "Name": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "Alias": "f" + }, + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "g" + }, + { + "Name": "MEM_LOAD_RETIRED.L1_MISS", + "Alias": "h" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( ( ( ( 170 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * e + ( ( 170 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) - ( 37 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) ) * f ) * ( 1 + ( g / h ) / 2 ) / ( a ) )", + "BaseFormula": "( ( ( 170 * tma_info_system_core_frequency ) - ( 37 * tma_info_system_core_frequency ) ) * mem_load_l3_miss_retired.remote_hitm + ( ( 170 * tma_info_system_core_frequency ) - ( 37 * tma_info_system_core_frequency ) ) * mem_load_l3_miss_retired.remote_fwd ) * ( 1 + ( mem_load_retired.fb_hit / mem_load_retired.l1_miss ) / 2 ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Remote_Cache(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......MEM_Latency(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....DRAM_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 10 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........Remote_Cache(%) > 5 & metric_TMA_......MEM_Latency(%) > 10 & metric_TMA_....DRAM_Bound(%) > 10 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSyncxn" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Offcore;Server;Snoop", + "LocateWith": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD" + }, + { + "MetricName": "Store_Bound", + "LegacyName": "metric_TMA_....Store_Bound(%)", + "ParentCategory": "Memory_Bound", + "Level": 3, + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.BOUND_ON_STORES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "exe_activity.bound_on_stores / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Stalls", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20 & c > 20", + "BaseFormula": "metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBound;TmaL3mem", + "LocateWith": "MEM_INST_RETIRED.ALL_STORES" + }, + { + "MetricName": "Store_Latency", + "LegacyName": "metric_TMA_......Store_Latency(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_STORE_RETIRED.L2_HIT", + "Alias": "a" + }, + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "b" + }, + { + "Name": "MEM_INST_RETIRED.ALL_STORES", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a * ( 10 ) * ( 1 - ( b / c ) ) ) + ( 1 - ( b / c ) ) * ( min( d , e ) ) ) / ( d ) )", + "BaseFormula": "( ( mem_store_retired.l2_hit * ( 10 ) * ( 1 - ( mem_inst_retired.lock_loads / mem_inst_retired.all_stores ) ) ) + ( 1 - ( mem_inst_retired.lock_loads / mem_inst_retired.all_stores ) ) * ( min( cpu_clk_unhalted.thread , offcore_requests_outstanding.cycles_with_demand_rfo ) ) ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Store_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Store_Latency(%) > 10 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueRFO, $issueSL, ~overlap" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvML;LockCont;MemoryLat;Offcore", + "LocateWith": "" + }, + { + "MetricName": "False_Sharing", + "LegacyName": "metric_TMA_......False_Sharing(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + }, + { + "Name": "OCR.DEMAND_RFO.L3_MISS:ocr_msr_val=0x103b800002", + "Alias": "e" + }, + { + "Name": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "Alias": "f" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "100 * ( ( ( 170 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * e + ( 81 * ( ( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) ) ) * f ) / ( a ) )", + "BaseFormula": "( ( 170 * tma_info_system_core_frequency ) * ocr.demand_rfo.l3_miss:ocr_msr_val=0x103b800002 + ( 81 * tma_info_system_core_frequency ) * ocr.demand_rfo.l3_hit.snoop_hitm ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......False_Sharing(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 20 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......False_Sharing(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSyncxn" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMS;DataSharing;LockCont;Offcore;Snoop", + "LocateWith": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM" + }, + { + "MetricName": "Split_Stores", + "LegacyName": "metric_TMA_......Split_Stores(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_INST_RETIRED.SPLIT_STORES", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( a / ( b if smt_on else ( c ) ) )", + "BaseFormula": "mem_inst_retired.split_stores / tma_info_core_core_clks", + "Category": "TMA", + "CountDomain": "Core_Utilization", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Split_Stores(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Split_Stores(%) > 20 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSpSt" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "MEM_INST_RETIRED.SPLIT_STORES" + }, + { + "MetricName": "Streaming_Stores", + "LegacyName": "metric_TMA_......Streaming_Stores(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "OCR.STREAMING_WR.ANY_RESPONSE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 9 * a / ( b ) )", + "BaseFormula": "9 * ocr.streaming_wr.any_response / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Streaming_Stores(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......Streaming_Stores(%) > 20 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSmSt" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryBW;Offcore", + "LocateWith": "OCR.STREAMING_WR.ANY_RESPONSE" + }, + { + "MetricName": "DTLB_Store", + "LegacyName": "metric_TMA_......DTLB_Store(%)", + "ParentCategory": "Store_Bound", + "Level": 4, + "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", + "Alias": "a" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( ( 7 ) * a + b ) / ( c if smt_on else ( d ) ) )", + "BaseFormula": "( ( 7 ) * dtlb_store_misses.stlb_hit:c1 + dtlb_store_misses.walk_active ) / tma_info_core_core_clks", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......DTLB_Store(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 20 & c > 20 & d > 20", + "BaseFormula": "metric_TMA_......DTLB_Store(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueTLB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvMT;MemoryTLB", + "LocateWith": "MEM_INST_RETIRED.STLB_MISS_STORES" + }, + { + "MetricName": "Store_STLB_Hit", + "LegacyName": "metric_TMA_........Store_STLB_Hit(%)", + "ParentCategory": "DTLB_Store", + "Level": 5, + "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.STLB_HIT:c1", + "Alias": "a" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( ( ( 7 ) * a + b ) / ( c if smt_on else ( d ) ) ) - ( b / ( c if smt_on else ( d ) ) ) )", + "BaseFormula": "tma_dtlb_store - tma_store_stlb_miss", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Store_STLB_Hit(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......DTLB_Store(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 20 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........Store_STLB_Hit(%) > 5 & metric_TMA_......DTLB_Store(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Store_STLB_Miss", + "LegacyName": "metric_TMA_........Store_STLB_Miss(%)", + "ParentCategory": "DTLB_Store", + "Level": 5, + "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( a / ( b if smt_on else ( c ) ) )", + "BaseFormula": "dtlb_store_misses.walk_active / tma_info_core_core_clks", + "Category": "TMA", + "CountDomain": "Clocks_Calculated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Store_STLB_Miss(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......DTLB_Store(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 20 & d > 20 & e > 20", + "BaseFormula": "metric_TMA_........Store_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Store(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Store_STLB_Miss_4K", + "LegacyName": "metric_TMA_..........Store_STLB_Miss_4K(%)", + "ParentCategory": "Store_STLB_Miss", + "Level": 6, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 4 KB pages for data store accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "Alias": "d" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "e" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "Alias": "f" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a / ( b if smt_on else ( c ) ) ) * d / ( d + e + f ) )", + "BaseFormula": "tma_store_stlb_miss * dtlb_store_misses.walk_completed_4k / ( dtlb_store_misses.walk_completed_4k + dtlb_store_misses.walk_completed_2m_4m + dtlb_store_misses.walk_completed_1g )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Store_STLB_Miss_4K(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_........Store_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_......DTLB_Store(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "f", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 5 & d > 20 & e > 20 & f > 20", + "BaseFormula": "metric_TMA_..........Store_STLB_Miss_4K(%) > 5 & metric_TMA_........Store_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Store(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Store_STLB_Miss_2M", + "LegacyName": "metric_TMA_..........Store_STLB_Miss_2M(%)", + "ParentCategory": "Store_STLB_Miss", + "Level": 6, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 2 or 4 MB pages for data store accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "d" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "Alias": "e" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "Alias": "f" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a / ( b if smt_on else ( c ) ) ) * d / ( e + d + f ) )", + "BaseFormula": "tma_store_stlb_miss * dtlb_store_misses.walk_completed_2m_4m / ( dtlb_store_misses.walk_completed_4k + dtlb_store_misses.walk_completed_2m_4m + dtlb_store_misses.walk_completed_1g )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Store_STLB_Miss_2M(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_........Store_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_......DTLB_Store(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "f", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 5 & d > 20 & e > 20 & f > 20", + "BaseFormula": "metric_TMA_..........Store_STLB_Miss_2M(%) > 5 & metric_TMA_........Store_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Store(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Store_STLB_Miss_1G", + "LegacyName": "metric_TMA_..........Store_STLB_Miss_1G(%)", + "ParentCategory": "Store_STLB_Miss", + "Level": 6, + "BriefDescription": "This metric estimates the fraction of cycles to walk the memory paging structures to cache translation of 1 GB pages for data store accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "Alias": "d" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "Alias": "e" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "f" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a / ( b if smt_on else ( c ) ) ) * d / ( e + f + d ) )", + "BaseFormula": "tma_store_stlb_miss * dtlb_store_misses.walk_completed_1g / ( dtlb_store_misses.walk_completed_4k + dtlb_store_misses.walk_completed_2m_4m + dtlb_store_misses.walk_completed_1g )", + "Category": "TMA", + "CountDomain": "Clocks_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Store_STLB_Miss_1G(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_........Store_STLB_Miss(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_......DTLB_Store(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_....Store_Bound(%)" + }, + { + "Alias": "e", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "f", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 5 & c > 5 & d > 20 & e > 20 & f > 20", + "BaseFormula": "metric_TMA_..........Store_STLB_Miss_1G(%) > 5 & metric_TMA_........Store_STLB_Miss(%) > 5 & metric_TMA_......DTLB_Store(%) > 5 & metric_TMA_....Store_Bound(%) > 20 & metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Core_Bound", + "LegacyName": "metric_TMA_..Core_Bound(%)", + "ParentCategory": "Backend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) )", + "BaseFormula": "max( 0 , tma_backend_bound - tma_memory_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 20", + "BaseFormula": "metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Backend;TmaL2;Compute", + "LocateWith": "" + }, + { + "MetricName": "Divider", + "LegacyName": "metric_TMA_....Divider(%)", + "ParentCategory": "Core_Bound", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "arith.div_active / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Divider(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 10 & c > 20", + "BaseFormula": "metric_TMA_....Divider(%) > 20 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvCB", + "LocateWith": "ARITH.DIVIDER_ACTIVE" + }, + { + "MetricName": "FP_Divider", + "LegacyName": "metric_TMA_......FP_Divider(%)", + "ParentCategory": "Divider", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles where the Floating-Point Divider unit was active.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ARITH.FPDIV_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "arith.fpdiv_active / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......FP_Divider(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Divider(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......FP_Divider(%) > 20 & metric_TMA_....Divider(%) > 20 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "INT_Divider", + "LegacyName": "metric_TMA_......INT_Divider(%)", + "ParentCategory": "Divider", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles where the Integer Divider unit was active.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "ARITH.FPDIV_ACTIVE", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b ) ) - ( c / ( b ) ) )", + "BaseFormula": "tma_divider - tma_fp_divider", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......INT_Divider(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Divider(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......INT_Divider(%) > 20 & metric_TMA_....Divider(%) > 20 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "Serializing_Operation", + "LegacyName": "metric_TMA_....Serializing_Operation(%)", + "ParentCategory": "Core_Bound", + "Level": 3, + "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.C02", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) + ( c / ( b ) ) )", + "BaseFormula": "resource_stalls.scoreboard / tma_info_thread_clks + tma_c02_wait", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Serializing_Operation(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20", + "BaseFormula": "metric_TMA_....Serializing_Operation(%) > 10 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueSO" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvIO;PortsUtil", + "LocateWith": "RESOURCE_STALLS.SCOREBOARD" + }, + { + "MetricName": "Slow_Pause", + "LegacyName": "metric_TMA_......Slow_Pause(%)", + "ParentCategory": "Serializing_Operation", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.PAUSE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "cpu_clk_unhalted.pause / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Slow_Pause(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Serializing_Operation(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......Slow_Pause(%) > 5 & metric_TMA_....Serializing_Operation(%) > 10 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "CPU_CLK_UNHALTED.PAUSE_INST" + }, + { + "MetricName": "C01_Wait", + "LegacyName": "metric_TMA_......C01_Wait(%)", + "ParentCategory": "Serializing_Operation", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due staying in C0.1 power-performance optimized state (Faster wakeup time; Smaller power savings).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.C01", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "cpu_clk_unhalted.c01 / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......C01_Wait(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Serializing_Operation(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......C01_Wait(%) > 5 & metric_TMA_....Serializing_Operation(%) > 10 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "C0Wait", + "LocateWith": "" + }, + { + "MetricName": "C02_Wait", + "LegacyName": "metric_TMA_......C02_Wait(%)", + "ParentCategory": "Serializing_Operation", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due staying in C0.2 power-performance optimized state (Slower wakeup time; Larger power savings).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.C02", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "cpu_clk_unhalted.c02 / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......C02_Wait(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Serializing_Operation(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......C02_Wait(%) > 5 & metric_TMA_....Serializing_Operation(%) > 10 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "C0Wait", + "LocateWith": "" + }, + { + "MetricName": "Memory_Fence", + "LegacyName": "metric_TMA_......Memory_Fence(%)", + "ParentCategory": "Serializing_Operation", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to LFENCE Instructions.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MISC2_RETIRED.LFENCE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 13 * a / ( b ) )", + "BaseFormula": "13 * misc2_retired.lfence / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Memory_Fence(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Serializing_Operation(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 5 & b > 10 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......Memory_Fence(%) > 5 & metric_TMA_....Serializing_Operation(%) > 10 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "AMX_Busy", + "LegacyName": "metric_TMA_....AMX_Busy(%)", + "ParentCategory": "Core_Bound", + "Level": 3, + "BriefDescription": "This metric estimates fraction of cycles where the Advanced Matrix eXtensions (AMX) execution engine was busy with tile (arithmetic) operations", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE.AMX_BUSY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( a / ( b if smt_on else ( c ) ) )", + "BaseFormula": "exe.amx_busy / tma_info_core_core_clks", + "Category": "TMA", + "CountDomain": "Core_Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....AMX_Busy(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 50 & b > 10 & c > 20", + "BaseFormula": "metric_TMA_....AMX_Busy(%) > 50 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvCB;Compute;HPC;Server", + "LocateWith": "" + }, + { + "MetricName": "Ports_Utilization", + "LegacyName": "metric_TMA_....Ports_Utilization(%)", + "ParentCategory": "Core_Bound", + "Level": 3, + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "Alias": "a" + }, + { + "Name": "RS.EMPTY_RESOURCE", + "Alias": "b" + }, + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "e" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "f" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "g" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "h" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "i" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "j" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "k" + }, + { + "Name": "EXE_ACTIVITY.2_3_PORTS_UTIL", + "Alias": "l" + }, + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "m" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( ( a + max( b - c , 0 ) ) / ( d ) * ( e - f ) / ( d ) ) * ( d ) + ( g + ( h / ( i + j + h + k ) ) * l ) ) / ( d ) if ( m < ( e - f ) ) else ( g + ( h / ( i + j + h + k ) ) * l ) / ( d ) )", + "BaseFormula": "( tma_ports_utilized_0 * tma_info_thread_clks + ( exe_activity.1_ports_util + tma_retiring * exe_activity.2_3_ports_util ) ) / tma_info_thread_clks if ( arith.div_active < ( cycle_activity.stalls_total - exe_activity.bound_on_loads ) ) else ( exe_activity.1_ports_util + tma_retiring * exe_activity.2_3_ports_util ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Ports_Utilization(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 15 & b > 10 & c > 20", + "BaseFormula": "metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil", + "LocateWith": "" + }, + { + "MetricName": "Ports_Utilized_0", + "LegacyName": "metric_TMA_......Ports_Utilized_0(%)", + "ParentCategory": "Ports_Utilization", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "Alias": "a" + }, + { + "Name": "RS.EMPTY_RESOURCE", + "Alias": "b" + }, + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "e" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + max( b - c , 0 ) ) / ( d ) * ( e - f ) / ( d ) )", + "BaseFormula": "( exe_activity.exe_bound_0_ports + max( rs.empty_resource - resource_stalls.scoreboard , 0 ) ) / tma_info_thread_clks * ( cycle_activity.stalls_total - exe_activity.bound_on_loads ) / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Ports_Utilized_0(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Ports_Utilization(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 15 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......Ports_Utilized_0(%) > 20 & metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil", + "LocateWith": "" + }, + { + "MetricName": "Mixing_Vectors", + "LegacyName": "metric_TMA_........Mixing_Vectors(%)", + "ParentCategory": "Ports_Utilized_0", + "Level": 5, + "BriefDescription": "This metric estimates penalty in terms of percentage of([SKL+] injected blend uops out of all Uops Issued , the Count Domain; [ADL+] cycles). Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ASSISTS.SSE_AVX_MIX", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 160 * a / ( b ) )", + "BaseFormula": "160 * assists.sse_avx_mix / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Mixing_Vectors(%)" + } + ], + "Formula": "a > 5", + "BaseFormula": "metric_TMA_........Mixing_Vectors(%) > 5", + "ThresholdIssues": "$issueMV" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "Ports_Utilized_1", + "LegacyName": "metric_TMA_......Ports_Utilized_1(%)", + "ParentCategory": "Ports_Utilization", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "exe_activity.1_ports_util / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Ports_Utilized_1(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Ports_Utilization(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 15 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......Ports_Utilized_1(%) > 20 & metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issueL1" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil", + "LocateWith": "EXE_ACTIVITY.1_PORTS_UTIL" + }, + { + "MetricName": "Ports_Utilized_2", + "LegacyName": "metric_TMA_......Ports_Utilized_2(%)", + "ParentCategory": "Ports_Utilization", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "EXE_ACTIVITY.2_PORTS_UTIL", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "exe_activity.2_ports_util / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Ports_Utilized_2(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Ports_Utilization(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 15 & b > 15 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......Ports_Utilized_2(%) > 15 & metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "PortsUtil", + "LocateWith": "EXE_ACTIVITY.2_PORTS_UTIL" + }, + { + "MetricName": "Ports_Utilized_3m", + "LegacyName": "metric_TMA_......Ports_Utilized_3m(%)", + "ParentCategory": "Ports_Utilization", + "Level": 4, + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_EXECUTED.CYCLES_GE_3", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "uops_executed.cycles_ge_3 / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Ports_Utilized_3m(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Ports_Utilization(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 40 & b > 15 & c > 10 & d > 20", + "BaseFormula": "metric_TMA_......Ports_Utilized_3m(%) > 40 & metric_TMA_....Ports_Utilization(%) > 15 & metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvCB;PortsUtil", + "LocateWith": "UOPS_EXECUTED.CYCLES_GE_3" + }, + { + "MetricName": "ALU_Op_Utilization", + "LegacyName": "metric_TMA_........ALU_Op_Utilization(%)", + "ParentCategory": "Ports_Utilized_3m", + "Level": 5, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_0", + "Alias": "a" + }, + { + "Name": "UOPS_DISPATCHED.PORT_1", + "Alias": "b" + }, + { + "Name": "UOPS_DISPATCHED.PORT_5_11", + "Alias": "c" + }, + { + "Name": "UOPS_DISPATCHED.PORT_6", + "Alias": "d" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "e" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "f" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a + b + c + d ) / ( 5 * ( e if smt_on else ( f ) ) ) )", + "BaseFormula": "( uops_dispatched.port_0 + uops_dispatched.port_1 + uops_dispatched.port_5_11 + uops_dispatched.port_6 ) / ( 5 * tma_info_core_core_clks )", + "Category": "TMA", + "CountDomain": "Core_Execution", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........ALU_Op_Utilization(%)" + } + ], + "Formula": "a > 40", + "BaseFormula": "metric_TMA_........ALU_Op_Utilization(%) > 40", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "Port_0", + "LegacyName": "metric_TMA_..........Port_0(%)", + "ParentCategory": "ALU_Op_Utilization", + "Level": 6, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_0", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( a / ( b if smt_on else ( c ) ) )", + "BaseFormula": "uops_dispatched.port_0 / tma_info_core_core_clks", + "Category": "TMA", + "CountDomain": "Core_Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Port_0(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..........Port_0(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute", + "LocateWith": "UOPS_DISPATCHED.PORT_0" + }, + { + "MetricName": "Port_1", + "LegacyName": "metric_TMA_..........Port_1(%)", + "ParentCategory": "ALU_Op_Utilization", + "Level": 6, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_1", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( a / ( b if smt_on else ( c ) ) )", + "BaseFormula": "uops_dispatched.port_1 / tma_info_core_core_clks", + "Category": "TMA", + "CountDomain": "Core_Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Port_1(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..........Port_1(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "UOPS_DISPATCHED.PORT_1" + }, + { + "MetricName": "Port_6", + "LegacyName": "metric_TMA_..........Port_6(%)", + "ParentCategory": "ALU_Op_Utilization", + "Level": 6, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple ALU)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_6", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( a / ( b if smt_on else ( c ) ) )", + "BaseFormula": "uops_dispatched.port_6 / tma_info_core_core_clks", + "Category": "TMA", + "CountDomain": "Core_Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..........Port_6(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..........Port_6(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "UOPS_DISPATCHED.PORT_1" + }, + { + "MetricName": "Load_Op_Utilization", + "LegacyName": "metric_TMA_........Load_Op_Utilization(%)", + "ParentCategory": "Ports_Utilized_3m", + "Level": 5, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_2_3_10", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( a / ( 3 * ( b if smt_on else ( c ) ) ) )", + "BaseFormula": "uops_dispatched.port_2_3_10 / ( 3 * tma_info_core_core_clks )", + "Category": "TMA", + "CountDomain": "Core_Execution", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Load_Op_Utilization(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_........Load_Op_Utilization(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "UOPS_DISPATCHED.PORT_2_3_10" + }, + { + "MetricName": "Store_Op_Utilization", + "LegacyName": "metric_TMA_........Store_Op_Utilization(%)", + "ParentCategory": "Ports_Utilized_3m", + "Level": 5, + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_DISPATCHED.PORT_4_9", + "Alias": "a" + }, + { + "Name": "UOPS_DISPATCHED.PORT_7_8", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "d" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a + b ) / ( 4 * ( c if smt_on else ( d ) ) ) )", + "BaseFormula": "( uops_dispatched.port_4_9 + uops_dispatched.port_7_8 ) / ( 4 * tma_info_core_core_clks )", + "Category": "TMA", + "CountDomain": "Core_Execution", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Store_Op_Utilization(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_........Store_Op_Utilization(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "UOPS_DISPATCHED.PORT_7_8" + }, + { + "MetricName": "Retiring", + "LegacyName": "metric_TMA_Retiring(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b + c + a + d ) )", + "BaseFormula": "perf_metrics.retiring / ( perf_metrics.frontend_bound + perf_metrics.bad_speculation + perf_metrics.retiring + perf_metrics.backend_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Retiring(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 70 | b > 10", + "BaseFormula": "metric_TMA_Retiring(%) > 70 | metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvUW;TmaL1", + "LocateWith": "UOPS_RETIRED.SLOTS" + }, + { + "MetricName": "Light_Operations", + "LegacyName": "metric_TMA_..Light_Operations(%)", + "ParentCategory": "Retiring", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations , instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) )", + "BaseFormula": "max( 0 , tma_retiring - tma_heavy_operations )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Retire;TmaL2", + "LocateWith": "INST_RETIRED.PREC_DIST" + }, + { + "MetricName": "FP_Arith", + "LegacyName": "metric_TMA_....FP_Arith(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "UOPS_EXECUTED.X87", + "Alias": "e" + }, + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "f" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "g" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR", + "Alias": "h" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "i" + }, + { + "Name": "FP_ARITH_INST_RETIRED.VECTOR", + "Alias": "j" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.VECTOR", + "Alias": "k" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a / ( b + c + a + d ) ) * e / f ) + ( ( g + h ) / ( ( a / ( b + c + a + d ) ) * ( i ) ) ) + ( ( j + k ) / ( ( a / ( b + c + a + d ) ) * ( i ) ) ) )", + "BaseFormula": "tma_x87_use + tma_fp_scalar + tma_fp_vector", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....FP_Arith(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 20 & b > 60", + "BaseFormula": "metric_TMA_....FP_Arith(%) > 20 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC", + "LocateWith": "" + }, + { + "MetricName": "X87_Use", + "LegacyName": "metric_TMA_......X87_Use(%)", + "ParentCategory": "FP_Arith", + "Level": 4, + "BriefDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "UOPS_EXECUTED.X87", + "Alias": "e" + }, + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( ( a / ( b + c + a + d ) ) * e / f )", + "BaseFormula": "tma_retiring * uops_executed.x87 / uops_executed.thread", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......X87_Use(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....FP_Arith(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 60", + "BaseFormula": "metric_TMA_......X87_Use(%) > 10 & metric_TMA_....FP_Arith(%) > 20 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute", + "LocateWith": "" + }, + { + "MetricName": "FP_Scalar", + "LegacyName": "metric_TMA_......FP_Scalar(%)", + "ParentCategory": "FP_Arith", + "Level": 4, + "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) )", + "BaseFormula": "( fp_arith_inst_retired.scalar + fp_arith_inst_retired2.scalar ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......FP_Scalar(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....FP_Arith(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 60", + "BaseFormula": "metric_TMA_......FP_Scalar(%) > 10 & metric_TMA_....FP_Arith(%) > 20 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops", + "LocateWith": "" + }, + { + "MetricName": "FP_Vector", + "LegacyName": "metric_TMA_......FP_Vector(%)", + "ParentCategory": "FP_Arith", + "Level": 4, + "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.VECTOR", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.VECTOR", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) )", + "BaseFormula": "( fp_arith_inst_retired.vector + fp_arith_inst_retired2.vector ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......FP_Vector(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....FP_Arith(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 20 & c > 60", + "BaseFormula": "metric_TMA_......FP_Vector(%) > 10 & metric_TMA_....FP_Arith(%) > 20 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops", + "LocateWith": "" + }, + { + "MetricName": "FP_Vector_128b", + "LegacyName": "metric_TMA_........FP_Vector_128b(%)", + "ParentCategory": "FP_Vector", + "Level": 5, + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting prior to LNL.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b + c ) / ( ( d / ( e + f + d + g ) ) * ( h ) ) )", + "BaseFormula": "( fp_arith_inst_retired.128b_packed_double + fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired2.128b_packed_half ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........FP_Vector_128b(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......FP_Vector(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....FP_Arith(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 60", + "BaseFormula": "metric_TMA_........FP_Vector_128b(%) > 10 & metric_TMA_......FP_Vector(%) > 10 & metric_TMA_....FP_Arith(%) > 20 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops", + "LocateWith": "" + }, + { + "MetricName": "FP_Vector_256b", + "LegacyName": "metric_TMA_........FP_Vector_256b(%)", + "ParentCategory": "FP_Vector", + "Level": 5, + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting prior to LNL.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b + c ) / ( ( d / ( e + f + d + g ) ) * ( h ) ) )", + "BaseFormula": "( fp_arith_inst_retired.256b_packed_double + fp_arith_inst_retired.256b_packed_single + fp_arith_inst_retired2.256b_packed_half ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........FP_Vector_256b(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......FP_Vector(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....FP_Arith(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 60", + "BaseFormula": "metric_TMA_........FP_Vector_256b(%) > 10 & metric_TMA_......FP_Vector(%) > 10 & metric_TMA_....FP_Arith(%) > 20 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops", + "LocateWith": "" + }, + { + "MetricName": "FP_Vector_512b", + "LegacyName": "metric_TMA_........FP_Vector_512b(%)", + "ParentCategory": "FP_Vector", + "Level": 5, + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b + c ) / ( ( d / ( e + f + d + g ) ) * ( h ) ) )", + "BaseFormula": "( fp_arith_inst_retired.512b_packed_double + fp_arith_inst_retired.512b_packed_single + fp_arith_inst_retired2.512b_packed_half ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........FP_Vector_512b(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_......FP_Vector(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_....FP_Arith(%)" + }, + { + "Alias": "d", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 20 & d > 60", + "BaseFormula": "metric_TMA_........FP_Vector_512b(%) > 10 & metric_TMA_......FP_Vector(%) > 10 & metric_TMA_....FP_Arith(%) > 20 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;Flops", + "LocateWith": "" + }, + { + "MetricName": "Int_Operations", + "LegacyName": "metric_TMA_....Int_Operations(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired). Vector/Matrix Int operations and shuffles are counted. Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_VEC_RETIRED.ADD_128", + "Alias": "a" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_128", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "INT_VEC_RETIRED.ADD_256", + "Alias": "h" + }, + { + "Name": "INT_VEC_RETIRED.MUL_256", + "Alias": "i" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_256", + "Alias": "j" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) ) + ( ( h + i + j ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) ) )", + "BaseFormula": "tma_int_vector_128b + tma_int_vector_256b", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Int_Operations(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 60", + "BaseFormula": "metric_TMA_....Int_Operations(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Int_Vector_128b", + "LegacyName": "metric_TMA_......Int_Vector_128b(%)", + "ParentCategory": "Int_Operations", + "Level": 4, + "BriefDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_VEC_RETIRED.ADD_128", + "Alias": "a" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_128", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b ) / ( ( c / ( d + e + c + f ) ) * ( g ) ) )", + "BaseFormula": "( int_vec_retired.add_128 + int_vec_retired.vnni_128 ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Int_Vector_128b(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Int_Operations(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 60", + "BaseFormula": "metric_TMA_......Int_Vector_128b(%) > 10 & metric_TMA_....Int_Operations(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;IntVector;Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Int_Vector_256b", + "LegacyName": "metric_TMA_......Int_Vector_256b(%)", + "ParentCategory": "Int_Operations", + "Level": 4, + "BriefDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD/MUL or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "INT_VEC_RETIRED.ADD_256", + "Alias": "a" + }, + { + "Name": "INT_VEC_RETIRED.MUL_256", + "Alias": "b" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_256", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "e" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( ( a + b + c ) / ( ( d / ( e + f + d + g ) ) * ( h ) ) )", + "BaseFormula": "( int_vec_retired.add_256 + int_vec_retired.mul_256 + int_vec_retired.vnni_256 ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Uops", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Int_Vector_256b(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Int_Operations(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 10 & c > 60", + "BaseFormula": "metric_TMA_......Int_Vector_256b(%) > 10 & metric_TMA_....Int_Operations(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "$issue2P" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Compute;IntVector;Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Memory_Operations", + "LegacyName": "metric_TMA_....Memory_Operations(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations , uops for memory load or store accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "MEM_UOP_RETIRED.ANY", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * f / ( ( a / ( b + c + a + d ) ) * ( g ) ) )", + "BaseFormula": "tma_light_operations * mem_uop_retired.any / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Memory_Operations(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 60", + "BaseFormula": "metric_TMA_....Memory_Operations(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Fused_Instructions", + "LegacyName": "metric_TMA_....Fused_Instructions(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions , where one uop can represent multiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Other_Light_Ops in MTL!)}", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "INST_RETIRED.MACRO_FUSED", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * f / ( ( a / ( b + c + a + d ) ) * ( g ) ) )", + "BaseFormula": "tma_light_operations * inst_retired.macro_fused / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Fused_Instructions(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 60", + "BaseFormula": "metric_TMA_....Fused_Instructions(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;BvBO;Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Non_Fused_Branches", + "LegacyName": "metric_TMA_....Non_Fused_Branches(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "f" + }, + { + "Name": "INST_RETIRED.MACRO_FUSED", + "Alias": "g" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "h" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * ( f - g ) / ( ( a / ( b + c + a + d ) ) * ( h ) ) )", + "BaseFormula": "tma_light_operations * ( br_inst_retired.all_branches - inst_retired.macro_fused ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Non_Fused_Branches(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 60", + "BaseFormula": "metric_TMA_....Non_Fused_Branches(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;BvBO;Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Other_Light_Ops", + "LegacyName": "metric_TMA_....Other_Light_Ops(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "UOPS_EXECUTED.X87", + "Alias": "f" + }, + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "g" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "h" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR", + "Alias": "i" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "j" + }, + { + "Name": "FP_ARITH_INST_RETIRED.VECTOR", + "Alias": "k" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.VECTOR", + "Alias": "l" + }, + { + "Name": "INT_VEC_RETIRED.ADD_128", + "Alias": "m" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_128", + "Alias": "n" + }, + { + "Name": "INT_VEC_RETIRED.ADD_256", + "Alias": "o" + }, + { + "Name": "INT_VEC_RETIRED.MUL_256", + "Alias": "p" + }, + { + "Name": "INT_VEC_RETIRED.VNNI_256", + "Alias": "q" + }, + { + "Name": "MEM_UOP_RETIRED.ANY", + "Alias": "r" + }, + { + "Name": "INST_RETIRED.MACRO_FUSED", + "Alias": "s" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "t" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) - ( ( ( ( a / ( b + c + a + d ) ) * f / g ) + ( ( h + i ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( ( k + l ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) ) + ( ( ( m + n ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( ( o + p + q ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * r / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * s / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) + ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * ( t - s ) / ( ( a / ( b + c + a + d ) ) * ( j ) ) ) ) ) )", + "BaseFormula": "max( 0 , tma_light_operations - ( tma_fp_arith + tma_int_operations + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Other_Light_Ops(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 30 & b > 60", + "BaseFormula": "metric_TMA_....Other_Light_Ops(%) > 30 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Nop_Instructions", + "LegacyName": "metric_TMA_......Nop_Instructions(%)", + "ParentCategory": "Other_Light_Ops", + "Level": 4, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "INST_RETIRED.NOP", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * f / ( ( a / ( b + c + a + d ) ) * ( g ) ) )", + "BaseFormula": "tma_light_operations * inst_retired.nop / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Nop_Instructions(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Other_Light_Ops(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 30 & c > 60", + "BaseFormula": "metric_TMA_......Nop_Instructions(%) > 10 & metric_TMA_....Other_Light_Ops(%) > 30 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvBO;Pipeline", + "LocateWith": "INST_RETIRED.NOP" + }, + { + "MetricName": "Shuffles_256b", + "LegacyName": "metric_TMA_......Shuffles_256b(%)", + "ParentCategory": "Other_Light_Ops", + "Level": 4, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring Shuffle operations of 256-bit vector size (FP or Integer). Shuffles may incur slow cross \"vector lane\" data transfers.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "e" + }, + { + "Name": "INT_VEC_RETIRED.SHUFFLES", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b + c + a + d ) ) - ( e / ( b + c + a + d ) ) ) ) * f / ( ( a / ( b + c + a + d ) ) * ( g ) ) )", + "BaseFormula": "tma_light_operations * int_vec_retired.shuffles / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Shuffles_256b(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Other_Light_Ops(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 30 & c > 60", + "BaseFormula": "metric_TMA_......Shuffles_256b(%) > 10 & metric_TMA_....Other_Light_Ops(%) > 30 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Heavy_Operations", + "LegacyName": "metric_TMA_..Heavy_Operations(%)", + "ParentCategory": "Retiring", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations , instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.([ICL+] Note this may overcount due to approximation using indirect events; [ADL+])", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b + c + d + e ) )", + "BaseFormula": "perf_metrics.heavy_operations / ( perf_metrics.frontend_bound + perf_metrics.bad_speculation + perf_metrics.retiring + perf_metrics.backend_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Retire;TmaL2", + "LocateWith": "UOPS_RETIRED.HEAVY" + }, + { + "MetricName": "Few_Uops_Instructions", + "LegacyName": "metric_TMA_....Few_Uops_Instructions(%)", + "ParentCategory": "Heavy_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or more uops. This highly-correlates with the number of uops in such instructions.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "PERF_METRICS.HEAVY_OPERATIONS", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "UOPS_RETIRED.MS", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b + c + d + e ) ) - ( f / ( g ) ) ) )", + "BaseFormula": "max( 0 , tma_heavy_operations - tma_microcode_sequencer )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Few_Uops_Instructions(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 5 & b > 10", + "BaseFormula": "metric_TMA_....Few_Uops_Instructions(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "$issueD0" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "Microcode_Sequencer", + "LegacyName": "metric_TMA_....Microcode_Sequencer(%)", + "ParentCategory": "Heavy_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.MS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "uops_retired.ms / tma_info_thread_slots", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Microcode_Sequencer(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 5 & b > 10", + "BaseFormula": "metric_TMA_....Microcode_Sequencer(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "$issueMC, $issueMS" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq", + "LocateWith": "UOPS_RETIRED.MS" + }, + { + "MetricName": "Assists", + "LegacyName": "metric_TMA_......Assists(%)", + "ParentCategory": "Microcode_Sequencer", + "Level": 4, + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ASSISTS.ANY", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * a / ( b ) )", + "BaseFormula": "( ( 99 *3 + 63 + 30 ) / 5 ) * assists.any / tma_info_thread_slots", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......Assists(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Microcode_Sequencer(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 10 & b > 5 & c > 10", + "BaseFormula": "metric_TMA_......Assists(%) > 10 & metric_TMA_....Microcode_Sequencer(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvIO", + "LocateWith": "ASSISTS.ANY" + }, + { + "MetricName": "Page_Faults", + "LegacyName": "metric_TMA_........Page_Faults(%)", + "ParentCategory": "Assists", + "Level": 5, + "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults. A Page Fault may apply on first application access to a memory page. Note operating system handling of page faults accounts for the majority of its cost.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ASSISTS.PAGE_FAULT", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 99 * a / ( b ) )", + "BaseFormula": "99 * assists.page_fault / tma_info_thread_slots", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........Page_Faults(%)" + } + ], + "Formula": "a > 5", + "BaseFormula": "metric_TMA_........Page_Faults(%) > 5", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "FP_Assists", + "LegacyName": "metric_TMA_........FP_Assists(%)", + "ParentCategory": "Assists", + "Level": 5, + "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ASSISTS.FP", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 30 * a / ( b ) )", + "BaseFormula": "30 * assists.fp / tma_info_thread_slots", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........FP_Assists(%)" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_........FP_Assists(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC", + "LocateWith": "" + }, + { + "MetricName": "AVX_Assists", + "LegacyName": "metric_TMA_........AVX_Assists(%)", + "ParentCategory": "Assists", + "Level": 5, + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "ASSISTS.SSE_AVX_MIX", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( 63 * a / ( b ) )", + "BaseFormula": "63 * assists.sse_avx_mix / tma_info_thread_slots", + "Category": "TMA", + "CountDomain": "Slots_Estimated", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_........AVX_Assists(%)" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_........AVX_Assists(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC", + "LocateWith": "" + }, + { + "MetricName": "CISC", + "LegacyName": "metric_TMA_......CISC(%)", + "ParentCategory": "Microcode_Sequencer", + "Level": 4, + "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.MS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "b" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b ) ) - ( ( ( 99 * 3 + 63 + 30 ) / 5 ) * c / ( b ) ) ) )", + "BaseFormula": "max( 0 , tma_microcode_sequencer - tma_assists )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_......CISC(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_....Microcode_Sequencer(%)" + }, + { + "Alias": "c", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 10 & b > 5 & c > 10", + "BaseFormula": "metric_TMA_......CISC(%) > 10 & metric_TMA_....Microcode_Sequencer(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "FRONTEND_RETIRED.MS_FLOWS" + }, + { + "MetricName": "Info_Botlnk_L0_Core_Bound_Likely", + "LegacyName": "metric_TMA_Info_Botlnk_L0_Core_Bound_Likely", + "Level": 1, + "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.MEMORY_BOUND", + "Alias": "e" + }, + { + "Name": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "Alias": "f" + }, + { + "Name": "RS.EMPTY_RESOURCE", + "Alias": "g" + }, + { + "Name": "RESOURCE_STALLS.SCOREBOARD", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + }, + { + "Name": "CYCLE_ACTIVITY.STALLS_TOTAL", + "Alias": "j" + }, + { + "Name": "EXE_ACTIVITY.BOUND_ON_LOADS", + "Alias": "k" + }, + { + "Name": "EXE_ACTIVITY.1_PORTS_UTIL", + "Alias": "l" + }, + { + "Name": "EXE_ACTIVITY.2_3_PORTS_UTIL", + "Alias": "m" + }, + { + "Name": "ARITH.DIV_ACTIVE", + "Alias": "n" + }, + { + "Name": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "Alias": "o" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "Alias": "p" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( 1 - ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) / ( ( ( ( f + max( g - h , 0 ) ) / ( i ) * ( j - k ) / ( i ) ) * ( i ) + ( l + ( d / ( b + c + d + a ) ) * m ) ) / ( i ) if ( n < ( j - k ) ) else ( l + ( d / ( b + c + d + a ) ) * m ) / ( i ) ) if ( max( 0 , ( a / ( b + c + d + a ) ) - ( e / ( b + c + d + a ) ) ) ) < ( ( ( ( f + max( g - h , 0 ) ) / ( i ) * ( j - k ) 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+ } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "br_inst_retired.all_branches / br_inst_retired.near_taken", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;Fed;PGO", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpFLOP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpFLOP", + "Level": 1, + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", + "Alias": "e" + }, + { + "Name": "FP_ARITH_INST_RETIRED.4_FLOPS", + "Alias": "f" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", + "Alias": "g" + }, + { + "Name": "FP_ARITH_INST_RETIRED.8_FLOPS", + "Alias": "h" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", + "Alias": "i" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "j" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", + "Alias": "k" + } + ], + "Constants": [], + "Formula": "a / ( ( 1 * ( b + c ) + 2 * ( d + e ) + 4 * f + 8 * ( g + h ) + 16 * ( i + j ) + 32 * k ) )", + "BaseFormula": "inst_retired.any / ( ( 1 * ( fp_arith_inst_retired.scalar + fp_arith_inst_retired2.scalar_half ) + 2 * ( fp_arith_inst_retired.128b_packed_double + fp_arith_inst_retired2.complex_scalar_half ) + 4 * fp_arith_inst_retired.4_flops + 8 * ( fp_arith_inst_retired2.128b_packed_half + fp_arith_inst_retired.8_flops ) + 16 * ( fp_arith_inst_retired2.256b_packed_half + fp_arith_inst_retired.512b_packed_single ) + 32 * fp_arith_inst_retired2.512b_packed_half ) )", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpFLOP" + } + ], + "Formula": "a < 10", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpFLOP < 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpArith", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting. Approximated prior to BDW.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED.VECTOR", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.VECTOR", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "a / ( ( b + c ) + ( d + e ) )", + "BaseFormula": "inst_retired.any / ( ( fp_arith_inst_retired.scalar + fp_arith_inst_retired2.scalar ) + ( fp_arith_inst_retired.vector + fp_arith_inst_retired2.vector ) )", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpArith" + } + ], + "Formula": "a < 10", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpArith < 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_Scalar_HP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_HP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Half-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / fp_arith_inst_retired2.scalar", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_HP" + } + ], + "Formula": "a < 10", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_HP < 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpScalar;InsType;Server", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_Scalar_SP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_SP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / fp_arith_inst_retired.scalar_single", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_SP" + } + ], + "Formula": "a < 10", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_SP < 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpScalar;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_Scalar_DP", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_DP", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / fp_arith_inst_retired.scalar_double", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_DP" + } + ], + "Formula": "a < 10", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpArith_Scalar_DP < 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpScalar;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX128", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX128", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "a / ( b + c + d )", + "BaseFormula": "inst_retired.any / ( fp_arith_inst_retired.128b_packed_double + fp_arith_inst_retired.128b_packed_single + fp_arith_inst_retired2.128b_packed_half )", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpArith_AVX128" + } + ], + "Formula": "a < 10", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpArith_AVX128 < 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX256", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX256", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "a / ( b + c + d )", + "BaseFormula": "inst_retired.any / ( fp_arith_inst_retired.256b_packed_double + fp_arith_inst_retired.256b_packed_single + fp_arith_inst_retired2.256b_packed_half )", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpArith_AVX256" + } + ], + "Formula": "a < 10", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpArith_AVX256 < 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpArith_AVX512", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpArith_AVX512", + "Level": 1, + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). Values < 1 are possible due to intentional FMA double counting.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "a / ( b + c + d )", + "BaseFormula": "inst_retired.any / ( fp_arith_inst_retired.512b_packed_double + fp_arith_inst_retired.512b_packed_single + fp_arith_inst_retired2.512b_packed_half )", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpArith_AVX512" + } + ], + "Formula": "a < 10", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpArith_AVX512 < 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpPause", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpPause", + "Level": 1, + "BriefDescription": "Instructions per PAUSE (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.PAUSE_INST", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "BaseFormula": "tma_info_inst_mix_instructions / cpu_clk_unhalted.pause_inst", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops;FpVector;InsType", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_IpSWPF", + "LegacyName": "metric_TMA_Info_Inst_Mix_IpSWPF", + "Level": 1, + "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "SW_PREFETCH_ACCESS.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / sw_prefetch_access.any", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Inst_Mix_IpSWPF" + } + ], + "Formula": "a < 100", + "BaseFormula": "metric_TMA_Info_Inst_Mix_IpSWPF < 100", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Prefetches", + "LocateWith": "" + }, + { + "MetricName": "Info_Inst_Mix_Instructions", + "LegacyName": "metric_TMA_Info_Inst_Mix_Instructions", + "Level": 1, + "BriefDescription": "Total number of retired Instructions", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "BaseFormula": "inst_retired.any", + "Category": "TMA", + "CountDomain": "Count", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary;TmaL1", + "LocateWith": "INST_RETIRED.PREC_DIST" + }, + { + "MetricName": "Info_Pipeline_Retire", + "LegacyName": "metric_TMA_Info_Pipeline_Retire", + "Level": 1, + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "e" + }, + { + "Name": "UOPS_RETIRED.SLOTS:c1", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "( ( a / ( b + c + a + d ) ) * ( e ) ) / f", + "BaseFormula": "( tma_retiring * tma_info_thread_slots ) / uops_retired.slots:c1", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline;Ret", + "LocateWith": "" + }, + { + "MetricName": "Info_Pipeline_Strings_Cycles", + "LegacyName": "metric_TMA_Info_Pipeline_Strings_Cycles", + "Level": 1, + "BriefDescription": "Estimated fraction of retirement-cycles dealing with repeat instructions", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.REP_ITERATION", + "Alias": "a" + }, + { + "Name": "UOPS_RETIRED.SLOTS:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.rep_iteration / uops_retired.slots:c1", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Pipeline_Strings_Cycles" + } + ], + "Formula": "a > 0.1", + "BaseFormula": "metric_TMA_Info_Pipeline_Strings_Cycles > 0.1", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq;Pipeline;Ret", + "LocateWith": "" + }, + { + "MetricName": "Info_Pipeline_IpAssist", + "LegacyName": "metric_TMA_Info_Pipeline_IpAssist", + "Level": 1, + "BriefDescription": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "ASSISTS.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / assists.any", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Pipeline_IpAssist" + } + ], + "Formula": "a < 100000", + "BaseFormula": "metric_TMA_Info_Pipeline_IpAssist < 100000", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq;Pipeline;Ret;Retire", + "LocateWith": "" + }, + { + "MetricName": "Info_Pipeline_Execute", + "LegacyName": "metric_TMA_Info_Pipeline_Execute", + "Level": 1, + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per physical core", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_EXECUTED.THREAD", + "Alias": "a" + }, + { + "Name": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "Alias": "b" + }, + { + "Name": "UOPS_EXECUTED.THREAD:c1", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "a / ( ( b / 2 ) if smt_on else c )", + "BaseFormula": "uops_executed.thread / ( ( uops_executed.core_cycles_ge_1 / 2 ) if smt_on else uops_executed.thread:c1 )", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "LocateWith": "" + }, + { + "MetricName": "Info_Pipeline_Fetch_DSB", + "LegacyName": "metric_TMA_Info_Pipeline_Fetch_DSB", + "Level": 1, + "BriefDescription": "Average number of uops fetched from DSB per cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.DSB_CYCLES_ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "idq.dsb_uops / idq.dsb_cycles_any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Pipeline_Fetch_MITE", + "LegacyName": "metric_TMA_Info_Pipeline_Fetch_MITE", + "Level": 1, + "BriefDescription": "Average number of uops fetched from MITE per cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ.MITE_UOPS", + "Alias": "a" + }, + { + "Name": "IDQ.MITE_CYCLES_ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "idq.mite_uops / idq.mite_cycles_any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_Fetch_UpC", + "LegacyName": "metric_TMA_Info_Frontend_Fetch_UpC", + "Level": 1, + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "uops_issued.any / uops_issued.any:c1", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_DSB_Coverage", + "LegacyName": "metric_TMA_Info_Frontend_DSB_Coverage", + "Level": 1, + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "IDQ.DSB_UOPS", + "Alias": "a" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "BaseFormula": "idq.dsb_uops / ( uops_issued.any )", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Frontend_DSB_Coverage" + }, + { + "Alias": "b", + "Value": "metric_TMA_Info_Thread_IPC" + } + ], + "Formula": "a < 0.7 & b / 6 > 0.35", + "BaseFormula": "metric_TMA_Info_Frontend_DSB_Coverage < 0.7 & metric_TMA_Info_Thread_IPC / 6 > 0.35", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSB;Fed;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_Unknown_Branch_Cost", + "LegacyName": "metric_TMA_Info_Frontend_Unknown_Branch_Cost", + "Level": 1, + "BriefDescription": "Average number of cycles the front-end was delayed due to an Unknown Branch detection. See Unknown_Branches node.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "a" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES:c1:e1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "int_misc.unknown_branch_cycles / int_misc.unknown_branch_cycles:c1:e1", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_DSB_Switch_Cost", + "LegacyName": "metric_TMA_Info_Frontend_DSB_Switch_Cost", + "Level": 1, + "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "a" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES:c1:e1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "dsb2mite_switches.penalty_cycles / dsb2mite_switches.penalty_cycles:c1:e1", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_TBpC", + "LegacyName": "metric_TMA_Info_Frontend_TBpC", + "Level": 1, + "BriefDescription": "Taken Branches retired Per Cycle", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_INST_RETIRED.NEAR_TAKEN", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "BaseFormula": "br_inst_retired.near_taken / tma_info_thread_clks", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_ICache_Miss_Latency", + "LegacyName": "metric_TMA_Info_Frontend_ICache_Miss_Latency", + "Level": 1, + "BriefDescription": "Average Latency for L1 instruction cache misses", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "a" + }, + { + "Name": "ICACHE_DATA.STALLS:c1:e1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "icache_data.stalls / icache_data.stalls:c1:e1", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchLat;IcMiss", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_IpDSB_Miss_Ret", + "LegacyName": "metric_TMA_Info_Frontend_IpDSB_Miss_Ret", + "Level": 1, + "BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "FRONTEND_RETIRED.ANY_DSB_MISS", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / frontend_retired.any_dsb_miss", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Frontend_IpDSB_Miss_Ret" + } + ], + "Formula": "a < 50", + "BaseFormula": "metric_TMA_Info_Frontend_IpDSB_Miss_Ret < 50", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;Fed", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_IpUnknown_Branch", + "LegacyName": "metric_TMA_Info_Frontend_IpUnknown_Branch", + "Level": 1, + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "BaseFormula": "tma_info_inst_mix_instructions / baclears.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_L2MPKI_Code", + "LegacyName": "metric_TMA_Info_Frontend_L2MPKI_Code", + "Level": 1, + "BriefDescription": "L2 cache true code cacheline misses per kilo instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FRONTEND_RETIRED.L2_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": "1000 * frontend_retired.l2_miss / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "IcMiss", + "LocateWith": "" + }, + { + "MetricName": "Info_Frontend_L2MPKI_Code_All", + "LegacyName": "metric_TMA_Info_Frontend_L2MPKI_Code_All", + "Level": 1, + "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_RQSTS.CODE_RD_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": "1000 * l2_rqsts.code_rd_miss / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "IcMiss", + "LocateWith": "" + }, + { + "MetricName": "Info_Botlnk_L2_DSB_Misses", + "LegacyName": "metric_TMA_Info_Botlnk_L2_DSB_Misses", + "Level": 1, + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "j" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "k" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "l" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "m" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "n" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "o" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "p" + }, + { + "Name": "DECODE.LCP", + "Alias": "q" + }, + { + "Name": "IDQ.MITE_CYCLES_ANY", + "Alias": "r" + }, + { + "Name": "IDQ.MITE_CYCLES_OK", + "Alias": "s" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "t" + }, + { + "Name": "IDQ.DSB_CYCLES_ANY", + "Alias": "u" + }, + { + "Name": "IDQ.DSB_CYCLES_OK", + "Alias": "v" + }, + { + "Name": "IDQ.MS_CYCLES_ANY", + "Alias": "w" + }, + { + "Name": "UOPS_RETIRED.MS:c1", + "Alias": "x" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( h / ( i ) ) / ( ( j / ( i ) ) + ( k / ( i ) ) + ( l / ( i ) + ( m / ( i ) ) ) + ( ( 3 ) * n / ( o / p ) / ( i ) ) + ( q / ( i ) ) + ( h / ( i ) ) ) + ( max( 0 , ( b / ( b + c + d + e ) - f / ( g ) ) - ( ( a / ( b + c + d + e ) - f / ( g ) ) ) ) ) * ( ( r - s ) / ( t if smt_on else ( i ) ) / 2 ) / ( ( ( r - s ) / ( t if smt_on else ( i ) ) / 2 ) + ( ( u - v ) / ( t if smt_on else ( i ) ) / 2 ) + ( max( w , x / ( o / p ) ) / ( t if smt_on else ( i ) ) / 2.4 ) ) )", + "BaseFormula": "100 * ( tma_fetch_latency * tma_dsb_switches / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_mite / ( tma_mite + tma_dsb + tma_ms ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Misses" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Misses > 10", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSBmiss;Fed", + "LocateWith": "" + }, + { + "MetricName": "Info_Botlnk_L2_DSB_Bandwidth", + "LegacyName": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth", + "Level": 1, + "BriefDescription": "Total pipeline cost of DSB (uop cache) hits - subset of the Instruction_Fetch_BW Bottleneck.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "d" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "e" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "f" + }, + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "g" + }, + { + "Name": "IDQ.DSB_CYCLES_ANY", + "Alias": "h" + }, + { + "Name": "IDQ.DSB_CYCLES_OK", + "Alias": "i" + }, + { + "Name": "CPU_CLK_UNHALTED.DISTRIBUTED", + "Alias": "j" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "k" + }, + { + "Name": "IDQ.MITE_CYCLES_ANY", + "Alias": "l" + }, + { + "Name": "IDQ.MITE_CYCLES_OK", + "Alias": "m" + }, + { + "Name": "IDQ.MS_CYCLES_ANY", + "Alias": "n" + }, + { + "Name": "UOPS_RETIRED.MS:c1", + "Alias": "o" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "p" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "q" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "100 * ( ( a / ( a + b + c + d ) - e / ( f ) ) * ( ( max( 0 , ( a / ( a + b + c + d ) - e / ( f ) ) - ( ( g / ( a + b + c + d ) - e / ( f ) ) ) ) ) / ( ( ( g / ( a + b + c + d ) - e / ( f ) ) ) + ( max( 0 , ( a / ( a + b + c + d ) - e / ( f ) ) - ( ( g / ( a + b + c + d ) - e / ( f ) ) ) ) ) ) ) * ( ( ( h - i ) / ( j if smt_on else ( k ) ) / 2 ) / ( ( ( l - m ) / ( j if smt_on else ( k ) ) / 2 ) + ( ( h - i ) / ( j if smt_on else ( k ) ) / 2 ) + ( max( n , o / ( p / q ) ) / ( j if smt_on else ( k ) ) / 2.4 ) ) ) )", + "BaseFormula": "100 * ( tma_frontend_bound * ( tma_fetch_bandwidth / ( tma_fetch_latency + tma_fetch_bandwidth ) ) * ( tma_dsb / ( tma_mite + tma_dsb + tma_ms ) ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_DSB_Bandwidth > 10", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "DSB;Fed;FetchBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Botlnk_L2_IC_Misses", + "LegacyName": "metric_TMA_Info_Botlnk_L2_IC_Misses", + "Level": 1, + "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "PERF_METRICS.FETCH_LATENCY", + "Alias": "a" + }, + { + "Name": "PERF_METRICS.FRONTEND_BOUND", + "Alias": "b" + }, + { + "Name": "PERF_METRICS.BAD_SPECULATION", + "Alias": "c" + }, + { + "Name": "PERF_METRICS.RETIRING", + "Alias": "d" + }, + { + "Name": "PERF_METRICS.BACKEND_BOUND", + "Alias": "e" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "f" + }, + { + "Name": "TOPDOWN.SLOTS:perf_metrics", + "Alias": "g" + }, + { + "Name": "ICACHE_DATA.STALLS", + "Alias": "h" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "i" + }, + { + "Name": "ICACHE_TAG.STALLS", + "Alias": "j" + }, + { + "Name": "INT_MISC.CLEAR_RESTEER_CYCLES", + "Alias": "k" + }, + { + "Name": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "Alias": "l" + }, + { + "Name": "UOPS_RETIRED.MS:c1:e1", + "Alias": "m" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "n" + }, + { + "Name": "UOPS_ISSUED.ANY", + "Alias": "o" + }, + { + "Name": "DECODE.LCP", + "Alias": "p" + }, + { + "Name": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "Alias": "q" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a / ( b + c + d + e ) - f / ( g ) ) ) * ( h / ( i ) ) / ( ( h / ( i ) ) + ( j / ( i ) ) + ( k / ( i ) + ( l / ( i ) ) ) + ( ( 3 ) * m / ( n / o ) / ( i ) ) + ( p / ( i ) ) + ( q / ( i ) ) ) )", + "BaseFormula": "100 * ( tma_fetch_latency * tma_icache_misses / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) )", + "Category": "TMA", + "CountDomain": "Scaled_Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Botlnk_L2_IC_Misses" + } + ], + "Formula": "a > 5", + "BaseFormula": "metric_TMA_Info_Botlnk_L2_IC_Misses > 5", + "ThresholdIssues": "$issueFL" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;FetchLat;IcMiss", + "LocateWith": "" + }, + { + "MetricName": "Info_Bad_Spec_IpMispredict", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMispredict", + "Level": 1, + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / br_misp_retired.all_branches", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Bad_Spec_IpMispredict" + } + ], + "Formula": "a < 200", + "BaseFormula": "metric_TMA_Info_Bad_Spec_IpMispredict < 200", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "LocateWith": "" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Cond_Ntaken", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Cond_Ntaken", + "Level": 1, + "BriefDescription": "Instructions per retired Mispredicts for conditional non-taken branches (lower number means higher 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"Name": "BR_MISP_RETIRED.RET", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / br_misp_retired.ret", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Bad_Spec_IpMisp_Ret" + } + ], + "Formula": "a < 500", + "BaseFormula": "metric_TMA_Info_Bad_Spec_IpMisp_Ret < 500", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Bad;BrMispredicts", + "LocateWith": "" + }, + { + "MetricName": "Info_Bad_Spec_IpMisp_Indirect", + "LegacyName": "metric_TMA_Info_Bad_Spec_IpMisp_Indirect", + "Level": 1, + "BriefDescription": "Instructions per retired Mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_MISP_RETIRED.INDIRECT", + "Alias": "b" + } + ], + "Constants": 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"BaseFormula": "1000 * mem_load_retired.l3_miss / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_FB_HPKI", + "LegacyName": "metric_TMA_Info_Memory_FB_HPKI", + "Level": 1, + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.FB_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": "1000 * mem_load_retired.fb_hit / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, 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"Events": [ + { + "Name": "LONGEST_LAT_CACHE.MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": "64 * longest_lat_cache.miss / ( 1000000000 ) / tma_info_system_time", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_L3_Cache_Access_BW", + "LegacyName": "metric_TMA_Info_Memory_L3_Cache_Access_BW", + "Level": 1, + "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS.ALL_REQUESTS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": "64 * offcore_requests.all_requests / ( 1000000000 ) / tma_info_system_time", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_TLB_Page_Walks_Utilization", + "LegacyName": "metric_TMA_Info_Memory_TLB_Page_Walks_Utilization", + "Level": 1, + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_PENDING", + "Alias": "a" + }, + { + "Name": "DTLB_LOAD_MISSES.WALK_PENDING", + "Alias": "b" + }, + { + "Name": "DTLB_STORE_MISSES.WALK_PENDING", + "Alias": "c" + }, + { + "Name": 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"metric_TMA_Info_Memory_TLB_Code_STLB_MPKI", + "Level": 1, + "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": "1000 * itlb_misses.walk_completed / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Fed;MemoryTLB", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_TLB_Load_STLB_MPKI", + "LegacyName": "metric_TMA_Info_Memory_TLB_Load_STLB_MPKI", + "Level": 1, + "BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page 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"LocateWith": "" + }, + { + "MetricName": "Info_Memory_Core_L3_Cache_Fill_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_Core_L3_Cache_Fill_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "LONGEST_LAT_CACHE.MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "BaseFormula": "tma_info_memory_l3_cache_fill_bw", + "Category": "TMA", + "CountDomain": "Core_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Core_L3_Cache_Access_BW_2T", + "LegacyName": "metric_TMA_Info_Memory_Core_L3_Cache_Access_BW_2T", + "Level": 1, + "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS.ALL_REQUESTS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 64 * a / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "BaseFormula": "tma_info_memory_l3_cache_access_bw", + "Category": "TMA", + "CountDomain": "Core_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Core_L2_Evictions_Silent_PKI", + "LegacyName": "metric_TMA_Info_Memory_Core_L2_Evictions_Silent_PKI", + "Level": 1, + "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or 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"BaseFormula": "1000 * l2_lines_out.non_silent / tma_info_inst_mix_instructions", + "Category": "TMA", + "CountDomain": "Core_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "L2Evicts;Mem;Server", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Prefetches_Useless_HWPF", + "LegacyName": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF", + "Level": 1, + "BriefDescription": "Rate of L2 HW prefetched lines that were not used by demand accesses", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "L2_LINES_OUT.USELESS_HWPF", + "Alias": "a" + }, + { + "Name": "L2_LINES_OUT.SILENT", + "Alias": "b" + }, + { + "Name": "L2_LINES_OUT.NON_SILENT", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "a / ( b + c )", + "BaseFormula": "l2_lines_out.useless_hwpf / ( l2_lines_out.silent + l2_lines_out.non_silent )", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF" + } + ], + "Formula": "a > 0.15", + "BaseFormula": "metric_TMA_Info_Memory_Prefetches_Useless_HWPF > 0.15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Prefetches", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Latency_Load_L2_Miss_Latency", + "LegacyName": "metric_TMA_Info_Memory_Latency_Load_L2_Miss_Latency", + "Level": 1, + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "offcore_requests_outstanding.demand_data_rd / offcore_requests.demand_data_rd", + "Category": "TMA", + "CountDomain": "Clocks_Latency", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "LockCont;Memory_Lat;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Latency_Load_L3_Miss_Latency", + "LegacyName": "metric_TMA_Info_Memory_Latency_Load_L3_Miss_Latency", + "Level": 1, + "BriefDescription": "Average Latency for L3 cache miss demand Loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "offcore_requests_outstanding.l3_miss_demand_data_rd / offcore_requests.l3_miss_demand_data_rd", + "Category": "TMA", + "CountDomain": "Clocks_Latency", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_Lat;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Latency_Load_L2_MLP", + "LegacyName": "metric_TMA_Info_Memory_Latency_Load_L2_MLP", + "Level": 1, + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "offcore_requests_outstanding.demand_data_rd / offcore_requests_outstanding.demand_data_rd:c1", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_BW;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Latency_Data_L2_MLP", + "LegacyName": "metric_TMA_Info_Memory_Latency_Data_L2_MLP", + "Level": 1, + "BriefDescription": "Average Parallel L2 cache miss data reads", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "Alias": "a" + }, + { + "Name": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "offcore_requests_outstanding.data_rd / offcore_requests_outstanding.cycles_with_data_rd", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Memory_BW;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Mix_Offcore_Read_Any_PKI", + "LegacyName": "metric_TMA_Info_Memory_Mix_Offcore_Read_Any_PKI", + "Level": 1, + "BriefDescription": "Off-core accesses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.READS_TO_CORE.ANY_RESPONSE", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "BaseFormula": "1000 * ocr.reads_to_core.any_response / tma_info_inst_mix_instructions", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "CacheHits;Offcore;Server", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Mix_Offcore_Read_L3M_PKI", + "LegacyName": "metric_TMA_Info_Memory_Mix_Offcore_Read_L3M_PKI", + "Level": 1, + "BriefDescription": "L3 cache misses per kilo instruction for reads-to-core requests (speculative; including in-core HW prefetches)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.READS_TO_CORE.L3_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "BaseFormula": "1000 * ocr.reads_to_core.l3_miss / tma_info_inst_mix_instructions", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Offcore;Server", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Mix_Offcore_MWrite_Any_PKI", + "LegacyName": "metric_TMA_Info_Memory_Mix_Offcore_MWrite_Any_PKI", + "Level": 1, + "BriefDescription": "Off-core accesses per kilo instruction for modified write requests", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.MODIFIED_WRITE.ANY_RESPONSE", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / ( b )", + "BaseFormula": "1000 * ocr.modified_write.any_response / tma_info_inst_mix_instructions", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Offcore;Server", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Mix_UC_Load_PKI", + "LegacyName": "metric_TMA_Info_Memory_Mix_UC_Load_PKI", + "Level": 1, + "BriefDescription": "Un-cacheable retired load per kilo instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_LOAD_MISC_RETIRED.UC", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": "1000 * mem_load_misc_retired.uc / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_Mix_Bus_Lock_PKI", + "LegacyName": "metric_TMA_Info_Memory_Mix_Bus_Lock_PKI", + "Level": 1, + "BriefDescription": "\"Bus lock\" per kilo instruction", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "SQ_MISC.BUS_LOCK", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": "1000 * sq_misc.bus_lock / inst_retired.any", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem", + "LocateWith": "" + }, + { + "MetricName": "Info_System_CPU_Utilization", + "LegacyName": "metric_TMA_Info_System_CPU_Utilization", + "Level": 1, + "BriefDescription": "Average CPU Utilization (percentage)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "b" + }, + { + "Name": "system.sockets[0].cpus.count * system.socket_count", + "Alias": "c" + } + ], + "Formula": "( a / b ) / c", + "BaseFormula": "tma_info_system_cpus_utilized / num_cpus", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Summary", + "LocateWith": "" + }, + { + "MetricName": "Info_System_CPUs_Utilized", + "LegacyName": "metric_TMA_Info_System_CPUs_Utilized", + "Level": 1, + "BriefDescription": "Average number of utilized CPUs", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "b" + } + ], + "Formula": "a / b", + "BaseFormula": "cpu_clk_unhalted.ref_tsc / tsc", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SYSTEM", + "MetricGroup": "Summary", + "LocateWith": "" + }, + { + "MetricName": "Info_System_Core_Frequency", + "LegacyName": "metric_TMA_Info_System_Core_Frequency", + "Level": 1, + "BriefDescription": "Measured Average Core Frequency for unhalted processors [GHz]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + }, + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( a ) / b ) * c / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": "tma_info_system_turbo_utilization * tsc / ( 1000000000 ) / tma_info_system_time", + "Category": "TMA", + "CountDomain": "System_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Summary;Power", + "LocateWith": "" + }, + { + "MetricName": "Info_System_Uncore_Frequency", + "LegacyName": "metric_TMA_Info_System_Uncore_Frequency", + "Level": 1, + "BriefDescription": "Measured Average Uncore Frequency for the SoC [GHz]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a ) / 1e9 / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": "tma_info_system_socket_clks / 1e9 / tma_info_system_time", + "Category": "TMA", + "CountDomain": "System_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "SoC", + "LocateWith": "" + }, + { + "MetricName": "Info_System_GFLOPs", + "LegacyName": "metric_TMA_Info_System_GFLOPs", + "Level": 1, + "BriefDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_ARITH_INST_RETIRED.SCALAR", + "Alias": "a" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", + "Alias": "b" + }, + { + "Name": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "Alias": "c" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", + "Alias": "d" + }, + { + "Name": "FP_ARITH_INST_RETIRED.4_FLOPS", + "Alias": "e" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", + "Alias": "f" + }, + { + "Name": "FP_ARITH_INST_RETIRED.8_FLOPS", + "Alias": "g" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", + "Alias": "h" + }, + { + "Name": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "Alias": "i" + }, + { + "Name": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", + "Alias": "j" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( ( ( 1 * ( a + b ) + 2 * ( c + d ) + 4 * e + 8 * ( f + g ) + 16 * ( h + i ) + 32 * j ) ) / ( 1000000000 ) ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": "( ( ( 1 * ( fp_arith_inst_retired.scalar + fp_arith_inst_retired2.scalar_half ) + 2 * ( fp_arith_inst_retired.128b_packed_double + fp_arith_inst_retired2.complex_scalar_half ) + 4 * fp_arith_inst_retired.4_flops + 8 * ( fp_arith_inst_retired2.128b_packed_half + fp_arith_inst_retired.8_flops ) + 16 * ( fp_arith_inst_retired2.256b_packed_half + fp_arith_inst_retired.512b_packed_single ) + 32 * fp_arith_inst_retired2.512b_packed_half ) ) / ( 1000000000 ) ) / tma_info_system_time", + "Category": "TMA", + "CountDomain": "Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Cor;Flops;HPC", + "LocateWith": "" + }, + { + "MetricName": "Info_System_Turbo_Utilization", + "LegacyName": "metric_TMA_Info_System_Turbo_Utilization", + "Level": 1, + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "BaseFormula": "tma_info_thread_clks / cpu_clk_unhalted.ref_tsc", + "Category": "TMA", + "CountDomain": "Core_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Power", + "LocateWith": "" + }, + { + "MetricName": "Info_System_SMT_2T_Utilization", + "LegacyName": "metric_TMA_Info_System_SMT_2T_Utilization", + "Level": 1, + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "HYPERTHREADING_ON", + "Alias": "smt_on" + }, + { + "Name": "THREADS_PER_CORE", + "Alias": "threads" + } + ], + "Formula": "1 - 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Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( 1000000000 ) * ( a / b ) / ( ( c ) / ( ( durationtimeinmilliseconds / 1000 ) ) )", + "BaseFormula": "( 1000000000 ) * ( unc_cha_tor_occupancy.ia_miss_drd / unc_cha_tor_inserts.ia_miss_drd ) / ( tma_info_system_socket_clks / tma_info_system_time )", + "Category": "TMA", + "CountDomain": "NanoSeconds", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryLat;SoC", + "LocateWith": "" + }, + { + "MetricName": "Info_System_MEM_Parallel_Reads", + "LegacyName": "metric_TMA_Info_System_MEM_Parallel_Reads", + "Level": 1, + "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD:c1", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "unc_cha_tor_occupancy.ia_miss_drd / unc_cha_tor_occupancy.ia_miss_drd:c1", + "Category": "TMA", + "CountDomain": "System_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Mem;MemoryBW;SoC", + "LocateWith": "" + }, + { + "MetricName": "Info_System_MEM_DRAM_Read_Latency", + "LegacyName": "metric_TMA_Info_System_MEM_DRAM_Read_Latency", + "Level": 1, + "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "( 1000000000 ) * ( a / b ) / c", + "BaseFormula": "( 1000000000 ) * ( unc_cha_tor_occupancy.ia_miss_drd_ddr / unc_cha_tor_inserts.ia_miss_drd_ddr ) / unc_cha_clockticks:one_unit", + "Category": "TMA", + "CountDomain": "NanoSeconds", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "MemOffcore;MemoryLat;SoC;Server", + "LocateWith": "" + }, + { + "MetricName": "Info_System_IO_Read_BW", + "LegacyName": "metric_TMA_Info_System_IO_Read_BW", + "Level": 1, + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]. Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "a * 64 / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": "unc_cha_tor_inserts.io_pcirdcur * 64 / ( 1000000000 ) / tma_info_system_time", + "Category": "TMA", + "CountDomain": "GB/sec", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "IoBW;MemOffcore;SoC;Server", + "LocateWith": "" + }, + { + "MetricName": "Info_System_IO_Write_BW", + "LegacyName": "metric_TMA_Info_System_IO_Write_BW", + "Level": 1, + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]. Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a + b ) * 64 / ( 1000000000 ) / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": "( unc_cha_tor_inserts.io_itom + unc_cha_tor_inserts.io_itomcachenear ) * 64 / ( 1000000000 ) / tma_info_system_time", + "Category": "TMA", + "CountDomain": "GB/sec", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "IoBW;MemOffcore;SoC;Server", + "LocateWith": "" + }, + { + "MetricName": "Info_System_UPI_Data_Transmit_BW", + "LegacyName": "metric_TMA_Info_System_UPI_Data_Transmit_BW", + "Level": 1, + "BriefDescription": "Cross-socket Ultra Path Interconnect (UPI) data transmit bandwidth for data only [MB / sec]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_UPI_TxL_FLITS.ALL_DATA", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a * 64 / 9 / 1000000", + "BaseFormula": "unc_upi_txl_flits.all_data * 64 / 9 / 1000000", + "Category": "TMA", + "CountDomain": "MB/sec", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "UPI, SOCKET, SYSTEM", + "MetricGroup": "SoC;Server", + "LocateWith": "" + }, + { + "MetricName": "Info_System_Power", + "LegacyName": "metric_TMA_Info_System_Power", + "Level": 1, + "BriefDescription": "Total package Power in Watts", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FREERUN_PKG_ENERGY_STATUS", + "Alias": "a" + }, + { + "Name": "FREERUN_DRAM_ENERGY_STATUS", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( a * ( 61 ) + 15.6 * b ) / ( ( durationtimeinmilliseconds / 1000 ) * ( 1000000 ) )", + "BaseFormula": "( freerun_pkg_energy_status * ( 61 ) + 15.6 * freerun_dram_energy_status ) / ( ( duration_time ) * ( 1000000 ) )", + "Category": "TMA", + "CountDomain": "System_Metric", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Power;SoC", + "LocateWith": "" + }, + { + "MetricName": "Info_System_Time", + "LegacyName": "metric_TMA_Info_System_Time", + "Level": 1, + "BriefDescription": "Run duration time in seconds", + "UnitOfMeasure": "", + "Events": [], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "( durationtimeinmilliseconds / 1000 )", + "BaseFormula": "duration_time", + "Category": "TMA", + "CountDomain": "Seconds", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_System_Time" + } + ], + "Formula": "a < 1", + "BaseFormula": "metric_TMA_Info_System_Time < 1", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "Summary", + "LocateWith": "" + }, + { + "MetricName": "Info_System_MUX", + "LegacyName": "metric_TMA_Info_System_MUX", + "Level": 1, + "BriefDescription": "PerfMon Event Multiplexing accuracy indicator", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "cpu_clk_unhalted.thread_p / cpu_clk_unhalted.thread", + "Category": "TMA", + "CountDomain": "Clocks", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_System_MUX" + } + ], + "Formula": "a > 1.1 | a < 0.9", + "BaseFormula": "metric_TMA_Info_System_MUX > 1.1 | metric_TMA_Info_System_MUX < 0.9", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Summary", + "LocateWith": "" + }, + { + "MetricName": "Info_System_Socket_CLKS", + "LegacyName": "metric_TMA_Info_System_Socket_CLKS", + "Level": 1, + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_CHA_CLOCKTICKS:one_unit", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "a", + "BaseFormula": "unc_cha_clockticks:one_unit", + "Category": "TMA", + "CountDomain": "Count", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "SoC", + "LocateWith": "" + }, + { + "MetricName": "Info_System_IpFarBranch", + "LegacyName": "metric_TMA_Info_System_IpFarBranch", + "Level": 1, + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.FAR_BRANCH:USER", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": "inst_retired.any / br_inst_retired.far_branch:user", + "Category": "TMA", + "CountDomain": "Inst_Metric", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Info_System_IpFarBranch" + } + ], + "Formula": "a < 1000000", + "BaseFormula": "metric_TMA_Info_System_IpFarBranch < 1000000", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;OS", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_SoC_R2C_Offcore_BW", + "LegacyName": "metric_TMA_Info_Memory_SoC_R2C_Offcore_BW", + "Level": 1, + "BriefDescription": "Average Off-core access BW for Reads-to-Core (R2C). R2C account for demand or prefetch load/RFO/code access that fill data into the Core caches.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.READS_TO_CORE.ANY_RESPONSE", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / 1e9 / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": "64 * ocr.reads_to_core.any_response / 1e9 / tma_info_system_time", + "Category": "TMA", + "CountDomain": "GB/sec", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Mem;MemoryBW;Server;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_SoC_R2C_L3M_BW", + "LegacyName": "metric_TMA_Info_Memory_SoC_R2C_L3M_BW", + "Level": 1, + "BriefDescription": "Average L3-cache miss BW for Reads-to-Core (R2C). This covering going to DRAM or other memory off-chip memory tears. See R2C_Offcore_BW.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.READS_TO_CORE.L3_MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / 1e9 / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": "64 * ocr.reads_to_core.l3_miss / 1e9 / tma_info_system_time", + "Category": "TMA", + "CountDomain": "GB/sec", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Mem;MemoryBW;Server;Offcore", + "LocateWith": "" + }, + { + "MetricName": "Info_Memory_SoC_R2C_DRAM_BW", + "LegacyName": "metric_TMA_Info_Memory_SoC_R2C_DRAM_BW", + "Level": 1, + "BriefDescription": "Average DRAM BW for Reads-to-Core (R2C) covering for memory attached to local- and remote-socket. See R2C_Offcore_BW.", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "OCR.READS_TO_CORE.DRAM", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "64 * a / 1e9 / ( ( durationtimeinmilliseconds / 1000 ) )", + "BaseFormula": "64 * ocr.reads_to_core.dram / 1e9 / tma_info_system_time", + "Category": "TMA", + "CountDomain": "GB/sec", + "Threshold": { + "Formula": "", + "BaseFormula": "", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "HPC;Mem;MemoryBW;Server;Offcore", + "LocateWith": "" + } + ] +} \ No newline at end of file diff --git a/cmd/metrics/resources/perfmon/spr/sapphirerapids_uncore.json b/cmd/metrics/resources/perfmon/spr/sapphirerapids_uncore.json new file mode 100644 index 00000000..dade6044 --- /dev/null +++ b/cmd/metrics/resources/perfmon/spr/sapphirerapids_uncore.json @@ -0,0 +1,5177 @@ +{ + "Header": { + "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture - V1.30", + "DatePublished": "07/03/2025", + "Version": "1.30", + "Legend": "" + }, + "Events": [ + { + "Unit": "PCU", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_P_CLOCKTICKS", + "BriefDescription": "PCU PCLK Clockticks", + "PublicDescription": "Number of PCU PCLK Clock cycles while the event is enabled", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_CLOCKTICKS", + "BriefDescription": "IRP Clockticks", + "PublicDescription": "Number of IRP clock cycles while the event is enabled", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x16", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_FAF_TRANSACTIONS", + "BriefDescription": "FAF allocation -- sent to ADQ", + "PublicDescription": "FAF allocation -- sent to ADQ", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x17", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_FAF_FULL", + "BriefDescription": "FAF RF full", + "PublicDescription": "FAF RF full", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x18", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_FAF_INSERTS", + "BriefDescription": "FAF - request insert from TC.", + "PublicDescription": "FAF - request insert from TC.", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x19", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_FAF_OCCUPANCY", + "BriefDescription": "FAF occupancy", + "PublicDescription": "FAF occupancy", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x1f", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_MISC1.LOST_FWD", + "BriefDescription": "Misc Events - Set 1 : Lost Forward", + "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x20", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", + "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)", + "PublicDescription": ": All Inserts Inbound (p2p + faf + cset)", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2PCIe", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M2P_CLOCKTICKS", + "BriefDescription": "M2P Clockticks", + "PublicDescription": "Number of M2P clock cycles while the event is enabled", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2PCIe", + "EventCode": "0xc0", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M2P_CMS_CLOCKTICKS", + "BriefDescription": "CMS Clockticks", + "PublicDescription": "CMS Clockticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x0000", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_CLOCKTICKS", + "BriefDescription": "IIO Clockticks", + "PublicDescription": "Number of IIO clock cycles while the event is enabled", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x0001", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "BriefDescription": "Write request of 4 bytes made by IIO Part0 to Memory", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x0002", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "BriefDescription": "Write request of 4 bytes made by IIO Part1 to Memory", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x0004", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "BriefDescription": "Write request of 4 bytes made by IIO Part2 to Memory", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x0008", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "BriefDescription": "Write request of 4 bytes made by IIO Part3 to Memory", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x0001", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "BriefDescription": "Read request for 4 bytes made by IIO Part0 to Memory", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x0002", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "BriefDescription": "Read request for 4 bytes made by IIO Part1 to Memory", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x0004", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "BriefDescription": "Read request for 4 bytes made by IIO Part2 to Memory", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x0008", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "BriefDescription": "Read request for 4 bytes made by IIO Part3 to Memory", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x0010", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", + "BriefDescription": "Data requested of the CPU : Card writing to DRAM", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x0020", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", + "BriefDescription": "Data requested of the CPU : Card writing to DRAM", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x0040", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", + "BriefDescription": "Data requested of the CPU : Card writing to DRAM", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x0080", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", + "BriefDescription": "Data requested of the CPU : Card writing to DRAM", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x0010", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", + "BriefDescription": "Data requested of the CPU : Card reading from DRAM", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x0020", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", + "BriefDescription": "Data requested of the CPU : Card reading from DRAM", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x0040", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", + "BriefDescription": "Data requested of the CPU : Card reading from DRAM", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x0080", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", + "BriefDescription": "Data requested of the CPU : Card reading from DRAM", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x0001", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", + "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part0 to Memory", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x0002", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", + "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part1 to Memory", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x0004", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", + "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part2 to Memory", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x0008", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", + "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part3 to Memory", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x0001", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", + "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part0 to Memory", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x0002", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", + "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part1 to Memory", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x0004", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", + "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part2 to Memory", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x0008", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", + "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part3 to Memory", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x0010", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x0020", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x0040", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x0080", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x0010", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x0020", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x0040", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x0080", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x01", + "PortMask": "0x0001", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", + "BriefDescription": "Write request of 4 bytes made to IIO Part0 by the CPU", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x01", + "PortMask": "0x0002", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", + "BriefDescription": "Write request of 4 bytes made to IIO Part1 by the CPU", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x01", + "PortMask": "0x0004", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", + "BriefDescription": "Write request of 4 bytes made to IIO Part2 by the CPU", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x01", + "PortMask": "0x0008", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", + "BriefDescription": "Write request of 4 bytes made to IIO Part3 by the CPU", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x04", + "PortMask": "0x0001", + "FCMask": "0x07", + "UMaskExt": "0x00070010", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0", + "PublicDescription": "Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x04", + "PortMask": "0x0002", + "FCMask": "0x07", + "UMaskExt": "0x00070020", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part1", + "PublicDescription": "Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x04", + "PortMask": "0x0004", + "FCMask": "0x07", + "UMaskExt": "0x00070040", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part2", + "PublicDescription": "Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x04", + "PortMask": "0x0008", + "FCMask": "0x07", + "UMaskExt": "0x00070080", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part3", + "PublicDescription": "Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x01", + "PortMask": "0x0010", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4", + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x01", + "PortMask": "0x0020", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5", + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x01", + "PortMask": "0x0040", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6", + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x01", + "PortMask": "0x0080", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7", + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x04", + "PortMask": "0x0010", + "FCMask": "0x07", + "UMaskExt": "0x00070100", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4", + "BriefDescription": "Data requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x04", + "PortMask": "0x0020", + "FCMask": "0x07", + "UMaskExt": "0x00070200", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5", + "BriefDescription": "Data requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x04", + "PortMask": "0x0040", + "FCMask": "0x07", + "UMaskExt": "0x00070400", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6", + "BriefDescription": "Data requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc0", + "UMask": "0x04", + "PortMask": "0x0080", + "FCMask": "0x07", + "UMaskExt": "0x00070800", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7", + "BriefDescription": "Data requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x01", + "PortMask": "0x0001", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", + "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x01", + "PortMask": "0x0002", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", + "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x01", + "PortMask": "0x0004", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", + "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x01", + "PortMask": "0x0008", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", + "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x04", + "PortMask": "0x0001", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", + "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part0", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x04", + "PortMask": "0x0002", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", + "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part1", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x04", + "PortMask": "0x0004", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", + "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part2", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x04", + "PortMask": "0x0008", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", + "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part3", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x01", + "PortMask": "0x0010", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x01", + "PortMask": "0x0020", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x01", + "PortMask": "0x0040", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x01", + "PortMask": "0x0080", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x04", + "PortMask": "0x0010", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x04", + "PortMask": "0x0020", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x04", + "PortMask": "0x0040", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xc1", + "UMask": "0x04", + "PortMask": "0x0080", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x01", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CLOCKTICKS", + "BriefDescription": "IMC Clockticks at DCLK frequency", + "PublicDescription": "Number of DRAM DCLK clock cycles while the event is enabled", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_HCLOCKTICKS", + "BriefDescription": "IMC Clockticks at HCLK frequency", + "PublicDescription": "Number of DRAM HCLK clock cycles while the event is enabled", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x02", + "UMask": "0xff", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_ACT_COUNT.ALL", + "BriefDescription": "Activate due to read, write, underfill, or bypass", + "PublicDescription": "DRAM Activate Count : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x03", + "UMask": "0x11", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_PRE_COUNT.RD", + "BriefDescription": "Precharge due to read on page miss", + "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x03", + "UMask": "0x22", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_PRE_COUNT.WR", + "BriefDescription": "Precharge due to write on page miss", + "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x03", + "UMask": "0x88", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_PRE_COUNT.PGT", + "BriefDescription": "DRAM Precharge commands", + "PublicDescription": "DRAM Precharge commands. Counts the number of DRAM Precharge commands sent on this channel.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x03", + "UMask": "0xff", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_PRE_COUNT.ALL", + "BriefDescription": "Precharge due to read, write, underfill, or PGT.", + "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x05", + "UMask": "0xcf", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT.RD", + "BriefDescription": "All DRAM read CAS commands issued (including underfills)", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM Read CAS commands issued on this channel. This includes underfills.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x05", + "UMask": "0xf0", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT.WR", + "BriefDescription": "All DRAM write CAS commands issued", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM Write CAS commands issued on this channel.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x05", + "UMask": "0xff", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT.ALL", + "BriefDescription": "All DRAM CAS commands issued", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : All DRAM Read and Write actions : DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM CAS commands issued on this channel.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x10", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_INSERTS.PCH0", + "BriefDescription": "Read Pending Queue Allocations", + "PublicDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x10", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_INSERTS.PCH1", + "BriefDescription": "Read Pending Queue Allocations", + "PublicDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x20", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_INSERTS.PCH0", + "BriefDescription": "Write Pending Queue Allocations", + "PublicDescription": "Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x20", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_INSERTS.PCH1", + "BriefDescription": "Write Pending Queue Allocations", + "PublicDescription": "Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x80", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0", + "BriefDescription": "Read Pending Queue Occupancy", + "PublicDescription": "Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x81", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1", + "BriefDescription": "Read Pending Queue Occupancy", + "PublicDescription": "Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x82", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0", + "BriefDescription": "Write Pending Queue Occupancy", + "PublicDescription": "Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x83", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1", + "BriefDescription": "Write Pending Queue Occupancy", + "PublicDescription": "Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xd3", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_TAGCHK.HIT", + "BriefDescription": "2LM Tag check hit in near memory cache (DDR4)", + "PublicDescription": "2LM Tag check hit in near memory cache (DDR4)", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xd3", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_TAGCHK.MISS_CLEAN", + "BriefDescription": "2LM Tag check miss, no data at this line", + "PublicDescription": "2LM Tag check miss, no data at this line", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xd3", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_TAGCHK.MISS_DIRTY", + "BriefDescription": "2LM Tag check miss, existing data may be evicted to PMM", + "PublicDescription": "2LM Tag check miss, existing data may be evicted to PMM", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xd3", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_TAGCHK.NM_RD_HIT", + "BriefDescription": "2LM Tag check hit due to memory read", + "PublicDescription": "2LM Tag check hit due to memory read", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xd3", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_TAGCHK.NM_WR_HIT", + "BriefDescription": "2LM Tag check hit due to memory write", + "PublicDescription": "2LM Tag check hit due to memory write", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M2M_CLOCKTICKS", + "BriefDescription": "M2M Clockticks", + "PublicDescription": "Clockticks of the mesh to memory (M2M)", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x20", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY", + "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)", + "PublicDescription": "Counts the number of hit data returns to egress with any directory to non persistent memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x20", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A", + "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)", + "PublicDescription": "Counts the number of hit data returns to egress with directory A to non persistent memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x20", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I", + "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)", + "PublicDescription": "Counts the number of hit data returns to egress with directory I to non persistent memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x20", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S", + "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)", + "PublicDescription": "Counts the number of hit data returns to egress with directory S to non persistent memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x21", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x03", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY", + "BriefDescription": "Multi-socket cacheline Directory update from/to Any state", + "PublicDescription": "Multi-socket cacheline Directory update from/to Any state", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0xc0", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x800000", + "EventName": "UNC_M2M_CMS_CLOCKTICKS", + "BriefDescription": "CMS Clockticks", + "PublicDescription": "CMS Clockticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M3UPI", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M3UPI_CLOCKTICKS", + "BriefDescription": "M3UPI Clockticks", + "PublicDescription": "Number of M2UPI clock cycles while the event is enabled", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_CLOCKTICKS", + "BriefDescription": "UPI Clockticks", + "PublicDescription": "Number of UPI LL clock cycles while the event is enabled", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x02", + "UMask": "0x0f", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", + "BriefDescription": "Valid Flits Sent : All Data", + "PublicDescription": "Valid Flits Sent : All Data : Counts number of data flits across this UPI link.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x02", + "UMask": "0x97", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", + "BriefDescription": "Valid Flits Sent : All Non Data", + "PublicDescription": "Valid Flits Sent : All Non Data : Shows legal flit time (hides impact of L0p and L0c).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x02", + "UMask": "0x27", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", + "BriefDescription": "All Null Flits", + "PublicDescription": "All Null Flits", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x03", + "UMask": "0x0f", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", + "BriefDescription": "Valid Flits Received : All Data", + "PublicDescription": "Valid Flits Received : All Data : Shows legal flit time (hides impact of L0p and L0c).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x03", + "UMask": "0x97", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", + "BriefDescription": "Valid Flits Received : All Non Data", + "PublicDescription": "Valid Flits Received : All Non Data : Shows legal flit time (hides impact of L0p and L0c).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x03", + "UMask": "0x27", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", + "BriefDescription": "Null FLITs received from any slot", + "PublicDescription": "Null FLITs received from any slot", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x21", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_L1_POWER_CYCLES", + "BriefDescription": "Cycles in L1", + "PublicDescription": "Cycles in L1 : Number of UPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a UPI link. Use edge detect to count the number of instances when the UPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", + "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data", + "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x20", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE", + "BriefDescription": "Remote requests for exclusive ownership of a cache line without receiving data", + "PublicDescription": "Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", + "BriefDescription": "Read requests from a unit on this socket", + "PublicDescription": "Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.READS_REMOTE", + "BriefDescription": "Read requests from a remote socket", + "PublicDescription": "Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL", + "BriefDescription": "Write Requests from a unit on this socket", + "PublicDescription": "Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", + "BriefDescription": "Read and Write Requests; Writes Remote", + "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x03", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.READS", + "BriefDescription": "Read requests made into the CHA", + "PublicDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) .", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x0c", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.WRITES", + "BriefDescription": "Write requests made into the CHA", + "PublicDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x54", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_DIR_UPDATE.HA", + "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe", + "PublicDescription": "Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x54", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_DIR_UPDATE.TOR", + "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe", + "PublicDescription": "Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x59", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", + "BriefDescription": "Normal priority reads issued to the memory controller from the CHA", + "PublicDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x5b", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", + "BriefDescription": "CHA to iMC Full Line Writes Issued; Full Line Non-ISOCH", + "PublicDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channels.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0xc0", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_CMS_CLOCKTICKS", + "BriefDescription": "CMS Clockticks", + "PublicDescription": "CMS Clockticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_CLOCKTICKS", + "BriefDescription": "CHA Clockticks", + "PublicDescription": "Number of CHA clock cycles while the event is enabled", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c001ff", + "EventName": "UNC_CHA_TOR_INSERTS.IA", + "BriefDescription": "TOR Inserts; All from Local IA", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests from IA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c001fd", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", + "BriefDescription": "TOR Inserts; Hits from Local IA", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c80ffd", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", + "BriefDescription": "TOR Inserts; CRd hits from local IA", + "PublicDescription": "TOR Inserts; Code read from local IA that hits in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c817fd", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD", + "BriefDescription": "TOR Inserts; DRd hits from local IA", + "PublicDescription": "TOR Inserts; Data read from local IA that hits in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00ccc7fd", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO", + "BriefDescription": "TOR Inserts; LLCPrefRFO hits from local IA", + "PublicDescription": "TOR Inserts; Last level cache prefetch read for ownership from local IA that hits in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c807fd", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", + "BriefDescription": "TOR Inserts; RFO hits from local IA", + "PublicDescription": "TOR Inserts; Read for ownership from local IA that hits in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c001fe", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", + "BriefDescription": "TOR Inserts; misses from Local IA", + "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c80ffe", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "BriefDescription": "TOR Inserts for CRd misses from local IA", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode CRd", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c817fe", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "BriefDescription": "TOR Inserts for DRd misses from local IA", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00ccc7fe", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO", + "BriefDescription": "TOR Inserts; LLCPrefRFO misses from local IA", + "PublicDescription": "TOR Inserts; Last level cache prefetch read for ownership from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c807fe", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", + "BriefDescription": "TOR Inserts; RFO misses from local IA", + "PublicDescription": "TOR Inserts; Read for ownership from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c001ff", + "EventName": "UNC_CHA_TOR_INSERTS.IO", + "BriefDescription": "TOR Inserts; All from local IO", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c001fd", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", + "BriefDescription": "TOR Inserts; Hits from local IO", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c001fe", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", + "BriefDescription": "TOR Inserts; Misses from local IO", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00cc43fe", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "BriefDescription": "TOR Inserts : ItoM, indicating a full cacheline write request, from IO Devices that missed the LLC", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c803fe", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "BriefDescription": "TOR Inserts; RFO misses from local IO", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c88ffd", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF", + "BriefDescription": "TOR Inserts; CRd Pref hits from local IA", + "PublicDescription": "TOR Inserts; Code read prefetch from local IA that hits in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c897fd", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF", + "BriefDescription": "TOR Inserts; DRd Pref hits from local IA", + "PublicDescription": "TOR Inserts; Data read prefetch from local IA that hits in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c887fd", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF", + "BriefDescription": "TOR Inserts; RFO Pref hits from local IA", + "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that hits in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c88ffe", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", + "BriefDescription": "TOR Inserts; CRd Pref misses from local IA", + "PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c897fe", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF", + "BriefDescription": "TOR Inserts for DRd Pref misses from local IA", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c887fe", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", + "BriefDescription": "TOR Inserts; RFO pref misses from local IA", + "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00cc43fd", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", + "BriefDescription": "TOR Inserts; ItoM hits from local IO", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c803fd", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO", + "BriefDescription": "TOR Inserts; RFO hits from local IO", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c803ff", + "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO", + "BriefDescription": "TOR Inserts; RFO from local IO", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00cc43ff", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "BriefDescription": "TOR Inserts for ItoM from local IO", + "PublicDescription": "Inserts into the TOR from local IO with the opcode ItoM", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c887ff", + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF", + "BriefDescription": "TOR Inserts; RFO pref from local IA", + "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c807ff", + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO", + "BriefDescription": "TOR Inserts; RFO from local IA", + "PublicDescription": "TOR Inserts; Read for ownership from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00ccc7ff", + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO", + "BriefDescription": "TOR Inserts; LLCPrefRFO from local IA", + "PublicDescription": "TOR Inserts; Last level cache prefetch read for ownership from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c817ff", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD", + "BriefDescription": "TOR Inserts; DRd from local IA", + "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c897ff", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF", + "BriefDescription": "TOR Inserts; DRd Pref from local IA", + "PublicDescription": "TOR Inserts; Data read prefetch from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c80fff", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD", + "BriefDescription": "TOR Inserts; CRd from local IA", + "PublicDescription": "TOR Inserts; Code read from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c816fe", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", + "BriefDescription": "TOR Inserts for DRd misses from local IA targeting local memory", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target local memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8177e", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", + "BriefDescription": "TOR Inserts for DRd misses from local IA targeting remote memory", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and target remote memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C896FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL", + "BriefDescription": "TOR Inserts for DRd Pref misses from local IA targeting local memory", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target local memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8977E", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE", + "BriefDescription": "TOR Inserts for DRd Pref misses from local IA targeting remote memory", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target remote memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c806fe", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL", + "BriefDescription": "TOR Inserts RFO misses from local IA", + "PublicDescription": "TOR Inserts; Read for ownership from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8077e", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE", + "BriefDescription": "TOR Inserts; RFO misses from local IA", + "PublicDescription": "TOR Inserts Read for ownership from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c886fe", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL", + "BriefDescription": "TOR Inserts; RFO prefetch misses from local IA", + "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8877e", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE", + "BriefDescription": "TOR Inserts; RFO prefetch misses from local IA", + "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8c7ff", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH", + "BriefDescription": "TOR Inserts;CLFlush from Local IA", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; CLFlush events that are initiated from the Core", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00cc57ff", + "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM", + "BriefDescription": "TOR Inserts;SpecItoM from Local IA", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; SpecItoM events that are initiated from the Core", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c001ff", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", + "BriefDescription": "TOR Occupancy; All from local IA", + "PublicDescription": "TOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c001fd", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", + "BriefDescription": "TOR Occupancy; Hits from local IA", + "PublicDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c80ffd", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", + "BriefDescription": "TOR Occupancy; CRd hits from local IA", + "PublicDescription": "TOR Occupancy; Code read from local IA that hits in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c817fd", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", + "BriefDescription": "TOR Occupancy; DRd hits from local IA", + "PublicDescription": "TOR Occupancy; Data read from local IA that hits in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00ccc7fd", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO", + "BriefDescription": "TOR Occupancy; LLCPrefRFO hits from local IA", + "PublicDescription": "TOR Occupancy; Last level cache prefetch read for ownership from local IA that hits in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c807fd", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "BriefDescription": "TOR Occupancy; RFO hits from local IA", + "PublicDescription": "TOR Occupancy; Read for ownership from local IA that hits in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c001fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", + "BriefDescription": "TOR Occupancy; Misses from Local IA", + "PublicDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c80ffe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", + "BriefDescription": "TOR Occupancy; CRd misses from local IA", + "PublicDescription": "TOR Occupancy; Code read from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c817fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "BriefDescription": "TOR Occupancy for DRd misses from local IA", + "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00ccc7fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO", + "BriefDescription": "TOR Occupancy; LLCPrefRFO misses from local IA", + "PublicDescription": "TOR Occupancy; Last level cache prefetch read for ownership from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c807fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", + "BriefDescription": "TOR Occupancy; RFO misses from local IA", + "PublicDescription": "TOR Occupancy; Read for ownership from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c001ff", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", + "BriefDescription": "TOR Occupancy; All from local IO", + "PublicDescription": "TOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c001fd", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", + "BriefDescription": "TOR Occupancy; Hits from local IO", + "PublicDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c001fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", + "BriefDescription": "TOR Occupancy; Misses from local IO", + "PublicDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00cc43fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", + "BriefDescription": "TOR Occupancy; ITOM misses from local IO", + "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c88ffd", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF", + "BriefDescription": "TOR Occupancy; CRd Pref hits from local IA", + "PublicDescription": "TOR Occupancy; Code read prefetch from local IA that hits in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c897fd", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_PREF", + "BriefDescription": "TOR Occupancy; DRd Pref hits from local IA", + "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that hits in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c887fd", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF", + "BriefDescription": "TOR Occupancy; RFO Pref hits from local IA", + "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that hits in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c897fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF", + "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA", + "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c887fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF", + "BriefDescription": "TOR Occupancy; RFO prefetch misses from local IA", + "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00cc43fd", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM", + "BriefDescription": "TOR Occupancy; ITOM hits from local IO", + "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00cc43ff", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM", + "BriefDescription": "TOR Occupancy; ITOM from local IO", + "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c807ff", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO", + "BriefDescription": "TOR Occupancy; RFO from local IA", + "PublicDescription": "TOR Occupancy; Read for ownership from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c887ff", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF", + "BriefDescription": "TOR Occupancy; RFO prefetch from local IA", + "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00ccc7ff", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO", + "BriefDescription": "TOR Occupancy; LLCPrefRFO from local IA", + "PublicDescription": "TOR Occupancy; Last level cache prefetch read for ownership from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c817ff", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD", + "BriefDescription": "TOR Occupancy; DRd from local IA", + "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c80fff", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD", + "BriefDescription": "TOR Occupancy; CRd from local IA", + "PublicDescription": "TOR Occupancy; Code read from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c897ff", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_PREF", + "BriefDescription": "TOR Occupancy; DRd Pref from local IA", + "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c816fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL", + "BriefDescription": "TOR Occupancy for DRd misses from local IA targeting local memory", + "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target local memory", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8177e", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE", + "BriefDescription": "TOR Occupancy for DRd misses from local IA targeting remote memory", + "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target remote memory", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8977E", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE", + "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA", + "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c806fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL", + "BriefDescription": "TOR Occupancy; RFO misses from local IA", + "PublicDescription": "TOR Occupancy; Read for ownership from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8077e", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_REMOTE", + "BriefDescription": "TOR Occupancy; RFO misses from local IA", + "PublicDescription": "TOR Occupancy; Read for ownership from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c886fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL", + "BriefDescription": "TOR Occupancy; RFO prefetch misses from local IA", + "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8877e", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE", + "BriefDescription": "TOR Occupancy; RFO prefetch misses from local IA", + "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8178a", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM", + "BriefDescription": "TOR Inserts for DRds issued by iA Cores targeting PMM Mem that Missed the LLC", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target PMM memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c81786", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", + "BriefDescription": "TOR Inserts for DRds issued by IA Cores targeting DDR Mem that Missed the LLC", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target DDR memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00cd43fd", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00cd43fe", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c81786", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR", + "BriefDescription": "TOR Occupancy for DRds issued by iA Cores targeting DDR Mem that Missed the LLC", + "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target DDR memory", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8178a", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM", + "BriefDescription": "TOR Occupancy for DRds issued by iA Cores targeting PMM Mem that Missed the LLC", + "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target PMM memory", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8f3fd", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR", + "BriefDescription": "TOR Inserts; RdCur and FsRdCur hits from local IO", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x24", + "UMask": "0x20", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000003", + "EventName": "UNC_M2M_IMC_READS.TO_PMM", + "BriefDescription": "UNC_M2M_IMC_READS.TO_PMM", + "PublicDescription": "UNC_M2M_IMC_READS.TO_PMM", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8f3fe", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "BriefDescription": "TOR Inserts; RdCur and FsRdCur requests from local IO that miss LLC", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8f3ff", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "BriefDescription": "TOR Inserts for RdCur from local IO", + "PublicDescription": "Inserts into the TOR from local IO with the opcode RdCur", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x25", + "UMask": "0x80", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000018", + "EventName": "UNC_M2M_IMC_WRITES.TO_PMM", + "BriefDescription": "PMM - All Channels", + "PublicDescription": "PMM - All Channels", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8f3fd", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR", + "BriefDescription": "TOR Occupancy; RdCur and FsRdCur hits from local IO", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8f3fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR", + "BriefDescription": "TOR Occupancy; RdCur and FsRdCur misses from local IO", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8f3ff", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR", + "BriefDescription": "TOR Occupancy; RdCur and FsRdCur from local IO", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00ccd7ff", + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA", + "BriefDescription": "TOR Inserts; LLCPrefData from local IA", + "PublicDescription": "TOR Inserts; Last level cache prefetch data read from local IA.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00ccd7fe", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", + "BriefDescription": "TOR Inserts; LLCPrefData misses from local IA", + "PublicDescription": "TOR Inserts; Last level cache prefetch data read from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00ccd7ff", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA", + "BriefDescription": "TOR Occupancy; LLCPrefData from local IA", + "PublicDescription": "TOR Occupancy; Last level cache prefetch data read from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00ccd7fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA", + "BriefDescription": "TOR Occupancy; LLCPrefData misses from local IA", + "PublicDescription": "TOR Occupancy; Last level cache prefetch data read from local IA that misses in the snoop filter", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00cd43ff", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "BriefDescription": "TOR Inserts for ItoMCacheNears from IO devices.", + "PublicDescription": "Inserts into the TOR from local IO devices with the opcode ItoMCacheNears. This event indicates a partial write request.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xe0", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL_SCH0", + "BriefDescription": "PMM Read Pending Queue occupancy", + "PublicDescription": "Accumulates the per cycle occupancy of the PMM Read Pending Queue.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xe0", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL_SCH1", + "BriefDescription": "PMM Read Pending Queue occupancy", + "PublicDescription": "Accumulates the per cycle occupancy of the PMM Read Pending Queue.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xe3", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_PMM_RPQ_INSERTS", + "BriefDescription": "PMM Read Pending Queue inserts", + "PublicDescription": "Counts number of read requests allocated in the PMM Read Pending Queue.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xe4", + "UMask": "0x03", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL", + "BriefDescription": "PMM Write Pending Queue Occupancy", + "PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the Write Pending Queue to the PMM DIMM.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xe7", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_PMM_WPQ_INSERTS", + "BriefDescription": "PMM Write Pending Queue inserts", + "PublicDescription": "Counts number of write requests allocated in the PMM Write Pending Queue.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x17", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_RDB_INSERTS.PCH0", + "BriefDescription": "Read Data Buffer Inserts", + "PublicDescription": "Read Data Buffer Inserts", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0x17", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00", + "EventName": "UNC_M_RDB_INSERTS.PCH1", + "BriefDescription": "Read Data Buffer Inserts", + "PublicDescription": "Read Data Buffer Inserts", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xE4", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL_SCH0", + "BriefDescription": "PMM Write Pending Queue Occupancy", + "PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "iMC", + "EventCode": "0xE4", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL_SCH1", + "BriefDescription": "PMM Write Pending Queue Occupancy", + "PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8168a", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM", + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8170a", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM", + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c81686", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR", + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c81706", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR", + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC23FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI", + "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8C3FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH", + "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8168a", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_PMM", + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8170a", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_PMM", + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c81686", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_DDR", + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c81706", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_DDR", + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00c8c7ff", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH", + "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores", + "PublicDescription": "TOR Occupancy : CLFlushes issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00cc57ff", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM", + "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores", + "PublicDescription": "TOR Occupancy : SpecItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00cd43fd", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR", + "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00cd43fe", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR", + "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x1F", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN", + "BriefDescription": "Clean NearMem Read Hit", + "PublicDescription": "Counts clean full line read hits (reads and RFOs).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2M", + "EventCode": "0x1F", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY", + "BriefDescription": "Dirty NearMem Read Hit", + "PublicDescription": "Counts dirty full line read hits (reads and RFOs).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x00", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_CLOCKTICKS_FREERUN", + "BriefDescription": "Free running counter that increments for IIO clocktick", + "PublicDescription": "0", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "FREERUN" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x80", + "PortMask": "0x0001", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0", + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x80", + "PortMask": "0x0002", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1", + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x80", + "PortMask": "0x0004", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2", + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x80", + "PortMask": "0x0008", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3", + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x80", + "PortMask": "0x0010", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4", + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x80", + "PortMask": "0x0020", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5", + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x80", + "PortMask": "0x0040", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6", + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x80", + "PortMask": "0x0080", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7", + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x80", + "PortMask": "0x0001", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0", + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x80", + "PortMask": "0x0002", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1", + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x80", + "PortMask": "0x0004", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2", + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x80", + "PortMask": "0x0008", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3", + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x80", + "PortMask": "0x0010", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4", + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x80", + "PortMask": "0x0020", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5", + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x80", + "PortMask": "0x0040", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6", + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x80", + "PortMask": "0x0080", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7", + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x85", + "UMask": "0x01", + "PortMask": "0x0FFF", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL", + "BriefDescription": "Number requests PCIe makes of the main die : All", + "PublicDescription": "Number requests PCIe makes of the main die : All : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x12", + "UMask": "0x78", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", + "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x11", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "BriefDescription": "Inbound write (fast path) requests received by the IRP.", + "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CXLCM", + "EventCode": "0x01", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CXLCM_CLOCKTICKS", + "BriefDescription": "Counts the number of lfclk ticks", + "PublicDescription": "Counts the number of lfclk ticks", + "Counter": "0,1,2,3,4,5,6,7", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CXLDP", + "EventCode": "0x01", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CXLDP_CLOCKTICKS", + "BriefDescription": "Counts the number of uclk ticks", + "PublicDescription": "Counts the number of uclk ticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x00ff", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS", + "BriefDescription": "Read request for 4 bytes made by IIO Part0-7 to Memory", + "PublicDescription": "Read request for 4 bytes made by IIO Part0-7 to Memory", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x00ff", + "FCMask": "0x07", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS", + "BriefDescription": "Write request of 4 bytes made by IIO Part0-7 to Memory", + "PublicDescription": "Write request of 4 bytes made by IIO Part0-7 to Memory", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "MCHBM", + "EventCode": "0x01", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_MCHBM_CLOCKTICKS", + "BriefDescription": "IMC Clockticks at DCLK frequency", + "PublicDescription": "IMC Clockticks at DCLK frequency", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2HBM", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M2HBM_CLOCKTICKS", + "BriefDescription": "Cycles - at UCLK", + "PublicDescription": "Cycles - at UCLK", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2HBM", + "EventCode": "0x20", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M2HBM_DIRECTORY_LOOKUP.ANY", + "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)", + "PublicDescription": "Counts the number of hit data returns to egress with any directory to non persistent memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2HBM", + "EventCode": "0x20", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M2HBM_DIRECTORY_LOOKUP.STATE_A", + "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)", + "PublicDescription": "Counts the number of hit data returns to egress with directory A to non persistent memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2HBM", + "EventCode": "0x20", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M2HBM_DIRECTORY_LOOKUP.STATE_I", + "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)", + "PublicDescription": "Counts the number of hit data returns to egress with directory I to non persistent memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2HBM", + "EventCode": "0x20", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M2HBM_DIRECTORY_LOOKUP.STATE_S", + "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)", + "PublicDescription": "Counts the number of hit data returns to egress with directory S to non persistent memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2HBM", + "EventCode": "0x21", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000003", + "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.ANY", + "BriefDescription": "Multi-socket cacheline Directory update from/to Any state", + "PublicDescription": "Multi-socket cacheline Directory update from/to Any state", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "M2HBM", + "EventCode": "0xc0", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00800000", + "EventName": "UNC_M2HBM_CMS_CLOCKTICKS", + "BriefDescription": "CMS Clockticks", + "PublicDescription": "CMS Clockticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8F2FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL", + "BriefDescription": "PCIRDCUR (read) transactions from an IO device that addresses memory on a remote socket", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8F37F", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE", + "BriefDescription": "PCIRDCUR (read) transactions from an IO device that addresses memory on the local socket", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC437F", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE", + "BriefDescription": "ItoM (write) transactions from an IO device that addresses memory on a remote socket", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC42FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL", + "BriefDescription": "ItoM (write) transactions from an IO device that addresses memory on the local socket", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD437F", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE", + "BriefDescription": "ItoMCacheNear (partial write) transactions from an IO device that addresses memory on a remote socket", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD42FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL", + "BriefDescription": "ItoMCacheNear (partial write) transactions from an IO device that addresses memory on the local socket", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + } + ] +} \ No newline at end of file diff --git a/cmd/metrics/resources/perfmon/spr/spr.json b/cmd/metrics/resources/perfmon/spr/spr.json new file mode 100644 index 00000000..9c4f70e1 --- /dev/null +++ b/cmd/metrics/resources/perfmon/spr/spr.json @@ -0,0 +1,1801 @@ +{ + "Header": { + "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", + "Info": "PerfSpect Performance Monitoring Metrics for Intel(R) 4th Generation Xeon(R) (Sapphire Rapids)" + }, + "PerfmonMetricsFile": "sapphirerapids_metrics.json", + "PerfmonCoreEventsFile": "sapphirerapids_core.json", + "PerfmonUncoreEventsFile": "sapphirerapids_uncore.json", + "PerfmonRetireLatencyFile": "", + "ReportMetrics": [ + { + "MetricName": "cpu_operating_frequency", + "LegacyName": "metric_CPU operating frequency (in GHz)", + "Origin": "perfmon" + }, + { + "MetricName": "cpu_utilization", + "LegacyName": "metric_CPU utilization %", + "Origin": "perfmon" + }, + { + "MetricName": "cpu_util_kernel", + "LegacyName": "metric_CPU utilization % in kernel mode", + "Origin": "perfspect" + }, + { + "MetricName": "cpi", + "LegacyName": "metric_CPI", + "Origin": "perfmon" + }, + { + "MetricName": "cycles_per_txn", + "LegacyName": "metric_cycles per txn", + "Origin": "perfspect" + }, + { + "MetricName": "kernel_cpi", + "LegacyName": "metric_kernel_CPI", + "Origin": "perfspect" + }, + { + "MetricName": "kernel_cycles_per_txn", + "LegacyName": "metric_kernel_cycles per txn", + "Origin": "perfspect" + }, + { + "MetricName": "ipc", + "LegacyName": "metric_IPC", + "Origin": "perfspect" + }, + { + "MetricName": "giga_instructions_per_sec", + "LegacyName": "metric_giga_instructions_per_sec", + "Origin": "perfspect" + }, + { + "MetricName": "branch_misprediction_ratio", + "LegacyName": "metric_branch misprediction ratio", + "Origin": "perfspect" + }, + { + "MetricName": "locks_retired_per_instr", + "LegacyName": "metric_locks retired per instr", + "Origin": "perfspect" + }, + { + "MetricName": "locks_retired_per_txn", + "LegacyName": "metric_locks retired per txn", + "Origin": "perfspect" + }, + { + "MetricName": "l1d_mpi", + "LegacyName": "metric_L1D MPI (includes data+rfo w/ prefetches)", + "Origin": "perfmon" + }, + { + "MetricName": "l1d_misses_per_txn", + "LegacyName": "metric_L1D misses per txn (includes data+rfo w/ prefetches)", + "Origin": "perfspect" + }, + { + "MetricName": "l1d_demand_data_read_hits_per_instr", + "LegacyName": "metric_L1D demand data read hits per instr", + "Origin": "perfmon" + }, + { + "MetricName": "l1d_demand_data_read_hits_per_txn", + "LegacyName": "metric_L1D demand data read hits per txn", + "Origin": "perfspect" + }, + { + "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", + "LegacyName": "metric_L1-I code read misses (w/ prefetches) per instr", + "Origin": "perfmon" + }, + { + "MetricName": "l1i_code_read_misses_per_txn", + "LegacyName": "metric_L1I code read misses (includes prefetches) per txn", + "Origin": "perfspect" + }, + { + "MetricName": "l2_demand_data_read_hits_per_instr", + "LegacyName": "metric_L2 demand data read hits per instr", + "Origin": "perfmon" + }, + { + "MetricName": "l2_demand_data_read_hits_per_txn", + "LegacyName": "metric_L2 demand data read hits per txn", + "Origin": "perfspect" + }, + { + "MetricName": "l2_mpi", + "LegacyName": "metric_L2 MPI (includes code+data+rfo w/ prefetches)", + "Origin": "perfmon" + }, + { + "MetricName": "l2_misses_per_txn", + "LegacyName": "metric_L2 misses per txn (includes code+data+rfo w/ prefetches)", + "Origin": "perfspect" + }, + { + "MetricName": "l2_demand_data_read_mpi", + "LegacyName": "metric_L2 demand data read MPI", + "Origin": "perfmon" + }, + { + "MetricName": "l2_demand_data_read_misses_per_txn", + "LegacyName": "metric_L2 demand data read misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "l2_demand_code_mpi", + "LegacyName": "metric_L2 demand code MPI", + "Origin": "perfmon" + }, + { + "MetricName": "l2_demand_code_misses_per_txn", + "LegacyName": "metric_L2 demand code misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "llc_code_read_mpi_demand_plus_prefetch", + "LegacyName": "metric_LLC code read MPI (demand+prefetch)", + "Origin": "perfmon" + }, + { + "MetricName": "llc_code_read_misses_per_txn", + "LegacyName": "metric_LLC code read (demand+prefetch) misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "llc_data_read_mpi_demand_plus_prefetch", + "LegacyName": "metric_LLC data read MPI (demand+prefetch)", + "Origin": "perfmon" + }, + { + "MetricName": "llc_data_read_misses_per_txn", + "LegacyName": "metric_LLC data read (demand+prefetch) misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "llc_demand_data_read_miss_latency", + "LegacyName": "metric_Average LLC demand data read miss latency (in ns)", + "Origin": "perfmon" + }, + { + "MetricName": "llc_demand_data_read_miss_latency_for_local_requests", + "LegacyName": "metric_Average LLC demand data read miss latency for LOCAL requests (in ns)", + "Origin": "perfmon" + }, + { + "MetricName": "llc_demand_data_read_miss_latency_for_remote_requests", + "LegacyName": "metric_Average LLC demand data read miss latency for REMOTE requests (in ns)", + "Origin": "perfmon" + }, + { + "MetricName": "upi_data_transmit_bw", + "LegacyName": "metric_UPI Data transmit BW (MB/sec) (only data)", + "Origin": "perfmon" + }, + { + "MetricName": "package_power", + "LegacyName": "metric_package power (watts)", + "Origin": "perfspect" + }, + { + "MetricName": "dram_power", + "LegacyName": "metric_DRAM power (watts)", + "Origin": "perfspect" + }, + { + "MetricName": "core_c6_residency", + "LegacyName": "metric_core c6 residency %", + "Origin": "perfspect" + }, + { + "MetricName": "package_c6_residency", + "LegacyName": "metric_package c6 residency %", + "Origin": "perfspect" + }, + { + "MetricName": "percent_uops_delivered_from_decoded_icache", + "LegacyName": "metric_% Uops delivered from decoded Icache (DSB)", + "Origin": "perfmon" + }, + { + "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline", + "LegacyName": "metric_% Uops delivered from legacy decode pipeline (MITE)", + "Origin": "perfmon" + }, + { + "MetricName": "memory_bandwidth_read", + "LegacyName": "metric_memory bandwidth read (MB/sec)", + "Origin": "perfmon" + }, + { + "MetricName": "memory_bandwidth_write", + "LegacyName": "metric_memory bandwidth write (MB/sec)", + "Origin": "perfmon" + }, + { + "MetricName": "memory_bandwidth_total", + "LegacyName": "metric_memory bandwidth total (MB/sec)", + "Origin": "perfmon" + }, + { + "MetricName": "itlb_2nd_level_mpi", + "LegacyName": "metric_ITLB (2nd level) MPI", + "Origin": "perfmon" + }, + { + "MetricName": "itlb_misses_per_txn", + "LegacyName": "metric_ITLB (2nd level) misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "dtlb_2nd_level_load_mpi", + "LegacyName": "metric_DTLB (2nd level) load MPI", + "Origin": "perfmon" + }, + { + "MetricName": "dtlb_load_misses_per_txn", + "LegacyName": "metric_DTLB (2nd level) load misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "dtlb_2nd_level_store_mpi", + "LegacyName": "metric_DTLB (2nd level) store MPI", + "Origin": "perfmon" + }, + { + "MetricName": "dtlb_store_misses_per_txn", + "LegacyName": "metric_DTLB (2nd level) store misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "numa_reads_addressed_to_local_dram", + "LegacyName": "metric_NUMA %_Reads addressed to local DRAM", + "Origin": "perfmon" + }, + { + "MetricName": "numa_reads_addressed_to_remote_dram", + "LegacyName": "metric_NUMA %_Reads addressed to remote DRAM", + "Origin": "perfmon" + }, + { + "MetricName": "uncore_frequency", + "LegacyName": "metric_uncore frequency GHz", + "Origin": "perfmon" + }, + { + "MetricName": "io_bandwidth_write", + "LegacyName": "metric_IO_bandwidth_disk_or_network_writes (MB/sec)", + "Origin": "perfmon" + }, + { + "MetricName": "io_bandwidth_read", + "LegacyName": "metric_IO_bandwidth_disk_or_network_reads (MB/sec)", + "Origin": "perfmon" + }, + { + "MetricName": "Frontend_Bound", + "LegacyName": "metric_TMA_Frontend_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Fetch_Latency", + "LegacyName": "metric_TMA_..Fetch_Latency(%)", + "Origin": "perfmon" + }, + { + "MetricName": "ICache_Misses", + "LegacyName": "metric_TMA_....ICache_Misses(%)", + "Origin": "perfmon" + }, + { + "MetricName": "ITLB_Misses", + "LegacyName": "metric_TMA_....ITLB_Misses(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Branch_Resteers", + "LegacyName": "metric_TMA_....Branch_Resteers(%)", + "Origin": "perfmon" + }, + { + "MetricName": "MS_Switches", + "LegacyName": "metric_TMA_....MS_Switches(%)", + "Origin": "perfmon" + }, + { + "MetricName": "LCP", + "LegacyName": "metric_TMA_....LCP(%)", + "Origin": "perfmon" + }, + { + "MetricName": "DSB_Switches", + "LegacyName": "metric_TMA_....DSB_Switches(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Fetch_Bandwidth", + "LegacyName": "metric_TMA_..Fetch_Bandwidth(%)", + "Origin": "perfmon" + }, + { + "MetricName": "MITE", + "LegacyName": "metric_TMA_....MITE(%)", + "Origin": "perfmon" + }, + { + "MetricName": "DSB", + "LegacyName": "metric_TMA_....DSB(%)", + "Origin": "perfmon" + }, + { + "MetricName": "MS", + "LegacyName": "metric_TMA_....MS(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Bad_Speculation", + "LegacyName": "metric_TMA_Bad_Speculation(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Branch_Mispredicts", + "LegacyName": "metric_TMA_..Branch_Mispredicts(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Other_Mispredicts", + "LegacyName": "metric_TMA_....Other_Mispredicts(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Machine_Clears", + "LegacyName": "metric_TMA_..Machine_Clears(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Other_Nukes", + "LegacyName": "metric_TMA_....Other_Nukes(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Backend_Bound", + "LegacyName": "metric_TMA_Backend_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Memory_Bound", + "LegacyName": "metric_TMA_..Memory_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "L1_Bound", + "LegacyName": "metric_TMA_....L1_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "DTLB_Load", + "LegacyName": "metric_TMA_......DTLB_Load(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Store_Fwd_Blk", + "LegacyName": "metric_TMA_......Store_Fwd_Blk(%)", + "Origin": "perfmon" + }, + { + "MetricName": "L1_Latency_Dependency", + "LegacyName": "metric_TMA_......L1_Latency_Dependency(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Lock_Latency", + "LegacyName": "metric_TMA_......Lock_Latency(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Split_Loads", + "LegacyName": "metric_TMA_......Split_Loads(%)", + "Origin": "perfmon" + }, + { + "MetricName": "FB_Full", + "LegacyName": "metric_TMA_......FB_Full(%)", + "Origin": "perfmon" + }, + { + "MetricName": "L2_Bound", + "LegacyName": "metric_TMA_....L2_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "L3_Bound", + "LegacyName": "metric_TMA_....L3_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Contested_Accesses", + "LegacyName": "metric_TMA_......Contested_Accesses(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Data_Sharing", + "LegacyName": "metric_TMA_......Data_Sharing(%)", + "Origin": "perfmon" + }, + { + "MetricName": "L3_Hit_Latency", + "LegacyName": "metric_TMA_......L3_Hit_Latency(%)", + "Origin": "perfmon" + }, + { + "MetricName": "SQ_Full", + "LegacyName": "metric_TMA_......SQ_Full(%)", + "Origin": "perfmon" + }, + { + "MetricName": "DRAM_Bound", + "LegacyName": "metric_TMA_....DRAM_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "MEM_Bandwidth", + "LegacyName": "metric_TMA_......MEM_Bandwidth(%)", + "Origin": "perfmon" + }, + { + "MetricName": "MEM_Latency", + "LegacyName": "metric_TMA_......MEM_Latency(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Store_Bound", + "LegacyName": "metric_TMA_....Store_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Store_Latency", + "LegacyName": "metric_TMA_......Store_Latency(%)", + "Origin": "perfmon" + }, + { + "MetricName": "False_Sharing", + "LegacyName": "metric_TMA_......False_Sharing(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Split_Stores", + "LegacyName": "metric_TMA_......Split_Stores(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Streaming_Stores", + "LegacyName": "metric_TMA_......Streaming_Stores(%)", + "Origin": "perfmon" + }, + { + "MetricName": "DTLB_Store", + "LegacyName": "metric_TMA_......DTLB_Store(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Core_Bound", + "LegacyName": "metric_TMA_..Core_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Divider", + "LegacyName": "metric_TMA_....Divider(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Serializing_Operation", + "LegacyName": "metric_TMA_....Serializing_Operation(%)", + "Origin": "perfmon" + }, + { + "MetricName": "AMX_Busy", + "LegacyName": "metric_TMA_....AMX_Busy(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Ports_Utilization", + "LegacyName": "metric_TMA_....Ports_Utilization(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Retiring", + "LegacyName": "metric_TMA_Retiring(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Light_Operations", + "LegacyName": "metric_TMA_..Light_Operations(%)", + "Origin": "perfmon" + }, + { + "MetricName": "FP_Arith", + "LegacyName": "metric_TMA_....FP_Arith(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Int_Operations", + "LegacyName": "metric_TMA_....Int_Operations(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Memory_Operations", + "LegacyName": "metric_TMA_....Memory_Operations(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Fused_Instructions", + "LegacyName": "metric_TMA_....Fused_Instructions(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Non_Fused_Branches", + "LegacyName": "metric_TMA_....Non_Fused_Branches(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Other_Light_Ops", + "LegacyName": "metric_TMA_....Other_Light_Ops(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Heavy_Operations", + "LegacyName": "metric_TMA_..Heavy_Operations(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Few_Uops_Instructions", + "LegacyName": "metric_TMA_....Few_Uops_Instructions(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Microcode_Sequencer", + "LegacyName": "metric_TMA_....Microcode_Sequencer(%)", + "Origin": "perfmon" + } +], + "Metrics": [ + { + "MetricName": "cpu_util_kernel", + "LegacyName": "metric_CPU utilization % in kernel mode", + "BriefDescription": "CPU utilization percentage in kernel mode", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + }, + { + "Name": "TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * (a / b)", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "cycles_per_txn", + "LegacyName": "metric_cycles per txn", + "BriefDescription": "Number of cycles per transaction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "kernel_cpi", + "LegacyName": "metric_kernel_CPI", + "BriefDescription": "Kernel cycles per instruction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "kernel_cycles_per_txn", + "LegacyName": "metric_kernel_cycles per txn", + "BriefDescription": "Number of kernel cycles per transaction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "ipc", + "LegacyName": "metric_IPC", + "BriefDescription": "Instructions per cycle", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "giga_instructions_per_sec", + "LegacyName": "metric_giga_instructions_per_sec", + "BriefDescription": "Billions of instructions per second", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + } + ], + "Constants": [ + ], + "Formula": "a / 1000000000", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "branch_misprediction_ratio", + "LegacyName": "metric_branch misprediction ratio", + "BriefDescription": "Ratio of branch mispredictions to the total number of branches retired.", + "Events": [ + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "locks_retired_per_instr", + "LegacyName": "metric_locks retired per instr", + "BriefDescription": "Locks retired per instruction", + "Events": [ + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "locks_retired_per_txn", + "LegacyName": "metric_locks retired per txn", + "BriefDescription": "Locks retired per transaction", + "Events": [ + { + "Name": "MEM_INST_RETIRED.LOCK_LOADS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l1d_misses_per_txn", + "LegacyName": "metric_L1D misses per txn (includes data+rfo w/ prefetches)", + "BriefDescription": "L1D misses per transaction (includes data+rfo with prefetches)", + "Events": [ + { + "Name": "L1D.REPLACEMENT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l1d_demand_data_read_hits_per_txn", + "LegacyName": "metric_L1D demand data read hits per txn", + "BriefDescription": "L1D demand data read hits per transaction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L1_HIT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l1i_code_read_misses_per_txn", + "LegacyName": "metric_L1I code read misses (includes prefetches) per txn", + "BriefDescription": "L1I code read misses (includes prefetches) per transaction", + "Events": [ + { + "Name": "L2_RQSTS.ALL_CODE_RD", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l2_demand_data_read_hits_per_txn", + "LegacyName": "metric_L2 demand data read hits per txn", + "BriefDescription": "L2 demand data read hits per transaction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_HIT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l2_misses_per_txn", + "LegacyName": "metric_L2 misses per txn (includes code+data+rfo w/ prefetches)", + "BriefDescription": "L2 misses per transaction (includes code+data+rfo with prefetches)", + "Events": [ + { + "Name": "L2_LINES_IN.ALL", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l2_demand_data_read_misses_per_txn", + "LegacyName": "metric_L2 demand data read misses per txn", + "BriefDescription": "L2 demand data read misses per transaction", + "Events": [ + { + "Name": "MEM_LOAD_RETIRED.L2_MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l2_demand_code_misses_per_txn", + "LegacyName": "metric_L2 demand code misses per txn", + "BriefDescription": "L2 demand code misses per transaction", + "Events": [ + { + "Name": "L2_RQSTS.CODE_RD_MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "llc_code_read_misses_per_txn", + "LegacyName": "metric_LLC code read (demand+prefetch) misses per txn", + "BriefDescription": "LLC code read (demand+prefetch) misses per transaction", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "llc_data_read_misses_per_txn", + "LegacyName": "metric_LLC data read (demand+prefetch) misses per txn", + "BriefDescription": "LLC data read (demand+prefetch) misses per transaction", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "d" + } + ], + "Formula": "(a + b + c) / d", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "package_power", + "LegacyName": "metric_package power (watts)", + "BriefDescription": "Package power consumption in watts", + "Events": [ + { + "Name": "power/energy-pkg/", + "Alias": "a" + } + ], + "Constants": [ + ], + "Formula": "a", + "ResolutionLevels": "SOCKET, SYSTEM" + }, + { + "MetricName": "dram_power", + "LegacyName": "metric_DRAM power (watts)", + "BriefDescription": "DRAM power consumption in watts", + "Events": [ + { + "Name": "power/energy-ram/", + "Alias": "a" + } + ], + "Constants": [ + ], + "Formula": "a", + "ResolutionLevels": "SOCKET, SYSTEM" + }, + { + "MetricName": "core_c6_residency", + "LegacyName": "metric_core c6 residency %", + "BriefDescription": "Core C6 state residency percentage", + "Events": [ + { + "Name": "cstate_core/c6-residency/", + "Alias": "a" + }, + { + "Name": "TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "ResolutionLevels": "CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "package_c6_residency", + "LegacyName": "metric_package c6 residency %", + "BriefDescription": "Package C6 state residency percentage", + "Events": [ + { + "Name": "cstate_pkg/c6-residency/", + "Alias": "a" + }, + { + "Name": "TSC", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "CORES_PER_SOCKET", + "Alias": "c" + } + ], + "Formula": "100 * a * c / b", + "ResolutionLevels": "SOCKET, SYSTEM" + }, + { + "MetricName": "itlb_misses_per_txn", + "LegacyName": "metric_ITLB (2nd level) misses per txn", + "BriefDescription": "ITLB (2nd level) misses per transaction", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "dtlb_load_misses_per_txn", + "LegacyName": "metric_DTLB (2nd level) load misses per txn", + "BriefDescription": "DTLB (2nd level) load misses per transaction", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "dtlb_store_misses_per_txn", + "LegacyName": "metric_DTLB (2nd level) store misses per txn", + "BriefDescription": "DTLB (2nd level) store misses per transaction", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + } + ], + "AlternateTMAMetrics": [ + { + "MetricName": "Frontend_Bound", + "LegacyName": "metric_TMA_Frontend_Bound(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ_BUBBLES.CORE", + "Alias": "a" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a - b ) / c )", + "BaseFormula": "100 * ( ( [IDQ_BUBBLES.CORE] - [INT_MISC.UOP_DROPPING] ) / [TOPDOWN.SLOTS_P] )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 15", + "BaseFormula": "metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvFB;BvIO;TmaL1;PGO", + "LocateWith": " FRONTEND_RETIRED.LATENCY_GE_4" + }, + { + "MetricName": "Fetch_Latency", + "LegacyName": "metric_TMA_..Fetch_Latency(%)", + "ParentCategory": "Frontend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "a" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( a * ( 6 ) - b ) / c )", + "BaseFormula": " ( 100 * ( ( [IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE] * ( 6 ) - [INT_MISC.UOP_DROPPING] ) / [TOPDOWN.SLOTS_P] ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Fetch_Latency(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Frontend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 15", + "BaseFormula": "metric_TMA_..Fetch_Latency(%) > 10 & metric_TMA_Frontend_Bound(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Frontend;TmaL2", + "LocateWith": " FRONTEND_RETIRED.LATENCY_GE_16;FRONTEND_RETIRED.LATENCY_GE_8" + }, + { + "MetricName": "Fetch_Bandwidth", + "LegacyName": "metric_TMA_..Fetch_Bandwidth(%)", + "ParentCategory": "Frontend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CORE", + "Alias": "a" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "c" + }, + { + "Name": "IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( ( a - b ) / ( c ) ) - ( ( d * ( 6 ) - b ) / ( c ) ) ) )", + "BaseFormula": "max( 0 , tma_frontend_bound - tma_fetch_latency )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Fetch_Bandwidth(%)" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_..Fetch_Bandwidth(%) > 20", + "ThresholdIssues": "$issueFB" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "FetchBW;Frontend;TmaL2", + "LocateWith": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1;FRONTEND_RETIRED.LATENCY_GE_1;FRONTEND_RETIRED.LATENCY_GE_2" + }, + { + "MetricName": "Bad_Speculation", + "LegacyName": "metric_TMA_Bad_Speculation(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ_BUBBLES.CORE", + "Alias": "a" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "c" + }, + { + "Name": "TOPDOWN.BACKEND_BOUND_SLOTS", + "Alias": "d" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "e" + } + ], + "Constants": [], + "Formula": "100 * ( max( 1 - ( ( ( a - b ) / c ) + ( d / c ) + ( e / c ) ) , 0 ) )", + "BaseFormula": " 100 * ( max( 1 - ( ( ( [IDQ_BUBBLES.CORE] - [INT_MISC.UOP_DROPPING] ) / [TOPDOWN.SLOTS_P] ) + ( [TOPDOWN.BACKEND_BOUND_SLOTS] / [TOPDOWN.SLOTS_P] ) + ( [UOPS_RETIRED.SLOTS] / [TOPDOWN.SLOTS_P] ) ) , 0 ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 15", + "BaseFormula": "metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "TmaL1", + "LocateWith": "#NA" + }, + { + "MetricName": "Branch_Mispredicts", + "LegacyName": "metric_TMA_..Branch_Mispredicts(%)", + "ParentCategory": "Bad_Speculation", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN.BR_MISPREDICT_SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "perf_metrics.branch_mispredicts / ( perf_metrics.frontend_bound + perf_metrics.bad_speculation + perf_metrics.retiring + perf_metrics.backend_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Branch_Mispredicts(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 10 & b > 15", + "BaseFormula": "metric_TMA_..Branch_Mispredicts(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "$issueBM" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2", + "LocateWith": "TOPDOWN.BR_MISPREDICT_SLOTS" + }, + { + "MetricName": "Machine_Clears", + "LegacyName": "metric_TMA_..Machine_Clears(%)", + "ParentCategory": "Bad_Speculation", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "IDQ_UOPS_NOT_DELIVERED.CORE", + "Alias": "a" + }, + { + "Name": "INT_MISC.UOP_DROPPING", + "Alias": "b" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "c" + }, + { + "Name": "TOPDOWN.BACKEND_BOUND_SLOTS", + "Alias": "d" + }, + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "e" + }, + { + "Name": "TOPDOWN.BR_MISPREDICT_SLOTS", + "Alias": "f" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( max( 1 - ( ( ( a - b ) / ( c ) ) + ( d / ( c ) ) + ( e / ( c ) ) ) , 0 ) ) - ( f / ( c ) ) ) )", + "BaseFormula": "max( 0 , tma_bad_speculation - tma_branch_mispredicts )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Machine_Clears(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Bad_Speculation(%)" + } + ], + "Formula": "a > 10 & b > 15", + "BaseFormula": "metric_TMA_..Machine_Clears(%) > 10 & metric_TMA_Bad_Speculation(%) > 15", + "ThresholdIssues": "$issueMC, $issueSyncxn" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2", + "LocateWith": "MACHINE_CLEARS.COUNT" + }, + { + "MetricName": "Backend_Bound", + "LegacyName": "metric_TMA_Backend_Bound(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN.BACKEND_BOUND_SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / b )", + "BaseFormula": " 100 * ( [TOPDOWN.BACKEND_BOUND_SLOTS] / [TOPDOWN.SLOTS_P] )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20", + "BaseFormula": "metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvOB;TmaL1", + "LocateWith": " TOPDOWN.BACKEND_BOUND_SLOTS" + }, + { + "MetricName": "Memory_Bound", + "LegacyName": "metric_TMA_..Memory_Bound(%)", + "ParentCategory": "Backend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN.MEMORY_BOUND_SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / b )", + "BaseFormula": " 100 * ( [TOPDOWN.MEMORY_BOUND_SLOTS] / [TOPDOWN.SLOTS_P] )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Memory_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 20 & b > 20", + "BaseFormula": "metric_TMA_..Memory_Bound(%) > 20 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Backend;TmaL2", + "LocateWith": "#NA" + }, + { + "MetricName": "Core_Bound", + "LegacyName": "metric_TMA_..Core_Bound(%)", + "ParentCategory": "Backend_Bound", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN.BACKEND_BOUND_SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + }, + { + "Name": "TOPDOWN.MEMORY_BOUND_SLOTS", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b ) ) - ( c / ( b ) ) ) )", + "BaseFormula": "max( 0 , tma_backend_bound - tma_memory_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Core_Bound(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_Backend_Bound(%)" + } + ], + "Formula": "a > 10 & b > 20", + "BaseFormula": "metric_TMA_..Core_Bound(%) > 10 & metric_TMA_Backend_Bound(%) > 20", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Backend;TmaL2;Compute", + "LocateWith": "" + }, + { + "MetricName": "Retiring", + "LegacyName": "metric_TMA_Retiring(%)", + "Level": 1, + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / b )", + "BaseFormula": " 100 * ( [UOPS_RETIRED.SLOTS] / [TOPDOWN.SLOTS_P] )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_Retiring(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 70 | b > 10", + "BaseFormula": "metric_TMA_Retiring(%) > 70 | metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "BvUW;TmaL1", + "LocateWith": " UOPS_RETIRED.SLOTS" + }, + { + "MetricName": "Light_Operations", + "LegacyName": "metric_TMA_..Light_Operations(%)", + "ParentCategory": "Retiring", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations , instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized code running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. ([ICL+] Note this may undercount due to approximation using indirect events; [ADL+] .)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + }, + { + "Name": "UOPS_RETIRED.HEAVY", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b ) ) - ( c / ( b ) ) ) )", + "BaseFormula": "max( 0 , tma_retiring - tma_heavy_operations )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 60", + "BaseFormula": "metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Retire;TmaL2", + "LocateWith": "INST_RETIRED.PREC_DIST" + }, + { + "MetricName": "Memory_Operations", + "LegacyName": "metric_TMA_....Memory_Operations(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations , uops for memory load or store accesses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + }, + { + "Name": "UOPS_RETIRED.HEAVY", + "Alias": "c" + }, + { + "Name": "MEM_UOP_RETIRED.ANY", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b ) ) - ( c / ( b ) ) ) ) * d / ( ( a / ( b ) ) * ( b ) ) )", + "BaseFormula": "tma_light_operations * mem_uop_retired.any / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Memory_Operations(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 60", + "BaseFormula": "metric_TMA_....Memory_Operations(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Fused_Instructions", + "LegacyName": "metric_TMA_....Fused_Instructions(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions , where one uop can represent multiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Other_Light_Ops in MTL!)}", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + }, + { + "Name": "UOPS_RETIRED.HEAVY", + "Alias": "c" + }, + { + "Name": "INST_RETIRED.MACRO_FUSED", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b ) ) - ( c / ( b ) ) ) ) * d / ( ( a / ( b ) ) * ( b ) ) )", + "BaseFormula": "tma_light_operations * inst_retired.macro_fused / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Fused_Instructions(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 60", + "BaseFormula": "metric_TMA_....Fused_Instructions(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;BvBO;Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Non_Fused_Branches", + "LegacyName": "metric_TMA_....Non_Fused_Branches(%)", + "ParentCategory": "Light_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.SLOTS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + }, + { + "Name": "UOPS_RETIRED.HEAVY", + "Alias": "c" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "d" + }, + { + "Name": "INST_RETIRED.MACRO_FUSED", + "Alias": "e" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "f" + }, + { + "Name": "INST_RETIRED.MACRO_FUSED", + "Alias": "g" + } + ], + "Constants": [], + "Formula": "100 * ( ( max( 0 , ( a / ( b ) ) - ( c / ( b ) ) ) ) * ( d - e ) / ( ( a / ( b ) ) * ( b ) ) )", + "BaseFormula": "tma_light_operations * ( br_inst_retired.all_branches - inst_retired.macro_fused ) / ( tma_retiring * tma_info_thread_slots )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Non_Fused_Branches(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Light_Operations(%)" + } + ], + "Formula": "a > 10 & b > 60", + "BaseFormula": "metric_TMA_....Non_Fused_Branches(%) > 10 & metric_TMA_..Light_Operations(%) > 60", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Branches;BvBO;Pipeline", + "LocateWith": "" + }, + { + "MetricName": "Heavy_Operations", + "LegacyName": "metric_TMA_..Heavy_Operations(%)", + "ParentCategory": "Retiring", + "Level": 2, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations , instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.([ICL+] Note this may overcount due to approximation using indirect events; [ADL+])", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.HEAVY", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / b )", + "BaseFormula": " 100 * ( [UOPS_RETIRED.HEAVY] / [TOPDOWN.SLOTS_P] )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 10", + "BaseFormula": "metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "Retire;TmaL2", + "LocateWith": " UOPS_RETIRED.HEAVY" + }, + { + "MetricName": "Few_Uops_Instructions", + "LegacyName": "metric_TMA_....Few_Uops_Instructions(%)", + "ParentCategory": "Heavy_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or more uops. This highly-correlates with the number of uops in such instructions.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.HEAVY", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + }, + { + "Name": "UOPS_RETIRED.MS", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( max( 0 , ( a / ( b ) ) - ( c / ( b ) ) ) )", + "BaseFormula": "max( 0 , tma_heavy_operations - tma_microcode_sequencer )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Few_Uops_Instructions(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 5 & b > 10", + "BaseFormula": "metric_TMA_....Few_Uops_Instructions(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "$issueD0" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "", + "LocateWith": "" + }, + { + "MetricName": "Microcode_Sequencer", + "LegacyName": "metric_TMA_....Microcode_Sequencer(%)", + "ParentCategory": "Heavy_Operations", + "Level": 3, + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UOPS_RETIRED.MS", + "Alias": "a" + }, + { + "Name": "TOPDOWN.SLOTS_P", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( b ) )", + "BaseFormula": "uops_retired.ms / tma_info_thread_slots", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "ThresholdMetrics": [ + { + "Alias": "a", + "Value": "metric_TMA_....Microcode_Sequencer(%)" + }, + { + "Alias": "b", + "Value": "metric_TMA_..Heavy_Operations(%)" + } + ], + "Formula": "a > 5 & b > 10", + "BaseFormula": "metric_TMA_....Microcode_Sequencer(%) > 5 & metric_TMA_..Heavy_Operations(%) > 10", + "ThresholdIssues": "$issueMC, $issueMS" + }, + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM", + "MetricGroup": "MicroSeq", + "LocateWith": "UOPS_RETIRED.MS" + } + ] +} diff --git a/cmd/metrics/resources/perfmon/srf/sierraforest_core.json b/cmd/metrics/resources/perfmon/srf/sierraforest_core.json new file mode 100644 index 00000000..b832feed --- /dev/null +++ b/cmd/metrics/resources/perfmon/srf/sierraforest_core.json @@ -0,0 +1,4711 @@ +{ + "Header": { + "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with E-cores - V1.11", + "DatePublished": "05/16/2025", + "Version": "1.11", + "Legend": "" + }, + "Events": [ + { + "EventCode": "0x00", + "UMask": "0x01", + "EventName": "INST_RETIRED.ANY", + "BriefDescription": "Fixed Counter: Counts the number of instructions retired", + "PublicDescription": "Fixed Counter: Counts the number of instructions retired", + "Counter": "Fixed counter 0", + "PEBScounters": "32", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "32", + "Speculative": "0" + }, + { + "EventCode": "0x00", + "UMask": "0x02", + "EventName": "CPU_CLK_UNHALTED.CORE", + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", + "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", + "Counter": "Fixed counter 1", + "PEBScounters": "33", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x00", + "UMask": "0x02", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", + "PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", + "Counter": "Fixed counter 1", + "PEBScounters": "33", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x00", + "UMask": "0x03", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles", + "PublicDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles", + "Counter": "Fixed counter 2", + "PEBScounters": "34", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x03", + "UMask": "0x01", + "EventName": "LD_BLOCKS.DATA_UNKNOWN", + "BriefDescription": "Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.", + "PublicDescription": "Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0x03", + "UMask": "0x02", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "BriefDescription": "Counts the number of retired loads that are blocked because its address partially overlapped with an older store.", + "PublicDescription": "Counts the number of retired loads that are blocked because its address partially overlapped with an older store.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0x03", + "UMask": "0x04", + "EventName": "LD_BLOCKS.ADDRESS_ALIAS", + "BriefDescription": "Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.", + "PublicDescription": "Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0x04", + "UMask": "0x01", + "EventName": "MEM_SCHEDULER_BLOCK.ST_BUF", + "BriefDescription": "Counts the number of cycles that uops are blocked due to a store buffer full condition.", + "PublicDescription": "Counts the number of cycles that uops are blocked due to a store buffer full condition.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "20003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x04", + "UMask": "0x02", + "EventName": "MEM_SCHEDULER_BLOCK.LD_BUF", + "BriefDescription": "Counts the number of cycles that uops are blocked due to a load buffer full condition.", + "PublicDescription": "Counts the number of cycles that uops are blocked due to a load buffer full condition.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "20003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x04", + "UMask": "0x04", + "EventName": "MEM_SCHEDULER_BLOCK.RSV", + "BriefDescription": "Counts the number of cycles that uops are blocked due to an RSV full condition.", + "PublicDescription": "Counts the number of cycles that uops are blocked due to an RSV full condition.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "20003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x04", + "UMask": "0x07", + "EventName": "MEM_SCHEDULER_BLOCK.ALL", + "BriefDescription": "Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full.", + "PublicDescription": "Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "20003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x05", + "UMask": "0x81", + "EventName": "LD_HEAD.L1_MISS_AT_RET", + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.", + "PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x05", + "UMask": "0x84", + "EventName": "LD_HEAD.ST_ADDR_AT_RET", + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match.", + "PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x05", + "UMask": "0x90", + "EventName": "LD_HEAD.DTLB_MISS_AT_RET", + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss.", + "PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x05", + "UMask": "0xa0", + "EventName": "LD_HEAD.PGWALK_AT_RET", + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk.", + "PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x05", + "UMask": "0xc0", + "EventName": "LD_HEAD.OTHER_AT_RET", + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.", + "PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases such as pipeline conflicts, fences, etc.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x05", + "UMask": "0xf4", + "EventName": "LD_HEAD.L1_BOUND_AT_RET", + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.", + "PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x05", + "UMask": "0xff", + "EventName": "LD_HEAD.ANY_AT_RET", + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.", + "PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x08", + "UMask": "0x02", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K page.", + "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x08", + "UMask": "0x04", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page.", + "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x08", + "UMask": "0x0e", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "BriefDescription": "Counts the number of page walks completed due to load DTLB misses.", + "PublicDescription": "Counts the number of page walks completed due to load DTLB misses.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x08", + "UMask": "0x10", + "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", + "BriefDescription": "Counts the number of page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle.", + "PublicDescription": "Counts the number of page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x08", + "UMask": "0x20", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "BriefDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.", + "PublicDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x0e", + "UMask": "0x00", + "EventName": "UOPS_ISSUED.ANY", + "BriefDescription": "Counts the number of uops issued by the front end every cycle.", + "PublicDescription": "Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x13", + "UMask": "0x02", + "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", + "BriefDescription": "Counts misaligned loads that are 4K page splits.", + "PublicDescription": "Counts misaligned loads that are 4K page splits.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0x13", + "UMask": "0x04", + "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", + "BriefDescription": "Counts misaligned stores that are 4K page splits.", + "PublicDescription": "Counts misaligned stores that are 4K page splits.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0x24", + "UMask": "0x01", + "EventName": "L2_REQUEST.MISS", + "BriefDescription": "Counts the number of total L2 Cache Accesses that resulted in a Miss from a front door request only (does not include rejects or recycles), per core event", + "PublicDescription": "Counts the number of total L2 Cache Accesses that resulted in a Miss from a front door request only (does not include rejects or recycles)", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x02", + "EventName": "L2_REQUEST.HIT", + "BriefDescription": "Counts the number of L2 Cache Accesses that resulted in a Hit from a front door request only (does not include rejects or recycles), per core event", + "PublicDescription": "Counts the number of L2 Cache Accesses that resulted in a Hit from a front door request only (does not include rejects or recycles)", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x24", + "UMask": "0x04", + "EventName": "L2_REQUEST.REJECTS", + "BriefDescription": "Counts the number of L2 Cache Accesses that miss the L2 and get BBL reject short and long rejects, per core event", + "PublicDescription": "Counts the number of L2 Cache Accesses that miss the L2 and get BBL reject short and long rejects", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x25", + "UMask": "0x02", + "EventName": "L2_LINES_IN.S", + "BriefDescription": "Counts the number of cache lines filled into the L2 cache that are in Shared state", + "PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Shared state. Counts on a per core basis.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x25", + "UMask": "0x04", + "EventName": "L2_LINES_IN.E", + "BriefDescription": "Counts the number of cache lines filled into the L2 cache that are in Exclusive state", + "PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Exclusive state. Counts on a per core basis.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x25", + "UMask": "0x08", + "EventName": "L2_LINES_IN.M", + "BriefDescription": "Counts the number of cache lines filled into the L2 cache that are in Modified state", + "PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Modified state. Counts on a per core basis.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x25", + "UMask": "0x10", + "EventName": "L2_LINES_IN.F", + "BriefDescription": "Counts the number of cache lines filled into the L2 cache that are in Forward state", + "PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Forward state. Counts on a per core basis.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x26", + "UMask": "0x01", + "EventName": "L2_LINES_OUT.SILENT", + "BriefDescription": "Counts the number of L2 cache lines that are silently dropped due to an L2 cache fill", + "PublicDescription": "Counts the number of L2 cache lines that are silently dropped due to an L2 cache fill. Increments on the core that brought the line in originally.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x26", + "UMask": "0x02", + "EventName": "L2_LINES_OUT.NON_SILENT", + "BriefDescription": "Counts the number of L2 cache lines that are evicted due to an L2 cache fill", + "PublicDescription": "Counts the number of L2 cache lines that are evicted due to an L2 cache fill. Increments on the core that brought the line in originally.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x2e", + "UMask": "0x41", + "EventName": "LONGEST_LAT_CACHE.MISS", + "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.", + "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x2e", + "UMask": "0x4f", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.", + "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x34", + "UMask": "0x01", + "EventName": "MEM_BOUND_STALLS_LOAD.L2_HIT", + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.", + "PublicDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x34", + "UMask": "0x06", + "EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT", + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.", + "PublicDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x34", + "UMask": "0x78", + "EventName": "MEM_BOUND_STALLS_LOAD.LLC_MISS", + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the local caches. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.", + "PublicDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the local caches. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x34", + "UMask": "0x7f", + "EventName": "MEM_BOUND_STALLS_LOAD.ALL", + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an L1 demand load miss.", + "PublicDescription": "Counts the number of unhalted cycles when the core is stalled due to an L1 demand load miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x34", + "UMask": "0x80", + "EventName": "MEM_BOUND_STALLS_LOAD.SBFULL", + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled to a store buffer full condition", + "PublicDescription": "Counts the number of unhalted cycles when the core is stalled to a store buffer full condition", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x35", + "UMask": "0x01", + "EventName": "MEM_BOUND_STALLS_IFETCH.L2_HIT", + "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.", + "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x35", + "UMask": "0x06", + "EventName": "MEM_BOUND_STALLS_IFETCH.LLC_HIT", + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which hit in the LLC. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.", + "PublicDescription": "Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which hit in the LLC. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x35", + "UMask": "0x78", + "EventName": "MEM_BOUND_STALLS_IFETCH.LLC_MISS", + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which missed all the caches. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.", + "PublicDescription": "Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which missed all the caches. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x35", + "UMask": "0x7f", + "EventName": "MEM_BOUND_STALLS_IFETCH.ALL", + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an instruction cache or TLB miss.", + "PublicDescription": "Counts the number of unhalted cycles when the core is stalled due to an instruction cache or TLB miss.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x3c", + "UMask": "0x00", + "EventName": "CPU_CLK_UNHALTED.CORE_P", + "BriefDescription": "Counts the number of unhalted core clock cycles [This event is alias to CPU_CLK_UNHALTED.THREAD_P]", + "PublicDescription": "Counts the number of unhalted core clock cycles [This event is alias to CPU_CLK_UNHALTED.THREAD_P]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x3c", + "UMask": "0x00", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "BriefDescription": "Counts the number of unhalted core clock cycles [This event is alias to CPU_CLK_UNHALTED.CORE_P]", + "PublicDescription": "Counts the number of unhalted core clock cycles [This event is alias to CPU_CLK_UNHALTED.CORE_P]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x3c", + "UMask": "0x01", + "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", + "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.", + "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x49", + "UMask": "0x02", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 4K page.", + "PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x49", + "UMask": "0x04", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 2M or 4M page.", + "PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x49", + "UMask": "0x0e", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G page.", + "PublicDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G page.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x49", + "UMask": "0x10", + "EventName": "DTLB_STORE_MISSES.WALK_PENDING", + "BriefDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle.", + "PublicDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x49", + "UMask": "0x20", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "BriefDescription": "Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Accounts for all pages sizes. Will result in a DTLB write from STLB.", + "PublicDescription": "Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Accounts for all pages sizes. Will result in a DTLB write from STLB.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x51", + "UMask": "0x01", + "EventName": "DL1.DIRTY_EVICTION", + "BriefDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches.", + "PublicDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches. Does not count evictions or dirty writebacks caused by snoops. Does not count a replacement unless a (dirty) line was written back.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x71", + "UMask": "0x00", + "EventName": "TOPDOWN_FE_BOUND.ALL_P", + "BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls [This event is alias to TOPDOWN_FE_BOUND.ALL]", + "PublicDescription": "Counts the number of retirement slots not consumed due to front end stalls [This event is alias to TOPDOWN_FE_BOUND.ALL]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x71", + "UMask": "0x00", + "EventName": "TOPDOWN_FE_BOUND.ALL", + "BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls [This event is alias to TOPDOWN_FE_BOUND.ALL_P]", + "PublicDescription": "Counts the number of retirement slots not consumed due to front end stalls [This event is alias to TOPDOWN_FE_BOUND.ALL_P]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x71", + "UMask": "0x01", + "EventName": "TOPDOWN_FE_BOUND.CISC", + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ms", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ms", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x71", + "UMask": "0x02", + "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BAClear", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BAClear", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x71", + "UMask": "0x04", + "EventName": "TOPDOWN_FE_BOUND.PREDECODE", + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to predecode wrong", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to predecode wrong", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x71", + "UMask": "0x08", + "EventName": "TOPDOWN_FE_BOUND.DECODE", + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stall", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stall", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x71", + "UMask": "0x10", + "EventName": "TOPDOWN_FE_BOUND.ITLB_MISS", + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to itlb miss [This event is alias to TOPDOWN_FE_BOUND.ITLB]", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to itlb miss [This event is alias to TOPDOWN_FE_BOUND.ITLB]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x71", + "UMask": "0x10", + "EventName": "TOPDOWN_FE_BOUND.ITLB", + "BriefDescription": "This event is deprecated. [This event is alias to TOPDOWN_FE_BOUND.ITLB_MISS]", + "PublicDescription": "This event is deprecated. [This event is alias to TOPDOWN_FE_BOUND.ITLB_MISS]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x71", + "UMask": "0x20", + "EventName": "TOPDOWN_FE_BOUND.ICACHE", + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to an icache miss", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to an icache miss", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x71", + "UMask": "0x40", + "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTClear", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTClear", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x71", + "UMask": "0x72", + "EventName": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY", + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x71", + "UMask": "0x80", + "EventName": "TOPDOWN_FE_BOUND.OTHER", + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend that do not categorize into any other common frontend stall", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend that do not categorize into any other common frontend stall", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x71", + "UMask": "0x8d", + "EventName": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH", + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x72", + "UMask": "0x00", + "EventName": "TOPDOWN_RETIRING.ALL_P", + "BriefDescription": "Counts the number of consumed retirement slots. [This event is alias to TOPDOWN_RETIRING.ALL]", + "PublicDescription": "Counts the number of consumed retirement slots. [This event is alias to TOPDOWN_RETIRING.ALL]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0x72", + "UMask": "0x00", + "EventName": "TOPDOWN_RETIRING.ALL", + "BriefDescription": "Counts the number of consumed retirement slots. [This event is alias to TOPDOWN_RETIRING.ALL_P]", + "PublicDescription": "Counts the number of consumed retirement slots. [This event is alias to TOPDOWN_RETIRING.ALL_P]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0x73", + "UMask": "0x00", + "EventName": "TOPDOWN_BAD_SPECULATION.ALL_P", + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION.ALL]", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION.ALL]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x73", + "UMask": "0x00", + "EventName": "TOPDOWN_BAD_SPECULATION.ALL", + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION.ALL_P]", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION.ALL_P]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x73", + "UMask": "0x01", + "EventName": "TOPDOWN_BAD_SPECULATION.NUKE", + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke).", + "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x73", + "UMask": "0x02", + "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to Fast Nukes such as Memory Ordering Machine clears and MRN nukes", + "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to Fast Nukes such as Memory Ordering Machine clears and MRN nukes", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x73", + "UMask": "0x03", + "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x73", + "UMask": "0x04", + "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to Branch Mispredict", + "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to Branch Mispredict", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x74", + "UMask": "0x00", + "EventName": "TOPDOWN_BE_BOUND.ALL_P", + "BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls [This event is alias to TOPDOWN_BE_BOUND.ALL]", + "PublicDescription": "Counts the number of retirement slots not consumed due to backend stalls [This event is alias to TOPDOWN_BE_BOUND.ALL]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x74", + "UMask": "0x00", + "EventName": "TOPDOWN_BE_BOUND.ALL", + "BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls [This event is alias to TOPDOWN_BE_BOUND.ALL_P]", + "PublicDescription": "Counts the number of retirement slots not consumed due to backend stalls [This event is alias to TOPDOWN_BE_BOUND.ALL_P]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x74", + "UMask": "0x01", + "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to due to certain allocation restrictions", + "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to due to certain allocation restrictions", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x74", + "UMask": "0x02", + "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stall (scheduler not being able to accept another uop). This could be caused by RSV full or load/store buffer block.", + "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stall (scheduler not being able to accept another uop). This could be caused by RSV full or load/store buffer block.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x74", + "UMask": "0x08", + "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC and FPC RAT stalls - which can be due to the FIQ and IEC reservation station stall (integer, FP and SIMD scheduler not being able to accept another uop. )", + "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC and FPC RAT stalls - which can be due to the FIQ and IEC reservation station stall (integer, FP and SIMD scheduler not being able to accept another uop. )", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x74", + "UMask": "0x10", + "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to iq/jeu scoreboards or ms scb", + "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to iq/jeu scoreboards or ms scb", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x74", + "UMask": "0x20", + "EventName": "TOPDOWN_BE_BOUND.REGISTER", + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to mrbl stall. A 'marble' refers to a physical register file entry, also known as the physical destination (PDST).", + "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to mrbl stall. A 'marble' refers to a physical register file entry, also known as the physical destination (PDST).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x74", + "UMask": "0x40", + "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to ROB full", + "PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to ROB full", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x75", + "UMask": "0x04", + "EventName": "SERIALIZATION.C01_MS_SCB", + "BriefDescription": "Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state.", + "PublicDescription": "Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x80", + "UMask": "0x02", + "EventName": "ICACHE.MISSES", + "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -", + "PublicDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x80", + "UMask": "0x03", + "EventName": "ICACHE.ACCESSES", + "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.", + "PublicDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x85", + "UMask": "0x01", + "EventName": "ITLB_MISSES.MISS_CAUSED_WALK", + "BriefDescription": "Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.", + "PublicDescription": "Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x85", + "UMask": "0x02", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 4K page.", + "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x85", + "UMask": "0x04", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 2M or 4M page.", + "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x85", + "UMask": "0x0e", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.", + "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x85", + "UMask": "0x10", + "EventName": "ITLB_MISSES.WALK_PENDING", + "BriefDescription": "Counts the number of page walks outstanding for iside in PMH every cycle.", + "PublicDescription": "Counts the number of page walks outstanding for iside in PMH every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals. Walks could be counted by edge detecting on this event, but would count restarted suspended walks.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0x85", + "UMask": "0x20", + "EventName": "ITLB_MISSES.STLB_HIT", + "BriefDescription": "Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB.", + "PublicDescription": "Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc0", + "UMask": "0x00", + "EventName": "INST_RETIRED.ANY_P", + "BriefDescription": "Counts the number of instructions retired", + "PublicDescription": "Counts the number of instructions retired", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x00", + "EventName": "UOPS_RETIRED.ALL", + "BriefDescription": "Counts the total number of uops retired.", + "PublicDescription": "Counts the total number of uops retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x01", + "EventName": "UOPS_RETIRED.MS", + "BriefDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.", + "PublicDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x02", + "EventName": "UOPS_RETIRED.X87", + "BriefDescription": "Counts the number of x87 uops retired, includes those in ms flows", + "PublicDescription": "Counts the number of x87 uops retired, includes those in ms flows", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x08", + "EventName": "UOPS_RETIRED.FPDIV", + "BriefDescription": "Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt).", + "PublicDescription": "Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt).", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc2", + "UMask": "0x10", + "EventName": "UOPS_RETIRED.IDIV", + "BriefDescription": "Counts the number of integer divide uops retired.", + "PublicDescription": "Counts the number of integer divide uops retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc3", + "UMask": "0x01", + "EventName": "MACHINE_CLEARS.SMC", + "BriefDescription": "Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page.", + "PublicDescription": "Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "20003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc3", + "UMask": "0x02", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.", + "PublicDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "20003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc3", + "UMask": "0x04", + "EventName": "MACHINE_CLEARS.FP_ASSIST", + "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.", + "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "20003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc3", + "UMask": "0x08", + "EventName": "MACHINE_CLEARS.DISAMBIGUATION", + "BriefDescription": "Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.", + "PublicDescription": "Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "20003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc3", + "UMask": "0x20", + "EventName": "MACHINE_CLEARS.PAGE_FAULT", + "BriefDescription": "Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs.", + "PublicDescription": "Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "20003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc3", + "UMask": "0x6f", + "EventName": "MACHINE_CLEARS.SLOW", + "BriefDescription": "This event is deprecated.", + "PublicDescription": "This event is deprecated.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "20003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xc4", + "UMask": "0x00", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "BriefDescription": "Counts the total number of branch instructions retired for all branch types.", + "PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "SRF6, SRF7", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0x7e", + "EventName": "BR_INST_RETIRED.COND", + "BriefDescription": "Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches.", + "PublicDescription": "Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "SRF7", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0xbf", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "BriefDescription": "Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return.", + "PublicDescription": "Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "SRF7", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0xc0", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "BriefDescription": "Counts the number of near taken branch instructions retired.", + "PublicDescription": "Counts the number of near taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "SRF7", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0xdf", + "EventName": "BR_INST_RETIRED.REL_JMP", + "BriefDescription": "Counts the number of near relative JMP branch instructions retired.", + "PublicDescription": "Counts the number of near relative JMP branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0xeb", + "EventName": "BR_INST_RETIRED.INDIRECT", + "BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired.", + "PublicDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "SRF7", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0xef", + "EventName": "BR_INST_RETIRED.INDIRECT_JMP", + "BriefDescription": "Counts the number of near indirect JMP branch instructions retired.", + "PublicDescription": "Counts the number of near indirect JMP branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0xf7", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "BriefDescription": "Counts the number of near RET branch instructions retired.", + "PublicDescription": "Counts the number of near RET branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0xf9", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "BriefDescription": "Counts the number of near CALL branch instructions retired.", + "PublicDescription": "Counts the number of near CALL branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "SRF6, SRF7", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0xfb", + "EventName": "BR_INST_RETIRED.IND_CALL", + "BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT_CALL", + "PublicDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT_CALL", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "SRF7", + "Offcore": "0", + "Deprecated": "1", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0xfb", + "EventName": "BR_INST_RETIRED.INDIRECT_CALL", + "BriefDescription": "Counts the number of near indirect CALL branch instructions retired.", + "PublicDescription": "Counts the number of near indirect CALL branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "SRF7", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0xfd", + "EventName": "BR_INST_RETIRED.REL_CALL", + "BriefDescription": "Counts the number of near relative CALL branch instructions retired.", + "PublicDescription": "Counts the number of near relative CALL branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc4", + "UMask": "0xfe", + "EventName": "BR_INST_RETIRED.COND_TAKEN", + "BriefDescription": "Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired.", + "PublicDescription": "Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x00", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.", + "PublicDescription": "Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x7e", + "EventName": "BR_MISP_RETIRED.COND", + "BriefDescription": "Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired.", + "PublicDescription": "Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0x80", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "BriefDescription": "Counts the number of mispredicted near taken branch instructions retired.", + "PublicDescription": "Counts the number of mispredicted near taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0xeb", + "EventName": "BR_MISP_RETIRED.INDIRECT", + "BriefDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired.", + "PublicDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0xef", + "EventName": "BR_MISP_RETIRED.INDIRECT_JMP", + "BriefDescription": "Counts the number of mispredicted near indirect JMP branch instructions retired.", + "PublicDescription": "Counts the number of mispredicted near indirect JMP branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0xf7", + "EventName": "BR_MISP_RETIRED.RETURN", + "BriefDescription": "Counts the number of mispredicted near RET branch instructions retired.", + "PublicDescription": "Counts the number of mispredicted near RET branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0xfb", + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", + "BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired.", + "PublicDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc5", + "UMask": "0xfe", + "EventName": "BR_MISP_RETIRED.COND_TAKEN", + "BriefDescription": "Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired.", + "PublicDescription": "Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x00", + "EventName": "FRONTEND_RETIRED.ALL", + "BriefDescription": "Counts the number of instructions retired that were tagged with having preceded with frontend bound behavior", + "PublicDescription": "Counts the number of instructions retired that were tagged with having preceded with frontend bound behavior", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x01", + "EventName": "FRONTEND_RETIRED.CISC", + "BriefDescription": "Counts the number of instructions retired that were tagged following an ms flow due to the bubble/wasted issue slot from exiting long ms flow", + "PublicDescription": "Counts the number of instructions retired that were tagged following an ms flow due to the bubble/wasted issue slot from exiting long ms flow", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x02", + "EventName": "FRONTEND_RETIRED.BRANCH_DETECT", + "BriefDescription": "Counts the number of instruction retired that are tagged after a branch instruction causes bubbles/empty issue slots due to a baclear", + "PublicDescription": "Counts the number of instruction retired that are tagged after a branch instruction causes bubbles/empty issue slots due to a baclear", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x04", + "EventName": "FRONTEND_RETIRED.PREDECODE", + "BriefDescription": "Counts the number of instruction retired that are tagged after a branch instruction causes bubbles/empty issue slots due to a predecode wrong.", + "PublicDescription": "Counts the number of instruction retired that are tagged after a branch instruction causes bubbles/empty issue slots due to a predecode wrong.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x08", + "EventName": "FRONTEND_RETIRED.DECODE", + "BriefDescription": "Counts the number of instructions retired that were tagged every cycle the decoder is unable to send 3 uops per cycle.", + "PublicDescription": "Counts the number of instructions retired that were tagged every cycle the decoder is unable to send 3 uops per cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x10", + "EventName": "FRONTEND_RETIRED.ITLB_MISS", + "BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss", + "PublicDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x20", + "EventName": "FRONTEND_RETIRED.ICACHE", + "BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to icache miss", + "PublicDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to icache miss", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x40", + "EventName": "FRONTEND_RETIRED.BRANCH_RESTEER", + "BriefDescription": "Counts the number of instruction retired that are tagged after a branch instruction causes bubbles /empty issue slots due to a btclear", + "PublicDescription": "Counts the number of instruction retired that are tagged after a branch instruction causes bubbles /empty issue slots due to a btclear", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc6", + "UMask": "0x80", + "EventName": "FRONTEND_RETIRED.OTHER", + "BriefDescription": "Counts the number of instruction retired tagged after a wasted issue slot if none of the previous events occurred", + "PublicDescription": "Counts the number of instruction retired tagged after a wasted issue slot if none of the previous events occurred", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x01", + "EventName": "FP_INST_RETIRED.32B_SP", + "BriefDescription": "Counts the number of retired instructions whose sources are a scalar 32bit single precision floating point.", + "PublicDescription": "Counts the number of retired instructions whose sources are a scalar 32bit single precision floating point.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x02", + "EventName": "FP_INST_RETIRED.64B_DP", + "BriefDescription": "Counts the number of retired instructions whose sources are a scalar 64 bit double precision floating point.", + "PublicDescription": "Counts the number of retired instructions whose sources are a scalar 64 bit double precision floating point.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x04", + "EventName": "FP_INST_RETIRED.128B_SP", + "BriefDescription": "Counts the number of retired instructions whose sources are a packed 128 bit single precision floating point. This may be SSE or AVX.128 operations.", + "PublicDescription": "Counts the number of retired instructions whose sources are a packed 128 bit single precision floating point. This may be SSE or AVX.128 operations.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x08", + "EventName": "FP_INST_RETIRED.128B_DP", + "BriefDescription": "Counts the total number of floating point retired instructions.", + "PublicDescription": "Counts the total number of floating point retired instructions.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc7", + "UMask": "0x20", + "EventName": "FP_INST_RETIRED.256B_DP", + "BriefDescription": "Counts the number of retired instructions whose sources are a packed 256 bit double precision floating point.", + "PublicDescription": "Counts the number of retired instructions whose sources are a packed 256 bit double precision floating point.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc8", + "UMask": "0x01", + "EventName": "FP_FLOPS_RETIRED.DP", + "BriefDescription": "This event is deprecated. [This event is alias to FP_FLOPS_RETIRED.FP64]", + "PublicDescription": "This event is deprecated. [This event is alias to FP_FLOPS_RETIRED.FP64]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc8", + "UMask": "0x01", + "EventName": "FP_FLOPS_RETIRED.FP64", + "BriefDescription": "Counts the number of floating point operations that produce 64 bit double precision results [This event is alias to FP_FLOPS_RETIRED.DP]", + "PublicDescription": "Counts the number of floating point operations that produce 64 bit double precision results [This event is alias to FP_FLOPS_RETIRED.DP]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc8", + "UMask": "0x02", + "EventName": "FP_FLOPS_RETIRED.SP", + "BriefDescription": "This event is deprecated. [This event is alias to FP_FLOPS_RETIRED.FP32]", + "PublicDescription": "This event is deprecated. [This event is alias to FP_FLOPS_RETIRED.FP32]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc8", + "UMask": "0x02", + "EventName": "FP_FLOPS_RETIRED.FP32", + "BriefDescription": "Counts the number of floating point operations that produce 32 bit single precision results [This event is alias to FP_FLOPS_RETIRED.SP]", + "PublicDescription": "Counts the number of floating point operations that produce 32 bit single precision results [This event is alias to FP_FLOPS_RETIRED.SP]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xc8", + "UMask": "0x03", + "EventName": "FP_FLOPS_RETIRED.ALL", + "BriefDescription": "Counts the number of all types of floating point operations per uop with all default weighting", + "PublicDescription": "Counts the number of all types of floating point operations per uop with all default weighting", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xcd", + "UMask": "0x02", + "EventName": "ARITH.FPDIV_ACTIVE", + "BriefDescription": "Counts the number of cycles when any of the floating point dividers are active.", + "PublicDescription": "Counts the number of cycles when any of the floating point dividers are active.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "NA", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xcd", + "UMask": "0x03", + "EventName": "ARITH.DIV_ACTIVE", + "BriefDescription": "Counts the number of cycles when any of the floating point or integer dividers are active.", + "PublicDescription": "Counts the number of cycles when any of the floating point or integer dividers are active.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "NA", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "1", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xd0", + "UMask": "0x05", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Counter": "0,1", + "PEBScounters": "0,1", + "SampleAfterValue": "1000003", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x05", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Counter": "0,1", + "PEBScounters": "0,1", + "SampleAfterValue": "1000003", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x05", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Counter": "0,1", + "PEBScounters": "0,1", + "SampleAfterValue": "1000003", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x05", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Counter": "0,1", + "PEBScounters": "0,1", + "SampleAfterValue": "1000003", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x05", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Counter": "0,1", + "PEBScounters": "0,1", + "SampleAfterValue": "1000003", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x05", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Counter": "0,1", + "PEBScounters": "0,1", + "SampleAfterValue": "1000003", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x05", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Counter": "0,1", + "PEBScounters": "0,1", + "SampleAfterValue": "1000003", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x05", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Counter": "0,1", + "PEBScounters": "0,1", + "SampleAfterValue": "1000003", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x05", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Counter": "0,1", + "PEBScounters": "0,1", + "SampleAfterValue": "1000003", + "MSRIndex": "0x3F6", + "MSRValue": "0x800", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x05", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024", + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Counter": "0,1", + "PEBScounters": "0,1", + "SampleAfterValue": "1000003", + "MSRIndex": "0x3F6", + "MSRValue": "0x400", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "1", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x06", + "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", + "BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES", + "PublicDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "1", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x11", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "BriefDescription": "Counts the number of load uops retired that miss in the second Level TLB.", + "PublicDescription": "Counts the number of load uops retired that miss in the second Level TLB.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x12", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "BriefDescription": "Counts the number of store uops retired that miss in the second level TLB.", + "PublicDescription": "Counts the number of store uops retired that miss in the second level TLB.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x13", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS", + "BriefDescription": "Counts the number of memory uops retired that missed in the second level TLB.", + "PublicDescription": "Counts the number of memory uops retired that missed in the second level TLB.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x21", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "BriefDescription": "Counts the number of load uops retired that performed one or more locks", + "PublicDescription": "Counts the number of load uops retired that performed one or more locks", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x41", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "BriefDescription": "Counts the number of retired split load uops.", + "PublicDescription": "Counts the number of retired split load uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x42", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "BriefDescription": "Counts the number of retired split store uops.", + "PublicDescription": "Counts the number of retired split store uops.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x43", + "EventName": "MEM_UOPS_RETIRED.SPLIT", + "BriefDescription": "Counts the number of memory uops retired that were splits.", + "PublicDescription": "Counts the number of memory uops retired that were splits.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x81", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "BriefDescription": "Counts the number of load ops retired.", + "PublicDescription": "Counts the number of load ops retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xd0", + "UMask": "0x82", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "BriefDescription": "Counts the number of store ops retired.", + "PublicDescription": "Counts the number of store ops retired.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "1", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x01", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "BriefDescription": "Counts the number of load ops retired that hit the L1 data cache.", + "PublicDescription": "Counts the number of load ops retired that hit the L1 data cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x02", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "BriefDescription": "Counts the number of load ops retired that hit in the L2 cache.", + "PublicDescription": "Counts the number of load ops retired that hit in the L2 cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x1c", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", + "BriefDescription": "Counts the number of load ops retired that hit in the L3 cache.", + "PublicDescription": "Counts the number of load ops retired that hit in the L3 cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x20", + "EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT", + "BriefDescription": "Counts the number of loads that hit in a write combining buffer (WCB), excluding the first load that caused the WCB to allocate.", + "PublicDescription": "Counts the number of loads that hit in a write combining buffer (WCB), excluding the first load that caused the WCB to allocate.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x40", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "BriefDescription": "Counts the number of load ops retired that miss in the L1 data cache.", + "PublicDescription": "Counts the number of load ops retired that miss in the L1 data cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xd1", + "UMask": "0x80", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "BriefDescription": "Counts the number of load ops retired that miss in the L2 cache.", + "PublicDescription": "Counts the number of load ops retired that miss in the L2 cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xd3", + "UMask": "0x01", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", + "BriefDescription": "Counts the number of load ops retired that miss the L3 cache and hit in DRAM", + "PublicDescription": "Counts the number of load ops retired that miss the L3 cache and hit in DRAM", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe4", + "UMask": "0x01", + "EventName": "MISC_RETIRED.LBR_INSERTS", + "BriefDescription": "Counts the number of Last Branch Record (LBR) entries. Requires LBRs to be enabled and configured in IA32_LBR_CTL. [This event is alias to LBR_INSERTS.ANY]", + "PublicDescription": "Counts the number of Last Branch Record (LBR) entries. Requires LBRs to be enabled and configured in IA32_LBR_CTL. [This event is alias to LBR_INSERTS.ANY]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe4", + "UMask": "0x01", + "EventName": "LBR_INSERTS.ANY", + "BriefDescription": "This event is deprecated. [This event is alias to MISC_RETIRED.LBR_INSERTS]", + "PublicDescription": "This event is deprecated. [This event is alias to MISC_RETIRED.LBR_INSERTS]", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "1", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "1", + "PDISTCounter": "NA", + "Speculative": "0" + }, + { + "EventCode": "0xe6", + "UMask": "0x01", + "EventName": "BACLEARS.ANY", + "BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", + "PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "200003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xe7", + "UMask": "0x04", + "EventName": "MS_DECODED.MS_BUSY", + "BriefDescription": "Counts the number of cycles that the micro-sequencer is busy.", + "PublicDescription": "Counts the number of cycles that the micro-sequencer is busy.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "MSRIndex": "0x00", + "MSRValue": "0x00", + "Precise": "0", + "CollectPEBSRecord": "2", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "0", + "Deprecated": "0", + "PDISTCounter": "NA", + "Speculative": "1" + }, + { + "EventCode": "0xB7", + "UMask": "0x01,0x02", + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "BriefDescription": "Counts demand data reads that have any type of response.", + "PublicDescription": "Counts demand data reads that have any type of response.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7", + "UMask": "0x01,0x02", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", + "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.", + "PublicDescription": "Counts demand data reads that were not supplied by the L3 cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7", + "UMask": "0x01,0x02", + "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", + "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket.", + "PublicDescription": "Counts demand data reads that were supplied by DRAM attached to this socket.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7", + "UMask": "0x01,0x02", + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", + "PublicDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7", + "UMask": "0x01,0x02", + "EventName": "OCR.DEMAND_RFO.L3_MISS", + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", + "PublicDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7", + "UMask": "0x01,0x02", + "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", + "BriefDescription": "Counts streaming stores that have any type of response.", + "PublicDescription": "Counts streaming stores that have any type of response.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10800", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7", + "UMask": "0x01,0x02", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", + "PublicDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7", + "UMask": "0x01,0x02", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "PublicDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7", + "UMask": "0x01,0x02", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "PublicDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + }, + { + "EventCode": "0xB7", + "UMask": "0x01,0x02", + "EventName": "OCR.DEMAND_DATA_RD.REMOTE_DRAM", + "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to another socket.", + "PublicDescription": "Counts demand data reads that were supplied by DRAM attached to another socket.", + "Counter": "0,1,2,3,4,5,6,7", + "PEBScounters": "0", + "SampleAfterValue": "100003", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x730000001", + "Precise": "0", + "CollectPEBSRecord": "0", + "TakenAlone": "0", + "CounterMask": "0", + "Invert": "0", + "EdgeDetect": "0", + "Data_LA": "0", + "L1_Hit_Indication": "0", + "Errata": "null", + "Offcore": "1", + "Deprecated": "0", + "PDISTCounter": "0", + "Speculative": "0" + } + ] +} \ No newline at end of file diff --git a/cmd/metrics/resources/perfmon/srf/sierraforest_metrics.json b/cmd/metrics/resources/perfmon/srf/sierraforest_metrics.json new file mode 100644 index 00000000..472b5808 --- /dev/null +++ b/cmd/metrics/resources/perfmon/srf/sierraforest_metrics.json @@ -0,0 +1,3157 @@ +{ + "Header": { + "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Metrics for Intel(R) Xeon(R) 6 Processor with E-cores0", + "DatePublished": "05/28/2025", + "Version": "1.02", + "Legend": "", + "TmaVersion": "3.6", + "TmaFlavor": "Public" + }, + "Metrics": [ + { + "MetricName": "cpu_operating_frequency", + "LegacyName": "metric_CPU operating frequency (in GHz)", + "Level": 1, + "BriefDescription": "CPU operating frequency (in GHz)", + "UnitOfMeasure": "GHz", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "c" + } + ], + "Formula": "(a / b * c) / 1000000000", + "Category": "Freq", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "uncore_frequency", + "LegacyName": "metric_uncore frequency GHz", + "Level": 1, + "BriefDescription": "Uncore operating frequency in GHz", + "UnitOfMeasure": "GHz", + "Events": [ + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "b" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "(a / (b * socket_count) / 1000000000) / DURATIONTIMEINSECONDS", + "Category": "Freq", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "cpu_utilization", + "LegacyName": "metric_CPU utilization %", + "Level": 1, + "BriefDescription": "Percentage of time spent in the active CPU power state C0", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + }, + { + "Name": "TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "Category": "Util", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "cpi", + "LegacyName": "metric_CPI", + "Level": 1, + "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "CPI", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_mpi", + "LegacyName": "metric_L2 MPI (includes code+data+rfo w/ prefetches)", + "Level": 1, + "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "LONGEST_LAT_CACHE.REFERENCE", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "numa_reads_addressed_to_local_dram", + "LegacyName": "metric_NUMA %_Reads addressed to local DRAM", + "Level": 1, + "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_LOCAL", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_REMOTE", + "Alias": "c" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_REMOTE", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (a + b) / (a + b + c + d)", + "Category": "NUMA", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "numa_reads_addressed_to_remote_dram", + "LegacyName": "metric_NUMA %_Reads addressed to remote DRAM", + "Level": 1, + "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_LOCAL", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_REMOTE", + "Alias": "c" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_REMOTE", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * (c + d) / (a + b + c + d)", + "Category": "NUMA", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_bandwidth_read", + "LegacyName": "metric_memory bandwidth read (MB/sec)", + "Level": 1, + "BriefDescription": "DDR memory read bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT_SCH0.RD", + "Alias": "a" + }, + { + "Name": "UNC_M_CAS_COUNT_SCH1.RD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, MC", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_bandwidth_write", + "LegacyName": "metric_memory bandwidth write (MB/sec)", + "Level": 1, + "BriefDescription": "DDR memory write bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT_SCH0.WR", + "Alias": "a" + }, + { + "Name": "UNC_M_CAS_COUNT_SCH1.WR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, MC", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "memory_bandwidth_total", + "LegacyName": "metric_memory bandwidth total (MB/sec)", + "Level": 1, + "BriefDescription": "DDR memory bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_M_CAS_COUNT_SCH0.RD", + "Alias": "a" + }, + { + "Name": "UNC_M_CAS_COUNT_SCH1.RD", + "Alias": "b" + }, + { + "Name": "UNC_M_CAS_COUNT_SCH0.WR", + "Alias": "c" + }, + { + "Name": "UNC_M_CAS_COUNT_SCH1.WR", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "((a + b + c + d) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, MC", + "ResolutionLevels": "CHANNEL, IMC, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "upi_data_transmit_bw", + "LegacyName": "metric_UPI Data transmit BW (MB/sec) (only data)", + "Level": 1, + "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_UPI_TxL_FLITS.ALL_DATA", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * (64 / 9.0) / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW", + "ResolutionLevels": "UPI, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "loads_retired_per_instr", + "LegacyName": "metric_loads retired per instr", + "Level": 1, + "BriefDescription": "Load operations retired per instruction", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_UOPS_RETIRED.ALL_LOADS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "stores_retired_per_instr", + "LegacyName": "metric_stores retired per instr", + "Level": 1, + "BriefDescription": "Store operations retired per instruction", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_UOPS_RETIRED.ALL_STORES", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l1d_demand_data_read_hits_per_instr", + "LegacyName": "metric_L1D demand data read hits per instr", + "Level": 1, + "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "D-side", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", + "LegacyName": "metric_L1-I code read misses (w/ prefetches) per instr", + "Level": 1, + "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "ICACHE.MISSES", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, I-side", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_demand_data_read_hits_per_instr", + "LegacyName": "metric_L2 demand data read hits per instr", + "Level": 1, + "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "D-side", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "l2_demand_data_read_mpi", + "LegacyName": "metric_L2 demand data read MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, D-side", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_data_read_mpi_demand_plus_prefetch", + "LegacyName": "metric_LLC data read MPI (demand+prefetch)", + "Level": 1, + "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", + "Alias": "c" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "(a + b + c) / d", + "Category": "MPI, D-side", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_code_read_mpi_demand_plus_prefetch", + "LegacyName": "metric_LLC code read MPI (demand+prefetch)", + "Level": 1, + "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", + "Alias": "b" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "(a + b) / d", + "Category": "MPI, I-side", + "ResolutionLevels": "SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_demand_data_read_miss_latency", + "LegacyName": "metric_Average LLC demand data read miss latency (in ns)", + "Level": 1, + "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds", + "UnitOfMeasure": "ns", + "Events": [ + { + "Name": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", + "Alias": "b" + }, + { + "Name": "UNC_CHA_CLOCKTICKS", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "CHAS_PER_SOCKET", + "Alias": "d" + }, + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "( 1000000000 * (a / b) / (c / (d * socket_count) ) ) * DURATIONTIMEINSECONDS", + "Category": "Latency", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "itlb_2nd_level_mpi", + "LegacyName": "metric_ITLB (2nd level) MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, I-side", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "itlb_2nd_level_large_page_mpi", + "LegacyName": "metric_ITLB (2nd level) large page MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "dtlb_2nd_level_load_mpi", + "LegacyName": "metric_DTLB (2nd level) load MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, D-side", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi", + "LegacyName": "metric_DTLB (2nd level) 2MB large page load MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, D-side", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "dtlb_2nd_level_store_mpi", + "LegacyName": "metric_DTLB (2nd level) store MPI", + "Level": 1, + "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", + "UnitOfMeasure": "per instruction", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "Category": "MPI, D-side", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_read", + "LegacyName": "metric_IO_bandwidth_disk_or_network_writes (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_write", + "LegacyName": "metric_IO_bandwidth_disk_or_network_reads (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_read_l3_miss", + "LegacyName": "metric_IO % of inbound reads that miss L3", + "Level": 1, + "BriefDescription": "The percent of inbound reads initiated by IO that miss the L3 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_partial_write_l3_miss", + "LegacyName": "metric_IO % of inbound partial writes that miss L3", + "Level": 1, + "BriefDescription": "The percent of inbound partial writes initiated by IO that miss the L3 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_RFO", + "Alias": "c" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ((b + d) / (a + c) )", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_full_write_l3_miss", + "LegacyName": "metric_IO % of inbound full writes that miss L3", + "Level": 1, + "BriefDescription": "The percent of inbound full cache line writes initiated by IO that miss the L3 cache.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * (b / a)", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_read_local", + "LegacyName": "metric_IO bandwidth read local (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the local CPU socket.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_read_remote", + "LegacyName": "metric_IO bandwidth read remote (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from a remote CPU socket.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_write_local", + "LegacyName": "metric_IO bandwidth write local (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the local CPU socket.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_write_remote", + "LegacyName": "metric_IO bandwidth write remote (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to a remote CPU socket.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW, IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_msi", + "LegacyName": "metric_IO MSI per sec", + "Level": 1, + "BriefDescription": "Message Signaled Interrupts (MSI) per second sent by the integrated I/O traffic controller (IIO) to System Configuration Controller (Ubox).", + "UnitOfMeasure": "per second", + "Events": [ + { + "Name": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX_POSTED", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a) / DURATIONTIMEINSECONDS", + "Category": "IO", + "ResolutionLevels": "IIO, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_miss_local_memory_bandwidth_read", + "LegacyName": "metric_llc_miss_local_memory_bandwidth_read_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.READS_LOCAL", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_miss_local_memory_bandwidth_write", + "LegacyName": "metric_llc_miss_local_memory_bandwidth_write_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.WRITES_LOCAL", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_miss_remote_memory_bandwidth_read", + "LegacyName": "metric_llc_miss_remote_memory_bandwidth_read_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.READS_REMOTE", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "llc_miss_remote_memory_bandwidth_write", + "LegacyName": "metric_llc_miss_remote_memory_bandwidth_write_MB/s", + "Level": 1, + "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_REQUESTS.WRITES_REMOTE", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "BW", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "iio_bandwidth_read", + "LegacyName": "metric_IIO_bandwidth_read (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth observed by the integrated I/O traffic contoller (IIO) of IO reads that are initiated by end device controllers that are requesting memory from the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 4 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "IO, BW", + "ResolutionLevels": "IIO, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "iio_bandwidth_write", + "LegacyName": "metric_IIO_bandwidth_write (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth observed by the integrated I/O traffic controller (IIO) of IO writes that are initiated by end device controllers that are writing memory to the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 4 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "IO, BW", + "ResolutionLevels": "IIO, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "cpu_cstate_c0", + "LegacyName": "metric_CPU_cstate_C0", + "Level": 1, + "BriefDescription": "The average number of cores that are in cstate C0 as observed by the power control unit (PCU).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_P_CLOCKTICKS", + "Alias": "a" + }, + { + "Name": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C0", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "(b / a[0]) * socket_count", + "Category": "Power", + "ResolutionLevels": "SOCKET, SYSTEM, PCU", + "MetricGroup": "cpu_cstate" + }, + { + "MetricName": "cpu_cstate_c6", + "LegacyName": "metric_CPU_cstate_C6", + "Level": 1, + "BriefDescription": "The average number of cores that are in cstate C6 as observed by the power control unit (PCU).", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "UNC_P_CLOCKTICKS", + "Alias": "a" + }, + { + "Name": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C6", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "SOCKET_COUNT", + "Alias": "socket_count" + } + ], + "Formula": "(b / a[0]) * socket_count", + "Category": "Power", + "ResolutionLevels": "SOCKET, SYSTEM, PCU", + "MetricGroup": "cpu_cstate" + }, + { + "MetricName": "io_bandwidth_read_l3_miss", + "LegacyName": "metric_IO_bandwidth_read_L3_miss (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of inbound IO reads that are initiated by end device controllers that are requesting memory from the CPU and miss the L3 cache.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "Alias": "a" + } + ], + "Constants": [], + "Formula": "(a * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "io_bandwidth_write_l3_miss", + "LegacyName": "metric_IO_bandwidth_write_L3_miss (MB/sec)", + "Level": 1, + "BriefDescription": "Bandwidth of inbound IO writes that are initiated by end device controllers that are writing memory to the CPU.", + "UnitOfMeasure": "MB/sec", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "((a + b) * 64 / 1000000) / DURATIONTIMEINSECONDS", + "Category": "IO", + "ResolutionLevels": "CHA, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Frontend_Bound", + "LegacyName": "metric_TMA_Frontend_Bound(%)", + "Level": 1, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to frontend stalls.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.ALL_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.all_p / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "IFetch_Latency", + "LegacyName": "metric_TMA_..IFetch_Latency(%)", + "ParentCategory": "Frontend_Bound", + "Level": 2, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend latency restrictions due to icache misses, itlb misses, branch detection, and resteer limitations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.frontend_latency / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_..IFetch_Latency(%) >0.15 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "ICache_Misses", + "LegacyName": "metric_TMA_....ICache_Misses(%)", + "ParentCategory": "IFetch_Latency", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.ICACHE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.icache / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....ICache_Misses(%) >0.05 && metric_TMA_..IFetch_Latency(%) >0.15 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "ITLB_Misses", + "LegacyName": "metric_TMA_....ITLB_Misses(%)", + "ParentCategory": "IFetch_Latency", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.ITLB_MISS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.itlb_miss / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....ITLB_Misses(%) >0.05 && metric_TMA_..IFetch_Latency(%) >0.15 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Branch_Detect", + "LegacyName": "metric_TMA_....Branch_Detect(%)", + "ParentCategory": "IFetch_Latency", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.BRANCH_DETECT", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.branch_detect / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Branch_Detect(%) >0.05 && metric_TMA_..IFetch_Latency(%) >0.15 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Branch_Resteer", + "LegacyName": "metric_TMA_....Branch_Resteer(%)", + "ParentCategory": "IFetch_Latency", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.branch_resteer / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Branch_Resteer(%) >0.05 && metric_TMA_..IFetch_Latency(%) >0.15 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "IFetch_Bandwidth", + "LegacyName": "metric_TMA_..IFetch_Bandwidth(%)", + "ParentCategory": "Frontend_Bound", + "Level": 2, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.frontend_bandwidth / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_..IFetch_Bandwidth(%) >0.10 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Cisc", + "LegacyName": "metric_TMA_....Cisc(%)", + "ParentCategory": "IFetch_Bandwidth", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS).", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.CISC", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.cisc / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Cisc(%) >0.05 && metric_TMA_..IFetch_Bandwidth(%) >0.10 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Decode", + "LegacyName": "metric_TMA_....Decode(%)", + "ParentCategory": "IFetch_Bandwidth", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to decode stalls.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.DECODE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.decode / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Decode(%) >0.05 && metric_TMA_..IFetch_Bandwidth(%) >0.10 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Predecode", + "LegacyName": "metric_TMA_....Predecode(%)", + "ParentCategory": "IFetch_Bandwidth", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.PREDECODE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.predecode / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Predecode(%) >0.05 && metric_TMA_..IFetch_Bandwidth(%) >0.10 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Other_FB", + "LegacyName": "metric_TMA_....Other_FB(%)", + "ParentCategory": "IFetch_Bandwidth", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_FE_BOUND.OTHER", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_fe_bound.other / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Other_FB(%) >0.05 && metric_TMA_..IFetch_Bandwidth(%) >0.10 && metric_TMA_Frontend_Bound(%) >0.20" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Bad_Speculation", + "LegacyName": "metric_TMA_Bad_Speculation(%)", + "Level": 1, + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BAD_SPECULATION.ALL_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_bad_speculation.all_p / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_Bad_Speculation(%) >0.15" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Branch_Mispredicts", + "LegacyName": "metric_TMA_..Branch_Mispredicts(%)", + "ParentCategory": "Bad_Speculation", + "Level": 2, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to branch mispredicts", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BAD_SPECULATION.MISPREDICT", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_bad_speculation.mispredict / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_..Branch_Mispredicts(%) >0.05 && metric_TMA_Bad_Speculation(%) >0.15" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Machine_Clears", + "LegacyName": "metric_TMA_..Machine_Clears(%)", + "ParentCategory": "Bad_Speculation", + "Level": 2, + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_bad_speculation.machine_clears / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_..Machine_Clears(%) >0.05 && metric_TMA_Bad_Speculation(%) >0.15" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Nuke", + "LegacyName": "metric_TMA_....Nuke(%)", + "ParentCategory": "Machine_Clears", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear that requires the use of microcode (slow nuke)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BAD_SPECULATION.NUKE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_bad_speculation.nuke / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Nuke(%) >0.05 && metric_TMA_..Machine_Clears(%) >0.05 && metric_TMA_Bad_Speculation(%) >0.15" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Fast_Nuke", + "LegacyName": "metric_TMA_....Fast_Nuke(%)", + "ParentCategory": "Machine_Clears", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear that does not require the use of microcode, classified as a fast nuke, due to memory ordering, memory disambiguation and memory renaming", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BAD_SPECULATION.FASTNUKE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_bad_speculation.fastnuke / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Fast_Nuke(%) >0.05 && metric_TMA_..Machine_Clears(%) >0.05 && metric_TMA_Bad_Speculation(%) >0.15" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Backend_Bound", + "LegacyName": "metric_TMA_Backend_Bound(%)", + "Level": 1, + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BE_BOUND.ALL_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_be_bound.all_p / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_Backend_Bound(%) >0.10" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Core_Bound", + "LegacyName": "metric_TMA_..Core_Bound(%)", + "ParentCategory": "Backend_Bound", + "Level": 2, + "BriefDescription": "Counts the number of cycles due to backend bound stalls that are bounded by core restrictions and not attributed to an outstanding load or stores, or resource limitation", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_be_bound.alloc_restrictions / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_..Core_Bound(%) >0.10 && metric_TMA_Backend_Bound(%) >0.10" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Allocation_Restriction", + "LegacyName": "metric_TMA_....Allocation_Restriction(%)", + "ParentCategory": "Core_Bound", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to certain allocation restrictions", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_be_bound.alloc_restrictions / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Allocation_Restriction(%) >0.10 && metric_TMA_..Core_Bound(%) >0.10 && metric_TMA_Backend_Bound(%) >0.10" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Resource_Bound", + "LegacyName": "metric_TMA_..Resource_Bound(%)", + "ParentCategory": "Backend_Bound", + "Level": 2, + "BriefDescription": "Counts the number of cycles the core is stalled due to a resource limitation", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BE_BOUND.ALL_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + }, + { + "Name": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( ( ( a / ( ( 6 ) * ( b ) ) ) - ( c / ( ( 6 ) * ( b ) ) ) ) )", + "BaseFormula": " ( ( topdown_be_bound.all_p / ( ( 6 ) * ( cpu_clk_unhalted.core ) ) ) - tma_core_bound )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_..Resource_Bound(%) >0.20 && metric_TMA_Backend_Bound(%) >0.10" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Mem_Scheduler", + "LegacyName": "metric_TMA_....Mem_Scheduler(%)", + "ParentCategory": "Resource_Bound", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_be_bound.mem_scheduler / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Mem_Scheduler(%) >0.10 && metric_TMA_..Resource_Bound(%) >0.20 && metric_TMA_Backend_Bound(%) >0.10" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Non_Mem_Scheduler", + "LegacyName": "metric_TMA_....Non_Mem_Scheduler(%)", + "ParentCategory": "Resource_Bound", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_be_bound.non_mem_scheduler / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Non_Mem_Scheduler(%) >0.10 && metric_TMA_..Resource_Bound(%) >0.20 && metric_TMA_Backend_Bound(%) >0.10" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Register", + "LegacyName": "metric_TMA_....Register(%)", + "ParentCategory": "Resource_Bound", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BE_BOUND.REGISTER", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_be_bound.register / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Register(%) >0.10 && metric_TMA_..Resource_Bound(%) >0.20 && metric_TMA_Backend_Bound(%) >0.10" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Reorder_Buffer", + "LegacyName": "metric_TMA_....Reorder_Buffer(%)", + "ParentCategory": "Resource_Bound", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BE_BOUND.REORDER_BUFFER", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_be_bound.reorder_buffer / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Reorder_Buffer(%) >0.10 && metric_TMA_..Resource_Bound(%) >0.20 && metric_TMA_Backend_Bound(%) >0.10" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Serialization", + "LegacyName": "metric_TMA_....Serialization(%)", + "ParentCategory": "Resource_Bound", + "Level": 3, + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS)", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_BE_BOUND.SERIALIZATION", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_be_bound.serialization / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_....Serialization(%) >0.10 && metric_TMA_..Resource_Bound(%) >0.20 && metric_TMA_Backend_Bound(%) >0.10" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Retiring", + "LegacyName": "metric_TMA_Retiring(%)", + "Level": 1, + "BriefDescription": "Counts the number of issue slots that result in retirement slots", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "TOPDOWN_RETIRING.ALL_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * ( a / ( ( 6 ) * ( b ) ) )", + "BaseFormula": " topdown_retiring.all_p / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "Slots", + "Threshold": { + "Formula": "metric_TMA_Retiring(%) >0.75" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Bottleneck_Mem_Exec_Bound_Cycles", + "LegacyName": "metric_TMA_Info_Bottleneck_%_Mem_Exec_Bound_Cycles", + "Level": 1, + "BriefDescription": "Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall. See Info.Mem_Exec_Bound", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "LD_HEAD.ANY_AT_RET", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / ( b )", + "BaseFormula": " 100 * ld_head.any_at_ret / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "Cycles", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Mem_Exec" + }, + { + "MetricName": "Info_Bottleneck_Load_Miss_Bound_Cycles", + "LegacyName": "metric_TMA_Info_Bottleneck_%_Load_Miss_Bound_Cycles", + "Level": 1, + "BriefDescription": "Percentage of time that retirement is stalled due to an L1 miss. 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"TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Mem_Exec_Blocks_Loads_with_AdressAliasing", + "LegacyName": "metric_TMA_Info_Mem_Exec_Blocks_%_Loads_with_AdressAliasing", + "Level": 1, + "BriefDescription": "Percentage of total non-speculative loads with an address aliasing block", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "LD_BLOCKS.ADDRESS_ALIAS", + "Alias": "a" + }, + { + "Name": "MEM_UOPS_RETIRED.ALL_LOADS", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "BaseFormula": " 100 * ld_blocks.address_alias / mem_uops_retired.all_loads", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Mem_Exec_Bound_LoadHead_with_STLBHit", + "LegacyName": "metric_TMA_Info_Mem_Exec_Bound_%_LoadHead_with_STLBHit", + "Level": 1, + "BriefDescription": "Percentage of Memory Execution Bound due to a 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"ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Mem_Exec_Bound_LoadHead_with_StoreFwding", + "LegacyName": "metric_TMA_Info_Mem_Exec_Bound_%_LoadHead_with_StoreFwding", + "Level": 1, + "BriefDescription": "Percentage of Memory Execution Bound due to a store forward address match", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "LD_HEAD.ST_ADDR_AT_RET", + "Alias": "a" + }, + { + "Name": "LD_HEAD.ANY_AT_RET", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "BaseFormula": " 100 * ld_head.st_addr_at_ret / ld_head.any_at_ret", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Mem_Exec_Bound_LoadHead_with_OtherPipelineBlks", + "LegacyName": "metric_TMA_Info_Mem_Exec_Bound_%_LoadHead_with_OtherPipelineBlks", + "Level": 1, + "BriefDescription": "Percentage of Memory Execution Bound due to other block cases, such as pipeline conflicts, fences, etc", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "LD_HEAD.OTHER_AT_RET", + "Alias": "a" + }, + { + "Name": "LD_HEAD.ANY_AT_RET", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "BaseFormula": " 100 * ld_head.other_at_ret / ld_head.any_at_ret", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Mem_Exec_Bound_LoadHead_with_L1miss", + "LegacyName": "metric_TMA_Info_Mem_Exec_Bound_%_LoadHead_with_L1miss", + "Level": 1, + "BriefDescription": "Percentage of Memory Execution Bound due to a first level data cache miss", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "LD_HEAD.L1_MISS_AT_RET", + "Alias": "a" + }, + { + "Name": "LD_HEAD.ANY_AT_RET", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "BaseFormula": " 100 * ld_head.l1_miss_at_ret / ld_head.any_at_ret", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Load_Store_Bound_Store_Bound", + "LegacyName": "metric_TMA_Info_Load_Store_Bound_Store_Bound", + "Level": 1, + "BriefDescription": "Counts the number of cycles the core is stalled due to store buffer full", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MEM_SCHEDULER_BLOCK.ST_BUF", + "Alias": "a" + }, + { + "Name": "MEM_SCHEDULER_BLOCK.ALL", + "Alias": "b" + }, + { + "Name": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", + "Alias": "c" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "d" + } + ], + "Constants": [], + "Formula": "100 * ( a / b ) * ( c / ( ( 6 ) * ( d ) ) )", + "BaseFormula": " 100 * ( mem_scheduler_block.st_buf / mem_scheduler_block.all ) * ( topdown_be_bound.mem_scheduler / ( ( 6 ) * ( cpu_clk_unhalted.core ) ) )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "load_store_bound" + }, + { + "MetricName": "Info_Load_Store_Bound_Load_Bound", + "LegacyName": "metric_TMA_Info_Load_Store_Bound_Load_Bound", + "Level": 1, + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "LD_HEAD.L1_BOUND_AT_RET", + "Alias": "a" + }, + { + "Name": "MEM_BOUND_STALLS_LOAD.ALL", + "Alias": "b" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "c" + } + ], + "Constants": [], + "Formula": "100 * ( a + b ) / ( c )", + "BaseFormula": " 100 * ( ld_head.l1_bound_at_ret + mem_bound_stalls_load.all ) / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "load_store_bound" + }, + { + "MetricName": "Info_Load_Store_Bound_L1_Bound", + "LegacyName": "metric_TMA_Info_Load_Store_Bound_L1_Bound", + "Level": 1, + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a pipeline block", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "LD_HEAD.L1_BOUND_AT_RET", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / ( b )", + "BaseFormula": " 100 * ld_head.l1_bound_at_ret / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "load_store_bound" + }, + { + "MetricName": "Info_Load_Miss_Bound_LoadMissBound_with_L2Hit", + "LegacyName": "metric_TMA_Info_Load_Miss_Bound_%_LoadMissBound_with_L2Hit", + "Level": 1, + "BriefDescription": "Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L2", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_BOUND_STALLS_LOAD.L2_HIT", + "Alias": "a" + }, + { + "Name": "MEM_BOUND_STALLS_LOAD.ALL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "BaseFormula": " 100 * mem_bound_stalls_load.l2_hit / mem_bound_stalls_load.all", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "load_store_bound" + }, + { + "MetricName": "Info_Load_Miss_Bound_LoadMissBound_with_L3Hit", + "LegacyName": "metric_TMA_Info_Load_Miss_Bound_%_LoadMissBound_with_L3Hit", + "Level": 1, + "BriefDescription": "Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L3", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_BOUND_STALLS_LOAD.LLC_HIT", + "Alias": "a" + }, + { + "Name": "MEM_BOUND_STALLS_LOAD.ALL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "BaseFormula": " 100 * mem_bound_stalls_load.llc_hit / mem_bound_stalls_load.all", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "load_store_bound" + }, + { + "MetricName": "Info_Ifetch_Miss_Bound_IfetchMissBound_with_L2Hit", + "LegacyName": "metric_TMA_Info_Ifetch_Miss_Bound_%_IfetchMissBound_with_L2Hit", + "Level": 1, + "BriefDescription": "Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L2", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_BOUND_STALLS_IFETCH.L2_HIT", + "Alias": "a" + }, + { + "Name": "MEM_BOUND_STALLS_IFETCH.ALL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / ( b )", + "BaseFormula": " 100 * mem_bound_stalls_ifetch.l2_hit / ( mem_bound_stalls_ifetch.all )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Ifetch_Miss_Bound_IfetchMissBound_with_L3Hit", + "LegacyName": "metric_TMA_Info_Ifetch_Miss_Bound_%_IfetchMissBound_with_L3Hit", + "Level": 1, + "BriefDescription": "Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L3", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_BOUND_STALLS_IFETCH.LLC_HIT", + "Alias": "a" + }, + { + "Name": "MEM_BOUND_STALLS_IFETCH.ALL", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / ( b )", + "BaseFormula": " 100 * mem_bound_stalls_ifetch.llc_hit / ( mem_bound_stalls_ifetch.all )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Br_Mispredict_Bound_Branch_Mispredict_Ratio", + "LegacyName": "metric_TMA_Info_Br_Mispredict_Bound_Branch_Mispredict_Ratio", + "Level": 1, + "BriefDescription": "Ratio of all branches which mispredict", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " br_misp_retired.all_branches / br_inst_retired.all_branches", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Br_Mispredict_Bound_Branch_Mispredict_to_Unknown_Branch_Ratio", + "LegacyName": "metric_TMA_Info_Br_Mispredict_Bound_Branch_Mispredict_to_Unknown_Branch_Ratio", + "Level": 1, + "BriefDescription": "Ratio between Mispredicted branches and unknown branches", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BACLEARS.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "BaseFormula": " br_misp_retired.all_branches / baclears.any", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Machine_Clear_Bound_Machine_Clears_FP_Assist_PKI", + "LegacyName": "metric_TMA_Info_Machine_Clear_Bound_Machine_Clears_FP_Assist_PKI", + "Level": 1, + "BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to floating point assists", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MACHINE_CLEARS.FP_ASSIST", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": " 1000 * machine_clears.fp_assist / inst_retired.any", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Machine_Clear_Bound_Machine_Clears_Page_Fault_PKI", + "LegacyName": "metric_TMA_Info_Machine_Clear_Bound_Machine_Clears_Page_Fault_PKI", + "Level": 1, + "BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to page faults", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MACHINE_CLEARS.PAGE_FAULT", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": " 1000 * machine_clears.page_fault / inst_retired.any", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Machine_Clear_Bound_Machine_Clears_SMC_PKI", + "LegacyName": "metric_TMA_Info_Machine_Clear_Bound_Machine_Clears_SMC_PKI", + "Level": 1, + "BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to self-modifying code", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "MACHINE_CLEARS.SMC", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "1000 * a / b", + "BaseFormula": " 1000 * machine_clears.smc / inst_retired.any", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Buffer_Stalls_Store_Buffer_Stall_Cycles", + "LegacyName": "metric_TMA_Info_Buffer_Stalls_%_Store_Buffer_Stall_Cycles", + "Level": 1, + "BriefDescription": "Percentage of time that allocation is stalled due to store buffer full", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_SCHEDULER_BLOCK.ST_BUF", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / ( b )", + "BaseFormula": " 100 * mem_scheduler_block.st_buf / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Buffer_Stalls_Load_Buffer_Stall_Cycles", + "LegacyName": "metric_TMA_Info_Buffer_Stalls_%_Load_Buffer_Stall_Cycles", + "Level": 1, + "BriefDescription": "Percentage of time that allocation is stalled due to load buffer full", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_SCHEDULER_BLOCK.LD_BUF", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / ( b )", + "BaseFormula": " 100 * mem_scheduler_block.ld_buf / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Buffer_Stalls_Mem_RSV_Stall_Cycles", + "LegacyName": "metric_TMA_Info_Buffer_Stalls_%_Mem_RSV_Stall_Cycles", + "Level": 1, + "BriefDescription": "Percentage of time that allocation is stalled due to memory reservation stations full", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "MEM_SCHEDULER_BLOCK.RSV", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / ( b )", + "BaseFormula": " 100 * mem_scheduler_block.rsv / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_Serialization_Tpause_Cycles", + "LegacyName": "metric_TMA_Info_Serialization _%_Tpause_Cycles", + "Level": 1, + "BriefDescription": "Percentage of time that the core is stalled due to a TPAUSE or UMWAIT instruction ", + "UnitOfMeasure": "percent", + "Events": [ + { + "Name": "SERIALIZATION.C01_MS_SCB", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / ( ( 6 ) * ( b ) )", + "BaseFormula": " 100 * serialization.c01_ms_scb / ( ( 6 ) * ( cpu_clk_unhalted.core ) )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_System_Turbo_Utilization", + "LegacyName": "metric_TMA_Info_System_Turbo_Utilization", + "Level": 1, + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / b", + "BaseFormula": " ( cpu_clk_unhalted.core ) / cpu_clk_unhalted.ref_tsc", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_System_Kernel_Utilization", + "LegacyName": "metric_TMA_Info_System_Kernel_Utilization", + "Level": 1, + "BriefDescription": "Fraction of cycles spent in Kernel mode", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.CORE_P:sup", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / ( b )", + "BaseFormula": " cpu_clk_unhalted.core_p:sup / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_System_CPU_Utilization", + "LegacyName": "metric_TMA_Info_System_CPU_Utilization", + "Level": 1, + "BriefDescription": "Average CPU Utilization", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.REF_TSC", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "SYSTEM_TSC_FREQ", + "Alias": "b" + } + ], + "Formula": "a / b", + "BaseFormula": " cpu_clk_unhalted.ref_tsc / tsc", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_System_MUX", + "LegacyName": "metric_TMA_Info_System_MUX", + "Level": 1, + "BriefDescription": "PerfMon Event Multiplexing accuracy indicator", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.CORE_P", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.CORE", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "( a ) / ( b )", + "BaseFormula": " ( cpu_clk_unhalted.core_p ) / ( cpu_clk_unhalted.core )", + "Category": "TMA", + "CountDomain": "", + "Threshold": { + "Formula": "metric_TMA_Info_System_MUX > 1.1 || metric_TMA_Info_System_MUX < 0.9" + }, + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "" + }, + { + "MetricName": "Info_System_GFLOPs", + "LegacyName": "metric_TMA_Info_System_GFLOPs", + "Level": 1, + "BriefDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width", + "UnitOfMeasure": "", + "Events": [ + { + "Name": "FP_FLOPS_RETIRED.ALL", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "DURATIONTIMEINMILLISECONDS", + "Alias": "durationtimeinmilliseconds" + } + ], + "Formula": "a / ( ( durationtimeinmilliseconds / 1000 ) * 1000000000 )", + "BaseFormula": " fp_flops_retired.all / ( ( duration_time ) * 1000000000 )", + "Category": "TMA", + "CountDomain": "", + "ResolutionLevels": "CORE, SOCKET, SYSTEM", + "MetricGroup": "Flops" + } + ] +} \ No newline at end of file diff --git a/cmd/metrics/resources/perfmon/srf/sierraforest_uncore.json b/cmd/metrics/resources/perfmon/srf/sierraforest_uncore.json new file mode 100644 index 00000000..48302665 --- /dev/null +++ b/cmd/metrics/resources/perfmon/srf/sierraforest_uncore.json @@ -0,0 +1,6005 @@ +{ + "Header": { + "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", + "Info": "Performance Monitoring Events for Intel(R) Xeon(R) 6 Processor with E-cores - V1.11", + "DatePublished": "05/16/2025", + "Version": "1.11", + "Legend": "" + }, + "Events": [ + { + "Unit": "B2CMI", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_CLOCKTICKS", + "BriefDescription": "Clockticks of the mesh to memory (B2CMI)", + "PublicDescription": "Clockticks of the mesh to memory (B2CMI)", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x24", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000001", + "EventName": "UNC_B2CMI_IMC_READS.NORMAL", + "BriefDescription": "Counts normal reads issue to CMI", + "PublicDescription": "Counts normal reads issue to CMI", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x24", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000001", + "EventName": "UNC_B2CMI_IMC_READS.ALL", + "BriefDescription": "Counts any read", + "PublicDescription": "Counts any read", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x25", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000001", + "EventName": "UNC_B2CMI_IMC_WRITES.FULL", + "BriefDescription": "Full Non-ISOCH - All Channels", + "PublicDescription": "Full Non-ISOCH - All Channels", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x25", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000001", + "EventName": "UNC_B2CMI_IMC_WRITES.PARTIAL", + "BriefDescription": "Partial Non-ISOCH - All Channels", + "PublicDescription": "Partial Non-ISOCH - All Channels", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x25", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000001", + "EventName": "UNC_B2CMI_IMC_WRITES.ALL", + "BriefDescription": "All Writes - All Channels", + "PublicDescription": "All Writes - All Channels", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x33", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_TRACKER_OCCUPANCY.CH0", + "BriefDescription": "Tracker Occupancy : Channel 0", + "PublicDescription": "Tracker Occupancy : Channel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x56", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_PREFCAM_INSERTS.UPI_ALLCH", + "BriefDescription": "Prefetch CAM Inserts : UPI - All Channels", + "PublicDescription": "Prefetch CAM Inserts : UPI - All Channels", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x56", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_PREFCAM_INSERTS.XPT_ALLCH", + "BriefDescription": "Prefetch CAM Inserts : XPT -All Channels", + "PublicDescription": "Prefetch CAM Inserts : XPT - All Channels", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x21", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000003", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.ANY", + "BriefDescription": "Counts cisgress directory updates", + "PublicDescription": "Counts cisgress directory updates", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x21", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000003", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.I2S", + "BriefDescription": "Any I2S Transition", + "PublicDescription": "Any I2S Transition", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x21", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000003", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.I2A", + "BriefDescription": "Any I2A Transition", + "PublicDescription": "Any I2A Transition", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x21", + "UMask": "0x20", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000003", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.A2I", + "BriefDescription": "Any A2I Transition", + "PublicDescription": "Any A2I Transition", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x21", + "UMask": "0x40", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000003", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.A2S", + "BriefDescription": "Any A2S Transition", + "PublicDescription": "Any A2S Transition", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x20", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECTORY_LOOKUP.ANY", + "BriefDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with any directory to non persistent memory", + "PublicDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with any directory to non persistent memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x20", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECTORY_LOOKUP.STATE_I", + "BriefDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with directory I to non persistent memory", + "PublicDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with directory I to non persistent memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x20", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECTORY_LOOKUP.STATE_S", + "BriefDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with directory S to non persistent memory", + "PublicDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with directory S to non persistent memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x20", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECTORY_LOOKUP.STATE_A", + "BriefDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with directory A to non persistent memory", + "PublicDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with directory A to non persistent memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x1A", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECT2UPI_NOT_TAKEN_DIRSTATE.EGRESS", + "BriefDescription": "Cycles when Direct2UPI was Disabled : Egress Ignored D2U : Counts the number of time D2K was not honoured by egress due to directory state constraints", + "PublicDescription": "Cycles when Direct2UPI was Disabled : Egress Ignored D2U", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x1B", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECT2UPI_NOT_TAKEN_CREDITS.EGRESS", + "BriefDescription": "Direct to UPI Transactions - Ignored due to lack of credits : All : Counts the number of d2k wasn't done due to credit constraints", + "PublicDescription": "Direct to UPI Transactions - Ignored due to lack of credits : All", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_CLOCKTICKS", + "BriefDescription": "Number of CHA clock cycles while the event is enabled", + "PublicDescription": "Clockticks of the uncore caching and home agent (CHA)", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C80FFD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", + "BriefDescription": "Code read from local IA that hit the cache", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCC7FD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO", + "BriefDescription": "Last level cache prefetch read for ownership from local IA that hit the cache", + "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C807FD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", + "BriefDescription": "Read for ownership from local IA that hit the cache", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C001FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", + "BriefDescription": "All locally initiated requests from IA Cores which miss the cache", + "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C80FFE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "BriefDescription": "Code read from local IA that miss the cache", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCC7FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO", + "BriefDescription": "Last level cache prefetch read for ownership from local IA that miss the cache", + "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C807FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", + "BriefDescription": "Read for ownership from local IA that miss the cache", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC43FE", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "BriefDescription": "All TOR ItoM inserts from local IO devices which miss the cache", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C803FE", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "BriefDescription": "All TOR RFO inserts from local IO devices which miss the cache", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C88FFD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF", + "BriefDescription": "Code read prefetch from local IA that hit the cache", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C827FD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT", + "BriefDescription": "Data read opt from local IA that hit the cache", + "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8A7FD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF", + "BriefDescription": "Data read opt prefetch from local IA that hit the cache", + "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C887FD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF", + "BriefDescription": "Read for ownership prefetch from local IA that hit the cache", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C88FFE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", + "BriefDescription": "Code read prefetch from local IA that miss the cache", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C827FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", + "BriefDescription": "Data read opt from local IA that miss the cache", + "PublicDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8A7FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF", + "BriefDescription": "Data read opt prefetch from local IA that miss the cache", + "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C887FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", + "BriefDescription": "Read for ownership prefetch from local IA that miss the cache", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC43FD", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", + "BriefDescription": "ItoMs from local IO devices which hit the cache", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C803FD", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO", + "BriefDescription": "RFOs from local IO devices which hit the cache", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C803FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO", + "BriefDescription": "RFOs from local IO devices", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC43FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "BriefDescription": "All TOR ItoM inserts from local IO devices", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C887FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF", + "BriefDescription": "Read for ownership prefetch from local IA", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C807FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO", + "BriefDescription": "Read for ownership from local IA", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCC7FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO", + "BriefDescription": "Last level cache prefetch read for ownership from local IA", + "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C827FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT", + "BriefDescription": "Data read opt from local IA", + "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8A7FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF", + "BriefDescription": "Data read opt prefetch from local IA", + "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C88FFF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF", + "BriefDescription": "Code read prefetch from local IA that miss the cache", + "PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filter", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C80FFF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD", + "BriefDescription": "Code read from local IA", + "PublicDescription": "TOR Inserts : CRDs issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C806FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL", + "BriefDescription": "Read for ownership from local IA that miss the LLC targeting local memory", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8077E", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE", + "BriefDescription": "Read for ownership from local IA that miss the LLC targeting remote memory", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C886FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL", + "BriefDescription": "Read for ownership prefetch from local IA that miss the LLC targeting local memory", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8877E", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE", + "BriefDescription": "Read for ownership prefetch from local IA that miss the LLC targeting remote memory", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8C7FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH", + "BriefDescription": "CLFlush events that are initiated from the Core", + "PublicDescription": "TOR Inserts : CLFlushes issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8D7FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT", + "BriefDescription": "CLFlushOpt events that are initiated from the Core", + "PublicDescription": "TOR Inserts : CLFlushOpts issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC47FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOM", + "BriefDescription": "ItoM events that are initiated from the Core", + "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC57FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM", + "BriefDescription": "SpecItoM events that are initiated from the Core", + "PublicDescription": "TOR Inserts : SpecItoMs issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD43FD", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", + "BriefDescription": "ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD43FE", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "BriefDescription": "ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC3FFF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE", + "BriefDescription": "WbEFtoEs issued by iA Cores. (Non Modified Write Backs)", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8F3FD", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR", + "BriefDescription": "PCIRDCURs issued by IO devices which hit the LLC", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8F3FE", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "BriefDescription": "PCIRDCURs issued by IO devices which miss the LLC", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8F3FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "BriefDescription": "PCIRDCURs issued by IO devices", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCCFFD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE", + "BriefDescription": "Last level cache prefetch code read from local IA that hit the cache", + "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCD7FD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA", + "BriefDescription": "Last level cache prefetch data read from local IA that hit the cache", + "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCD7FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA", + "BriefDescription": "Last level cache prefetch data read from local IA.", + "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCCFFE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE", + "BriefDescription": "Last level cache prefetch code read from local IA that miss the cache", + "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCD7FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", + "BriefDescription": "Last level cache prefetch data read from local IA that miss the cache", + "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCCFFF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE", + "BriefDescription": "Last level cache prefetch code read from local IA.", + "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD43FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "BriefDescription": "ItoMCacheNears, indicating a partial write request, from IO Devices", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C80EFE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL", + "BriefDescription": "CRDs from local IA cores to locally homed memory", + "PublicDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C80F7E", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_REMOTE", + "BriefDescription": "CRDs from local IA cores to remotely homed memory", + "PublicDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C88EFE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL", + "BriefDescription": "CRD Prefetches from local IA cores to locally homed memory", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C88F7E", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_REMOTE", + "BriefDescription": "CRD Prefetches from local IA cores to remotely homed memory", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD47FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR", + "BriefDescription": "ItoMCacheNear requests from local IA cores", + "PublicDescription": "TOR Inserts : ItoMCacheNears issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC27FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI", + "BriefDescription": "WbMtoI requests from local IA cores", + "PublicDescription": "TOR Inserts : WbMtoIs issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC47FD", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_ITOM", + "BriefDescription": "ItoM requests from local IA cores that hit the cache", + "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores that Hit LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC47FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_ITOM", + "BriefDescription": "ItoM requests from local IA cores that miss the cache", + "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores that Missed LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C877DE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF", + "BriefDescription": "UCRDF requests from local IA cores that miss the cache", + "PublicDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C87FDE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL", + "BriefDescription": "WIL requests from local IA cores that miss the cache", + "PublicDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C867FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF", + "BriefDescription": "WCILF requests from local IA core", + "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C867FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF", + "BriefDescription": "WCILF requests from local IA core that miss the cache", + "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86786", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR", + "BriefDescription": "WCILF requests from local IA cores to DDR homed addresses which miss the cache", + "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86686", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR", + "BriefDescription": "WCILF requests from local IA cores to locally homed DDR addresses that miss the cache", + "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86706", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR", + "BriefDescription": "WCILF requests from local IA cores to remotely homed DDR addresses that miss the cache", + "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86FFF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL", + "BriefDescription": "WCIL requests from a local IA core", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86FFE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL", + "BriefDescription": "WCIL requests from a local IA core that miss the cache", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86F86", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR", + "BriefDescription": "WCIL requests from local IA cores to DDR homed addresses which miss the cache", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86E86", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR", + "BriefDescription": "WCIL requests from local IA cores to locally homed DDR addresses that miss the cache", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86F06", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR", + "BriefDescription": "WCIL requests from local IA cores to remotely homed DDR addresses that miss the cache", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC23FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI", + "BriefDescription": "WBMtoI requests from IO devices", + "PublicDescription": "TOR Inserts : WbMtoIs issued by IO Devices", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8C3FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH", + "BriefDescription": "CLFlush requests from IO devices", + "PublicDescription": "TOR Inserts : CLFlushes issued by IO Devices", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC2FFF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE", + "BriefDescription": "WbMtoEs issued by iA Cores . (Modified Write Backs)", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC37FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI", + "BriefDescription": "WbEFtoIs issued by iA Cores . (Non Modified Write Backs)", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC67FF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI", + "BriefDescription": "WbStoIs issued by iA Cores . (Non Modified Write Backs)", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C81782", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_ACC", + "BriefDescription": "DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card.", + "PublicDescription": "DRds issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C80782", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_ACC", + "BriefDescription": "RFOs issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "RFOs issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C88782", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO_CXL_ACC", + "BriefDescription": "L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10CCC782", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_CXL_ACC", + "BriefDescription": "LLC RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "LLC RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C89782", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_CXL_ACC", + "BriefDescription": "L2 data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "L2 data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10CCD782", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA_CXL_ACC", + "BriefDescription": "LLC data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "LLC data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C00182", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CXL_ACC", + "BriefDescription": "All requests issued from IA cores to CXL accelerator memory regions that miss the LLC.", + "PublicDescription": "All requests issued from IA cores to CXL accelerator memory regions that miss the LLC.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C00181", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CXL_ACC", + "BriefDescription": "All requests issued from IA cores to CXL accelerator memory regions that hit the LLC.", + "PublicDescription": "All requests issued from IA cores to CXL accelerator memory regions that hit the LLC.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C80FFD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", + "BriefDescription": "TOR Occupancy for Code read from local IA that hit the cache", + "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCC7FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO", + "BriefDescription": "TOR Occupancy for Last level cache prefetch read for ownership from local IA that hit the cache", + "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C807FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "BriefDescription": "TOR Occupancy for Read for ownership from local IA that hit the cache", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C80FFE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", + "BriefDescription": "TOR Occupancy for Code read from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCC7FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO", + "BriefDescription": "TOR Occupancy for Last level cache prefetch read for ownership from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C807FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", + "BriefDescription": "TOR Occupancy for Read for ownership from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C803FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", + "BriefDescription": "TOR Occupancy for All TOR RFO inserts from local IO devices which miss the cache", + "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC43FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", + "BriefDescription": "TOR Occupancy for All TOR ItoM inserts from local IO devices which miss the cache", + "PublicDescription": "TOR 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"PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8A7FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF", + "BriefDescription": "TOR Occupancy for Data read opt prefetch from local IA that hit the cache", + "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C887FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF", + "BriefDescription": "TOR Occupancy for Read for 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"BriefDescription": "TOR Occupancy for Data read opt from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8A7FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF", + "BriefDescription": "TOR Occupancy for Data read opt prefetch from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C887FE", + 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+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM", + "BriefDescription": "TOR Occupancy for All TOR ItoM inserts from local IO devices", + "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C807FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO", + "BriefDescription": "TOR Occupancy for Read for ownership from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C887FF", + "EventName": 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}, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8877E", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE", + "BriefDescription": "TOR Occupancy for Read for ownership prefetch from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8F3FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR", + "BriefDescription": "TOR Occupancy for PCIRDCURs issued by IO devices which hit the LLC", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + 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"Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCCFFD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE", + "BriefDescription": "TOR Occupancy for Last level cache prefetch code read from local IA that hit the cache", + "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCD7FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA", + "BriefDescription": "TOR Occupancy for Last level cache prefetch data read from local IA that hit the cache", + "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCD7FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA", + "BriefDescription": "TOR Occupancy for Last level cache prefetch data read from local IA.", + "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCCFFE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE", + "BriefDescription": "TOR Occupancy for Last level cache prefetch code read from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCD7FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA", + "BriefDescription": "TOR Occupancy for Last level cache prefetch data read from local IA that miss the cache", + "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CCCFFF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE", + "BriefDescription": "TOR Occupancy for Last level cache prefetch code read from local IA.", + "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C80EFE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL", + "BriefDescription": "TOR Occupancy for CRDs from local IA cores to locally homed memory", + "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C80F7E", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_REMOTE", + "BriefDescription": "TOR Occupancy for CRDs from local IA cores to remotely homed memory", + "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C88EFE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL", + "BriefDescription": "TOR Occupancy for CRD Prefetches from local IA cores to locally homed memory", + "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C88F7E", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_REMOTE", + "BriefDescription": "TOR Occupancy for CRD Prefetches from local IA cores to remotely homed memory", + "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8C7FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH", + "BriefDescription": "TOR Occupancy for CLFlush events that are initiated from the Core", + "PublicDescription": "TOR Occupancy : CLFlushes issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8D7FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT", + "BriefDescription": "TOR Occupancy for CLFlushOpt events that are initiated from the Core", + "PublicDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD47FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR", + "BriefDescription": "TOR Occupancy for ItoMCacheNear requests from local IA cores", + "PublicDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC57FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM", + "BriefDescription": "TOR Occupancy for SpecItoM events that are initiated from the Core", + "PublicDescription": "TOR Occupancy : SpecItoMs issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC27FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI", + "BriefDescription": "TOR Occupancy for WbMtoI requests from local IA cores", + "PublicDescription": "TOR Occupancy : WbMtoIs issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC47FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOM", + "BriefDescription": "TOR Occupancy for ItoM events that are initiated from the Core", + "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC47FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM", + "BriefDescription": "TOR Occupancy for ItoM requests from local IA cores that hit the cache", + "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC47FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM", + "BriefDescription": "TOR Occupancy for ItoM requests from local IA cores that miss the cache", + "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C877DE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF", + "BriefDescription": "TOR Occupancy for UCRDF requests from local IA cores that miss the cache", + "PublicDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C87FDE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL", + "BriefDescription": "TOR Occupancy for WIL requests from local IA cores that miss the cache", + "PublicDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C867FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF", + "BriefDescription": "TOR Occupancy for WCILF requests from local IA core", + "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C867FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF", + "BriefDescription": "TOR Occupancy for WCILF requests from local IA core that miss the cache", + "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86786", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR", + "BriefDescription": "TOR Occupancy for WCILF requests from local IA cores to DDR homed addresses which miss the cache", + "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86686", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR", + "BriefDescription": "TOR Occupancy for WCILF requests from local IA cores to locally homed DDR addresses that miss the cache", + "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86706", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_DDR", + "BriefDescription": "TOR Occupancy for WCILF requests from local IA cores to remotely homed DDR addresses that miss the cache", + "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86FFF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL", + "BriefDescription": "TOR Occupancy for WCIL requests from a local IA core", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86FFE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL", + "BriefDescription": "TOR Occupancy for WCIL requests from a local IA core that miss the cache", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86F86", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR", + "BriefDescription": "TOR Occupancy for WCIL requests from local IA cores to DDR homed addresses which miss the cache", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86E86", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR", + "BriefDescription": "TOR Occupancy for WCIL requests from local IA cores to locally homed DDR addresses that miss the cache", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C86F06", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_DDR", + "BriefDescription": "TOR Occupancy for WCIL requests from local IA cores to remotely homed DDR addresses that miss the cache", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC23FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI", + "BriefDescription": "TOR Occupancy for WBMtoI requests from IO devices", + "PublicDescription": "TOR Occupancy : WbMtoIs issued by IO Devices", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8C3FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH", + "BriefDescription": "TOR Occupancy for CLFlush requests from IO devices", + "PublicDescription": "TOR Occupancy : CLFlushes issued by IO Devices", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD43FD", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR", + "BriefDescription": "TOR Occupancy for ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD43FE", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR", + "BriefDescription": "TOR Occupancy for ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD43FF", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR", + "BriefDescription": "TOR Occupancy for ItoMCacheNears, indicating a partial write request, from IO Devices", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C80782", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_ACC", + "BriefDescription": "TOR Occupancy for RFOs issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "TOR Occupancy for RFOs issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C81782", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_ACC", + "BriefDescription": "TOR Occupancy for DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card.", + "PublicDescription": "TOR Occupancy for DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C89782", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_CXL_ACC", + "BriefDescription": "TOR Occupancy for L2 data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "TOR Occupancy for L2 data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10CCD782", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA_CXL_ACC", + "BriefDescription": "TOR Occupancy for LLC data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "TOR Occupancy for LLC data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C88782", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO_CXL_ACC", + "BriefDescription": "TOR Occupancy for L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "TOR Occupancy for L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10CCC782", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_CXL_ACC", + "BriefDescription": "TOR Occupancy for LLC RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "PublicDescription": "TOR Occupancy for LLC RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C00182", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CXL_ACC", + "BriefDescription": "TOR Occupancy for All requests issued from IA cores to CXL accelerator memory regions that miss the LLC.", + "PublicDescription": "TOR Occupancy for All requests issued from IA cores to CXL accelerator memory regions that miss the LLC.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x36", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x10C00181", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CXL_ACC", + "BriefDescription": "TOR Occupancy for All requests issued from IA cores to CXL accelerator memory regions that hit the LLC.", + "PublicDescription": "TOR Occupancy for All requests issued from IA cores to CXL accelerator memory regions that hit the LLC.", + "Counter": "0", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x39", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_MISC.RFO_HIT_S", + "BriefDescription": "Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state.", + "PublicDescription": "Cbo Misc : RFO HitS", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x3d", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_SF_EVICTION.M_STATE", + "BriefDescription": "Counts snoop filter capacity evictions for entries tracking modified lines in the core's cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a core's cache replaces a tracked cacheline with a new cacheline.", + "PublicDescription": "Snoop Filter Capacity Evictions : M state", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", + "BriefDescription": "Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", + "PublicDescription": "Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.READS_REMOTE", + "BriefDescription": "Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", + "PublicDescription": "Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL", + "BriefDescription": "Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", + "PublicDescription": "Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", + "BriefDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).", + "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", + "BriefDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x20", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE", + "BriefDescription": "Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "PublicDescription": "Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x30", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.INVITOE", + "BriefDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "PublicDescription": "HA Read and Write Requests : InvalItoE", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x03", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.READS", + "BriefDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) .", + "PublicDescription": "HA Read and Write Requests : Reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x50", + "UMask": "0x0C", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REQUESTS.WRITES", + "BriefDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", + "PublicDescription": "HA Read and Write Requests : Writes", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x55", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_OSB.RFO_HITS_SNP_BCAST", + "BriefDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcast : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.", + "PublicDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcast", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x01", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CLOCKTICKS", + "BriefDescription": "Number of DRAM DCLK clock cycles while the event is enabled. DCLK is 1/4 of DRAM data rate.", + "PublicDescription": "DRAM Clockticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x02", + "UMask": "0xF7", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_ACT_COUNT.ALL", + "BriefDescription": "DRAM Activate Count : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.", + "PublicDescription": "DRAM Activate Count", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x03", + "UMask": "0xF8", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_PRE_COUNT.PGT", + "BriefDescription": "DRAM Precharge commands. : Precharge due to (?) : Counts the number of DRAM Precharge commands sent on this channel.", + "PublicDescription": "DRAM Precharge commands.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x05", + "UMask": "0xC1", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH0.RD_REG", + "BriefDescription": "CAS count for SubChannel 0 regular reads", + "PublicDescription": "CAS count for SubChannel 0 regular reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x05", + "UMask": "0xC4", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH0.RD_UNDERFILL", + "BriefDescription": "CAS count for SubChannel 0 underfill reads", + "PublicDescription": "CAS count for SubChannel 0 underfill reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x05", + "UMask": "0xCF", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH0.RD", + "BriefDescription": "CAS count for SubChannel 0, all reads", + "PublicDescription": "CAS count for SubChannel 0, all reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x05", + "UMask": "0xF0", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH0.WR", + "BriefDescription": "CAS count for SubChannel 0, all writes", + "PublicDescription": "CAS count for SubChannel 0, all writes", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x05", + "UMask": "0xFF", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH0.ALL", + "BriefDescription": "CAS count for SubChannel 0, all CAS operations", + "PublicDescription": "CAS count for SubChannel 0, all CAS operations", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x06", + "UMask": "0xC1", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH1.RD_REG", + "BriefDescription": "CAS count for SubChannel 1 regular reads", + "PublicDescription": "CAS count for SubChannel 1 regular reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x06", + "UMask": "0xC4", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH1.RD_UNDERFILL", + "BriefDescription": "CAS count for SubChannel 1 underfill reads", + "PublicDescription": "CAS count for SubChannel 1 underfill reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x06", + "UMask": "0xCF", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH1.RD", + "BriefDescription": "CAS count for SubChannel 1, all reads", + "PublicDescription": "CAS count for SubChannel 1, all reads", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x06", + "UMask": "0xF0", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH1.WR", + "BriefDescription": "CAS count for SubChannel 1, all writes", + "PublicDescription": "CAS count for SubChannel 1, all writes", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x06", + "UMask": "0xFF", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_CAS_COUNT_SCH1.ALL", + "BriefDescription": "CAS count for SubChannel 1, all CAS operations", + "PublicDescription": "CAS count for SubChannel 1, all CAS operations", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x1a", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RDB_OCCUPANCY_SCH0", + "BriefDescription": "Read buffer occupancy on subchannel 0", + "PublicDescription": "Read buffer occupancy on subchannel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x1b", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RDB_OCCUPANCY_SCH1", + "BriefDescription": "Read buffer occupancy on subchannel 1", + "PublicDescription": "Read buffer occupancy on subchannel 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x80", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_OCCUPANCY_SCH0_PCH0", + "BriefDescription": "Read pending queue occupancy for subchannel 0, pseudochannel 0", + "PublicDescription": "Read pending queue occupancy for subchannel 0, pseudochannel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x81", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_OCCUPANCY_SCH0_PCH1", + "BriefDescription": "Read pending queue occupancy for subchannel 0, pseudochannel 1", + "PublicDescription": "Read pending queue occupancy for subchannel 0, pseudochannel 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x82", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_OCCUPANCY_SCH1_PCH0", + "BriefDescription": "Read pending queue occupancy for subchannel 1, pseudochannel 0", + "PublicDescription": "Read pending queue occupancy for subchannel 1, pseudochannel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x83", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_OCCUPANCY_SCH1_PCH1", + "BriefDescription": "Read pending queue occupancy for subchannel 1, pseudochannel 1", + "PublicDescription": "Read pending queue occupancy for subchannel 1, pseudochannel 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x84", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_OCCUPANCY_SCH0_PCH0", + "BriefDescription": "Write pending queue occupancy for subchannel 0, pseudochannel 0", + "PublicDescription": "Write pending queue occupancy for subchannel 0, pseudochannel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x85", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_OCCUPANCY_SCH0_PCH1", + "BriefDescription": "Write pending queue occupancy for subchannel 0, pseudochannel 1", + "PublicDescription": "Write pending queue occupancy for subchannel 0, pseudochannel 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x86", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_OCCUPANCY_SCH1_PCH0", + "BriefDescription": "Write pending queue occupancy for subchannel 1, pseudochannel 0", + "PublicDescription": "Write pending queue occupancy for subchannel 1, pseudochannel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x87", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_OCCUPANCY_SCH1_PCH1", + "BriefDescription": "Write pending queue occupancy for subchannel 1, pseudochannel 1", + "PublicDescription": "Write pending queue occupancy for subchannel 1, pseudochannel 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CXLCM", + "EventCode": "0x41", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_DATA", + "BriefDescription": "Number of Allocation to Mem Data Packing buffer", + "PublicDescription": "Number of Allocation to Mem Data Packing buffer", + "Counter": "4,5,6,7", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CXLDP", + "EventCode": "0x02", + "UMask": "0x20", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.M2S_DATA", + "BriefDescription": "Number of Allocation to M2S Data AGF", + "PublicDescription": "Number of Allocation to M2S Data AGF", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2HOT", + "EventCode": "0x01", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2HOT_CLOCKTICKS", + "BriefDescription": "UNC_B2HOT_CLOCKTICKS", + "PublicDescription": "UNC_B2HOT_CLOCKTICKS", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x000", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_IIO_CLOCKTICKS", + "BriefDescription": "IIO Clockticks", + "PublicDescription": "IIO Clockticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x001", + "FCMask": "0x07", + "UMaskExt": "0x00070010", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x001", + "FCMask": "0x07", + "UMaskExt": "0x00070010", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x0FF", + "FCMask": "0x07", + "UMaskExt": "0x00070FF0", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS", + "BriefDescription": "Counts once for every 4 bytes read from this card to memory. This event does include reads to IO.", + "PublicDescription": "Counts once for every 4 bytes read from this card to memory. This event does include reads to IO.", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x0FF", + "FCMask": "0x07", + "UMaskExt": "0x00070FF0", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS", + "BriefDescription": "Counts once for every 4 bytes written from this card to memory. This event does include writes to IO.", + "PublicDescription": "Counts once for every 4 bytes written from this card to memory. This event does include writes to IO.", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x001", + "FCMask": "0x07", + "UMaskExt": "0x00070010", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x001", + "FCMask": "0x07", + "UMaskExt": "0x00070010", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x01", + "PortMask": "0x001", + "FCMask": "0x07", + "UMaskExt": "0x00070010", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x01", + "PortMask": "0x001", + "FCMask": "0x07", + "UMaskExt": "0x00070010", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x04", + "PortMask": "0x001", + "FCMask": "0x07", + "UMaskExt": "0x00070010", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_CLOCKTICKS", + "BriefDescription": "IRP Clockticks", + "PublicDescription": "IRP Clockticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x11", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "BriefDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.", + "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IRP", + "EventCode": "0x18", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_I_FAF_INSERTS", + "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue", + "PublicDescription": "Inbound read requests received by the IRP and inserted into the FAF queue", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_CLOCKTICKS", + "BriefDescription": "Number of UPI LL clock cycles while the event is enabled", + "PublicDescription": "Number of kfclks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x02", + "UMask": "0x0F", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", + "BriefDescription": "Valid Flits Sent : All Data : Counts number of data flits across this UPI link.", + "PublicDescription": "Valid Flits Sent : All Data", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x02", + "UMask": "0x27", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", + "BriefDescription": "All Null Flits", + "PublicDescription": "Valid Flits Sent : Idle", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x02", + "UMask": "0x47", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_TxL_FLITS.IDLE", + "BriefDescription": "Valid Flits Sent : Idle : Shows legal flit time (hides impact of L0p and L0c).", + "PublicDescription": "Valid Flits Sent", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x02", + "UMask": "0x97", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", + "BriefDescription": "Valid Flits Sent : All Non Data : Shows legal flit time (hides impact of L0p and L0c).", + "PublicDescription": "Valid Flits Sent : Null FLITs transmitted to any slot", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x03", + "UMask": "0x0F", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", + "BriefDescription": "Valid Flits Received : All Data : Shows legal flit time (hides impact of L0p and L0c).", + "PublicDescription": "Valid Flits Received : All Data", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x03", + "UMask": "0x97", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", + "BriefDescription": "Valid Flits Received : All Non Data : Shows legal flit time (hides impact of L0p and L0c).", + "PublicDescription": "Valid Flits Received : All Non Data", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x05", + "UMask": "0x08", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", + "BriefDescription": "Matches on Receive path of a UPI Port : Request", + "PublicDescription": "Matches on Receive path of a UPI Port : Request", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UPI LL", + "EventCode": "0x05", + "UMask": "0x0D", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB", + "BriefDescription": "Matches on Receive path of a UPI Port : Writeback", + "PublicDescription": "Matches on Receive path of a UPI Port : Writeback", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2UPI", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2UPI_CLOCKTICKS", + "BriefDescription": "Number of uclks in domain", + "PublicDescription": "Number of uclks in domain", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CXL", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x000", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CXL_CLOCKTICKS", + "BriefDescription": "B2CXL Clockticks", + "PublicDescription": "B2CXL Clockticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "UBOX", + "EventCode": "0x42", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", + "BriefDescription": "Message Received : MSI", + "PublicDescription": "Message Received : MSI : Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only)", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "PCU", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_P_CLOCKTICKS", + "BriefDescription": "PCU Clockticks", + "PublicDescription": "PCU Clockticks: The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "PCU", + "EventCode": "0x35", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C0", + "BriefDescription": "Number of cores in C0", + "PublicDescription": "Number of cores in C0 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "PCU", + "EventCode": "0x37", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C6", + "BriefDescription": "Number of cores in C6", + "PublicDescription": "Number of cores in C6 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x03", + "UMask": "0xFF", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_PRE_COUNT.ALL", + "BriefDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", + "PublicDescription": "DRAM Precharge commands.", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x32", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000001", + "EventName": "UNC_B2CMI_TRACKER_INSERTS.CH0", + "BriefDescription": "Tracker Inserts : Channel 0", + "PublicDescription": "Tracker Inserts : Channel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x19", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECT2UPI_TAKEN", + "BriefDescription": "Counts the number of times egress did D2K (Direct to KTI)", + "PublicDescription": "Counts the number of times egress did D2K (Direct to KTI)", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x1A", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECT2UPI_NOT_TAKEN_DIRSTATE", + "BriefDescription": "Counts the number of time D2K was not honoured by egress due to directory state constraints", + "PublicDescription": "Counts the number of time D2K was not honoured by egress due to directory state constraints", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x1B", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECT2UPI_NOT_TAKEN_CREDITS", + "BriefDescription": "Counts the number of d2k wasn't done due to credit constraints", + "PublicDescription": "Counts the number of d2k wasn't done due to credit constraints", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x1C", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECT2UPI_TXN_OVERRIDE", + "BriefDescription": "Counts the number of times D2K wasn't honoured even though the incoming request had d2k set for non cisgress txn", + "PublicDescription": "Counts the number of times D2K wasn't honoured even though the incoming request had d2k set for non cisgress txn", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "B2CMI", + "EventCode": "0x16", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_B2CMI_DIRECT2CORE_TAKEN", + "BriefDescription": "Counts the number of times B2CMI egress did D2C (direct to core)", + "PublicDescription": "Counts the number of times B2CMI egress did D2C (direct to core)", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x02", + "FCMask": "0x07", + "UMaskExt": "0x00070020", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x04", + "FCMask": "0x07", + "UMaskExt": "0x00070040", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x08", + "FCMask": "0x07", + "UMaskExt": "0x00070080", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x10", + "FCMask": "0x07", + "UMaskExt": "0x00070100", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x20", + "FCMask": "0x07", + "UMaskExt": "0x00070200", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x40", + "FCMask": "0x07", + "UMaskExt": "0x00070400", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x01", + "PortMask": "0x80", + "FCMask": "0x07", + "UMaskExt": "0x00070800", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "PublicDescription": "Four byte data request of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x02", + "FCMask": "0x07", + "UMaskExt": "0x00070020", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x04", + "FCMask": "0x07", + "UMaskExt": "0x00070040", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x08", + "FCMask": "0x07", + "UMaskExt": "0x00070080", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x10", + "FCMask": "0x07", + "UMaskExt": "0x00070100", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x20", + "FCMask": "0x07", + "UMaskExt": "0x00070200", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x40", + "FCMask": "0x07", + "UMaskExt": "0x00070400", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x83", + "UMask": "0x04", + "PortMask": "0x80", + "FCMask": "0x07", + "UMaskExt": "0x00070800", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "PublicDescription": "Four byte data request of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x59", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_IRQ", + "BriefDescription": "Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in IRQ (immediate cause for triggering).", + "PublicDescription": "Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in IRQ (immediate cause for triggering).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x59", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_TOR", + "BriefDescription": "Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in TOR (immediate cause for triggering).", + "PublicDescription": "Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in TOR (immediate cause for triggering).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x59", + "UMask": "0x03", + "PortMask": "0x000", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_ANY", + "BriefDescription": "Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in TOR or IRQ (immediate cause for triggering).", + "PublicDescription": "Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in TOR or IRQ (immediate cause for triggering).", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHACMS", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x000", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHACMS_CLOCKTICKS", + "BriefDescription": "Clockticks for CMS units attached to CHA", + "PublicDescription": "UNC_CHACMS_CLOCKTICKS", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x002", + "FCMask": "0x07", + "UMaskExt": "0x00070020", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x002", + "FCMask": "0x07", + "UMaskExt": "0x00070020", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x004", + "FCMask": "0x07", + "UMaskExt": "0x00070040", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x004", + "FCMask": "0x07", + "UMaskExt": "0x00070040", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x008", + "FCMask": "0x07", + "UMaskExt": "0x00070080", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x008", + "FCMask": "0x07", + "UMaskExt": "0x00070080", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x010", + "FCMask": "0x07", + "UMaskExt": "0x00070100", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x010", + "FCMask": "0x07", + "UMaskExt": "0x00070100", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x020", + "FCMask": "0x07", + "UMaskExt": "0x00070200", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x020", + "FCMask": "0x07", + "UMaskExt": "0x00070200", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x040", + "FCMask": "0x07", + "UMaskExt": "0x00070400", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x040", + "FCMask": "0x07", + "UMaskExt": "0x00070400", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x01", + "PortMask": "0x080", + "FCMask": "0x07", + "UMaskExt": "0x00070800", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7", + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x84", + "UMask": "0x04", + "PortMask": "0x080", + "FCMask": "0x07", + "UMaskExt": "0x00070800", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7", + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x01", + "PortMask": "0x002", + "FCMask": "0x07", + "UMaskExt": "0x00070020", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x01", + "PortMask": "0x004", + "FCMask": "0x07", + "UMaskExt": "0x00070040", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x01", + "PortMask": "0x008", + "FCMask": "0x07", + "UMaskExt": "0x00070080", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x01", + "PortMask": "0x010", + "FCMask": "0x07", + "UMaskExt": "0x00070100", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4", + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x01", + "PortMask": "0x020", + "FCMask": "0x07", + "UMaskExt": "0x00070200", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5", + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x01", + "PortMask": "0x040", + "FCMask": "0x07", + "UMaskExt": "0x00070400", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6", + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x01", + "PortMask": "0x080", + "FCMask": "0x07", + "UMaskExt": "0x00070800", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7", + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x02", + "PortMask": "0x0FF", + "FCMask": "0x07", + "UMaskExt": "0x00070FF0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.ALL_PARTS", + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC0", + "UMask": "0x08", + "PortMask": "0x0FF", + "FCMask": "0x07", + "UMaskExt": "0x00070FF0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.ALL_PARTS", + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x01", + "PortMask": "0x002", + "FCMask": "0x07", + "UMaskExt": "0x00070020", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x04", + "PortMask": "0x002", + "FCMask": "0x07", + "UMaskExt": "0x00070020", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x01", + "PortMask": "0x004", + "FCMask": "0x07", + "UMaskExt": "0x00070040", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x04", + "PortMask": "0x004", + "FCMask": "0x07", + "UMaskExt": "0x00070040", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x01", + "PortMask": "0x008", + "FCMask": "0x07", + "UMaskExt": "0x00070080", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x04", + "PortMask": "0x008", + "FCMask": "0x07", + "UMaskExt": "0x00070080", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x01", + "PortMask": "0x010", + "FCMask": "0x07", + "UMaskExt": "0x00070100", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x04", + "PortMask": "0x010", + "FCMask": "0x07", + "UMaskExt": "0x00070100", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x01", + "PortMask": "0x020", + "FCMask": "0x07", + "UMaskExt": "0x00070200", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x04", + "PortMask": "0x020", + "FCMask": "0x07", + "UMaskExt": "0x00070200", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x01", + "PortMask": "0x040", + "FCMask": "0x07", + "UMaskExt": "0x00070400", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x04", + "PortMask": "0x040", + "FCMask": "0x07", + "UMaskExt": "0x00070400", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x01", + "PortMask": "0x080", + "FCMask": "0x07", + "UMaskExt": "0x00070800", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x04", + "PortMask": "0x080", + "FCMask": "0x07", + "UMaskExt": "0x00070800", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x01", + "PortMask": "0x0FF", + "FCMask": "0x07", + "UMaskExt": "0x00070FF0", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.ALL_PARTS", + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x02", + "PortMask": "0x0FF", + "FCMask": "0x07", + "UMaskExt": "0x00070FF0", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.ALL_PARTS", + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x04", + "PortMask": "0x0FF", + "FCMask": "0x07", + "UMaskExt": "0x00070FF0", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.ALL_PARTS", + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0xC1", + "UMask": "0x08", + "PortMask": "0x0FF", + "FCMask": "0x07", + "UMaskExt": "0x00070FF0", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.ALL_PARTS", + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", + "Counter": "2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x10", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_INSERTS.SCH0_PCH0", + "BriefDescription": "Read Pending Queue inserts for subchannel 0, pseudochannel 0", + "PublicDescription": "Read Pending Queue inserts for subchannel 0, pseudochannel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x10", + "UMask": "0x20", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_INSERTS.SCH0_PCH1", + "BriefDescription": "Read Pending Queue inserts for subchannel 0, pseudochannel 1", + "PublicDescription": "Read Pending Queue inserts for subchannel 0, pseudochannel 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x10", + "UMask": "0x40", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_INSERTS.SCH1_PCH0", + "BriefDescription": "Read Pending Queue inserts for subchannel 1, pseudochannel 0", + "PublicDescription": "Read Pending Queue inserts for subchannel 1, pseudochannel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x10", + "UMask": "0x80", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_RPQ_INSERTS.SCH1_PCH1", + "BriefDescription": "Read Pending Queue inserts for subchannel 1, pseudochannel 1", + "PublicDescription": "Read Pending Queue inserts for subchannel 1, pseudochannel 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x22", + "UMask": "0x10", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_INSERTS.SCH0_PCH0", + "BriefDescription": "Write Pending Queue inserts for subchannel 0, pseudochannel 0", + "PublicDescription": "Write Pending Queue inserts for subchannel 0, pseudochannel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x22", + "UMask": "0x20", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_INSERTS.SCH0_PCH1", + "BriefDescription": "Write Pending Queue inserts for subchannel 0, pseudochannel 1", + "PublicDescription": "Write Pending Queue inserts for subchannel 0, pseudochannel 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x22", + "UMask": "0x40", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_INSERTS.SCH1_PCH0", + "BriefDescription": "Write Pending Queue inserts for subchannel 1, pseudochannel 0", + "PublicDescription": "Write Pending Queue inserts for subchannel 1, pseudochannel 0", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IMC", + "EventCode": "0x22", + "UMask": "0x80", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_M_WPQ_INSERTS.SCH1_PCH1", + "BriefDescription": "Write Pending Queue inserts for subchannel 1, pseudochannel 1", + "PublicDescription": "Write Pending Queue inserts for subchannel 1, pseudochannel 1", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x02", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C001FF", + "EventName": "UNC_CHA_TOR_INSERTS.LLC_OR_SF_EVICTIONS", + "BriefDescription": "TOR Inserts for SF or LLC Evictions", + "PublicDescription": "TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x69", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_CHA_REMOTE_SF.MISS", + "BriefDescription": "UNC_CHA_REMOTE_SF.MISS", + "PublicDescription": "UNC_CHA_REMOTE_SF.MISS", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "MDF", + "EventCode": "0x01", + "UMask": "0x00", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00000000", + "EventName": "UNC_MDF_CLOCKTICKS", + "BriefDescription": "MDF Clockticks", + "PublicDescription": "MDF Clockticks", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C826FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_LOCAL", + "BriefDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd_Opt, and which target local memory", + "PublicDescription": "TOR Inserts : DRd_Opt issued by iA Cores that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8A6FE", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_LOCAL", + "BriefDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF_OPT, and target local memory", + "PublicDescription": "TOR Inserts : Data read opt prefetch from local iA that missed the LLC targeting local memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8277E", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_REMOTE", + "BriefDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd_Opt, and target remote memory", + "PublicDescription": "TOR Inserts : Data read opt from local iA that missed the LLC targeting remote memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x01", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8A77E", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_REMOTE", + "BriefDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF_OPT, and target remote memory", + "PublicDescription": "TOR Inserts : Data read opt prefetch from local iA that missed the LLC targeting remote memory", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD42FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL", + "BriefDescription": "ItoMCacheNear (partial write) transactions from an IO device that addresses memory on the local socket", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that address memory on the local socket", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CD437F", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE", + "BriefDescription": "ItoMCacheNear (partial write) transactions from an IO device that addresses memory on a remote socket", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that address memory on a remote socket", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC42FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL", + "BriefDescription": "ItoM (write) transactions from an IO device that addresses memory on the local socket", + "PublicDescription": "TOR Inserts : ItoM, indicating a write request, from IO Devices that address memory on the local socket", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00CC437F", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE", + "BriefDescription": "ItoM (write) transactions from an IO device that addresses memory on a remote socket", + "PublicDescription": "TOR Inserts : ItoM, indicating a write request, from IO Devices that address memory on a remote socket", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8F2FF", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL", + "BriefDescription": "PCIRDCUR (read) transactions from an IO device that addresses memory on the local socket", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that addresses memory on the local socket", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "CHA", + "EventCode": "0x35", + "UMask": "0x04", + "PortMask": "0x00", + "FCMask": "0x00", + "UMaskExt": "0x00C8F37F", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE", + "BriefDescription": "PCIRDCUR (read) transactions from an IO device that addresses memory on a remote socket", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that addresses memory on a remote socket", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + }, + { + "Unit": "IIO", + "EventCode": "0x8e", + "UMask": "0x04", + "PortMask": "0x0FF", + "FCMask": "0x01", + "UMaskExt": "0x00010FF0", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX_POSTED", + "BriefDescription": "Posted requests sent by the integrated IO (IIO) controller to the Ubox, useful for counting message signaled interrupts (MSI).", + "PublicDescription": "-", + "Counter": "0,1,2,3", + "ELLC": "0", + "Filter": "na", + "ExtSel": "0", + "Deprecated": "0", + "FILTER_VALUE": "0", + "CounterType": "PGMABLE" + } + ] +} \ No newline at end of file diff --git a/cmd/metrics/resources/perfmon/srf/srf.json b/cmd/metrics/resources/perfmon/srf/srf.json new file mode 100644 index 00000000..d04f5450 --- /dev/null +++ b/cmd/metrics/resources/perfmon/srf/srf.json @@ -0,0 +1,828 @@ +{ + "Header": { + "Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.", + "Info": "PerfSpect Performance Monitoring Metrics for Intel(R) Xeon(R) 6 Processor with E-cores (Sierra Forest)" + }, + "PerfmonMetricsFile": "sierraforest_metrics.json", + "PerfmonCoreEventsFile": "sierraforest_core.json", + "PerfmonUncoreEventsFile": "sierraforest_uncore.json", + "PerfmonRetireLatencyFile": "", + "ReportMetrics": [ + { + "MetricName": "cpu_operating_frequency", + "LegacyName": "metric_CPU operating frequency (in GHz)", + "Origin": "perfmon" + }, + { + "MetricName": "cpu_utilization", + "LegacyName": "metric_CPU utilization %", + "Origin": "perfmon" + }, + { + "MetricName": "cpu_util_kernel", + "LegacyName": "metric_CPU utilization % in kernel mode", + "Origin": "perfspect" + }, + { + "MetricName": "cpi", + "LegacyName": "metric_CPI", + "Origin": "perfmon" + }, + { + "MetricName": "cycles_per_txn", + "LegacyName": "metric_cycles per txn", + "Origin": "perfspect" + }, + { + "MetricName": "kernel_cpi", + "LegacyName": "metric_kernel_CPI", + "Origin": "perfspect" + }, + { + "MetricName": "kernel_cycles_per_txn", + "LegacyName": "metric_kernel_cycles per txn", + "Origin": "perfspect" + }, + { + "MetricName": "ipc", + "LegacyName": "metric_IPC", + "Origin": "perfspect" + }, + { + "MetricName": "giga_instructions_per_sec", + "LegacyName": "metric_giga_instructions_per_sec", + "Origin": "perfspect" + }, + { + "MetricName": "branch_misprediction_ratio", + "LegacyName": "metric_branch misprediction ratio", + "Origin": "perfspect" + }, + { + "MetricName": "locks_retired_per_instr", + "LegacyName": "metric_locks retired per instr", + "Origin": "perfspect" + }, + { + "MetricName": "locks_retired_per_txn", + "LegacyName": "metric_locks retired per txn", + "Origin": "perfspect" + }, + { + "MetricName": "l1d_misses_per_txn", + "LegacyName": "metric_L1D misses per txn (includes data+rfo w/ prefetches)", + "Origin": "perfspect" + }, + { + "MetricName": "l1d_demand_data_read_hits_per_instr", + "LegacyName": "metric_L1D demand data read hits per instr", + "Origin": "perfmon" + }, + { + "MetricName": "l1d_demand_data_read_hits_per_txn", + "LegacyName": "metric_L1D demand data read hits per txn", + "Origin": "perfspect" + }, + { + "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", + "LegacyName": "metric_L1-I code read misses (w/ prefetches) per instr", + "Origin": "perfmon" + }, + { + "MetricName": "l1i_code_read_misses_per_txn", + "LegacyName": "metric_L1I code read misses (includes prefetches) per txn", + "Origin": "perfspect" + }, + { + "MetricName": "l2_demand_data_read_hits_per_instr", + "LegacyName": "metric_L2 demand data read hits per instr", + "Origin": "perfmon" + }, + { + "MetricName": "l2_demand_data_read_hits_per_txn", + "LegacyName": "metric_L2 demand data read hits per txn", + "Origin": "perfspect" + }, + { + "MetricName": "l2_mpi", + "LegacyName": "metric_L2 MPI (includes code+data+rfo w/ prefetches)", + "Origin": "perfmon" + }, + { + "MetricName": "l2_misses_per_txn", + "LegacyName": "metric_L2 misses per txn (includes code+data+rfo w/ prefetches)", + "Origin": "perfspect" + }, + { + "MetricName": "l2_demand_data_read_mpi", + "LegacyName": "metric_L2 demand data read MPI", + "Origin": "perfmon" + }, + { + "MetricName": "l2_demand_data_read_misses_per_txn", + "LegacyName": "metric_L2 demand data read misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "llc_code_read_mpi_demand_plus_prefetch", + "LegacyName": "metric_LLC code read MPI (demand+prefetch)", + "Origin": "perfmon" + }, + { + "MetricName": "llc_code_read_misses_per_txn", + "LegacyName": "metric_LLC code read (demand+prefetch) misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "llc_data_read_mpi_demand_plus_prefetch", + "LegacyName": "metric_LLC data read MPI (demand+prefetch)", + "Origin": "perfmon" + }, + { + "MetricName": "llc_data_read_misses_per_txn", + "LegacyName": "metric_LLC data read (demand+prefetch) misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "llc_demand_data_read_miss_latency", + "LegacyName": "metric_Average LLC demand data read miss latency (in ns)", + "Origin": "perfmon" + }, + { + "MetricName": "package_power", + "LegacyName": "metric_package power (watts)", + "Origin": "perfspect" + }, + { + "MetricName": "dram_power", + "LegacyName": "metric_DRAM power (watts)", + "Origin": "perfspect" + }, + { + "MetricName": "core_c6_residency", + "LegacyName": "metric_core c6 residency %", + "Origin": "perfspect" + }, + { + "MetricName": "package_c6_residency", + "LegacyName": "metric_package c6 residency %", + "Origin": "perfspect" + }, + { + "MetricName": "memory_bandwidth_read", + "LegacyName": "metric_memory bandwidth read (MB/sec)", + "Origin": "perfmon" + }, + { + "MetricName": "memory_bandwidth_write", + "LegacyName": "metric_memory bandwidth write (MB/sec)", + "Origin": "perfmon" + }, + { + "MetricName": "memory_bandwidth_total", + "LegacyName": "metric_memory bandwidth total (MB/sec)", + "Origin": "perfmon" + }, + { + "MetricName": "itlb_2nd_level_mpi", + "LegacyName": "metric_ITLB (2nd level) MPI", + "Origin": "perfmon" + }, + { + "MetricName": "itlb_misses_per_txn", + "LegacyName": "metric_ITLB (2nd level) misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "dtlb_2nd_level_load_mpi", + "LegacyName": "metric_DTLB (2nd level) load MPI", + "Origin": "perfmon" + }, + { + "MetricName": "dtlb_load_misses_per_txn", + "LegacyName": "metric_DTLB (2nd level) load misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "dtlb_2nd_level_store_mpi", + "LegacyName": "metric_DTLB (2nd level) store MPI", + "Origin": "perfmon" + }, + { + "MetricName": "dtlb_store_misses_per_txn", + "LegacyName": "metric_DTLB (2nd level) store misses per txn", + "Origin": "perfspect" + }, + { + "MetricName": "numa_reads_addressed_to_local_dram", + "LegacyName": "metric_NUMA %_Reads addressed to local DRAM", + "Origin": "perfmon" + }, + { + "MetricName": "numa_reads_addressed_to_remote_dram", + "LegacyName": "metric_NUMA %_Reads addressed to remote DRAM", + "Origin": "perfmon" + }, + { + "MetricName": "uncore_frequency", + "LegacyName": "metric_uncore frequency GHz", + "Origin": "perfmon" + }, + { + "MetricName": "io_bandwidth_write", + "LegacyName": "metric_IO_bandwidth_disk_or_network_writes (MB/sec)", + "Origin": "perfmon" + }, + { + "MetricName": "io_bandwidth_read", + "LegacyName": "metric_IO_bandwidth_disk_or_network_reads (MB/sec)", + "Origin": "perfmon" + }, + { + "MetricName": "Frontend_Bound", + "LegacyName": "metric_TMA_Frontend_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "IFetch_Latency", + "LegacyName": "metric_TMA_..IFetch_Latency(%)", + "Origin": "perfmon" + }, + { + "MetricName": "ICache_Misses", + "LegacyName": "metric_TMA_....ICache_Misses(%)", + "Origin": "perfmon" + }, + { + "MetricName": "ITLB_Misses", + "LegacyName": "metric_TMA_....ITLB_Misses(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Branch_Detect", + "LegacyName": "metric_TMA_....Branch_Detect(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Branch_Resteer", + "LegacyName": "metric_TMA_....Branch_Resteer(%)", + "Origin": "perfmon" + }, + { + "MetricName": "IFetch_Bandwidth", + "LegacyName": "metric_TMA_..IFetch_Bandwidth(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Cisc", + "LegacyName": "metric_TMA_....Cisc(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Decode", + "LegacyName": "metric_TMA_....Decode(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Predecode", + "LegacyName": "metric_TMA_....Predecode(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Other_FB", + "LegacyName": "metric_TMA_....Other_FB(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Bad_Speculation", + "LegacyName": "metric_TMA_Bad_Speculation(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Branch_Mispredicts", + "LegacyName": "metric_TMA_..Branch_Mispredicts(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Machine_Clears", + "LegacyName": "metric_TMA_..Machine_Clears(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Nuke", + "LegacyName": "metric_TMA_....Nuke(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Fast_Nuke", + "LegacyName": "metric_TMA_....Fast_Nuke(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Backend_Bound", + "LegacyName": "metric_TMA_Backend_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Core_Bound", + "LegacyName": "metric_TMA_..Core_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Allocation_Restriction", + "LegacyName": "metric_TMA_....Allocation_Restriction(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Resource_Bound", + "LegacyName": "metric_TMA_..Resource_Bound(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Mem_Scheduler", + "LegacyName": "metric_TMA_....Mem_Scheduler(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Non_Mem_Scheduler", + "LegacyName": "metric_TMA_....Non_Mem_Scheduler(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Register", + "LegacyName": "metric_TMA_....Register(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Reorder_Buffer", + "LegacyName": "metric_TMA_....Reorder_Buffer(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Serialization", + "LegacyName": "metric_TMA_....Serialization(%)", + "Origin": "perfmon" + }, + { + "MetricName": "Retiring", + "LegacyName": "metric_TMA_Retiring(%)", + "Origin": "perfmon" + } + ], + "Metrics": [ + { + "MetricName": "cpu_util_kernel", + "LegacyName": "metric_CPU utilization % in kernel mode", + "BriefDescription": "CPU utilization percentage in kernel mode", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + }, + { + "Name": "TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * (a / b)", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "cycles_per_txn", + "LegacyName": "metric_cycles per txn", + "BriefDescription": "Number of cycles per transaction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "kernel_cpi", + "LegacyName": "metric_kernel_CPI", + "BriefDescription": "Kernel cycles per instruction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "kernel_cycles_per_txn", + "LegacyName": "metric_kernel_cycles per txn", + "BriefDescription": "Number of kernel cycles per transaction", + "Events": [ + { + "Name": "CPU_CLK_UNHALTED.THREAD_P:SUP", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "ipc", + "LegacyName": "metric_IPC", + "BriefDescription": "Instructions per cycle", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + }, + { + "Name": "CPU_CLK_UNHALTED.THREAD", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "giga_instructions_per_sec", + "LegacyName": "metric_giga_instructions_per_sec", + "BriefDescription": "Billions of instructions per second", + "Events": [ + { + "Name": "INST_RETIRED.ANY", + "Alias": "a" + } + ], + "Constants": [ + ], + "Formula": "a / 1000000000", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "branch_misprediction_ratio", + "LegacyName": "metric_branch misprediction ratio", + "BriefDescription": "Ratio of branch mispredictions to the total number of branches retired.", + "Events": [ + { + "Name": "BR_MISP_RETIRED.ALL_BRANCHES", + "Alias": "a" + }, + { + "Name": "BR_INST_RETIRED.ALL_BRANCHES", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "locks_retired_per_instr", + "LegacyName": "metric_locks retired per instr", + "BriefDescription": "Locks retired per instruction", + "Events": [ + { + "Name": "MEM_UOPS_RETIRED.LOCK_LOADS", + "Alias": "a" + }, + { + "Name": "INST_RETIRED.ANY", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "locks_retired_per_txn", + "LegacyName": "metric_locks retired per txn", + "BriefDescription": "Locks retired per transaction", + "Events": [ + { + "Name": "MEM_UOPS_RETIRED.LOCK_LOADS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l1d_misses_per_txn", + "LegacyName": "metric_L1D misses per txn (includes data+rfo w/ prefetches)", + "BriefDescription": "L1D misses per transaction (includes data+rfo with prefetches)", + "Events": [ + { + "Name": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l1d_demand_data_read_hits_per_txn", + "LegacyName": "metric_L1D demand data read hits per txn", + "BriefDescription": "L1D demand data read hits per transaction", + "Events": [ + { + "Name": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l1i_code_read_misses_per_txn", + "LegacyName": "metric_L1I code read misses (includes prefetches) per txn", + "BriefDescription": "L1I code read misses (includes prefetches) per transaction", + "Events": [ + { + "Name": "ICACHE.MISSES", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l2_demand_data_read_hits_per_txn", + "LegacyName": "metric_L2 demand data read hits per txn", + "BriefDescription": "L2 demand data read hits per transaction", + "Events": [ + { + "Name": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l2_misses_per_txn", + "LegacyName": "metric_L2 misses per txn (includes code+data+rfo w/ prefetches)", + "BriefDescription": "L2 misses per transaction (includes code+data+rfo with prefetches)", + "Events": [ + { + "Name": "LONGEST_LAT_CACHE.REFERENCE", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "l2_demand_data_read_misses_per_txn", + "LegacyName": "metric_L2 demand data read misses per txn", + "BriefDescription": "L2 demand data read misses per transaction", + "Events": [ + { + "Name": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "llc_code_read_misses_per_txn", + "LegacyName": "metric_LLC code read (demand+prefetch) misses per txn", + "BriefDescription": "LLC code read (demand+prefetch) misses per transaction", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "c" + } + ], + "Formula": "(a + b) / c", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "llc_data_read_misses_per_txn", + "LegacyName": "metric_LLC data read (demand+prefetch) misses per txn", + "BriefDescription": "LLC data read (demand+prefetch) misses per transaction", + "Events": [ + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", + "Alias": "a" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF", + "Alias": "b" + }, + { + "Name": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", + "Alias": "c" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "d" + } + ], + "Formula": "(a + b + c) / d", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "package_power", + "LegacyName": "metric_package power (watts)", + "BriefDescription": "Package power consumption in watts", + "Events": [ + { + "Name": "power/energy-pkg/", + "Alias": "a" + } + ], + "Constants": [ + ], + "Formula": "a", + "ResolutionLevels": "SOCKET, SYSTEM" + }, + { + "MetricName": "dram_power", + "LegacyName": "metric_DRAM power (watts)", + "BriefDescription": "DRAM power consumption in watts", + "Events": [ + { + "Name": "power/energy-ram/", + "Alias": "a" + } + ], + "Constants": [ + ], + "Formula": "a", + "ResolutionLevels": "SOCKET, SYSTEM" + }, + { + "MetricName": "core_c6_residency", + "LegacyName": "metric_core c6 residency %", + "BriefDescription": "Core C6 state residency percentage", + "Events": [ + { + "Name": "cstate_core/c6-residency/", + "Alias": "a" + }, + { + "Name": "TSC", + "Alias": "b" + } + ], + "Constants": [], + "Formula": "100 * a / b", + "ResolutionLevels": "CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "package_c6_residency", + "LegacyName": "metric_package c6 residency %", + "BriefDescription": "Package C6 state residency percentage", + "Events": [ + { + "Name": "cstate_pkg/c6-residency/", + "Alias": "a" + }, + { + "Name": "TSC", + "Alias": "b" + } + ], + "Constants": [ + { + "Name": "CORES_PER_SOCKET", + "Alias": "c" + } + ], + "Formula": "100 * a * c / b", + "ResolutionLevels": "SOCKET, SYSTEM" + }, + { + "MetricName": "itlb_misses_per_txn", + "LegacyName": "metric_ITLB (2nd level) misses per txn", + "BriefDescription": "ITLB (2nd level) misses per transaction", + "Events": [ + { + "Name": "ITLB_MISSES.WALK_COMPLETED", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "dtlb_load_misses_per_txn", + "LegacyName": "metric_DTLB (2nd level) load misses per txn", + "BriefDescription": "DTLB (2nd level) load misses per transaction", + "Events": [ + { + "Name": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + }, + { + "MetricName": "dtlb_store_misses_per_txn", + "LegacyName": "metric_DTLB (2nd level) store misses per txn", + "BriefDescription": "DTLB (2nd level) store misses per transaction", + "Events": [ + { + "Name": "DTLB_STORE_MISSES.WALK_COMPLETED", + "Alias": "a" + } + ], + "Constants": [ + { + "Name": "TXN", + "Alias": "b" + } + ], + "Formula": "a / b", + "ResolutionLevels": "THREAD, CORE, SOCKET, SYSTEM" + } + ] +}