raid: about the input parameter restriction conditions in the headfile raid.h

[liuqinfei]

1. why should be aligned to 32B for xor_gen/pq_gen, however be aligned to 16B for xor_check/pq_check

2. if "Src and dest pointers must be aligned to 32B." means that the length input of xor_gen should be 32XB? or other? I saw requirement
   directly for input len of pq_gen/pq_check, but not for xor_gen/xor_check.

[pablodelara]

Hi,

1. xor_check/pq_check use aligned loads for 128-bit xmm registers, which requires 16B alignment, whereas xor_gen/pq_gen use aligned stores for 256-bit ymm registers, which requires 32B alignment.
2. Xor_gen/xor_check does not have any length requirement

[liuqinfei]

2. Xor_gen/xor_check does not have any length requirement

Thanks for reply.
It seems that there is two aligned issue here.
One is about the pointer aligned. This is for all the four API. As understand, the requirement for 32-byte or 16-byte alignment of addresses in the x86 architecture is to improve memory access efficiency. And i see xmm registors are used in xor_gen_sse.asm, ymm registors are used in xor_gen_avx.asm, zmm registors are used in xor_gen_avx512.asm. However, "Vectors must be aligned to 16 bytes." are set in all of them. So, the requirements of 32B/16B alignment seems not to be just releated to the registers type.

The other issue is about the len aligned. Yes, i saw tail resolvement for xor_gen/xor_check, so the len can be any value. There is no tail resolvement for pq_gen/pq_check, so the len should be aligned. However, i think for pq_gen/pq_check, the tail resolvement part can also exist if we want. From my point of view, Regardless of their registor type, the header file stipulation should be consistent for all the APIs. And as usual, the len may be multiple of 512B which is the size of a sector . So 512B should be the aligned requirement.

[pablodelara]

2. Xor_gen/xor_check does not have any length requirement

Thanks for reply. It seems that there is two aligned issue here. One is about the pointer aligned. This is for all the four API. As understand, the requirement for 32-byte or 16-byte alignment of addresses in the x86 architecture is to improve memory access efficiency. And i see xmm registors are used in xor_gen_sse.asm, ymm registors are used in xor_gen_avx.asm, zmm registors are used in xor_gen_avx512.asm. However, "Vectors must be aligned to 16 bytes." are set in all of them. So, the requirements of 32B/16B alignment seems not to be just releated to the registers type.

The other issue is about the len aligned. Yes, i saw tail resolvement for xor_gen/xor_check, so the len can be any value. There is no tail resolvement for pq_gen/pq_check, so the len should be aligned. However, i think for pq_gen/pq_check, the tail resolvement part can also exist if we want. From my point of view, Regardless of their registor type, the header file stipulation should be consistent for all the APIs. And as usual, the len may be multiple of 512B which is the size of a sector . So 512B should be the aligned requirement.

1 - Correct, but avx512 uses non-aligned move (vmovdqu) instructions.
2 - Your reasoning sounds good. Will keep in mind. However, as you said, this shouldn't be a major issue, as usually the sizes passed are aligned to bigger sizes.

Thanks!