diff --git a/tdx-compliance/tdx-compliance-msr.h b/tdx-compliance/tdx-compliance-msr.h
index 61f9988..2594925 100644
--- a/tdx-compliance/tdx-compliance-msr.h
+++ b/tdx-compliance/tdx-compliance-msr.h
@@ -228,7 +228,7 @@ struct test_msr msr_cases[] = {
 	DEF_WRITE_MSR(MSR_IA32_TSC, X86_TRAP_VE, NO_PRE_COND),
 	DEF_READ_MSR(MSR_IA32_SPEC_CTRL, NO_EXCP, NO_PRE_COND),
 	DEF_WRITE_MSR(MSR_IA32_SPEC_CTRL, NO_EXCP, NO_PRE_COND),
-	DEF_READ_MSR(MSR_IA32_PRED_CMD, NO_EXCP, NO_PRE_COND),
+	DEF_READ_MSR(MSR_IA32_PRED_CMD, X86_TRAP_GP, NO_PRE_COND),
 	DEF_WRITE_MSR(MSR_IA32_PRED_CMD, NO_EXCP, NO_PRE_COND),
 	DEF_READ_MSR(MSR_IA32_MKTME_PARTITIONING, X86_TRAP_VE, pre_0x7_edx18),
 	DEF_WRITE_MSR(MSR_IA32_MKTME_PARTITIONING, X86_TRAP_VE, pre_0x7_edx18),
@@ -251,8 +251,8 @@ struct test_msr msr_cases[] = {
 	DEF_READ_MSR(MSR_IA32_UMWAIT_CONTROL, NO_EXCP, pre_0x7_ecx5),
 	DEF_WRITE_MSR(MSR_IA32_UMWAIT_CONTROL, NO_EXCP, pre_0x7_ecx5),
 
-	DEF_WRITE_MSR(MSR_IA32_ARCH_CAPABILITIES, NO_EXCP, NO_PRE_COND),
-	DEF_READ_MSR(MSR_IA32_FLUSH_CMD, NO_EXCP, NO_PRE_COND),
+	DEF_WRITE_MSR(MSR_IA32_ARCH_CAPABILITIES, X86_TRAP_GP, NO_PRE_COND),
+	DEF_READ_MSR(MSR_IA32_FLUSH_CMD, X86_TRAP_GP, NO_PRE_COND),
 	DEF_WRITE_MSR(MSR_IA32_FLUSH_CMD, NO_EXCP, NO_PRE_COND),
 	DEF_READ_MSR(MSR_IA32_TSX_CTRL, NO_EXCP, pre_tsx),
 	DEF_WRITE_MSR(MSR_IA32_TSX_CTRL, NO_EXCP, pre_tsx),
@@ -288,11 +288,11 @@ struct test_msr msr_cases[] = {
 	DEF_READ_MSR(MSR_PERF_METRICS, NO_EXCP, pre_perfmon),
 	DEF_WRITE_MSR(MSR_PERF_METRICS, NO_EXCP, pre_perfmon),
 
-	DEF_WRITE_MSR(MSR_IA32_PERF_CAPABILITIES, NO_EXCP, pre_perfmon),
+	DEF_WRITE_MSR(MSR_IA32_PERF_CAPABILITIES, X86_TRAP_GP, pre_perfmon),
 	DEF_READ_MSR(MSR_CORE_PERF_FIXED_CTR_CTRL, NO_EXCP, pre_perfmon),
 	DEF_WRITE_MSR(MSR_CORE_PERF_FIXED_CTR_CTRL, NO_EXCP, pre_perfmon),
 	DEF_READ_MSR(MSR_CORE_PERF_GLOBAL_STATUS, NO_EXCP, pre_perfmon),
-	DEF_WRITE_MSR(MSR_CORE_PERF_GLOBAL_STATUS, NO_EXCP, pre_perfmon),
+	DEF_WRITE_MSR(MSR_CORE_PERF_GLOBAL_STATUS, X86_TRAP_GP, pre_perfmon),
 	DEF_READ_MSR(MSR_CORE_PERF_GLOBAL_CTRL, NO_EXCP, pre_perfmon),
 	DEF_WRITE_MSR(MSR_CORE_PERF_GLOBAL_CTRL, NO_EXCP, pre_perfmon),
 	DEF_READ_MSR(MSR_CORE_PERF_GLOBAL_OVF_CTRL, NO_EXCP, pre_perfmon),
@@ -300,7 +300,7 @@ struct test_msr msr_cases[] = {
 	DEF_READ_MSR(IA32_PERF_GLOBAL_STATUS_SET, NO_EXCP, pre_perfmon),
 	DEF_WRITE_MSR(IA32_PERF_GLOBAL_STATUS_SET, NO_EXCP, pre_perfmon),
 	DEF_READ_MSR(IA32_PERF_GLOBAL_INUSE, NO_EXCP, pre_perfmon),
-	DEF_WRITE_MSR(IA32_PERF_GLOBAL_INUSE, NO_EXCP, pre_perfmon),
+	DEF_WRITE_MSR(IA32_PERF_GLOBAL_INUSE, X86_TRAP_GP, pre_perfmon),
 	DEF_READ_MSR(MSR_IA32_PEBS_ENABLE, NO_EXCP, pre_perfmon),
 	DEF_WRITE_MSR(MSR_IA32_PEBS_ENABLE, NO_EXCP, pre_perfmon),
 	DEF_READ_MSR(MSR_PEBS_DATA_CFG, NO_EXCP, pre_perfmon),
@@ -403,22 +403,22 @@ struct test_msr msr_cases[] = {
 	DEF_WRITE_MSR_SIZE(RESERVED_XAPIC_0X0804, X86_TRAP_GP, NO_PRE_COND, 0x4),
 	DEF_READ_MSR(IA32_X2APIC_TPR, NO_EXCP, NO_PRE_COND),
 	DEF_WRITE_MSR(IA32_X2APIC_TPR, NO_EXCP, NO_PRE_COND),
-	DEF_READ_MSR(RESERVED_XAPIC_0X0809, NO_EXCP, NO_PRE_COND),
-	DEF_WRITE_MSR(RESERVED_XAPIC_0X0809, NO_EXCP, NO_PRE_COND),
+//	DEF_READ_MSR(RESERVED_XAPIC_0X0809, NO_EXCP, NO_PRE_COND),
+//	DEF_WRITE_MSR(RESERVED_XAPIC_0X0809, NO_EXCP, NO_PRE_COND),
 	DEF_READ_MSR(IA32_X2APIC_PPR, NO_EXCP, NO_PRE_COND),
-	DEF_WRITE_MSR(IA32_X2APIC_PPR, NO_EXCP, NO_PRE_COND),
+	DEF_WRITE_MSR(IA32_X2APIC_PPR, X86_TRAP_GP, NO_PRE_COND),
 	DEF_READ_MSR(IA32_X2APIC_EOI, NO_EXCP, NO_PRE_COND),
 	DEF_WRITE_MSR(IA32_X2APIC_EOI, NO_EXCP, NO_PRE_COND),
-	DEF_READ_MSR(RESERVED_XAPIC_0X080C, NO_EXCP, NO_PRE_COND),
-	DEF_WRITE_MSR(RESERVED_XAPIC_0X080C, NO_EXCP, NO_PRE_COND),
-	DEF_READ_MSR(RESERVED_XAPIC_0X080E, NO_EXCP, NO_PRE_COND),
-	DEF_WRITE_MSR(RESERVED_XAPIC_0X080E, NO_EXCP, NO_PRE_COND),
+//	DEF_READ_MSR(RESERVED_XAPIC_0X080C, NO_EXCP, NO_PRE_COND),
+//	DEF_WRITE_MSR(RESERVED_XAPIC_0X080C, NO_EXCP, NO_PRE_COND),
+//	DEF_READ_MSR(RESERVED_XAPIC_0X080E, NO_EXCP, NO_PRE_COND),
+//	DEF_WRITE_MSR(RESERVED_XAPIC_0X080E, NO_EXCP, NO_PRE_COND),
 	DEF_READ_MSR_SIZE(IA32_X2APIC_ISRX, NO_EXCP, NO_PRE_COND, 0x8),
-	DEF_WRITE_MSR_SIZE(IA32_X2APIC_ISRX, NO_EXCP, NO_PRE_COND, 0x8),
+	DEF_WRITE_MSR_SIZE(IA32_X2APIC_ISRX, X86_TRAP_GP, NO_PRE_COND, 0x8),
 	DEF_READ_MSR_SIZE(IA32_X2APIC_TMRX, NO_EXCP, NO_PRE_COND, 0x8),
-	DEF_WRITE_MSR_SIZE(IA32_X2APIC_TMRX, NO_EXCP, NO_PRE_COND, 0x8),
+	DEF_WRITE_MSR_SIZE(IA32_X2APIC_TMRX, X86_TRAP_GP, NO_PRE_COND, 0x8),
 	DEF_READ_MSR_SIZE(IA32_X2APIC_IRRX, NO_EXCP, NO_PRE_COND, 0x8),
-	DEF_WRITE_MSR_SIZE(IA32_X2APIC_IRRX, NO_EXCP, NO_PRE_COND, 0x8),
+	DEF_WRITE_MSR_SIZE(IA32_X2APIC_IRRX, X86_TRAP_GP, NO_PRE_COND, 0x8),
 	DEF_READ_MSR_SIZE(RESERVED_XAPIC_0X0829, X86_TRAP_GP, NO_PRE_COND, 0x6),
 	DEF_WRITE_MSR_SIZE(RESERVED_XAPIC_0X0829, X86_TRAP_GP, NO_PRE_COND, 0x6),
 	DEF_READ_MSR(RESERVED_XAPIC_0X0831, X86_TRAP_GP, NO_PRE_COND),