From 772b165024afa6c059c7ce2ab2d87be748ea0fd7 Mon Sep 17 00:00:00 2001 From: DCyan_Elite Date: Mon, 20 Nov 2023 11:01:10 +0800 Subject: [PATCH] Add spec2.0 cases Signed-off-by: DCyan_Elite --- tdx-compliance/tdx-compliance-cpuid.h | 405 +++++++++---------- tdx-compliance/tdx-compliance-cr.h | 40 +- tdx-compliance/tdx-compliance-msr.h | 540 +++++++++++++------------- tdx-compliance/tdx-compliance.c | 6 +- tdx-compliance/tdx-compliance.h | 1 + tdx-compliance/testallcase.sh | 2 +- 6 files changed, 507 insertions(+), 487 deletions(-) diff --git a/tdx-compliance/tdx-compliance-cpuid.h b/tdx-compliance/tdx-compliance-cpuid.h index 161378c..c996426 100644 --- a/tdx-compliance/tdx-compliance-cpuid.h +++ b/tdx-compliance/tdx-compliance-cpuid.h @@ -53,50 +53,50 @@ extern void initial_cpuid(void); void initial_cpuid(void) { /* CPUID(0x0) */ - EXP_CPUID_BYTE(0x0, 0, eax, 0x00000021, VER1_0); //"MaxIndex" + EXP_CPUID_BYTE(0x0, 0, eax, 0x00000021, VER1_0 | VER2_0); //"MaxIndex" EXP_CPUID_BYTE(0x0, 0, eax, 0x00000023, VER1_5); //"MaxIndex" EXP_CPUID_BYTE(0x0, 0, ebx, 0x756e6547, VER1_5); //"Genu" EXP_CPUID_BYTE(0x0, 0, ecx, 0x6c65746e, VER1_5); //"ntel" EXP_CPUID_BYTE(0x0, 0, edx, 0x49656e69, VER1_5); //"ineI" /* CPUID(0x1).EAX */ - EXP_CPUID_RES_BITS(0x1, 0, eax, 14, 15, VER1_0 | VER1_5); //Reserved_15_14 - EXP_CPUID_RES_BITS(0x1, 0, eax, 28, 31, VER1_0 | VER1_5); //Reserved_31_28 + EXP_CPUID_RES_BITS(0x1, 0, eax, 14, 15, VER1_0 | VER1_5 | VER2_0); //Reserved_15_14 + EXP_CPUID_RES_BITS(0x1, 0, eax, 28, 31, VER1_0 | VER1_5 | VER2_0); //Reserved_31_28 /* CPUID(0x1).EBX */ EXP_CPUID_RES_BITS(0x1, 0, ebx, 0, 7, VER1_5); //Brand Index /* CLFLUSH Line Size */ - EXP_CPUID_BIT(0x1, 0, ebx, 8, 0, VER1_0 | VER1_5); - EXP_CPUID_BIT(0x1, 0, ebx, 9, 0, VER1_0 | VER1_5); - EXP_CPUID_BIT(0x1, 0, ebx, 10, 0, VER1_0 | VER1_5); - EXP_CPUID_BIT(0x1, 0, ebx, 11, 1, VER1_0 | VER1_5); - EXP_CPUID_BIT(0x1, 0, ebx, 12, 0, VER1_0 | VER1_5); - EXP_CPUID_BIT(0x1, 0, ebx, 13, 0, VER1_0 | VER1_5); - EXP_CPUID_BIT(0x1, 0, ebx, 14, 0, VER1_0 | VER1_5); - EXP_CPUID_BIT(0x1, 0, ebx, 15, 0, VER1_0 | VER1_5); + EXP_CPUID_BIT(0x1, 0, ebx, 8, 0, VER1_0 | VER1_5 | VER2_0); + EXP_CPUID_BIT(0x1, 0, ebx, 9, 0, VER1_0 | VER1_5 | VER2_0); + EXP_CPUID_BIT(0x1, 0, ebx, 10, 0, VER1_0 | VER1_5 | VER2_0); + EXP_CPUID_BIT(0x1, 0, ebx, 11, 1, VER1_0 | VER1_5 | VER2_0); + EXP_CPUID_BIT(0x1, 0, ebx, 12, 0, VER1_0 | VER1_5 | VER2_0); + EXP_CPUID_BIT(0x1, 0, ebx, 13, 0, VER1_0 | VER1_5 | VER2_0); + EXP_CPUID_BIT(0x1, 0, ebx, 14, 0, VER1_0 | VER1_5 | VER2_0); + EXP_CPUID_BIT(0x1, 0, ebx, 15, 0, VER1_0 | VER1_5 | VER2_0); /* CPUID(0x1).ECX */ EXP_CPUID_BIT(0x1, 0, ecx, 0, 1, VER1_5); //SSE3 EXP_CPUID_BIT(0x1, 0, ecx, 1, 1, VER1_5); //PCLMULQDQ EXP_CPUID_BIT(0x1, 0, ecx, 2, 1, VER1_5); //DTES64 - EXP_CPUID_BIT(0x1, 0, ecx, 3, 0, VER1_0); //MONITOR + EXP_CPUID_BIT(0x1, 0, ecx, 3, 0, VER1_0 | VER2_0); //MONITOR EXP_CPUID_BIT(0x1, 0, ecx, 4, 1, VER1_5); //DS-CPL - EXP_CPUID_BIT(0x1, 0, ecx, 5, 0, VER1_0 | VER1_5); //VMX - EXP_CPUID_BIT(0x1, 0, ecx, 6, 0, VER1_0 | VER1_5); //SMX + EXP_CPUID_BIT(0x1, 0, ecx, 5, 0, VER1_0 | VER1_5 | VER2_0); //VMX + EXP_CPUID_BIT(0x1, 0, ecx, 6, 0, VER1_0 | VER1_5 | VER2_0); //SMX EXP_CPUID_BIT(0x1, 0, ecx, 9, 1, VER1_5); //SSSE3 - EXP_CPUID_BIT(0x1, 0, ecx, 13, 1, VER1_0 | VER1_5); //CMPXCHG16B - EXP_CPUID_BIT(0x1, 0, ecx, 15, 1, VER1_0 | VER1_5); //PDCM - EXP_CPUID_BIT(0x1, 0, ecx, 16, 0, VER1_0 | VER1_5); //Reserved_16 + EXP_CPUID_BIT(0x1, 0, ecx, 13, 1, VER1_0 | VER1_5 | VER2_0); //CMPXCHG16B + EXP_CPUID_BIT(0x1, 0, ecx, 15, 1, VER1_0 | VER1_5 | VER2_0); //PDCM + EXP_CPUID_BIT(0x1, 0, ecx, 16, 0, VER1_0 | VER1_5 | VER2_0); //Reserved_16 EXP_CPUID_BIT(0x1, 0, ecx, 17, 1, VER1_5); //PCID EXP_CPUID_BIT(0x1, 0, ecx, 19, 1, VER1_5); //SSE4_1 EXP_CPUID_BIT(0x1, 0, ecx, 20, 1, VER1_5); //SSE4_2 - EXP_CPUID_BIT(0x1, 0, ecx, 21, 1, VER1_0 | VER1_5); //x2APIC + EXP_CPUID_BIT(0x1, 0, ecx, 21, 1, VER1_0 | VER1_5 | VER2_0); //x2APIC EXP_CPUID_BIT(0x1, 0, ecx, 22, 1, VER1_5); //MOVBE EXP_CPUID_BIT(0x1, 0, ecx, 23, 1, VER1_5); //POPCNT - EXP_CPUID_BIT(0x1, 0, ecx, 25, 1, VER1_0 | VER1_5); //AESNI - EXP_CPUID_BIT(0x1, 0, ecx, 26, 1, VER1_0 | VER1_5); //XSAVE - EXP_CPUID_BIT(0x1, 0, ecx, 30, 1, VER1_0 | VER1_5); //RDRAND - EXP_CPUID_BIT(0x1, 0, ecx, 31, 1, VER1_0 | VER1_5); //Reserved_31 + EXP_CPUID_BIT(0x1, 0, ecx, 25, 1, VER1_0 | VER1_5 | VER2_0); //AESNI + EXP_CPUID_BIT(0x1, 0, ecx, 26, 1, VER1_0 | VER1_5 | VER2_0); //XSAVE + EXP_CPUID_BIT(0x1, 0, ecx, 30, 1, VER1_0 | VER1_5 | VER2_0); //RDRAND + EXP_CPUID_BIT(0x1, 0, ecx, 31, 1, VER1_0 | VER1_5 | VER2_0); //Reserved_31 /* CPUID(0x1).EDX */ EXP_CPUID_BIT(0x1, 0, edx, 0, 1, VER1_5); //FPU @@ -104,36 +104,36 @@ void initial_cpuid(void) EXP_CPUID_BIT(0x1, 0, edx, 2, 1, VER1_5); //DE EXP_CPUID_BIT(0x1, 0, edx, 3, 1, VER1_5); //PSE EXP_CPUID_BIT(0x1, 0, edx, 4, 1, VER1_5); //TSC - EXP_CPUID_BIT(0x1, 0, edx, 5, 1, VER1_0 | VER1_5); //MSR - EXP_CPUID_BIT(0x1, 0, edx, 6, 1, VER1_0 | VER1_5); //PAE - EXP_CPUID_BIT(0x1, 0, edx, 7, 1, VER1_0 | VER1_5); //MCE + EXP_CPUID_BIT(0x1, 0, edx, 5, 1, VER1_0 | VER1_5 | VER2_0); //MSR + EXP_CPUID_BIT(0x1, 0, edx, 6, 1, VER1_0 | VER1_5 | VER2_0); //PAE + EXP_CPUID_BIT(0x1, 0, edx, 7, 1, VER1_0 | VER1_5 | VER2_0); //MCE EXP_CPUID_BIT(0x1, 0, edx, 8, 1, VER1_5); //CX8 - EXP_CPUID_BIT(0x1, 0, edx, 9, 1, VER1_0 | VER1_5); //APIC - EXP_CPUID_BIT(0x1, 0, edx, 10, 0, VER1_0 | VER1_5); //Reserved_10 + EXP_CPUID_BIT(0x1, 0, edx, 9, 1, VER1_0 | VER1_5 | VER2_0); //APIC + EXP_CPUID_BIT(0x1, 0, edx, 10, 0, VER1_0 | VER1_5 | VER2_0); //Reserved_10 EXP_CPUID_BIT(0x1, 0, edx, 11, 1, VER1_5); //SEP - EXP_CPUID_BIT(0x1, 0, edx, 12, 1, VER1_0 | VER1_5); //MTRR + EXP_CPUID_BIT(0x1, 0, edx, 12, 1, VER1_0 | VER1_5 | VER2_0); //MTRR EXP_CPUID_BIT(0x1, 0, edx, 13, 1, VER1_5); //PGE - EXP_CPUID_BIT(0x1, 0, edx, 14, 1, VER1_0 | VER1_5); //MCA + EXP_CPUID_BIT(0x1, 0, edx, 14, 1, VER1_0 | VER1_5 | VER2_0); //MCA EXP_CPUID_BIT(0x1, 0, edx, 15, 1, VER1_5); //CMOV EXP_CPUID_BIT(0x1, 0, edx, 16, 1, VER1_5); //PAT EXP_CPUID_BIT(0x1, 0, edx, 17, 0, VER1_5); //PSE-36 - EXP_CPUID_BIT(0x1, 0, edx, 19, 1, VER1_0 | VER1_5); //CLFSH - EXP_CPUID_BIT(0x1, 0, edx, 20, 0, VER1_0 | VER1_5); //Reserved_20 - EXP_CPUID_BIT(0x1, 0, edx, 21, 1, VER1_0 | VER1_5); //DS + EXP_CPUID_BIT(0x1, 0, edx, 19, 1, VER1_0 | VER1_5 | VER2_0); //CLFSH + EXP_CPUID_BIT(0x1, 0, edx, 20, 0, VER1_0 | VER1_5 | VER2_0); //Reserved_20 + EXP_CPUID_BIT(0x1, 0, edx, 21, 1, VER1_0 | VER1_5 | VER2_0); //DS EXP_CPUID_BIT(0x1, 0, edx, 23, 1, VER1_5); //MMX EXP_CPUID_BIT(0x1, 0, edx, 24, 1, VER1_5); //FXSR EXP_CPUID_BIT(0x1, 0, edx, 25, 1, VER1_5); //SSE EXP_CPUID_BIT(0x1, 0, edx, 26, 1, VER1_5); //SSE2 - EXP_CPUID_BIT(0x1, 0, edx, 30, 0, VER1_0 | VER1_5); //Reserved_30 + EXP_CPUID_BIT(0x1, 0, edx, 30, 0, VER1_0 | VER1_5 | VER2_0); //Reserved_30 /* CPUID(0x3) */ - EXP_CPUID_RES_BITS(0x3, 0, eax, 0, 31, VER1_0 | VER1_5); //Reserved_0_31 - EXP_CPUID_RES_BITS(0x3, 0, ebx, 0, 31, VER1_0 | VER1_5); //Reserved_0_31 - EXP_CPUID_RES_BITS(0x3, 0, ecx, 0, 31, VER1_0 | VER1_5); //Reserved_0_31 - EXP_CPUID_RES_BITS(0x3, 0, edx, 0, 31, VER1_0 | VER1_5); //Reserved_0_31 + EXP_CPUID_RES_BITS(0x3, 0, eax, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved_0_31 + EXP_CPUID_RES_BITS(0x3, 0, ebx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved_0_31 + EXP_CPUID_RES_BITS(0x3, 0, ecx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved_0_31 + EXP_CPUID_RES_BITS(0x3, 0, edx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved_0_31 /* CPUID(0x4, 0x0).EAX */ - EXP_CPUID_RES_BITS(0x4, 0, eax, 10, 13, VER1_5); //Reserved_13_10 + EXP_CPUID_RES_BITS(0x4, 0, eax, 10, 13, VER1_5 | VER2_0); //Reserved_13_10 /* CPUID(0x4, 0x0).EBX */ /* L */ @@ -151,10 +151,10 @@ void initial_cpuid(void) EXP_CPUID_BIT(0x4, 0, ebx, 11, 0, VER1_5); /* CPUID(0x4, 0x0).EDX */ - EXP_CPUID_BIT(0x4, 0, edx, 2, 0, VER1_5); //Reserved_2 + EXP_CPUID_BIT(0x4, 0, edx, 2, 0, VER1_5 | VER2_0); //Reserved_2 /* CPUID(0x4, 0x1).EAX */ - EXP_CPUID_RES_BITS(0x4, 1, eax, 10, 13, VER1_5); //Reserved_13_10 + EXP_CPUID_RES_BITS(0x4, 1, eax, 10, 13, VER1_5 | VER2_0); //Reserved_13_10 /* CPUID(0x4, 0x1).EBX */ /* L */ @@ -172,10 +172,10 @@ void initial_cpuid(void) EXP_CPUID_BIT(0x4, 1, ebx, 11, 0, VER1_5); /* CPUID(0x4, 0x1).EDX */ - EXP_CPUID_BIT(0x4, 1, edx, 2, 0, VER1_5); //Reserved_2 + EXP_CPUID_BIT(0x4, 1, edx, 2, 0, VER1_5 | VER2_0); //Reserved_2 /* CPUID(0x4, 0x2).EAX */ - EXP_CPUID_RES_BITS(0x4, 2, eax, 10, 13, VER1_5); //Reserved_13_10 + EXP_CPUID_RES_BITS(0x4, 2, eax, 10, 13, VER1_5 | VER2_0); //Reserved_13_10 /* CPUID(0x4, 0x2).EBX */ /* L */ @@ -193,10 +193,10 @@ void initial_cpuid(void) EXP_CPUID_BIT(0x4, 2, ebx, 11, 0, VER1_5); /* CPUID(0x4, 0x2).EDX */ - EXP_CPUID_BIT(0x4, 2, edx, 2, 0, VER1_5); //Reserved_2 + EXP_CPUID_BIT(0x4, 2, edx, 2, 0, VER1_5 | VER2_0); //Reserved_2 /* CPUID(0x4, 0x3).EAX */ - EXP_CPUID_RES_BITS(0x4, 3, eax, 10, 13, VER1_5); //Reserved_13_10 + EXP_CPUID_RES_BITS(0x4, 3, eax, 10, 13, VER1_5 | VER2_0); //Reserved_13_10 /* CPUID(0x4, 0x3).EBX */ /* L */ @@ -214,95 +214,97 @@ void initial_cpuid(void) EXP_CPUID_BIT(0x4, 3, ebx, 11, 0, VER1_5); /* CPUID(0x4, 0x3).EDX */ - EXP_CPUID_RES_BITS(0x4, 3, edx, 3, 31, VER1_5); //Reserved_31_3 + EXP_CPUID_RES_BITS(0x4, 3, edx, 3, 31, VER1_5 | VER2_0); //Reserved_31_3 /* CPUID(0x4, 0x4).EAX */ - EXP_CPUID_RES_BITS(0x4, 4, eax, 0, 4, VER1_0 | VER1_5); //Type - EXP_CPUID_RES_BITS(0x4, 4, eax, 5, 7, VER1_0 | VER1_5); //Level - EXP_CPUID_BIT(0x4, 4, eax, 8, 0, VER1_0 | VER1_5); //Self Initializing - EXP_CPUID_BIT(0x4, 4, eax, 9, 0, VER1_0 | VER1_5); //Fully Associative - EXP_CPUID_RES_BITS(0x4, 4, eax, 10, 13, VER1_0 | VER1_5); //Reserved - EXP_CPUID_RES_BITS(0x4, 4, eax, 14, 25, VER1_0 | VER1_5); //Addressable IDs Sharing this Cache - EXP_CPUID_RES_BITS(0x4, 4, eax, 26, 31, VER1_0 | VER1_5); //Addressable IDs for Cores in Package + EXP_CPUID_RES_BITS(0x4, 4, eax, 0, 4, VER1_0 | VER1_5 | VER2_0); //Type + EXP_CPUID_RES_BITS(0x4, 4, eax, 5, 7, VER1_0 | VER1_5 | VER2_0); //Level + EXP_CPUID_BIT(0x4, 4, eax, 8, 0, VER1_0 | VER1_5 | VER2_0); //Self Initializing + EXP_CPUID_BIT(0x4, 4, eax, 9, 0, VER1_0 | VER1_5 | VER2_0); //Fully Associative + EXP_CPUID_RES_BITS(0x4, 4, eax, 10, 13, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_RES_BITS(0x4, 4, eax, 14, 25, VER1_0 | VER1_5 | VER2_0); //Addressable IDs Sharing this Cache + EXP_CPUID_RES_BITS(0x4, 4, eax, 26, 31, VER1_0 | VER1_5 | VER2_0); //Addressable IDs for Cores in Package /* CPUID(0x4, 0x4).EBX */ - EXP_CPUID_RES_BITS(0x4, 4, ebx, 0, 11, VER1_0 | VER1_5); //L - EXP_CPUID_RES_BITS(0x4, 4, ebx, 12, 21, VER1_0 | VER1_5); //P - EXP_CPUID_RES_BITS(0x4, 4, ebx, 22, 31, VER1_0 | VER1_5); //W + EXP_CPUID_RES_BITS(0x4, 4, ebx, 0, 11, VER1_0 | VER1_5 | VER2_0); //L + EXP_CPUID_RES_BITS(0x4, 4, ebx, 12, 21, VER1_0 | VER1_5 | VER2_0); //P + EXP_CPUID_RES_BITS(0x4, 4, ebx, 22, 31, VER1_0 | VER1_5 | VER2_0); //W /* CPUID(0x4, 0x4).ECX */ - EXP_CPUID_BYTE(0x4, 4, ecx, 0, VER1_0 | VER1_5); //Number of Sets + EXP_CPUID_BYTE(0x4, 4, ecx, 0, VER1_0 | VER1_5 | VER2_0); //Number of Sets /* CPUID(0x4, 0x4).EDX */ - EXP_CPUID_BIT(0x4, 4, edx, 0, 0, VER1_0 | VER1_5); //WBINVD - EXP_CPUID_BIT(0x4, 4, edx, 1, 0, VER1_0 | VER1_5); //Cache Inclusiveness - EXP_CPUID_BIT(0x4, 4, edx, 2, 0, VER1_0 | VER1_5); //Complex Cache Indexing - EXP_CPUID_RES_BITS(0x4, 4, edx, 3, 31, VER1_0 | VER1_5); //Reserved + EXP_CPUID_BIT(0x4, 4, edx, 0, 0, VER1_0 | VER1_5 | VER2_0); //WBINVD + EXP_CPUID_BIT(0x4, 4, edx, 1, 0, VER1_0 | VER1_5 | VER2_0); //Cache Inclusiveness + EXP_CPUID_BIT(0x4, 4, edx, 2, 0, VER1_0 | VER1_5 | VER2_0); //Complex Cache Indexing + EXP_CPUID_RES_BITS(0x4, 4, edx, 3, 31, VER1_0 | VER1_5 | VER2_0); //Reserved /* CPUID(0x7, 0x0).EAX */ EXP_CPUID_BYTE(0x7, 0, eax, 2, VER1_5); //Max Sub-Leaves - EXP_CPUID_BYTE(0x7, 0, eax, 1, VER1_0); //Max Sub-Leaves + EXP_CPUID_BYTE(0x7, 0, eax, 1, VER1_0 | VER2_0); //Max Sub-Leaves /* CPUID(0x7, 0x0).EBX */ - EXP_CPUID_BIT(0x7, 0x0, ebx, 0, 1, VER1_0 | VER1_5); //FSGSBASE - EXP_CPUID_BIT(0x7, 0x0, ebx, 1, 0, VER1_0 | VER1_5); //IA32_TSC_ADJUST - EXP_CPUID_BIT(0x7, 0x0, ebx, 2, 0, VER1_0 | VER1_5); //SGX + EXP_CPUID_BIT(0x7, 0x0, ebx, 0, 1, VER1_0 | VER1_5 | VER2_0); //FSGSBASE + EXP_CPUID_BIT(0x7, 0x0, ebx, 1, 0, VER1_0 | VER1_5 | VER2_0); //IA32_TSC_ADJUST + EXP_CPUID_BIT(0x7, 0x0, ebx, 2, 0, VER1_0 | VER1_5 | VER2_0); //SGX EXP_CPUID_BIT(0x7, 0x0, ebx, 6, 1, VER1_5); //FDP_EXCPTN_ONLY EXP_CPUID_BIT(0x7, 0x0, ebx, 7, 1, VER1_5); //SMEP EXP_CPUID_BIT(0x7, 0x0, ebx, 10, 1, VER1_5); //INVPCID + EXP_CPUID_BIT(0x7, 0x0, ebx, 11, 1, VER2_0); //RTM EXP_CPUID_BIT(0x7, 0x0, ebx, 13, 1, VER1_5); //FCS/FDS Deprecation - EXP_CPUID_BIT(0x7, 0x0, ebx, 14, 0, VER1_0 | VER1_5); //MPX - EXP_CPUID_BIT(0x7, 0x0, ebx, 18, 1, VER1_0 | VER1_5); //RDSEED - EXP_CPUID_BIT(0x7, 0x0, ebx, 20, 1, VER1_0 | VER1_5); //SMAP/CLAC/STAC + EXP_CPUID_BIT(0x7, 0x0, ebx, 14, 0, VER1_0 | VER1_5 | VER2_0); //MPX + EXP_CPUID_BIT(0x7, 0x0, ebx, 18, 1, VER1_0 | VER1_5 | VER2_0); //RDSEED + EXP_CPUID_BIT(0x7, 0x0, ebx, 20, 1, VER1_0 | VER1_5 | VER2_0); //SMAP/CLAC/STAC EXP_CPUID_BIT(0x7, 0x0, ebx, 22, 0, VER1_0); //PCOMMIT - EXP_CPUID_BIT(0x7, 0x0, ebx, 23, 1, VER1_0 | VER1_5); //CLFLUSHOPT - EXP_CPUID_BIT(0x7, 0x0, ebx, 24, 1, VER1_0 | VER1_5); //CLWB - EXP_CPUID_BIT(0x7, 0x0, ebx, 29, 1, VER1_0 | VER1_5); //SHA + EXP_CPUID_BIT(0x7, 0x0, ebx, 23, 1, VER1_0 | VER1_5 | VER2_0); //CLFLUSHOPT + EXP_CPUID_BIT(0x7, 0x0, ebx, 24, 1, VER1_0 | VER1_5 | VER2_0); //CLWB + EXP_CPUID_BIT(0x7, 0x0, ebx, 29, 1, VER1_0 | VER1_5 | VER2_0); //SHA /* CPUID(0x7, 0x0).ECX */ - EXP_CPUID_BIT(0x7, 0x0, ecx, 15, 0, VER1_0 | VER1_5); //FZM - EXP_CPUID_RES_BITS(0x7, 0x0, ecx, 17, 21, VER1_0 | VER1_5); //MAWAU for MPX - EXP_CPUID_BIT(0x7, 0x0, ecx, 24, 1, VER1_0 | VER1_5); //BUSLOCK - EXP_CPUID_BIT(0x7, 0x0, ecx, 26, 0, VER1_5); //Reserved + EXP_CPUID_BIT(0x7, 0x0, ecx, 15, 0, VER1_0 | VER1_5 | VER2_0); //FZM + EXP_CPUID_RES_BITS(0x7, 0x0, ecx, 17, 21, VER1_0 | VER1_5 | VER2_0); //MAWAU for MPX + EXP_CPUID_BIT(0x7, 0x0, ecx, 24, 1, VER1_0 | VER1_5 | VER2_0); //BUSLOCK + EXP_CPUID_BIT(0x7, 0x0, ecx, 26, 0, VER1_5 | VER2_0); //Reserved EXP_CPUID_BIT(0x7, 0x0, ecx, 27, 1, VER1_5); //MOVDIRI - EXP_CPUID_BIT(0x7, 0x0, ecx, 28, 1, VER1_0 | VER1_5); //MOVDIR64B - EXP_CPUID_BIT(0x7, 0x0, ecx, 29, 0, VER1_0 | VER1_5); //ENQCMD - EXP_CPUID_BIT(0x7, 0x0, ecx, 30, 0, VER1_0 | VER1_5); //SGX_LC + EXP_CPUID_BIT(0x7, 0x0, ecx, 28, 1, VER1_0 | VER1_5 | VER2_0); //MOVDIR64B + EXP_CPUID_BIT(0x7, 0x0, ecx, 29, 0, VER1_0 | VER1_5 | VER2_0); //ENQCMD + EXP_CPUID_BIT(0x7, 0x0, ecx, 30, 0, VER1_0 | VER1_5 | VER2_0); //SGX_LC /* CPUID(0x7, 0x0).EDX */ - EXP_CPUID_RES_BITS(0x7, 0x0, edx, 0, 1, VER1_0 | VER1_5); //Reserved - EXP_CPUID_RES_BITS(0x7, 0x0, edx, 6, 7, VER1_0 | VER1_5); //Reserved - EXP_CPUID_BIT(0x7, 0x0, edx, 9, 0, VER1_0 | VER1_5); //MCU_OPT supported + EXP_CPUID_RES_BITS(0x7, 0x0, edx, 0, 1, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_RES_BITS(0x7, 0x0, edx, 6, 7, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_BIT(0x7, 0x0, edx, 9, 0, VER1_0 | VER1_5 | VER2_0); //MCU_OPT supported EXP_CPUID_BIT(0x7, 0x0, edx, 10, 1, VER1_5); //MD_CLEAR supported - EXP_CPUID_RES_BITS(0x7, 0x0, edx, 11, 12, VER1_0 | VER1_5); //Reserved - EXP_CPUID_BIT(0x7, 0x0, edx, 13, 0, VER1_0 | VER1_5); //RTM_FORCE_ABORT_SUPPORT(Reserved in 1.0) - EXP_CPUID_BIT(0x7, 0x0, edx, 17, 0, VER1_0 | VER1_5); //Reserved - EXP_CPUID_BIT(0x7, 0x0, edx, 21, 0, VER1_0 | VER1_5); //Reserved - EXP_CPUID_BIT(0x7, 0x0, edx, 26, 1, VER1_0 | VER1_5); //IBRS + EXP_CPUID_RES_BITS(0x7, 0x0, edx, 11, 12, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_BIT(0x7, 0x0, edx, 13, 0, VER1_0 | VER1_5 | VER2_0); //RTM_FORCE_ABORT_SUPPORT(Reserved in 1.0) + EXP_CPUID_BIT(0x7, 0x0, edx, 17, 0, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_BIT(0x7, 0x0, edx, 21, 0, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_BIT(0x7, 0x0, edx, 26, 1, VER1_0 | VER1_5 | VER2_0); //IBRS EXP_CPUID_BIT(0x7, 0x0, edx, 27, 1, VER1_5); //STIBP - EXP_CPUID_BIT(0x7, 0x0, edx, 29, 1, VER1_0 | VER1_5); //IA32_ARCH_CAPABILITIES Support - EXP_CPUID_BIT(0x7, 0x0, edx, 30, 1, VER1_0 | VER1_5); //IA32_CORE_CAPABILITIES Present - EXP_CPUID_BIT(0x7, 0x0, edx, 31, 1, VER1_0 | VER1_5); //SSBD(Speculative Store Bypass Disable) + EXP_CPUID_BIT(0x7, 0x0, edx, 29, 1, VER1_0 | VER1_5 | VER2_0); //IA32_ARCH_CAPABILITIES Support + EXP_CPUID_BIT(0x7, 0x0, edx, 30, 1, VER1_0 | VER1_5 | VER2_0); //IA32_CORE_CAPABILITIES Present + EXP_CPUID_BIT(0x7, 0x0, edx, 31, 1, VER1_0 | VER1_5 | VER2_0); //SSBD(Speculative Store Bypass Disable) /* CPUID(0x7, 0x1).EAX */ - EXP_CPUID_RES_BITS(0x7, 0x1, eax, 0, 3, VER1_0 | VER1_5); //Reserved + EXP_CPUID_RES_BITS(0x7, 0x1, eax, 0, 3, VER1_0 | VER1_5 | VER2_0); //Reserved EXP_CPUID_RES_BITS(0x7, 0x1, eax, 6, 9, VER1_0); //Reserved - EXP_CPUID_BIT(0x7, 0x1, eax, 7, 0, VER1_5); //Reserved - EXP_CPUID_BIT(0x7, 0x1, eax, 9, 0, VER1_5); //Reserved - EXP_CPUID_RES_BITS(0x7, 0x1, eax, 13, 21, VER1_0 | VER1_5); //Reserved - EXP_CPUID_BIT(0x7, 0x1, eax, 22, 0, VER1_0 | VER1_5); //HRESET + EXP_CPUID_BIT(0x7, 0x1, eax, 7, 0, VER1_5 | VER2_0); //Reserved + EXP_CPUID_BIT(0x7, 0x1, eax, 8, 0, VER2_0); //Reserved + EXP_CPUID_BIT(0x7, 0x1, eax, 9, 0, VER1_5 | VER2_0); //Reserved + EXP_CPUID_RES_BITS(0x7, 0x1, eax, 13, 21, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_BIT(0x7, 0x1, eax, 22, 0, VER1_0 | VER1_5 | VER2_0); //HRESET EXP_CPUID_RES_BITS(0x7, 0x1, eax, 23, 31, VER1_0); //Reserved - EXP_CPUID_RES_BITS(0x7, 0x1, eax, 23, 25, VER1_5); //Reserved - EXP_CPUID_RES_BITS(0x7, 0x1, eax, 27, 31, VER1_5); //Reserved + EXP_CPUID_RES_BITS(0x7, 0x1, eax, 23, 25, VER1_5 | VER2_0); //Reserved + EXP_CPUID_RES_BITS(0x7, 0x1, eax, 27, 31, VER1_5 | VER2_0); //Reserved /* CPUID(0x7, 0x1).EBX */ - EXP_CPUID_RES_BITS(0x7, 0x1, ebx, 0, 31, VER1_0 | VER1_5); //Reserved + EXP_CPUID_RES_BITS(0x7, 0x1, ebx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved /* CPUID(0x7, 0x1).ECX */ - EXP_CPUID_RES_BITS(0x7, 0x1, ecx, 0, 31, VER1_0 | VER1_5); //Reserved + EXP_CPUID_RES_BITS(0x7, 0x1, ecx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved /* CPUID(0x7, 0x1).EDX */ - EXP_CPUID_RES_BITS(0x7, 0x1, edx, 0, 31, VER1_0 | VER1_5); //Reserved + EXP_CPUID_RES_BITS(0x7, 0x1, edx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved /* CPUID(0x7, 0x2).EAX */ EXP_CPUID_RES_BITS(0x7, 0x2, eax, 0, 31, VER1_5); //Reserved @@ -321,95 +323,95 @@ void initial_cpuid(void) EXP_CPUID_RES_BITS(0x7, 0x2, edx, 6, 31, VER1_5); //Reserved /* CPUID(0x8) */ - EXP_CPUID_RES_BITS(0x8, 0x0, eax, 0, 31, VER1_0 | VER1_5); //Reserved - EXP_CPUID_RES_BITS(0x8, 0x0, ebx, 0, 31, VER1_0 | VER1_5); //Reserved - EXP_CPUID_RES_BITS(0x8, 0x0, ecx, 0, 31, VER1_0 | VER1_5); //Reserved - EXP_CPUID_RES_BITS(0x8, 0x0, edx, 0, 31, VER1_0 | VER1_5); //Reserved + EXP_CPUID_RES_BITS(0x8, 0x0, eax, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_RES_BITS(0x8, 0x0, ebx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_RES_BITS(0x8, 0x0, ecx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_RES_BITS(0x8, 0x0, edx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved /* CPUID(0xa, 0x0).EDX */ - EXP_CPUID_RES_BITS(0xa, 0x0, edx, 13, 14, VER1_5); //Reserved - EXP_CPUID_BIT(0xa, 0x0, edx, 15, 1, VER1_5); //AnyThread Deprecation - EXP_CPUID_RES_BITS(0xa, 0x0, edx, 16, 31, VER1_5); //Reserved + EXP_CPUID_RES_BITS(0xa, 0x0, edx, 13, 14, VER1_5 | VER2_0); //Reserved + EXP_CPUID_BIT(0xa, 0x0, edx, 15, 1, VER1_5 | VER2_0); //AnyThread Deprecation + EXP_CPUID_RES_BITS(0xa, 0x0, edx, 16, 31, VER1_5 | VER2_0); //Reserved /* CPUID(0xd, 0x0).EAX */ - EXP_CPUID_BIT(0xd, 0x0, eax, 0, 1, VER1_0 | VER1_5); //X87 - EXP_CPUID_BIT(0xd, 0x0, eax, 1, 1, VER1_0 | VER1_5); //SSE - EXP_CPUID_BIT(0xd, 0x0, eax, 3, 0, VER1_0 | VER1_5); //PL_BNDREGS - EXP_CPUID_BIT(0xd, 0x0, eax, 4, 0, VER1_0 | VER1_5); //PL_BNDCFS - EXP_CPUID_BIT(0xd, 0x0, eax, 8, 0, VER1_0 | VER1_5); //Reserved - EXP_CPUID_RES_BITS(0xd, 0x0, eax, 10, 16, VER1_0 | VER1_5); //Reserved - EXP_CPUID_RES_BITS(0xd, 0x0, eax, 19, 31, VER1_0 | VER1_5); //Reserved + EXP_CPUID_BIT(0xd, 0x0, eax, 0, 1, VER1_0 | VER1_5 | VER2_0); //X87 + EXP_CPUID_BIT(0xd, 0x0, eax, 1, 1, VER1_0 | VER1_5 | VER2_0); //SSE + EXP_CPUID_BIT(0xd, 0x0, eax, 3, 0, VER1_0 | VER1_5 | VER2_0); //PL_BNDREGS + EXP_CPUID_BIT(0xd, 0x0, eax, 4, 0, VER1_0 | VER1_5 | VER2_0); //PL_BNDCFS + EXP_CPUID_BIT(0xd, 0x0, eax, 8, 0, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_RES_BITS(0xd, 0x0, eax, 10, 16, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_RES_BITS(0xd, 0x0, eax, 19, 31, VER1_0 | VER1_5 | VER2_0); //Reserved /* CPUID(0xd, 0x0).EDX */ - EXP_CPUID_RES_BITS(0xd, 0x0, edx, 0, 31, VER1_0 | VER1_5); //Reserved + EXP_CPUID_RES_BITS(0xd, 0x0, edx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved /* CPUID(0xd, 0x1).EAX */ - EXP_CPUID_BIT(0xd, 0x1, eax, 0, 1, VER1_0 | VER1_5); //Supports XSAVEOPT - EXP_CPUID_BIT(0xd, 0x1, eax, 1, 1, VER1_0 | VER1_5); //Supports XSAVEC and compacted XRSTOR + EXP_CPUID_BIT(0xd, 0x1, eax, 0, 1, VER1_0 | VER1_5 | VER2_0); //Supports XSAVEOPT + EXP_CPUID_BIT(0xd, 0x1, eax, 1, 1, VER1_0 | VER1_5 | VER2_0); //Supports XSAVEC and compacted XRSTOR EXP_CPUID_BIT(0xd, 0x1, eax, 2, 1, VER1_5); //Supports XGETBV with ECX = 1 - EXP_CPUID_BIT(0xd, 0x1, eax, 3, 1, VER1_0 | VER1_5); //Supports XSAVES/XRSTORS and IA32_XSS - EXP_CPUID_RES_BITS(0xd, 0x1, eax, 5, 31, VER1_0 | VER1_5); //Reserved + EXP_CPUID_BIT(0xd, 0x1, eax, 3, 1, VER1_0 | VER1_5 | VER2_0); //Supports XSAVES/XRSTORS and IA32_XSS + EXP_CPUID_RES_BITS(0xd, 0x1, eax, 5, 31, VER1_0 | VER1_5 | VER2_0); //Reserved /* CPUID(0xd, 0x1).ECX */ - EXP_CPUID_RES_BITS(0xd, 0x1, ecx, 0, 7, VER1_0 | VER1_5); //Reserved - EXP_CPUID_BIT(0xd, 0x1, ecx, 9, 0, VER1_0 | VER1_5); //Reserved - EXP_CPUID_BIT(0xd, 0x1, ecx, 10, 0, VER1_0 | VER1_5); //PASID - EXP_CPUID_BIT(0xd, 0x1, ecx, 13, 0, VER1_0 | VER1_5); //HDC - EXP_CPUID_BIT(0xd, 0x1, ecx, 16, 0, VER1_0 | VER1_5); //HDC - EXP_CPUID_RES_BITS(0xd, 0x1, ecx, 17, 31, VER1_0 | VER1_5); //Reserved + EXP_CPUID_RES_BITS(0xd, 0x1, ecx, 0, 7, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_BIT(0xd, 0x1, ecx, 9, 0, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_BIT(0xd, 0x1, ecx, 10, 0, VER1_0 | VER1_5 | VER2_0); //PASID + EXP_CPUID_BIT(0xd, 0x1, ecx, 13, 0, VER1_0 | VER1_5 | VER2_0); //HDC + EXP_CPUID_BIT(0xd, 0x1, ecx, 16, 0, VER1_0 | VER1_5 | VER2_0); //HDC + EXP_CPUID_RES_BITS(0xd, 0x1, ecx, 17, 31, VER1_0 | VER1_5 | VER2_0); //Reserved /* CPUID(0xd, 0x1).EDX */ - EXP_CPUID_RES_BITS(0xd, 0x1, edx, 0, 31, VER1_0 | VER1_5); //Reserved + EXP_CPUID_RES_BITS(0xd, 0x1, edx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved /* CPUID(0xd, 0x2-0x12).EDX */ - EXP_CPUID_RES_BITS(0xd, 0x2, edx, 0, 31, VER1_5); //Reserved_0_31 - EXP_CPUID_RES_BITS(0xd, 0x3, edx, 0, 31, VER1_5); //Reserved_0_31 - EXP_CPUID_RES_BITS(0xd, 0x4, edx, 0, 31, VER1_5); //Reserved_0_31 - EXP_CPUID_RES_BITS(0xd, 0x5, edx, 0, 31, VER1_5); //Reserved_0_31 - EXP_CPUID_RES_BITS(0xd, 0x6, edx, 0, 31, VER1_5); //Reserved_0_31 - EXP_CPUID_RES_BITS(0xd, 0x7, edx, 0, 31, VER1_5); //Reserved_0_31 - EXP_CPUID_RES_BITS(0xd, 0x8, edx, 0, 31, VER1_5); //Reserved_0_31 - EXP_CPUID_RES_BITS(0xd, 0x9, edx, 0, 31, VER1_5); //Reserved_0_31 - EXP_CPUID_RES_BITS(0xd, 0xa, edx, 0, 31, VER1_5); //Reserved_0_31 - EXP_CPUID_RES_BITS(0xd, 0xb, edx, 0, 31, VER1_5); //Reserved_0_31 - EXP_CPUID_RES_BITS(0xd, 0xc, edx, 0, 31, VER1_5); //Reserved_0_31 - EXP_CPUID_RES_BITS(0xd, 0xd, edx, 0, 31, VER1_5); //Reserved_0_31 - EXP_CPUID_RES_BITS(0xd, 0xe, edx, 0, 31, VER1_5); //Reserved_0_31 - EXP_CPUID_RES_BITS(0xd, 0xf, edx, 0, 31, VER1_5); //Reserved_0_31 - EXP_CPUID_RES_BITS(0xd, 0x10, edx, 0, 31, VER1_5); //Reserved_0_31 - EXP_CPUID_RES_BITS(0xd, 0x11, edx, 0, 31, VER1_5); //Reserved_0_31 - EXP_CPUID_RES_BITS(0xd, 0x12, edx, 0, 31, VER1_5); //Reserved_0_31 + EXP_CPUID_RES_BITS(0xd, 0x2, edx, 0, 31, VER1_5 | VER2_0); //Reserved_0_31 + EXP_CPUID_RES_BITS(0xd, 0x3, edx, 0, 31, VER1_5 | VER2_0); //Reserved_0_31 + EXP_CPUID_RES_BITS(0xd, 0x4, edx, 0, 31, VER1_5 | VER2_0); //Reserved_0_31 + EXP_CPUID_RES_BITS(0xd, 0x5, edx, 0, 31, VER1_5 | VER2_0); //Reserved_0_31 + EXP_CPUID_RES_BITS(0xd, 0x6, edx, 0, 31, VER1_5 | VER2_0); //Reserved_0_31 + EXP_CPUID_RES_BITS(0xd, 0x7, edx, 0, 31, VER1_5 | VER2_0); //Reserved_0_31 + EXP_CPUID_RES_BITS(0xd, 0x8, edx, 0, 31, VER1_5 | VER2_0); //Reserved_0_31 + EXP_CPUID_RES_BITS(0xd, 0x9, edx, 0, 31, VER1_5 | VER2_0); //Reserved_0_31 + EXP_CPUID_RES_BITS(0xd, 0xa, edx, 0, 31, VER1_5 | VER2_0); //Reserved_0_31 + EXP_CPUID_RES_BITS(0xd, 0xb, edx, 0, 31, VER1_5 | VER2_0); //Reserved_0_31 + EXP_CPUID_RES_BITS(0xd, 0xc, edx, 0, 31, VER1_5 | VER2_0); //Reserved_0_31 + EXP_CPUID_RES_BITS(0xd, 0xd, edx, 0, 31, VER1_5 | VER2_0); //Reserved_0_31 + EXP_CPUID_RES_BITS(0xd, 0xe, edx, 0, 31, VER1_5 | VER2_0); //Reserved_0_31 + EXP_CPUID_RES_BITS(0xd, 0xf, edx, 0, 31, VER1_5 | VER2_0); //Reserved_0_31 + EXP_CPUID_RES_BITS(0xd, 0x10, edx, 0, 31, VER1_5 | VER2_0); //Reserved_0_31 + EXP_CPUID_RES_BITS(0xd, 0x11, edx, 0, 31, VER1_5 | VER2_0); //Reserved_0_31 + EXP_CPUID_RES_BITS(0xd, 0x12, edx, 0, 31, VER1_5 | VER2_0); //Reserved_0_31 /* CPUID(0xe, 0x0) */ - EXP_CPUID_RES_BITS(0xe, 0x0, eax, 0, 31, VER1_0 | VER1_5); //Reserved - EXP_CPUID_RES_BITS(0xe, 0x0, ebx, 0, 31, VER1_0 | VER1_5); //Reserved - EXP_CPUID_RES_BITS(0xe, 0x0, ecx, 0, 31, VER1_0 | VER1_5); //Reserved - EXP_CPUID_RES_BITS(0xe, 0x0, edx, 0, 31, VER1_0 | VER1_5); //Reserved + EXP_CPUID_RES_BITS(0xe, 0x0, eax, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_RES_BITS(0xe, 0x0, ebx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_RES_BITS(0xe, 0x0, ecx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_RES_BITS(0xe, 0x0, edx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved /* CPUID(0x11, 0x0) */ - EXP_CPUID_RES_BITS(0x11, 0x0, eax, 0, 31, VER1_0 | VER1_5); //Reserved - EXP_CPUID_RES_BITS(0x11, 0x0, ebx, 0, 31, VER1_0 | VER1_5); //Reserved - EXP_CPUID_RES_BITS(0x11, 0x0, ecx, 0, 31, VER1_0 | VER1_5); //Reserved - EXP_CPUID_RES_BITS(0x11, 0x0, edx, 0, 31, VER1_0 | VER1_5); //Reserved + EXP_CPUID_RES_BITS(0x11, 0x0, eax, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_RES_BITS(0x11, 0x0, ebx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_RES_BITS(0x11, 0x0, ecx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_RES_BITS(0x11, 0x0, edx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved /* CPUID(0x12, 0x0) */ - EXP_CPUID_RES_BITS(0x12, 0x0, eax, 0, 31, VER1_0 | VER1_5); //Reserved - EXP_CPUID_RES_BITS(0x12, 0x0, ebx, 0, 31, VER1_0 | VER1_5); //Reserved - EXP_CPUID_RES_BITS(0x12, 0x0, ecx, 0, 31, VER1_0 | VER1_5); //Reserved - EXP_CPUID_RES_BITS(0x12, 0x0, edx, 0, 31, VER1_0 | VER1_5); //Reserved + EXP_CPUID_RES_BITS(0x12, 0x0, eax, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_RES_BITS(0x12, 0x0, ebx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_RES_BITS(0x12, 0x0, ecx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_RES_BITS(0x12, 0x0, edx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved /* CPUID(0x13, 0x0) */ - EXP_CPUID_RES_BITS(0x13, 0x0, eax, 0, 31, VER1_0 | VER1_5); //Reserved - EXP_CPUID_RES_BITS(0x13, 0x0, ebx, 0, 31, VER1_0 | VER1_5); //Reserved - EXP_CPUID_RES_BITS(0x13, 0x0, ecx, 0, 31, VER1_0 | VER1_5); //Reserved - EXP_CPUID_RES_BITS(0x13, 0x0, edx, 0, 31, VER1_0 | VER1_5); //Reserved + EXP_CPUID_RES_BITS(0x13, 0x0, eax, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_RES_BITS(0x13, 0x0, ebx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_RES_BITS(0x13, 0x0, ecx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_RES_BITS(0x13, 0x0, edx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved /* CPUID(0x15, 0x0).EAX */ - EXP_CPUID_BYTE(0x15, 0x0, eax, 0x1, VER1_0 | VER1_5); //Denominator + EXP_CPUID_BYTE(0x15, 0x0, eax, 0x1, VER1_0 | VER1_5 | VER2_0); //Denominator /* CPUID(0x15, 0x0).ECX */ - EXP_CPUID_BYTE(0x15, 0x0, ecx, 0x017d7840, VER1_0 | VER1_5); //Nominal ART Frequency + EXP_CPUID_BYTE(0x15, 0x0, ecx, 0x017d7840, VER1_0 | VER1_5 | VER2_0); //Nominal ART Frequency /* CPUID(0x15, 0x0).EDX */ - EXP_CPUID_RES_BITS(0x15, 0x0, edx, 0, 31, VER1_0 | VER1_5); //Reserved + EXP_CPUID_RES_BITS(0x15, 0x0, edx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved /* CPUID(0x19, 0x0).EAX */ EXP_CPUID_RES_BITS(0x19, 0x0, eax, 3, 31, VER1_5); //Reserved @@ -422,25 +424,25 @@ void initial_cpuid(void) /* CPUID(0x19, 0x0).ECX */ EXP_CPUID_BIT(0x19, 0x0, ecx, 0, 0, VER1_5); //LOADIWKey Support - EXP_CPUID_BIT(0x19, 0x0, ecx, 1, 0, VER1_0); //Random IWKey Support - EXP_CPUID_RES_BITS(0x19, 0x0, ecx, 2, 31, VER1_0 | VER1_5); //Reserved + EXP_CPUID_BIT(0x19, 0x0, ecx, 1, 0, VER1_0 | VER2_0); //Random IWKey Support + EXP_CPUID_RES_BITS(0x19, 0x0, ecx, 2, 31, VER1_0 | VER1_5 | VER2_0); //Reserved /* CPUID(0x19, 0x0).EDX */ - EXP_CPUID_RES_BITS(0x19, 0x0, edx, 0, 31, VER1_0 | VER1_5); //Reserved + EXP_CPUID_RES_BITS(0x19, 0x0, edx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved /* CPUID(0x20, 0x0) */ - EXP_CPUID_RES_BITS(0x20, 0x0, eax, 0, 31, VER1_0 | VER1_5); //Reserved - EXP_CPUID_RES_BITS(0x20, 0x0, ebx, 0, 31, VER1_0 | VER1_5); //Reserved - EXP_CPUID_RES_BITS(0x20, 0x0, ecx, 0, 31, VER1_0 | VER1_5); //Reserved - EXP_CPUID_RES_BITS(0x20, 0x0, edx, 0, 31, VER1_0 | VER1_5); //Reserved + EXP_CPUID_RES_BITS(0x20, 0x0, eax, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_RES_BITS(0x20, 0x0, ebx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_RES_BITS(0x20, 0x0, ecx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_RES_BITS(0x20, 0x0, edx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved /* CPUID(0x21, 0x0).EAX */ - EXP_CPUID_BYTE(0x21, 0x0, eax, 0x0, VER1_0 | VER1_5); //Maximum sub-leaf + EXP_CPUID_BYTE(0x21, 0x0, eax, 0x0, VER1_0 | VER1_5 | VER2_0); //Maximum sub-leaf /* CPUID(0x21, 0x0).EBX */ - EXP_CPUID_BYTE(0x21, 0x0, ebx, 0x65746E49, VER1_0 | VER1_5); //"Intel" + EXP_CPUID_BYTE(0x21, 0x0, ebx, 0x65746E49, VER1_0 | VER1_5 | VER2_0); //"Intel" /* CPUID(0x21, 0x0).ECX */ - EXP_CPUID_BYTE(0x21, 0x0, ecx, 0x20202020, VER1_0 | VER1_5); //" " + EXP_CPUID_BYTE(0x21, 0x0, ecx, 0x20202020, VER1_0 | VER1_5 | VER2_0); //" " /* CPUID(0x21, 0x0).EDX */ - EXP_CPUID_BYTE(0x21, 0x0, edx, 0x5844546C, VER1_0 | VER1_5); //"lTDX" + EXP_CPUID_BYTE(0x21, 0x0, edx, 0x5844546C, VER1_0 | VER1_5 | VER2_0); //"lTDX" /* CPUID(0x22, 0x0) */ EXP_CPUID_RES_BITS(0x22, 0x0, eax, 0, 31, VER1_5); //Reserved @@ -481,34 +483,34 @@ void initial_cpuid(void) /* CPUID(0x80000000).EAX */ EXP_CPUID_BYTE(0x80000000, 0x0, eax, 0x80000008, VER1_5); //MaxIndex /* CPUID(0x80000000).EBX */ - EXP_CPUID_RES_BITS(0x80000000, 0x0, ebx, 0, 31, VER1_0 | VER1_5); //Reserved + EXP_CPUID_RES_BITS(0x80000000, 0x0, ebx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved /* CPUID(0x80000000).ECX */ - EXP_CPUID_RES_BITS(0x80000000, 0x0, ecx, 0, 31, VER1_0 | VER1_5); //Reserved + EXP_CPUID_RES_BITS(0x80000000, 0x0, ecx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved /* CPUID(0x80000000).EDX */ - EXP_CPUID_RES_BITS(0x80000000, 0x0, edx, 0, 31, VER1_0 | VER1_5); //Reserved + EXP_CPUID_RES_BITS(0x80000000, 0x0, edx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved /* CPUID(0x80000001).EAX */ - EXP_CPUID_RES_BITS(0x80000001, 0x0, eax, 0, 31, VER1_0 | VER1_5); //Reserved + EXP_CPUID_RES_BITS(0x80000001, 0x0, eax, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved /* CPUID(0x80000001).EBX */ - EXP_CPUID_RES_BITS(0x80000001, 0x0, ebx, 0, 31, VER1_0 | VER1_5); //Reserved + EXP_CPUID_RES_BITS(0x80000001, 0x0, ebx, 0, 31, VER1_0 | VER1_5 | VER2_0); //Reserved /* CPUID(0x80000001).ECX */ EXP_CPUID_BIT(0x80000001, 0x0, ecx, 0, 1, VER1_5); //LAHF/SAHF in 64-bit Mode - EXP_CPUID_RES_BITS(0x80000001, 0x0, ecx, 1, 4, VER1_0 | VER1_5); //Reserved + EXP_CPUID_RES_BITS(0x80000001, 0x0, ecx, 1, 4, VER1_0 | VER1_5 | VER2_0); //Reserved EXP_CPUID_BIT(0x80000001, 0x0, ecx, 5, 1, VER1_5); //LZCNT - EXP_CPUID_RES_BITS(0x80000001, 0x0, ecx, 6, 7, VER1_0 | VER1_5); //Reserved + EXP_CPUID_RES_BITS(0x80000001, 0x0, ecx, 6, 7, VER1_0 | VER1_5 | VER2_0); //Reserved EXP_CPUID_BIT(0x80000001, 0x0, ecx, 8, 1, VER1_5); //PREFETCHW - EXP_CPUID_RES_BITS(0x80000001, 0x0, ecx, 9, 31, VER1_0 | VER1_5); //Reserved + EXP_CPUID_RES_BITS(0x80000001, 0x0, ecx, 9, 31, VER1_0 | VER1_5 | VER2_0); //Reserved /* CPUID(0x80000001).EDX */ - EXP_CPUID_RES_BITS(0x80000001, 0x0, edx, 0, 10, VER1_0 | VER1_5); //Reserved - EXP_CPUID_RES_BITS(0x80000001, 0x0, edx, 12, 19, VER1_0 | VER1_5); //Reserved - EXP_CPUID_BIT(0x80000001, 0x0, edx, 20, 1, VER1_0 | VER1_5); //Execute Dis Bit - EXP_CPUID_RES_BITS(0x80000001, 0x0, edx, 21, 25, VER1_0 | VER1_5); //Reserved - EXP_CPUID_BIT(0x80000001, 0x0, edx, 26, 1, VER1_0 | VER1_5); //1GB Pages - EXP_CPUID_BIT(0x80000001, 0x0, edx, 27, 1, VER1_0 | VER1_5); //RDTSCP - EXP_CPUID_BIT(0x80000001, 0x0, edx, 28, 0, VER1_0 | VER1_5); //Reserved - EXP_CPUID_BIT(0x80000001, 0x0, edx, 29, 1, VER1_0 | VER1_5); //Intel 64 - EXP_CPUID_RES_BITS(0x80000001, 0x0, edx, 30, 31, VER1_0 | VER1_5); //Reserved + EXP_CPUID_RES_BITS(0x80000001, 0x0, edx, 0, 10, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_RES_BITS(0x80000001, 0x0, edx, 12, 19, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_BIT(0x80000001, 0x0, edx, 20, 1, VER1_0 | VER1_5 | VER2_0); //Execute Dis Bit + EXP_CPUID_RES_BITS(0x80000001, 0x0, edx, 21, 25, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_BIT(0x80000001, 0x0, edx, 26, 1, VER1_0 | VER1_5 | VER2_0); //1GB Pages + EXP_CPUID_BIT(0x80000001, 0x0, edx, 27, 1, VER1_0 | VER1_5 | VER2_0); //RDTSCP + EXP_CPUID_BIT(0x80000001, 0x0, edx, 28, 0, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_BIT(0x80000001, 0x0, edx, 29, 1, VER1_0 | VER1_5 | VER2_0); //Intel 64 + EXP_CPUID_RES_BITS(0x80000001, 0x0, edx, 30, 31, VER1_0 | VER1_5 | VER2_0); //Reserved /* CPUID(0x80000007).EAX */ EXP_CPUID_RES_BITS(0x80000007, 0x0, eax, 0, 31, VER1_5); //Reserved @@ -523,24 +525,25 @@ void initial_cpuid(void) /* CPUID(0x80000008).EAX */ /* CPUID.EAX[0:7] Number of Physical Address Bits */ - EXP_CPUID_BIT(0x80000008, 0x0, eax, 0, 0, VER1_0 | VER1_5); - EXP_CPUID_BIT(0x80000008, 0x0, eax, 1, 0, VER1_0 | VER1_5); - EXP_CPUID_BIT(0x80000008, 0x0, eax, 2, 1, VER1_0 | VER1_5); - EXP_CPUID_BIT(0x80000008, 0x0, eax, 3, 0, VER1_0 | VER1_5); - EXP_CPUID_BIT(0x80000008, 0x0, eax, 4, 1, VER1_0 | VER1_5); - EXP_CPUID_BIT(0x80000008, 0x0, eax, 5, 1, VER1_0 | VER1_5); - EXP_CPUID_BIT(0x80000008, 0x0, eax, 6, 0, VER1_0 | VER1_5); - EXP_CPUID_BIT(0x80000008, 0x0, eax, 7, 0, VER1_0 | VER1_5); - EXP_CPUID_RES_BITS(0x80000008, 0x0, eax, 16, 31, VER1_0 | VER1_5); //Reserved + EXP_CPUID_BIT(0x80000008, 0x0, eax, 0, 0, VER1_0 | VER1_5 | VER2_0); + EXP_CPUID_BIT(0x80000008, 0x0, eax, 1, 0, VER1_0 | VER1_5 | VER2_0); + EXP_CPUID_BIT(0x80000008, 0x0, eax, 2, 1, VER1_0 | VER1_5 | VER2_0); + EXP_CPUID_BIT(0x80000008, 0x0, eax, 3, 0, VER1_0 | VER1_5 | VER2_0); + EXP_CPUID_BIT(0x80000008, 0x0, eax, 4, 1, VER1_0 | VER1_5 | VER2_0); + EXP_CPUID_BIT(0x80000008, 0x0, eax, 5, 1, VER1_0 | VER1_5 | VER2_0); + EXP_CPUID_BIT(0x80000008, 0x0, eax, 6, 0, VER1_0 | VER1_5 | VER2_0); + EXP_CPUID_BIT(0x80000008, 0x0, eax, 7, 0, VER1_0 | VER1_5 | VER2_0); + EXP_CPUID_RES_BITS(0x80000008, 0x0, eax, 16, 31, VER1_0 | VER1_5 | VER2_0); //Reserved /* CPUID(0x80000008).EBX */ - EXP_CPUID_RES_BITS(0x80000008, 0x0, ebx, 0, 8, VER1_0 | VER1_5); //Reserved - EXP_CPUID_RES_BITS(0x80000008, 0x0, ebx, 10, 31, VER1_0); //Reserved + EXP_CPUID_RES_BITS(0x80000008, 0x0, ebx, 0, 8, VER1_0 | VER1_5 | VER2_0); //Reserved + EXP_CPUID_BIT(0x80000008, 0x0, ebx, 9, 1, VER2_0); //WBNOINVD support + EXP_CPUID_RES_BITS(0x80000008, 0x0, ebx, 10, 31, VER1_0 | VER2_0); //Reserved /* CPUID(0x80000008).ECX */ - EXP_CPUID_RES_BITS(0x80000008, 0x0, ecx, 0, 31, VER1_0); //Reserved + EXP_CPUID_RES_BITS(0x80000008, 0x0, ecx, 0, 31, VER1_0 | VER2_0); //Reserved /* CPUID(0x80000008).EDX */ - EXP_CPUID_RES_BITS(0x80000008, 0x0, edx, 0, 31, VER1_0); //Reserved + EXP_CPUID_RES_BITS(0x80000008, 0x0, edx, 0, 31, VER1_0 | VER2_0); //Reserved } #endif diff --git a/tdx-compliance/tdx-compliance-cr.h b/tdx-compliance/tdx-compliance-cr.h index 0a78d50..e216bc5 100644 --- a/tdx-compliance/tdx-compliance-cr.h +++ b/tdx-compliance/tdx-compliance-cr.h @@ -196,34 +196,34 @@ struct test_cr cr_list[] = { * bits PE(0) and NE(5) are always set to 1 * bits NW(29) and CD(30) are always cleared to 0 */ - DEF_GET_CR0(X86_CR0_CD, BIT_CLEAR, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_GET_CR0(X86_CR0_NW, BIT_CLEAR, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_GET_CR0(X86_CR0_PE, BIT_SET, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_GET_CR0(X86_CR0_NE, BIT_SET, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), + DEF_GET_CR0(X86_CR0_CD, BIT_CLEAR, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_GET_CR0(X86_CR0_NW, BIT_CLEAR, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_GET_CR0(X86_CR0_PE, BIT_SET, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_GET_CR0(X86_CR0_NE, BIT_SET, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), - DEF_GET_CR4(X86_CR4_SMXE, BIT_CLEAR, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_GET_CR4(X86_CR4_VMXE, BIT_CLEAR, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_GET_CR4(X86_CR4_MCE, BIT_SET, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), + DEF_GET_CR4(X86_CR4_SMXE, BIT_CLEAR, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_GET_CR4(X86_CR4_VMXE, BIT_CLEAR, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_GET_CR4(X86_CR4_MCE, BIT_SET, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), - DEF_CLEAR_CR0(X86_CR0_PE, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_CLEAR_CR0(X86_CR0_NE, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_CLEAR_CR0(X86_CR0_PE | X86_CR0_PG, NO_EXCP, pre_cond_cr0_combine, VER1_0 | VER1_5), + DEF_CLEAR_CR0(X86_CR0_PE, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_CLEAR_CR0(X86_CR0_NE, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_CLEAR_CR0(X86_CR0_PE | X86_CR0_PG, NO_EXCP, pre_cond_cr0_combine, VER1_0 | VER1_5 | VER2_0), - DEF_SET_CR0(X86_CR0_NW, X86_TRAP_VE, NO_PRE_COND, VER1_0 | VER1_5), - DEF_SET_CR0(X86_CR0_CD, X86_TRAP_VE, NO_PRE_COND, VER1_0 | VER1_5), + DEF_SET_CR0(X86_CR0_NW, X86_TRAP_VE, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_SET_CR0(X86_CR0_CD, X86_TRAP_VE, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), /* * TD attempts to modify them results in a #VE, * bits VMXE(13) and SMXE(14) are fixed to 0. */ - DEF_XCH_CR4(X86_CR4_VMXE, X86_TRAP_VE, NO_PRE_COND, VER1_0 | VER1_5), - DEF_XCH_CR4(X86_CR4_SMXE, X86_TRAP_VE, NO_PRE_COND, VER1_0 | VER1_5), + DEF_XCH_CR4(X86_CR4_VMXE, X86_TRAP_VE, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_XCH_CR4(X86_CR4_SMXE, X86_TRAP_VE, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), /* * TD attempts to modify bit MCE(6) results in a #VE, * bits MCE(6) are fixed to 1. */ - DEF_XCH_CR4(X86_CR4_MCE, X86_TRAP_VE, NO_PRE_COND, VER1_0 | VER1_5), + DEF_XCH_CR4(X86_CR4_MCE, X86_TRAP_VE, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), /* * TD attempts to set bit PCE(8) results in a #GP(0), @@ -235,29 +235,29 @@ struct test_cr cr_list[] = { * TD attempts to set bit KL(19) results in a #GP(0), * if the TD's ATTRIBUTES.KL is 0. */ - DEF_SET_CR4(X86_CR4_KL, NO_EXCP, pre_cond_cr4_kl, VER1_0 | VER1_5), + DEF_SET_CR4(X86_CR4_KL, NO_EXCP, pre_cond_cr4_kl, VER1_0 | VER1_5 | VER2_0), /* * TD attempts to set bit PKS(24) results in a #GP(0), * if the TD's ATTRIBUTES.PKS is 0. */ - DEF_SET_CR4(X86_CR4_PKS, NO_EXCP, pre_cond_cr4_pks, VER1_0 | VER1_5), + DEF_SET_CR4(X86_CR4_PKS, NO_EXCP, pre_cond_cr4_pks, VER1_0 | VER1_5 | VER2_0), /* * TD modification of CR4 bit PKE(22) is prevented, * depending on TD's XFAM. */ - DEF_XCH_CR4(X86_CR4_PKE, NO_EXCP, pre_cond_cr4_pke, VER1_0 | VER1_5), + DEF_XCH_CR4(X86_CR4_PKE, NO_EXCP, pre_cond_cr4_pke, VER1_0 | VER1_5 | VER2_0), /* * TD modification of CR4 bit CET(23) is prevented, * depending on TD's XFAM. */ - DEF_XCH_CR4(X86_CR4_CET, NO_EXCP, pre_cond_cr4_cet, VER1_0 | VER1_5), + DEF_XCH_CR4(X86_CR4_CET, NO_EXCP, pre_cond_cr4_cet, VER1_0 | VER1_5 | VER2_0), /* * TD modification of CR4 bit UINT(25) is prevented, * depending on TD's XFAM */ - DEF_XCH_CR4(X86_CR4_UINT, NO_EXCP, pre_cond_cr4_uint, VER1_0 | VER1_5), + DEF_XCH_CR4(X86_CR4_UINT, NO_EXCP, pre_cond_cr4_uint, VER1_0 | VER1_5 | VER2_0), }; diff --git a/tdx-compliance/tdx-compliance-msr.h b/tdx-compliance/tdx-compliance-msr.h index eabbbe2..52a8632 100644 --- a/tdx-compliance/tdx-compliance-msr.h +++ b/tdx-compliance/tdx-compliance-msr.h @@ -39,8 +39,11 @@ #define IA32_PERF_GLOBAL_STATUS_SET 0x0391 #define IA32_PERF_GLOBAL_INUSE 0x0392 #define IA32_SGX_SVN_STATUS 0x0500 +#define IA32_SE_SVN_EXPAN 0x0501 #define IA32_PKRS 0x06e1 #define RESERVED_XAPIC_0X0800 0x0800 +#define IA32_X2APIC_APICID 0x0802 +#define IA32_X2APIC_VERSION 0x0803 #define RESERVED_XAPIC_0X0804 0x0804 #define IA32_X2APIC_TPR 0x0808 #define RESERVED_XAPIC_0X0809 0x0809 @@ -69,14 +72,6 @@ #define IA32_UINT_TT 0x098a #define IA32_DEBUG_INTERFACE 0x0c80 #define IA32_UARCH_MISC_CTL 0x1b01 -#define RESERVED_0X0550 0x0550 -#define RESERVED_0X09A0 0x09a0 -#define RESERVED_0X09C0 0x09c0 -#define RESERVED_0X09E0 0x09e0 -#define RESERVED_0X09F0 0x09f0 -#define RESERVED_0X1921 0x1921 -#define RESERVED_0X1925 0x1925 -#define RESERVED_0X1981 0x1981 /* pre-conditions */ static int get_perfmon(void) { @@ -242,300 +237,317 @@ static void pre_fixedctr(struct test_msr *c) } struct test_msr msr_cases[] = { - DEF_READ_MSR(MSR_IA32_TSC, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_TSC, X86_TRAP_VE, NO_PRE_COND, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_SPEC_CTRL, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_SPEC_CTRL, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), + DEF_READ_MSR(MSR_IA32_PLATFORM_ID, X86_TRAP_VE, NO_PRE_COND, VER1_5), + DEF_WRITE_MSR(MSR_IA32_PLATFORM_ID, X86_TRAP_VE, NO_PRE_COND, VER1_5), + /* according to MSR Index & Name, Ihis is a Guest behavior. */ + DEF_READ_MSR(MSR_IA32_APICBASE, NO_EXCP, NO_PRE_COND, VER1_5), + DEF_WRITE_MSR(MSR_IA32_APICBASE, X86_TRAP_VE, NO_PRE_COND, VER1_5), + DEF_READ_MSR(MSR_TEST_CTRL, X86_TRAP_VE, NO_PRE_COND, VER1_5), + DEF_WRITE_MSR(MSR_TEST_CTRL, X86_TRAP_VE, NO_PRE_COND, VER1_5), + DEF_READ_MSR(MSR_IA32_TSC_ADJUST, X86_TRAP_VE, NO_PRE_COND, VER1_5), + DEF_WRITE_MSR(MSR_IA32_TSC_ADJUST, X86_TRAP_VE, NO_PRE_COND, VER1_5), + DEF_READ_MSR(MSR_IA32_TSC, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_TSC, X86_TRAP_VE, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_SPEC_CTRL, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_SPEC_CTRL, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), DEF_READ_MSR(MSR_IA32_PRED_CMD, NO_EXCP, NO_PRE_COND, VER1_0), - DEF_READ_MSR(MSR_IA32_PRED_CMD, X86_TRAP_GP, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(MSR_IA32_PRED_CMD, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_MKTME_PARTITIONING, X86_TRAP_VE, pre_0x7_edx18, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_MKTME_PARTITIONING, X86_TRAP_VE, pre_0x7_edx18, VER1_0 | VER1_5), - DEF_READ_MSR_SIZE(MSR_IA32_SGXLEPUBKEYHASH0, X86_TRAP_GP, NO_PRE_COND, 0x4, VER1_0 | VER1_5), - DEF_WRITE_MSR_SIZE(MSR_IA32_SGXLEPUBKEYHASH0, X86_TRAP_GP, NO_PRE_COND, 0x4, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_WBINVDP, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_WBINVDP, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_WBNOINVDP, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_WBNOINVDP, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_INTR_PENDING, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_INTR_PENDING, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_SMM_MONITOR_CTL, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_SMM_MONITOR_CTL, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_SMBASE, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_SMBASE, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_READ_MSR(IA32_MISC_PACKAGE_CTLS, NO_EXCP, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(IA32_MISC_PACKAGE_CTLS, X86_TRAP_VE, NO_PRE_COND, VER1_5), - DEF_READ_MSR_SIZE(MSR_IA32_PERFCTR0, NO_EXCP, pre_perfmon, 0x8, VER1_5), - DEF_WRITE_MSR_SIZE(MSR_IA32_PERFCTR0, NO_EXCP, pre_perfmon, 0x8, VER1_5), - DEF_READ_MSR(MSR_IA32_UMWAIT_CONTROL, NO_EXCP, pre_0x7_ecx5, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_UMWAIT_CONTROL, NO_EXCP, pre_0x7_ecx5, VER1_0 | VER1_5), + DEF_READ_MSR(MSR_IA32_PRED_CMD, X86_TRAP_GP, NO_PRE_COND, VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_PRED_CMD, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_MKTME_PARTITIONING, X86_TRAP_VE, pre_0x7_edx18, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_MKTME_PARTITIONING, X86_TRAP_VE, pre_0x7_edx18, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR_SIZE(MSR_IA32_SGXLEPUBKEYHASH0, X86_TRAP_GP, NO_PRE_COND, 0x4, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR_SIZE(MSR_IA32_SGXLEPUBKEYHASH0, X86_TRAP_GP, NO_PRE_COND, 0x4, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_WBINVDP, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_WBINVDP, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_WBNOINVDP, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_WBNOINVDP, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_INTR_PENDING, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_INTR_PENDING, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_SMM_MONITOR_CTL, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_SMM_MONITOR_CTL, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_SMBASE, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_SMBASE, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(IA32_MISC_PACKAGE_CTLS, NO_EXCP, NO_PRE_COND, VER1_5 | VER2_0), + DEF_WRITE_MSR(IA32_MISC_PACKAGE_CTLS, X86_TRAP_VE, NO_PRE_COND, VER1_5 | VER2_0), + DEF_READ_MSR_SIZE(MSR_IA32_PERFCTR0, NO_EXCP, pre_perfmon, 0x8, VER1_5 | VER2_0), + DEF_WRITE_MSR_SIZE(MSR_IA32_PERFCTR0, NO_EXCP, pre_perfmon, 0x8, VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_UMWAIT_CONTROL, NO_EXCP, pre_0x7_ecx5, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_UMWAIT_CONTROL, NO_EXCP, pre_0x7_ecx5, VER1_0 | VER1_5 | VER2_0), DEF_WRITE_MSR(MSR_IA32_ARCH_CAPABILITIES, NO_EXCP, NO_PRE_COND, VER1_0), - DEF_WRITE_MSR(MSR_IA32_ARCH_CAPABILITIES, X86_TRAP_GP, NO_PRE_COND, VER1_5), + DEF_WRITE_MSR(MSR_IA32_ARCH_CAPABILITIES, X86_TRAP_GP, NO_PRE_COND, VER1_5 | VER2_0), DEF_READ_MSR(MSR_IA32_FLUSH_CMD, NO_EXCP, NO_PRE_COND, VER1_0), - DEF_READ_MSR(MSR_IA32_FLUSH_CMD, X86_TRAP_GP, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(MSR_IA32_FLUSH_CMD, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), + DEF_READ_MSR(MSR_IA32_FLUSH_CMD, X86_TRAP_GP, NO_PRE_COND, VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_FLUSH_CMD, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), DEF_READ_MSR(MSR_IA32_TSX_CTRL, X86_TRAP_GP, NO_PRE_COND, VER1_0), DEF_WRITE_MSR(MSR_IA32_TSX_CTRL, X86_TRAP_GP, NO_PRE_COND, VER1_0), DEF_READ_MSR(MSR_IA32_TSX_CTRL, NO_EXCP, pre_tsx, VER1_5), DEF_WRITE_MSR(MSR_IA32_TSX_CTRL, NO_EXCP, pre_tsx, VER1_5), - DEF_READ_MSR(MSR_IA32_SYSENTER_CS, NO_EXCP, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(MSR_IA32_SYSENTER_CS, NO_EXCP, NO_PRE_COND, VER1_5), - DEF_READ_MSR(MSR_IA32_SYSENTER_ESP, NO_EXCP, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(MSR_IA32_SYSENTER_ESP, NO_EXCP, NO_PRE_COND, VER1_5), - DEF_READ_MSR(MSR_IA32_SYSENTER_EIP, NO_EXCP, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(MSR_IA32_SYSENTER_EIP, NO_EXCP, NO_PRE_COND, VER1_5), - DEF_READ_MSR_SIZE(MSR_P6_EVNTSEL0, NO_EXCP, pre_perfmon, 0x8, VER1_0 | VER1_5), - DEF_WRITE_MSR_SIZE(MSR_P6_EVNTSEL0, NO_EXCP, pre_perfmon, 0x8, VER1_0 | VER1_5), - - DEF_WRITE_MSR(MSR_IA32_MISC_ENABLE, X86_TRAP_VE, NO_PRE_COND, VER1_0 | VER1_5), - DEF_READ_MSR_SIZE(MSR_OFFCORE_RSP_0, NO_EXCP, pre_perfmon, 0x2, VER1_0 | VER1_5), - DEF_WRITE_MSR_SIZE(MSR_OFFCORE_RSP_0, NO_EXCP, pre_perfmon, 0x2, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_XFD, NO_EXCP, pre_0xd_0x1_eax4, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_XFD, NO_EXCP, pre_0xd_0x1_eax4, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_XFD_ERR, NO_EXCP, pre_0xd_0x1_eax4, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_XFD_ERR, NO_EXCP, pre_0xd_0x1_eax4, VER1_0 | VER1_5), - - DEF_READ_MSR(IA32_PLATFORM_DCA_CAP, X86_TRAP_VE, pre_0x1_ecx18, VER1_0 | VER1_5), - DEF_WRITE_MSR(IA32_PLATFORM_DCA_CAP, X86_TRAP_VE, pre_0x1_ecx18, VER1_0 | VER1_5), - DEF_READ_MSR(IA32_CPU_DCA_CAP, X86_TRAP_VE, pre_0x1_ecx18, VER1_0 | VER1_5), - DEF_WRITE_MSR(IA32_CPU_DCA_CAP, X86_TRAP_VE, pre_0x1_ecx18, VER1_0 | VER1_5), - DEF_READ_MSR(IA32_DCA_0_CAP, X86_TRAP_VE, pre_0x1_ecx18, VER1_0 | VER1_5), - DEF_WRITE_MSR(IA32_DCA_0_CAP, X86_TRAP_VE, pre_0x1_ecx18, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_SLAM_ENABLE, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_SLAM_ENABLE, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_CR_PAT, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_CR_PAT, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), + DEF_READ_MSR(MSR_IA32_TSX_CTRL, NO_EXCP, NO_PRE_COND, VER2_0), + DEF_WRITE_MSR(MSR_IA32_TSX_CTRL, NO_EXCP, NO_PRE_COND, VER2_0), + DEF_READ_MSR(MSR_IA32_SYSENTER_CS, NO_EXCP, NO_PRE_COND, VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_SYSENTER_CS, NO_EXCP, NO_PRE_COND, VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_SYSENTER_ESP, NO_EXCP, NO_PRE_COND, VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_SYSENTER_ESP, NO_EXCP, NO_PRE_COND, VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_SYSENTER_EIP, NO_EXCP, NO_PRE_COND, VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_SYSENTER_EIP, NO_EXCP, NO_PRE_COND, VER1_5 | VER2_0), + DEF_READ_MSR_SIZE(MSR_P6_EVNTSEL0, NO_EXCP, pre_perfmon, 0x8, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR_SIZE(MSR_P6_EVNTSEL0, NO_EXCP, pre_perfmon, 0x8, VER1_0 | VER1_5 | VER2_0), + + DEF_WRITE_MSR(MSR_IA32_MISC_ENABLE, X86_TRAP_VE, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR_SIZE(MSR_OFFCORE_RSP_0, NO_EXCP, pre_perfmon, 0x2, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR_SIZE(MSR_OFFCORE_RSP_0, NO_EXCP, pre_perfmon, 0x2, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_XFD, NO_EXCP, pre_0xd_0x1_eax4, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_XFD, NO_EXCP, pre_0xd_0x1_eax4, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_XFD_ERR, NO_EXCP, pre_0xd_0x1_eax4, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_XFD_ERR, NO_EXCP, pre_0xd_0x1_eax4, VER1_0 | VER1_5 | VER2_0), + + DEF_READ_MSR(IA32_PLATFORM_DCA_CAP, X86_TRAP_VE, pre_0x1_ecx18, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(IA32_PLATFORM_DCA_CAP, X86_TRAP_VE, pre_0x1_ecx18, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(IA32_CPU_DCA_CAP, X86_TRAP_VE, pre_0x1_ecx18, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(IA32_CPU_DCA_CAP, X86_TRAP_VE, pre_0x1_ecx18, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(IA32_DCA_0_CAP, X86_TRAP_VE, pre_0x1_ecx18, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(IA32_DCA_0_CAP, X86_TRAP_VE, pre_0x1_ecx18, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_SLAM_ENABLE, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_SLAM_ENABLE, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_CR_PAT, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_CR_PAT, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), DEF_READ_MSR_SIZE(MSR_CORE_PERF_FIXED_CTR0, NO_EXCP, pre_fixedctr, 0x8, VER1_0 | VER1_5), DEF_WRITE_MSR_SIZE(MSR_CORE_PERF_FIXED_CTR0, NO_EXCP, pre_fixedctr, 0x8, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_PERF_METRICS, NO_EXCP, pre_perfmon, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_PERF_METRICS, NO_EXCP, pre_perfmon, VER1_0 | VER1_5), - - DEF_WRITE_MSR(MSR_IA32_PERF_CAPABILITIES, X86_TRAP_GP, pre_perfmon, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_CORE_PERF_FIXED_CTR_CTRL, NO_EXCP, pre_perfmon, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_CORE_PERF_FIXED_CTR_CTRL, NO_EXCP, pre_perfmon, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_CORE_PERF_GLOBAL_STATUS, NO_EXCP, pre_perfmon, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_CORE_PERF_GLOBAL_STATUS, X86_TRAP_GP, pre_perfmon, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_CORE_PERF_GLOBAL_CTRL, NO_EXCP, pre_perfmon, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_CORE_PERF_GLOBAL_CTRL, NO_EXCP, pre_perfmon, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_CORE_PERF_GLOBAL_OVF_CTRL, NO_EXCP, pre_perfmon, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_CORE_PERF_GLOBAL_OVF_CTRL, NO_EXCP, pre_perfmon, VER1_0 | VER1_5), - DEF_READ_MSR(IA32_PERF_GLOBAL_STATUS_SET, NO_EXCP, pre_perfmon, VER1_0 | VER1_5), - DEF_WRITE_MSR(IA32_PERF_GLOBAL_STATUS_SET, NO_EXCP, pre_perfmon, VER1_0 | VER1_5), - DEF_READ_MSR(IA32_PERF_GLOBAL_INUSE, NO_EXCP, pre_perfmon, VER1_0 | VER1_5), - DEF_WRITE_MSR(IA32_PERF_GLOBAL_INUSE, X86_TRAP_GP, pre_perfmon, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_PEBS_ENABLE, NO_EXCP, pre_perfmon, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_PEBS_ENABLE, NO_EXCP, pre_perfmon, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_PEBS_DATA_CFG, NO_EXCP, pre_perfmon, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_PEBS_DATA_CFG, NO_EXCP, pre_perfmon, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_PEBS_LD_LAT_THRESHOLD, NO_EXCP, pre_perfmon, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_PEBS_LD_LAT_THRESHOLD, NO_EXCP, pre_perfmon, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_PEBS_FRONTEND, NO_EXCP, pre_perfmon, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_PEBS_FRONTEND, NO_EXCP, pre_perfmon, VER1_0 | VER1_5), + DEF_READ_MSR_SIZE(MSR_CORE_PERF_FIXED_CTR0, NO_EXCP, pre_fixedctr, 0x4, VER1_0 | VER1_5), + DEF_WRITE_MSR_SIZE(MSR_CORE_PERF_FIXED_CTR0, NO_EXCP, pre_fixedctr, 0x4, VER1_0 | VER1_5), + DEF_READ_MSR(MSR_PERF_METRICS, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_PERF_METRICS, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0), + + DEF_WRITE_MSR(MSR_IA32_PERF_CAPABILITIES, X86_TRAP_GP, pre_perfmon, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_CORE_PERF_FIXED_CTR_CTRL, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_CORE_PERF_FIXED_CTR_CTRL, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_CORE_PERF_GLOBAL_STATUS, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_CORE_PERF_GLOBAL_STATUS, X86_TRAP_GP, pre_perfmon, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_CORE_PERF_GLOBAL_CTRL, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_CORE_PERF_GLOBAL_CTRL, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_CORE_PERF_GLOBAL_OVF_CTRL, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_CORE_PERF_GLOBAL_OVF_CTRL, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(IA32_PERF_GLOBAL_STATUS_SET, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(IA32_PERF_GLOBAL_STATUS_SET, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(IA32_PERF_GLOBAL_INUSE, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(IA32_PERF_GLOBAL_INUSE, X86_TRAP_GP, pre_perfmon, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_PEBS_ENABLE, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_PEBS_ENABLE, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_PEBS_DATA_CFG, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_PEBS_DATA_CFG, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_PEBS_LD_LAT_THRESHOLD, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_PEBS_LD_LAT_THRESHOLD, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_PEBS_FRONTEND, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_PEBS_FRONTEND, NO_EXCP, pre_perfmon, VER1_0 | VER1_5 | VER2_0), DEF_READ_MSR(MSR_IA32_VMX_BASIC, X86_TRAP_GP, NO_PRE_COND, VER1_0), - DEF_READ_MSR(MSR_IA32_VMX_BASIC, NO_EXCP, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(MSR_IA32_VMX_BASIC, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), + DEF_READ_MSR(MSR_IA32_VMX_BASIC, NO_EXCP, NO_PRE_COND, VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_VMX_BASIC, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), DEF_READ_MSR(MSR_IA32_VMX_PINBASED_CTLS, X86_TRAP_GP, NO_PRE_COND, VER1_0), - DEF_READ_MSR(MSR_IA32_VMX_PINBASED_CTLS, X86_TRAP_VE, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(MSR_IA32_VMX_PINBASED_CTLS, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), + DEF_READ_MSR(MSR_IA32_VMX_PINBASED_CTLS, X86_TRAP_VE, NO_PRE_COND, VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_VMX_PINBASED_CTLS, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), DEF_READ_MSR(MSR_IA32_VMX_PROCBASED_CTLS, X86_TRAP_GP, NO_PRE_COND, VER1_0), - DEF_READ_MSR(MSR_IA32_VMX_PROCBASED_CTLS, X86_TRAP_VE, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(MSR_IA32_VMX_PROCBASED_CTLS, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), + DEF_READ_MSR(MSR_IA32_VMX_PROCBASED_CTLS, X86_TRAP_VE, NO_PRE_COND, VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_VMX_PROCBASED_CTLS, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), DEF_READ_MSR(MSR_IA32_VMX_EXIT_CTLS, X86_TRAP_GP, NO_PRE_COND, VER1_0), - DEF_READ_MSR(MSR_IA32_VMX_EXIT_CTLS, X86_TRAP_VE, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(MSR_IA32_VMX_EXIT_CTLS, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), + DEF_READ_MSR(MSR_IA32_VMX_EXIT_CTLS, X86_TRAP_VE, NO_PRE_COND, VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_VMX_EXIT_CTLS, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), DEF_READ_MSR(MSR_IA32_VMX_ENTRY_CTLS, X86_TRAP_GP, NO_PRE_COND, VER1_0), - DEF_READ_MSR(MSR_IA32_VMX_ENTRY_CTLS, X86_TRAP_VE, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(MSR_IA32_VMX_ENTRY_CTLS, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), + DEF_READ_MSR(MSR_IA32_VMX_ENTRY_CTLS, X86_TRAP_VE, NO_PRE_COND, VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_VMX_ENTRY_CTLS, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), DEF_READ_MSR(MSR_IA32_VMX_MISC, X86_TRAP_GP, NO_PRE_COND, VER1_0), - DEF_READ_MSR(MSR_IA32_VMX_MISC, NO_EXCP, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(MSR_IA32_VMX_MISC, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), + DEF_READ_MSR(MSR_IA32_VMX_MISC, NO_EXCP, NO_PRE_COND, VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_VMX_MISC, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), DEF_READ_MSR(MSR_IA32_VMX_CR0_FIXED0, X86_TRAP_GP, NO_PRE_COND, VER1_0), - DEF_READ_MSR(MSR_IA32_VMX_CR0_FIXED0, NO_EXCP, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(MSR_IA32_VMX_CR0_FIXED0, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), + DEF_READ_MSR(MSR_IA32_VMX_CR0_FIXED0, NO_EXCP, NO_PRE_COND, VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_VMX_CR0_FIXED0, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), DEF_READ_MSR(MSR_IA32_VMX_CR0_FIXED1, X86_TRAP_GP, NO_PRE_COND, VER1_0), - DEF_READ_MSR(MSR_IA32_VMX_CR0_FIXED1, NO_EXCP, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(MSR_IA32_VMX_CR0_FIXED1, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), + DEF_READ_MSR(MSR_IA32_VMX_CR0_FIXED1, NO_EXCP, NO_PRE_COND, VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_VMX_CR0_FIXED1, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), DEF_READ_MSR(MSR_IA32_VMX_CR4_FIXED0, X86_TRAP_GP, NO_PRE_COND, VER1_0), - DEF_READ_MSR(MSR_IA32_VMX_CR4_FIXED0, NO_EXCP, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(MSR_IA32_VMX_CR4_FIXED0, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), + DEF_READ_MSR(MSR_IA32_VMX_CR4_FIXED0, NO_EXCP, NO_PRE_COND, VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_VMX_CR4_FIXED0, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), DEF_READ_MSR(MSR_IA32_VMX_CR4_FIXED1, X86_TRAP_GP, NO_PRE_COND, VER1_0), - DEF_READ_MSR(MSR_IA32_VMX_CR4_FIXED1, NO_EXCP, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(MSR_IA32_VMX_CR4_FIXED1, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), + DEF_READ_MSR(MSR_IA32_VMX_CR4_FIXED1, NO_EXCP, NO_PRE_COND, VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_VMX_CR4_FIXED1, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), DEF_READ_MSR(MSR_IA32_VMX_VMCS_ENUM, X86_TRAP_GP, NO_PRE_COND, VER1_0), - DEF_READ_MSR(MSR_IA32_VMX_VMCS_ENUM, X86_TRAP_VE, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(MSR_IA32_VMX_VMCS_ENUM, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), + DEF_READ_MSR(MSR_IA32_VMX_VMCS_ENUM, X86_TRAP_VE, NO_PRE_COND, VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_VMX_VMCS_ENUM, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), DEF_READ_MSR(MSR_IA32_VMX_PROCBASED_CTLS2, X86_TRAP_GP, NO_PRE_COND, VER1_0), - DEF_READ_MSR(MSR_IA32_VMX_PROCBASED_CTLS2, NO_EXCP, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(MSR_IA32_VMX_PROCBASED_CTLS2, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), + DEF_READ_MSR(MSR_IA32_VMX_PROCBASED_CTLS2, NO_EXCP, NO_PRE_COND, VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_VMX_PROCBASED_CTLS2, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), DEF_READ_MSR(MSR_IA32_VMX_EPT_VPID_CAP, X86_TRAP_GP, NO_PRE_COND, VER1_0), - DEF_READ_MSR(MSR_IA32_VMX_EPT_VPID_CAP, NO_EXCP, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(MSR_IA32_VMX_EPT_VPID_CAP, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), + DEF_READ_MSR(MSR_IA32_VMX_EPT_VPID_CAP, NO_EXCP, NO_PRE_COND, VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_VMX_EPT_VPID_CAP, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), DEF_READ_MSR(MSR_IA32_VMX_TRUE_PINBASED_CTLS, X86_TRAP_GP, NO_PRE_COND, VER1_0), - DEF_READ_MSR(MSR_IA32_VMX_TRUE_PINBASED_CTLS, NO_EXCP, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(MSR_IA32_VMX_TRUE_PINBASED_CTLS, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), + DEF_READ_MSR(MSR_IA32_VMX_TRUE_PINBASED_CTLS, NO_EXCP, NO_PRE_COND, VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_VMX_TRUE_PINBASED_CTLS, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), DEF_READ_MSR(MSR_IA32_VMX_TRUE_PROCBASED_CTLS, X86_TRAP_GP, NO_PRE_COND, VER1_0), - DEF_READ_MSR(MSR_IA32_VMX_TRUE_PROCBASED_CTLS, NO_EXCP, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(MSR_IA32_VMX_TRUE_PROCBASED_CTLS, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), + DEF_READ_MSR(MSR_IA32_VMX_TRUE_PROCBASED_CTLS, NO_EXCP, NO_PRE_COND, VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_VMX_TRUE_PROCBASED_CTLS, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), DEF_READ_MSR(MSR_IA32_VMX_TRUE_EXIT_CTLS, X86_TRAP_GP, NO_PRE_COND, VER1_0), - DEF_READ_MSR(MSR_IA32_VMX_TRUE_EXIT_CTLS, NO_EXCP, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(MSR_IA32_VMX_TRUE_EXIT_CTLS, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), + DEF_READ_MSR(MSR_IA32_VMX_TRUE_EXIT_CTLS, NO_EXCP, NO_PRE_COND, VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_VMX_TRUE_EXIT_CTLS, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), DEF_READ_MSR(MSR_IA32_VMX_TRUE_ENTRY_CTLS, X86_TRAP_GP, NO_PRE_COND, VER1_0), - DEF_READ_MSR(MSR_IA32_VMX_TRUE_ENTRY_CTLS, NO_EXCP, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(MSR_IA32_VMX_TRUE_ENTRY_CTLS, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), + DEF_READ_MSR(MSR_IA32_VMX_TRUE_ENTRY_CTLS, NO_EXCP, NO_PRE_COND, VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_VMX_TRUE_ENTRY_CTLS, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), DEF_READ_MSR(MSR_IA32_VMX_VMFUNC, X86_TRAP_GP, NO_PRE_COND, VER1_0), - DEF_READ_MSR(MSR_IA32_VMX_VMFUNC, NO_EXCP, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(MSR_IA32_VMX_VMFUNC, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), + DEF_READ_MSR(MSR_IA32_VMX_VMFUNC, NO_EXCP, NO_PRE_COND, VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_VMX_VMFUNC, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), DEF_READ_MSR(MSR_IA32_VMX_PROCBASED_CTLS3, X86_TRAP_GP, NO_PRE_COND, VER1_0), - DEF_READ_MSR(MSR_IA32_VMX_PROCBASED_CTLS3, NO_EXCP, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(MSR_IA32_VMX_PROCBASED_CTLS3, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_READ_MSR_SIZE(MSR_IA32_PMC0, NO_EXCP, pre_perfmon, 0x8, VER1_0 | VER1_5), - DEF_WRITE_MSR_SIZE(MSR_IA32_PMC0, NO_EXCP, pre_perfmon, 0x8, VER1_0 | VER1_5), - DEF_READ_MSR(IA32_SGX_SVN_STATUS, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_WRITE_MSR(IA32_SGX_SVN_STATUS, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_RTIT_OUTPUT_BASE, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_RTIT_OUTPUT_BASE, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_RTIT_OUTPUT_MASK, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_RTIT_OUTPUT_MASK, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_RTIT_CTL, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_RTIT_CTL, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_RTIT_STATUS, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_RTIT_STATUS, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_RTIT_CR3_MATCH, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_RTIT_CR3_MATCH, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_RTIT_ADDR0_A, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_RTIT_ADDR0_A, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_RTIT_ADDR0_B, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_RTIT_ADDR0_B, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_RTIT_ADDR1_A, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_RTIT_ADDR1_A, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_RTIT_ADDR1_B, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_RTIT_ADDR1_B, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_RTIT_ADDR2_A, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_RTIT_ADDR2_A, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_RTIT_ADDR2_B, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_RTIT_ADDR2_B, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_RTIT_ADDR3_A, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_RTIT_ADDR3_A, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_RTIT_ADDR3_B, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_RTIT_ADDR3_B, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_DS_AREA, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_DS_AREA, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_U_CET, NO_EXCP, pre_xfam_12_11, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_U_CET, NO_EXCP, pre_xfam_12_11, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_S_CET, NO_EXCP, pre_xfam_12_11, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_S_CET, NO_EXCP, pre_xfam_12_11, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_PL0_SSP, NO_EXCP, pre_xfam_12_11, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_PL0_SSP, NO_EXCP, pre_xfam_12_11, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_PL1_SSP, NO_EXCP, pre_xfam_12_11, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_PL1_SSP, NO_EXCP, pre_xfam_12_11, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_PL2_SSP, NO_EXCP, pre_xfam_12_11, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_PL2_SSP, NO_EXCP, pre_xfam_12_11, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_PL3_SSP, NO_EXCP, pre_xfam_12_11, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_PL3_SSP, NO_EXCP, pre_xfam_12_11, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_INT_SSP_TAB, NO_EXCP, pre_xfam_12_11, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_INT_SSP_TAB, NO_EXCP, pre_xfam_12_11, VER1_0 | VER1_5), + DEF_READ_MSR(MSR_IA32_VMX_PROCBASED_CTLS3, NO_EXCP, NO_PRE_COND, VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_VMX_PROCBASED_CTLS3, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR_SIZE(MSR_IA32_PMC0, NO_EXCP, pre_perfmon, 0x8, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR_SIZE(MSR_IA32_PMC0, NO_EXCP, pre_perfmon, 0x8, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(IA32_SGX_SVN_STATUS, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(IA32_SGX_SVN_STATUS, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + + DEF_READ_MSR(IA32_SE_SVN_EXPAN, X86_TRAP_VE, NO_PRE_COND, VER1_5 | VER2_0), + DEF_WRITE_MSR(IA32_SE_SVN_EXPAN, X86_TRAP_VE, NO_PRE_COND, VER1_5 | VER2_0), + + DEF_READ_MSR(MSR_IA32_RTIT_OUTPUT_BASE, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_RTIT_OUTPUT_BASE, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_RTIT_OUTPUT_MASK, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_RTIT_OUTPUT_MASK, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_RTIT_CTL, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_RTIT_CTL, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_RTIT_STATUS, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_RTIT_STATUS, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_RTIT_CR3_MATCH, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_RTIT_CR3_MATCH, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_RTIT_ADDR0_A, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_RTIT_ADDR0_A, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_RTIT_ADDR0_B, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_RTIT_ADDR0_B, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_RTIT_ADDR1_A, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_RTIT_ADDR1_A, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_RTIT_ADDR1_B, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_RTIT_ADDR1_B, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_RTIT_ADDR2_A, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_RTIT_ADDR2_A, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_RTIT_ADDR2_B, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_RTIT_ADDR2_B, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_RTIT_ADDR3_A, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_RTIT_ADDR3_A, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_RTIT_ADDR3_B, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_RTIT_ADDR3_B, NO_EXCP, pre_xfam_8, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_DS_AREA, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_DS_AREA, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_U_CET, NO_EXCP, pre_xfam_12_11, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_U_CET, NO_EXCP, pre_xfam_12_11, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_S_CET, NO_EXCP, pre_xfam_12_11, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_S_CET, NO_EXCP, pre_xfam_12_11, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_PL0_SSP, NO_EXCP, pre_xfam_12_11, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_PL0_SSP, NO_EXCP, pre_xfam_12_11, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_PL1_SSP, NO_EXCP, pre_xfam_12_11, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_PL1_SSP, NO_EXCP, pre_xfam_12_11, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_PL2_SSP, NO_EXCP, pre_xfam_12_11, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_PL2_SSP, NO_EXCP, pre_xfam_12_11, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_PL3_SSP, NO_EXCP, pre_xfam_12_11, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_PL3_SSP, NO_EXCP, pre_xfam_12_11, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_INT_SSP_TAB, NO_EXCP, pre_xfam_12_11, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_INT_SSP_TAB, NO_EXCP, pre_xfam_12_11, VER1_0 | VER1_5 | VER2_0), DEF_READ_MSR(MSR_IA32_TSC_DEADLINE, X86_TRAP_VE, pre_0x1_ecx24, VER1_5), DEF_WRITE_MSR(MSR_IA32_TSC_DEADLINE, X86_TRAP_VE, pre_0x1_ecx24, VER1_5), - DEF_READ_MSR(IA32_PKRS, NO_EXCP, pre_pks, VER1_0 | VER1_5), - DEF_WRITE_MSR(IA32_PKRS, NO_EXCP, pre_pks, VER1_0 | VER1_5), - DEF_READ_MSR_SIZE(RESERVED_XAPIC_0X0800, X86_TRAP_GP, NO_PRE_COND, 0x2, VER1_0 | VER1_5), - DEF_WRITE_MSR_SIZE(RESERVED_XAPIC_0X0800, X86_TRAP_GP, NO_PRE_COND, 0x2, VER1_0 | VER1_5), - DEF_READ_MSR_SIZE(RESERVED_XAPIC_0X0804, X86_TRAP_GP, NO_PRE_COND, 0x4, VER1_0 | VER1_5), - DEF_WRITE_MSR_SIZE(RESERVED_XAPIC_0X0804, X86_TRAP_GP, NO_PRE_COND, 0x4, VER1_0 | VER1_5), - DEF_READ_MSR(IA32_X2APIC_TPR, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_WRITE_MSR(IA32_X2APIC_TPR, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), -// DEF_READ_MSR(RESERVED_XAPIC_0X0809, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), -// DEF_WRITE_MSR(RESERVED_XAPIC_0X0809, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_READ_MSR(IA32_X2APIC_PPR, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), + /* according to MSR Index & Name, Ihis is a Guest behavior. */ + DEF_READ_MSR(MSR_IA32_TSC_DEADLINE, NO_EXCP, NO_PRE_COND, VER2_0), + DEF_WRITE_MSR(MSR_IA32_TSC_DEADLINE, NO_EXCP, NO_PRE_COND, VER2_0), + DEF_READ_MSR(IA32_PKRS, NO_EXCP, pre_pks, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(IA32_PKRS, NO_EXCP, pre_pks, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR_SIZE(RESERVED_XAPIC_0X0800, X86_TRAP_GP, NO_PRE_COND, 0x2, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR_SIZE(RESERVED_XAPIC_0X0800, X86_TRAP_GP, NO_PRE_COND, 0x2, VER1_0 | VER1_5 | VER2_0), + /* according to MSR Index & Name, Ihis is a Guest behavior. */ + DEF_READ_MSR(IA32_X2APIC_APICID, NO_EXCP, NO_PRE_COND, VER1_5 | VER2_0), + DEF_WRITE_MSR(IA32_X2APIC_APICID, X86_TRAP_VE, NO_PRE_COND, VER1_5 | VER2_0), + /* according to MSR Index & Name, Ihis is a Guest behavior. */ + DEF_READ_MSR(IA32_X2APIC_VERSION, NO_EXCP, NO_PRE_COND, VER1_5 | VER2_0), + DEF_WRITE_MSR(IA32_X2APIC_VERSION, X86_TRAP_VE, NO_PRE_COND, VER1_5 | VER2_0), + DEF_READ_MSR_SIZE(RESERVED_XAPIC_0X0804, X86_TRAP_GP, NO_PRE_COND, 0x4, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR_SIZE(RESERVED_XAPIC_0X0804, X86_TRAP_GP, NO_PRE_COND, 0x4, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(IA32_X2APIC_TPR, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(IA32_X2APIC_TPR, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), +// DEF_READ_MSR(RESERVED_XAPIC_0X0809, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), +// DEF_WRITE_MSR(RESERVED_XAPIC_0X0809, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(IA32_X2APIC_PPR, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), DEF_WRITE_MSR(IA32_X2APIC_PPR, NO_EXCP, NO_PRE_COND, VER1_0), - DEF_WRITE_MSR(IA32_X2APIC_PPR, X86_TRAP_GP, NO_PRE_COND, VER1_5), - DEF_READ_MSR(IA32_X2APIC_EOI, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_WRITE_MSR(IA32_X2APIC_EOI, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), -// DEF_READ_MSR(RESERVED_XAPIC_0X080C, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), -// DEF_WRITE_MSR(RESERVED_XAPIC_0X080C, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), -// DEF_READ_MSR(RESERVED_XAPIC_0X080E, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), -// DEF_WRITE_MSR(RESERVED_XAPIC_0X080E, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_READ_MSR_SIZE(IA32_X2APIC_ISRX, NO_EXCP, NO_PRE_COND, 0x8, VER1_0 | VER1_5), + DEF_WRITE_MSR(IA32_X2APIC_PPR, X86_TRAP_GP, NO_PRE_COND, VER1_5 | VER2_0), + DEF_READ_MSR(IA32_X2APIC_EOI, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(IA32_X2APIC_EOI, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), +// DEF_READ_MSR(RESERVED_XAPIC_0X080C, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), +// DEF_WRITE_MSR(RESERVED_XAPIC_0X080C, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), +// DEF_READ_MSR(RESERVED_XAPIC_0X080E, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), +// DEF_WRITE_MSR(RESERVED_XAPIC_0X080E, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR_SIZE(IA32_X2APIC_ISRX, NO_EXCP, NO_PRE_COND, 0x8, VER1_0 | VER1_5 | VER2_0), DEF_WRITE_MSR_SIZE(IA32_X2APIC_ISRX, NO_EXCP, NO_PRE_COND, 0x8, VER1_0), - DEF_WRITE_MSR_SIZE(IA32_X2APIC_ISRX, X86_TRAP_GP, NO_PRE_COND, 0x8, VER1_5), - DEF_READ_MSR_SIZE(IA32_X2APIC_TMRX, NO_EXCP, NO_PRE_COND, 0x8, VER1_0 | VER1_5), + DEF_WRITE_MSR_SIZE(IA32_X2APIC_ISRX, X86_TRAP_GP, NO_PRE_COND, 0x8, VER1_5 | VER2_0), + DEF_READ_MSR_SIZE(IA32_X2APIC_TMRX, NO_EXCP, NO_PRE_COND, 0x8, VER1_0 | VER1_5 | VER2_0), DEF_WRITE_MSR_SIZE(IA32_X2APIC_TMRX, NO_EXCP, NO_PRE_COND, 0x8, VER1_0), - DEF_WRITE_MSR_SIZE(IA32_X2APIC_TMRX, X86_TRAP_GP, NO_PRE_COND, 0x8, VER1_5), - DEF_READ_MSR_SIZE(IA32_X2APIC_IRRX, NO_EXCP, NO_PRE_COND, 0x8, VER1_0 | VER1_5), + DEF_WRITE_MSR_SIZE(IA32_X2APIC_TMRX, X86_TRAP_GP, NO_PRE_COND, 0x8, VER1_5 | VER2_0), + DEF_READ_MSR_SIZE(IA32_X2APIC_IRRX, NO_EXCP, NO_PRE_COND, 0x8, VER1_0 | VER1_5 | VER2_0), DEF_WRITE_MSR_SIZE(IA32_X2APIC_IRRX, NO_EXCP, NO_PRE_COND, 0x8, VER1_0), - DEF_WRITE_MSR_SIZE(IA32_X2APIC_IRRX, X86_TRAP_GP, NO_PRE_COND, 0x8, VER1_5), - DEF_READ_MSR_SIZE(RESERVED_XAPIC_0X0829, X86_TRAP_GP, NO_PRE_COND, 0x6, VER1_0 | VER1_5), - DEF_WRITE_MSR_SIZE(RESERVED_XAPIC_0X0829, X86_TRAP_GP, NO_PRE_COND, 0x6, VER1_0 | VER1_5), - DEF_READ_MSR(RESERVED_XAPIC_0X0831, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_WRITE_MSR(RESERVED_XAPIC_0X0831, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_READ_MSR(IA32_X2APIC_SELF_IPI, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), - /* DEF_WRITE_MSR(IA32_X2APIC_SELF_IPI, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), + DEF_WRITE_MSR_SIZE(IA32_X2APIC_IRRX, X86_TRAP_GP, NO_PRE_COND, 0x8, VER1_5 | VER2_0), + DEF_READ_MSR_SIZE(RESERVED_XAPIC_0X0829, X86_TRAP_GP, NO_PRE_COND, 0x6, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR_SIZE(RESERVED_XAPIC_0X0829, X86_TRAP_GP, NO_PRE_COND, 0x6, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(RESERVED_XAPIC_0X0831, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(RESERVED_XAPIC_0X0831, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(IA32_X2APIC_SELF_IPI, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + /* DEF_WRITE_MSR(IA32_X2APIC_SELF_IPI, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), * this case will crash the guestTD. */ - DEF_READ_MSR_SIZE(RESERVED_XAPIC_0X0840, X86_TRAP_GP, NO_PRE_COND, 0x40, VER1_0 | VER1_5), - DEF_WRITE_MSR_SIZE(RESERVED_XAPIC_0X0840, X86_TRAP_GP, NO_PRE_COND, 0x40, VER1_0 | VER1_5), - DEF_READ_MSR_SIZE(RESERVED_XAPIC_0X0880, X86_TRAP_GP, NO_PRE_COND, 0x40, VER1_0 | VER1_5), - DEF_WRITE_MSR_SIZE(RESERVED_XAPIC_0X0880, X86_TRAP_GP, NO_PRE_COND, 0x40, VER1_0 | VER1_5), - DEF_READ_MSR_SIZE(RESERVED_XAPIC_0X08C0, X86_TRAP_GP, NO_PRE_COND, 0x40, VER1_0 | VER1_5), - DEF_WRITE_MSR_SIZE(RESERVED_XAPIC_0X08C0, X86_TRAP_GP, NO_PRE_COND, 0x40, VER1_0 | VER1_5), - DEF_READ_MSR(IA32_TME_CAPABILITIES, X86_TRAP_VE, pre_0x7_ecx13, VER1_0 | VER1_5), - DEF_WRITE_MSR(IA32_TME_CAPABILITIES, X86_TRAP_VE, pre_0x7_ecx13, VER1_0 | VER1_5), - DEF_READ_MSR(IA32_TME_ACTIVATE, X86_TRAP_VE, pre_0x7_ecx13, VER1_0 | VER1_5), - DEF_WRITE_MSR(IA32_TME_ACTIVATE, X86_TRAP_VE, pre_0x7_ecx13, VER1_0 | VER1_5), - DEF_READ_MSR(IA32_TME_EXCLUDE_MASK, X86_TRAP_VE, pre_0x7_ecx13, VER1_0 | VER1_5), - DEF_WRITE_MSR(IA32_TME_EXCLUDE_MASK, X86_TRAP_VE, pre_0x7_ecx13, VER1_0 | VER1_5), - DEF_READ_MSR(IA32_TME_EXCLUDE_BASE, X86_TRAP_VE, pre_0x7_ecx13, VER1_0 | VER1_5), - DEF_WRITE_MSR(IA32_TME_EXCLUDE_BASE, X86_TRAP_VE, pre_0x7_ecx13, VER1_0 | VER1_5), - DEF_READ_MSR(IA32_UINT_RR, NO_EXCP, pre_xfam_14, VER1_0 | VER1_5), - DEF_WRITE_MSR(IA32_UINT_RR, NO_EXCP, pre_xfam_14, VER1_0 | VER1_5), - DEF_READ_MSR(IA32_UINT_HANDLER, NO_EXCP, pre_xfam_14, VER1_0 | VER1_5), - DEF_WRITE_MSR(IA32_UINT_HANDLER, NO_EXCP, pre_xfam_14, VER1_0 | VER1_5), - DEF_READ_MSR(IA32_UINT_STACKADJUST, NO_EXCP, pre_xfam_14, VER1_0 | VER1_5), - DEF_WRITE_MSR(IA32_UINT_STACKADJUST, NO_EXCP, pre_xfam_14, VER1_0 | VER1_5), - DEF_READ_MSR(IA32_UINT_MISC, NO_EXCP, pre_xfam_14, VER1_0 | VER1_5), - DEF_WRITE_MSR(IA32_UINT_MISC, NO_EXCP, pre_xfam_14, VER1_0 | VER1_5), - DEF_READ_MSR(IA32_UINT_PD, NO_EXCP, pre_xfam_14, VER1_0 | VER1_5), - DEF_WRITE_MSR(IA32_UINT_PD, NO_EXCP, pre_xfam_14, VER1_0 | VER1_5), - DEF_READ_MSR(IA32_UINT_TT, NO_EXCP, pre_xfam_14, VER1_0 | VER1_5), - DEF_WRITE_MSR(IA32_UINT_TT, NO_EXCP, pre_xfam_14, VER1_0 | VER1_5), - DEF_READ_MSR(IA32_DEBUG_INTERFACE, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_WRITE_MSR(IA32_DEBUG_INTERFACE, X86_TRAP_VE, NO_PRE_COND, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_BNDCFGS, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_BNDCFGS, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_PASID, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_IA32_PASID, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_IA32_XSS, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), - - DEF_READ_MSR_SIZE(MSR_ARCH_LBR_INFO_0, NO_EXCP, pre_xfam_15, 0x100, VER1_0 | VER1_5), - DEF_WRITE_MSR_SIZE(MSR_ARCH_LBR_INFO_0, NO_EXCP, pre_xfam_15, 0x100, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_ARCH_LBR_CTL, NO_EXCP, pre_xfam_15, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_ARCH_LBR_CTL, NO_EXCP, pre_xfam_15, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_ARCH_LBR_DEPTH, NO_EXCP, pre_xfam_15, VER1_0 | VER1_5), - DEF_WRITE_MSR(MSR_ARCH_LBR_DEPTH, NO_EXCP, pre_xfam_15, VER1_0 | VER1_5), - DEF_READ_MSR_SIZE(MSR_ARCH_LBR_FROM_0, NO_EXCP, pre_xfam_15, 0x100, VER1_0 | VER1_5), - DEF_WRITE_MSR_SIZE(MSR_ARCH_LBR_FROM_0, NO_EXCP, pre_xfam_15, 0x100, VER1_0 | VER1_5), - DEF_READ_MSR_SIZE(MSR_ARCH_LBR_TO_0, NO_EXCP, pre_xfam_15, 0x100, VER1_0 | VER1_5), - DEF_WRITE_MSR_SIZE(MSR_ARCH_LBR_TO_0, NO_EXCP, pre_xfam_15, 0x100, VER1_0 | VER1_5), + DEF_READ_MSR_SIZE(RESERVED_XAPIC_0X0840, X86_TRAP_GP, NO_PRE_COND, 0x40, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR_SIZE(RESERVED_XAPIC_0X0840, X86_TRAP_GP, NO_PRE_COND, 0x40, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR_SIZE(RESERVED_XAPIC_0X0880, X86_TRAP_GP, NO_PRE_COND, 0x40, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR_SIZE(RESERVED_XAPIC_0X0880, X86_TRAP_GP, NO_PRE_COND, 0x40, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR_SIZE(RESERVED_XAPIC_0X08C0, X86_TRAP_GP, NO_PRE_COND, 0x40, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR_SIZE(RESERVED_XAPIC_0X08C0, X86_TRAP_GP, NO_PRE_COND, 0x40, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(IA32_TME_CAPABILITIES, X86_TRAP_VE, pre_0x7_ecx13, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(IA32_TME_CAPABILITIES, X86_TRAP_VE, pre_0x7_ecx13, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(IA32_TME_ACTIVATE, X86_TRAP_VE, pre_0x7_ecx13, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(IA32_TME_ACTIVATE, X86_TRAP_VE, pre_0x7_ecx13, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(IA32_TME_EXCLUDE_MASK, X86_TRAP_VE, pre_0x7_ecx13, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(IA32_TME_EXCLUDE_MASK, X86_TRAP_VE, pre_0x7_ecx13, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(IA32_TME_EXCLUDE_BASE, X86_TRAP_VE, pre_0x7_ecx13, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(IA32_TME_EXCLUDE_BASE, X86_TRAP_VE, pre_0x7_ecx13, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(IA32_UINT_RR, NO_EXCP, pre_xfam_14, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(IA32_UINT_RR, NO_EXCP, pre_xfam_14, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(IA32_UINT_HANDLER, NO_EXCP, pre_xfam_14, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(IA32_UINT_HANDLER, NO_EXCP, pre_xfam_14, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(IA32_UINT_STACKADJUST, NO_EXCP, pre_xfam_14, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(IA32_UINT_STACKADJUST, NO_EXCP, pre_xfam_14, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(IA32_UINT_MISC, NO_EXCP, pre_xfam_14, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(IA32_UINT_MISC, NO_EXCP, pre_xfam_14, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(IA32_UINT_PD, NO_EXCP, pre_xfam_14, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(IA32_UINT_PD, NO_EXCP, pre_xfam_14, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(IA32_UINT_TT, NO_EXCP, pre_xfam_14, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(IA32_UINT_TT, NO_EXCP, pre_xfam_14, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(IA32_DEBUG_INTERFACE, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(IA32_DEBUG_INTERFACE, X86_TRAP_VE, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_BNDCFGS, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_BNDCFGS, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_PASID, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_IA32_PASID, X86_TRAP_GP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_IA32_XSS, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + + DEF_READ_MSR_SIZE(MSR_ARCH_LBR_INFO_0, NO_EXCP, pre_xfam_15, 0x100, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR_SIZE(MSR_ARCH_LBR_INFO_0, NO_EXCP, pre_xfam_15, 0x100, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_ARCH_LBR_CTL, NO_EXCP, pre_xfam_15, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_ARCH_LBR_CTL, NO_EXCP, pre_xfam_15, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_ARCH_LBR_DEPTH, NO_EXCP, pre_xfam_15, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR(MSR_ARCH_LBR_DEPTH, NO_EXCP, pre_xfam_15, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR_SIZE(MSR_ARCH_LBR_FROM_0, NO_EXCP, pre_xfam_15, 0x100, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR_SIZE(MSR_ARCH_LBR_FROM_0, NO_EXCP, pre_xfam_15, 0x100, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR_SIZE(MSR_ARCH_LBR_TO_0, NO_EXCP, pre_xfam_15, 0x100, VER1_0 | VER1_5 | VER2_0), + DEF_WRITE_MSR_SIZE(MSR_ARCH_LBR_TO_0, NO_EXCP, pre_xfam_15, 0x100, VER1_0 | VER1_5 | VER2_0), DEF_READ_MSR(IA32_UARCH_MISC_CTL, NO_EXCP, NO_PRE_COND, VER1_5), DEF_WRITE_MSR(IA32_UARCH_MISC_CTL, NO_EXCP, NO_PRE_COND, VER1_5), /* cases below here in WRMSR will crash the guest TD. */ - DEF_READ_MSR(MSR_EFER, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_STAR, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_LSTAR, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_SYSCALL_MASK, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_FS_BASE, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_GS_BASE, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_KERNEL_GS_BASE, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), - DEF_READ_MSR(MSR_TSC_AUX, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5), - - DEF_READ_MSR(MSR_IA32_PLATFORM_ID, X86_TRAP_VE, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(MSR_IA32_PLATFORM_ID, X86_TRAP_VE, NO_PRE_COND, VER1_5), - /* according to MSR Index & Name, Ihis is a Guest behavior. */ - DEF_READ_MSR(MSR_IA32_APICBASE, NO_EXCP, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(MSR_IA32_APICBASE, X86_TRAP_VE, NO_PRE_COND, VER1_5), - DEF_READ_MSR(MSR_TEST_CTRL, X86_TRAP_VE, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(MSR_TEST_CTRL, X86_TRAP_VE, NO_PRE_COND, VER1_5), - DEF_READ_MSR(MSR_IA32_TSC_ADJUST, X86_TRAP_VE, NO_PRE_COND, VER1_5), - DEF_WRITE_MSR(MSR_IA32_TSC_ADJUST, X86_TRAP_VE, NO_PRE_COND, VER1_5), + DEF_READ_MSR(MSR_EFER, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_STAR, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_LSTAR, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_CSTAR, X86_TRAP_VE, NO_PRE_COND, VER1_5 | VER2_0), + DEF_READ_MSR(MSR_SYSCALL_MASK, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_FS_BASE, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_GS_BASE, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_KERNEL_GS_BASE, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), + DEF_READ_MSR(MSR_TSC_AUX, NO_EXCP, NO_PRE_COND, VER1_0 | VER1_5 | VER2_0), }; diff --git a/tdx-compliance/tdx-compliance.c b/tdx-compliance/tdx-compliance.c index dd658bd..0627592 100644 --- a/tdx-compliance/tdx-compliance.c +++ b/tdx-compliance/tdx-compliance.c @@ -84,8 +84,10 @@ void parse_version(void) spec_version = VER1_0; else if (strstr(version_name, "1.5")) spec_version = VER1_5; + else if (strstr(version_name, "2.0")) + spec_version = VER2_0; else - spec_version = (VER1_0 | VER1_5); + spec_version = (VER1_0 | VER1_5 | VER2_0); } static char* case_version(int ret) { @@ -94,6 +96,8 @@ static char* case_version(int ret) { return "1.0"; case VER1_5: return "1.5"; + case VER2_0: + return "2.0"; } return ""; diff --git a/tdx-compliance/tdx-compliance.h b/tdx-compliance/tdx-compliance.h index 0e155de..100b69c 100644 --- a/tdx-compliance/tdx-compliance.h +++ b/tdx-compliance/tdx-compliance.h @@ -23,6 +23,7 @@ #define VER1_0 1 #define VER1_5 2 +#define VER2_0 4 struct cpuid_reg { u32 val; diff --git a/tdx-compliance/testallcase.sh b/tdx-compliance/testallcase.sh index 9522720..14af912 100644 --- a/tdx-compliance/testallcase.sh +++ b/tdx-compliance/testallcase.sh @@ -1,6 +1,6 @@ #!/bin/bash case=("msr" "cr" "cpuid" "all") -ver=("1.0" "1.5" "") +ver=("1.0" "1.5" "2.0") # store test results to a specified folder script_dir=$(dirname "$0")