diff --git a/BM/tools/pcie/pcie_check.c b/BM/tools/pcie/pcie_check.c
index 51dad29..a56eae9 100644
--- a/BM/tools/pcie/pcie_check.c
+++ b/BM/tools/pcie/pcie_check.c
@@ -178,15 +178,19 @@ int find_bar(void)
 	}
 	fclose(maps);
 
+	/*
+	 * In CXL QEMU environment, MMIO base address is incorrect,
+	 * so will not use dmesg check way to detect the MMIO base
+	 * address, will use mcfg way instead.
+	 * if (BASE_ADDR == 0) {
+	 * BASE_ADDR = find_base_from_dmesg();
+	 * }
+	 */
 	if (BASE_ADDR == 0) {
-		//printf("Check kconfig CONFIG_IO_STRICT_DEVMEM or v6.9 or newer kernel!\n");
-		BASE_ADDR = find_base_from_dmesg();
+		BASE_ADDR = find_base_from_mcfg();
 		if (BASE_ADDR == 0) {
-			BASE_ADDR = find_base_from_mcfg();
-			if (BASE_ADDR == 0) {
-				printf("No MMIO in dmesg, /proc/iomem and mcfg, check acpidump.\n");
-				exit(2);
-			}
+			printf("No MMIO in dmesg, /proc/iomem and mcfg, check acpidump.\n");
+			exit(2);
 		}
 	}
 #endif
@@ -411,8 +415,9 @@ int recognize_pcie(u32 *ptrdata)
 	/* 0x34/4 is capability pointer in PCI */
 	nextpoint = (u8)(*(ptrdata + PCI_CAP_START / 4));
 
+	/* If 0x34 next point is 0, will continue and code is 3 */
 	if (nextpoint == 0)
-		return 0;
+		return 3;
 
 	ptrsearch = ptrdata + nextpoint / 4;
 	while (1) {
@@ -511,7 +516,7 @@ int scan_pci(void)
 	u32 bus, dev, fun;
 	// Must 32bit for data check!
 	u32 *ptrdata = malloc(sizeof(unsigned long) * 4096);
-	int fd;
+	int fd, ret;
 
 	fd = open("/dev/mem", O_RDWR);
 
@@ -537,12 +542,17 @@ int scan_pci(void)
 				}
 
 				if ((*ptrdata != ptr_content) && (*ptrdata != 0)) {
-					if (recognize_pcie(ptrdata) == 2) {
-						printf("%02x:%02x.%x debug:pcie_check a %x %x %x\n",
-						       bus, dev, fun, bus, dev, fun);
+					ret = recognize_pcie(ptrdata);
+					if (ret == 2) {
+						printf("[ERROR] PCI %02x:%02x.%x offset 0xff,",
+						       bus, dev, fun);
+						printf("please debug:pcie_check a %x %x %x\n",
+						       bus, dev, fun);
 						munmap(ptrdata, LEN_SIZE);
 						close(fd);
 						return 2;
+					} else if (ret == 3) {
+						continue;
 					}
 
 					if (is_pcie == 0)
@@ -587,6 +597,9 @@ int specific_pcie_cap(u32 *ptrdata, u16 cap)
 		 *	PCI_CAP_START, ptrdata, *ptrdata);
 		 */
 		return 2;
+	/* If 0x34 next point is 0, will continue and code is 3 */
+	} else if (nextpoint == 0) {
+		return 3;
 	}
 
 	cap_value = (u16)(*(ptrdata + next / 4));
@@ -790,11 +803,13 @@ int find_pcie_reg(u16 cap, u32 offset, u32 size)
 						check_pcie_register(cap, offset, size);
 					} else if (result == 2) {
 						/* This PCIe ended with unknown CAP ff, mark it */
-						printf("%02x:%02x.%x debug:pcie_check a %x %x %x\n",
-						       bus, dev, func, bus, dev, func);
-						munmap(ptrdata, LEN_SIZE);
-						close(fd);
-						return 2;
+						printf("[WARN] PCIe %02x:%02x.%x error PCI CAP ff,",
+						       bus, dev, func);
+						printf("please debug:pcie_check a %x %x %x\n",
+						       bus, dev, func);
+						continue;
+					} else if (result == 3) {
+						continue;
 					}
 				}
 				munmap(ptrdata, LEN_SIZE);
@@ -964,11 +979,13 @@ int find_pci_reg(u16 cap, u32 offset, u32 size)
 						check_pci_register((u8)cap, (u8)offset, size);
 					} else if (result == 1) {
 						/* This PCI ended with unknown CAP ff so mark it */
-						printf("%02x:%02x.%x debug:pcie_check a %x %x %x\n",
-						       bus, dev, func, bus, dev, func);
-						munmap(ptrdata, LEN_SIZE);
-						close(fd);
-						return 2;
+						printf("[WARN] PCI %02x:%02x.%x unknown CAP ff,",
+						       bus, dev, func);
+						printf("please debug:pcie_check a %x %x %x\n",
+						       bus, dev, func);
+						continue;
+					} else if (result == 3) {
+						continue;
 					}
 				}
 				munmap(ptrdata, LEN_SIZE);