From 764a5437c27462422b42a6cffce7bcbaaf2a2846 Mon Sep 17 00:00:00 2001 From: Pengfei Xu Date: Mon, 9 Sep 2024 15:55:53 +0800 Subject: [PATCH 1/3] pcie_check: will continue instead of return if PCI cap is 0xff Will continue instead of return if PCI cap is 0xff. Add more description info for pcie check. Reported-by: Yi Lai Signed-off-by: Pengfei Xu --- BM/tools/pcie/pcie_check.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/BM/tools/pcie/pcie_check.c b/BM/tools/pcie/pcie_check.c index 51dad29..1fd0ccc 100644 --- a/BM/tools/pcie/pcie_check.c +++ b/BM/tools/pcie/pcie_check.c @@ -538,8 +538,10 @@ int scan_pci(void) if ((*ptrdata != ptr_content) && (*ptrdata != 0)) { if (recognize_pcie(ptrdata) == 2) { - printf("%02x:%02x.%x debug:pcie_check a %x %x %x\n", - bus, dev, fun, bus, dev, fun); + printf("[ERROR] PCI %02x:%02x.%x offset 0xff,", + bus, dev, fun); + printf("please debug:pcie_check a %x %x %x\n", + bus, dev, fun); munmap(ptrdata, LEN_SIZE); close(fd); return 2; @@ -790,11 +792,11 @@ int find_pcie_reg(u16 cap, u32 offset, u32 size) check_pcie_register(cap, offset, size); } else if (result == 2) { /* This PCIe ended with unknown CAP ff, mark it */ - printf("%02x:%02x.%x debug:pcie_check a %x %x %x\n", - bus, dev, func, bus, dev, func); - munmap(ptrdata, LEN_SIZE); - close(fd); - return 2; + printf("[WARN] PCIe %02x:%02x.%x error PCI CAP ff,", + bus, dev, func); + printf("please debug:pcie_check a %x %x %x\n", + bus, dev, func); + continue; } } munmap(ptrdata, LEN_SIZE); @@ -964,11 +966,11 @@ int find_pci_reg(u16 cap, u32 offset, u32 size) check_pci_register((u8)cap, (u8)offset, size); } else if (result == 1) { /* This PCI ended with unknown CAP ff so mark it */ - printf("%02x:%02x.%x debug:pcie_check a %x %x %x\n", - bus, dev, func, bus, dev, func); - munmap(ptrdata, LEN_SIZE); - close(fd); - return 2; + printf("[WARN] PCI %02x:%02x.%x unknown CAP ff,", + bus, dev, func); + printf("please debug:pcie_check a %x %x %x\n", + bus, dev, func); + continue; } } munmap(ptrdata, LEN_SIZE); From b61f59bae85416cec61803990520f541b9bfa254 Mon Sep 17 00:00:00 2001 From: Pengfei Xu Date: Tue, 10 Sep 2024 16:46:06 +0800 Subject: [PATCH 2/3] pcie_check: will not show unavailable PCI or PCIe info in the list Add the judgment that PCI capability is 0, it will not show unavailable PCI or PCIe info in the list. Reported-by: Yi Lai Signed-off-by: Pengfei Xu --- BM/tools/pcie/pcie_check.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/BM/tools/pcie/pcie_check.c b/BM/tools/pcie/pcie_check.c index 1fd0ccc..bf754aa 100644 --- a/BM/tools/pcie/pcie_check.c +++ b/BM/tools/pcie/pcie_check.c @@ -411,8 +411,9 @@ int recognize_pcie(u32 *ptrdata) /* 0x34/4 is capability pointer in PCI */ nextpoint = (u8)(*(ptrdata + PCI_CAP_START / 4)); + /* If 0x34 next point is 0, will continue and code is 3 */ if (nextpoint == 0) - return 0; + return 3; ptrsearch = ptrdata + nextpoint / 4; while (1) { @@ -511,7 +512,7 @@ int scan_pci(void) u32 bus, dev, fun; // Must 32bit for data check! u32 *ptrdata = malloc(sizeof(unsigned long) * 4096); - int fd; + int fd, ret; fd = open("/dev/mem", O_RDWR); @@ -537,7 +538,8 @@ int scan_pci(void) } if ((*ptrdata != ptr_content) && (*ptrdata != 0)) { - if (recognize_pcie(ptrdata) == 2) { + ret = recognize_pcie(ptrdata); + if (ret == 2) { printf("[ERROR] PCI %02x:%02x.%x offset 0xff,", bus, dev, fun); printf("please debug:pcie_check a %x %x %x\n", @@ -545,6 +547,8 @@ int scan_pci(void) munmap(ptrdata, LEN_SIZE); close(fd); return 2; + } else if (ret == 3) { + continue; } if (is_pcie == 0) @@ -589,6 +593,9 @@ int specific_pcie_cap(u32 *ptrdata, u16 cap) * PCI_CAP_START, ptrdata, *ptrdata); */ return 2; + /* If 0x34 next point is 0, will continue and code is 3 */ + } else if (nextpoint == 0) { + return 3; } cap_value = (u16)(*(ptrdata + next / 4)); @@ -797,6 +804,8 @@ int find_pcie_reg(u16 cap, u32 offset, u32 size) printf("please debug:pcie_check a %x %x %x\n", bus, dev, func); continue; + } else if (result == 3) { + continue; } } munmap(ptrdata, LEN_SIZE); @@ -971,6 +980,8 @@ int find_pci_reg(u16 cap, u32 offset, u32 size) printf("please debug:pcie_check a %x %x %x\n", bus, dev, func); continue; + } else if (result == 3) { + continue; } } munmap(ptrdata, LEN_SIZE); From 7b847cd6e795838c050a587ca2c4cbbfbed15b1c Mon Sep 17 00:00:00 2001 From: Pengfei Xu Date: Fri, 13 Sep 2024 15:54:30 +0800 Subject: [PATCH 3/3] pcie_check.c: remove MMIO base address detection by dmesg way Remove MMIO base address detection by dmesg way, because in CXL QEMU environment, dmesg shows incorrect MMIO base address "0xffc00000": " [ 0.000000] efi: Remove mem128: MMIO range=[0xffc00000-0xffffffff] (4MB) from e820 map " And use MCFG way directly and it could detect correct MMIO base address "0xe0000000" for CXL QEMU environment. Signed-off-by: Pengfei Xu --- BM/tools/pcie/pcie_check.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/BM/tools/pcie/pcie_check.c b/BM/tools/pcie/pcie_check.c index bf754aa..a56eae9 100644 --- a/BM/tools/pcie/pcie_check.c +++ b/BM/tools/pcie/pcie_check.c @@ -178,15 +178,19 @@ int find_bar(void) } fclose(maps); + /* + * In CXL QEMU environment, MMIO base address is incorrect, + * so will not use dmesg check way to detect the MMIO base + * address, will use mcfg way instead. + * if (BASE_ADDR == 0) { + * BASE_ADDR = find_base_from_dmesg(); + * } + */ if (BASE_ADDR == 0) { - //printf("Check kconfig CONFIG_IO_STRICT_DEVMEM or v6.9 or newer kernel!\n"); - BASE_ADDR = find_base_from_dmesg(); + BASE_ADDR = find_base_from_mcfg(); if (BASE_ADDR == 0) { - BASE_ADDR = find_base_from_mcfg(); - if (BASE_ADDR == 0) { - printf("No MMIO in dmesg, /proc/iomem and mcfg, check acpidump.\n"); - exit(2); - } + printf("No MMIO in dmesg, /proc/iomem and mcfg, check acpidump.\n"); + exit(2); } } #endif