[LLVM Pulldown] Bump to rev a3557c3abde66c7001f12f6fec7a13885574e55a (#1122)

Author: Garra1980

build_tools/llvm_version.txt

@@ -1 +1 @@
-89e2d58ec8189e77c34e39b1e8c9992315ad682f
+a3557c3abde66c7001f12f6fec7a13885574e55a

build_tools/patches/0001-Add-support-for-VectorAnyINTEL-capability.patch

@@ -64,32 +64,32 @@ index 6b4e3dd60319..987b33c055e9 100644
 +// `allowedRanges` list, the list has two values, start and end of the range (inclusive)
 +class IsVectorOfLengthRangePred<list<int> allowedRanges> :
 +  And<[IsVectorOfNonZeroRankTypePred,
-+       And<[CPred<[{cast<::mlir::VectorType>($_self).getNumElements()
++       And<[CPred<[{::llvm::cast<::mlir::VectorType>($_self).getNumElements()
 +                           >= }]
 +                         # allowedRanges[0]>,
-+                        CPred<[{cast<::mlir::VectorType>($_self).getNumElements()
++                        CPred<[{::llvm::cast<::mlir::VectorType>($_self).getNumElements()
 +                           <= }]
 +                         # allowedRanges[1]>]>]>;
 +
 +// Whether the number of elements of a fixed-length vector is from the given
 +// `allowedRanges` list, the list has two values, start and end of the range (inclusive)
 +class IsFixedVectorOfLengthRangePred<list<int> allowedRanges> :
 +  And<[IsFixedVectorOfAnyRankTypePred,
-+       And<[CPred<[{cast<::mlir::VectorType>($_self).getNumElements()
++       And<[CPred<[{::llvm::cast<::mlir::VectorType>($_self).getNumElements()
 +                           >= }]
 +                         # allowedRanges[0]>,
-+                        CPred<[{cast<::mlir::VectorType>($_self).getNumElements()
++                        CPred<[{::llvm::cast<::mlir::VectorType>($_self).getNumElements()
 +                           <= }]
 +                         # allowedRanges[1]>]>]>;
 +
 +// Whether the number of elements of a scalable vector is from the given
 +// `allowedRanges` list, the list has two values, start and end of the range (inclusive)
 +class IsScalableVectorOfLengthRangePred<list<int> allowedRanges> :
 +  And<[IsVectorTypeWithAnyDimScalablePred,
-+       And<[CPred<[{cast<::mlir::VectorType>($_self).getNumElements()
++       And<[CPred<[{::llvm::cast<::mlir::VectorType>($_self).getNumElements()
 +                           >= }]
 +                         # allowedRanges[0]>,
-+                        CPred<[{cast<::mlir::VectorType>($_self).getNumElements()
++                        CPred<[{::llvm::cast<::mlir::VectorType>($_self).getNumElements()
 +                           <= }]
 +                         # allowedRanges[1]>]>]>;
 +

build_tools/patches/0008-xegpu-temporary-downstream-defintion-changes-and-vec.patch

@@ -1,41 +1,41 @@
-From 6a3b9a4936f774957b6a1cedcae40a355fb9670e Mon Sep 17 00:00:00 2001
+From e2a5c68fb109839d7ef07aa9d7c11119556ad0a7 Mon Sep 17 00:00:00 2001
 From: Garra1980 <[email protected]>
-Date: Wed, 20 Aug 2025 01:20:08 +0200
+Date: Sun, 19 Oct 2025 01:45:36 +0200
 Subject: [PATCH] xegpu temporary downstream defintion changes and vec
 
 ---
- mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td      |  5 +++++
+ mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td      |  6 ++++++
  mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp |  7 ++++++-
  mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp              | 10 ++++++----
- 3 files changed, 17 insertions(+), 5 deletions(-)
+ 3 files changed, 18 insertions(+), 5 deletions(-)
 
 diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
-index eb54d6887681..b849c6b97d9d 100644
+index 426377fcf598..f77aaf0bd02e 100644
 --- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
 +++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
-@@ -329,6 +329,7 @@ def XeGPU_LoadNdOp : XeGPU_Op<"load_nd", [
+@@ -358,6 +358,7 @@ def XeGPU_LoadNdOp : XeGPU_Op<"load_nd", [
                         OptionalAttr<DenseI64ArrayAttr>: $const_offsets,
                         OptionalAttr<UnitAttr>: $packed,
                         OptionalAttr<DenseI64ArrayAttr>: $transpose,
 +                       OptionalAttr<I32Attr>: $transpose_bit_width,
                         OptionalAttr<XeGPU_CacheHintAttr>: $l1_hint,
                         OptionalAttr<XeGPU_CacheHintAttr>: $l2_hint,
                         OptionalAttr<XeGPU_CacheHintAttr>: $l3_hint);
-@@ -1260,5 +1261,9 @@ def XeGPU_MemDescSubviewOp: XeGPU_Op<"mem_desc_subview",
+@@ -1398,4 +1399,9 @@ def XeGPU_StoreMatrixOp: XeGPU_Op<"store_matrix", [MemoryEffects<[MemWrite]>,
    let hasVerifier = 1;
  }
 
 +def XeGPU_CompileHintOp : XeGPU_Op<"compile_hint", []> {
 +  let summary = "prevents the compiler from scheduling.";
 +  let assemblyFormat = [{ attr-dict }];
 +}
-
++
  #endif // MLIR_DIALECT_XEGPU_IR_XEGPUOPS_TD
 diff --git a/mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp b/mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
-index 819c2e5973ff..545f1d77156c 100644
+index e2c7d803e5a5..a55a9a233209 100644
 --- a/mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
 +++ b/mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
-@@ -485,7 +485,9 @@ struct TransferReadLowering : public OpRewritePattern<vector::TransferReadOp> {
+@@ -535,7 +535,9 @@ struct TransferReadLowering : public OpRewritePattern<vector::TransferReadOp> {
      // By default, no specific caching policy is assigned.
      xegpu::CachePolicyAttr hint = nullptr;
      auto loadOp = xegpu::LoadNdOp::create(rewriter, loc, vecTy, ndDesc,
@@ -45,7 +45,7 @@ index 819c2e5973ff..545f1d77156c 100644
                                            /*l1_hint=*/hint,
                                            /*l2_hint=*/hint, /*l3_hint=*/hint);
      rewriter.replaceOp(readOp, loadOp);
-@@ -569,7 +571,10 @@ struct LoadLowering : public OpRewritePattern<vector::LoadOp> {
+@@ -684,7 +686,10 @@ struct LoadLowering : public OpRewritePattern<vector::LoadOp> {
      // By default, no specific caching policy is assigned.
      xegpu::CachePolicyAttr hint = nullptr;
      auto loadNdOp = xegpu::LoadNdOp::create(
@@ -58,18 +58,18 @@ index 819c2e5973ff..545f1d77156c 100644
          /*l2_hint=*/hint, /*l3_hint=*/hint);
      rewriter.replaceOp(loadOp, loadNdOp);
 diff --git a/mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp b/mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
-index 906c71d8b8da..ecee53c56a54 100644
+index abd12e2e69ac..7d076503c1a9 100644
 --- a/mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
 +++ b/mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
-@@ -78,6 +78,7 @@ static bool isWriteHintOrNone(const CachePolicyAttr &attr) {
+@@ -71,6 +71,7 @@ static bool isWriteHintOrNone(const CachePolicyAttr &attr) {
      return true;
    auto kind = attr.getValue();
    return kind == CachePolicy::CACHED || kind == CachePolicy::UNCACHED ||
 +         kind == CachePolicy::STREAMING ||
           kind == CachePolicy::WRITE_BACK || kind == CachePolicy::WRITE_THROUGH;
  }
 
-@@ -438,8 +439,8 @@ void LoadNdOp::build(OpBuilder &builder, OperationState &state, Type retType,
+@@ -495,8 +496,8 @@ void LoadNdOp::build(OpBuilder &builder, OperationState &state, Type retType,
                       xegpu::CachePolicyAttr l3_hint) {
 
    return build(builder, state, retType, tensorDesc, ValueRange(),
@@ -80,7 +80,7 @@ index 906c71d8b8da..ecee53c56a54 100644
  }
 
  void LoadNdOp::build(OpBuilder &builder, OperationState &state, Type retType,
-@@ -455,7 +456,8 @@ void LoadNdOp::build(OpBuilder &builder, OperationState &state, Type retType,
+@@ -512,7 +513,8 @@ void LoadNdOp::build(OpBuilder &builder, OperationState &state, Type retType,
    auto staticOffsetsAttr = builder.getDenseI64ArrayAttr(staticOffsets);
 
    build(builder, state, retType, tensorDesc, dynamicOffsets, staticOffsetsAttr,
@@ -90,7 +90,7 @@ index 906c71d8b8da..ecee53c56a54 100644
  }
 
  LogicalResult LoadNdOp::verify() {
-@@ -517,7 +519,7 @@ LogicalResult LoadNdOp::verify() {
+@@ -574,7 +576,7 @@ LogicalResult LoadNdOp::verify() {
        mlir::emitWarning(getLoc()) << "Invalid transpose attr. It is ignored.";
    }
 

build_tools/patches/0011-Add-Offset-Computing-Interface-For-MemDescType.patch

@@ -334,7 +334,8 @@ class InitOpPattern final : public OpConversionPattern<xetile::InitTileOp> {
               loc, rewriter.getIndexVectorAttr(cst));
           auto baseValue = getValueOrCreateConstantIndexOp(rewriter, loc, base);
           auto idxTy = VectorType::get(tileShape[0], rewriter.getIndexType());
-          auto splat = rewriter.create<vector::SplatOp>(loc, baseValue, idxTy);
+          auto splat =
+              rewriter.create<vector::BroadcastOp>(loc, idxTy, baseValue);
           auto result = add(splat.getResult(), cstOffsets.getResult());
           return getValueOrCreateConstantIndexOp(rewriter, loc, result);
         };