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Fix various crashes.
1 parent ba05d30 commit d5208ba

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5 files changed

+76
-59
lines changed

5 files changed

+76
-59
lines changed

‎clang/lib/CodeGen/TargetInfo.cpp‎

Lines changed: 32 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -297,21 +297,22 @@ static llvm::Value *emitRoundPointerUpToAlignment(CodeGenFunction &CGF,
297297
///
298298
/// This version implements the core direct-value passing rules.
299299
///
300-
/// \param SlotSize - The size and alignment of a stack slot.
300+
/// \param SlotSize - The size of a stack slot.
301301
/// Each argument will be allocated to a multiple of this number of
302-
/// slots, and all the slots will be aligned to this value.
302+
/// slots.
303+
/// \param SlotAlign - The alignment of a stack slot.
304+
/// Each slot will be aligned to this value.
303305
/// \param AllowHigherAlign - The slot alignment is not a cap;
304306
/// an argument type with an alignment greater than the slot size
305307
/// will be emitted on a higher-alignment address, potentially
306308
/// leaving one or more empty slots behind as padding. If this
307309
/// is false, the returned address might be less-aligned than
308310
/// DirectAlign.
309-
static Address emitVoidPtrDirectVAArg(CodeGenFunction &CGF,
310-
Address VAListAddr,
311+
static Address emitVoidPtrDirectVAArg(CodeGenFunction &CGF, Address VAListAddr,
311312
llvm::Type *DirectTy,
312313
CharUnits DirectSize,
313-
CharUnits DirectAlign,
314-
CharUnits SlotSize,
314+
CharUnits DirectAlign, CharUnits SlotSize,
315+
CharUnits SlotAlign,
315316
bool AllowHigherAlign) {
316317
// Cast the element type to i8* if necessary. Some platforms define
317318
// va_list as a struct containing an i8* instead of just an i8*.
@@ -322,11 +323,11 @@ static Address emitVoidPtrDirectVAArg(CodeGenFunction &CGF,
322323

323324
// If the CC aligns values higher than the slot size, do so if needed.
324325
Address Addr = Address::invalid();
325-
if (AllowHigherAlign && DirectAlign > SlotSize) {
326+
if (AllowHigherAlign && DirectAlign > SlotAlign) {
326327
Addr = Address(emitRoundPointerUpToAlignment(CGF, Ptr, DirectAlign),
327328
DirectAlign);
328329
} else {
329-
Addr = Address(Ptr, SlotSize);
330+
Addr = Address(Ptr, SlotAlign);
330331
}
331332

332333
// Advance the pointer past the argument, then store that back.
@@ -352,18 +353,18 @@ static Address emitVoidPtrDirectVAArg(CodeGenFunction &CGF,
352353
/// \param IsIndirect - Values of this type are passed indirectly.
353354
/// \param ValueInfo - The size and alignment of this type, generally
354355
/// computed with getContext().getTypeInfoInChars(ValueTy).
355-
/// \param SlotSizeAndAlign - The size and alignment of a stack slot.
356-
/// Each argument will be allocated to a multiple of this number of
357-
/// slots, and all the slots will be aligned to this value.
356+
/// \param SlotSize - The size of a stack slot.
357+
/// Each argument will be allocated to a multiple of this number of slots.
358+
/// \param SlotAlign - The alignment of a stack slot.
359+
/// Each slot will be aligned to this value.
358360
/// \param AllowHigherAlign - The slot alignment is not a cap;
359361
/// an argument type with an alignment greater than the slot size
360362
/// will be emitted on a higher-alignment address, potentially
361363
/// leaving one or more empty slots behind as padding.
362364
static Address emitVoidPtrVAArg(CodeGenFunction &CGF, Address VAListAddr,
363365
QualType ValueTy, bool IsIndirect,
364-
TypeInfoChars ValueInfo,
365-
CharUnits SlotSizeAndAlign,
366-
bool AllowHigherAlign) {
366+
TypeInfoChars ValueInfo, CharUnits SlotSize,
367+
CharUnits SlotAlign, bool AllowHigherAlign) {
367368
// The size and alignment of the value that was passed directly.
368369
CharUnits DirectSize, DirectAlign;
369370
if (IsIndirect) {
@@ -379,25 +380,32 @@ static Address emitVoidPtrVAArg(CodeGenFunction &CGF, Address VAListAddr,
379380
if (IsIndirect)
380381
DirectTy = DirectTy->getPointerTo(0);
381382

382-
Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, DirectTy,
383-
DirectSize, DirectAlign,
384-
SlotSizeAndAlign,
385-
AllowHigherAlign);
383+
Address Addr =
384+
emitVoidPtrDirectVAArg(CGF, VAListAddr, DirectTy, DirectSize, DirectAlign,
385+
SlotSize, SlotAlign, AllowHigherAlign);
386386

387387
if (IsIndirect) {
388388
Addr = Address(CGF.Builder.CreateLoad(Addr), ValueInfo.Align);
389389
}
390390

391391
return Addr;
392+
}
392393

394+
static Address emitVoidPtrVAArg(CodeGenFunction &CGF, Address VAListAddr,
395+
QualType ValueTy, bool IsIndirect,
396+
TypeInfoChars ValueInfo,
397+
CharUnits SlotSizeAndAlign,
398+
bool AllowHigherAlign) {
399+
return emitVoidPtrVAArg(CGF, VAListAddr, ValueTy, IsIndirect, ValueInfo,
400+
SlotSizeAndAlign, SlotSizeAndAlign, AllowHigherAlign);
393401
}
394402

395403
static Address complexTempStructure(CodeGenFunction &CGF, Address VAListAddr,
396404
QualType Ty, CharUnits SlotSize,
397405
CharUnits EltSize, const ComplexType *CTy) {
398-
Address Addr =
399-
emitVoidPtrDirectVAArg(CGF, VAListAddr, CGF.Int8Ty, SlotSize * 2,
400-
SlotSize, SlotSize, /*AllowHigher*/ true);
406+
Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, CGF.Int8Ty,
407+
SlotSize * 2, SlotSize, SlotSize,
408+
SlotSize, /*AllowHigher*/ true);
401409

402410
Address RealAddr = Addr;
403411
Address ImagAddr = RealAddr;
@@ -11240,13 +11248,12 @@ class Z80TargetCodeGenInfo : public TargetCodeGenInfo {
1124011248

1124111249
Address Z80ABIInfo::EmitVAArg(CodeGenFunction &CGF,
1124211250
Address VAListAddr, QualType Ty) const {
11243-
Address Addr = emitVoidPtrVAArg(
11251+
return emitVoidPtrVAArg(
1124411252
CGF, VAListAddr, Ty, /*Indirect*/ false,
1124511253
getContext().getTypeInfoInChars(Ty),
11246-
CharUnits::fromQuantity(getDataLayout().getPointerSize()),
11254+
/*SlotSize*/ CharUnits::fromQuantity(getDataLayout().getPointerSize()),
11255+
/*SlotAlign*/ CharUnits::One(),
1124711256
/*AllowHigherAlign*/ false);
11248-
// Remove SlotSize over-alignment, since stack is never aligned.
11249-
return Address(Addr.getPointer(), CharUnits::fromQuantity(1));
1125011257
}
1125111258

1125211259
void Z80TargetCodeGenInfo::setTargetAttributes(

‎llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -984,7 +984,7 @@ class LegalizationArtifactCombiner {
984984
const unsigned NumMergeRegs = MergeI->getNumOperands() - 1;
985985

986986
if (NumMergeRegs < NumDefs) {
987-
if (NumMergeRegs % NumDefs != 0)
987+
if (NumDefs % NumMergeRegs != 0)
988988
return false;
989989

990990
if (ConvertOp && !MRI.getType(MergeI->getOperand(0).getReg()).isVector())
@@ -1188,6 +1188,8 @@ class LegalizationArtifactCombiner {
11881188
(ExtractOffset + ExtractSize - 1) / MergeSrcSize;
11891189

11901190
Register MergeSrcReg;
1191+
if (MergeSrcIdx == 0 && EndMergeSrcIdx == NumMergeSrcs - 1)
1192+
return false;
11911193
if (MergeSrcIdx != EndMergeSrcIdx) {
11921194
// Create a sub-merge to extract from.
11931195
unsigned NumSubSrcs = EndMergeSrcIdx - MergeSrcIdx + 1;
@@ -1202,7 +1204,7 @@ class LegalizationArtifactCombiner {
12021204
MergeSrcReg = MergeI->getOperand(MergeSrcIdx + 1).getReg();
12031205

12041206
// TODO: We could modify MI in place in most cases.
1205-
Builder.buildExtract(DstReg, MergeI->getOperand(MergeSrcIdx + 1).getReg(),
1207+
Builder.buildExtract(DstReg, MergeSrcReg,
12061208
ExtractOffset - MergeSrcIdx * MergeSrcSize);
12071209
break;
12081210
}

‎llvm/lib/CodeGen/GlobalISel/Legalizer.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -103,6 +103,7 @@ static bool isArtifact(const MachineInstr &MI) {
103103
case TargetOpcode::G_CONCAT_VECTORS:
104104
case TargetOpcode::G_BUILD_VECTOR:
105105
case TargetOpcode::G_EXTRACT:
106+
case TargetOpcode::G_INSERT:
106107
return true;
107108
}
108109
}

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp‎

Lines changed: 38 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -46,8 +46,6 @@ using namespace MIPatternMatch;
4646
/// satisfiable.
4747
static std::pair<int, int>
4848
getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
49-
assert(!LeftoverTy.isValid() && "this is an out argument");
50-
5149
unsigned Size = OrigTy.getSizeInBits();
5250
unsigned NarrowSize = NarrowTy.getSizeInBits();
5351
unsigned NumParts = Size / NarrowSize;
@@ -175,7 +173,6 @@ bool LegalizerHelper::extractParts(Register Reg, LLT RegTy,
175173
std::tie(NumParts, NumLeftover) =
176174
getNarrowTypeBreakDown(RegTy, MainTy, LeftoverTy);
177175
unsigned MainSize = MainTy.getSizeInBits();
178-
unsigned LeftoverSize = LeftoverTy.getSizeInBits();
179176

180177
// Use an unmerge when possible.
181178
if (NumLeftover == 0) {
@@ -202,10 +199,11 @@ bool LegalizerHelper::extractParts(Register Reg, LLT RegTy,
202199
MIRBuilder.buildExtract(MainTy, Reg, MainSize * I).getReg(0));
203200

204201
for (int I = 0; I != NumLeftover; ++I)
205-
VRegs.push_back(MIRBuilder
206-
.buildExtract(LeftoverTy, Reg,
207-
MainSize * NumParts + LeftoverSize * I)
208-
.getReg(0));
202+
LeftoverRegs.push_back(
203+
MIRBuilder
204+
.buildExtract(LeftoverTy, Reg,
205+
MainSize * NumParts + LeftoverTy.getSizeInBits() * I)
206+
.getReg(0));
209207

210208
return true;
211209
}
@@ -248,10 +246,8 @@ void LegalizerHelper::extractVectorParts(Register Reg, unsigned NumElts,
248246
}
249247
}
250248

251-
void LegalizerHelper::insertParts(Register DstReg,
252-
LLT ResultTy, LLT PartTy,
253-
ArrayRef<Register> PartRegs,
254-
LLT LeftoverTy,
249+
void LegalizerHelper::insertParts(Register DstReg, LLT ResultTy, LLT PartTy,
250+
ArrayRef<Register> PartRegs, LLT LeftoverTy,
255251
ArrayRef<Register> LeftoverRegs) {
256252
if (!LeftoverTy.isValid()) {
257253
assert(LeftoverRegs.empty());
@@ -283,12 +279,19 @@ void LegalizerHelper::insertParts(Register DstReg,
283279
return mergeMixedSubvectors(DstReg, AllRegs);
284280
}
285281

286-
SmallVector<Register> GCDRegs;
287-
LLT GCDTy = getGCDType(getGCDType(ResultTy, LeftoverTy), PartTy);
288-
for (auto PartReg : concat<const Register>(PartRegs, LeftoverRegs))
289-
extractGCDType(GCDRegs, GCDTy, PartReg);
290-
LLT ResultLCMTy = buildLCMMergePieces(ResultTy, LeftoverTy, GCDTy, GCDRegs);
291-
buildWidenedRemergeToDst(DstReg, ResultLCMTy, GCDRegs);
282+
unsigned Offset = 0;
283+
unsigned ResultSize = ResultTy.getSizeInBits();
284+
Register TmpReg = MIRBuilder.buildUndef(ResultTy).getReg(0);
285+
for (Register Reg : concat<const Register>(PartRegs, LeftoverRegs)) {
286+
unsigned NextOffset = Offset + MRI.getType(Reg).getSizeInBits();
287+
DstOp Result = ResultTy;
288+
if (NextOffset == ResultSize)
289+
Result = DstReg;
290+
TmpReg = MIRBuilder.buildInsert(Result, TmpReg, Reg, Offset).getReg(0);
291+
Offset = NextOffset;
292+
}
293+
if (DstReg != TmpReg)
294+
MIRBuilder.buildCopy(DstReg, TmpReg);
292295
}
293296

294297
void LegalizerHelper::appendVectorElts(SmallVectorImpl<Register> &Elts,
@@ -1087,7 +1090,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
10871090
LeftoverRegs.clear();
10881091

10891092
unsigned MainSize = PartRegs.size() * NarrowSize;
1090-
unsigned LeftoverSize;
1093+
unsigned LeftoverSize = 0;
10911094
if (SizeOp0 < MainSize) {
10921095
PartRegs.truncate(SizeOp0 / NarrowSize);
10931096
LeftoverSize = SizeOp0 % NarrowSize;
@@ -1101,6 +1104,10 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
11011104
LeftoverRegs.push_back(
11021105
MIRBuilder.buildExtract(LeftoverTy, Op1, Offset).getReg(0));
11031106
}
1107+
if (PartRegs.empty()) {
1108+
NarrowTy = std::exchange(LeftoverTy, LLT{});
1109+
PartRegs.swap(LeftoverRegs);
1110+
}
11041111

11051112
insertParts(Op0, Op0Ty, NarrowTy, PartRegs, LeftoverTy, LeftoverRegs);
11061113
MI.eraseFromParent();
@@ -1111,19 +1118,19 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
11111118
if (TypeIdx != 0)
11121119
return UnableToLegalize;
11131120

1114-
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
1115-
// Should widen scalar first
1116-
if (Ty.getSizeInBits() % NarrowTy.getSizeInBits() != 0)
1121+
Register Op1 = MI.getOperand(1).getReg();
1122+
LLT Op1Ty = MRI.getType(Op1);
1123+
LLT LeftoverTy;
1124+
SmallVector<Register, 4> PartRegs;
1125+
SmallVector<Register, 1> LeftoverRegs;
1126+
if (!extractParts(Op1, Op1Ty, NarrowTy, LeftoverTy, PartRegs, LeftoverRegs))
11171127
return UnableToLegalize;
1128+
for (Register &PartReg : PartRegs)
1129+
PartReg = MIRBuilder.buildFreeze(NarrowTy, PartReg).getReg(0);
1130+
for (Register &LeftoverReg : LeftoverRegs)
1131+
LeftoverReg = MIRBuilder.buildFreeze(LeftoverTy, LeftoverReg).getReg(0);
11181132

1119-
auto Unmerge = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1).getReg());
1120-
SmallVector<Register, 8> Parts;
1121-
for (unsigned i = 0; i < Unmerge->getNumDefs(); ++i) {
1122-
Parts.push_back(
1123-
MIRBuilder.buildFreeze(NarrowTy, Unmerge.getReg(i)).getReg(0));
1124-
}
1125-
1126-
MIRBuilder.buildMerge(MI.getOperand(0).getReg(), Parts);
1133+
insertParts(Op0, Op0Ty, NarrowTy, PartRegs, LeftoverTy, LeftoverRegs);
11271134
MI.eraseFromParent();
11281135
return Legalized;
11291136
}
@@ -1295,7 +1302,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
12951302
for (unsigned j = 1; j < MI.getNumOperands(); j += 2)
12961303
MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1));
12971304
}
1298-
SmallVector<Register, 1> DstLeftoverRegs(SrcRegs[0].size());
1305+
SmallVector<Register, 1> DstLeftoverRegs(SrcLeftoverRegs[0].size());
12991306
for (unsigned i = 0; i < DstLeftoverRegs.size(); ++i) {
13001307
auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI, {LeftoverTy}, {});
13011308
DstLeftoverRegs[i] = MIB.getReg(0);
@@ -5546,7 +5553,7 @@ LegalizerHelper::narrowScalarExt(MachineInstr &MI, unsigned TypeIdx,
55465553
PartRegs.push_back(ExtReg);
55475554
if (SizeOp0 > NumParts * NarrowSize) {
55485555
LeftoverTy = LLT::scalar(SizeOp0 - NarrowSize * NumParts);
5549-
LeftoverRegs[0] = MIRBuilder.buildTrunc(LeftoverTy, ExtReg).getReg(0);
5556+
LeftoverRegs = {MIRBuilder.buildTrunc(LeftoverTy, ExtReg).getReg(0)};
55505557
} else {
55515558
LeftoverTy = LLT{};
55525559
LeftoverRegs.clear();

‎llvm/lib/Target/Z80/GISel/Z80CallLowering.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -148,7 +148,7 @@ struct CallArgHandler : public Z80OutgoingValueHandler {
148148
auto SaveInsertPt = std::prev(MIRBuilder.getInsertPt());
149149
MIRBuilder.setInsertPt(MIRBuilder.getMBB(), StackPushes);
150150
--StackPushes;
151-
if (MemTy != SlotTy)
151+
if (MemTy.getSizeInBits() < SlotTy.getSizeInBits())
152152
ValVReg = MIRBuilder.buildAnyExt(SlotTy, ValVReg).getReg(0);
153153
MIRBuilder.buildInstr(STI.is24Bit() ? Z80::PUSH24r : Z80::PUSH16r,
154154
{}, {ValVReg});

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