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signalgenerate.flow.rpt
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Flow report for signalgenerate
Mon Mar 04 22:45:31 2019
Quartus II 64-Bit Version 14.1.0 Build 186 12/03/2014 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus II License Agreement,
the Altera MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Altera and sold by Altera or its
authorized distributors. Please refer to the applicable
agreement for further details.
+----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+---------------------------------------------+
; Flow Status ; Successful - Mon Mar 04 22:45:08 2019 ;
; Quartus II 64-Bit Version ; 14.1.0 Build 186 12/03/2014 SJ Full Version ;
; Revision Name ; signalgenerate ;
; Top-level Entity Name ; PCI ;
; Family ; Cyclone IV E ;
; Device ; EP4CE30F23I7 ;
; Timing Models ; Final ;
; Total logic elements ; 3,565 / 28,848 ( 12 % ) ;
; Total combinational functions ; 1,791 / 28,848 ( 6 % ) ;
; Dedicated logic registers ; 3,072 / 28,848 ( 11 % ) ;
; Total registers ; 3072 ;
; Total pins ; 87 / 329 ( 26 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 356,416 / 608,256 ( 59 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
+------------------------------------+---------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 03/04/2019 22:41:30 ;
; Main task ; Compilation ;
; Revision Name ; signalgenerate ;
+-------------------+---------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+-------------+------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+-------------+------------------+
; COMPILER_SIGNATURE_ID ; 88491855341211.155171049001532 ; -- ; -- ; -- ;
; ENABLE_DA_RULE ; C101, C102, C103, C104, C105, C106, R101, R102, R103, R104, R105, T101, T102, A101, A102, A103, A104, A105, A106, A107, A108, A109, A110, S101, S102, S103, S104, D101, D102, D103, M101, M102, M103, M104, M105 ; -- ; -- ; -- ;
; ENABLE_SIGNALTAP ; On ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 100 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; -40 ; -- ; -- ; -- ;
; MISC_FILE ; PLL_80.bsf ; -- ; -- ; -- ;
; MISC_FILE ; PLL_80_inst.vhd ; -- ; -- ; -- ;
; MISC_FILE ; PLL_80.inc ; -- ; -- ; -- ;
; MISC_FILE ; PLL_80.cmp ; -- ; -- ; -- ;
; MISC_FILE ; PLL_80.ppf ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; PCI ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; PCI ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; PCI ; Top ;
; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
; SLD_FILE ; db/stp1_auto_stripped.stp ; -- ; -- ; -- ;
; SLD_NODE_CREATOR_ID ; 110 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_ENTITY_NAME ; sld_signaltap ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_NODE_INFO=805334528 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_POWER_UP_TRIGGER=0 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_ATTRIBUTE_MEM_MODE=OFF ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_STATE_FLOW_USE_GENERATED=0 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_STATE_BITS=11 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_BUFFER_FULL_STOP=1 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_CURRENT_RESOURCE_WIDTH=1 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_TRIGGER_LEVEL=1 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_TRIGGER_IN_ENABLED=0 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_ADVANCED_TRIGGER_ENTITY=basic,1, ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_TRIGGER_LEVEL_PIPELINE=1 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_ENABLE_ADVANCED_TRIGGER=0 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_INCREMENTAL_ROUTING=1 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_RAM_BLOCK_TYPE=AUTO ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_SEGMENT_SIZE=2048 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_SAMPLE_DEPTH=2048 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_DATA_BITS=160 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_TRIGGER_BITS=160 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_STORAGE_QUALIFIER_BITS=160 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_INVERSION_MASK=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_INVERSION_MASK_LENGTH=505 ; -- ; -- ; auto_signaltap_0 ;
; TOP_LEVEL_ENTITY ; PCI ; signalgenerate ; -- ; -- ;
; USE_SIGNALTAP_FILE ; stp1.stp ; -- ; -- ; -- ;
+-------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+-------------+------------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:02:02 ; 1.0 ; 4902 MB ; 00:03:39 ;
; Fitter ; 00:01:05 ; 1.3 ; 5751 MB ; 00:01:29 ;
; Assembler ; 00:00:09 ; 1.0 ; 4737 MB ; 00:00:09 ;
; TimeQuest Timing Analyzer ; 00:00:16 ; 1.3 ; 4896 MB ; 00:00:18 ;
; Total ; 00:03:32 ; -- ; -- ; 00:05:35 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+----------------------------------------------------------------------------------------+
; Flow OS Summary ;
+---------------------------+------------------+-----------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+---------------------------+------------------+-----------+------------+----------------+
; Analysis & Synthesis ; LAPTOP-FD3GDQQ0 ; Windows 7 ; 6.2 ; x86_64 ;
; Fitter ; LAPTOP-FD3GDQQ0 ; Windows 7 ; 6.2 ; x86_64 ;
; Assembler ; LAPTOP-FD3GDQQ0 ; Windows 7 ; 6.2 ; x86_64 ;
; TimeQuest Timing Analyzer ; LAPTOP-FD3GDQQ0 ; Windows 7 ; 6.2 ; x86_64 ;
+---------------------------+------------------+-----------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off signalgenerate -c signalgenerate
quartus_fit --read_settings_files=off --write_settings_files=off signalgenerate -c signalgenerate
quartus_asm --read_settings_files=off --write_settings_files=off signalgenerate -c signalgenerate
quartus_sta signalgenerate -c signalgenerate