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bd_zcu102_2cam.tcl
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bd_zcu102_2cam.tcl
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################################################################
# This is a generated script based on design: design_1
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2017.4
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source design_1_script.tcl
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xczu9eg-ffvb1156-2-e
set_property BOARD_PART xilinx.com:zcu102:part0:3.1 [current_project]
}
# CHANGE DESIGN NAME HERE
variable design_name
set design_name design_1
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
return $nRet
}
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:axi_gpio:2.0\
xilinx.com:ip:axi_intc:4.1\
xilinx.com:ip:clk_wiz:5.4\
xilinx.com:ip:xlconcat:2.1\
xilinx.com:ip:proc_sys_reset:5.0\
xilinx.com:ip:axi_iic:2.0\
xilinx.com:ip:zynq_ultra_ps_e:3.1\
xilinx.com:ip:axi_data_fifo:2.1\
xilinx.com:ip:axis_subset_converter:1.1\
xilinx.com:ip:xlslice:1.0\
xilinx.com:ip:mipi_csi2_rx_subsystem:3.0\
xilinx.com:ip:v_demosaic:1.0\
xilinx.com:ip:v_frmbuf_wr:2.0\
xilinx.com:ip:v_gamma_lut:1.0\
xilinx.com:ip:v_proc_ss:2.0\
xilinx.com:ip:xlconstant:1.1\
"
set list_ips_missing ""
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
if { $ip_obj eq "" } {
lappend list_ips_missing $ip_vlnv
}
}
if { $list_ips_missing ne "" } {
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
##################################################################
# DESIGN PROCs
##################################################################
# Hierarchical cell: mipi_csi2_rx1
proc create_hier_cell_mipi_csi2_rx1 { parentCell nameHier } {
variable script_folder
if { $parentCell eq "" || $nameHier eq "" } {
catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_mipi_csi2_rx1() - Empty argument(s)!"}
return
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create cell and set as current instance
set hier_obj [create_bd_cell -type hier $nameHier]
current_bd_instance $hier_obj
# Create interface pins
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_S2MM
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 csirxss_s_axi
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 ctrl
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:mipi_phy_rtl:1.0 mipi_phy_if_0
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_CTRL1
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_CTRL2
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_ctrl
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_ctrl3
# Create pins
create_bd_pin -dir I -from 94 -to 0 Din
create_bd_pin -dir O -from 0 -to 0 Dout
create_bd_pin -dir I -type rst axi_resetn
create_bd_pin -dir O -type intr csirxss_csi_irq
create_bd_pin -dir O -from 0 -to 0 dout1
create_bd_pin -dir I -type clk dphy_clk_200M
create_bd_pin -dir I -type clk m_axi_s2mm_aclk
create_bd_pin -dir O -type intr s2mm_introut
create_bd_pin -dir I -type clk s_axi_lite_aclk
create_bd_pin -dir I -type rst video_aresetn
# Create instance: axi_data_fifo_0, and set properties
set axi_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_data_fifo:2.1 axi_data_fifo_0 ]
set_property -dict [ list \
CONFIG.WRITE_FIFO_DELAY {1} \
CONFIG.WRITE_FIFO_DEPTH {512} \
] $axi_data_fifo_0
# Create instance: axis_subset_converter_0, and set properties
set axis_subset_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 axis_subset_converter_0 ]
set_property -dict [ list \
CONFIG.M_TDATA_NUM_BYTES {2} \
CONFIG.S_TDATA_NUM_BYTES {3} \
CONFIG.TDATA_REMAP {tdata[19:12],tdata[9:2]} \
] $axis_subset_converter_0
# Create instance: demosaic_rst_gpio, and set properties
set demosaic_rst_gpio [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 demosaic_rst_gpio ]
set_property -dict [ list \
CONFIG.DIN_FROM {7} \
CONFIG.DIN_TO {7} \
CONFIG.DIN_WIDTH {95} \
CONFIG.DOUT_WIDTH {1} \
] $demosaic_rst_gpio
# Create instance: frmbuf_wr_rst_gpio, and set properties
set frmbuf_wr_rst_gpio [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 frmbuf_wr_rst_gpio ]
set_property -dict [ list \
CONFIG.DIN_FROM {2} \
CONFIG.DIN_TO {2} \
CONFIG.DIN_WIDTH {95} \
CONFIG.DOUT_WIDTH {1} \
] $frmbuf_wr_rst_gpio
# Create instance: gamma_rst_gpio, and set properties
set gamma_rst_gpio [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 gamma_rst_gpio ]
set_property -dict [ list \
CONFIG.DIN_FROM {8} \
CONFIG.DIN_TO {8} \
CONFIG.DIN_WIDTH {95} \
CONFIG.DOUT_WIDTH {1} \
] $gamma_rst_gpio
# Create instance: mipi_csi2_rx_subsystem_0, and set properties
set mipi_csi2_rx_subsystem_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mipi_csi2_rx_subsystem:3.0 mipi_csi2_rx_subsystem_0 ]
set_property -dict [ list \
CONFIG.CLK_LANE_IO_LOC {AE5} \
CONFIG.CLK_LANE_IO_LOC_NAME {IO_L13P_T2L_N0_GC_QBC_65} \
CONFIG.CMN_INC_IIC {false} \
CONFIG.CMN_NUM_LANES {4} \
CONFIG.CMN_NUM_PIXELS {2} \
CONFIG.CMN_PROJ_FAMILY {1} \
CONFIG.CMN_PXL_FORMAT {RAW10} \
CONFIG.CSI_BUF_DEPTH {4096} \
CONFIG.C_CLK_LANE_IO_POSITION {26} \
CONFIG.C_CSI_EN_ACTIVELANES {true} \
CONFIG.C_CSI_FILTER_USERDATATYPE {true} \
CONFIG.C_DATA_LANE0_IO_POSITION {30} \
CONFIG.C_DATA_LANE1_IO_POSITION {32} \
CONFIG.C_DATA_LANE2_IO_POSITION {34} \
CONFIG.C_DATA_LANE3_IO_POSITION {36} \
CONFIG.C_DPHY_LANES {4} \
CONFIG.C_EN_BG0_PIN0 {false} \
CONFIG.C_EN_BG1_PIN0 {false} \
CONFIG.C_EN_BG3_PIN0 {false} \
CONFIG.C_HS_LINE_RATE {1440} \
CONFIG.C_HS_SETTLE_NS {141} \
CONFIG.DATA_LANE0_BYTE {All_Byte} \
CONFIG.DATA_LANE0_IO_LOC {AH4} \
CONFIG.DATA_LANE0_IO_LOC_NAME {IO_L15P_T2L_N4_AD11P_65} \
CONFIG.DATA_LANE1_BYTE {All_Byte} \
CONFIG.DATA_LANE1_IO_LOC {AJ6} \
CONFIG.DATA_LANE1_IO_LOC_NAME {IO_L16P_T2U_N6_QBC_AD3P_65} \
CONFIG.DATA_LANE2_BYTE {All_Byte} \
CONFIG.DATA_LANE2_IO_LOC {AE3} \
CONFIG.DATA_LANE2_IO_LOC_NAME {IO_L17P_T2U_N8_AD10P_65} \
CONFIG.DATA_LANE3_BYTE {All_Byte} \
CONFIG.DATA_LANE3_IO_LOC {AD4} \
CONFIG.DATA_LANE3_IO_LOC_NAME {IO_L18P_T2U_N10_AD2P_65} \
CONFIG.DPY_EN_REG_IF {false} \
CONFIG.DPY_LINE_RATE {1440} \
CONFIG.HP_IO_BANK_SELECTION {65} \
CONFIG.SupportLevel {1} \
] $mipi_csi2_rx_subsystem_0
# Create instance: sensor_rst_gpio, and set properties
set sensor_rst_gpio [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 sensor_rst_gpio ]
set_property -dict [ list \
CONFIG.DIN_FROM {12} \
CONFIG.DIN_TO {12} \
CONFIG.DIN_WIDTH {95} \
CONFIG.DOUT_WIDTH {1} \
] $sensor_rst_gpio
# Create instance: v_demosaic_0, and set properties
set v_demosaic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:v_demosaic:1.0 v_demosaic_0 ]
set_property -dict [ list \
CONFIG.ENABLE_ZIPPER_REMOVAL {false} \
CONFIG.SAMPLES_PER_CLOCK {2} \
] $v_demosaic_0
# Create instance: v_frmbuf_wr_0, and set properties
set v_frmbuf_wr_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:v_frmbuf_wr:2.0 v_frmbuf_wr_0 ]
set_property -dict [ list \
CONFIG.AXIMM_DATA_WIDTH {128} \
CONFIG.C_M_AXI_MM_VIDEO_DATA_WIDTH {128} \
CONFIG.HAS_RGB8 {0} \
CONFIG.HAS_RGBX8 {0} \
CONFIG.HAS_UYVY8 {1} \
CONFIG.HAS_Y8 {1} \
CONFIG.HAS_YUV8 {0} \
CONFIG.HAS_YUVX8 {0} \
CONFIG.HAS_YUYV8 {1} \
CONFIG.HAS_Y_UV8 {0} \
CONFIG.HAS_Y_UV8_420 {0} \
CONFIG.MAX_NR_PLANES {1} \
CONFIG.SAMPLES_PER_CLOCK {2} \
] $v_frmbuf_wr_0
# Create instance: v_gamma_lut_0, and set properties
set v_gamma_lut_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:v_gamma_lut:1.0 v_gamma_lut_0 ]
set_property -dict [ list \
CONFIG.SAMPLES_PER_CLOCK {2} \
] $v_gamma_lut_0
# Create instance: v_proc_ss_csc, and set properties
set v_proc_ss_csc [ create_bd_cell -type ip -vlnv xilinx.com:ip:v_proc_ss:2.0 v_proc_ss_csc ]
set_property -dict [ list \
CONFIG.C_COLORSPACE_SUPPORT {2} \
CONFIG.C_CSC_ENABLE_WINDOW {false} \
CONFIG.C_MAX_DATA_WIDTH {8} \
CONFIG.C_SAMPLES_PER_CLK {2} \
CONFIG.C_TOPOLOGY {3} \
] $v_proc_ss_csc
# Create instance: v_proc_ss_scaler, and set properties
set v_proc_ss_scaler [ create_bd_cell -type ip -vlnv xilinx.com:ip:v_proc_ss:2.0 v_proc_ss_scaler ]
set_property -dict [ list \
CONFIG.C_COLORSPACE_SUPPORT {1} \
CONFIG.C_ENABLE_CSC {true} \
CONFIG.C_H_SCALER_TAPS {8} \
CONFIG.C_MAX_DATA_WIDTH {8} \
CONFIG.C_SAMPLES_PER_CLK {2} \
CONFIG.C_TOPOLOGY {0} \
CONFIG.C_V_SCALER_TAPS {8} \
] $v_proc_ss_scaler
# Create instance: vcc, and set properties
set vcc [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 vcc ]
# Create instance: vpss_csc_rst_gpio, and set properties
set vpss_csc_rst_gpio [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 vpss_csc_rst_gpio ]
set_property -dict [ list \
CONFIG.DIN_FROM {6} \
CONFIG.DIN_TO {6} \
CONFIG.DIN_WIDTH {95} \
CONFIG.DOUT_WIDTH {1} \
] $vpss_csc_rst_gpio
# Create instance: vpss_scaler_rst_gpio, and set properties
set vpss_scaler_rst_gpio [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 vpss_scaler_rst_gpio ]
set_property -dict [ list \
CONFIG.DIN_FROM {4} \
CONFIG.DIN_TO {4} \
CONFIG.DIN_WIDTH {95} \
CONFIG.DOUT_WIDTH {1} \
] $vpss_scaler_rst_gpio
# Create interface connections
connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins s_axi_ctrl] [get_bd_intf_pins v_proc_ss_scaler/s_axi_ctrl]
connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins s_axi_CTRL1] [get_bd_intf_pins v_gamma_lut_0/s_axi_CTRL]
connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins s_axi_CTRL2] [get_bd_intf_pins v_frmbuf_wr_0/s_axi_CTRL]
connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins s_axi_ctrl3] [get_bd_intf_pins v_proc_ss_csc/s_axi_ctrl]
connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins mipi_phy_if_0] [get_bd_intf_pins mipi_csi2_rx_subsystem_0/mipi_phy_if]
connect_bd_intf_net -intf_net axi_data_fifo_0_M_AXI [get_bd_intf_pins M_AXI_S2MM] [get_bd_intf_pins axi_data_fifo_0/M_AXI]
connect_bd_intf_net -intf_net axi_interconnect_hpm0_M05_AXI [get_bd_intf_pins csirxss_s_axi] [get_bd_intf_pins mipi_csi2_rx_subsystem_0/csirxss_s_axi]
connect_bd_intf_net -intf_net axis_subset_converter_0_M_AXIS [get_bd_intf_pins axis_subset_converter_0/M_AXIS] [get_bd_intf_pins v_demosaic_0/s_axis_video]
connect_bd_intf_net -intf_net ctrl_1 [get_bd_intf_pins ctrl] [get_bd_intf_pins v_demosaic_0/s_axi_CTRL]
connect_bd_intf_net -intf_net mipi_csi2_rx_subsystem_0_video_out [get_bd_intf_pins axis_subset_converter_0/S_AXIS] [get_bd_intf_pins mipi_csi2_rx_subsystem_0/video_out]
connect_bd_intf_net -intf_net v_demosaic_0_m_axis_video [get_bd_intf_pins v_demosaic_0/m_axis_video] [get_bd_intf_pins v_gamma_lut_0/s_axis_video]
connect_bd_intf_net -intf_net v_frmbuf_wr_0_m_axi_mm_video [get_bd_intf_pins axi_data_fifo_0/S_AXI] [get_bd_intf_pins v_frmbuf_wr_0/m_axi_mm_video]
connect_bd_intf_net -intf_net v_gamma_lut_0_m_axis_video [get_bd_intf_pins v_gamma_lut_0/m_axis_video] [get_bd_intf_pins v_proc_ss_csc/s_axis]
connect_bd_intf_net -intf_net v_proc_ss_0_m_axis [get_bd_intf_pins v_frmbuf_wr_0/s_axis_video] [get_bd_intf_pins v_proc_ss_scaler/m_axis]
connect_bd_intf_net -intf_net v_proc_ss_1_m_axis [get_bd_intf_pins v_proc_ss_csc/m_axis] [get_bd_intf_pins v_proc_ss_scaler/s_axis]
# Create port connections
connect_bd_net -net Din_1 [get_bd_pins Din] [get_bd_pins demosaic_rst_gpio/Din] [get_bd_pins frmbuf_wr_rst_gpio/Din] [get_bd_pins gamma_rst_gpio/Din] [get_bd_pins sensor_rst_gpio/Din] [get_bd_pins vpss_csc_rst_gpio/Din] [get_bd_pins vpss_scaler_rst_gpio/Din]
connect_bd_net -net M06_ARESETN_1 [get_bd_pins video_aresetn] [get_bd_pins axis_subset_converter_0/aresetn] [get_bd_pins mipi_csi2_rx_subsystem_0/video_aresetn]
connect_bd_net -net clk_150mhz [get_bd_pins m_axi_s2mm_aclk] [get_bd_pins axi_data_fifo_0/aclk] [get_bd_pins axis_subset_converter_0/aclk] [get_bd_pins mipi_csi2_rx_subsystem_0/video_aclk] [get_bd_pins v_demosaic_0/ap_clk] [get_bd_pins v_frmbuf_wr_0/ap_clk] [get_bd_pins v_gamma_lut_0/ap_clk] [get_bd_pins v_proc_ss_csc/aclk] [get_bd_pins v_proc_ss_scaler/aclk_axis] [get_bd_pins v_proc_ss_scaler/aclk_ctrl]
connect_bd_net -net clk_50mhz [get_bd_pins s_axi_lite_aclk] [get_bd_pins mipi_csi2_rx_subsystem_0/lite_aclk]
connect_bd_net -net clk_wiz_0_clk_out3 [get_bd_pins dphy_clk_200M] [get_bd_pins mipi_csi2_rx_subsystem_0/dphy_clk_200M]
connect_bd_net -net demosaic_rst_gpio_Dout [get_bd_pins demosaic_rst_gpio/Dout] [get_bd_pins v_demosaic_0/ap_rst_n]
connect_bd_net -net frmbuf_wr_rst_gpio1_Dout [get_bd_pins v_proc_ss_scaler/aresetn_ctrl] [get_bd_pins vpss_scaler_rst_gpio/Dout]
connect_bd_net -net gamma_rst_gpio_Dout [get_bd_pins gamma_rst_gpio/Dout] [get_bd_pins v_gamma_lut_0/ap_rst_n]
connect_bd_net -net mipi_csi2_rx_subsystem_0_csirxss_csi_irq [get_bd_pins csirxss_csi_irq] [get_bd_pins mipi_csi2_rx_subsystem_0/csirxss_csi_irq]
connect_bd_net -net proc_sys_reset_clk50_peripheral_aresetn [get_bd_pins axi_resetn] [get_bd_pins mipi_csi2_rx_subsystem_0/lite_aresetn]
connect_bd_net -net sensor_rst_gpio_Dout [get_bd_pins Dout] [get_bd_pins sensor_rst_gpio/Dout]
connect_bd_net -net tpg_rst_gpio_Dout [get_bd_pins axi_data_fifo_0/aresetn] [get_bd_pins frmbuf_wr_rst_gpio/Dout] [get_bd_pins v_frmbuf_wr_0/ap_rst_n]
connect_bd_net -net v_frmbuf_wr_0_interrupt [get_bd_pins s2mm_introut] [get_bd_pins v_frmbuf_wr_0/interrupt]
connect_bd_net -net vcc_dout [get_bd_pins dout1] [get_bd_pins vcc/dout]
connect_bd_net -net vpss_csc_rst_gpio_Dout [get_bd_pins v_proc_ss_csc/aresetn] [get_bd_pins vpss_csc_rst_gpio/Dout]
# Restore current instance
current_bd_instance $oldCurInst
}
# Hierarchical cell: mipi_csi2_rx0
proc create_hier_cell_mipi_csi2_rx0 { parentCell nameHier } {
variable script_folder
if { $parentCell eq "" || $nameHier eq "" } {
catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_mipi_csi2_rx0() - Empty argument(s)!"}
return
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create cell and set as current instance
set hier_obj [create_bd_cell -type hier $nameHier]
current_bd_instance $hier_obj
# Create interface pins
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_S2MM
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 csirxss_s_axi
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 ctrl
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:mipi_phy_rtl:1.0 mipi_phy_if_0
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_CTRL1
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_CTRL2
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_ctrl
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_ctrl3
# Create pins
create_bd_pin -dir I -from 94 -to 0 Din
create_bd_pin -dir O -from 0 -to 0 Dout
create_bd_pin -dir I -type rst axi_resetn
create_bd_pin -dir O -type intr csirxss_csi_irq
create_bd_pin -dir O -from 0 -to 0 dout1
create_bd_pin -dir I -type clk dphy_clk_200M
create_bd_pin -dir I -type clk m_axi_s2mm_aclk
create_bd_pin -dir O -type intr s2mm_introut
create_bd_pin -dir I -type clk s_axi_lite_aclk
create_bd_pin -dir I -type rst video_aresetn
# Create instance: axi_data_fifo_0, and set properties
set axi_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_data_fifo:2.1 axi_data_fifo_0 ]
set_property -dict [ list \
CONFIG.WRITE_FIFO_DELAY {1} \
CONFIG.WRITE_FIFO_DEPTH {512} \
] $axi_data_fifo_0
# Create instance: axis_subset_converter_0, and set properties
set axis_subset_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 axis_subset_converter_0 ]
set_property -dict [ list \
CONFIG.M_TDATA_NUM_BYTES {2} \
CONFIG.S_TDATA_NUM_BYTES {3} \
CONFIG.TDATA_REMAP {tdata[19:12],tdata[9:2]} \
] $axis_subset_converter_0
# Create instance: demosaic_rst_gpio, and set properties
set demosaic_rst_gpio [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 demosaic_rst_gpio ]
set_property -dict [ list \
CONFIG.DIN_FROM {7} \
CONFIG.DIN_TO {7} \
CONFIG.DIN_WIDTH {95} \
CONFIG.DOUT_WIDTH {1} \
] $demosaic_rst_gpio
# Create instance: frmbuf_wr_rst_gpio, and set properties
set frmbuf_wr_rst_gpio [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 frmbuf_wr_rst_gpio ]
set_property -dict [ list \
CONFIG.DIN_FROM {2} \
CONFIG.DIN_TO {2} \
CONFIG.DIN_WIDTH {95} \
CONFIG.DOUT_WIDTH {1} \
] $frmbuf_wr_rst_gpio
# Create instance: gamma_rst_gpio, and set properties
set gamma_rst_gpio [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 gamma_rst_gpio ]
set_property -dict [ list \
CONFIG.DIN_FROM {8} \
CONFIG.DIN_TO {8} \
CONFIG.DIN_WIDTH {95} \
CONFIG.DOUT_WIDTH {1} \
] $gamma_rst_gpio
# Create instance: mipi_csi2_rx_subsystem_0, and set properties
set mipi_csi2_rx_subsystem_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mipi_csi2_rx_subsystem:3.0 mipi_csi2_rx_subsystem_0 ]
set_property -dict [ list \
CONFIG.CLK_LANE_IO_LOC {Y4} \
CONFIG.CLK_LANE_IO_LOC_NAME {IO_L13P_T2L_N0_GC_QBC_66} \
CONFIG.CMN_INC_IIC {false} \
CONFIG.CMN_NUM_LANES {4} \
CONFIG.CMN_NUM_PIXELS {2} \
CONFIG.CMN_PROJ_FAMILY {1} \
CONFIG.CMN_PXL_FORMAT {RAW10} \
CONFIG.CSI_BUF_DEPTH {4096} \
CONFIG.C_CLK_LANE_IO_POSITION {26} \
CONFIG.C_CSI_EN_ACTIVELANES {true} \
CONFIG.C_CSI_FILTER_USERDATATYPE {true} \
CONFIG.C_DATA_LANE0_IO_POSITION {30} \
CONFIG.C_DATA_LANE1_IO_POSITION {32} \
CONFIG.C_DATA_LANE2_IO_POSITION {34} \
CONFIG.C_DATA_LANE3_IO_POSITION {36} \
CONFIG.C_DPHY_LANES {4} \
CONFIG.C_EN_BG0_PIN0 {false} \
CONFIG.C_EN_BG1_PIN0 {false} \
CONFIG.C_EN_BG3_PIN0 {false} \
CONFIG.C_HS_LINE_RATE {1440} \
CONFIG.C_HS_SETTLE_NS {141} \
CONFIG.DATA_LANE0_BYTE {All_Byte} \
CONFIG.DATA_LANE0_IO_LOC {W5} \
CONFIG.DATA_LANE0_IO_LOC_NAME {IO_L15P_T2L_N4_AD11P_66} \
CONFIG.DATA_LANE1_BYTE {All_Byte} \
CONFIG.DATA_LANE1_IO_LOC {AB4} \
CONFIG.DATA_LANE1_IO_LOC_NAME {IO_L16P_T2U_N6_QBC_AD3P_66} \
CONFIG.DATA_LANE2_BYTE {All_Byte} \
CONFIG.DATA_LANE2_IO_LOC {V4} \
CONFIG.DATA_LANE2_IO_LOC_NAME {IO_L17P_T2U_N8_AD10P_66} \
CONFIG.DATA_LANE3_BYTE {All_Byte} \
CONFIG.DATA_LANE3_IO_LOC {U5} \
CONFIG.DATA_LANE3_IO_LOC_NAME {IO_L18P_T2U_N10_AD2P_66} \
CONFIG.DPY_EN_REG_IF {false} \
CONFIG.DPY_LINE_RATE {1440} \
CONFIG.HP_IO_BANK_SELECTION {66} \
CONFIG.SupportLevel {1} \
] $mipi_csi2_rx_subsystem_0
# Create instance: sensor_rst_gpio, and set properties
set sensor_rst_gpio [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 sensor_rst_gpio ]
set_property -dict [ list \
CONFIG.DIN_FROM {12} \
CONFIG.DIN_TO {12} \
CONFIG.DIN_WIDTH {95} \
CONFIG.DOUT_WIDTH {1} \
] $sensor_rst_gpio
# Create instance: v_demosaic_0, and set properties
set v_demosaic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:v_demosaic:1.0 v_demosaic_0 ]
set_property -dict [ list \
CONFIG.ENABLE_ZIPPER_REMOVAL {false} \
CONFIG.SAMPLES_PER_CLOCK {2} \
] $v_demosaic_0
# Create instance: v_frmbuf_wr_0, and set properties
set v_frmbuf_wr_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:v_frmbuf_wr:2.0 v_frmbuf_wr_0 ]
set_property -dict [ list \
CONFIG.AXIMM_DATA_WIDTH {128} \
CONFIG.C_M_AXI_MM_VIDEO_DATA_WIDTH {128} \
CONFIG.HAS_RGB8 {0} \
CONFIG.HAS_RGBX8 {0} \
CONFIG.HAS_UYVY8 {1} \
CONFIG.HAS_Y8 {1} \
CONFIG.HAS_YUV8 {0} \
CONFIG.HAS_YUVX8 {0} \
CONFIG.HAS_YUYV8 {1} \
CONFIG.HAS_Y_UV8 {0} \
CONFIG.HAS_Y_UV8_420 {0} \
CONFIG.MAX_NR_PLANES {1} \
CONFIG.SAMPLES_PER_CLOCK {2} \
] $v_frmbuf_wr_0
# Create instance: v_gamma_lut_0, and set properties
set v_gamma_lut_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:v_gamma_lut:1.0 v_gamma_lut_0 ]
set_property -dict [ list \
CONFIG.SAMPLES_PER_CLOCK {2} \
] $v_gamma_lut_0
# Create instance: v_proc_ss_csc, and set properties
set v_proc_ss_csc [ create_bd_cell -type ip -vlnv xilinx.com:ip:v_proc_ss:2.0 v_proc_ss_csc ]
set_property -dict [ list \
CONFIG.C_COLORSPACE_SUPPORT {2} \
CONFIG.C_CSC_ENABLE_WINDOW {false} \
CONFIG.C_MAX_DATA_WIDTH {8} \
CONFIG.C_SAMPLES_PER_CLK {2} \
CONFIG.C_TOPOLOGY {3} \
] $v_proc_ss_csc
# Create instance: v_proc_ss_scaler, and set properties
set v_proc_ss_scaler [ create_bd_cell -type ip -vlnv xilinx.com:ip:v_proc_ss:2.0 v_proc_ss_scaler ]
set_property -dict [ list \
CONFIG.C_COLORSPACE_SUPPORT {1} \
CONFIG.C_ENABLE_CSC {true} \
CONFIG.C_H_SCALER_TAPS {8} \
CONFIG.C_MAX_DATA_WIDTH {8} \
CONFIG.C_SAMPLES_PER_CLK {2} \
CONFIG.C_TOPOLOGY {0} \
CONFIG.C_V_SCALER_TAPS {8} \
] $v_proc_ss_scaler
# Create instance: vcc, and set properties
set vcc [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 vcc ]
# Create instance: vpss_csc_rst_gpio, and set properties
set vpss_csc_rst_gpio [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 vpss_csc_rst_gpio ]
set_property -dict [ list \
CONFIG.DIN_FROM {6} \
CONFIG.DIN_TO {6} \
CONFIG.DIN_WIDTH {95} \
CONFIG.DOUT_WIDTH {1} \
] $vpss_csc_rst_gpio
# Create instance: vpss_scaler_rst_gpio, and set properties
set vpss_scaler_rst_gpio [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 vpss_scaler_rst_gpio ]
set_property -dict [ list \
CONFIG.DIN_FROM {4} \
CONFIG.DIN_TO {4} \
CONFIG.DIN_WIDTH {95} \
CONFIG.DOUT_WIDTH {1} \
] $vpss_scaler_rst_gpio
# Create interface connections
connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins s_axi_ctrl] [get_bd_intf_pins v_proc_ss_scaler/s_axi_ctrl]
connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins s_axi_CTRL1] [get_bd_intf_pins v_gamma_lut_0/s_axi_CTRL]
connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins s_axi_CTRL2] [get_bd_intf_pins v_frmbuf_wr_0/s_axi_CTRL]
connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins s_axi_ctrl3] [get_bd_intf_pins v_proc_ss_csc/s_axi_ctrl]
connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins mipi_phy_if_0] [get_bd_intf_pins mipi_csi2_rx_subsystem_0/mipi_phy_if]
connect_bd_intf_net -intf_net axi_data_fifo_0_M_AXI [get_bd_intf_pins M_AXI_S2MM] [get_bd_intf_pins axi_data_fifo_0/M_AXI]
connect_bd_intf_net -intf_net axi_interconnect_hpm0_M05_AXI [get_bd_intf_pins csirxss_s_axi] [get_bd_intf_pins mipi_csi2_rx_subsystem_0/csirxss_s_axi]
connect_bd_intf_net -intf_net axis_subset_converter_0_M_AXIS [get_bd_intf_pins axis_subset_converter_0/M_AXIS] [get_bd_intf_pins v_demosaic_0/s_axis_video]
connect_bd_intf_net -intf_net ctrl_1 [get_bd_intf_pins ctrl] [get_bd_intf_pins v_demosaic_0/s_axi_CTRL]
connect_bd_intf_net -intf_net mipi_csi2_rx_subsystem_0_video_out [get_bd_intf_pins axis_subset_converter_0/S_AXIS] [get_bd_intf_pins mipi_csi2_rx_subsystem_0/video_out]
connect_bd_intf_net -intf_net v_demosaic_0_m_axis_video [get_bd_intf_pins v_demosaic_0/m_axis_video] [get_bd_intf_pins v_gamma_lut_0/s_axis_video]
connect_bd_intf_net -intf_net v_frmbuf_wr_0_m_axi_mm_video [get_bd_intf_pins axi_data_fifo_0/S_AXI] [get_bd_intf_pins v_frmbuf_wr_0/m_axi_mm_video]
connect_bd_intf_net -intf_net v_gamma_lut_0_m_axis_video [get_bd_intf_pins v_gamma_lut_0/m_axis_video] [get_bd_intf_pins v_proc_ss_csc/s_axis]
connect_bd_intf_net -intf_net v_proc_ss_0_m_axis [get_bd_intf_pins v_frmbuf_wr_0/s_axis_video] [get_bd_intf_pins v_proc_ss_scaler/m_axis]
connect_bd_intf_net -intf_net v_proc_ss_1_m_axis [get_bd_intf_pins v_proc_ss_csc/m_axis] [get_bd_intf_pins v_proc_ss_scaler/s_axis]
# Create port connections
connect_bd_net -net Din_1 [get_bd_pins Din] [get_bd_pins demosaic_rst_gpio/Din] [get_bd_pins frmbuf_wr_rst_gpio/Din] [get_bd_pins gamma_rst_gpio/Din] [get_bd_pins sensor_rst_gpio/Din] [get_bd_pins vpss_csc_rst_gpio/Din] [get_bd_pins vpss_scaler_rst_gpio/Din]
connect_bd_net -net M06_ARESETN_1 [get_bd_pins video_aresetn] [get_bd_pins axis_subset_converter_0/aresetn] [get_bd_pins mipi_csi2_rx_subsystem_0/video_aresetn]
connect_bd_net -net clk_150mhz [get_bd_pins m_axi_s2mm_aclk] [get_bd_pins axi_data_fifo_0/aclk] [get_bd_pins axis_subset_converter_0/aclk] [get_bd_pins mipi_csi2_rx_subsystem_0/video_aclk] [get_bd_pins v_demosaic_0/ap_clk] [get_bd_pins v_frmbuf_wr_0/ap_clk] [get_bd_pins v_gamma_lut_0/ap_clk] [get_bd_pins v_proc_ss_csc/aclk] [get_bd_pins v_proc_ss_scaler/aclk_axis] [get_bd_pins v_proc_ss_scaler/aclk_ctrl]
connect_bd_net -net clk_50mhz [get_bd_pins s_axi_lite_aclk] [get_bd_pins mipi_csi2_rx_subsystem_0/lite_aclk]
connect_bd_net -net clk_wiz_0_clk_out3 [get_bd_pins dphy_clk_200M] [get_bd_pins mipi_csi2_rx_subsystem_0/dphy_clk_200M]
connect_bd_net -net demosaic_rst_gpio_Dout [get_bd_pins demosaic_rst_gpio/Dout] [get_bd_pins v_demosaic_0/ap_rst_n]
connect_bd_net -net frmbuf_wr_rst_gpio1_Dout [get_bd_pins v_proc_ss_scaler/aresetn_ctrl] [get_bd_pins vpss_scaler_rst_gpio/Dout]
connect_bd_net -net gamma_rst_gpio_Dout [get_bd_pins gamma_rst_gpio/Dout] [get_bd_pins v_gamma_lut_0/ap_rst_n]
connect_bd_net -net mipi_csi2_rx_subsystem_0_csirxss_csi_irq [get_bd_pins csirxss_csi_irq] [get_bd_pins mipi_csi2_rx_subsystem_0/csirxss_csi_irq]
connect_bd_net -net proc_sys_reset_clk50_peripheral_aresetn [get_bd_pins axi_resetn] [get_bd_pins mipi_csi2_rx_subsystem_0/lite_aresetn]
connect_bd_net -net sensor_rst_gpio_Dout [get_bd_pins Dout] [get_bd_pins sensor_rst_gpio/Dout]
connect_bd_net -net tpg_rst_gpio_Dout [get_bd_pins axi_data_fifo_0/aresetn] [get_bd_pins frmbuf_wr_rst_gpio/Dout] [get_bd_pins v_frmbuf_wr_0/ap_rst_n]
connect_bd_net -net v_frmbuf_wr_0_interrupt [get_bd_pins s2mm_introut] [get_bd_pins v_frmbuf_wr_0/interrupt]
connect_bd_net -net vcc_dout [get_bd_pins dout1] [get_bd_pins vcc/dout]
connect_bd_net -net vpss_csc_rst_gpio_Dout [get_bd_pins v_proc_ss_csc/aresetn] [get_bd_pins vpss_csc_rst_gpio/Dout]
# Restore current instance
current_bd_instance $oldCurInst
}
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
variable script_folder
variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
set csi_mipi_phy_if0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:mipi_phy_rtl:1.0 csi_mipi_phy_if0 ]
set csi_mipi_phy_if1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:mipi_phy_rtl:1.0 csi_mipi_phy_if1 ]
set push_buttons_5bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 push_buttons_5bits ]
set sensor0_iic [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 sensor0_iic ]
set sensor1_iic [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 sensor1_iic ]
# Create ports
set sensor0_gpio_flash [ create_bd_port -dir O -from 0 -to 0 sensor0_gpio_flash ]
set sensor0_gpio_rst [ create_bd_port -dir O -from 0 -to 0 sensor0_gpio_rst ]
set sensor0_gpio_spi_cs_n [ create_bd_port -dir O -from 0 -to 0 sensor0_gpio_spi_cs_n ]
set sensor1_gpio_flash [ create_bd_port -dir O -from 0 -to 0 sensor1_gpio_flash ]
set sensor1_gpio_rst [ create_bd_port -dir O -from 0 -to 0 sensor1_gpio_rst ]
set sensor1_gpio_spi_cs_n [ create_bd_port -dir O -from 0 -to 0 sensor1_gpio_spi_cs_n ]
# Create instance: axi_gpio_0, and set properties
set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
set_property -dict [ list \
CONFIG.GPIO_BOARD_INTERFACE {push_buttons_5bits} \
CONFIG.USE_BOARD_FLOW {true} \
] $axi_gpio_0
# Create instance: axi_intc_0, and set properties
set axi_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_0 ]
# Create instance: axi_interconnect_hp1, and set properties
set axi_interconnect_hp1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_hp1 ]
set_property -dict [ list \
CONFIG.ENABLE_ADVANCED_OPTIONS {0} \
CONFIG.M00_HAS_DATA_FIFO {2} \
CONFIG.M00_HAS_REGSLICE {1} \
CONFIG.NUM_MI {1} \
CONFIG.NUM_SI {2} \
CONFIG.S00_HAS_DATA_FIFO {2} \
CONFIG.S00_HAS_REGSLICE {1} \
CONFIG.S01_HAS_DATA_FIFO {2} \
CONFIG.S01_HAS_REGSLICE {1} \
CONFIG.S02_HAS_DATA_FIFO {2} \
CONFIG.S02_HAS_REGSLICE {1} \
CONFIG.S03_HAS_DATA_FIFO {2} \
CONFIG.S03_HAS_REGSLICE {1} \
CONFIG.S04_HAS_DATA_FIFO {2} \
CONFIG.S04_HAS_REGSLICE {1} \
CONFIG.S05_HAS_DATA_FIFO {2} \
CONFIG.S05_HAS_REGSLICE {1} \
CONFIG.S06_HAS_DATA_FIFO {2} \
CONFIG.S06_HAS_REGSLICE {1} \
CONFIG.STRATEGY {2} \
CONFIG.SYNCHRONIZATION_STAGES {2} \
] $axi_interconnect_hp1
# Create instance: axi_interconnect_hpm0, and set properties
set axi_interconnect_hpm0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_hpm0 ]
set_property -dict [ list \
CONFIG.ENABLE_ADVANCED_OPTIONS {0} \
CONFIG.NUM_MI {6} \
CONFIG.STRATEGY {1} \
CONFIG.SYNCHRONIZATION_STAGES {2} \
] $axi_interconnect_hpm0
# Create instance: axi_interconnect_hpm1, and set properties
set axi_interconnect_hpm1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_hpm1 ]
set_property -dict [ list \
CONFIG.ENABLE_ADVANCED_OPTIONS {0} \
CONFIG.M00_HAS_REGSLICE {1} \
CONFIG.M01_HAS_REGSLICE {1} \
CONFIG.M02_HAS_REGSLICE {1} \
CONFIG.M03_HAS_REGSLICE {1} \
CONFIG.M04_HAS_REGSLICE {1} \
CONFIG.M05_HAS_REGSLICE {1} \
CONFIG.M06_HAS_REGSLICE {1} \
CONFIG.M07_HAS_REGSLICE {1} \
CONFIG.M08_HAS_REGSLICE {1} \
CONFIG.M09_HAS_REGSLICE {1} \
CONFIG.M10_HAS_REGSLICE {1} \
CONFIG.NUM_MI {19} \
CONFIG.S00_HAS_REGSLICE {1} \
CONFIG.STRATEGY {1} \
CONFIG.SYNCHRONIZATION_STAGES {2} \
] $axi_interconnect_hpm1
# Create instance: clk_wiz_1, and set properties
set clk_wiz_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.4 clk_wiz_1 ]
set_property -dict [ list \
CONFIG.CLKIN1_JITTER_PS {200.02} \
CONFIG.CLKOUT1_DRIVES {Buffer} \
CONFIG.CLKOUT1_JITTER {163.726} \
CONFIG.CLKOUT1_PHASE_ERROR {154.695} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {50.000} \
CONFIG.CLKOUT2_DRIVES {Buffer} \
CONFIG.CLKOUT2_JITTER {148.390} \
CONFIG.CLKOUT2_PHASE_ERROR {154.695} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {75.000} \
CONFIG.CLKOUT2_USED {true} \
CONFIG.CLKOUT3_DRIVES {Buffer} \
CONFIG.CLKOUT3_JITTER {129.940} \
CONFIG.CLKOUT3_PHASE_ERROR {154.695} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {150.000} \
CONFIG.CLKOUT3_USED {true} \
CONFIG.CLKOUT4_DRIVES {Buffer} \
CONFIG.CLKOUT4_JITTER {116.512} \
CONFIG.CLKOUT4_PHASE_ERROR {154.695} \
CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {300.000} \
CONFIG.CLKOUT4_USED {true} \
CONFIG.CLKOUT5_DRIVES {Buffer} \
CONFIG.CLKOUT5_JITTER {124.151} \
CONFIG.CLKOUT5_PHASE_ERROR {154.695} \
CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {200.000} \
CONFIG.CLKOUT5_USED {true} \
CONFIG.CLKOUT6_DRIVES {Buffer} \
CONFIG.CLKOUT7_DRIVES {Buffer} \
CONFIG.MMCM_CLKFBOUT_MULT_F {24.000} \
CONFIG.MMCM_CLKIN1_PERIOD {20.002} \
CONFIG.MMCM_CLKIN2_PERIOD {10.0} \
CONFIG.MMCM_CLKOUT0_DIVIDE_F {24.000} \
CONFIG.MMCM_CLKOUT1_DIVIDE {16} \
CONFIG.MMCM_CLKOUT2_DIVIDE {8} \
CONFIG.MMCM_CLKOUT3_DIVIDE {4} \
CONFIG.MMCM_CLKOUT4_DIVIDE {6} \
CONFIG.MMCM_DIVCLK_DIVIDE {1} \
CONFIG.NUM_OUT_CLKS {5} \
CONFIG.PHASESHIFT_MODE {LATENCY} \
CONFIG.PRIM_SOURCE {No_buffer} \
CONFIG.USE_INCLK_SWITCHOVER {false} \
CONFIG.USE_RESET {false} \
] $clk_wiz_1
# Create instance: interrupts0, and set properties
set interrupts0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 interrupts0 ]
set_property -dict [ list \
CONFIG.NUM_PORTS {1} \
] $interrupts0
# Create instance: mipi_csi2_rx0
create_hier_cell_mipi_csi2_rx0 [current_bd_instance .] mipi_csi2_rx0
# Create instance: mipi_csi2_rx1
create_hier_cell_mipi_csi2_rx1 [current_bd_instance .] mipi_csi2_rx1
# Create instance: platform_interrupts, and set properties
set platform_interrupts [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 platform_interrupts ]
set_property -dict [ list \
CONFIG.NUM_PORTS {6} \
] $platform_interrupts
# Create instance: proc_sys_reset_1, and set properties
set proc_sys_reset_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1 ]
set_property -dict [ list \
CONFIG.C_AUX_RESET_HIGH {0} \
] $proc_sys_reset_1
# Create instance: sensor0_iic, and set properties
set sensor0_iic [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 sensor0_iic ]
set_property -dict [ list \
CONFIG.IIC_FREQ_KHZ {400} \
] $sensor0_iic
# Create instance: sensor1_iic, and set properties
set sensor1_iic [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 sensor1_iic ]
set_property -dict [ list \
CONFIG.IIC_FREQ_KHZ {400} \
] $sensor1_iic
# Create instance: zynq_ultra_ps_e_0, and set properties
set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.1 zynq_ultra_ps_e_0 ]
set_property -dict [ list \
CONFIG.CAN0_BOARD_INTERFACE {custom} \
CONFIG.CAN1_BOARD_INTERFACE {custom} \
CONFIG.CSU_BOARD_INTERFACE {custom} \
CONFIG.DP_BOARD_INTERFACE {custom} \
CONFIG.GEM0_BOARD_INTERFACE {custom} \
CONFIG.GEM1_BOARD_INTERFACE {custom} \
CONFIG.GEM2_BOARD_INTERFACE {custom} \
CONFIG.GEM3_BOARD_INTERFACE {custom} \
CONFIG.GPIO_BOARD_INTERFACE {custom} \
CONFIG.IIC0_BOARD_INTERFACE {custom} \
CONFIG.IIC1_BOARD_INTERFACE {custom} \
CONFIG.NAND_BOARD_INTERFACE {custom} \
CONFIG.PCIE_BOARD_INTERFACE {custom} \
CONFIG.PJTAG_BOARD_INTERFACE {custom} \
CONFIG.PMU_BOARD_INTERFACE {custom} \
CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \
CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \
CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \
CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
CONFIG.PSU_IMPORT_BOARD_PRESET {} \
CONFIG.PSU_MIO_0_DIRECTION {out} \
CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_0_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_0_SLEW {slow} \
CONFIG.PSU_MIO_10_DIRECTION {inout} \
CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_10_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_10_SLEW {slow} \
CONFIG.PSU_MIO_11_DIRECTION {inout} \
CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_11_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_11_SLEW {slow} \
CONFIG.PSU_MIO_12_DIRECTION {out} \
CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_12_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_12_SLEW {slow} \
CONFIG.PSU_MIO_13_DIRECTION {inout} \
CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_13_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_13_SLEW {slow} \
CONFIG.PSU_MIO_14_DIRECTION {inout} \
CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_14_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_14_SLEW {slow} \
CONFIG.PSU_MIO_15_DIRECTION {inout} \
CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_15_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_15_SLEW {slow} \
CONFIG.PSU_MIO_16_DIRECTION {inout} \
CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_16_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_16_SLEW {slow} \
CONFIG.PSU_MIO_17_DIRECTION {inout} \
CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_17_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_17_SLEW {slow} \
CONFIG.PSU_MIO_18_DIRECTION {in} \
CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_18_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_18_SLEW {slow} \
CONFIG.PSU_MIO_19_DIRECTION {out} \
CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_19_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_19_SLEW {slow} \
CONFIG.PSU_MIO_1_DIRECTION {inout} \
CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_1_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_1_SLEW {slow} \
CONFIG.PSU_MIO_20_DIRECTION {out} \
CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_20_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_20_SLEW {slow} \
CONFIG.PSU_MIO_21_DIRECTION {in} \
CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_21_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_21_SLEW {slow} \
CONFIG.PSU_MIO_22_DIRECTION {inout} \
CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_22_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_22_SLEW {slow} \
CONFIG.PSU_MIO_23_DIRECTION {inout} \
CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_23_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_23_SLEW {slow} \
CONFIG.PSU_MIO_24_DIRECTION {out} \
CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
CONFIG.PSU_MIO_24_INPUT_TYPE {schmitt} \
CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \
CONFIG.PSU_MIO_24_SLEW {slow} \