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Simulation of full HDL #7

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hyanki opened this issue Jun 9, 2020 · 3 comments
Open

Simulation of full HDL #7

hyanki opened this issue Jun 9, 2020 · 3 comments

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@hyanki
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hyanki commented Jun 9, 2020

Hi
i have doubt that can i simulate complete design on modelsim?
regards
hyanki
@hyanki
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hyanki commented Jun 10, 2020

Hi jshi
what are the steps to simulate in icarus verilog.
Regards
Hyanki

@hyanki
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hyanki commented Jul 23, 2020

Hi i
In demodulater.v file why scaling factor is taken 1024 though input is in 16 bit?
What is data format of IQ in 16bit?
Regards
J S Hyanki

@JiaoXianjun
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if you like, you can simulate via Vivado. our reference: open-sdr/openwifi-hw#17

jhshi pushed a commit that referenced this issue Jan 29, 2023
@JiaoXianjun
Merge pull request #7 from open-sdr/pre-release
5837538 
Pre release
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@JiaoXianjun @hyanki