diff --git a/README.md b/README.md
index d19fb17a..586194bc 100644
--- a/README.md
+++ b/README.md
@@ -32,8 +32,6 @@ TODO List:
 
 ### vfrstp.b/h
 
-### vsignconv.b/h/w/d
-
 ### vfsub.s/d
 
 ### vfmul.s/d
diff --git a/code/gen_impl.py b/code/gen_impl.py
index 9c3214ba..4d0e6897 100644
--- a/code/gen_impl.py
+++ b/code/gen_impl.py
@@ -449,6 +449,13 @@
             file=f,
         )
         print(f"}}", file=f)
+    with open(f"vsigncov_{width}.h", "w") as f:
+        print(f"for (int i = 0;i < {128 // w};i++) {{", file=f)
+        print(
+            f"  dst.{m}[i] = (a.{m}[i] == 0) ? 0 : ((s{w})a.{m}[i] > 0 ? b.{m}[i] : -b.{m}[i]);",
+            file=f,
+        )
+        print(f"}}", file=f)
 
 for width in ["s", "d"]:
     m = members_fp[width]
diff --git a/code/gen_tb.py b/code/gen_tb.py
index b1be5545..8291e1cc 100644
--- a/code/gen_tb.py
+++ b/code/gen_tb.py
@@ -83,6 +83,7 @@
     "vreplve": (widths_signed, "v128 a, int idx", [0, 1]),
     "vreplvei": (widths_signed, "v128 a, int idx", [0, 1]),
     "vsadd": (widths_all, "v128 a, v128 b"),
+    "vsigncov": (widths_signed, "v128 a, v128 b"),
     "vssub": (widths_all, "v128 a, v128 b"),
     "vseq": (widths_signed, "v128 a, v128 b"),
     "vsll": (widths_signed, "v128 a, v128 b"),
diff --git a/code/vsigncov_b.cpp b/code/vsigncov_b.cpp
new file mode 100644
index 00000000..1f1d3120
--- /dev/null
+++ b/code/vsigncov_b.cpp
@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vsigncov_b(v128 a, v128 b) {
+  v128 dst;
+#include "vsigncov_b.h"
+  return dst;
+}
+
+void test() { FUZZ2(vsigncov_b); }
diff --git a/code/vsigncov_b.h b/code/vsigncov_b.h
new file mode 100644
index 00000000..6942bfcc
--- /dev/null
+++ b/code/vsigncov_b.h
@@ -0,0 +1,4 @@
+for (int i = 0; i < 16; i++) {
+  dst.byte[i] =
+      (a.byte[i] == 0) ? 0 : ((s8)a.byte[i] > 0 ? b.byte[i] : -b.byte[i]);
+}
diff --git a/code/vsigncov_d.cpp b/code/vsigncov_d.cpp
new file mode 100644
index 00000000..79f776fa
--- /dev/null
+++ b/code/vsigncov_d.cpp
@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vsigncov_d(v128 a, v128 b) {
+  v128 dst;
+#include "vsigncov_d.h"
+  return dst;
+}
+
+void test() { FUZZ2(vsigncov_d); }
diff --git a/code/vsigncov_d.h b/code/vsigncov_d.h
new file mode 100644
index 00000000..37a814fd
--- /dev/null
+++ b/code/vsigncov_d.h
@@ -0,0 +1,4 @@
+for (int i = 0; i < 2; i++) {
+  dst.dword[i] =
+      (a.dword[i] == 0) ? 0 : ((s64)a.dword[i] > 0 ? b.dword[i] : -b.dword[i]);
+}
diff --git a/code/vsigncov_h.cpp b/code/vsigncov_h.cpp
new file mode 100644
index 00000000..6330b0cc
--- /dev/null
+++ b/code/vsigncov_h.cpp
@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vsigncov_h(v128 a, v128 b) {
+  v128 dst;
+#include "vsigncov_h.h"
+  return dst;
+}
+
+void test() { FUZZ2(vsigncov_h); }
diff --git a/code/vsigncov_h.h b/code/vsigncov_h.h
new file mode 100644
index 00000000..6abe43dc
--- /dev/null
+++ b/code/vsigncov_h.h
@@ -0,0 +1,4 @@
+for (int i = 0; i < 8; i++) {
+  dst.half[i] =
+      (a.half[i] == 0) ? 0 : ((s16)a.half[i] > 0 ? b.half[i] : -b.half[i]);
+}
diff --git a/code/vsigncov_w.cpp b/code/vsigncov_w.cpp
new file mode 100644
index 00000000..f350791b
--- /dev/null
+++ b/code/vsigncov_w.cpp
@@ -0,0 +1,9 @@
+#include "common.h"
+
+v128 vsigncov_w(v128 a, v128 b) {
+  v128 dst;
+#include "vsigncov_w.h"
+  return dst;
+}
+
+void test() { FUZZ2(vsigncov_w); }
diff --git a/code/vsigncov_w.h b/code/vsigncov_w.h
new file mode 100644
index 00000000..1013ccee
--- /dev/null
+++ b/code/vsigncov_w.h
@@ -0,0 +1,4 @@
+for (int i = 0; i < 4; i++) {
+  dst.word[i] =
+      (a.word[i] == 0) ? 0 : ((s32)a.word[i] > 0 ? b.word[i] : -b.word[i]);
+}
diff --git a/docs/lsx/misc.md b/docs/lsx/misc.md
index 6b6ca5a5..6c9fa46d 100644
--- a/docs/lsx/misc.md
+++ b/docs/lsx/misc.md
@@ -43,4 +43,9 @@
 {{ vreplvei('b') }}
 {{ vreplvei('h') }}
 {{ vreplvei('w') }}
-{{ vreplvei('d') }}
\ No newline at end of file
+{{ vreplvei('d') }}
+
+{{ vsigncov('b') }}
+{{ vsigncov('h') }}
+{{ vsigncov('w') }}
+{{ vsigncov('d') }}
\ No newline at end of file
diff --git a/main.py b/main.py
index 64b8658d..809a60b8 100644
--- a/main.py
+++ b/main.py
@@ -752,4 +752,13 @@ def vreplvei(name):
             intrinsic=f"__m128i __lsx_vreplvei_{name} (__m128i a, imm0_{imm_upper} idx)",
             instr=f"vreplvei.{name} vr, vr, imm",
             desc=f"Repeat the element in lane `idx` of `a` to whole vector.",
+        )
+
+    @env.macro
+    def vsigncov(name):
+        width = widths[name]
+        return instruction(
+            intrinsic=f"__m128i __lsx_vsigncov_{name} (__m128i a, __m128i b)",
+            instr=f"vsigncov.{name} vr, vr, vr",
+            desc=f"If the {width}-bit element in `a` equals to zero, set the result to zero. If the signed {width}-bit element in `a` is posiive, copy element in `b` to result. Otherwise, copy negated element in `b` to result.",
         )
\ No newline at end of file