diff --git a/.gitignore b/.gitignore index 5ba6ba1..0c21cbf 100644 --- a/.gitignore +++ b/.gitignore @@ -33,6 +33,10 @@ # Folders *.vscode/ +quartus/db +quartus/incremental_db +quartus/output_files +quartus/simulation # Software (alpha) *.asm diff --git a/quartus/MARVIN.qpf b/quartus/MARVIN.qpf new file mode 100644 index 0000000..a78a03b --- /dev/null +++ b/quartus/MARVIN.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2023 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition +# Date created = 16:43:21 Oktober 27, 2023 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "22.1" +DATE = "16:43:21 Oktober 27, 2023" + +# Revisions + +PROJECT_REVISION = "marvin" diff --git a/quartus/marvin.qsf b/quartus/marvin.qsf new file mode 100644 index 0000000..83b7e6d --- /dev/null +++ b/quartus/marvin.qsf @@ -0,0 +1,442 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2023 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition +# Date created = 16:43:21 Oktober 27, 2023 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# marvin_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Intel recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name TOP_LEVEL_ENTITY marvin +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016" +set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.2 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (SystemVerilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan +set_global_assignment -name SYSTEMVERILOG_FILE ../src/pkg.sv +set_global_assignment -name SYSTEMVERILOG_FILE ../src/marvin.sv +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_N5 -to clk_10 +set_location_assignment PIN_P11 -to clk1_50 +set_location_assignment PIN_N14 -to clk2_50 +set_location_assignment PIN_F16 -to ardu_rst_ +set_location_assignment PIN_AB5 -to ardu_gpio[0] +set_location_assignment PIN_AB6 -to ardu_gpio[1] +set_location_assignment PIN_AB7 -to ardu_gpio[2] +set_location_assignment PIN_AB8 -to ardu_gpio[3] +set_location_assignment PIN_AB9 -to ardu_gpio[4] +set_location_assignment PIN_Y10 -to ardu_gpio[5] +set_location_assignment PIN_AA11 -to ardu_gpio[6] +set_location_assignment PIN_AA12 -to ardu_gpio[7] +set_location_assignment PIN_AB17 -to ardu_gpio[8] +set_location_assignment PIN_AA17 -to ardu_gpio[9] +set_location_assignment PIN_AB19 -to ardu_gpio[10] +set_location_assignment PIN_AA19 -to ardu_gpio[11] +set_location_assignment PIN_Y19 -to ardu_gpio[12] +set_location_assignment PIN_AB20 -to ardu_gpio[13] +set_location_assignment PIN_AB21 -to ardu_gpio[14] +set_location_assignment PIN_AA20 -to ardu_gpio[15] +set_location_assignment PIN_U17 -to dram_addr[0] +set_location_assignment PIN_W19 -to dram_addr[1] +set_location_assignment PIN_V18 -to dram_addr[2] +set_location_assignment PIN_U18 -to dram_addr[3] +set_location_assignment PIN_U19 -to dram_addr[4] +set_location_assignment PIN_T18 -to dram_addr[5] +set_location_assignment PIN_T19 -to dram_addr[6] +set_location_assignment PIN_R18 -to dram_addr[7] +set_location_assignment PIN_P18 -to dram_addr[8] +set_location_assignment PIN_P19 -to dram_addr[9] +set_location_assignment PIN_T20 -to dram_addr[10] +set_location_assignment PIN_P20 -to dram_addr[11] +set_location_assignment PIN_R20 -to dram_addr[12] +set_location_assignment PIN_T21 -to dram_bank[0] +set_location_assignment PIN_T22 -to dram_bank[1] +set_location_assignment PIN_U21 -to dram_cas_ +set_location_assignment PIN_N22 -to dram_cke +set_location_assignment PIN_L14 -to dram_clk +set_location_assignment PIN_U20 -to dram_cs_ +set_location_assignment PIN_Y21 -to dram_dq[0] +set_location_assignment PIN_Y20 -to dram_dq[1] +set_location_assignment PIN_AA22 -to dram_dq[2] +set_location_assignment PIN_AA21 -to dram_dq[3] +set_location_assignment PIN_Y22 -to dram_dq[4] +set_location_assignment PIN_W22 -to dram_dq[5] +set_location_assignment PIN_W20 -to dram_dq[6] +set_location_assignment PIN_V21 -to dram_dq[7] +set_location_assignment PIN_P21 -to dram_dq[8] +set_location_assignment PIN_J22 -to dram_dq[9] +set_location_assignment PIN_H21 -to dram_dq[10] +set_location_assignment PIN_H22 -to dram_dq[11] +set_location_assignment PIN_G22 -to dram_dq[12] +set_location_assignment PIN_G20 -to dram_dq[13] +set_location_assignment PIN_G19 -to dram_dq[14] +set_location_assignment PIN_F22 -to dram_dq[15] +set_location_assignment PIN_J21 -to dram_qdm[1] +set_location_assignment PIN_V22 -to dram_qdm[0] +set_location_assignment PIN_U22 -to dram_ras_ +set_location_assignment PIN_V20 -to dram_re +set_location_assignment PIN_V10 -to gpio[0] +set_location_assignment PIN_V9 -to gpio[2] +set_location_assignment PIN_W10 -to gpio[1] +set_location_assignment PIN_W9 -to gpio[3] +set_location_assignment PIN_V8 -to gpio[4] +set_location_assignment PIN_W8 -to gpio[5] +set_location_assignment PIN_V7 -to gpio[6] +set_location_assignment PIN_W7 -to gpio[7] +set_location_assignment PIN_W6 -to gpio[8] +set_location_assignment PIN_V5 -to gpio[9] +set_location_assignment PIN_W5 -to gpio[10] +set_location_assignment PIN_AA15 -to gpio[11] +set_location_assignment PIN_AA14 -to gpio[12] +set_location_assignment PIN_W13 -to gpio[13] +set_location_assignment PIN_W12 -to gpio[14] +set_location_assignment PIN_AB13 -to gpio[15] +set_location_assignment PIN_AB12 -to gpio[16] +set_location_assignment PIN_Y11 -to gpio[17] +set_location_assignment PIN_AB11 -to gpio[18] +set_location_assignment PIN_W11 -to gpio[19] +set_location_assignment PIN_AB10 -to gpio[20] +set_location_assignment PIN_AA10 -to gpio[21] +set_location_assignment PIN_AA9 -to gpio[22] +set_location_assignment PIN_Y8 -to gpio[23] +set_location_assignment PIN_AA8 -to gpio[24] +set_location_assignment PIN_Y7 -to gpio[25] +set_location_assignment PIN_AA7 -to gpio[26] +set_location_assignment PIN_Y6 -to gpio[27] +set_location_assignment PIN_AA6 -to gpio[28] +set_location_assignment PIN_Y5 -to gpio[29] +set_location_assignment PIN_AA5 -to gpio[30] +set_location_assignment PIN_Y4 -to gpio[31] +set_location_assignment PIN_AB3 -to gpio[32] +set_location_assignment PIN_Y3 -to gpio[33] +set_location_assignment PIN_AB2 -to gpio[34] +set_location_assignment PIN_AA2 -to gpio[35] +set_location_assignment PIN_V12 -to gsensor_sdo +set_location_assignment PIN_V11 -to gsensor_sdi +set_location_assignment PIN_AB15 -to gsensor_sclk +set_location_assignment PIN_Y13 -to gsensor_int[2] +set_location_assignment PIN_Y14 -to gsensor_int[1] +set_location_assignment PIN_AB16 -to gsensor_cs_ +set_location_assignment PIN_C14 -to hex[0][0] +set_location_assignment PIN_E15 -to hex[0][1] +set_location_assignment PIN_C15 -to hex[0][2] +set_location_assignment PIN_C16 -to hex[0][3] +set_location_assignment PIN_E16 -to hex[0][4] +set_location_assignment PIN_D17 -to hex[0][5] +set_location_assignment PIN_C17 -to hex[0][6] +set_location_assignment PIN_D15 -to hex[0][7] +set_location_assignment PIN_C18 -to hex[1][0] +set_location_assignment PIN_D18 -to hex[1][1] +set_location_assignment PIN_E18 -to hex[1][2] +set_location_assignment PIN_B16 -to hex[1][3] +set_location_assignment PIN_A17 -to hex[1][4] +set_location_assignment PIN_A18 -to hex[1][5] +set_location_assignment PIN_B17 -to hex[1][6] +set_location_assignment PIN_A16 -to hex[1][7] +set_location_assignment PIN_B20 -to hex[2][0] +set_location_assignment PIN_A20 -to hex[2][1] +set_location_assignment PIN_B19 -to hex[2][2] +set_location_assignment PIN_A21 -to hex[2][3] +set_location_assignment PIN_B21 -to hex[2][4] +set_location_assignment PIN_C22 -to hex[2][5] +set_location_assignment PIN_B22 -to hex[2][6] +set_location_assignment PIN_A19 -to hex[2][7] +set_location_assignment PIN_F21 -to hex[3][0] +set_location_assignment PIN_E22 -to hex[3][1] +set_location_assignment PIN_E21 -to hex[3][2] +set_location_assignment PIN_C19 -to hex[3][3] +set_location_assignment PIN_C20 -to hex[3][4] +set_location_assignment PIN_D19 -to hex[3][5] +set_location_assignment PIN_E17 -to hex[3][6] +set_location_assignment PIN_D22 -to hex[3][7] +set_location_assignment PIN_F18 -to hex[4][0] +set_location_assignment PIN_E20 -to hex[4][1] +set_location_assignment PIN_E19 -to hex[4][2] +set_location_assignment PIN_J18 -to hex[4][3] +set_location_assignment PIN_H19 -to hex[4][4] +set_location_assignment PIN_F19 -to hex[4][5] +set_location_assignment PIN_F20 -to hex[4][6] +set_location_assignment PIN_F17 -to hex[4][7] +set_location_assignment PIN_J20 -to hex[5][0] +set_location_assignment PIN_K20 -to hex[5][1] +set_location_assignment PIN_L18 -to hex[5][2] +set_location_assignment PIN_N18 -to hex[5][3] +set_location_assignment PIN_M20 -to hex[5][4] +set_location_assignment PIN_N19 -to hex[5][5] +set_location_assignment PIN_N20 -to hex[5][6] +set_location_assignment PIN_L19 -to hex[5][7] +set_location_assignment PIN_A7 -to key[1] +set_location_assignment PIN_B8 -to key[0] +set_location_assignment PIN_B11 -to ledr[9] +set_location_assignment PIN_A11 -to ledr[8] +set_location_assignment PIN_D14 -to ledr[7] +set_location_assignment PIN_E14 -to ledr[6] +set_location_assignment PIN_C13 -to ledr[5] +set_location_assignment PIN_D13 -to ledr[4] +set_location_assignment PIN_B10 -to ledr[3] +set_location_assignment PIN_A10 -to ledr[2] +set_location_assignment PIN_A9 -to ledr[1] +set_location_assignment PIN_A8 -to ledr[0] +set_location_assignment PIN_F15 -to sw[9] +set_location_assignment PIN_B14 -to sw[8] +set_location_assignment PIN_A14 -to sw[7] +set_location_assignment PIN_A13 -to sw[6] +set_location_assignment PIN_B12 -to sw[5] +set_location_assignment PIN_A12 -to sw[4] +set_location_assignment PIN_C12 -to sw[3] +set_location_assignment PIN_D12 -to sw[2] +set_location_assignment PIN_C11 -to sw[1] +set_location_assignment PIN_C10 -to sw[0] +set_location_assignment PIN_AA1 -to vga_color.red[0] +set_location_assignment PIN_V1 -to vga_color.red[1] +set_location_assignment PIN_Y2 -to vga_color.red[2] +set_location_assignment PIN_Y1 -to vga_color.red[3] +set_location_assignment PIN_W1 -to vga_color.green[0] +set_location_assignment PIN_T2 -to vga_color.green[1] +set_location_assignment PIN_R2 -to vga_color.green[2] +set_location_assignment PIN_R1 -to vga_color.green[3] +set_location_assignment PIN_P1 -to vga_color.blue[0] +set_location_assignment PIN_T1 -to vga_color.blue[1] +set_location_assignment PIN_P4 -to vga_color.blue[2] +set_location_assignment PIN_N2 -to vga_color.blue[3] +set_location_assignment PIN_N3 -to vga_hs +set_location_assignment PIN_N1 -to vga_vs +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ardu_gpio[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ardu_gpio[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ardu_gpio[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ardu_gpio[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ardu_gpio[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ardu_gpio[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ardu_gpio[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ardu_gpio[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ardu_gpio[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ardu_gpio[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ardu_gpio[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ardu_gpio[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ardu_gpio[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ardu_gpio[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ardu_gpio[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ardu_gpio[0] +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to ardu_rst_ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk1_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_10 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_addr[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_addr[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_addr[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_addr[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_addr[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_addr[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_addr[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_addr[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_addr[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_addr[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_addr[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_addr[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_addr[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_bank[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_bank[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_cas_ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_cke +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_cs_ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_dq[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_dq[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_dq[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_dq[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_dq[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_dq[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_dq[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_dq[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_dq[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_dq[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_dq[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_dq[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_dq[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_dq[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_dq[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_dq[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_qdm[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_qdm[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_ras_ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dram_re +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[35] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gsensor_cs_ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gsensor_int[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gsensor_int[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gsensor_sclk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gsensor_sdi +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gsensor_sdo +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[0][0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[0][1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[0][2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[0][3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[0][4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[0][5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[0][6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[0][7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[1][0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[1][1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[1][2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[1][3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[1][4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[1][5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[1][6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[1][7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[2][0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[2][1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[2][2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[2][3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[2][4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[2][5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[2][6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[2][7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[3][0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[3][1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[3][2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[3][3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[3][4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[3][5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[3][6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[3][7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[4][0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[4][1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[4][2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[4][3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[4][4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[4][5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[4][6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[4][7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[5][0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[5][1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[5][2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[5][3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[5][4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[5][5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[5][6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hex[5][7] +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to key[1] +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to key[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ledr[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ledr[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ledr[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ledr[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ledr[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ledr[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ledr[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ledr[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ledr[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ledr[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sw[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sw[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sw[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sw[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sw[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sw[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sw[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sw[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sw[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sw[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_color.blue[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_color.blue[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_color.blue[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_color.blue[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_color.green[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_color.green[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_color.green[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_color.green[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_color.red[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_color.red[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_color.red[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_color.red[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_hs +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_vs +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to key +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/quartus/marvin.sdc b/quartus/marvin.sdc new file mode 100644 index 0000000..f183bb1 --- /dev/null +++ b/quartus/marvin.sdc @@ -0,0 +1,83 @@ +#************************************************************** +# This .sdc file is created by Terasic Tool. +# Users are recommended to modify this file to match users logic. +#************************************************************** + +#************************************************************** +# Create Clock +#************************************************************** +create_clock -period "10.0 MHz" [get_ports clk_10] +create_clock -period "50.0 MHz" [get_ports clk1_50] +create_clock -period "50.0 MHz" [get_ports clk2_50] + +#************************************************************** +# Create Generated Clock +#************************************************************** +derive_pll_clocks + + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** +derive_clock_uncertainty + + + +#************************************************************** +# Set Input Delay +#************************************************************** + + + +#************************************************************** +# Set Output Delay +#************************************************************** + + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + + + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + + + +#************************************************************** +# Set Load +#************************************************************** diff --git a/src/marvin.sv b/src/marvin.sv new file mode 100644 index 0000000..beac2e4 --- /dev/null +++ b/src/marvin.sv @@ -0,0 +1,89 @@ +/* + Project: MARVIN + Sector: TOP + Entity: marvin + Summary: Toplevel design file + Device: terasIC® DE10-Lite Development Board with Altera® MAX 10 10M50DAF484C7G FPGA + Authors: Leonard Pfeiffer +*/ + +import pkg::*; + +module marvin( + // ===== CLOCKS ====================================================== + input clk_10, // 10MHz clock (for ADCs) 3.3V LVTTL + + input clk1_50, // 50MHz primary clock 3.3V LVTTL + + input clk2_50, // 50MHz secondary clock 3.3V LVTTL + + // ===== BASIC IN ==================================================== + input [1:0] key, // 2 push buttons 3.3V Schmitt + + input [9:0] sw, // 10 toggle switches 3.3V LVTTL + + // ===== BASIC OUT =================================================== + output [9:0] ledr, // 10 red leds 3.3V LVTTL + + output [5:0][7:0] hex, // 6x8-element hex display 3.3V LVTTL + + // ===== BASIC IO ==================================================== + inout [35:0] gpio, // 36 pin expansion header 3.3V LVTTL + + // ===== ARDUINO ===================================================== + inout [15:0] ardu_gpio, // 16 pin arduino connector 3.3V LVTTL + inout ardu_rst_, // Arduino reset 3.3V Schmitt + + // ===== VGA ========================================================= + output pkg::color vga_color, // 3x4 VGA color output 3.3V LVTTL + output vga_hs, // VGA horizontal sync 3.3V LVTTL + output vga_vs, // VGA vertical sync 3.3V LVTTL + + // ===== SDRAM ======================================================= + output [12:0] dram_addr, // 13 bit SDRAM address 3.3V LVTTL + inout [15:0] dram_dq, // 16 bit SDRAM data bus 3.3V LVTTL + output [1:0] dram_bank, // 2 bit SDRAM bank address 3.3V LVTTL + output [1:0] dram_qdm, // 2 bit SDRAM bit mask 3.3V LVTTL + output dram_ras_, // SDRAM row address strobe 3.3V LVTTL + output dram_cas_, // SDRAM col address strobe 3.3V LVTTL + output dram_cke, // SDRAM clock enable 3.3V LVTTL + output dram_clk, // 200MHz SDRAM clock 3.3V LVTTL + output dram_re, // SDRAM read enable 3.3V LVTTL + output dram_cs_, // SDRAM chip select 3.3V LVTTL + + // ===== GSENSOR ===================================================== + inout gsensor_sdi, // I2C D or SPI I 4 / IO 3 3.3V LVTTL + inout gsensor_sdo, // SPI O 4 / Alt I2C Addr 3.3V LVTTL + output gsensor_cs_, // I2C / SPI Mode 3.3V LVTTL + output gsensor_sclk, // I2C / SPI serial clock 3.3V LVTTL + input [2:1] gsensor_int // GSensor interrupt pins 3.3V LVTTL +); + assign ledr = '0; + assign hex = '0; + assign gpio = '0; + assign ardu_gpio = '0; + assign ardu_rst_ = 0; + assign vga_color.red = '0; + assign vga_color.green = '0; + assign vga_color.blue = '0; + assign vga_hs = 0; + assign vga_vs = 0; + + // ===== SDRAM ============ + assign dram_addr = '0; + assign dram_dq = '0; + assign dram_bank = '0; + assign dram_qdm = '0; + assign dram_cas_ = 0; + assign dram_ras_ = 0; + assign dram_cke = 0; + assign dram_clk = 0; + assign dram_re = 0; + assign dram_cs_ = 1; + + // ===== GSENSOR ========== + assign gsensor_sdi = 0; + assign gsensor_sdo = 0; + assign gsensor_cs_ = 1; + assign gsensor_sclk = 0; +endmodule diff --git a/src/pkg.sv b/src/pkg.sv new file mode 100644 index 0000000..7fbe775 --- /dev/null +++ b/src/pkg.sv @@ -0,0 +1,12 @@ +/* + Project: MARVIN + Sector: TOP + Entity: pkg + Summary: Toplevel package file + Device: terasIC® DE10-Lite Development Board with Altera® MAX 10 10M50DAF484C7G FPGA + Authors: Leonard Pfeiffer +*/ + +package pkg; + typedef struct { logic [3:0] red, green, blue; } color; +endpackage \ No newline at end of file