From c069df9600fe00aa3fa8f0a37ba93fe11a73e731 Mon Sep 17 00:00:00 2001 From: jon011235 <148149771+jon011235@users.noreply.github.com> Date: Wed, 25 Oct 2023 20:12:08 +0200 Subject: [PATCH 1/5] Rename verilog-compiler.vhdl to verilog-compiler.yml --- .github/actions/{verilog-compiler.vhdl => verilog-compiler.yml} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename .github/actions/{verilog-compiler.vhdl => verilog-compiler.yml} (100%) diff --git a/.github/actions/verilog-compiler.vhdl b/.github/actions/verilog-compiler.yml similarity index 100% rename from .github/actions/verilog-compiler.vhdl rename to .github/actions/verilog-compiler.yml From 52e9688bcc9d63e3545202172f026295b444292b Mon Sep 17 00:00:00 2001 From: Leonard Pfeiffer Date: Wed, 25 Oct 2023 20:55:27 +0200 Subject: [PATCH 2/5] Rename .github/actions to .github/workflows --- .github/{actions => workflows}/verilog-compiler.yml | 0 .github/{actions => workflows}/verilog-linter.yml | 0 2 files changed, 0 insertions(+), 0 deletions(-) rename .github/{actions => workflows}/verilog-compiler.yml (100%) rename .github/{actions => workflows}/verilog-linter.yml (100%) diff --git a/.github/actions/verilog-compiler.yml b/.github/workflows/verilog-compiler.yml similarity index 100% rename from .github/actions/verilog-compiler.yml rename to .github/workflows/verilog-compiler.yml diff --git a/.github/actions/verilog-linter.yml b/.github/workflows/verilog-linter.yml similarity index 100% rename from .github/actions/verilog-linter.yml rename to .github/workflows/verilog-linter.yml From a88f9856ad33b219a63c8869542d80d4f2c3f7e1 Mon Sep 17 00:00:00 2001 From: jon011235 <148149771+jon011235@users.noreply.github.com> Date: Thu, 26 Oct 2023 10:55:57 +0200 Subject: [PATCH 3/5] Update verilog-linter.yml --- .github/workflows/verilog-linter.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/verilog-linter.yml b/.github/workflows/verilog-linter.yml index f33c7c1..b98156c 100644 --- a/.github/workflows/verilog-linter.yml +++ b/.github/workflows/verilog-linter.yml @@ -6,7 +6,7 @@ jobs: steps: - uses: actions/checkout@v2 # Checkout source - uses: reviewdog/action-setup@v1 # Setup reviewdog - - uses: SuibianP/verilog-cleaner@v1 # lint and format + - uses: SuibianP/verilog-cleaner@v0.1.1 # lint and format with: github_token: ${{ secrets.GITHUB_TOKEN }} - uses: peter-evans/create-pull-request@v3 # Creates pull request with formatting results From c4bbafe3707f59ad807c80c8e3e2fb9bde40b429 Mon Sep 17 00:00:00 2001 From: jon011235 <148149771+jon011235@users.noreply.github.com> Date: Thu, 26 Oct 2023 11:13:31 +0200 Subject: [PATCH 4/5] Add actually working linter --- .github/workflows/verilog-linter.yml | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/.github/workflows/verilog-linter.yml b/.github/workflows/verilog-linter.yml index b98156c..9787ef8 100644 --- a/.github/workflows/verilog-linter.yml +++ b/.github/workflows/verilog-linter.yml @@ -1,14 +1,11 @@ -on: [pull_request] - +name: Verible linter example +on: + pull_request: jobs: - clean-verilog: + lint: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v2 # Checkout source - - uses: reviewdog/action-setup@v1 # Setup reviewdog - - uses: SuibianP/verilog-cleaner@v0.1.1 # lint and format + - uses: actions/checkout@master + - uses: chipsalliance/verible-linter-action@main with: github_token: ${{ secrets.GITHUB_TOKEN }} - - uses: peter-evans/create-pull-request@v3 # Creates pull request with formatting results - with: - delete-branch: true From 1f9a2e19077b3edd726b91be648500ef2f2090b3 Mon Sep 17 00:00:00 2001 From: jon011235 <148149771+jon011235@users.noreply.github.com> Date: Thu, 26 Oct 2023 09:23:18 +0000 Subject: [PATCH 5/5] Finishing workflows for now --- .github/workflows/verilog-compiler.yml | 27 -------------------------- .github/workflows/verilog-linter.yml | 2 ++ 2 files changed, 2 insertions(+), 27 deletions(-) delete mode 100644 .github/workflows/verilog-compiler.yml diff --git a/.github/workflows/verilog-compiler.yml b/.github/workflows/verilog-compiler.yml deleted file mode 100644 index 550eed3..0000000 --- a/.github/workflows/verilog-compiler.yml +++ /dev/null @@ -1,27 +0,0 @@ -name: "Verilog Build and Analysis" - -on: - [pull_request] - -jobs: - build-and-analyze: - runs-on: ubuntu-latest - - steps: - - name: Verilog Compiler - uses: jge162/verilog_compiler@1.0.0 - - - run: | - echo "Install required dependencies" - sudo apt-get update - sudo apt-get install iverilog - sudo apt-get install verilator - - - run: | - echo "Set executable permission on script file" - chmod --recursive +x /* - - - run: | - echo "Run, Build Application using script" - VERILOG_FILES=find . -type f -name "*.v" -print0 | xargs -0 echo -n - iverilog -o test_project $VERILOG_FILES diff --git a/.github/workflows/verilog-linter.yml b/.github/workflows/verilog-linter.yml index 9787ef8..791ce56 100644 --- a/.github/workflows/verilog-linter.yml +++ b/.github/workflows/verilog-linter.yml @@ -9,3 +9,5 @@ jobs: - uses: chipsalliance/verible-linter-action@main with: github_token: ${{ secrets.GITHUB_TOKEN }} + +# For the future simulating and compiling in modelsim would be great https://purisa.me/blog/testing-hdl-on-github/ \ No newline at end of file