Use TSC_DEADLINE for single-stepping

[jovanbulck]

Now that x2apic is supported (#72) and libsgxstep has privileged IRQ gates for rdmsr/wrmsr, we should consider using the finer-grained IA32_TSC_DEADLINE MSR for scheduling single-stepping timer interrupts.

The underlying APIC may still use the slower bus frequency to trigger the interrupt, but at least it may be more natural to express the interval in TSC cycles instead of external bus cycles.

Would prob be best to also finally implement this together with #2 .