diff --git a/doc/docs/tutorial/custom_fifo.md b/doc/docs/tutorial/custom_fifo.md
index f730d9f..2431638 100644
--- a/doc/docs/tutorial/custom_fifo.md
+++ b/doc/docs/tutorial/custom_fifo.md
@@ -131,6 +131,16 @@ fn custom_fifo(ingress: [Vr<u32>; 5]) -> Vr<u32> {
 
 You can find the full implementation in [custom_fifo.rs](https://github.com/kaist-cp/hazardflow/blob/main/hazardflow-designs/src/examples/custom_fifo.rs).
 
+You can generate the Verilog codes with the following commands:
+
+```bash
+# Generate a separate Verilog file for each submodule.
+$ cargo run --release -- --target custom_fifo --deadcode --wire-cache
+
+# Generate an integrated Verilog file combining all submodules.
+$ cargo run --release -- --target custom_fifo --deadcode --wire-cache --merge
+```
+
 ---
 
 Congratulations! You finished the tutorial!
diff --git a/doc/docs/tutorial/fir_filter.md b/doc/docs/tutorial/fir_filter.md
index 3470069..068cf17 100644
--- a/doc/docs/tutorial/fir_filter.md
+++ b/doc/docs/tutorial/fir_filter.md
@@ -147,3 +147,13 @@ It transforms the ingress payload to sum of them.
 In the application-specific logic in `map` interface combinator, we use `fold` method which aggregates the data within array of signal.
 
 You can find the implementation in [fir_filter.rs](https://github.com/kaist-cp/hazardflow/blob/main/hazardflow-designs/src/examples/fir_filter.rs).
+
+You can generate the Verilog codes with the following commands:
+
+```bash
+# Generate a separate Verilog file for each submodule.
+$ cargo run --release -- --target fir_filter --deadcode --wire-cache
+
+# Generate an integrated Verilog file combining all submodules.
+$ cargo run --release -- --target fir_filter --deadcode --wire-cache --merge
+```