From 257fc021bc6852f70907e8b81878a399bb73f329 Mon Sep 17 00:00:00 2001
From: Minseong Jang <minseong.jang@kaist.ac.kr>
Date: Mon, 2 Sep 2024 11:04:55 +0900
Subject: [PATCH] Update FIR fiter scripts organization

---
 scripts/fir_filter/Makefile | 10 ++++++----
 scripts/fir_filter/dump.v   |  8 ++++++++
 scripts/fir_filter/fir.v    |  5 -----
 3 files changed, 14 insertions(+), 9 deletions(-)
 create mode 100644 scripts/fir_filter/dump.v

diff --git a/scripts/fir_filter/Makefile b/scripts/fir_filter/Makefile
index 8fcbcc6..d3778cc 100644
--- a/scripts/fir_filter/Makefile
+++ b/scripts/fir_filter/Makefile
@@ -1,10 +1,12 @@
 # Makefile
 
-# defaults
-SIM ?= icarus
-TOPLEVEL_LANG ?= verilog
+TOPLEVEL_LANG = verilog
+SIM = icarus
 
 VERILOG_SOURCES += $(PWD)/fir.v
+VERILOG_SOURCES += $(PWD)/dump.v
+
+COMPILE_ARGS += -s dump
 
 # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
 TOPLEVEL = fir
@@ -16,5 +18,5 @@ MODULE = test_fir
 include $(shell cocotb-config --makefiles)/Makefile.sim
 
 clean::
-	@rm -rf iverilog_dump.v
+	@rm -rf results.xml
 	@rm -rf $(TOPLEVEL).vcd
diff --git a/scripts/fir_filter/dump.v b/scripts/fir_filter/dump.v
new file mode 100644
index 0000000..7f4de35
--- /dev/null
+++ b/scripts/fir_filter/dump.v
@@ -0,0 +1,8 @@
+module dump();
+
+initial begin
+    $dumpfile("fir.vcd");
+    $dumpvars(0, fir);
+end
+
+endmodule
diff --git a/scripts/fir_filter/fir.v b/scripts/fir_filter/fir.v
index 4443abd..ddd3166 100644
--- a/scripts/fir_filter/fir.v
+++ b/scripts/fir_filter/fir.v
@@ -11,9 +11,4 @@ module fir (
 
 // TODO: Implement this module.
 
-initial begin
-    $dumpfile("fir.vcd");
-    $dumpvars(0, fir);
-end
-
 endmodule