diff --git a/doc/book.toml b/doc/book.toml index 21e2982..539f307 100644 --- a/doc/book.toml +++ b/doc/book.toml @@ -3,3 +3,6 @@ title = "HazardFlow HDL" language = "en" multilingual = false src = "docs" + +[output.html] +mathjax-support = true diff --git a/doc/docs/advanced/dependency.md b/doc/docs/advanced/dependency.md index 9c0909c..397f41c 100644 --- a/doc/docs/advanced/dependency.md +++ b/doc/docs/advanced/dependency.md @@ -16,7 +16,7 @@ It is defined as variants of an enum `Dep`: ```rust,noplayground /// Dependency type of a hazard interface. #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, ConstParamTy)] -pub enum Dep { +enum Dep { /// The payload (`Fwd`) does not depend on the resolver (`Bwd`). Helpful = 0, @@ -33,7 +33,7 @@ We annotate the dependency type to the hazard interface. ```rust,noplayground /// Hazard interface. #[derive(Debug)] -pub struct I; +struct I; ``` The benefit of using dependency type is that it is useful to guarantee the transfer happens or not in the interface. diff --git a/doc/docs/examples/cpu/implementation.md b/doc/docs/examples/cpu/implementation.md index 0129da2..f5c252f 100644 --- a/doc/docs/examples/cpu/implementation.md +++ b/doc/docs/examples/cpu/implementation.md @@ -27,65 +27,3 @@ fn core( - We chain the 5 sub-modules `fetch`, `decode`, `exe`, `mem`, and `wb` by using the `comb` method. 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file mode 100644 index d5e06c7..0000000 --- a/doc/docs/formulas/fir/y.svg +++ /dev/null @@ -1,2 +0,0 @@ - - \ No newline at end of file diff --git a/doc/docs/lang/combinator.md b/doc/docs/lang/combinator.md index aa8581d..ec8e9bc 100644 --- a/doc/docs/lang/combinator.md +++ b/doc/docs/lang/combinator.md @@ -6,6 +6,39 @@ The combinator specifies the combinational logic of calculating the egress inter Note that in this section, you will see the dependency type `D` in the combinators' signature, for more information about the dependency, please refer to the [dependency section](../advanced/dependency.md). +## Combine Blackbox Module to Interface + +The `comb` method within the interface trait is used to combine the blackbox module to the given interface and return the egress interface. + +```rust,noplayground +trait Interface { + .. + + fn comb(self, m: impl FnOnce(Self) -> E) -> E { + m(self) + } +} +``` + +It is useful when we want to combine multiple modules together. +For example, we can combine multiple stage modules with `comb` in the CPU core. + +```rust,noplayground +fn core( + imem: impl FnOnce(Vr) -> Vr, + dmem: impl FnOnce(Vr) -> Vr, +) { + fetch::(imem) + .comb(decode) + .comb(exe) + .comb(move |ingress| mem(ingress, dmem)) + .comb(wb) +} +``` + +- `imem` and `dmem` are modules for instruction memory and data memory, respectively. +- We chain the 5 sub-modules `fetch`, `decode`, `exe`, `mem`, and `wb` by using the `comb` method. + ## Generic FSM Combinator The essence of the interface combinator is the generic `fsm` combinator. @@ -22,7 +55,7 @@ We provide the `fsm` combinator that transforms the ingress interface to egress With this combinator, you can represent an arbitrary FSM. ```rust,noplayground -pub trait Interface: Sized { +trait Interface { type Fwd: Copy; type Bwd: Copy; @@ -275,7 +308,7 @@ These combinators can either duplicate a single ingress interface into multiple We demonstrate the two most representative combinators: `lfork` and `branch`. -#### lfork +#### `lfork` This combinator delivers the ingress payload to all the egress interfaces' egress payload when all the egress interfaces are ready to receive the ingress payload, and also combines all the egress interfaces' resolvers to the ingress resolver. We demonstrate `lfork` with the ingress interface `Vr`, whose resolver is `()`. @@ -362,7 +395,7 @@ The example cycle-level behavior of `lfork` is as follows: - Cycle 1, 4, 5: transfer happens at ingress, first egress, and second egress sides. -#### branch +#### `branch` This combinator splits a single ingress interface into multiple egress interfaces and only selects one of the egress interfaces to transfer the payload, also combines all the egress interfaces' resolvers into the ingress resolver. We demonstrate `branch` with the ingress interface `Vr>`. @@ -468,7 +501,7 @@ The egress interface could contain all the ingress interfaces' payload and resol We demonstrate the two most representative combinators: `join` and `merge`. -#### join +#### `join` This combinator merges the ingress interfaces' payload and resolver. We demonstrate this combinator with the ingress interfaces `(Vr, Vr)`. @@ -555,7 +588,7 @@ The example cycle-level behavior of `join` is as follows: - Cycle 1, 4, 5: transfer happens. -#### merge +#### `merge` This combinator will select one from the ingress interfaces to deliver the ingress payload to the egress payload and also leave the inner of the egress resolver untouched to the ingress interfaces. We will demonstrate the `cmerge` combinator with 2 ingress interfaces `[Vr, Vr]`. @@ -654,7 +687,7 @@ Similar to other combinators, register style combinators have other variants too #### `reg_fwd` -We can use `reg_fwd` to reduce the clock cycle times. +We can use `reg_fwd` to make a pipeline, and reduce the critical path. Let's assume we have a circuit with ingress interface `Vr

`: @@ -662,14 +695,14 @@ Let's assume we have a circuit with ingress interface `Vr

`:

-Transforming from ingress payload from `P` to `EP2` needs to happen within one clock cycle, the total clock cycle times is the `Sum(lat(f1) + lat(f2))`. -If we add a `reg_fwd` combinator between those two `map` combinators. +Transforming from ingress payload from `P` to `EP2` needs to happen within a cycle, the critical path becomes `cpath(f1) + cpath(f2)`. +To resolve this, we add a `reg_fwd` combinator between those two `map` combinators.

-The total clock times is reduced to `Max(lat(f1), lat(f2))`. +Then the critical path is reduced to `max(cpath(f1), cpath(f2))`.

@@ -677,16 +710,12 @@ The total clock times is reduced to `Max(lat(f1), lat(f2))`. ```rust,noplayground impl Vr

{ - fn reg_fwd(self, pipe: bool) -> Vr

{ + fn reg_fwd(self) -> Vr

{ self.fsm::, HOption

>(None, |ip, er, s| { let ep = s; let et = ep.is_some_and(|p| er.ready); - let ir = if pipe { - Ready::new(s.is_none() || et, (er.inner, s)) - } else { - Ready::new(s.is_none(), (er.inner, s)) - }; + let ir = Ready::new(s.is_none() || et, (er.inner, s)); let it = ip.is_some_and(|p| ir.ready); let s_next = if it { @@ -703,7 +732,6 @@ impl Vr

{ } ``` -This combinator could be a pipeline when the `pipe` parameter is `true`. * The current state is the valid egress payload. * The ingress interface is ready to receive a valid payload whenever the current register is empty or the egress transfer happens. * If the ingress transfer happens, then the register stores the new valid payload as the next state. @@ -711,7 +739,7 @@ This combinator could be a pipeline when the `pipe` parameter is `true`. * If neither ingress transfer nor egress transfer happens, then the next state stays the same as the current state. * The only difference between `pipe` is `true` or `false` is the ingress transfer happens only when the current register is empty, delaying one cycle compared to the pipeline. -Let's assume the ingress interface type is `Vr` and we turn on the `pipe`. +Let's assume the ingress interface type is `Vr`. The example cycle-level behavior of `reg_fwd` is as follows: @@ -756,7 +784,7 @@ The example cycle-level behavior of `reg_fwd` is as follows: } --> -#### fifo +#### `fifo` This combinator is a pipelined FIFO queue, it can accept a new element every cycle if the queue is not full. @@ -843,7 +871,7 @@ These combinators have only either ingress interface or egress interface. We demonstrate the two most representative combinators: `source` and `sink`. -#### source +#### `source` This combinator immediately returns the data to the payload when the data is coming from resolver. The `source` combinator only has the egress interface. @@ -899,7 +927,7 @@ When `P` is `u32`, the example cycle-level behavior of `source` is as follows: - Cycle 0, 1, 2, 4, 5: Egress transfer happens. - Cycle 3: Egress transfer does not happen because egress ready signal is `false`. -#### sink +#### `sink` This combinator maintains a state and calculates the ingress resolver with `f`, which takes the current state and ingress payload as inputs. The `sink` combinator only has the ingress interface. @@ -1109,11 +1137,11 @@ It outputs 3 consecutive numbers starting from each input number. ```rust,noplayground fn consecutive_3(input: Vr) -> Vr { - input.fsm_egress(0, true, |p, add| { - let ep = p + add; - let add_next = add + 1; - let is_last = add == 2; - (ep, add_next, is_last) + input.fsm_egress(0, true, |p, count| { + let ep = p + count; + let count_next = count + 1; + let is_last = count == 2; + (ep, count_next, is_last) }) } ``` @@ -1180,6 +1208,8 @@ The example cycle-level behavior of `fsm_egress` is as follows: * At T3, the FSM state is reset and a new FSM is started. * From T3 to T5, the FSM is running with the saved payload `Some(1)`, and it outputs `1`, `2`, `3`. + diff --git a/doc/docs/lang/concepts.md b/doc/docs/lang/concepts.md index f25cc39..977e79f 100644 --- a/doc/docs/lang/concepts.md +++ b/doc/docs/lang/concepts.md @@ -1,6 +1,6 @@ # Concepts - [Signal](./signal.md): The data types that can be transferred through wires. -- [Interface](./interface.md): A data structure contains forward signal, backward signal and its transfer condition. -- [Combinators](./combinator.md): The mechanism of chaining two interfaces together. -- [Modules](./module.md): A collection of combinators work together and perform a distinct task, serving as the building block for a digital circuit. +- [Interface](./interface.md): Communication protocol between modules. It contains forward signal, backward signal and its transfer condition. +- [Modules](./module.md): Hardware module. It serves as the building block for a digital circuit. +- [Interface Combinators](./combinator.md): The mechanism of chaining two interfaces together. diff --git a/doc/docs/lang/interface.md b/doc/docs/lang/interface.md index eaa0a60..39f364a 100644 --- a/doc/docs/lang/interface.md +++ b/doc/docs/lang/interface.md @@ -56,7 +56,7 @@ In HazardFlow HDL, we abstracted any arbitraty communication protocol into `Haza It describes the necessary information for communication: payload, resolver, and ready function. ```rust,noplayground -pub trait Hazard { +trait Hazard { type P: Copy; type R: Copy; @@ -145,11 +145,6 @@ type VrH = AndH>; For reusability, we added additional resolver signals that simply flow from the receiver to the sender. - - ## Interface An interface is an abstraction that represents the IO of a hardware module. @@ -159,7 +154,7 @@ Typically, a single interface is composed of zero, one, or multiple hazard inter ### Specification ```rust,noplayground -pub trait Interface { +trait Interface { type Fwd: Copy; type Bwd: Copy; @@ -188,7 +183,7 @@ For an arbitraty hazard specification `H`, we define the hazard interface `I`, where `H` is the hazard, and `D` is the dependency type of hazard protocol. For more information of the dependency, please refer to the [dependency section](../advanced/dependency.md). --> ```rust,noplayground -pub struct I; +struct I; impl Interface for I { type Fwd = HOption, diff --git a/doc/docs/lang/module.md b/doc/docs/lang/module.md index c513cf0..dd921ba 100644 --- a/doc/docs/lang/module.md +++ b/doc/docs/lang/module.md @@ -2,47 +2,37 @@ -We consider a module as a function takes the ingress interface and returns the egress interface. +In Rust, the [`FnOnce` trait](https://doc.rust-lang.org/stable/std/ops/trait.FnOnce.html) is automatically implemented for types that can be called once. For example, the primitive function `fn(i: Ingress) -> Egress` and closures that might consume captured variables (`|i: Ingress| -> Egress { .. }`) implements `FnOnce(Ingress) -> Egress` trait. -```rust,noplayground -m: impl FnOnce(I) -> E -``` +And in HazardFlow, we treat a function `m` that implements the `FnOnce(Ingress) -> Egress` trait where `Ingress` and `Egress` implement the [`Interface` trait](interface.html#interface-1) as a module with `Ingress` as its ingress interface and `Egress` as its egress interface. -We can construct a module as a class of interface combinators. Please refer to the [Interface Combinators](./combinator.md) for more information. +

+ +

-## Combine Blackbox Module to Interface +The common way to construct a module is chaining interface combinators. +Please refer to the [Interface Combinators](./combinator.md) for more information. -The `comb` method within the interface trait is used to combine the blackbox module to the given interface and return the egress interface. -```rust,noplayground -fn comb(self, m: impl FnOnce(Self) -> E) -> E { - m(self) -} -``` +### Example: FIR Filter + +In the [tutorial](../tutorial/fir_filter.html#implementation), the FIR filter module was implemented as follows: -- Applying the given interface to the module is essentially applying the module function `m` to the ingress interface. -- It is useful when we want to combine multiple modules together. - -For example, we can combine multiple stage modules with `comb` in the CPU core. - -```rust,noplayground -pub fn core( - imem: impl FnOnce(Vr) -> Vr, - dmem: impl FnOnce(Vr) -> Vr, -) { - fetch::(imem) - .comb(decode) - .comb(exe) - .comb(move |ingress| mem(ingress, dmem)) - .comb(wb) +```rust +fn fir_filter(input: Valid) -> Valid { + let weight = Array::::from([4, 2, 3]); + + input + .window::<3>() + .map(|ip| ip.zip(weight).map(|(e, wt)| e * wt)) + .sum() } ``` -- `imem` and `dmem` are modules for instruction memory and data memory, respectively. -- We chain the 5 sub-modules `fetch`, `decode`, `exe`, `mem`, and `wb` by using the `comb` method. +The `fir_filter` function implements `FnOnce(Valid) -> Valid`, so we can treat it as a module with `Valid` as both its ingress and egress interface. ## Module Combinators -We provide some handy module combinators that manipulates modules. +We provide some convenient module combinators that take a module, modify it, and return a new module. ### `seq` @@ -61,37 +51,9 @@ You can construct an array of modules explicitly from elements, or if all the mo Flips a module's input and output. ```rust -pub fn flip( +fn flip( f: T ) -> impl FnOnce(I2, I1) -> (O2, O1) where T: FnOnce(I1, I2) -> (O1, O2), ``` - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/doc/docs/lang/signal.md b/doc/docs/lang/signal.md index be5abf8..2a7abca 100644 --- a/doc/docs/lang/signal.md +++ b/doc/docs/lang/signal.md @@ -1,14 +1,22 @@ # Signal Signal is a collection of types that can be transferred through wires in HazardFlow HDL. We divide these types into two categories: **scalar** and **compound**. -The HazardFlow HDL reuse some data types from the Rust programming language. Normally we can consider a data type implements `Copy` in Rust as a signal type in the HazardFlow HDL. +The HazardFlow HDL reuse some data types from the Rust programming language. +Normally we can consider a data type implements [`Copy` trait in Rust](https://doc.rust-lang.org/std/marker/trait.Copy.html) as a signal type in the HazardFlow HDL. -For more information of the Rust data types, you can reference to [The Rust Programming Language Book](https://doc.rust-lang.org/beta/book/ch03-02-data-types.html). +> The `Copy` trait in Rust and the signal type in HazardFlow are not in a perfect 1:1 relationship. +While the signal type in HazardFlow must implement Rust's `Copy` trait, there are some types like function pointers (e.g., `fn() -> i32`) that implement the `Copy` trait but are not treated as signal types in HazardFlow. + +For more information of the Rust data types, please refer to [The Rust Programming Language Book](https://doc.rust-lang.org/beta/book/ch03-02-data-types.html). ## Scalar Types A scalar type represents a single value. +### Boolean + +We interpret the Boolean type the same as the `bool` type in the Rust programming language. In HazardFlow HDL, we also interpret the Boolean value as `0` or `1` and can be sent through the wires when the value is `True` or `False`. + ### Unsigned Integer In the HazardFlow HDL, we support arbitrary bit-width unsigned integers. We define it as `U`, where `N` is the bit-width. We provide a handful of primitive functions for supporting unsigned integers' arithmetic operations, type conversion, and also ordering between different unsigned integers. @@ -21,10 +29,6 @@ In the HazardFlow HDL, we support arbitrary bit-width unsigned integers. We defi * Ordering * We provide ordering functions for developers to easily compare two unsigned integers. -### Boolean - -We interpret the Boolean type the same as the `bool` type in the Rust programming language. In HazardFlow HDL, we also interpret the Boolean value as `0` or `1` and can be sent through the wires when the value is `True` or `False`. - ## Compound Types Compound types can group multiple values into one type. @@ -39,7 +43,7 @@ Similar to the `Option` type in Rust, the `HOption` type in HazardFlow HDL is al ```rust,noplayground #[derive(Debug, Clone, Copy, HEq)] -pub enum HOption { +enum HOption { /// No value. None, /// Some value of type `T`. @@ -79,7 +83,7 @@ The `Array` type is primitive in the HazardFlow HDL. We can define an `N` size s In HazardFlow HDL, we represent unsigned integer as an `Array` of `bool` with bit-width `N`. When `bool` is `true`, we interpret it as a bit with value `1`, `false` as `0`. ```rust,noplayground -pub type U = Array; +type U = Array; ``` diff --git a/doc/docs/tutorial/custom_fifo.md b/doc/docs/tutorial/custom_fifo.md index 88c4de0..5f35630 100644 --- a/doc/docs/tutorial/custom_fifo.md +++ b/doc/docs/tutorial/custom_fifo.md @@ -109,13 +109,12 @@ Based on the above submodules, we can implement the custom FIFO in a concise and fn custom_fifo(ingress: [Vr; N]) -> Vr { ingress .masked_merge() - .map_resolver::<((), FifoS<(u32, U<{ clog2(N) }>), M>)>(|er| { - let (_, fifo_s) = er.inner; - range::().fold(Array::from([false; N]), |acc, i| { - if i.resize() >= fifo_s.len { - acc + .map_resolver_inner::<((), FifoS<(u32, U<{ clog2(N) }>), M>)>(|(_, fifo_s)| { + fifo_s.inner_with_valid().fold(false.repeat::(), |acc, i| { + if let Some((_, idx)) = i { + acc.set(idx, true) } else { - acc.set(fifo_s.inner[wrapping_add(fifo_s.raddr, i, M.into_u())].1, true) + acc } }) }) @@ -125,12 +124,13 @@ fn custom_fifo(ingress: [Vr; N]) -> Vr { ``` - We used `u32` for the payload type, `N` for the number of ingress interfaces and `M` for the FIFO size. -- `fifo_s.inner` represents the inner elements of the FIFO. -- We `fold` the inner elements of the FIFO in the `map_resolver` combinator: - - The initializer is a boolean array with all elements as `false` of size `N` - - The index of the initializer array indicates the index of the ingress interfaces. - - We iterate through all the elements within the FIFO and set the accumulator's value at the index in each FIFO element to `true`. - - The final result indicates which ingress interfaces are present in the current FIFO. +- `fifo_s.inner_with_valid()` represents the inner elements of the FIFO. + + It has type `Array, M>`, `HOption` represents the validity of the element. +- We `fold` the inner elements of the FIFO in the `map_resolver_inner` combinator: + + The initializer is a boolean array with all elements as `false` of size `N` + + The index of the initializer array indicates the index of the ingress interfaces. + + We iterate through all the elements within the FIFO and set the accumulator's value at the index in each FIFO element to `true`. + + The final result indicates which ingress interfaces are present in the current FIFO. - We send back this resolver to the `masked_merge` combinator to make decision for choosing the next ingress interface. - We filter out the unnecessary index information in the last `map` combinator. - The implementation of the `masked_merge()` combinator will be explained in the [Implementing Combinators](../advanced/combinator.md) section. diff --git a/doc/docs/tutorial/fir_filter.md b/doc/docs/tutorial/fir_filter.md index 54961c1..0bfe17f 100644 --- a/doc/docs/tutorial/fir_filter.md +++ b/doc/docs/tutorial/fir_filter.md @@ -11,9 +11,9 @@ The FIR filter of order *N* performs the following operation: It receives input signals from the stream *x* and outputs the weighted sum of the most recent *N+1* input signals to the stream *y*. It can be expressed with the following formula: -
+\\[ y[n] = b_0 x[n] + b_1 x[n-1] + ... + b_N x[n-N] = \sum^{N}_{i=0} b_i x[n-i] \\] -where and represent the input and output signals, represents the filter order, and represents the *i*-th filter coefficient. +where \\( x[n] \\) and \\( y[n] \\) represent the input and output signals, \\( N \\) represents the filter order, and \\( b_i \\) represents the *i*-th filter coefficient. For example, the IO signals of a FIR filter of order 2 with coefficients [4, 2, 3] are as follows: @@ -58,9 +58,11 @@ Based on the above submodules, we can implement the FIR filter in a concise and ```rust,noplayground fn fir_filter(input: Valid) -> Valid { + let weight = Array::::from([4, 2, 3]); + input .window::<3>() - .map(|ip| ip.zip(Array::from([4, 2, 3])).map(|(e, wt)| e * wt)) + .map(|ip| ip.zip(weight).map(|(e, wt)| e * wt)) .sum() } ``` @@ -112,7 +114,7 @@ The anonymous function is where we specify the fsm logic from the `(ingress payl The `map` combinator is used to represent the `weight` submodule. ```rust,noplayground -map(|ip| ip.zip(Array::from([4, 2, 3])).map(|(e, wt)| e * wt)) +map(|ip| ip.zip(weight).map(|(e, wt)| e * wt)) ``` It takes an `Valid>` and returns an egress hazard interface `Valid>`. diff --git a/hazardflow-designs/src/examples/custom_fifo.rs b/hazardflow-designs/src/examples/custom_fifo.rs index 4c7add4..601c0fc 100644 --- a/hazardflow-designs/src/examples/custom_fifo.rs +++ b/hazardflow-designs/src/examples/custom_fifo.rs @@ -46,13 +46,12 @@ where [(); clog2(N)]: pub fn custom_fifo(ingress: [Vr; N]) -> Vr { ingress .masked_merge() - .map_resolver::<((), FifoS<(u32, U<{ clog2(N) }>), M>)>(|er| { - let (_, fifo_s) = er.inner; - range::().fold(Array::from([false; N]), |acc, i| { - if i.resize() >= fifo_s.len { - acc + .map_resolver_inner::<((), FifoS<(u32, U<{ clog2(N) }>), M>)>(|(_, fifo_s)| { + fifo_s.inner_with_valid().fold(false.repeat::(), |acc, i| { + if let Some((_, idx)) = i { + acc.set(idx, true) } else { - acc.set(fifo_s.inner[wrapping_add(fifo_s.raddr, i, M.into_u())].1, true) + acc } }) }) diff --git a/hazardflow-designs/src/examples/fir_filter.rs b/hazardflow-designs/src/examples/fir_filter.rs index 11bd8fe..717eee2 100644 --- a/hazardflow-designs/src/examples/fir_filter.rs +++ b/hazardflow-designs/src/examples/fir_filter.rs @@ -32,5 +32,7 @@ impl Valid> { /// FIR filter implementation #[synthesize] pub fn fir_filter(input: Valid) -> Valid { - input.window::<3>().map(|ip| ip.zip(Array::from([4, 2, 3])).map(|(e, wt)| e * wt)).sum() + let weight = Array::::from([4, 2, 3]); + + input.window::<3>().map(|ip| ip.zip(weight).map(|(e, wt)| e * wt)).sum() } diff --git a/hazardflow-designs/src/std/combinators/fifo.rs b/hazardflow-designs/src/std/combinators/fifo.rs index f773355..29533cc 100644 --- a/hazardflow-designs/src/std/combinators/fifo.rs +++ b/hazardflow-designs/src/std/combinators/fifo.rs @@ -29,6 +29,24 @@ where } } +impl FifoS +where + [(); clog2(N)]:, + [(); clog2(N + 1)]:, + [(); clog2(N) + 1]:, +{ + /// Returns inner elements with valid bit. + pub fn inner_with_valid(self) -> Array, N> { + range::().map(|i| { + if i.resize() >= self.len { + None + } else { + Some(self.inner[wrapping_add::<{ clog2(N) }>(self.raddr, i, N.into_u())]) + } + }) + } +} + impl I, D> { /// FIFO queue with `N` entries. /// diff --git a/hazardflow/src/compiler/prelude.rs b/hazardflow/src/compiler/prelude.rs index 5a95d5f..479fca4 100644 --- a/hazardflow/src/compiler/prelude.rs +++ b/hazardflow/src/compiler/prelude.rs @@ -308,16 +308,22 @@ impl PortDecls { match ty.kind() { TyKind::Bool => Some(Self::unsigned_bits(1)), TyKind::Int(int_ty) => { - let width: usize = int_ty.bit_width().expect("isize is not supported").try_into().unwrap(); + let width: usize = int_ty + .bit_width() + .expect("`isize` cannot be used as a signal type. Specify the bitwidth explicitly, such as `i32` or `i64`.") + .try_into() + .unwrap(); + Some(Self::signed_bits(width)) } TyKind::Uint(uint_ty) => { - let width: usize = uint_ty + let width = uint_ty .bit_width() - // NOTE: This fails when type is `usize`, and falls back to 32 bits .unwrap_or(32) + // .expect("`usize` cannot be used as a signal type. Specify the bitwidth explicitly, such as `u32` or `u64`.") .try_into() .unwrap(); + Some(Self::unsigned_bits(width)) } TyKind::Adt(def, substs) => AdtLayout::new(tcx, def, substs).port_decls().into(),