From be940a35ff7fbef46c2358d9bafa275a2849468e Mon Sep 17 00:00:00 2001
From: Minseong Jang <minseong.jang@kaist.ac.kr>
Date: Wed, 20 Nov 2024 05:36:54 +0000
Subject: [PATCH] Define `ACC_BITS` in configs

---
 hazardflow-designs/src/gemmini/configs.rs                   | 2 ++
 hazardflow-designs/src/gemmini/execute/systolic_array/pe.rs | 3 ---
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/hazardflow-designs/src/gemmini/configs.rs b/hazardflow-designs/src/gemmini/configs.rs
index 236104d..c2497dd 100644
--- a/hazardflow-designs/src/gemmini/configs.rs
+++ b/hazardflow-designs/src/gemmini/configs.rs
@@ -86,5 +86,7 @@ pub const CL_RS_MAX_PER_TYPE: usize = clog2(RS_MAX_PER_TYPE);
 
 /// Bit width of inputType.
 pub const INPUT_BITS: usize = 8;
+/// Bit width of the PE register type.
+pub const ACC_BITS: usize = 32;
 /// Bit width of outputType.
 pub const OUTPUT_BITS: usize = 20;
diff --git a/hazardflow-designs/src/gemmini/execute/systolic_array/pe.rs b/hazardflow-designs/src/gemmini/execute/systolic_array/pe.rs
index fafd8a6..7440975 100644
--- a/hazardflow-designs/src/gemmini/execute/systolic_array/pe.rs
+++ b/hazardflow-designs/src/gemmini/execute/systolic_array/pe.rs
@@ -4,9 +4,6 @@
 
 use super::*;
 
-/// Bit width of the register type.
-pub const ACC_BITS: usize = 32;
-
 /// PE row data signals.
 #[derive(Debug, Clone, Copy)]
 pub struct PeRowData {