From ec4ecdd7827d9aba911d22e06f054a9c9a9f337d Mon Sep 17 00:00:00 2001 From: Minseong Jang Date: Tue, 8 Oct 2024 15:40:52 +0900 Subject: [PATCH] Update FIFO implementation --- doc/docs/lang/combinator.md | 8 ++++---- hazardflow-designs/src/std/combinators/fifo.rs | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/doc/docs/lang/combinator.md b/doc/docs/lang/combinator.md index 063d7b2..aa8581d 100644 --- a/doc/docs/lang/combinator.md +++ b/doc/docs/lang/combinator.md @@ -779,8 +779,8 @@ impl Vr

{ let ep = if s.len == 0.into_u() { None } else { Some(s.inner[s.raddr]) }; let ir = Ready::new(!full, ()); - let inner_next = if enq { inner.set(waddr.resize::<{ clog2(N) }>(), ip.unwrap()) } else { inner }; - let len_next = (len + U::from(enq).resize() - if deq { 1.into_u() } else { 0.into_u() }).resize(); + let inner_next = if enq { inner.set(waddr, ip.unwrap()) } else { inner }; + let len_next = (len + U::from(enq).resize() - U::from(deq).resize()).resize(); let raddr_next = if deq { wrapping_inc::<{ clog2(N) }>(raddr, N.into_u()) } else { raddr }; let waddr_next = if enq { wrapping_inc::<{ clog2(N) }>(waddr, N.into_u()) } else { waddr }; @@ -832,8 +832,8 @@ The example cycle-level behavior of `fifo` is as follows: } --> -- The ingress ready signal is true as long as the queue is not full. -- Pipeline is disabled for the FIFO queue. +- The ingress ready signal is `true` as long as the queue is not full. +- It does not give maximum throughput because both ingress transfer and egress transfer cannot happen simultaneously when the FIFO is full. - Cycle 0, 1, 2, 3, 6: Ingress transfer happens. - Cycle 1, 5, 6, 7: Egress transfer happens. diff --git a/hazardflow-designs/src/std/combinators/fifo.rs b/hazardflow-designs/src/std/combinators/fifo.rs index d2f7283..f773355 100644 --- a/hazardflow-designs/src/std/combinators/fifo.rs +++ b/hazardflow-designs/src/std/combinators/fifo.rs @@ -120,7 +120,7 @@ where let ep = Some(s); let ir = Ready::new(!full, (er.inner.0, s)); - let inner_next = if enq { inner.set(waddr.resize::<{ clog2(N) }>(), ip.unwrap()) } else { inner }; + let inner_next = if enq { inner.set(waddr, ip.unwrap()) } else { inner }; let len_next = (len + U::from(enq).resize() - if deq { pop.resize() } else { 0.into_u() }).resize(); let raddr_next = if deq { wrapping_add::<{ clog2(N) }>(raddr, pop.resize(), N.into_u()) } else { raddr };